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8259 STUDY CARD USER MANUAL - Electro Systems Associates

1. Symbol Pin No Name and Function VCC 28 1 Supply 5V Supply GND 14 1 Ground CS 1 1 Chip Select A low on this pin enables RD and WR communication Between the CPU and the 8259A INTA functions are independent of CS WR 2 0 Write A low on this pin when CS is low enables the 8259A to accept command words from the CPU RD 3 1 Read A low on this pin when CS is low enables the 8259A to release Status onto the data bus for the CPU D Do 4 11 Bi directional Data Bus Control status interrupt vector information is transferred via this bus CAS o CAS 12 13 Cascade Lines The CAS lines form a private 8259A bus to control a 15 multiple 8259A structure These pins are outputs for a master 8259A and inputs for a slave 8259A SP EN 16 Slave Program Enable Buffer This is a dual function pin When in the Buffered Mode it can be used as an output to control buffer transceivers EN When not in the buffered mode it is used as an input to designate a master SP 1 or slave SP 0 INT 17 O Interrupt This pin goes high whenever a valid interrupt request is asserted It is used to interrupt the CPU thus it is connected to CPU s OAD 8259A STUDY CARD USER MANUAL NULI interrupt pin IRo IR 18 25 1 Interrupt Requests Asynchronous inputs An interrupt request is executed by raising an IR input low to high and holding it high until it is acknowledged Ed
2. 71 8259 STUDY CARD USER MANUAL NULI 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 8259A STUDY CARD USER MANUAL Oa ELECTRO SYSTEMS ASSOCIATES LTD itle STUDY CARD ADAPTER 72 OAD JDO 8259A STUDY CARD USER MANUAL 73
3. LOOP A 95H 31H A 60H 30H LOOP 31 8271 8273 8275 8277 8279 827 827E 8280 8282 8284 8287 8289 828B 828D 828F 8292 8294 8296 8298 829A 829D 829F 82 1 82 82 5 82 8 82 82 82 82 0 82B3 82B5 82B8 EXAMPLE 3 3E D3 3E D3 c3 3E D3 3E D3 c3 3E D3 3E D3 c3 3E D3 3E D3 c3 3E D3 3E D3 c3 3E D3 3E D3 CD FE C2 EF 95 31 B5 30 BO 95 31 F4 30 BO 95 31 66 30 BO 95 31 D6 30 BO 95 31 D7 30 BO 95 31 70 30 BA 1C BO 82 82 82 82 82 03 82 S2 S3 S4 S5 S6 S7 LOOP MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT CALL CPI RST A 95H 31H A 0B5H 30H LOOP A 95H 31H A OF4H 30H LOOP 95 31H A 66H 30H LOOP A 95H 31H A OD6H 30H LOOP A 95H 31H A 0D7H 30H LOOP A 95H 31H A 70H 30H RDKBD Waiting for NEXT key 1CH LOOP 5 This Program configures 8259 to accept only Int1 using the interrupt mask command OCW1 Keep the dipswitch SW1 for IR1 interrupt Execute the program from 8000H Then press the push button switch OAD 8259A STUDY CARD USER MANUAL NULI 32 Execute the program SERIAL mode only 8000 8002 8004 8006 8008 800A 800C 800E 8010 8011 8014 8100 8103 8106 8107 8108 810B 810E 810F 8110 8113 8116 8117 8118 811B 811E 811F 8120 8123 8
4. OAH OOH 37 81 7 81 81 1 81 6 81 81 8201 8206 820 8210 49 53 45 54 00 49 53 45 54 00 52 20 52 45 52 20 52 45 36 49 52 44 37 49 52 44 20 4E 55 OD 20 4E 55 OD 49 54 50 0A 49 54 50 0A 56 DB IR6 IS INTERRUPTED ODH OAH OOH 57 DB IR7 IS INTERRUPTED 0ODH 0AH 00H 5 DEMONSTRATION PROGRAMS FOR ESA 85 2 TRAINER Connect the FRC between the connectors P1 of Trainer and P1 of Study Card Change the Jumper selection JP5 of the Trainer to 23 position before executing the following programs EXAMPLE 1 The following Program configures the 8259 to accept 8 interrupt requests The interrupts can be given from onboard switch or from external sources For onboard interrupts select the interrupt number using the dipswitch SW1 for corresponding interrupt Execute the program from 8000H Then press the push button switch to give the interrupt Execute the program in SERIAL mode only The displays the corresponding interrupt number on the console or on the serial monitor ADDRESSES OF STUDY CARD 8259 ARE 90H AND 91H 8000 8002 8004 8006 8008 800A 800c 800E 8010 8011 8014 8100 8103 8106 8107 8108 OAD 8259A STUDY CARD USER MANUAL QUO 46 40 5B 80 81 81 81 DISPM ORG START MVI OUT MVI OUT MVI OUT MVI OUT EI SSS JMP UP RST ORG LXI JMP NOP NOP LXI EQU 0B04H Display Routin
5. SSS EQU ORG MVI OUT MVI OUT MVI OUT MVI OUT EI JMP ORG CALL JMP NOP NOP CALL NOP NOP CALL JMP NOP NOP CALL NOP NOP CALL OAD 8259A STUDY CARD USER MANUAL QUO 03BAH 8000H A 12H 90H A 82H 91H A 00H 91H A 20H 90H SSS 8200H RO 50 RO 51 RO 52 RO 53 RO 54 Routine to read the keys on the hexpad single edge triggerd mode call address interval 8 interrupt vector address Normal EOI for 80 85 mode for 8259 Non specific EOI command Routine to Display int number on the Trainer 30 RO s5 RO 56 RO 57 90 A 60H Routine to display Intr 00 on seven segment display 8226 00 NOP 8227 00 NOP 8228 CD 3E 82 CALL 822B C3 92 82 JMP 822 00 822F 00 NOP 8230 CD 3E 82 CALL 8233 C3 9D 82 JMP 8236 00 NOP 8237 00 NOP 8238 CD 3E 82 CALL 823B C3 8 82 JMP 823E 3E 90 RO MVI 8240 D3 31 OUT 8242 3E 60 MVI 8244 D3 30 OUT 8246 3E 45 MVI 8248 D3 30 OUT 824A 3E 87 MVI 824C D3 30 OUT 824E 3E 05 MVI 8250 D3 30 OUT 8252 3E F3 MVI 8254 D3 30 OUT 8256 3E 00 MVI 8258 D3 30 OUT 825A C9 RET 825B 3E 95 S0 MVI 825D D3 31 OUT 825F 3E F3 MVI 8261 D3 30 OUT 8263 C3 BO 82 JMP 8266 3E 95 S1 MVI 8268 D3 31 OUT 826A 3E 60 MVI 826C D3 30 OUT 826E C3 0 82 JMP OAD JDE 8259A STUDY CARD USER MANUAL 30H A 45H 30H A 87H 30H 05 30H OOH 95 31H
6. OCCURRED OCCURRED OCCURRED OCCURRED OCCURRED OCCURRED OAH ODH OAH ODH OAH ODH OAH ODH OAH ODH OAH ODH OAH ODH OAH ODH 62 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 OAD 8259A STUDY CARD USER MANUAL NULI 217D 2183 2200 2201 2206 2209 2210 2211 2216 2219 2220 2221 2226 2229 2230 2231 2236 2239 2240 2241 2246 2249 2250 37 52 FA 2 9 2 9 2 9 2 9 2 9 20 45 8D F7 8D E7 8D D7 8D C7 8D B7 4F 44 16 00 16 00 16 00 16 00 16 00 43 0 00 11 22 33 44 43 OD 21 21 21 21 21 55 ORG CLI LEA INT ORG CLI LEA INT ORG CLI LEA INT ORG CLI LEA INT ORG CLI LEA INT ORG CLI 2200H DX MSGO DISP 03 2210H DX MSG1 DISP 03 2220H DX MSG2 DISP 03 2230H DX MSG3 DISP 03 2240H DX MSG4 DISP 03 2250H INTO ISR INT1 ISR INT2 ISR INT3 ISR INT4 ISR INT5 ISR 63 0000 2251 0000 2256 0000 2259 0000 2260 0000 2261 0000 2266 0000 2269 0000 2270 0000 2271 0000 2276 0000 2279 0000 2300 0000 2302 0000 2305 0000 230
7. JUMP INT7 ROUTINE 8210 02 00 03 LUMP 03H 8213 90 85 00 INTO MOV DPTR MSGO TO DISPLAY THE MESSAGE 8216 C2 D5 CLR PSW 5 INTO OCCURRED 8218 12 03 FA LCALL CALL ROUTINE TO DISPLAY THE MESSAGE 821B 74 60 MOV A 60H CLEAR THE INTERRUPT REQUEST WITH 821D F2 MOVX RO A SPECIFIC EOI COMMAND USING OCW2 821E 32 RETI RETURN FROM INTERRUPT 821F 90 85 13 INT1 MOV DPTR MSG1 8222 C2 D5 CLR PSW 5 8224 12 FA LCALL 8227 74 61 MOV A 61H 8229 F2 MOVX RO A 822A 32 RETI 822B 90 85 26 INT2 MOV DPTR MSG2 822E C2 D5 CLR Psw 5 8230 12 03 FA LCALL 0 8233 174 62 MOV A 62H 8235 F2 MOVX RO A 8236 32 RETI 8237 90 85 39 INT3 MOV DPTR MSG3 823A C2 D5 CLR PSW 5 66 OAD JDO 8259A STUDY CARD USER MANUAL 823 823F 8241 8242 8243 8246 8248 824B 824D 824E 824F 8252 8254 8257 8259 825A 825B 825E 8260 8263 8265 8266 8267 826A 826C 826F 8271 8272 8500 8505 OAD NULI 12 74 F2 32 90 C2 12 74 F2 32 90 C2 12 74 F2 90 C2 12 74 F2 32 90 C2 12 74 F2 32 20 54 03 FA 63 85 INT4 D5 03 FA 64 85 5 D5 03 FA 65 85 72 INT6 D5 03 FA 66 85 85 INT7 D5 03 FA 67 20 OA 49 4E 30 20 4F 43 LCALL MOV MOVX RETI MOV CLR LCALL MOV MOVX RETI MOV CLR LCALL MOV MOVX RETI MOV CLR LCALL MOV MOVX RETI MOV CLR LCALL MOV MOVX RETI ORG MSGO 03FAH A 63H RO
8. 40 C6 00 C6 50 C6 00 C6 60 C6 00 C6 70 C6 02 00 02 22 02 00 02 22 02 00 02 22 02 00 02 22 02 00 02 22 02 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV SI AX SI 02 0000 SI AX SI 02H AX 2230H SI SI 02H AX 0000H SI AX SI 02H 2240 SI SI 02H AX 0000H SI AX SI 02H AX 2250H SI AX SI 02H AX 0000H SI AX SI 02H AX 2260H SI AX SI 02H AX 0000H SI AX SI 02H AX 2270H SI AX SI 02H INT3 VECTOR ADDRESS INT4 VECTOR ADDRESS INT5 VECTOR ADDRESS INT6 VECTOR ADDRESS INT7 VECTOR ADDRESS 56 0000 2087 0000 208 B8 89 00 00 MOV 04 MOV AX 0000H SI AX INITIALIZATION SEQUENCE FOR SLAVE study card s interrupt controller 0000 208C 0000 208F 0000 2091 0000 2092 0000 2095 0000 2097 0000 2098 0000 209A 0000 209 0000 209D 0000 209E 0000 20A0 BA BO EE BA BO EE BO EE BO EE BO EE 90 00 MOV 15 MOV OUT 92 00 MOV 48 MOV OUT 00 MOV OUT 05 MOV OUT 00 MOV OUT DX 0090H AL 15H DX AL DX 0092H AL 48H DX AL AL DX AL AL 05 DX AL AL DX AL ICW1 SGL MODE ICW4 EDGE TRIGGERED INTERRUPT 1CW2 BASE ADDRESS ICW3 SLAVE SLAVE ID 0 ICWA 86 88 MODE OCW1 NO IN
9. 44 34 49 52 44 35 49 52 44 36 49 52 44 37 49 52 44 4E 55 OD 20 4E 55 OD 20 4E 55 OD 20 4E 55 OD 20 4E 55 0 20 55 OD 20 4E 55 OD 54 50 0A 49 54 50 0A 49 54 50 0A 49 54 50 0A 49 54 50 0A 49 54 50 0A 49 54 50 0A 00 MES2 MES3 MESA MES5 MES6 57 DB DB DB DB DB DB IR2 IR3 IR4 IR5 IR6 Is Is Is Is Is Is INTERRUPTED OAH OOH INTERRUPTED OAH OOH INTERRUPTED OAH OOH INTERRUPTED OAH OOH INTERRUPTED OAH OOH INTERRUPTED OAH OOH Configure 8259 to accept priority interrupt by using Set priority command In this program IRS is fixed as the bottom priority device So IR6 will have the highest one Execute this program in SERIAL mode only OAD 8259A STUDY CARD USER MANUAL NULI 45 Note test this program connect 8255 at 035 PAO to PA7 pins to EIRO to EIR7 pins of J2 Put the jumper JP1 to JP7 at 12 position 8000 8002 8004 8006 8008 800A 800c 800E 8010 8011 8013 8100 8103 8104 8107 8108 810B 810 810F 8110 8113 8114 8117 8118 811B 811 811F 8120 8121 8124 3E D3 3E D3 3E D3 3E D3 FB 3E D3 00 c3 00 c3 00 C3 00 C3 00 C3 00 C3 00 C3 00 DF 21 CD 80 43 16 90 81 91 C5 90 FF 40 21
10. 81 81 81 81 30 49 52 44 31 49 52 44 32 49 52 44 20 4E 55 OD 20 4E 55 OD 20 4E 55 OD R1 R2 R3 R4 R5 R6 R7 49 54 50 0 49 54 50 0 49 54 50 0 LXI CALL LXI CALL LXI CALL LXI CALL LXI CALL LXI CALL LXI CALL MESO MES1 MES2 UP H MES1 DISPM UP 52 DISPM UP H MES3 DISPM UP H MES4 DISPM UP H MES5 DISPM UP H MES6 DISPM UP H MES7 DISPM UP DB IRO IS INTERRUPTED OAH OOH DB IS INTERRUPTED OAH OOH DB IR2 IS INTERRUPTED 0ODH 0AH 00H 47 81 7 81 8 81AD 81B2 81B7 81BC 81BD 81C2 81C7 81CC 81D1 81D2 81D7 81DC 81 1 81 6 81 7 81 81 1 81 6 81 81 8201 8206 820 8210 00 49 53 45 54 00 49 53 45 54 00 49 53 45 54 00 49 53 45 54 00 49 53 45 54 00 52 20 52 45 52 20 52 45 52 20 52 45 52 20 52 45 52 20 52 45 33 49 52 44 34 49 52 44 35 49 52 44 36 49 52 44 37 49 52 44 20 4E 55 OD 20 4E 55 OD 20 4 55 OD 20 4E 55 OD 20 4E 55 OD 49 54 50 0A 49 54 50 0A 49 54 50 0A 49 54 50 0A 49 54 50 0A MES3 MESA MES5 MES6 MES7 OAD 8259A STUDY CARD USER MANUAL QUO DB DB DB DB DB IR3 IR4 IR5 IR6 Is Is Is Is Is INTERRUPTED
11. IRI 4 IR3 e IRA 5 lt IR6 8259 STUDY CARD USER MANUAL INTERRUPT MASK REG IMR M IR7 ADDRESS BUS 16 CONTROL BUS _ no vow mr mera DATA BUS 8 Z CS 0 D7 DO RD WR INT INTA CASO ees 8259A CASECADE CASI IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ LINES 4 gt CAS SP EN 7 6 5 4 4 2 1 0 SLAVE PROGRESS ENABLE BUFFER INTERRUPT REQUESTS Figure 5 8259A Interface to Standard System Bus INTERRUPT REQUEST REGISTER IRR AND IN SERVICE REGISTER ISR 8259A STUDY CARD USER MANUAL The interrupts at the IR input lines are handled by two registers in cascade the Interrupt Request Register IRR and the In Service Register ISR The IRR is used to store all the interrupt levels which are requesting service and the ISR is used to store all the interrupt levels which are being serviced PRIORITY RESOLVER This logic block determines the priorities of the bits set in the IRR The highest priority is selected and strobed into the corresponding bit of the ISR during INTA pulse INTERRUPT MASK REGISTER IMR The IMR stores the bits which mask the interrupt lines to be masked The IMR operates on the IRR Masking of a higher priority input will not affect the interrupt request lines of lower priority INT INTERRUPT This output goes directly to the CPU interrupt input The Voy level on this line is designed to be fully compatible with t
12. 00 FE CALLS 0000 2214 2E CS 0000 2215 8D 16 BA 20 LEA 0000 2219 BA C2 MOVW 0000 221B 9A 55 1B 00 FE CALLS 0000 2220 INT3 ORG 0000 2250 FA CLI 0000 2251 2E cs OAD JDO 8259A STUDY CARD USER MANUAL AL AL 48 BASE ADDRESS 72d DX 01 ICW3 MASTER DX IRO HAS A SLAVE ON 0D ICW4 MASTER DX 86 88 MODE AEOI 0FE OCW1 ALL INTERRUPTS DX ARE MASKED EXCEPT INTO SET INTERRUPT FLAG 20A8 OA 0 OD M INTERRUPT 0 OCCURRED N 0 2200 ISR FOR INTERRUPT 0 DX 20 DX FE00 1B55 AL 30 00 1 50 DX 20 DX 00 1 55 2250 ISR FOR INTERRUPT 1 51 0000 2252 8D 16 AA 20 LEA 0000 2256 BA C2 MOVW 0000 2258 9A 55 1B 00 FE CALLS 0000 225D BO 31 MOVB 0000 225F 9A 50 1B 00 FE CALLS 0000 2264 2E cs 0000 2265 8D 16 BA 20 LEA 0000 2269 BA C2 MOVW 0000 226B 9A 55 1B 00 FE CALLS 0000 2270 cc INT3 ORG 0000 2300 FA CLI 0000 2301 2E cs 0000 2302 8D 16 AA 20 LEA 0000 2306 BA C2 MOVW 0000 2308 9A 55 1B 00 FE CALLS 0000 230D BO 32 MOVB 0000 230F 9A 50 1B 00 FE CALLS 0000 2314 2E cs 0000 2315 8D 16 BA 20 LEA 0000 2319 BA C2 MOVW 0000 231B 9A 55 1B 00 FE CALLS 0000 2320 cc INT3 ORG 0000 2350 FA CLI 0000 2351 2E cs 0000 2352 8D 16 AA 20 LEA 0000 2356 BA C2 MOVW 0000 2358 9A 55 1B 00 FE CALLS 0000 235D BO 33 MOVB 0000 235F 9A 50 1B 00 FE CALLS 0000 2364 2E cs 0000 2365 8D 16 BA 20 LEA 0000 2369 BA C2 MOVW 0000 236 9A 55 1B 00 FE CALLS OAD JDO 8259A STU
13. 2450 0136 0000 0138 2500 013A 0000 013C 2550 013E 0000 SLAVE INT4 VECTOR ADDRESS SLAVE INT5 VECTOR ADDRESS SLAVE INT6 VECTOR ADDRESS SLAVE INT7 VECTOR ADDRESS SLAVE INITIALIZATION SEQUENCE FOR SLAVE MOVW MOVB OUTB MOVW MOVB OUTB MOVB OUTB MOVB OUTB MOVB OUTB INITIALIZATION FF FF MOVW DX 0090 ICW1 AL 15 SGL MODE ICW4 NEEDED DX EDGE TRIGGERED INTERRUPT DX 0092 ICW2 AL 48 BASE ADDRESS 72d DX FOR 48 INTERRUPT AL 00 ICW3 SLAVE DX SLAVE ID 000 AL 05 ICW4 DX 86 88 MODE AL 00 OCW1 DX NO INTERRUPTS MASKED ON SLAVE SEQUENCE FOR MASTER INTERRUPT CONTROLLER DX OFFF4 MOVB AL 15 OUTB MOVW OAD 8259A STUDY CARD USER MANUAL NULI DX DX 0FFF6 2 CAS MODE ICW4 NEEDED EDGE TRIGGERED INTERRRUPT ICW2 50 0000 209 0 48 0000 209D EE OUTB 0000 209E BO 01 MOVB 0000 20A0 EE OUTB 0000 20A1 BO OD MOVB 0000 20A3 EE OUTB 0000 20A4 BO FE MOVB 0000 20A6 EE OUTB 0000 20A7 FB STI 0000 20A8 EB FE JMP 0000 20AA 0A 0A DB 0000 20AC OD DB 0000 20AD 49 4E 54 45 52 52 ASC 0000 20B3 55 50 54 20 2D 20 0000 20B9 00 DB 0 0000 20 20 4F 43 43 55 ASC 0000 20 52 52 45 44 21 0000 20C4 00 DB O0 ORG 0000 2200 FA CLI 0000 2201 2E CS 0000 2202 8D 16 AA 20 LEA 0000 2206 BA C2 MOVW 0000 2208 9A 55 1B 00 FE CALLS 0000 220D BO 30 MOVB 0000 220F 9A 50 1B
14. 44 33 49 52 44 34 49 52 44 35 49 52 44 36 49 52 44 37 49 52 44 4E 55 OD 20 4E 55 OD 20 4E 55 OD 20 4E 55 OD 20 4E 55 0 20 55 OD 20 4E 55 0 54 50 0A 49 54 50 0A 49 54 50 0A 49 54 50 0A 49 54 50 0A 49 54 50 0A 49 54 50 0A MES2 MES3 MESA MES5 MES6 57 OAD 8259A STUDY CARD USER MANUAL NULI DB DB DB DB DB DB IR2 IR3 IR4 IR5 IR6 Is Is Is Is Is Is INTERRUPTED OAH OOH INTERRUPTED OAH OOH INTERRUPTED OAH OOH INTERRUPTED OAH OOH INTERRUPTED OAH OOH INTERRUPTED OAH OOH 29 This Program configures the 8259 to accept 8 interrupt requests from onboard sources Keep the dipswitch SW1 for corresponding interrupt Execute the program from 8000H Then press the push button switch Execute the program in KEYBOARD mode only 8000 8002 8004 8006 8008 800A 800C 800E 8010 8011 8200 8203 8206 8207 8208 820B 820E 820F 8210 8213 8216 8217 8218 821B 821E 821F 8220 8223 3E D3 3E D3 3E D3 3E D3 FB c3 CD c3 00 00 CD c3 00 00 CD C3 00 00 CD C3 00 00 CD C3 12 90 82 91 00 91 20 90 11 3E 5B 3E 66 3E 71 3E 7C 3E 87 80 82 82 82 82 82 82 82 82 82 82 RDKBD START
15. A DPTR MSG4 PSW 5 03FAH A 64H RO A DPTR MSG5 PSW 5 03FAH A 65H RO A DPTR MSG6 PSW 5 03FAH 66H RO A DPTR MSG7 PSW 5 03FAH A 67H RO A 8500H LOOK UP TABLE TO STORE THE MESSAGES 20H 20H 0AH INTO OCCURRED OAH ODH OOH 67 8259A STUDY CARD USER MANUAL 850 850F 8513 8518 851D 8522 8526 852B 8530 8535 8539 853E 8543 8548 854C 8551 8556 855B 855F 8564 8569 856E 8572 8577 857C 8581 8585 858A 858F 8594 OAD QUO 43 44 20 54 43 44 20 54 43 44 20 54 43 44 20 54 43 44 20 54 43 44 20 54 43 44 20 54 43 44 8259A STUDY CARD USER MANUAL 55 0A 20 31 55 0A 20 32 55 0A 20 33 55 0A 20 34 55 0A 20 35 55 0A 20 36 55 0A 20 37 55 0A 52 OD 0A 20 52 OD 0A 20 52 OD 0 20 52 OD 0 20 52 OD 0 20 52 OD 0A 20 52 OD 0A 20 52 OD 52 00 49 52 00 49 52 00 49 4F 52 00 49 52 00 49 4F 52 00 49 52 00 49 4F 52 00 45 4E 45 4E 43 45 4E 45 4E 43 45 4E 45 4E 43 45 4E 43 45 MSG1 MSG2 MSG3 MSGA MSG5 MSG6 MSG7 DB DB DB DB DB DB DB 20H 20H 0AH INT1 OCCURRED OAH ODH OOH 20H 20 OAH INT2 OCCURRED OAH ODH OOH 20H 20H OAH INT3 OCCURRED OAH ODH 00H 20H 20H OAH INT
16. INITILIZATION COMMAND WORDS 1 AND 2 ICW ICW2 5 15 Page starting address of service routines In an MCS 80 85 system the 8 request levels will generate CALLs to 8 locations equally spaced at intervals of 4 of 8 memory locations thus the 8 routines will occupy a page of 32 or 64 bytes respectively The address format is 2 bytes long Ao A 5 When the routine interval is 4 Ao A are automatically inserted by the 8259A while are programmed externally When the routine interval is 8 are automatically inserted by the 8259A While 6 15 are programmed externally The 8 byte interval will maintain compatibility with current software while the 4 byte interval is best for a compact jump table In an iAPX 86 system are inserted in the five most significant bits of the vectoring byte and the 8259A sets the three least significant bits according to the interrupt level 0 are ignored and ADI Address interval has no effect LTIM If LTIM 1 then the 8259A will operate in the level interrupt mode Edge detect logic on the interrupt mode Edge defect logic on the interrupt inputs will be disabled ADI CALL address interval ADI 1then interval 24 0 then interval 8 SNGL Single Means that this is the only 8259A in the system If SNGL 1 no ICW3 will be issued 4 If this bit is set ICWA4 has to be read If ICW4 is not needed set IC4 0 INITILIZATION COMMAND WORD 3 ICW3 This word is
17. ISR a normal IR7 interrupt will set the corresponding ISR bit a default IR7 won t If a default IR7 routine occurs during a normal IR7 routine however the ISR will remain set In this case it is necessary to keep track of whether or not the IR7 routine was previously entered If another IR7 occurs it is a default THE SPECIAL FULLY NESTED MODE This mode will be used in the case of a big system where cascading is used and the priority has to be conserved within each slave In this case the fully nested mode will be programmed to the master using ICW4 This mode is similar to the normal nested mode with the following exceptions a When an interrupt request from a certain slave is in service this slave is not locked out from the master s priority logic and further interrupt requests from higher priority IR s within the slave will be recognized by the master and will initiate interrupts to the processor In the normal nested mode a slave is masked out when its request is in service and no higher requests from the same slave can be serviced b When exiting the interrupt Service routine the software has to check whether the interrupt serviced was the only one from that slave This is done by sending a non specific End of interrupt EOI command to the slave and then reading its in service register and checking for zero If it is empty a non specific EOI can be sent to the master too If not no EOI should be sent BUFFERED MODE When the 82
18. MODE MASTER 1 SPECIAL FULLY NESTED MODE 0 NOT SPECIAL FULLY NESTED MODE Figure 7 Initialization Command Word Format OAD JDO 8259A STUDY CARD USER MANUAL 1 8086 8088 MODE 20 OPERATION COMMAND WORDS OCWs After the initialization Command Words IC Ws are programmed into the 8259A the chip is ready to accept interrupt requests at its input lines However during the 8259A operation a selection of algorithms can command the 8259A to operate in various modes through the Operation Command Words OCWs OPERATION CONTROL WORDS OCWs 0 7 D6 05 D4 D3 D2 DI DO M7 M6 M5 M4 M3 M2 MI 0 OCW2 R SL EOI 0 0 12 10 OCW3 0 5 SMM 0 1 RR RIS OPERATION CONTROL WORD 1 OCW1 sets and clears the mask bits in the interrupt Mask Register represents the eight mask bits M 1 indicates the channel is masked inhibited 0 indicates the channel is enabled OPERATION CONTROL WORD 2 OCW2 R SL EOI These three bits control the Rotate and End of interrupt modes and combinations of the two A chart of these combinations can be found on the Operation Command Word Format L L Lo These bits determine the interrupt level acted upon when the SL bit is active OPERATION CONTROL WORD 3 OCW3 ESMM Enable Special Mask Mode When this bit is set to 1 it enables the SMM bit to set or res
19. OAH OOH INTERRUPTED OAH OOH INTERRUPTED OAH OOH INTERRUPTED OAH OOH INTERRUPTED OAH OOH 48 5 DEMONSTRATION PROGRAM FOR 8086 SERIES KITS 5A DEMONSTRATION PROGRAM FOR ESA 86 88 2 TRAINER The following Program configures the Study Card s 8259 as Slave and onboard 8259 i e Trainer s as Master in cascade mode The Slave interrupt will be connected to INTO of Master The interrupts to Slave can be given from on board dipswitch and push button Keep the dipswitch SW1 for corresponding interrupt Execute the program from 2000H Then press the push button switch Execute the program in serial mode Place a Jumper between 1 and 2 INTO of JP8 on the Trainer before executing the Program Onboard 8259 addresses are FFF4 and FFF6 Study Card s 8259 addresses are 0090 and 0092 0000 2000 0000 2001 0000 2004 0000 2006 0000 2008 0000 200A 0000 200D 0000 200E 0000 2014 0000 2015 0000 201B 0000 201C 0000 2022 0000 2023 0000 2029 0000 202A 0000 2030 0000 2031 0000 2037 0000 2038 0000 203E FA B8 8E 8E 80 BC 26 C7 26 C7 26 C7 26 C7 26 C7 26 C7 26 C7 26 00 C8 co DO 00 06 06 06 06 06 06 06 00 30 20 22 24 26 28 2A 2C 01 01 01 01 01 01 01 00 00 50 00 00 00 50 22 00 22 00 23 00 23 ORG CLI MOVW MOVW MOVW MOVW MOVW ES MOVW E
20. read only when there is more than one 8259A in the system and cascading is used in which case SNGL 0 it will load the 8 bit slave register The functions of this register are a In the master mode either when SP 1 or in buffered mode when M S 1 in ICW4 a 1 is set for each slave in the system The master then will release byte 1 of the call sequence for MCS 80 85 system and will enable the corresponding slave to release bytes 2 and 3 for 1APX 86 only byte 2 through the cascade lines b Inthe slave mode either when SP 0 or if BUF 1 and M S 0 in ICWA bits 2 0 identify the slave slave compares its cascade input with these bits and if they are equal bytes 2 and 3 of the call sequence or just byte 2 for iAPX 86 are released by it on the Data Bus INITIALIZATION COMMAND WORD 4 ICW4 SFNM If SENM Ithe special fully nested mode is programmed BUF If BUF 1 the buffered mode is programmed In buffered mode SP EN becomes an enable output and the master slave determination is by M S M S If buffered mode is selected M S 1 means the 8259A is programmed to be a master M S 0 means the 8259A is programmed to be a slave If BUF 0 M S has no function AEOI If AEOI 1 the automatic end of interrupt mode is programmed uPM Microprocessor mode uPM 0 sets the 8259A for MCS 80 85 system operation uPM 1 sets the 8259A for iAPX 86 system operation 15 OAD JDO 8259A STUDY CARD USER MANUAL ICW1
21. 0 8123 8126 8127 8128 812 812 812F 8130 8133 8136 8137 8138 813B 813E 813F 8140 8143 8146 814B 8150 8155 815A 815B 21 C3 00 00 21 C3 00 00 21 C3 00 00 21 C3 00 00 21 C3 00 00 21 C3 00 00 21 C3 00 00 CD C3 49 53 45 54 00 49 5B 40 70 40 85 40 9A 40 AF 40 C4 40 D9 40 04 14 52 20 52 45 52 81 81 81 81 81 81 81 81 81 81 81 81 81 81 OB 80 30 49 52 44 31 20 4E 55 OD 20 SUBRT 49 54 50 0A 49 LXI H MES1 JMP SUBRT NOP NOP LXI H MES2 JMP SUBRT NOP NOP LXI H MES3 JMP SUBRT NOP NOP LXI 54 JMP SUBRT NOP NOP LXI H MES5 JMP SUBRT NOP NOP LXI 56 JMP SUBRT NOP NOP LXI H MES7 JMP SUBRT NOP NOP CALL DISPM JMP UP MESO DB IRO IS INTERRUPTED ODH OAH OOH MES1 DB IR1 IS INTERRUPTED ODH OAH 44 OAD 8259A STUDY CARD USER MANUAL QUO EXAMPLE 4 8160 8165 816 816F 8170 8175 817A 817F 8184 8185 818A 818F 8194 8199 819A 819F 81 4 81A9 81AE 81AF 81B4 81B9 81BE 81C3 81C4 81C9 81CE 81D3 81D8 81D9 81DE 81 81 8 53 45 54 00 49 53 45 54 00 49 53 45 54 00 49 53 45 54 00 49 53 45 54 00 49 53 45 54 00 49 53 45 54 20 52 45 52 20 52 45 52 20 52 45 52 20 52 45 52 20 52 45 52 20 52 45 52 20 52 45 49 52 44 32 49 52 44 33 49 52
22. 0 0 1 IRO T7 T6 5 T4 T3 0 0 0 PROGRAMMING THE 8259A The 8259A accepts two types of command words generated by the CPU 1 Initialization Command Words ICWS Before normal operation can begin each 8259A the system must be brought to a starting point by a sequence of 2 to 4 bytes timed by WR pulses 2 Operation Command Words OCWS These are the command words which command the 8259A to operate in various interrupt modes These modes are Fully nested mode Rotating priority mode Special mask mode Polled mode OCWs can be written into the 8259A anytime after initialization INITILIZATION COMMAND WORDS ICWS GENERAL Whenever a command is issued with AO 0 and D4 1 this is interpreted as initialization Command Word 1 ICW1 ICW1 starts the initialization sequence during which the following automatically occur a The edge sense circuit is reset which means that following initialization an interrupt request input must make a low to high transition to generate an interrupt b The interrupt Mask Register is cleared IR7 input is assigned priority 7 The slave mode address is set to 7 e Special Mask Mode is cleared and Status Read is set to IRR f IfIC4 0 then all functions selected in ICW4 are set to zero Non Buffered mode 1 MCS 80 85 system 14 OAD JDO 8259A STUDY CARD USER MANUAL Note Master Slave in ICW4 is only used in the buffered mode
23. 0 B8 00 00 MOV AX 0000H INITIALIZE SEGMENT 0000 2003 8E C8 MOV CS AX REGISTERS 0000 2005 8E CO MOV ES AX 0000 2007 8E DO MOV SS AX 0000 2009 BC 00 30 MOV SP 3000H INITIALIZE SP INTERRUPT VECTOR TABLE INITIALIZATION 0000 200C BE 20 01 MOV SI 0120H INTO VECTOR ADDRESS 0000 200F 8 00 22 MOV AX 2200H 0120H IS THE BASE OF INT 0000 2012 89 04 MOV SI AX VECTOR TABLE 0000 2014 83 C6 02 ADD SI 02H 0000 2017 B8 00 00 MOV AX 0000H 0000 201A 89 04 MOV SI AX 0000 201C 83 C6 02 ADD SI 02H INT1 VECTOR ADDRESS 0000 201F B8 10 22 MOV AX 2210H 0000 2022 89 04 MOV SI AX 0000 2024 83 C6 02 ADD SI 02H 0000 2027 B8 00 00 MOV AX 0000H 0000 202A 89 04 MOV SI AX 0000 202C 83 c6 02 ADD SI 02H INT2 VECTOR ADDRESS 0000 202F B8 20 22 AX 2220H 55 OAD Uo 8259A STUDY CARD USER MANUAL 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 OAD 8259A STUDY CARD USER MANUAL NULI 2032 2034 2037 203A 203C 203F 2042 2044 2047 204A 204C 204F 2052 2054 2057 205A 205C 205F 2062 2064 2067 206A 206C 206F 2072 2074 2077 207A 207C 207F 2082 2084 89 83 B8 89 83 B8 89 83 B8 89 83 B8 89 83 B8 89 83 B8 89 83 B8 89 83 B8 89 83 B8 89 83 B8 89 83 C6 00 C6 30 C6 00 C6
24. 00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 250F 2514 2515 2519 251B 2520 2550 2551 2552 2556 2558 255D 255F 2564 2565 2569 256B 2570 9A 2E 8D BA 9A cc FA 2E 8D BA 9A BO 9A 2E 8D BA 9A cc 50 16 2 16 2 2 1B BA 1B 1B 1B BA 1B 00 20 00 20 00 00 20 00 FE FE FE FE FE CALLS cs LEA MOVW CALLS INT3 ORG CLI cs LEA MOVW CALLS MOVB CALLS cs LEA MOVW CALLS INT3 OAD 8259A STUDY CARD USER MANUAL QUO 00 1 50 DX 20 AX DX 00 1 55 2550 DX 20 00 1 55 AL 37 00 1 50 DX 20 AX DX 00 1 55 ISR FOR INTERRUPT 7 54 5B DEMONSTRATION PROGRAM FOR ESA 86 88 3 TRAINER The following Program configures the Study Card s 8259 as Slave and onboard 8259 i e Trainer s as Master in cascade mode The Slave interrupt will be connected to INTO of Master The interrupts to Slave can be given from on board dipswitch and push button Keep the dipswitch SW1 for corresponding interrupt Execute the program from 2000H Then press the push button switch Execute the program in serial mode Place a Jumper between and INTO of JP15 on the Trainer before executing the Program Onboard Trainer s 8259 addresses are FFF4 and FFF6 Study Card s 8259 addresses are 0090 and 0092 ORG 2000H 0000 200
25. 00 20 35 52 00 20 36 52 00 20 37 52 20 20 52 20 20 52 20 20 52 20 20 52 20 20 52 20 20 52 20 20 52 FA 0A AF 45 0A AF 45 0A AF 45 0A AF 45 0A AF 45 0A AF 45 0A AF 45 49 43 44 49 43 44 49 43 44 49 43 44 49 43 44 49 43 44 49 43 44 AE 43 0A 43 0 4E 43 0A AE 43 0A AE 43 0A AE 43 0A AE 43 0A 54 55 OD 54 55 OD 54 55 OD 54 55 0 54 55 OD 54 55 OD 54 55 OD 2E 8D 16 00 21 E9 71 00 CC FA MSG1 MSG2 MSG3 MSG4 MSG5 MSG6 MSG7 00 ORG CLI LEA JMP INT ORG CLI 2E 8D 16 13 21 LEA DB DB DB DB DB DB DB OAD 8259A STUDY CARD USER MANUAL NULI 20H 20H OAH INT1 20H 20H OAH INT2 20H 20H 0AH INT3 20H 20H 0AH INT4 20H 20H OAH 5 20H 20H OAH INT6 20H 20H OAH INT7 2200H DX MSGO DISP 03H 2210H DX MSG1 OCCURRED OAH ODH 00H OCCURRED OAH ODH 00H OCCURRED OAH ODH 00H OCCURRED OAH ODH 00H OCCURRED OAH ODH 00H OCCURRED OAH ODH 00H OCCURRED OAH 00H ISR FOR INTERRUPTO ISR FOR INTERRUPT1 58 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 OAD 825
26. 0000 209D 0000 209E 0000 209F 0000 2100 0000 2106 0000 210C 0000 2111 0000 2117 0000 211D 0000 2122 0000 2128 0000 212E 0000 2133 0000 2139 0000 213F 0000 2144 0000 214A 0000 2150 0000 2155 0000 215B 0000 2161 0000 2166 0000 216C 0000 2172 0000 2177 EE BO EE FB E9 20 30 52 20 31 52 20 32 52 20 33 52 20 34 52 20 35 52 20 36 52 20 00 FD 20 20 45 20 20 45 20 20 45 20 20 45 20 20 45 20 20 45 20 20 45 20 FF 0A AF 44 0A AF 44 0A AF 44 0A AF 44 0A AF 44 0A AF 44 0A AF 44 0A OUT MOV OUT STI HERE JMP 49 43 0A 49 43 0A 49 43 0A 49 43 0A 49 43 0A 49 43 0A 49 43 0A 49 AE 43 OD 4E 43 OD 4E 43 0 4 43 OD 4E 43 OD 4E 43 OD AE 43 OD 4E 54 55 54 55 54 55 54 55 54 55 54 55 54 55 54 ORG 560 MSG1 MSG2 MSG3 MSGA MSG5 MSG6 MSG7 OAD 8259A STUDY CARD USER MANUAL NULI DX AL AL 00H DX AL HERE OCW1 ENABLE ALL INTERRUPTS ENABLE INTR OF 8086 TRAINER 2100H MESSAGES DB DB DB DB DB DB DB DB 20H 20H 0AH INTO 20H 20H 0AH INT1 20H 20H 0AH INT2 20H 20H 0AH INT3 20H 20H 0AH INT4 20H 20H OAH 5 20H 20H OAH INT6 20H 20H OAH INT7 FOR ISRs OCCURRED OCCURRED
27. 001101 onto the 8 bit Data Bus through its D7 0 pins 5 This CALL instruction will initiate two more INTA pulses to be sent to the 8259A from the CPU group 6 These two INTA pulses allow the 8259A to release its preprogrammed subroutine address onto the Data Bus The lower 8 bit address is released at the first INTA pulse and the higher 8 bit address is released at the second INTA pulse 7 This completes the 8 byte CALL instruction released by the 8259A In the AEOI mode the ISR bit is reset at the end of the third INTA pulse Otherwise the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt sequence The events occurring in an iAPX 86 systems are the same until step 4 4 Upon receiving an INTA from the CPU group the highest priority ISR bit is set and the corresponding IRR bit is reset The 8259A does not drive the Data Bus during this cycle 5 The iAPX 86 10 will initiate a second INTA pulse During the pulse the 8259A releases 8 bit pointer onto the Data Bus where it is read by the CPU 6 This completes the interrupt cycle In the AEOI mode the ISR bit is reset at the end of the second INTA pulse Otherwise the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt subroutine If no interrupt request present at step 4 of either sequence i e the request was too short in duration the 8259A will issue an interrupt level 7 Both the vectoring b
28. 126 8127 3E D3 3E D3 3E D3 3E D3 FB c3 DF 21 c3 00 00 21 c3 00 00 21 C3 00 00 21 C3 00 00 21 C3 00 00 12 90 81 91 00 91 FD 91 11 46 40 5B 40 70 40 85 40 9A 40 DISPM 80 81 81 81 81 81 81 81 81 81 81 EQU START 555 UP 0 5 ORG MVI OUT MVI OUT MVI OUT MVI OUT EI JMP RST ORG LXI NOP NOP LXI NOP NOP LXI NOP NOP LXI NOP NOP LXI NOP NOP OAD 8259A STUDY CARD USER MANUAL QUO 8000H A 12H 90H A 81H 91H A 00H 91H 91H 555 8100 50 SUBRT H MES1 SUBRT H MES2 SUBRT H MES3 SUBRT H MES4 SUBRT single edge triggerd mode call address interval 8 interrupt vector address Normal EOI for 80 85 mode for 8259 Enable only IR1 interrupt in OCW1 Routine to display the message 33 8128 812 812 812F 8130 8133 8136 8137 8138 813B 813E 813F 8140 8143 8146 814B 8150 8155 815A 815B 8160 8165 816A 816F 8170 8175 817A 817F 8184 8185 818A 818F 8194 8199 819A 819F 21 c3 00 00 21 c3 00 00 21 C3 00 00 CD C3 49 53 45 54 00 49 53 45 54 00 49 53 45 54 00 49 53 45 54 00 49 53 AF 40 C4 40 D9 40 5B 14 52 20 52 45 52 20 52 45 52 20 52 45 52 20 52 45 52 20 81 81 81 81 81 81 OB 80 30 49 52 44 31 49 52 44 32 49 5
29. 2 44 33 49 52 44 34 49 20 4E 55 OD 20 4E 55 OD 20 4E 55 OD 20 4E 55 OD 20 4E SUBRT 49 54 50 0A 49 54 50 0A 49 54 50 0A 49 54 50 0A 49 54 LXI NOP NOP LXI NOP NOP LXI NOP NOP CALL MESO MES1 MES2 MES3 MES4 OAD 8259A STUDY CARD USER MANUAL QUO DB DB DB DB DB H MES5 SUBRT H MES6 SUBRT H MES7 SUBRT DISPM UP IRO IS INTERRUPTED ODH OAH OOH 1 IS INTERRUPTED ODH OAH IR2 IS INTERRUPTED ODH OAH 00H IR3 IS INTERRUPTED ODH OAH 00H IRA IS INTERRUPTED ODH OAH 00H 34 81 4 45 52 52 55 50 81A9 54 45 44 OD OA 81AE 00 81AF 49 52 35 20 49 55 DB IR5 IS INTERRUPTED ODH OAH OOH 81 4 53 20 49 4E 54 81 9 45 52 52 55 50 81 54 45 44 OD OA 81C3 00 81 4 49 52 36 20 49 56 DB IR6 IS INTERRUPTED ODH OAH OOH 81C9 53 20 49 4E 54 81CE 45 52 52 55 50 81D3 54 45 44 OD OA 81D8 00 8109 49 52 37 20 49 MES7 DB IR7 IS INTERRUPTED ODH OAH OOH 81DE 53 20 49 4E 54 81E3 45 52 52 55 50 81E8 54 45 44 OD OA 81ED 00 EXAMPLE 4 This Program configures 8259 to accept priority interrupt by using Set priority command In this program IRS is fixed as the bottom priority device So IR6 will have the highest one Execute this program in SERIAL mode only Note test this program Connect 8255 at U12 PAO to PA7 pins to EIRO to EIR7 pins of J2 Put the j
30. 226 8227 8228 822B 822E 822F 8230 8233 8236 8237 8238 823B 823E 8240 8242 8244 8246 8248 824A 824 824 8250 8252 8254 8256 00 00 CD c3 00 00 CD c3 00 00 CD c3 00 00 CD c3 00 00 CD c3 00 00 CD c3 3E D3 3E D3 3E D3 3E D3 3E D3 3E D3 3E 3E 71 3E 7C 3E 87 3E 92 3E 9D 3E A8 90 31 60 30 45 30 87 30 05 30 F3 30 00 82 82 82 82 82 82 82 82 82 82 82 82 RO NOP NOP CALL NOP NOP CALL NOP NOP CALL NOP NOP CALL NOP NOP CALL NOP NOP CALL MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT MVI RO 52 RO 53 RO 54 RO 55 RO 56 RO 57 90 Routine to display 31H Intr 00 on seven segment A 60H display 30H A 45H 30H A 87H 30H A 05H 30H A 30H A 00H 41 8258 D3 30 OUT 825A C9 RET 825B 3E 95 S0 MVI 825D D3 31 OUT 825F 3E F3 MVI 8261 D3 30 OUT 8263 C3 0 82 JMP 8266 3E 95 S1 MVI 8268 D3 31 OUT 826A 3E 60 MVI 826C D3 30 OUT 826E C3 0 82 JMP 8271 3E 95 52 MVI 8273 D3 31 OUT 8275 3E B5 MVI 8277 D3 30 OUT 8279 C3 BO 82 JMP 827C 3E 95 S3 MVI 827E D3 31 OUT 8280 F4 MVI 8282 D3 30 OUT 8284 C3 BO 82 JMP 8287 3E 95 54 MVI 8289 D3 31 OUT 828B 3E 66 828D D3 30 OUT 828F C3 B0 82 JMP 8292 3E 95 S5 MVI 8294 D3 31 OUT 8296 3E D6 MVI 8298 D3 30 OUT 829A C3 B0 82 JMP 829D 3E 95 S6 MVI 829F D3 31 OUT 82A1 3E D7 MVI 82 D3
31. 2A 33 3C 45 AE 57 60 69 04 81 81 81 81 81 81 81 81 UP 81 DISPM EQU ORG 8000H MVI A 80H OUT 43H MVI A 16H OUT 90H MVI A 81H OUT 91H MVI 5 90H EI MVI 40H ORG 8100H JMP RO NOP JMP R1 NOP JMP R2 NOP JMP R3 NOP JMP R4 NOP JMP R5 NOP JMP R6 NOP JMP R7 NOP RST 3 RO LXI CALL OAD 8259A STUDY CARD USER MANUAL NULI Configure 8255 all ports O P Single edge triggerd mode call address interval 4 Interrupt vector address Fix IR5 as bottom priority by set priority command in OCW2 Send all IRO to IR7 high at a time Interrupt vector address for IRO Interrupt vector address for and so on H MESO Routine to display messages DISPM 46 8127 812 812D 8130 8133 8136 8139 813C 813F 8142 8145 8148 814B 814E 8151 8154 8157 815A 815D 8160 8163 8166 8169 816E 8173 8178 817D 817E 8183 8188 818D 8192 8193 8198 819D 81 2 OAD 8259A STUDY CARD USER MANUAL QUO c3 21 CD c3 21 CD c3 21 CD c3 21 CD c3 21 CD c3 21 CD c3 21 CD c3 49 53 45 54 00 49 53 45 54 00 49 53 45 54 20 7E 04 20 93 04 20 A8 04 20 BD 04 20 D2 04 20 E7 04 20 FC 04 20 52 20 52 45 52 20 52 45 52 20 52 45 81 81 81 81 81 81 81 81 81 81 81
32. 30 OUT 82 5 0 82 JMP OAD JDE 8259A STUDY CARD USER MANUAL 30H 95 31H LOOP A 95H 31H A 60H 30H LOOP A 95H 31H 5 LOOP A 95H 31H A OF4H 30H LOOP A 95H 31H A 66H 30H LOOP A 95H 31H A 0D6H 30H LOOP A 95H 31H A 0D7H 30H LOOP 42 82 8 95 57 MVI 95 82AA D3 31 OUT 31H 82AC 3E 70 MVI A 70H 82AE D3 30 OUT 30H 82B0 CD 14 05 LOOP CALL RDKBD Waiting for NEXT key 82B3 FE 1C CPI 1CH 82B5 C2 BO 82 JNZ LOOP 82B8 DF RST 3 EXAMPLE 3 Configure 8259 to accept interrupt requests from onboard sources by using interrupt mask command in Keep the dipswitch SW1 for IR1 interrupt Execute the program from 8000H Then press the push button switch Execute the program in SERIAL mode only DISPM EQU 0B04H ORG 8000H 8000 3E 12 START MVI A 12H single edge triggerd mode call address interval 8 8002 D3 90 OUT 90H 8004 3E 81 MVI A 81H interrupt vector address 8006 D3 91 OUT 91H 8008 3E 00 MVI A 00H Normal EOI for 80 85 800A D3 91 OUT 91H mode for 8259 800C 3E FD MVI A 0FDH Enable only interrupt 800E D3 91 OUT 91H in OCW1 8010 FB EI 8011 C3 11 80 SSS JMP SSS 8014 DF UP RST 3 ORG 8100H 8100 21 46 81 LXI H MESO Routine to display 8103 C3 40 81 JMP SUBRT the message 8106 00 NOP 8107 00 NOP 43 OAD JDE 8259A STUDY CARD USER MANUAL 8108 810 810 810 8110 8113 8116 8117 8118 811 811 811 812
33. 4 OCCURRED OAH ODH 00H 20H 20 OAH INT5 OCCURRED OAH ODH OOH 20H 20H OAH INT6 OCCURRED OAH ODH 00H 20H 20 OAH INT7 OCCURRED OAH 00H 68 VER Ho 1 2 3 41 5 517 0519 7 gus 51 sh T Fi 30 PM FRE MALE ST LL s l eee 26 PIN FRC BALE ST Ww os 26 FEC L 3 OAD 8259A STUDY CARD USER MANUAL QUO vy gt gt BANGALORE GSA ELECTRO 69 a BIE WR Sp EN tnst IN 52 4 mr vri CHR E EN umm Dm E 5279 T 7 4 VIN n ELECTRO SYSTEMS ASFOCIATES PVT LTD L Title 915245 STUDY CARD 8259 Erre ecument Number PRN AND CKD BY SUDHA tate 23 ecoopreet IS 70 8259A STUDY CARD USER MANUAL 1 re 13 4 ESI 47 8 adl 12 S BURE 1 S 1 d RU 13 21 23 pov me 2 mua 3 7 25 26 l ss q 1 4 5 6 7 6 9 1 1 1 1 2 ELECTRO SYSTEMS ASSOCIATES PVT LTD tte bedei Leta 22605050 STUDY CARD PIC 9259 NIME TT 34 DRN AND BY SUDHA Wate Feb vary E 5 2000 l 420
34. 59A STUDY CARD USER MANUAL NULI 203F 2042 2044 2047 204A 204C 204F 2052 2054 2057 205A 205C 205F 2062 2064 2067 206A 206C 206F 2072 2074 2077 207A 207C 207F 2082 2084 2087 208A 208C 208F 2091 2092 2095 2097 2098 B8 89 83 B8 89 83 B8 89 83 B8 89 83 B8 89 83 B8 89 83 B8 89 83 B8 89 83 B8 89 83 B8 89 BA BO EE BA BO EE BO 30 04 6 00 04 6 40 04 6 00 04 6 50 04 6 00 04 6 60 04 6 00 04 C6 70 04 C6 00 04 C8 17 CA 48 03 22 02 00 02 22 02 00 02 22 02 00 02 22 02 00 02 22 02 00 FF FF MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV OUT MOV MOV OUT MOV AX 2230E SI SI 02H AX 0000H SI SI 02H INT4 VECTOR ADDRESS 2240 SI SI 02H AX 0000H SI AX SI 02H INT5 VECTOR ADDRESS AX 2250H SI AX SI 02H AX 0000H SI AX SI 02H INT6 VECTOR ADDRESS AX 2260H SI AX SI 02H AX 0000H SI AX SI 02H INT7 VECTOR ADDRESS AX 2270H SI AX SI 02H AX 0000H SI AX 18259 INTIALIZATION DX OFFC8H AL 17H ICW1 IC4 NEEDED SINGLE DX AL INTERVAL 4 EDGE TRIG INT DX OFFCAH ICW2 MULTIPLE FOR INT VECTOR AL 48 ADDRESS TABLE FOR MAKING 120H DX AL BASE ADDRESS OF TABLE AL 03H ICW4 8086 MODE AUTO EOI 61 0000 209 0000 209
35. 59A is used in a large system where bus driving buffers are required on the data bus and the cascading mode is used there exists the problem of enabling buffers The buffered mode will structure the 8259 to send an enable signal on SP EN to enable the buffers In this mode whenever the 8259A s data bus outputs are enabled the SP EN output becomes active This modification forces the use of software programming to determine whether the 8259A is a master or a slave Bit ICW4 programs the buffered mode and bit 2 in ICW4 determines whether it is a master or a slave CASCADE MODE The 8259A be easily interconnected in a system of one master with up to eight slaves to handle up to 64 priority levels The master controls the slaves through the 3 line cascade bus The cascade bus acts like chip selects to the slaves during the INTA sequence In a cascade configuration the slave interrupt outputs are connected to the master interrupt request inputs When a slave request line is activated and afterwards acknowledged the master will enable the corresponding slave to release the device routine address during bytes 2 and 3 of INTA Byte 2 only for 8086 8088 The cascade bus lines are normally low and will contain the slave address code from the trailing edge of the first INTA pulse to the trailing edge of the third pulse Each 82594 in the system must follow a separate initialization sequence and can be programmed to work in a diffe
36. 7 0000 230 0000 230D 0000 230F 0000 2310 2E E9 cc FA 2E E9 cc FA 2E E9 cc 8B B9 8A 9A 46 E2 FB CF 8D 7 8D 97 8D 87 F2 11 04 00 F6 16 55 21 00 16 66 21 00 16 77 21 00 DISP 00 L1 00 00 FE LEA DX MSG5 JMP DISP INT 03 ORG 2260H INT6 ISR CLI LEA DX MSG6 JMP DISP INT 03 ORG 2270H INT7 ISR CLI LEA DX MSG7 JMP DISP INT 03 ORG 2300H COMMON DISPLAY ROUTINE MOV SI DX FOR ALL ISRs MOV CX 011H MOV AL SI CALL FAR OFE00 0000H CALL ROUTINE TO INC SI DISPLAY THE MSGS LOOP 11 5 RETURN FROM INTERRUPT 64 OAD 8259A STUDY CARD USER MANUAL QUO 6 DEMONSTRATION PROGRAM FOR 8051 SERIES KITS 6A DEMONSTRATION PROGRAM FOR ESA 51E ESA51E Ver 4 00 TRAINER The following program demonstrates the Polled Mode operation of 8259 the program first initializes the 8259 for interrupts using 4 and OCW2 The interrupt output from the 8259 is connected to External interrupt INT1 of the micro controller The program also enables the INT1of the micro controller Select the interrupt number using 4 way dipswitch and press the push button switch to give the interrupt to 8259 now the 8259 will interrupt the Trainer The ISR of the INT1 will read the Interrupt Request Register of 8259 in Poll mode The program displays the corresponding interrupt number on Serial or on LCD depends on the mode of operation of the Trainer ADD
37. 811 8120 8123 8126 8127 8128 812 812 812F 8130 8133 8136 8137 8138 813B 813E 813F 8140 8143 8146 814B 8150 8155 815A 815B 21 C3 00 00 21 C3 00 00 21 C3 00 00 21 C3 00 00 21 C3 00 00 21 C3 00 00 21 C3 00 00 CD C3 49 53 45 54 00 49 5B 40 70 40 85 40 9A 40 AF 40 C4 40 D9 40 5B 14 52 20 52 45 52 81 81 81 81 81 81 81 81 81 81 81 81 81 81 OB 80 30 49 52 44 31 SUBRT 20 4E 55 OD 20 49 54 50 0A 49 LXI H MES1 JMP SUBRT NOP NOP LXI H MES2 JMP SUBRT NOP NOP LXI H MES3 JMP SUBRT NOP NOP LXI 54 JMP SUBRT NOP NOP LXI H MES5 JMP SUBRT NOP NOP LXI 56 JMP SUBRT NOP NOP LXI H MES7 JMP SUBRT NOP NOP CALL DISPM JMP UP MESO DB IRO IS INTERRUPTED ODH OAH OOH MES1 DB IR1 IS INTERRUPTED ODH OAH OOH OAD 8259A STUDY CARD USER MANUAL QUO 28 EXAMPLE 2 8160 8165 816 816F 8170 8175 817A 817F 8184 8185 818A 818F 8194 8199 819A 819F 81 4 81A9 81AE 81AF 81B4 81B9 81BE 81C3 81C4 81C9 81CE 81D3 81D8 81D9 81DE 81 81 8 81ED 53 45 54 00 49 53 45 54 00 49 53 45 54 00 49 53 45 54 00 49 53 45 54 00 49 53 45 54 00 49 53 45 54 00 20 52 45 52 20 52 45 52 20 52 45 52 20 52 45 52 20 52 45 52 20 52 45 52 20 52 45 49 52 44 32 49 52
38. 8259 STUDY CARD 1 INTRODUCTION Electro Systems Associates Private Limited ESA manufactures trainers for most of the popular microprocessors viz 8085 Z 80 8031 8086 88 68000 and 80196 ESA offers a variety of modules which can be interfaced to these trainers These modules can be effectively used for teaching training in the Laboratories The 8259 Study Card incorporates Intel s 8259A PIC Programmable Interrupt Controller The Study Card is designed to demonstrate the different modes of operation of 8259 This Manual presents the User about Functional description of 8259 implementation of the circuit and sample programs for 8259 2 DESCRIPTION OF THE CIRCUIT The 8259 Study Card allows the user to study the different modes of operation of 8259 by connecting it to different microprocessor controller trainers The interrupts to 8259 can be given from on board provision or from external sources through jumper selections The on board interrupt source uses a four way dipswitch to select the eight different interrupts and the push button switch is to give the interrupt For the onboard interrupts user has to place the jumpers JP1 to JP8 in the position 23 For external interrupt place the jumpers JP1 to JP8 at 12 position depends on the interrupt number The Study Card has got two 26 Pin J3 amp J4 and one 50 Pin P1 connectors for interfacing with different Trainers The user can find more details about 8259A i e Programmin
39. 9A STUDY CARD USER MANUAL NULI 2216 2219 2220 2221 2226 2229 2230 2231 2236 2239 2240 2241 2246 2249 2250 2251 2256 2259 225A 2260 2261 2266 2269 2270 2271 2276 9 2 9 2 9 2 9 2 9 2 9 2 9 61 8D 51 8D 41 8D 31 8D 21 8D 11 8D 01 00 16 00 16 00 16 00 16 00 16 00 16 00 26 39 4 72 85 21 21 21 21 21 21 ORG CLI LEA INT ORG CLI LEA INT ORG CLI LEA INT ORG CLI LEA INT ORG CLI LEA INT ORG CLI LEA DISP 03H 2220H DX MSG2 DISP 03H 2230H DX MSG3 DISP 03H 2240H DX MSG4 DISP 03H 2250H DX MSG5 DISP 03H 2260H DX MSG6 DISP 03H 2270H DX MSG7 DISP ISR ISR ISR ISR ISR ISR FOR FOR FOR FOR FOR FOR INTERRUPT2 INTERRUPT3 INTERRUPT4 INTERRUPT5 INTERRUPT6 INTERRUPT7 59 0000 2279 0000 227 0000 227 0000 2281 INT 03H 8B C2 DISP MOV AX DX 9A 13 00 00 FE CALL FAR 0 00 0013 cc INT 03H 5C DEMONSTRATION PROGRAM FOR ESA 86E Ver 2 00 TRAINER Connect 26 Pin FRCs between the J3 amp J4 of the Study Card and J4 amp J6 of Trainer respectively The following demo Program Enables all the interrupts of 8259 Us
40. DEMONSTRATION PROGRAMS FOR MPS 85 3 TRAINER Connect the Study Card s J3 amp J4 connectors to Trainer s J3 amp J4 connectors using FRCs respectively EXAMPLE 1 The following program configures the 8259 to accept the all the interrupts from 0 to 8 User can give interrupt from the on board push button switch or from external sources For on board interrupts select the interrupt number by Dipswitch selection and press the push button to generate the interrupt Execute the Program in Serial mode of operation of the Trainer The program displays the corresponding interrupt number on the console or on serial monitor ADDRESSES OF 8259 ARE 90H AND 91H 8000 8002 8004 8006 8008 800A 800C 800E 8010 8011 8014 8100 8103 8106 8107 3E D3 3E D3 3E D3 3E D3 FB c3 DF 21 c3 00 00 DISPM EQU ORG 12 START MVI 90 OUT 81 MVI 91 OUT 00 MVI 91 OUT 20 MVI 90 OUT EI 11 80 555 JMP UP RST ORG 46 81 LXI 40 81 JMP NOP NOP 0BSBH DISPLAY ROUTINE ADDRESS TO DISPLAY MESSAGE ON SERIAL 8000H A 12H 90H A 81H 91H OOH 91H A 20H 90H 555 8100 50 SUBRT OAD 8259A STUDY CARD USER MANUAL QUO single edge triggerd mode call address interval 8 interrupt vector address Normal EOI for 80 85 mode for 8259 Non specific EOI command Routine to display the massage 27 8108 810 810 810 8110 8113 8116 8117 8118 811 811
41. DY CARD USER MANUAL DX 20AA AX DX 00 1 55 AL 31 00 1 50 DX 20 AX DX 00 1 55 2300 ISR FOR INTERRUPT 2 DX 20AA 00 1 55 AL 32 00 1 50 DX 20 AX DX 00 1 55 2350 ISR FOR INTERRUPT 3 DX 20AA FE00 1B55 AL 433 00 1 50 DX 20 AX DX 00 1 55 52 0000 2370 INT3 ORG 0000 2400 FA CLI 0000 2401 2E CS 0000 2402 8D 16 AA 20 LEA 0000 2406 BA C2 MOVW 0000 2408 9A 55 1B 00 FE CALLS 0000 240D BO 34 MOVB 0000 240F 9A 50 1B 00 FE CALLS 0000 2414 2E CS 0000 2415 8D 16 BA 20 LEA 0000 2419 BA C2 MOVW 0000 241B 9A 55 1B 00 FE CALLS 0000 2420 cc INT3 ORG 0000 2450 FA CLI 0000 2451 2E CS 0000 2452 8D 16 AA 20 LEA 0000 2456 BA C2 MOVW 0000 2458 9A 55 1B 00 FE CALLS 0000 245D BO 35 MOVB 0000 245F 9A 50 1B 00 FE CALLS 0000 2464 2E CS 0000 2465 8D 16 BA 20 LEA 0000 2469 BA C2 MOVW 0000 246B 9A 55 1B 00 FE CALLS 0000 2470 cc INT3 ORG 0000 2500 FA CLI 0000 2501 2E CS 0000 2502 8D 16 AA 20 LEA 0000 2506 BA C2 MOVW 0000 2508 9A 55 1B 00 FE CALLS 0000 250D BO 36 MOVB OAD JDO 8259A STUDY CARD USER MANUAL 2400 ISR FOR INTERRUPT 4 DX 20AA AX DX FE00 1B55 AL 34 00 1 50 DX 20 00 1 55 2450 ISR FOR INTERRUPT 5 DX 20AA FE00 1B55 AL 35 00 1 50 DX 20 AX DX 00 1 55 2500 ISR FOR INTERRUPT 6 DX 20AA 00 1 55 AL 36 53 0000 0000 00
42. ICW2 IN NO SINGL CASCADE 1 d gt MODE Y YES SNGL 1 ICW3 N NEEDED N i d 5 1 4 1 ICW4 READY TO ACCEPT INTERRUPT REQUESTS PDF created with pdfFactory Pro trial version www pdffactory com 16 OAD JDE 8259A STUDY CARD USER MANUAL N 7 D U ICWI AO D7 D6 55 D3 D2 1 m ADI 8259A STUDY CARD USER MANUAL D1 d IC4 1 ICW4 NEEDED 0 NO ICW4 NEEDED 1 SINGLE 0 CASCADE MODE L CALL ADDRESS INTERVAL I INTERVAL OF 4 0 OF 8 1 LEVEL TRIGGERED MODE 0 EDGE TRIGGERED MODE 7 5 OF INTERRUPT VECTOR ADDRESS MCS 80 85 MODE ONLY 17 0 ICW2 D7 D6 D5 D4 D3 D2 DI DO an 8 8259A STUDY CARD USER MANUAL 15 8 OF INTERRUPT VECTOR ADDRESS MCS80 85 MODE T7 13 OF INTERRUPT VECTOR ADDRESS 8086 8088 MODE 18 ICW3 MASTER DEVICE D7 D6 D5 D4 D3 D DI DO 57 56 55 54 2 a S0 12 IR INPUT HAS A SLAVE 111111 0 IR INPUT DOES NOT HAVE A SLAVE 1 ICW3 SLAVE DEVICE A0 D7 D6 D5 D4 D3 D2 DI DO SLAVE ID S OAD JDE 8259A STUDY CARD USER MANUAL Icw4 A0 D7 D6 05 DA D3 D DI DO OL uPM 0 5 80 85 MODE 1 AUTO E OI gt 0 NORMAL E OI 0 TX NON BUFFERED MODE 0 BUFFERED MODE SLAVE 1 BUFFERED
43. RESSES OF 8259 ARE F190 AND F191 ORG 8000H 8000 75 A0 F1 MOV P2 0F1H F190H ONE OF 8259 ADDRESSES 8003 78 90 MOV RO 90H 8005 74 17 A 17H ICW1 ICW4 SINGLE INTERVAL4 8007 F2 MOVX QRO A EDGE TRIGGERED INTERRUPT 8008 78 91 MOV RO 91H F191H ONE OF 8259 ADDRESSES 800A 74 02 MOV A 02H ICW4 8085 MODE 800 2 MOVX RO A 800D 74 00 MOV A 00H OCW1 ENABLE ALL INTERRUPTS 800F F2 MOVX RO A 8010 78 90 MOV 90 8012 D2 8A SETB TCON 2 SELECT EDGE TRIGGER FOR 8014 75 8 84 MOV 484 ENABLE INTERRUPT 8017 80 FE HERE SJMP HERE WAIT FOR THE INTERRUPT ORG OFFF3H ISR LOCATION FOR INT1 of TRAINER FFF3 02 81 00 LJMP 8100 JUMP TO 8100H ORG 8100H 8100 78 90 MOV 90 8102 74 A 0EH OCW3 SELECT THE POLLING MODE OF 8259 8104 F2 MOVX QRO A TO READ THE IR REGISTER 8105 E2 MOVX A QRO READ THE IR REGISTER FOR INT NUMBER 8106 54 07 ANL A 07H FIND THE INTERRUPT REQUEST NUMBER 8108 25 EO ADD A A ADD THE OFFSET TO JUMP LOCATION 810A 90 82 00 MOV DPTR 8200H 65 OAD JDE 8259A STUDY CARD USER MANUAL 8105 73 A DPTR 810E 02 00 03 LJMP 03H ORG 8200H 8200 41 13 AJMP INTO JUMP INTO ROUTINE 8202 41 1F AJMP JUMP INT1 ROUTINE 8204 41 2B AJMP INT2 JUMP INT2 ROUTINE 8206 41 37 AJMP INT3 JUMP INT3 ROUTINE 8208 41 43 AJMP INT4 JUMP INT4 ROUTINE 820A 41 4F AJMP INT5 JUMP INT5 ROUTINE 820C 41 5B AJMP INT6 JUMP INT6 ROUTINE 820E 41 67 AJMP INT7
44. S MOVW ES MOVW ES MOVW ES MOVW ES MOVW ES MOVW ES OAD 8259A STUDY CARD USER MANUAL NULI 2000H CLEAR INTERRUPT FLAG AX 0000 INITIALIZE SEGMENT CX AX REGISTERS ES AX SS AX SP 3000 INITIALIZE SP INTERRUPT VECTOR INITIALIZATION 0120 42200 INTO VECTOR ADDRESS 0122 40000 SLAVE 0124 42250 INT1 VECTOR ADDRESS 0126 40000 SLAVE 0128 42300 INT2 VECTOR ADDRESS 012A 40000 SLAVE 012C 42350 INT3 VECTOR ADDRESS 49 0000 203F 0000 2045 0000 2046 0000 204C 0000 204D 0000 2053 0000 2054 0000 205A 0000 205 0000 2061 0000 2062 0000 2068 0000 2069 0000 206 0000 2070 0000 2076 0000 2077 0000 207D 0000 2080 0000 2082 0000 2083 0000 2086 0000 2088 0000 2089 0000 208 0000 208 0000 208 0000 208 0000 2091 0000 2092 0000 2095 0000 2097 0000 2098 C7 26 C7 26 C7 26 C7 26 C7 26 C7 26 C7 26 C7 26 C7 BA BO EE BA BO EE BO EE BO EE BO EE BA BO EE BA 06 06 06 06 06 06 06 06 06 90 15 92 48 00 05 00 F4 15 F6 2E 30 32 34 36 38 3A 3C 3E 00 00 01 01 01 01 01 01 01 01 01 00 00 00 50 00 00 00 50 00 00 24 00 24 00 25 00 25 00 MOVW ES MOVW ES MOVW ES MOVW ES MOVW ES MOVW ES MOVW ES MOVW ES MOVW 012E 0000 0130 2400 0132 0000 0134
45. TED OAH OOH INTERRUPTED OAH OOH 39 81B4 81B9 81BE 81 3 81C4 81C9 81CE 81D3 81D8 81D9 81DE 81E3 81E8 81ED EXAMPLE 2 4 55 OD 20 4E 55 OD 20 4E 55 OD 54 50 0 49 54 50 0 49 54 50 0 56 DB IR6 IS INTERRUPTED ODH OAH OOH MES7 DB IR7 IS INTERRUPTED 0ODH 0AH 00H The following Program configures 8259 to accept 8 interrupt requests from onboard sources Keep the dip switch SW1 for corresponding interrupt Execute the program from 8000H Then press the push button switch Execute the program in KEYBOARD mode only RDKBD 8000 8002 8004 8006 8008 800A 800C 800E 8010 8011 8200 8203 8206 8207 8208 820B OAD 8259A STUDY CARD USER MANUAL NULI 3E D3 3E D3 3E D3 3E D3 FB c3 CD c3 00 00 CD c3 12 90 82 91 00 91 20 90 11 3E 5B 3E 66 80 82 82 82 82 START SSS ORG MVI OUT MVI OUT MVI OUT MVI OUT EI JMP ORG CALL NOP NOP CALL JMP EQU 8000H A 12H 90H A 82H 91H A 00H 91H A 20H 90H sss 8200H RO so RO 51 0514H Routine to read the keys from hex key pad single edge triggerd mode call address interval 8 interrupt vector address Normal EOI for 80 85 mode for 8259 Non specific EOI command 40 OAD 8259A STUDY CARD USER MANUAL QO 820E 820F 8210 8213 8216 8217 8218 821B 821E 821F 8220 8223 8
46. TERRUPTS MASKE INITIALIZATION SEQUENCE FOR MASTER INTERRUPT CONTROLLER 0000 20A1 0000 20A4 0000 20A6 0000 20A7 0000 20AA 0000 20AC 0000 20AD 0000 20AF 0000 20B0 0000 20B2 0000 20B3 0000 20B5 0000 20 6 0000 20 7 BO EE BA BO EE BO EE BO EE BO EE FB E9 F4 FF MOV 15 MOV OUT F6 FF MOV 48 MOV OUT 01 OUT OD MOV OUT FE MOV OUT STI FD FF HERE JMP ORG DX OFFF4H AL 15H DX AL DX OFFF6H AL 48H DX AL AL 01 DX AL AL DX AL AL OFEH DX AL HERE 2100H 2 CAS MODE ICW4 NEED EDGE TRIGGERED INT ICW2 BASE ADDRESS 72d ICW3 MASTER IRO HAS A SLAVE ON ICW4 MASTER 86 88 MODE AEOI OCW1 ALL BUT IRO MASKED SET INTERRUPT FLAG MESSAGES FOR ISRs 0000 2100 20 20 49 4E 54 MSGO DB 20H 20H 0AH INTO OCCURRED OAH OOH 0000 2106 30 20 4F 43 43 55 0000 210 52 52 45 44 OA OD OAD 8259A STUDY CARD USER MANUAL NULI 57 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 2112 2113 2119 211F 2125 2126 212 2132 2138 2139 213F 2145 214B 214 2152 2158 215E 215F 2165 216B 2171 2172 2178 217E 2184 2185 218B 2191 2200 2201 2206 2209 2210 2211 00 20 31 52 00 20 32 52 00 20 33 52 00 20 34 52
47. command word that must be issued to the 8259A before returning from a service routine EOI command An EOI command must be issued twice if in the Cascade mode once for the master and once for the corresponding slave There two forms of EOI command Specific and non specific When the 8259A is operated in modes which preserve the fully nested structure it can determine which IS bit to reset on EOI When a Non Specific EOI command is issued the 8259A will automatically reset the highest IS bit of those that are set since in the fully nested mode the highest IS level was necessarily the last level acknowledged and serviced A non specific EOI can be issued with OCW2 EOI 1 SL 0 R20 When a mode is used which may disturb the fully nested structure the 8259A may no longer be able to determine the last level acknowledged In this case a Specific End of interrupt must be issued which includes as part of the command the IS level to be reset A specific EOI can be issued with OCW2 1 1 SLZI 0 and LO L2 is the binary level of the IS bit to be reset It should be noted that an IS bit that is masked by an IMR bit will not be cleared by a non specific EOI if the 8259A is in the Special Mask Mode AUTOMATIC END OF INTERRUPT AEOI MODE If AEOI 1 in ICWA then the 8259A will operate in AEOI mode continuously until reprogrammed by ICW4 In this mode the 8259A will automatically perform a non specific EOI operation at the trailing edge o
48. ddress lines 11 OAD JDE 8259A STUDY CARD USER MANUAL THE CASCADE BUFFER COMPARATOR This function block stores and compares the IDs of all 8259A s used in the system The associated three I O pins 50 2 are outputs when the 8259A is used as a master and are inputs when the 8259A is used as a slave As a master the 8259A sends the ID of the interrupting slave device onto the CASO 2 lines The slave thus selected will send its preprogrammed subroutines address onto the Data Bus during the next one or two consecutive INTA pulses See section Cascading the 8259A INTERRUPT SEQUENCE The powerful features of the 8259A in a microcomputer system are its programmability and the interrupt routine address capability The latter allows direct or indirect jumping to the specific interrupt routine requested without any polling of the interrupting devices The normal sequence of events during an interrupt depends on the type of CPU being used The events occur as follows in a MCS 80 85 system 1 One or more of the INTERRUPT REQUEST lines IR7 0 are raised high setting the corresponding IRR bit s 2 8259A evaluates these requests and sends an INT to the CPU if appropriate 3 CPU acknowledges the INT and responds with INTA pulse 4 Upon receiving an INTA from the CPU group the highest priority ISR bit is set and the corresponding IRR bit is reset The 8259A will also release a CALL instruction code 11
49. de which is set by R 1 SL 0 EOI 0 and cleared SPECIFIC ROTATION specific Priority The programmer can change priorities by programming the bottom priority and thus fixing all other priorities 1 if IR5 is programmed as the bottom priority device then IR6 will have the highest one The Set Priority command is issued in OCW2 where R 1 SL 1 LO L2 is the binary priority level code of the bottom priority device Observe that in this mode internal status is updated by software control during OCW2 However it is independent of the End of interrupt EOI command also executed by OCW2 Priority changes can be executed during an EOI in OCW2 R 1 SL 1 EOI 1 and LO L2 IR level to receive bottom priority INTERRUPT MASKS Each Interrupt Request input can be masked individually by the interrupt Mask Register IMR programmed through OCWI Each bit in the IMR masks one interrupt channel if it is set 1 Bit 0 masks IRO Bit 1 masks IRI and so forth Masking an IR channel does not affect the other channels operation SPECIAL MASK MODE Some applications may require an interrupt service routine to dynamically alter the system priority structure during its execution under software control For example the routine may wish to inhibit lower priority requests for a portion of its execution but enable some of them for another portion The difficulty here is that if an interrupt Request is acknowledged and an End of Interrupt command d
50. e to display message on serial 8000H A 12H single edge triggerd mode 90H call address interval 8 A 81H interrupt vector address 91H 00 Normal EOI for 80 85 91H mode for 8259 A 20H Non specific EOI command 90H SSS 3 8100H H MESO Routine to display the massage SUBRT 51 38 810 810 810F 8110 8113 8116 8117 8118 811B 811E 811F 8120 8123 8126 8127 8128 812B 812E 812F 8130 8133 8136 8137 8138 813B 813E 813F 8140 8143 8146 814B 8150 8155 815A 815B 8160 8165 816A 816F 8170 8175 817A 817F 8184 8185 818A 818F 8194 8199 819A 819F 81 4 81A9 81AE 81AF 40 70 40 85 40 9A 40 AF 40 C4 40 D9 40 81 81 81 81 81 81 81 81 81 81 81 81 81 SUBRT 20 4E 55 OD 20 4E 55 OD 20 4E 55 OD 20 4E 55 OD 20 4E 55 OD 20 NOP NOP LXI NOP NOP LXI NOP NOP LXI NOP NOP LXI NOP NOP LXI NOP NOP LXI NOP NOP CALL JMP SUBRT H MES2 SUBRT H MES3 SUBRT H MES4 SUBRT H MES5 SUBRT H MES6 SUBRT H MES7 SUBRT DISPM UP MESO DB MES1 DB MES2 DB MES3 DB 54 DB 55 DB OAD 8259A STUDY CARD USER MANUAL NULI IRO IRI IR2 IR3 IR4 IR5 Is Is Is Is Is Is INTERRUPTED OAH OOH INTERRUPTED OAH OOH INTERRUPTED OAH OOH INTERRUPTED OAH OOH INTERRUP
51. ed The output data bus will contain the IMR whenever RD is active and AO 1 1 Polling overrides status read when P 1 RR 1 in OCW3 EDGE AND LEVEL TRIGGERED MODES This mode is programmed using bit 3 in ICWI If LTIM 0 an interrupt request will be recognized by a low to high transition on an IR input The IR input can remain high without generating another interrupt If LTIM 1 an interrupt request will be recognized by a high level on IR input and there is no need for an edge detection The interrupt request must be removed before the EOI Command is issued or the CPU interrupt is enabled to prevent a second interrupt from occurring The priority cell diagram shows a conceptual circuit of the level sensitive and edge sensitive input circuitry of the 8259A Be sure to note that the request latch is a transparent D type latch 24 OAD JDE 8259A STUDY CARD USER MANUAL In both the edge and level triggered modes the IR inputs must remain high until after the falling edge of the first INTA If the IR input goes low before this time a DEFAULT IR7 will occur when the CPU acknowledges the interrupt This can be a useful safeguard for detecting interrupts caused by spurious noise glitches on the IR inputs To implement this feature the IR7 routine is used for clean up simply executing a return instruction thus ignoring the interrupt If IR7 is needed for other purposes a default IR7 can still be detected by reading the
52. er can give interrupts to 8259 using onboard dipswitch and push button Execute the program from 2000H in Serial mode only The program will be continuously polling for the interrupt so press reset on trainer to come out of program ADDRESSES 8259 FFC8 AND FFCA 0000 2000 0000 2003 0000 2005 0000 2007 0000 2009 0000 200C 0000 200F 0000 2012 0000 2014 0000 2017 0000 201A 0000 201C 0000 201F 0000 2022 0000 2024 0000 2027 0000 202A 0000 202C 0000 202F 0000 2032 0000 2034 0000 2037 0000 203A 0000 203C ORG 2000H B8 00 00 MOV AX 0000H 8E C8 MOV CS AX 8E CO MOV ES AX 8E DO MOV SS AX BC 00 30 MOV SP 3000H BE 20 01 MOV SI 0120H INTO VECTOR ADDRESS B8 00 22 MOV AX 2200H 0120H IS THE BASE OF 89 04 MOV SI AX INT VECTOR TABLE 83 C6 02 ADD SI 02H B8 00 00 MOV AX 0000H 89 04 MOV SI AX 83 C6 02 ADD SI 02H INT1 VECTOR ADDRESS B8 10 22 MOV AX 2210H 89 04 MOV SI AX 83 C6 02 ADD SI 02H B8 00 00 MOV AX 0000H 89 04 MOV SI AX 83 C6 02 ADD SI 02H INT2 VECTOR ADDRESS B8 20 22 MOV AX 2220H 89 04 MOV SI AX 83 C6 02 ADD SI 02H B8 00 00 MOV AX 0000H 89 04 MOV SI AX 83 C6 02 ADD SI 02H INT3 VECTOR ADDRESS 60 OAD 8259A STUDY CARD USER MANUAL NULI 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 OAD 82
53. et the Special Mask Mode When ESMM 0 the SMM bit becomes a don t care SMM Special Mask Mode If ESMM 1 and SMM 1 the 8259A will enter Special Mask Mode If 1 SMM 0 the 8259A will revert to normal mask mode When ESMM 0 SMM has no effect FULLY NESTED MODE This mode is entered after initialization unless another mode is programmed interrupt requests are ordered in priority form 0 through 7 0 highest When an interrupt is acknowledged the highest priority request is determined and its vector placed on the bus Additionally a bit of the interrupt Service register ISO 7 is set End of interrupt EO1 command immediately before returning from the service routine or if AEO1 Automatic End of Interrupt bit is set until the trailing edge of the last INTA While the bit IS set all further interrupts of the same or lower priority are inhibited While higher levels will generate an interrupt Which will be 21 OAD JDE 8259A STUDY CARD USER MANUAL acknowledged only if the microprocessor internal interrupt enable flip flop has been re enabled through software After the initialization sequence IRO has the highest priority and IR7 the lowest Priorities can be changed as will be explained in the rotating priority mode END OF INTERRUPT EOD The in Service IS bit can be reset either automatically following the trailing edge of the last in sequence INTA pulse when AEOI bit in ICWI is set or by a
54. f the last interrupt acknowledge pulse third pulse in MCS 80 85 second in iAPX 86 Note that from a system standpoint this mode should be used only when a nested multilevel interrupt structure is not required within a single 8259A The AEOI mode can only be used in a master 8259 and not a slave AUTOMATIC ROTATION Equal Priority Devices In some applications there are a number of interrupting devices of equal priority In this mode a device after being serviced receives the lowest priority so a device requesting an interrupt will have to wait in the worst case until each of 7 other devices are serviced at most once For example if the priority and service status 1s Before Rotate IRA the highest priority requiring service IS Status 167 156 155 154 193 152 151 ISO 0 1 0 1 0 10 0 10 Priority Status Lowest Priority Highest Priority TX 193 After Rotate IR4 was serviced all other priorities rotated correspondingly IS Status 167 156 155 154 153 152 151 ISO 0 1 010 10 10 0 10 Priority Status Lowest Priority Highest Priority 22 OAD JDO 8259A STUDY CARD USER MANUAL 2 1 0 7 6 5 4 3 There two ways to accomplish Automatic Rotation using OCW2 the Rotation Non specific EOI Command R 1 SL 0 EOI 1 and Rotate in Automatic EOI Mo
55. g Pin details etc in the next section Default factory settings for onboard interrupts for MPS 85 3 ESA 85 2 ESA 31 51 ESA 51E and ESA 86E Trainers are as follows 1 1 23 JP6 23 JP2 23 JP7 23 JP3 23 JP8 23 JP4 23 JP9 23 JP5 23 JP10 12 JP11 JP12 amp JP13 must be left open OAD JDE 8259A STUDY CARD USER MANUAL Default factory settings for onboard interrupts for ESA 86 88 2 3 Trainers as follows JP1 23 JP6 23 2 23 JP7 23 JP3 23 JP8 23 JP4 23 JP9 12 JP5 23 10 12 JP11 JP12 amp JP13 must be Closed 4 Way Dip Switch selection for different interrupts are as follows SWI 4WAY 3 2 1 Interrupt OFF OFF OFF IRO OFF ON OFF OFF IR2 OFF ON ON IR3 ON OFF OFF IRA ON OFF ON IRS ON ON OFF IR6 ON ON ON IR7 OAD JDO 8259A STUDY CARD USER MANUAL 8259 PROGRAMMABLE INTERRUPT CONTROLLER 8259A 8259 2 THEORY 86 IAPX 88 Compatible MCS 80 MCS 85Compatible Eight Level Priority Controller Expandable to 64 Levels Programmable Interrupt Modes Individual Request No Clocks 28 Pin Dual In Line Package The Intel 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU It is cascadable for up to 64 vectored priority interrupts without additional circuitry It is packaged in a 28 pin DIP uses NMOS technology and requires a single 5V supply Circuitry is static requiring no clock inp
56. ge Triggered Mode or just by a high level on an IR input Level Triggered Mode INTA 26 1 Interrupt Acknowledge This pin is used to enable 8259A interrupt vector data onto the data bus by a sequence of interrupt acknowledge pulses issued by the CPU Ao 27 1 AO Address Line This pin acts in conjunction with the CS WR and RD pins It is used by the 8259A to decipher various Command Words the CPU writes and status the CPU wishes to read It is typically connected to the CPU Ao address A for 86 88 FUNCTIONAL DESCRIPTION Interrupts in Microcomputer Systems Microcomputer system design requires that I O devices such as keyboards displays sensors and other components receive servicing in an efficient manner so that large amounts of the total system tasks can be assumed by the microcomputer with little or no effect on through put The most common method of servicing such devices is the Polled approach This is where the processor must test each device in sequence and in effect ask each one if it needs servicing It is easy to see that a large portion of the main program is looping through this continuous polling cycle and that such a method would have a serious detrimental effect on system through put thus limiting the tasks that could be assumed by the microcomputer and reducing the cost effectiveness of using such devices A more desirable method would be one that would allow the microprocess
57. he 8080 8085A and 8086 input levels INTA INTERRUPT ACKNOWLEDGE INTA puises will cause the 8259A to release vectoring information onto the data bus The format of this data depends on the system mode of the 8259A DATA BUS BUFFER This 3 state bi directional 8 bit buffer is used to interface the 8259 to the system Data Bus Control words and status information are transferred through the Data Bus Buffer READ WRITE CONTROL LOGIC The function of this block is to accept OUTPUT commands from the CPU It contains the initialization Command Word ICW registers and Operation Command Word OCW registers which store the various control formats for device operation This function block also allows the status of the 8259A to be transferred onto the Data Bus CS CHIP SELECT A LOW on this input enables the 8259A reading or writing of the chip will occur unless the device is selected WR WRITE A LOW on this input enables the CPU to write control words ICWs OCWs to the 8259A RD READ A LOW on this input enables the 8259A to send the status of the interrupt Request Register IRR In Service Register ISR the Interrupt Mask Register IMR or the interrupt level onto the Data Bus Ao This input signal is used in conjunction with WR and RD signals to write commands into the various command registers as well as reading the various status registers of the chip This line can be tied directly to one of the a
58. id not reset its IS bit 1 while executing a service routine the 8259A would have inhibited all lower priority requests with no easy way for the routine to enable them That is where the Special Mask Mode comes in In the special Mask Mode when a mask bit is set in OCWI it inhibits further interrupts at that level and enables interrupts from all other levels lower as well as higher that are not masked Thus any interrupts may be selectively enabled by loading the mask register The special Mask Mode is set by OCW3 where SSMM 1 SMM 1 and cleared where SSMM 1 SMM 0 POLL COMMAND In this mode the INT output is not used or the microprocessor internal interrupt Enable flip flop is reset disabling its interrupt input Service to devices is achieved by software using a Poll command The Poll command is issued by setting P 1 in OCW3 The 8259A treats the next pulse to the 8259A 1 RD 0 CS 0 as an interrupt acknowledge sets the appropriate IS bit if there is a request and reads the priority level Interrupt is frozen from WR to RD The word enabled onto the data bus during RD is D7 D6 D5 D4 D3 D2 DI D0 23 OAD JDE 8259A STUDY CARD USER MANUAL 1 pu Em HE meee W2 WI WO WO0 W2 Binary code of the highest priority level requesting service 1 Equal to a 1 if there 18 an interrupt This mode is useful if there is a routine command c
59. nd so on H MESO Routine to display messages DISPM UP H MES1 DISPM UP H MES2 DISPM UP H MES3 DISPM UP H MES4 DISPM UP H MES5 DISPM UP 36 8157 815A 815D 8160 8163 8166 8169 816E 8173 8178 817D 817E 8183 8188 818D 8192 8193 8198 819D 81A2 81A7 81A8 81AD 81B2 81B7 81BC 81BD 81C2 81C7 81cc 81D1 81D2 81D7 81DC 81 1 81 6 21 CD c3 21 CD c3 49 53 45 54 00 49 53 45 54 00 49 53 45 54 00 49 53 45 54 00 49 53 45 54 00 49 53 45 54 00 ET7 5B 20 FC 5B 20 52 20 52 45 52 20 52 45 52 20 52 45 52 20 52 45 52 20 52 45 52 20 52 45 81 81 81 81 30 49 52 44 31 49 52 44 32 49 52 44 33 49 52 44 34 49 52 44 35 49 52 44 20 4E 55 OD 20 4E 55 OD 20 4E 55 OD 20 4E 55 0 20 4E 55 OD 20 4E 55 OD 49 54 50 0A 49 54 50 0A 49 54 50 0A 49 54 50 0A 49 54 50 0A 49 54 50 0A R6 R7 LXI CALL LXI CALL MESO MES1 MES2 MES3 MES4 MESS OAD 8259A STUDY CARD USER MANUAL QUO H MES6 DISPM UP H MES7 DISPM UP DB IRO DB DB IR2 DB IR3 DB IR4 DB IR5 Is Is Is Is Is Is INTERRUPTED OAH OOH INTERRUPTED OAH OOH INTERRUPTED OAH OOH INTERRUPTED OAH OOH INTERRUPTED OAH OOH INTERRUPTED
60. ommon to several levels so that the INTA sequence is not needed saves ROM space Another application is to use the poll mode to expand the number of priority levels to more than 64 READING THE 8259A STATUS The input status of several internal registers can be read to update the user information on the system following registers can be read via OCW3 IRR and ISR or OCW1 Interrupt Request Register IRR 8 bit register which contains the levels requesting an interrupt to be acknowledged The highest request level is reset from the IRR When an Interrupt is acknowledged not affected by IMR In Service Register ISR 8 bit register which contains the priority levels that are being serviced The ISR is updated when an End of Interrupt Command is issued Interrupt Mask Register 8 bit register which contains the interrupt request lines which are masked The IRR can be read when prior to the RD pulse a Read Register Command is issued with OCW3 RR 1 RIS 0 The ISR can be read when prior to the RD pulse a Read Register Command is issued with OCW3 RR 1 RIS 0 There is need to write OCW3 before every status read operation as long as the status read corresponds with the previous one 1 the 8259A remembers whether the IRR or ISR has been previously selected by the OCW3 This is not true when poll is used After initialization the 8259A is set to IRR For reading the IMR no OCW3 is need
61. or to be executing its main program and only stop to service peripheral devices when it is told to do so by the device itself In effect the method would provide an external asynchronous input that would inform the processor that it should complete whatever instruction is currently being executed and fetch a new routine that will service the requesting device Once this servicing is complete however the processor would resume exactly where it left off This method is called interrupt It is easy to see that system throughput would drastically increase and thus more tasks could be assumed by the microcomputer to further enhance its cost effectiveness The Programmable interrupt Controller PIC functions as an overall manager in an interrupt Driven system environment It accepts requests from the peripheral equipment determines which of the incoming requests is of the highest importance priority ascertains whether the incoming request has a higher priority value than the level currently being serviced and issues an interrupt to the CPU based on this determination Each peripheral device or structure usually has a special program or routine that is associated with its specific functional or operational requirements this 1s referred to as a service routine PIC after issuing an interrupt to the CPU must somehow input information into the CPU that can point the Program Counter to the service routine associated with the requesting de
62. rammed as byte 2 of the initialization sequence As A 5 is enabled onto the bus Content of Third Interrupt Vector Byte D7 D6 D5 D4 D3 D2 D1 DO 15 Al4 A13 Al2 All A10 9 8 86 88 IAPX 86 mode is similar to MCS 80 mode except that only two interrupt acknowledge cycles are issued by the processor and no CALL opcode is sent to the processor The first interrupt acknowledge cycle is similar to that 13 OAD JDO 8259A STUDY CARD USER MANUAL of MCS 80 85 systems in that the 8259A uses it to internally freeze the state of the interrupts for priority resolution and as a master it issues the interrupt code on the cascade lines at the end of the INTA pulse On this first cycle it does not issue any data to the processor and leaves its data bus buffers disabled On the second interrupt acknowledge cycle in IAPX 86 mode the master or slave if so programmed will send a byte of data to the processor with the acknowledged interrupt code composed as follows note the state of the ADI mode control is ignored and A5 A are unused in iAPX 86 mode Content of Interrupt Vector Byte for IAPX 86 System Mode D7 D6 D5 D4 D3 D2 DI D0 87 7 6 5 T3 1 1 1 6 T7 T6 5 3 1 1 0 IRS 7 6 5 T4 T3 1 0 1 IR4 7 6 5 T4 T3 I 0 0 IR3 T7 T6 T5 T4 T3 0 1 1 IR2 7 6 5 T3 0 1 0 IRI T7 T6 T5 T4 T3
63. rent mode An EOI command must be issued twice once for the master and once for the corresponding slave An address decoder is required to active the Chip Select CS input of each 8259 25 OAD JDE 8259A STUDY CARD USER MANUAL The cascade lines of the Master 8259 activated only for slave inputs non slave inputs leave the cascade line inactive low 3 0 INSTALLATION AND CONFIGURATION The Connector details for connecting the Study Card to different Trainers are mentioned below CONNECTORS ON TRAINER CONNECTORS STUDY CARD ADAPTER CONNECTORS ON TRAINER STUDY CARD J3 26 PIN J3 26 PIN MPS 85 3 14 26 PIN J4 26 PIN ESA 85 2 P1 50 PIN P1 50 PIN J1 50 PIN 50 PIN J3 26 PIN J3 26 PIN ESA 86 88 2 3 J2 50 PIN J2 50 PIN 14 26 PIN J4 26 PIN J6 26 PIN J3 26 PIN ESA 86E Ver 2 00 J7 26 PIN 4 J4 26 PIN P1 26 PIN J3 26 PIN ESA 51E 14 P3 50 P2 26 J4 26 PIN ESA 51E Ver 4 00 J4 26 PIN 13 26 76 26 PIN J4 26PIN External Study Card Adapter is required to connect the Study Card with the Trainer Connect the Study Card by following the above mentioned connectors with FRCs respectively Switch Off Power to the Trainer while connecting the Study Card Press Reset after giving power to the Trainer 26 OAD JDE 8259A STUDY CARD USER MANUAL 4 DEMONSTRATION PROGRAM FOR 8085 SERIES KITS 4A
64. umper JP1 to JP7 at 12 positions on the Study Card DISPM EQU OB5BH ORG 8000H 8000 3E 80 MVI A 80H Configure 8255 all 8002 D3 43 OUT 43H ports O P 8004 3E 16 MVI A 16H Single edge triggerd mode call address interval 4 8006 D3 90 OUT 90H 8008 3E 81 MVI A 81H Interrupt vector address 800A D3 91 OUT 91H 800C 3E C5 MVI A 0C5H Fix IR5 as bottom priority 800E D3 90 OUT 90H by set priority command in OCW2 8010 FB EI 8011 3E FF MVI A 0FFH Send all IRO to IR7 high at a 35 OAD JDE 8259A STUDY CARD USER MANUAL 8013 8100 8103 8104 8107 8108 810 810 810F 8110 8113 8114 8117 8118 811B 811 811 8120 8121 8124 8127 812 812D 8130 8133 8136 8139 8136 813F 8142 8145 8148 814B 814E 8151 8154 D3 c3 00 c3 00 c3 00 c3 00 c3 00 c3 00 c3 00 C3 00 DF 21 CD C3 21 CD C3 21 CD C3 21 CD C3 21 CD C3 21 CD C3 40 21 2A 33 3C 45 4E 57 60 69 5B 20 7E 5B 20 93 5B 20 A8 5B 20 BD 5B 20 D2 5B 20 81 81 81 81 81 81 81 81 UP 81 OB 81 81 OB 81 81 OB 81 81 OB 81 81 OB 81 81 OB 81 R1 R2 R3 R4 R5 OUT 4 8100 RO R1 R2 R3 R4 R5 R6 R7 LXI CALL LXI CALL LXI CALL LXI CALL LXI CALL JMP LXI CALL OAD 8259A STUDY CARD USER MANUAL QUO OH time Interrupt vector address for IRO Interrupt vector address for a
65. ut The 8259A is designed to minimize the software and real time overhead in handling multi level priority interrupts It has several modes permitting optimization for a variety of system requirements The 8259 is fully upward compatible with the Intel 8259 Software originally written for the 8259 will operate the 8259A equivalent modes MCS 80 85 Non Buffered Edge Triggered Pin Configuration WR C 27 RD 25 E INTA 7 15 24 6 23 7 8259 22 5 D4 C 02 EJ m4 scm n L3 19 mi po 11 18 7 Ten caso 12 17 INT CASI C SP EN GND CAS2 OAD JDE 8259A STUDY CARD USER MANUAL AD VO Data Bus Bi directional Read Input rite Input Command Select Address Chip Select 52 CASO Cascade lines SP EN Slave Program Enable Buffer INT Interrupt Output INTA Interrupt Acknowledge Input TRO 7 Interrupt Request Inputs 8259A STUDY CARD USER MANUAL Block Diagram INTA INT EK p p Dat CONTROL LOGIC TD lt Bus Buffer o Read In Priority Interrup 4 IRO WR write service Resolver t request IRI 9 logic Reg reg IRR 4 Table 1 Pin Description ISR 14 183 R4 CS lt IRS IR6 CASO 4 M R7 Cascade CAS 4 CAS Compar ator INTERRUPT MASK REG A IR SP my f um x Internal bus
66. vice This pointer is an address in a vectoring table and will often be referred to in this document as vectoring data OAD JDE 8259A STUDY CARD USER MANUAL CPU RAM dum MEL lt 1 N iy AD VO Interrupt Method 8259A STUDY CARD USER MANUAL RAM Polled Method The 8259A is a device specifically designed for use in real time interrupt driven microcomputer systems It manages eight levels or requests and has built in features for expandability to other 8259A s up to 64 levels It is programmed by the system s software as an I O peripheral A selection of priority modes is available to the programmer so that the manner in which the requests are processed by the 8259A can be configured to match his system requirements The priority modes can be changed or reconfigured dynamically at any time during the main program This means that the complete interrupt structure can be defined as required based on the total system environment OAD JDE 8259A STUDY CARD USER MANUAL Data D Do Bus Buffer Read write logic CS _ puc Cascade CAS 44 Buffer CAS2 Compar ator RD gt WR 0 SP EN bus Figure 4a 8259A Block Diagram INTA INT CONTROL LOGIC In service Reg ISR Priority Resolver 1 Interrup t request reg IRR IR2 IRO
67. ytes and the CAS lines will look like an interrupt level 7 was requested INTERRUPT SEQUENCE OUTPUTS 12 OAD JDE 8259A STUDY CARD USER MANUAL MCS 80 MCS 85 This sequence is timed by three INTA pulses During the first INTA pulse the CALL opcode is enabled onto the data bus Content of First Interrupt Vector Byte D7 D6 D5 D4 D2 D1 DO CALLCODE 9 0 1 0 1 During the second INTA pulse the lower address of the appropriate service routine is enabled onto the data bus When interval 4 bits 5 are programmed while are automatically inserted by the 8259A When interval 8 only and A are programmed while are automatically inserted Content of Second Interrupt Vector Byte IR INTERVAL 4 D7 D6 55 D4 D3 D2 D1 DO 7 A7 5 1 1 1 0 0 6 A7 A6 A5 I I 0 0 0 5 7 A5 1 0 1 0 0 4 A7 5 1 0 0 0 0 3 7 A5 0 1 1 0 0 2 A7 5 0 1 0 0 0 1 A7 A5 0 0 1 0 0 0 7 5 0 0 0 0 0 INTERVAL 8 D7 D6 D5 D4 D3 D2 D1 DO 7 A7 1 1 1 0 0 0 6 A7 1 1 0 0 0 0 5 7 6 1 0 1 0 0 0 4 A7 6 1 0 0 0 0 0 3 7 6 0 1 1 0 0 0 2 7 6 0 1 0 0 0 0 1 7 6 0 0 1 0 0 0 0 7 6 0 0 0 0 0 0 During the third pulse the higher address of the appropriate service routine which was prog

8259 STUDY CARD USER MANUAL - Electro Systems Associates

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