Registers - Jérôme Saint
Contents
1. nN ER TH a W 4 n L 2 UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTBELIARD System architecture utom Nicolas Lacaille UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Computer system is made up of gt Microprocessor 7 Clock gt Memory For each cycle processor gt Fetch an instruction from memory program gt Execute instruction Instruction can do 7 Data processing gt Move data from to memory gt Branch to an other address in memory UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTBELIARD Since a microprocessor can only move data to from memory external communication can only be done with special memory device Interfaces exchange data with external peripherals processor need interfaces 7 Processor side interface are memory device called I O port or memory mapped registers gt User side interface are specialized device for specific peripheral e Applications control peripheral through the port of interfaces exchange data control the device knowing the state of the device UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD m Interface Interface Control iL Ap 4 NZ External devices keyboard display UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Processor System Bus SDRAM Bridee 1 Memory bus ROM Per2. 32 interrupt request inputs Interrupt request must be HIGH level e VIC ORs vectored interrupt request to produce irq or fiq signal to the core e Each interrupt can be enable or disable e Each interrupt can be asserted by software Each interrupt is assigned to irq or line e Each interrupt 15 programmed with a priority on 4 bits 70 highest priority gt 15 lowest priority UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD interrupt request masking and selection SoftintClear IntEnableClear 31 0 31 0 E EBR 31 0 gt L status registers and FIQ generation 31 0 Rawintr IntSelect 31 0 31 0 PRIORITY LOGIC I VectIRQ31 1 Vect Addr31 I Fig 22 Block diagram of the Vectored Interrupt Controller UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Table 102 Summary of VIC registers VICIRQStatus VICFIQStatus VICRawintr VICIntSelect VICIntEnable VICIntEnCIr VICSottint ViCSoftintClear VICProtection VICSWPriorityMask VIC VectAddr VICVectAddr1 ViCVectAddr2 fa dan VIL VICVectPriority30 VICVectPriority31 ViCAddress Description IRQ Status Register This register reads out the state of those interrupt requests that are enabled and classified as IRQ FIQ Status Requests This register reads out the state of those interrupt requests that are enabled and classified as FIQ Raw Interrupt Status R
3. DLAB 0 amp 8 bits no Parity 1 Stop bit UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Table 387 UARTn Line Status Register U0LSR address 0xE000 C014 U2LSR 0xE007 8014 U3LSR 0xE007 C014 Read Only bit description Bit Symbol 0 Receiver Data Ready RDR 1 Overrun Error OE 2 Parity Error PE 3 Framing Error FE Value Description Reset Value 4 Break UnLSRO is set when the UnRBR holds an unread character 0 Interrupt and is cleared when the UARTn RBR FIFO is empty 0 UnRBR is empty UnRBR contains valid data The error condition is set as soon as it occurs An 0 UnLSR read clears UnLSR1 UnLSR1 is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full In this case the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost 0 Overun error status is inactive 5 Transmitter Overrun error status is active Holding Register Empty when the parity bit of a received character is in the wrong 0 THRE state a parity error occurs An UnLSR read clears UnLSR 2 6 Transmitter Time of parity error detection is dependent on UNFCRIO Empty Note A parity error is associated with the character at the top TEMT of the UARTn RBR FIFO 0 Parity error status is inactive Parity error status is active EmorinRX When the stop bit of a received character is a logic 0 a 0 FIFO framing error occurs
4. Bit 7 6 5 4 3 2 1 0 Symbol LED7 LED6 LED5 LED4 LED3 LED2 LED1 LEDO Default X X X X X X X X Remark The default value X is determined by the externally applied logic level normally logic 1 when used for directly driving LED with pull up to Vpp Table 5 1 Input register 1 description Bit 7 6 5 3 2 1 0 Symbol LED15 LED14 LED13 LED12 1 011 LED10 LED9 LED8 Default X X X X X X X X UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTBELIARD Table 10 150 to 1 53 LED selector registers bit description Legend default value Register Bit Value Description LSO LEDO to LED3 selector LSO 7 6 00 LED3 selected 5 4 00 LED2 selected 3 2 00 LED1 selected 1 0 00 LEDO selected 00 output is set high impedance LED off defau LS1 LED4 to LED7 selector 01 output is set LOW LED on EM 10 output blinks at PWMO rate Ei e 3 2 00 LED5 selected 11 output blinks at PWM1 rate 1 0 00 LED4 selected LS2 LED8 to LED11 selector LS2 7 6 00 LED11 selected 5 4 00 LED10 selected 3 2 00 LED9 selected 1 0 00 LED8 selected LS3 LED12 to LED15 selector 153 7 6 00 LED15 selected 5 4 00 LED14 selected 3 2 00 LED13 selected 1 0 00 LED12 selected UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD PCA9532 is connected to pin P0 27 SDAO and to pin PO 28 SCLO an I2C EPROM 15 also connected Initialization gt Power activation for I2CO PCONPO lt lt 7 7 Clock division
5. ONNEXI on 11 P0 00 has a pull down resistor enabled 31 30 P0 15MODE PORTO pin 15 on chip pull up down resistor control 00 UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Exemple Table 130 Pin function select register 0 PINSEL0 address 0xE002 C000 bit description PINSELO Pin Function when Function when 01 Function Function Reset name 00 when 10 when 11 value GPIO port 0 1 00 CANI TD1 01 0 Chip s pin NMZ UART3 RXD3 10 I2C1 SCLI ae CHIP LPC2478 48 UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD 5 general purpose 32 bits port e GPIO controller are located on the local bus for fast controlling PortO and Port can also be controlled by legacy control register on APB bus slow e PortO and Port2 can generate interrupts on individual change of individual pin e Each individual pin can be configured as Input or out put FIOxDIR e Each individual pin can be masked FIOxMASK for reading and writing read 0 and no effects on write UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Table 159 Summary of GPIO registers local bus accessible registers enhanced GPIO features Generic Name FIODIR FIOMASK FIOPIN FIOSET FIOCLR Description Fast GPIO Port Direction control register This register individually controls the direction of each port pin Fast Mask register for
6. from Slave to Master Fig 113 Format of Master Receive mode UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Table 512 Summary of registers Generic Description Access Reset I2Cn Register Name value Name 8 Address I2CONSET 12C Control Set Register When a one is written toa RAW 0x00 I2COCONSET 0xE001 C000 bit of this register the corresponding bit in the I2C I2C1CONSET 0xE005 C000 control register is set Writing a zero has no effect on I2C2CONSET 0xE008 0000 the corresponding bit in the I C control register I2STAT I2C Status Register During 12C operation this RO OxF8 I2COSTAT 0 001 C004 register provides detailed status codes that allow I2C1STAT OxEO05 C004 software to determine the next action needed I2C2STAT OxE008 0004 I2DAT I2C Data Register During master or slave transmit R W 0x00 IZCODAT 0xE001 C008 mode data to be transmitted is written to this register I2C1DAT 0xE005 C008 During master or slave receive mode data that has I2C2DAT 0xE008 0008 been received may be read from this register 12 Slave Address Register Contains the 7 bitslave RAW 0x00 I2COADR 0xE001 C00C address for operation of the I2C interface in slave I2C1ADR 0xE005 C00C mode and is not used in master mode The least I2C2ADR 08 000C significant bit determines whether a slave responds to the general call address I2SCLH SCH Duty Cycle Register High Half Word R W 0x04 I2COSCLH OxEO01 C010 Determine
7. CCLKCFG CCLKDivValue Set clock divider if USE USB USBCLKCFG USBCLKDivValue usbclk 288 MHz 6 48 MHz endif while PLLSTAT amp 1 lt lt 26 Check lock bit status MValue PLLSTAT amp 0 00007 NValue PLLSTAT amp 0x00FF0000 gt gt 16 while MValue PLL_MValue amp amp NValue PLL_NValue PLLCON 3 enable and connect PLLFEED PLLFEED 0x55 while PLLSTAT amp 1 lt lt 25 0 Check connect bit status UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Table 57 Peripheral Clock Selection register 1 PCLKSEL1 address 0xE01F C1AC bit description Bit Symbol Description Reset value 10 PCLK BAT RAM Peripheral clock selection for the battery supported RAM 00 32 PCLK GPIO Peripheral clock selection for GPIOs 00 5 4 PCLK_PCB Peripheral clock selection for the Pin Connect block 00 P C L KS E L 0 7 6 PCLK 201 Peripheral clock selection for I2C1 00 9 8 Unused always read as 0 00 P C L KS E L 1 11 10 PCLK_SSP0 Peripheral clock selection for SSP0 00 13 12 PCLK TIMER2 Peripheral clock selection for TIMER2 00 15 14 PCLK TIMER3 Peripheral clock selection for TIMER3 00 17 16 PCLK UART2 Peripheral clock selection for UART2 00 1948 PCLK UART3 Peripheral clock selection for UART3 00 2120 PCLK 262 Peripheral clock selection for 12 2 00 2322 125 Peripheral clock selection for 125 00 25 24 PCLK
8. INTERNAL RC OSCILLATOR wor clock select WOTCLKEEL OSCILLATOR Fig 12 Clock generation for the LPC2400 USB clock contig USBCLKCFG PERIPHERAL CLOCK GENERATOR PCLK SELO 19 18 other poriphorats sao POLKSELO PCONRISI 581 272 SEL1 22 28 UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD At startup the Internal RC oscillator 15 used and PLL 15 bypassed e User boot can activate the main oscillator SCS system Control ans Status Register e When main oscillator 1s stabilized user program can use it as clock source for the PLL CLKSRCSEL register and activate 1t with specific value PLLCFG to choose M and N CPU CCLKCFG and USB USBCLKCFG divider are set Peripheral clocks are set PCLKSELO and 1 UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD void ConfigurePLL void unsigned int MValue NValue if PLLSTAT amp 1 lt lt 25 M PLLCON 1 Enable PLL disconnected PLLFEED 0xaa PLLFEED 0x55 PLLCON 0 Disable PLL disconnected PLLFEED PLLFEED 0 55 SCS 0 20 Enable OSC while SCS amp 0 40 Wait until main OSC is usable CLKSRCSEL 0x1 select main OSC 12MHz as the PLL clock source PLLCFG PLL MValue PLL_NValue lt lt 16 PLLFEED PLLFEED 0x55 PLLCON 1 Enable PLL disconnected PLLFEED 0xaa PLLFEED 0x55
9. gt PC 1s loaded with exception vector Address between 0x0 reset to 0x1C UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Software Interrupt SWI Supervisor svc 6 mu UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD For arm processor each mode has their own stack pointer gt Allow the exception handler to save data in its own memory area without corrupting the application data During the execution of the exception handler no interrupt are allowed gt No peripheral or system services can be serviced without re enable interrupt Exception handler are architecture specific and differs from standard function gt Exception routine need special entry and exit code that can be written in asm or provided by a library UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Exception Vectors Mapped to Address 0 Absolute addressing mode must be used Dummy Handlers are implemented as infinite loops which can be modified Vectors LDR Reset Addr LDR PC Undef Addr LDR PC SWI Addr LDR PC Addr LDR PC DAbt Addr NOP Reserved Vector LDR PC IRQ Addr LDR PC FIQ Addr Reset Addr DCD Reset Handler Undef Addr DCD Undef Handler SWI Addr DCD SWI Handler PAbt Addr DCD PAbt Handler DAbt Addr DCD DAbt Handler DCD 0 Reserved Address IRQ Addr DCD IRQ Handler FIQ Addr DCD FIQ Handler UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Trust
10. PCLKSELO 15 14 00 for pclk cclk 4 18MHz gt PCLKSELO amp 3 lt lt 14 gt PINSELI 23 22 01 and PINSELI 25 24 01 PINSEL kr 3 lt lt 22 3 lt lt 24 PINSELI 1 lt lt 22 01 lt lt 24 gt Clock timing 100kHz High duty cycle 90 pclk I20SCLH 90 Low duty cycle 90 pclk tic IZOSCLL 90 gt DCOCONCLR 12 SI I2C STO PEN gt DCOCONSET 2C DEN UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD I20CONSET 12 STA while 120 amp I2C_SJ check status to handle error I20CONCLR DC SI I2C STA I20DAT 0 0 while I20CONSET amp SD check status to handle error nack I20CONCLR DC SI I20DAT 0x18 while I20CONSET amp SI check status to handle error nack I20CONCLR I2C SE I20DAT 0x01 0x4 0x10 0x40 while I20CONSET amp SD check status to handle error nack I20CONCLR I2C SE I20CONSET I2C STO while IZOCONSET amp I2C STO send START Wait for START clear SI and STA PCA address Wait for ADDRESS send clear SI select register LS2 and AI Wait for DATA send clear SI 4 leds on led8 to 11 Wait for DATA send clear SI send STOP Wait for STOP STO is cleared automatically UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD
11. Peripheral clock selection for MCI 00 27 26 Unused always read as 0 00 2928 PCLK_SYSCON Peripheral clock selection for the System Control block 00 31 30 Unused always read as 0 00 Table 58 Peripheral Clock Selection register bit values PCLKSELO and PCLKSEL1 Function Reset individual peripheral s clock value select options 00 PCLK_xyz CCLK 4 00 01 PCLK CCLKIU 10 PCLK xyz CCLK 2 11 Peripheral s clock is selected to PCLK xyz CCLK 8 except for CAN1 CAN2 and CAN filtering when 11 selects PCLK xyz CCLK 6 1 ForPCLK RTC only the value 01 is illegal Do not write 01 to the PCLK RTC Attempting to write 01 results in the previous value being unchanged UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD 4 special modes of power reduction gt Idle Clocks core stopped Resume on reset or interrupt gt Sleep Main oscillator powered down and all clock stopped Wake up on reset or interrupt PLL must be reconfigured gt Power down All clock powered down Flash is powered down unlike sleep gt Deep power down Power regulator turned off register values are not retained UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Each peripheral can be turned off clock disable Control of power peripheral done through PCONP reg Bit Symbol Description Reset Symbol Description value value 0 Unused always 0 0 22 PCTIM2 Timer 2 power clock control bit 0 1
12. 01 is reserved for flashless parts LPC2420 60 70 10 User RAM Mode Interrupt vectors are re mapped to Static RAM 11 User External Memory Mode Interrupt vectors are re mapped to external memory bank 0 Warning Improper setting of this value may result in incorrect operation of the device T2 Reserved user software should not write ones to reserved bits NA The value read from a reserved bit is not defined UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD e Provide initial operation after reset and means to programs user flash memory e At reset with certain conditions an ISP handler 15 Invoked In System Programming gt P2 10 sampled low gt Watchdog flag not set e If P2 10 1s sampled High the boot loader search for a valid user program 1n flash 7 A checksum of exception vector is done signature in 0x14 added with the sum of other exception vectors must be 0 gt If checksum is valid the user program is launch otherwise no UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD 3 oscillators Main oscillator 1 to 24 MHz 12MHz Internal RC oscillator 4MHz RTC oscillator All oscillator can drive a PLL and subsequently the CPU PLL allow to choose the CPU clock frequency from the clock source USBSEL 3 0 2 M Jr 2 N f sected CCLKSEL 7 0 Fig 14 PLL block diagram N 16 M 125 USBSEL 6 CCLKSEL 4 UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD MAN E
13. PCTIMO Timer Counter 0 power clock control bit 1 23 PCTIM3 Timer 3 power clock control bit 0 2 PCTIM1 Timer Counter 1 power clock control bit 1 24 PCUART2 UART 2 power clock control bit 0 3 PCUARTO UARTO power clock control bit 1 25 PCUART3 UART 3 power clock control bit 0 4 PCUART1 UART1 power clock control bit 1 26 PCI2C2 125 interface 2 power clock control bit 1 5 PCPWMO PWMO power clock control bit 1 27 PCI2S PS interface power clock control bit 0 6 PCPWM1 PWM1 power clock control bit 1 28 PCSDC SD card interface power clock control bit 0 7 PCI2CO The 12 0 interface power clock control bit 1 29 PCGPDMA GP DMA function powericiock control bit 0 8 PCSPI The SPI interface power clock control bit 1 30 PCENET Ethernet block power clock control bit 0 9 PCRTC The RTC power clock control bit 1 31 PCUSB USB interface power clock control bit 0 10 PCSSP1 SSP1 interface power clock control bit 1 11 PCEMC External Memory Controller 1 12 AID converter ADC powericiock control bit 0 l enab l Note Clear the bit in the ADOCR before clearing this bit and set A this bit before setting PDN di S abl e 13 PCCAN1 CAN Controller 1 power clock control bit 0 14 2 CAN Controller 2 power clock control bit 0 18 15 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 19 PCI2C1 The 12 1 interface power clock control bit 20 LCD co
14. Parity Number Word Length Select R W Panty Panty Enable of Stop Select Bits NA 0x00 0x00 0x00 U0RBR 0 000 C000 U2RBR 0xE007 8000 U3RBR 0 007 C000 UOTHR 0xE000 C000 U2THR 0xE007 8000 U3THR 0xE007 C000 U0DLL 0xE000 C000 U2DLL 0xE007 8000 U3DLL 0xE007 C000 UODLM 0 000 C004 U2DLM 0xE007 8004 U3DLM 0 007 C004 U0IER 0xE000 C004 U2IER 0xE007 8004 U3IER 0xE007 C004 U0IIR 0xE000 C008 UZIR 0xE007 8008 U3IIR 0xE007 C008 U0FCR 0xE000 C008 U2FCR 0xE007 8008 U3FCR 0xE007 C008 UOLCR 0 000 C00C U2LCR 0xE007 800C U3LCR 0 007 COOC UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Table 377 UART Register Map UOLSR 0xE000 C014 U2LSR 0xE007 8014 U3LSR 0xE007 C014 U3FDR 0xE007 C028 SCR Scratch Pad 8 bit Data RW 10 00 UOSCR Register 0 000 CO1C U2SCR 0 007 801C U3SCR 0 007 C01C ACR Auto baud Reserved 31 10 ABTO R W 10 00 UDACR Control IntCir IntCir 0 000 C020 Reset U3ACR 0 007 C020 ICR IrDA Control Reserved PulseDiv FixPulse IrDAInv IDAEn RW 0 U3ICR 0xE000 C024 Register En only FDR Fractional MulVal DivAddVal RW 040 UOFDR 0xE000 C028 Divider Register U2FDR 0xE007 8028 TER Transmit UOTER 0xE000 C030 U2TER 0xE007 8030 U3TER 0xE007 C030 UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD To allow a working s
15. UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Table 57 Peripheral Clock Selection register 1 PCLKSEL1 address 0xE01F C1AC bit description Bit Symbol Description Reset value PCLKSEL1 amp 0 3 lt lt 2 7 6 PCLK 12 1 Peripheral clock selection for I2C1 00 9 8 Unused always read as 0 00 11 10 PCLK SSPO Peripheral clock selection for SSPO 00 13 12 PCLK TIMER2 Peripheral clock selection for TIMER2 00 The 2 b its 3 2 are 1 d 15 14 PCLK_TIMER3 Peripheral clock selection for TIMER3 00 17 16 PCLK UART2 Peripheral clock selection for UART2 00 S l cting a l O ck O f C C LK 4 for 1948 PCLK_UART3 Peripheral clock selection for UART3 00 2120 PCLK_I2C2 Peripheral clock selection for 12 2 00 the GP I O 2322 PCLK 12 Peripheral clock selection for 125 00 25 24 PCLK Peripheral clock selection for MCI 00 27 26 Unused always read as 0 00 2928 PCLK_SYSCON Peripheral clock selection for the System Control block 00 31 30 Unused always read as 0 00 Table 58 Peripheral Clock Selection register bit values PCLKSELO and PCLKSEL1 Function Reset individual peripheral s clock value select options 00 PCLK_xyz CCLK 4 00 01 PCLK CCLKIU 10 PCLK xyz 2 11 Peripheral s clock is selected to PCLK xyz CCLK 8 except for CAN1 CAN2 and CAN filtering when 11 selects PCLK xyz CCLK 6 1 ForPCLK RTC only the value 01 is illegal Do not write 01 to t
16. as a System Timer The alarm registers allow the user to specify a date and time for an interrupt to be generated UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Reference Clock Divider Minute Alarm Interrupt available Day of month Day of month Alarm on increment of register value Day of week Day week Alarm Day of year Day of year Alarm Interrupt on match Seconds Seconds Alarm UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD e Provide a method of recovering control of a crashed program Timer that can produce gt nterrupt gt Reset e Watchdog timer must be feeded reloaded within a predetermined amount of time gt From few usec to few minutes UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD PWM Pulse Width Modulation e I2S bus inter integrated circuit sound interface e SSP Synchronous Serial Peripheral e ADC and DAC Analog digital conversion e SD MMC Card Interface e CAN Controller Area Network e Ethernet e USB host and device e LCD controller 9 8 b lt Wh lt n lt EN E UNIVERSIT DE TECHNOLOGIE DE BELFORT MONTB LIARD utom
17. branch instruction can be conditional UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD 10 11 12 13 14 15 16 17 18 19 1 hr mel CIE 7 EPRE s en Offset11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Move shifted register Add subtract Move compare add Isubtract immediate ALU operations Hi register operations branch exchange PC relative load Load store with register offset Load store sign extended byte halfword Load store with immediate offset Load store halfword SP relative load store Load address Add offset to stack pointer Push pop registers Multiple load store Conditional branch Software Interrupt Unconditional branch Long branch with link UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Reset Reset pin activated Undefined Special instruction code Instruction Software Interrupt Instruction code used to generate exception system SWI call Prefetch Abort Memory access violation during fetch IRQ IRQ pin activated FIQ pin activated UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD e When an exception occurs 7 PC 4 1s saved in lr mode 7 CPSR is saved in SPSR mode gt CPSR is changed Mode becomes svc irq data or prefetch abort depending the exception bit 1 set IRQ not allowed for all exceptions F bit 15 set if the exception 1s or reset
18. chip non volatile 0x0000 0000 0x0007 FFFF Flash Memory 512 kB 0x3FFF FFFF memory and Fastl O C000 0x3FFF FFFF Fast GPIO registers 0x4000 0000 to On chip RAM 0x4000 0000 0x4000 FFFF RAM 64 kB Ox7FFF FFFF Ox7FEO 0000 OxX7FEO 3FFF Ethernet RAM 16 kB Ox7FDO 0000 OX7FDO 3FFF USB RAM 16 kB 0x8000 0000 to Off Chip Memory Four static memory banks 16 MB each OxDFFF FFFF 0x8000 0000 FFFF Static memory bank 0 0x8100 0000 OX81FF FFFF Static memory bank 1 0x8200 0000 0x82FF FFFF Static memory bank 2 0x8300 0000 0x83FF FFFF Static memory bank 3 Four dynamic memory banks 256 MB each 0 000 0000 OXAFFF FFFF Dynamic memory bank 0 0xB000 0000 0xBFFF FFFF Dynamic memory bank 1 0xC000 0000 0xCFFF FFFF Dynamic memory bank 2 0xD000 0000 0xDFFF FFFF Dynamic memory bank 3 0xE000 0000 to APB Peripherals 36 peripheral blocks 16 kB each OxEFFF FFFF 0xF000 0000 to AHB peripherals OxFFFF FFFF UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD e ARM exception vectors are at address 0x0 0 1 e Remapping on LPC2478 consists In changing some memory address to map vector address 64 byte from 0 0 to Ox3F M O de S Mode Activation Usage Boot Hardware The Boot Loader always executes after any reset The Boot ROM Loader activation by interrupt vectors are mapped to the bottom of memory to allow mode any Reset handling exceptions and using interrupts during the Boot Loading process A
19. if MR0 matches the TC 0 Feature disabled UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD static void mdelay unsigned int ms TITCR 0x02 stop and reset timer TIPR 0x00 set prescaler to zero TIMRO ms Fpclk 1000 Fpclk 36000000 TIMCR 0x04 stop timer on match TITCR 0x01 start timer wait until delay time has elapsed test the enable bit while TITCR amp 0x01 2 UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Inter Integrated Circuit Two Wire Interface Two wire communication bus synchronous serial transmission Multimaster 400kbit s for slow devices Each device has an address 8 or 10 bits which 1s used when addressed in slave mode UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD pull up resistor pull up resistor 12 bus SDA SCL OTHER DEVICE WITH LPC2400 I2C INTERFACE Fig 111 bus configuration SDA SCL OTHER DEVICE WITH 2 INTERFACE UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD e Master drives the clocks and initiate transfer Slave respond to master request A Transmission 15 started by a start sequence e Data are transferred In sequence of 8 bits from to master MSb first gt Data are changed during low edge of clock gt Data must be stable during high edge of clock Transmission ends with a stop sequence For each 8 bits data receiver must acknowledge sender by
20. port Writes sets clears and reads to port done via writes to FIOPIN FIOSET and FIOCLR and reads of FIOPIN alter or return only the bits enabled by zeros in this register Fast Port Pin value register using FIOMASK The current state of digital port pins can be read from this register regardless of pin direction or alternate function selection as long as pins are not configured as an input to ADC The value read is masked by ANDing with inverted FIOMASK Writing to this register places corresponding values in all bits enabled by zeros in FIOMASK Important if a FIOPIN register is read its bit s masked with 1 in the FIOMASK register will be set to 0 regardless of the physical pin state Fast Port Output Set register using FIOMASK This register controls the state of output pins Writing 1 produces highs at the corresponding port pins Writing 0s has no effect Reading this register returns the current contents of the port output register Only bits enabled by 0 in FIOMASK can be altered Fast Port Output Clear register using FIOMASKO This register controls the state of output pins Writing 1 produces lows at the corresponding port pins Writing 0 has no effect Only bits enabled by 0 in FIOMASKO can be altered Access Reset value RW 0x0 RW 0x0 RAN 0 0 RW 0x0 WO 0 0 PORTn Register Address amp Name FIO0DIR 0x3FFF C000 FIO1DIR 0x3FFF C020 FIO2DIR 0x3FFF C040 FIO3DIR 0x3FFF C060 FIO4DIR 0x3FFF C08
21. 0 FIOOMASK 0x3FFF C010 FIO1MASK 0x3FFF C030 FIO2MASK 0x3FFF C050 FIO3MASK 0x3FFF C070 FIO4MASK 0x3FFF C090 FIO0PIN 0x3FFF C014 FIO1PIN 0x3FFF C034 FIO2PIN 0x3FFF C054 FIO3PIN 0x3FFF C074 FIO4PIN 0x3FFF C094 FIOOSET 0x3FFF C018 FIO1SET 0x3FFF C038 FIO2SET 0x3FFF C058 FIO3SET 0x3FFF C078 FIO4SET 0x3FFF C098 FIO0CLR 0x3FFF C01C FIO1CLR 0x3FFF FIO2CLR 0x3FFF C05C FIO3CLR 0x3FFF 07 FIO4CLR 09 UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD To configure pin as output a 1 must be written on the corresponding pin in FIOxDIR 0 15 for input To set or clear a pin Two register can be used 7 FIOxSET set the pin by writing a 1 on the corresponding bit gt FIOxCLEAR clear the bin by writing a on the corresponding bit e Writing a value in FIOxPIN can also be used Corresponding bit in FIOXMASK must be 0 e Ex FIOODIR 0x2 set direction for bit 1 FIOODIR 0x2 FIOOSET 0x2 set PO 1 FIOOPIN 7 0x2 set PO 1 FIOOCLEAR 0x2 clear PO 1 FIOOPIN amp 0 2 clear P0 1 UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD e Port0 and 2 can be configured to generate Interrupt 2 pairs of enable status registers are present one for a rising edge and one for falling edge 7 InEnF R enable corresponding pin for interrupt 7 ntStatF R RO to verify which pin has generate interrupt Interrupt must be cleared through Int
22. 0 0 PINSELO 0x00000050 Enable TxDO and RxDO 5 UOFDR 0 85 Fractional divider 7 UOLCR 0 83 8 bits Parity 1 Stop bit DLAB 1 UODLL 6 115200 Baud Rate 18 MHZ PCLK UODLM 2 20 High divisor latch 0 UOLCR 0 03 8 bits no Parity 1 Stop bit DLAB 0 int sendchar int ch Write character to Serial Port While U2LSR amp 0x20 Walt for transmitt buffer empty return U2THR ch int getkey void Read character from Serial Port While U2LSR amp 0x01 Walt for receive buffer not empty return U2RBR UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD The RIC 1s a set of counters for measuring time when system power 1s on and optionally when it is off e RIC can be clocked by a separate 32 768 kHz oscillator or by a programmable prescaler divider based on PCLK RTC and battery SRAM have a separate power domain supplying 3 3V to the Vbat pin Provides Seconds Minutes Hours Day of Month Month Year Day of Week and Day of Year UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD e An alarm output pin 15 included to assist in waking up when the chip has had power removed to all functions except the RTC and Battery RAM e Periodic interrupts can be generated from increments of any field of the time registers and selected fractional second values 7 This enhancement enables the to be used
23. 1 4 8 14 for receiver e Line Status Register UnLSR for status information gt Data received or transmitted error on received data Control gt UARTn Line Control Register UnLCR Number of bits stop bit parity enable parity type divisor latch access DLAB gt FIFO Control Register UnFCR to reset emitter or transmitter and to chose receiver s fifo trigger UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD e Baud rate 7 Divisor latch UnDLL and UnDLM 7 Fractional Divider Register UnFDR for baud rate Interrupt 7 Interrupt Enable Register UnIER to allow interrupt source request to the system data transmitter s fifo empty received data error or time out 7 Interrupt Identification Register UnIIR to identify the interrupt source UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTBELIARD Table 377 UART Register Map IER FCR LCR InterruptEnable Register Interrupt ID Register FIFO Control Register Line Control Register FIFOs Enabled RX Trigger DLAB Set Break 8 bit Read Data RO 8 bit Write Data l 8 bit Data m 8 bit Data Reserved Enable EnableEnd RAW Auto Baud of Auto Time Out Baud Interrupt Interrupt 0 Enable Enable Enable RX RX Line THRE Data Status Interupt Available Interrupt Interrupt Reserved ABEOint RO 0 IIR3 2 IIR1 0 Reserved TXFIFO RXFIFO FIFO WO Reset Reset Enable Stick Even
24. An UnLSR read clears UnLSR 3 The RXFE time of the framing error detection is dependent on UnFCRO Upon detection of a framing error the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit However it cannot be assumed that the next received byte will be correct even if there is no Framing Error Note A framing error is associated with the character at the top of the UARTn RBR FIFO 0 Framing error status is inactive Framing error status is active When RXDn is held in the spacing state all 0 s for one full 0 character transmission start data parity stop a break interrupt occurs Once the break condition has been detected the receiver goes idle until RXDn goes to marking state all 15 An UnLSR read clears this status bit The time of break detection is dependent on UnFCRI O Note The break interrupt is associated with the character at the top of the UARTn RBR FIFO Break interrupt status is inactive Break interrupt status is active THRE is set immediately upon detection of an empty UARTn 1 THR and is cleared on a UnTHR write UnTHR contains valid data UnTHR is empty TEMT is set when both UnTHR and UnTSR are empty TEMT 1 is cleared when either the UnTSR or the UnTHR contain valid data UnTHR and or the UnTSR contains valid data UnTHR and the UnTSR are empty UnLSR 7 is set when a character with a Rx error such as 0 framing error parity err
25. Clr register Table 160 GPIO interrupt register map Generic Description Access Reset PORTn Register Name value Address 8 Name IntEnR GPIO Interrupt Enable for Rising edge R W 0x0 IOOINtENR 0xE002 8090 IO2IntEnR 0xE002 80B0 IntEnF GPIO Interrupt Enable for Falling edge RAN 0 0 IOOINtENR 0xE002 8094 IO2IntEnR 0xE002 8084 IntStatR GPIO Interrupt Status for Rising edge RO 0 0 IOOINtStatR 0xE002 8084 IO2IntStatR 002 80A4 IntStatF GPIO Interrupt Status for Falling edge RO 0x0 IO0IntStatF 0xE002 8088 IO2IntStatF 0xE002 80A8 IntCIr GPIO Interrupt Clear WO 0 0 IOOINtCIr 0xE002 808C IO2IntCIr 0xE002 80AC IntStatus GPIO overall Interrupt Status RO 0x00 lOlntStatus 0xE002 8080 UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTBELIARD void led210 init void Power control GPIO cannot be turned off if CLOCK PCLKSELI 6 0x3 lt lt 2 3 2 0600 CCLK 4 PIN i function select for P2 10 GPIO in PINSEL4 PINSEL4 21 20 0600 RW PINSEL4 amp 3 lt lt 20 connect mode selection for pin 00 pull up resistor selected RW PINMODE4 amp 3 lt lt 20 direction mode selection output 1 et input 0 out selected R W FIO2DIR 1 lt lt 10 to allowed read an write on the selected pin 0 enable FIO2MASK amp 1 lt lt 10 void led210 turn on void 4 FIO2CLR 1 lt lt 10 void led210 turn off void 4 FIO2SET 1 lt lt 10
26. SI check status to handle error I20CONCLR DC SI I2C STA I20DAT slave address while I20CONSET SI check status to handle error nack I20CONCLR DC SI I20DAT data0 while 120 amp SD check status to handle error nack I20CONCLR I2C SE I20CONSET DC STO while I20CONSET amp I2C STO send START Wait for START clear SI and STA slave address Wait for ADDRESS send clear SI data 0 Wait for DATA send clear SI send STOP Wait for STOP note STO is cleared automatically UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Controlling interface gt For every events SI is set Astatus code Is present in IZSTAT gt When SI 1s set the status code can be used to take appropriate action gt After each operation software must wait for SI to be set 1nterruption can be used e Bit AA 1s used to allow interface to become slave Repeated STA new start before stop must be used with some interface selecting register inside a device before a read by example UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD trom Siave to Master any number of data bytes and their associated Acknowledge bits this number contained In I2STA corresponds to a defined state of the PC bus Fig 120 Format and States in the Master Transmitter mode successful tran
27. STER AHBTO SLAVE USB DEVICE Vous MIURMII PORT AHB BRIDGE PORT HOST OTG WITH porti 4 RAM AND port2 AHB TO BRIDGE CONTROLLER ESE EXTERNAL INTERRUPTS LCD INTERFACE 8 gt LCD control dec s WITH DMA LCDVDI23 0 LCDCLKIN 2 CAPTURE COMPARE CAP2ICAP3 TIMERO TIMER1 MM 4 x MAT2 MATS ein TIMER2 TIMER3 n 3x C ESINTERFACE DM 1 denm SCK0 SCK 1 MOSIO 2x PCAP1 SSP0 SPI INTERFACE rene eren LEGACY GPVO SSELO SSEL 64 PINS TOTAL SSPtINTERFACE E MOGH MISOt SSEL1 MCICLK MCIPWR SD MMC CARD INTERFACE MCICMD MCIDAT 3 0 TXDO TXD2 TXD3 UARTO UART2 UART3 RXD2 RXD3 TXD1 DTR1 RTS1 EEJ BERI CIBI DCD1 RH RD1 RD2 2 CAN1 CAN2 WATCHDOGTIMER TD1 TD2 SCLO SCL1 SCL2 CO ct 2 CONTROL SDA0 SDA1 SDA2 UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD OXFFFF FFFF AHB PERIPHERALS OxFOOO 0000 PERIPHERALS EXTERNAL STATIC AND DYNAMIC MEMORY BOOT ROM AND BOOT FLASH RESERVED ADORESS SPACE ON CHIP STATIC RAM 0 4000 0000 Ee SPECIAL REGISTERS 8000 RESERVED ADDRESS SPACE ON CHIP NON VOLATILE MEMORY OR RESERVED Fig6 LPC2400 system memory map UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Address range General use Address range details and description 0x0000 0000 to On
28. Zone 67 Multicore 6K x Improved SIMD Instructions Jazelle 5TEJ x ARM7TDMI ARM926EJ S ARM1136JF S Cortex A8 R4 M3 M1 ARM922T ARM946E S ARM1176JZF S Thumb2 Thunb ARM966E S ARM11 MPCore instruction set Extensions ra Unaligned data support applications NEON v7R real time HW Divide DSP instructions Thumb 2 672 microcontroller HW Extensions Divide and Thumb 2 only Wr b 2 l A E v ak gt i n 4 7 200000006 gr 2 2 1 2 ma NIVERSITE DE TECHNOLOGIE DE BELFORT MONTBELIARD NXP LPC2478 S utom Nicolas Lacaille UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Microcontroler from with ARM7TDMI S core e Running up to 80M Hz 64 kbyte of SRAM 518 kbyte of flash program memory External memory interface 7 An external memory controller is present to connect static or dynamic RAM or FLASH Peripherals gt AHB peripherals VIC ethernet usb memory FastGPIO gt APB peripherals s rial Timer PWM ADC RT clock UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTBELIARD TMS TDI trace signals 00 3 3 7851 SYSTEM VREF PO P1 P2 TEST DEBUG FUNCTIONS a Vssio Vsscong INTERFACE 5 2 DD DCDC 2V3 lt INTERNAL RC 2u OSCILLATOR zo 160 PINS a TOTAL nia A 23 0 control lines BRIDGE MA
29. ated by a software interrupt 9 Write to the VICAddress Register This clears the respective interrupt in the internal interrupt priority hardware 10 Return from the interrupt This re enables the interrupts UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD 0x18 LDR pc pc 0 1201 Load Vector into PC vector handler Code to enable interrupt nesting STMFD 1131 r12 r14 stack Ir irq and r12 plus other regs used below if appropriate MRS r12 spsr Copy spsr into 112 STMFD ri3 4112 and save to stack MSR c 0xlf Switch to SYS mode re enable IRQ STMFD 1131 r0 r3 r14 stack lr sys and r0 r3 Interrupt service routine Add code to clear the interrupt source Code to exit handler BL 2nd level handler this corrupts lr sys and r0 r3 r13 1 0 3 r14 unstack lr sys and r0 r3 MSR epsr c 0 92 Disable IRQ and return to IRQ mode LDMFD ri3 r12 unstack r12 MSR spsr cxsf rl2 and restore spsr LDMFD r13 r12 r14 unstack registers LDR r1 VectorAddr STR 10 r1 2 Acknowledge VIRQ serviced SUBS pe lr 4 2 Return from ISR UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Some toolchains can provide entry exit code of a interrupt routine Basic entry exit code gt To use more complex code to allow nested interrupt or to switch context you still have to write the entry exit code in asm With gcc you can use th
30. e attribute keyword to modify the entry exit code of a function gt For a interrupt use interrupt attribute void myISR void attribute interrupt Pour ARM attribute interrupt IRQ UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTBELIARD Universal Asynchronous Receiver transmitter 7 Standard PC serial line Serial data are transmitted bit after bit Isb first Asynchronous gt No clock to synchronize symbol detection gt Transmitter and receiver must use the same baud rate 7 Synchronization with start stop bit gt Automatic baud rate detection capable Full duplex via two different lines RX and TX UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Figure 44 Asynchronous Mode Start Bit Detection Rate Clock 1111111 True Start 00 Detection Sampling Figure 45 Asynchronous Mode Character Reception Example 8 bit parity enabled 1 stop 0 5 bit 1 bit 1 po I Sampling DO 01 02 03 04 05 06 07 Stop Bit True Start Detection Parity Bit UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Diagram serial intemace Application serializer Application LPC2478 99 UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD 16 bytes FIFO for receiver and transmitter gt Write and read from a unique register Read Buffer Register UnRBR and Transmit Holding Register Un THR gt Trigger point
31. egister This register reads out the state of the 32 interrupt requests software interrupts regardless of enabling or classification Interrupt Select Register This register classifies each of the 32 interrupt requests as contributing to FIQ or IRQ Interrupt Enable Register This register controls which of the 32 interrupt requests and software interrupts are enabled to contribute to FIQ or IRQ Interrupt Enable Clear Register This register allows software to clear one or more bits in the Interrupt Enable register Software Interrupt Register The contents of this register are ORed with the 32 interrupt requests from various peripheral functions Software Interrupt Clear Register This register allows software to clear one or more bits in the Software Interrupt register Protection enable register This register allows limiting access to the VIC registers by software running in privileged mode Software Priority Mask Register Allows masking individual interrupt priority levels in any combination Vector address 0 register Vector Address Registers 0 31 hold the addresses of the Interrupt Service routines ISRs for the 32 vectored IRQ slots Vector address 1 register Vector address 2 register i Tonmiatan eco VOGLI I ISYISITI Vector priority 30 register Vector priority 31 register Vector address register When an IRQ interrupt occurs the Vector Address Register holds the addres
32. erial line the baud rate must be set to match both emitter transmitter device The baud rate 15 selected with 2 registers 7 UnDLM an UnDLL which are respectively at Un THR and UnRBR address location when DLAB UnLCR is set gt Fractional Divider Register UnFDR Bit Function Value Description Reset value 3 0 DIVADDVAL 0 Baud rate generation pre scaler divisor value If this field 1 0 0 fractional baud rate generator will not impact the UARTn baudrate 74 MULVAL 1 Baud rate pre scaler multiplier value This field must be 1 greater or equal 1 for UARTn to operate properly regardless of whether the fractional baud rate generator is used or not 31 8 NA Reserved user software should not write ones to reserved 0 bits The value read from a reserved bit is not defined PCLK UARIn m DivaddVal 16 x 256 UnDLM UnDLL x 1 UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD e Fora 8 1 N configuration and 115 200 baud e Baud rate gt Pelk 72 4 18MHz gt DL 18e6 16 115200 9 76 7 DL is calculated to have FR near 1 5 DL 9 76 1 5 6 and FR 1 628 7 FRis chosen from tab p393 DIVADDVAL 5 MULVAL and real FR 1 625 gt Baud rate 115 384 diff 0 1 UnFDR 0x85 Fractional divider UnLCR 0x83 8 bits no Parity 1 Stop bit DLAB 1 6 115200 Baud Rate 18 MHZ PCLK UnDLM 0 High divisor latch 0 7 UnLCR 0x03
33. he PCLK RTC Attempting to write 01 results in the previous value being unchanged UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTBELIARD Table 135 LPC2420 60 68 70 78 pin function select register 4 PINSEL4 address 0 002 C010 bit description PINSEL4 11 10 13 12 15 14 17 16 19 18 function select for P2 10 GPIO in PINSEL4 PINSEL4 21 20 0500 PINSEL4 amp 3 lt lt 20 Pin name P2 5 P2 6 P2 7 P2 8 Function when Function 00 GPIO Port 2 5 GPIO Port 2 6 GPIO Port 2 7 GPIO Port 2 8 GPIO Port 2 9 when 01 PWM1 6 PCAP1 0 RD2 TD2 USB_CONN ECT1 LCDCLKIN Function when 10 DTR1 RI1 RTS1 TXD2 RXD2 RW Function when 11 TRACEPKTOLY LCDLP LCDVDI4 TRACEPKT2UY LCDVDI5 LCDVD 6 LCDVD 3J LCDVDI7 Reset value 00 00 00 00 UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD e The LPC2478 includes four 32 bit Timer Counters Count cycles of the system derived clock or an externally supplied clock Include programmable 32 bit prescaler Can optionally generate interrupts or perform other actions at specified timer values based on four match registers Set LOW on match Set HIGH on match Toggle on match Do nothing on match The Timer Counter also includes four capture
34. inputs to trap the timer value when an input signal transitions gt capture event may also optionally generate an interrupt UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTBELIARD Po Reset Enable UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD e Prescaler gt Each PCLK edge the prescaler counter is incremented gt When the prescaler counter equals the prescaler register timer counter is incremented and the prescaler counter 15 cleared Timer Control register gt Enable or disable the 2 counter prescaler and timer gt reset of the timer counter and the prescaler counter UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Use to measure pulse duration 7 Counter captured on external events on CAP pin Rising edge falling edge toggle 7 nterrupt request can be generated by a capture Pin Counter Logic Capture Register Capture control register UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD e Used to control the counter gt Disable or reset the counters Can generate an interrupt request on match The pin level can be changed on match external match register 7 Set cleared toggle Timer Counter Linen External Match Register Match Register UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD AUU U UUU U U ATATAU outer 2 Li A2 A A2 Ko l Lo l KOU e oJ ti
35. ipheral bus Interface I O Interface 1 I O Interface I O interface 5 UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD An embedded system control an industrial process gt one side you have captor connected to Input ports gt On the other side you have motor unit connected to output ports The application do cycle made up of 7 Reading data from the Input port at a known memory address 7 Computing the data Writing new data to the output port UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Input output port are device register that can be acceded in the physical memory map gt Memory mapped register e Memory mapped register most of time don t work like standard memory use for variable 7 Read only RO or Write only WO registers gt Variable size 8 16 32 bits gt Values can change outside the running application The correct type must be used In C language The volatile term must be used signals compiler that the variable can be changed outside the program UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Using a simple pointer to access port volatile unsigned port unsigned Int 0 40000000 for an output port port value foran input port variable port C macro define port volatile unsigned int 0x40000000 port value or value p
36. m instructions from flash 7 2 buffers are alternatively used to maintain prefetch rate Include a branch trail buffer for loops Set memory accelerater module MAMCR 0 if Feclk lt 20000000 MAMTIM 1 else if Feclk lt 40000000 MAMTIM 2 else MAMTIM 3 endif endif MAMCR SETTING 0 0158 160 1 partly enabled enabled for code prefetch but not for data 2 fully enabled UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTBELIARD To reduce number of pins on chip pins are multiplexed gt Different functions can use the pins Registers which are controlling pin function are gt PINSEL PINSELO to PINSEL11 gt PINMODE PINMODEO to PINMODE9 9 Table 130 Pin function select register 0 PINSELO address 0xE002 C000 bit description PINSELO Pin Function when Function when 01 Function Function Reset name 00 when 10 when 11 value P IN S EL C ontr O S 1 0 GPIO 0 0 1 TXD3 SDA1 00 32 GPIOPot01 TD1 RXD3 SCL1 00 l l 54 0 2 GPIO 0 2 TXDO Reserved Reserved 00 pin mu tip Table 146 Pin Mode select register 0 PINMODEO address 0xE002 C040 bit description PINMODEO Symbol Value Description Reset value 1 0 PO0 00MODE PORTO pin 0 on chip pull up down resistor control 00 PINMODE d e fi n e 00 P0 00 pin has a pull up resistor enabled 01 Reserved This value should not be used 10 P0 00 has neither pull up nor pull down e l ctric al p m
37. mer counter amp d interrupt Fig 129 A timer cycle in which PR 2 MRx 6 and both interrupt and reset on match are enabled PCLK prescale counter timer counter TCRIDO counter enable interrupt Fig 130 A timer Cycle in Which PR 2 MRx 6 and both interrupt and stop on match are enabled UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Table 548 Timer Control Register TCR TIMERn TnTCR addresses 0xE000 4004 0xE000 8004 0xE007 0004 0xE007 4004 bit description Bit Symbol Description Reset Value 0 Counter Enable When one the Timer Counter and Prescale Counterare 0 enabled for counting When zero the counters are disabled 1 Counter Reset When one the Timer Counter and the Prescale Counter 0 are synchronously reset on the next positive edge of PCLK The counters remain reset until TCR 1 is retumed to zero 7 2 Reserved user software should not write ones to NA reserved bits The value read from a reserved bit is not defined Table 550 Match Control Register T 0 1 2 3 MCR addresses 0xE000 4014 0xE000 8014 0xE007 0014 0xE007 4014 bit description Bit Symbol Value Description Reset Value 0 MROI 1 Interrupt on MRO an interrupt is generated when MRO matches 0 the value in the TC 0 This interrupt is disabled 1 MROR 1 Reset on MR0 the TC will be reset if MR0 matches it 0 0 Feature disabled 2 MROS 1 Stop on MR0 the TC and PC will be stopped and TCR 0 willbe 0 set to 0
38. ng address of the device 0xC0 7 Sending the number of the register gt Sending address of the device 0xC1 with repeated STA 7 read data from the device register UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD condition acknowledge from slave write to register twa data out from port DATA 1 VALID 00255 6 Fig 11 Write to register slave address command byte from slave data from register data from register La eot 5 1 1 0 0 A2 A1 m DATA first byte DATA last byte wal e Auto Increment 1 repeated register address acknowledge no acknowledge STOP START condition if Al 1 from master from master condition pom dare slave at this moment master transmitter becomes master receiver and slave receiver becomes slave transmitter Fig 12 Read from register UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTBELIARD Table 3 Register summary B3 B2 B1 Symbol Access Description 0 0 0 0 INPUTO read only input register 0 0 0 0 1 INPUT1 read only input register 1 0 0 1 0 PSCO read write frequency prescaler 0 0 0 1 1 PWM0 read write PWM register 0 0 1 0 0 PSC1 read write frequency prescaler 1 0 1 0 1 PWM1 read write PWM register 1 0 1 1 0 LS0 read write LEDO to LED3 selector 0 1 1 1 LS1 read write LED4 to LED7 selector 1 0 0 0 LS2 read write LED8 to LED11 selector 1 0 0 1 LS3 read write LED12 to LED15 selector Table4 INPUTO Input register 0 description
39. ntroller power control bit 0 21 PCSSPO SSPO interface power clock control bit If peripheral is disable read or write register are not valid UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Each peripheral can be turned off clock disable Control of power peripheral done through PCONP reg Bit Symbol Description Reset Symbol Description value value 0 Unused always 0 0 22 PCTIM2 Timer 2 power clock control bit 0 1 PCTIMO Timer Counter 0 power clock control bit 1 23 PCTIM3 Timer 3 power clock control bit 0 2 PCTIM1 Timer Counter 1 power clock control bit 1 24 PCUART2 UART 2 power clock control bit 0 3 PCUARTO UARTO power clock control bit 1 25 PCUART3 UART 3 power clock control bit 0 4 PCUART1 UART1 power clock control bit 1 26 PCI2C2 125 interface 2 power clock control bit 1 5 PCPWMO PWMO power clock control bit 1 27 PCI2S PS interface power clock control bit 0 6 PCPWM1 PWM1 power clock control bit 1 28 PCSDC SD card interface power clock control bit 0 7 PCI2CO The 12 0 interface power clock control bit 1 29 PCGPDMA GP DMA function powericiock control bit 0 8 PCSPI The SPI interface power clock control bit 1 30 PCENET Ethernet block power clock control bit 0 9 PCRTC The RTC power clock control bit 1 31 PCUSB USB interface power clock control bit 0 10 PCSSP1 SSP1 interface power clock control bit 1 11 PCEMC External Memory Controller 1 12 AID converter ADC powericiock cont
40. or or break interrupt is loaded into the UnRBR This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO UnRBR contains no UARTn RX errors or UnFCR 0 0 UARTn RBR contains at least one UARTn RX error UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Configure the baud rate Configure bit number parity stop bit Optionally reset emitter and transmitter and enable fifo Transmitting data Write in Un THR up to 16 byte gt Wait for THE transmitter s fifo empty flag to set or for Transmitter empty TEMT flag signaling serializer empty last byte completely transfered gt Write other data in UnTHR gt gt THE can source of UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD e Receiving data gt in UnLSR is set when an unread data is present in the RBR FIFO 7 Software waiting for data must poll bit wait for RDR to be set 7 Software must read data from UnRBR until is cleared Using interrupt 7 UnIER allow interrupt request on THRE RBR RX line status Overrun error OE Parity Error PE break BI and time out on reception gt UnIIR allow software to identify interrupt source UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD void init serial void 1 lt lt 3 Enable UARTO power PCLKSELO amp OxFFFFFF3F Pclock uart0 Cclock 4 PINSELO amp 0 00000
41. ort Using a macro provided by the kernel gt HAL WRITE UINT32 address value or inl int Using structure struct port 1 volatile unsigned config volatile unsigned data y portA portA struct port 0x40000000 portA gt config valuel value2 portA data ARM7TDMI microprocessor b l l il i n utom UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD 32 bits general purpose architecture 3 stages pipeline RISC architecture 32 bits instructions ARM mode or 16 bits Instructions for code compression THUMB mode Register to register and load store architecture Single bus for instruction and data Low consumption for embedded system UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD 7 execution modes 7 User usr 7 Supervisor svc privilieged for OS 7 FIQ fiq Fast Interrupt gt IRQ irq Normal Interrupt 7 System sys privileged for OS gt Abort abt addressing s fault gt Undefined not defined instruction Changed are done by software or on special event exceptions Modes out of usr are privileged modes UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD 31 general purpose registers Only 16 registers can be used in each mode gt r0 gt 115 n all mode 7115 1s program counter pc 114 15 the link register Ir 7113 is the stack pointer sp By convention AAPCS EABI gt r4 to r11 are variable registers vl to
42. rol bit 0 l enab l Note Clear the bit in the ADOCR before clearing this bit and set A this bit before setting PDN di S abl e 13 PCCAN1 CAN Controller 1 power clock control bit 0 14 2 CAN Controller 2 power clock control bit 0 18 15 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 19 PCI2C1 The 12 1 interface power clock control bit 20 LCD controller power control bit 0 21 PCSSPO SSPO interface power clock control bit If peripheral is disable read or write register are not valid UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTBELIARD Dynamic memory interface support including Single Data Rate SDRAM Asynchronous static memory device support including RAM ROM and Flash with or without asynchronous page mode Low transaction latency Read and write buffers to reduce latency and to improve performance 8 bit 16 bit and 32 bit wide static memory support 16 bit and 32 bit wide chip select SDRAM memory support Static memory features include Asynchronous page mode read Programmable wait states Bus turnaround delay Output enable and write enable delays Extended wait Four chip selects for synchronous memory and four chip selects for static memory devices Power saving modes dynamically control CKE and CLKOUT to SDRAMs Dynamic memory self refresh mode controlled by software Controller suppo
43. rts 2 kbit 4 kbit and 8 kbit row address synchronous memory parts That is typical 512 MB 256 MB and 128 MB parts with 4 8 16 or 32 data bits per device Separate reset domains allow the for auto refresh through a chip reset if desired Note Synchronous static memory devices synchronous burst mode are not supported UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD AHB SLAVE REGISTER INTERFACE AHB SLAVE MEMORY INTERFACE Fig 15 EMC block diagram DATA BUFFERS MEMORY CONTROLLER STATE MACHINE LU 2 a lt A 23 0 shared D 31 0 signals WE OE static BLS 3 0 memory met signals CS 3 0 DYCSI3 0 CAS RAS dynamic CLKOUTI1 0 memory signals CKEOUT 3 0 DQMOUTI3 0 UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD External NOR FLASH 32 MBit 4 MByte in size addressed by CSO address range 0 8000 0000 0x80FF FFFF Accessed via 16 bit databus External NAND FLASH 1 GBit 128 MByte in size addressed by CS1 address range 088100 0000 Ox81FF FFFF Accessed via 8 bit databus External SDRAM 256 MBit 32 MByte in size addressed by DYCSO address range 0xA000 0000 FFFF Accessed via 32 bit databus LPC2478 45 UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Small SRAM memory between flash and core Allow fast instruction access gt Direct access to flash 15 limited to 20M Hz 50ns access time Load 4 ar
44. s 2 instructions forward the executing one fetch No branch prediction UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD 32 bits RISC instructions gt Register to register or register to immediate operand operations gt CPSR flags are not changed except if explicitly asked gt Load store instruction for moving data from register to from memory register based addressing e Most instructions can be conditionally executed UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1211 10 8 8 7 6 5 4 3 2 1 0 n Data Processing PSR Transfer gogo 0000 m mat ton 9981688181 8 00001086 1 18000 110 0100 0 Cond GERE Halfword Data Transfer register offset 661801 OTT immediate offset 2000007 e k cw m 580 om pru Transfer TEA CP Opc Rm Coprocessor Data Operation Transfer Cond 1 1 1 1 Ignored by processor Software Interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1211 10 9 8 7 6 5 4 3 2 1 0 UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD 16 bits Instructions are more constrained 7 Only 8 registers are code reachable 7 Shortest immediate operands gt Flags are always updated no more explicitly Only
45. s of the currentiy active interrupt Access RO RO RO WO WO 52 maar navy 522 Reset valuel l OxFFFF OxF OxF Address OxFFFF F000 OxFFFF F004 OxFFFF F008 OxFFFF FOOC OxFFFF F010 OxFFFF F014 OxFFFF F018 OxFFFF FO1C OxFFFF F020 OxFFFF F024 OxFFFF F100 OxFFFF F104 OxFFFF F108 Aa rrrr rann UATTTT rare F278 F27C OxFFFF FFOO UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTBELIARD VICSoftInt ORed with interrupt request gt VICSoftIntClear to clear one or more bit in VICSoftInt e VICIntEnable enable soft and hard irq gt VICIntEnClear to clear one or more bit In VICIntEnable VICProtect allow usr mode to access VIC register VICIntSelect contribue to irq 0 or 1 VICIrqStatus VICFiqStatus show active irq fiq request VICVectAddr0 31 isr address for each request lines VICVectPriority0 31 priority for each request lines 0 to 15 with 15 lowest priority e VICAddress address of 151 that is to be serviced 9 9 gt Musts be written at end of isr to acknowledge the IRQ UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTBELIARD e When interrupt N occurs if interrupt is enable irq line 1s asserted If the interrupt line is not masked gt Bit N in VICIntEnable set 7 The current priority is lower than the priority assigned to the corresponding IRQ N The VICVectAddrN of as
46. s the high time of the I C clock I2C1SCLH 0xE005 C010 I2C2SCLH OxE008 0010 I2SCLL SCL Duty Cycle Register Low Half Word R W 0x04 I2COSCLL 0xE001 C014 Determines the low time of the 12C clock I2nSCLL I2C1SCLL OxEOOS C014 and I2nSCLH together determine the clock frequency I2C2SCLL 0 008 0014 generated by 2C master and certain times used in slave mode I2CONCLR 12 Control Clear Register When a one is written to WO NA I2COCONCLR 0xE001 C018 I2C1CONCLR OxEO05 C018 I2C2CONCLR 0xE008 0018 a bit of this register the corresponding bit in the 2 control register is cleared Writing a zero has no effect on the corresponding bit in the I C control register UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD comman d N status UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD e Master Transmitter mode gt Initialize ICONSET clear SI STA STO in IZCONCLR Table 510 I2CnCONSET used to configure Master mode Bit 7 6 5 4 3 2 1 0 Symbol 12 STO SI AA Value a 1 0 0 0 0 7 Set the STA bit SI bit is set when done and new status code Is present in IZSTAT gt Place data in I2DAT register Address for first byte Clear SI and STA Wait for SI set when data has been sent new status code Place new data gt Set STO to end transmission UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD I20CONSET 12 STA while I20CONSET amp PC
47. sector of the flash memory the Boot flash is available to hold part of the Boot Code User Software For LPC2400 parts with flash only Activated by the Boot Loader when Flash activation by a valid User Program Signature is recognized in memory and Boot mode Boot code Loader operation is not forced Interrupt vectors are not re mapped and are found in the bottom of the flash memory UserRAM Software Activated by a User Program as desired Interrupt vectors are mode activationby re mapped to the bottom of the Static RAM User program User Software For LPC2400 parts with flash Interrupt vectors are re mapped to External activation by external memory bank 0 01 memory user code mode Software For flashless parts LPC2420 60 70 only Interrupt vectors are activation by re mapped to external memory bank 0 2 boot code UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Table 20 Memory mapping control registers Name Description Access Reset Address value MEMMAP Memory mapping control Selects whether the R W 0x00 OXEO1F C040 ARM interrupt vectors are read from the Boot ROM User Flash or RAM Table 21 Memory Mapping control register MEMMAP address 0xE01F C040 bit description Bit Symbol Value Description Reset value 1 0 MAP 00 Boot Loader Mode Interrupt vectors are re mapped to Boot ROM 00 01 User Flash Mode Interrupt vectors are not re mapped and reside in Flash Remark This mode is for parts with flash only Value
48. sending an ack bit low level UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD OF DATA DATA VALID 5000361 Figure 5 Bit transfer on the I2C bus pe pa SDA N LL N SDA __ _ SCL 5 START STOP CONDITION CONDITION SU00362 UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD e Transfer from master to slave 7 First byte transmitted by master 1s slave address 7 bits 7 The 8 bit is low signaling a write to the device gt Next follows a numbers of data bytes 7 Slave returns an ACK bit after each received byte s 5 5 ww 0 write 1 read data transferred n Bytes Acknowledge A Acknowledge SDA low Not acknowledge SDA high S START condition P STOP condition from Master to Slave from Slave to Master Fig 112 Format in the Master Transmitter mode UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD e Transfer from slave to master 7 First byte transmitted by master 1s slave address 7 bits 7 The 8 bit is high signaling a read from the device gt Next follows a numbers of data bytes send by the slave 7 The master send a NACK to stop the reading 0 write 1 read data transferred n Bytes Acknowledge A Acknowledge SDA low A Not acknowledge SDA high S START condition P STOP condition E from Master to Slave
49. smission to a Slave transmitter next transfer started with a Repeated Start condition Not Acknowledge received after the Slave address arbitration lost in Slave address or Acknowledge bit arbitration lost and addressed as Slave LI DATA SLA x o LL LA U I 1 other Master LA other Master continues continues other Master to corresponding states in Slave mode from Master to Slave from Slave to Master any number of data bytes and their associated Acknowledge bits this number contained in I2STA corresponds to a defined state of the PC bus Fig 121 Format and States in the Master Receiver mode UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Void IZCISR void switch I2STAT case 0x08 IZCONCLR STA I2DAT I2CAddress break 0 18 I2DAT I2CData break case 0x20 I2DAT I2CAddress break 0 28 I2CONSET STO break default break I2CONCLR 51 VICVectAddr 0 start bit send address slave address ack slave address nack data ack clear Interrupt flag VIC ack UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD DC 16 led driver Controlled by 10 registers e Writing 7 Sending address of the device 0xC0 7 Sending the number of the register 7 Sending data to the device register e Reading 7 Sendi
50. sociated interrupt 1s copied In VICAddress register to be read by software most of time this is the isr address The IRQ or line connected to the core 15 asserted UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD When software read VICAddress 7 the fiq line to the core Is de asserted gt Hardware priority in VIC is set to the highest priority pending here N During the time of irq is serviced by software gt If an irq M with lower priority appears nothing occurs gt If an irq M with higher priority appears same stages as described before activation of irq line copy of VICVectAddrM When interrupt 1 serviced software must write a dummy value in VICAddress This signal the end of the treatment and the Hardware priority in VIC is lowered to the higher pending irq priority UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTBELIARD Table 117 Interrupt sources bit allocation table Bit 31 30 29 28 27 26 25 24 Symbol 25 1262 UART3 UART2 TIMER3 TIMER2 GPDMA SD MMC Bit 23 22 21 20 49 48 47 46 Symbol CAN182 USB Ethernet BOD I2C1 AD0 EINT3 EINT2 Bit 45 44 43 42 41 10 9 8 Symbol EINT1 EINTO RTC PLL SSP1 SPI SSPO I2CO PWMO amp 1 Bit 6 5 4 3 2 1 0 Symbol UART1 UARTO TIMER1 TIMERO ARMCore1 ARMCore0 WDT UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTBELIARD e For vectorized irq each interrupt routine address 15 must be written in VICVectAddr
51. turn from the interrupt This re enables the interrupts UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD 0 18 pc pc 0 120 Load Vector into vector handler Code to enable interrupt nesting STMFD 1131 r0 r3 r12 lr stack registers that will be corrupted by a function call Interrupt service routine BL 2nd level handler this corrupts lr and r0 r3 and r12 Add code to clear the interrupt source JCode to exit handler r13 r0 r3 r12 r14 unstack lr irq and r0 r3 r12 rl VectorAddr STR 10 r1 Acknowledge VIRQ serviced with a dummy write SUBS pc lr 4 Return from ISR UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD 1 An Interrupt occurs 2 The ARM processor branches to either the interrupt vector 3 If the interrupt is an IRQ read the VICVectAddr Register and branch to the interrupt service routine You can do this using an LDR PC instruction Reading the VICAddress Register updates the interrupt controllers hardware priority register 4 Stack the workspace so that you can re enable IRQ interrupts 5 Enable the IRQ interrupts so that a higher priority can be serviced 6 Execute the Interrupt Service Routine ISR 7 Disable the interrupts and restore the workspace 8 Clear the requesting interrupt in the peripheral or write to the VICSoftIntClear register if the request was gener
52. v8 710 to r3 are scratch argument registers al to a4 ML E ED eo m m m j m ow mu we R e e w w ww w ow wo w m w wo w w w ke e b mw s sw s s hb ma Lo L w p 7 ms se m a me m D emo 68 0 NCC om nese euam ee e e e e La DA indicates that the normal register used User System mode has been replaced by an alternative register specific to the exception mode UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD e PSR program state register 7 cpsr current program state register 7 spsr saved program state register only present privileged mode CPSR contains gt ALU flags C V Z N gt land F flags for allowing interrupts gt Processor mode UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD 31 30 29 28 27 26 25 24 23 20 19 16 15 10 9 8 7 6 5 UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD 3 operations per cycles instructions parallelism 7 Fetch instructions fetch gt Decode operands fetch gt Execute integer operation and store PC point
53. x At irq vector address 0x18 instruction load pc with VIC address and so jump to the appropriate isr Vectors LDR PC Reset Addr LDR PC Undef Addr LDR PC SWI Addr LDR PC PAbt Addr LDR PC DAbt Addr NOP Reserved Vector LDR PC PC 0x0120 Vector from VicVectAddr LDR PC FIQ Addr UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD Configuring VIC for UARTO VICIntSelect amp 1 lt lt 6 contribution VICVectAddr6 unsigned long 11811 151 isr address VICVectPriority6 10 priority 10 VICIntEnable 1 lt lt 6 enable uart0 IRQ UNIVERSITE DE TECHNOLOGIE DE BELFORT MONTB LIARD 1 An interrupt occurs 2 The ARM processor branches to either the IRQ interrupt vector 3 If interrupt is IRQ read VICVectAddr Register and branch to the interrupt service routine You can do this using an LDR PC instruction Reading the VICAddress Register updates the interrupt controllers hardware priority register 4 Stack any registers that will be used to avoid any register corruption 5 Execute the service 6 Clear the requesting interrupt in peripheral or write to the VICSoftIntClear register 1f the request was generated by a software interrupt 7 Restore the previously saved register 8 Write to VICAddress Register This clears the respective interrupt in the internal interrupt priority hardware e 9 Re
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