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VM162/VM172

1. JO 0oUUOJ uod eLIase ANS A TUTN STEA JOJDIUUOD qng q UIJ SI Jo SSA Sra Page 3 7 PEP Modular Computers Juli 23 1997 VM162 VM172 Chapter 3 Configuration r 3 3 1 CPU Type e ums uma E 3 3 2 CPU Power Supply EE J12 J15 CPU power is 5 volt 68040 N B CPU power is 3 3 volt 68040V or 68060 3 3 3 CPU Bus Clock Jumper Setting Description JS J7 Set Set CPU Bus clock is 25 0 MHz Set CPU Bus clock is 33 3 MHz 3 3 4 SRAM Size Jumper Seiting Description 20 J19 J20 1 2 1 2 SRAM size is 1 MByte Page 3 8 PEP Modular Computers Juli 23 1997 Chapter 3 Configuration VM162 VM172 Note The above solder jumpers describe the basic configuration of the board They are factory set and should not be altered by the user Alteration of these jumpers can result in damage to the board 3 3 5 Communications Clock oo EE 24 MHz connected to 68EN360 RCLK2 pin Default pf Open 24 MHz disconnected from 68EN360 RCLK2 pin 3 3 6 EEPROM Write Protection The serial EEPROM stores important data such as the PEP assigned Ethernet address In order to pre vent overwriting users may set the protection CCE Lwe NE Serial EEPROM write protected om Serial EEPROM not write protected Default 3 3 7 JTAG Chain
2. Juli 23 1997 PEP Modular Computers Page 2 31 VM162 VM172 Chapter 2 Functional Description 2 10 8 IP Memory Size Control After a board reset the IP Memory Size is set to 8 MB linear address space by default By setting Bit 3 of the IP Slot Control register Memory size bit the linear addressable memory space can be reduced from 8 MB to 1 MB If 1 MB is selected the whole IP memory address space of 8 MB is available further on The currently used memory page 1 of 8 1MB pages is determined by the memory page bits within the Slot Control register Bit 2 0 Note This feature is implemented for compatibility reasons to further IP Carrier boards with reduced address space 2 10 9 IP Interface Address Map IPa Base Address Size Port Width Device HEX CE 00 08 00 128 Byte D8 D16 IP Slot a IO Space CE 00 08 80 128 Byte D8 D16 IP Slot a ID Space CE 00 09 01 128 Byte D8 IP Slot a Interrupt Control register CE 00 09 81 128 Byte D8 IP Slot a Control ragister DO 00 00 00 1 or 8 MB IP Slot a Memory Space IPb Base Address Size Port Width Device HEX CE 00 0A 00 128 Byte D8 D16 IP Slot b IO Space CE 00 0A 80 128 Byte D8 D16 IP Slot b ID Space CE 00 OB 01 128 Byte D8 IP Slot b Interrupt Control register CE 00 OB 81 128 Byte IP Slot b Control ragister DO 80 00 00 1 or 8 MB IP Slot b Memory Space Note Whether 1 or 8 MByte memory address space is selected depends on the memory size bit within the
3. ze ms ee JTAG Chain CPUs included Po quis JTAG Chain CPUs excluded Default Juli 23 1997 PEP Modular Computers Page 3 9 VM162 VM172 Chapter 3 Configuration 3 3 8 SRAM Data Retention The battery backup of the VM162 VM172 is connected to both the SRAM and RTC This jumper gives the user the possibility to disconnect the SRAM from the battery backup giving the RTC longer backup support e Lou eme SRAM data retention is off N B SRAM data retention is on Default 3 3 9 BERRI Timeout This jumper sets the timeout of the BERRI and can be used for debugging purposes J17 J18 J21 E J17 J18 J21 Set Open Open 3 3 10 Backup Current Test Bridge This jumper is reserved for support usage ze es ee RS CET Page 3 10 PEP Modular Computers Juli 23 1997 Chapter 4 Programming VM162 VM172 Programming 4 1 VMIGZAVMI 72 Address Map nus eai dis 4 3 4 2 Initializing the OSENIGO sessie syans ousa GER EKG Ge Se ed eGGSA 4 4 do Jnitializing th EE 4 7 July 19 1997 PEP Modular Computers Page 4 1 VM162 VM172 Chapter 4 Programming m Page 4 2 PEP Modular Computers July 19 1997 VM162 VM172 Address range less than HEX 80 00 00 00 is to be initialized as cachable address areas and address range greater than HEX 80 00 00 00 is to be initialized as non cachable serialized address area Chapter 4 Programming 4 1 VM162 VM172 Address Map Base Address
4. 2 8 1 Ethernet SER4 Port If a network interface such as Ethernet or a fieldbus is required the most upper port on the front panel can be used This port based on SCC1 of the 68360 is physically configured by a so called SI Piggyback SI Piggybacks are available at the moment for the 3 standard Ethernet versions 10Base5 AUD 10Base2 and 10BaseT Additionally an isolated RS485 interface is available with 9 pin D Sub frontpanel con nector which is especially designed for Fieldbus applications available as well as a standard RS232 in terface for more information please refer to the SI Piggyback Appendix in this manual Juli 23 1997 PEP Modular Computers Page 2 21 VM162 VM172 Chapter 2 Functional Description 2 8 2 SER1 SER2 and SER3 Ports The three serial ports based on the SCC2 SCC3 and SCC4 lines of the 68EN360 are configured by de fault as RS232 ports They support full modem handshake and can be re configured by other piggybacks in the SC product line These ports are usually used for communication between systems or to subsy stems modems In addition the signals of SCC2 SCC3 and SCC4 are routed to the CXC This is mainly useful for phy sical adaptions where the application requirements cannot be met using SC piggybacks SERI SER2 and SER3 Pinouts RJ45 Connector N C Not Connected Page 2 22 PEP Modular Computers Juli 23 1997 Chapter 2 Functional Description VM162 VM172 2 8 3 TERM Pin
5. The VM162 VM172 supports three addressing modes which are A32 A24 and A16 The following AM codes according to the standard for VME64 are supported by the VM162 VM172 Table 2 5 External Signal Connection 3E A24 supervisory program access 3D A24 supervisory data access 3A A24 non privaleged program access 39 A24 non privaleged sata access 2D A16 supervisory access 29 A16 non privaleged access tora am A EET nus TEEN EEE A32 non privileged data access Note For the user defined codes IF 18 and 17 10 there are A24 D16 cycles generated by the VM162 VM172 Juli 23 1997 PEP Modular Computers Page 2 9 VM162 VM172 Chapter 2 Functional Description 2 5 1 2 VME Address Map The various combinations of addressing modes and data bus sizes are selected on different address areas within the address map of the CPU The corresponding AM codes are generated according to the Table below Table 2 6 Generated AM Codes VME VME Size VME Address Range CPU Address Range AM Code Cycle Type HEX HEX HEX A32 D32 512 MByte 00 00 00 00 IE FF FF FF AO 00 00 00 BF FF FF FF A32 D16 256 MByte 00 00 00 00 OF FF FF FF 90 00 00 00 9F FF FF FF A24 D32 16 MByte xx 00 00 00 xx FF FF FF 8F 00 00 00 8F FF FF FF A24 D16 16 MByte xx 00 00 00 xx FF FF FF 87 00 00 00 87 FF FF FF A16 D32 64 kByte xx Xx 00 00 xx xx FF FF 8D 00 00 00 8D 00 FF FF 2D 29 A16 D16 64 kByte xx xx 00 00 xx xx FF FF 8
6. Bor memory for the VM162 172 oun Memory Piggyback with 8 MByte DRAM and 4 MByte FLASH Po memory for the VM162 172 e SI6 10B2 IP 10Base2 Thin Ethernet interface piggyback with RG58 coax 16136 connector SI6 10B5 IP 10Base5 Ethernet AUD interface piggyback with 15 pin D Sub 16137 connector Page 1 10 PEP Modular Computers Juli 23 1997 VM172 BASE Chapter 1 Introduction VM162 VM172 Product Description Order Nr 10BaseT Twisted pair Ethernet interface piggyback with RJ45 connector SI6 Front panel without networking interface s 16028 DUMMY IP S16 PB485 IP Optoisolated RS485 interface piggyback with 9 Pin D Sub 16192 connector SI6 10BT IP 16147 SC 2321 Optoisolated RS232 interface piggyback with TxD RxD DTR and 12919 CTS signals and Baud rate up to 38 4 kBaud SC 4851 Optoisolated RS485 interface piggyback for half duplex 13468 communication at a Baud rate up to 38 4 kBaud CABLE RS232 3 meter RS232 Serial Interface cable with RJ45 to 9 Pin D Sub 15191 male for terminal connection Important The VM162 and VM172 must be ordered with a memory module DM60x and a front pa nel with integrated SI6 piggyback module For configurations requiring the 2 x 50 pin D Sub front panel connectors instead of the flat band cable option please contact the nearest PEP sales office for further information 1 8 Related Publications e VMEbus Specifications VME64 e IndustryPack e CXC Specification from
7. Modular Computers vMi62VvMI 2 VMEbus Single Board Computer with Dual IndustryPack Support Manual Order Nr 16596 User s Manual Issue 1 Modular Computers Table Of Contents Chapter Introduction RE koka ek 1 1 LT PRODUCT OVEFVIEW ees starter ee ee Bees 13 1 2 IndustryPack PCY abi kt EE AE ON 13 1 3 Controller eXtension ConnE TOT ee Beds RS AN ke KAK EA 1 4 14 Front Panel and VO Configuration 1 4 L3 EE 1 6 10 RE AE EE ENE 1 8 1 7 Ordering Information EO OE tee 1 10 1 8 Related Publications osse disk a ia ank kan a kk s ki saaa eka bab 1 11 1 9 Schematic Board E suis iden ie di ee vi oe Ge ia kass 1 12 Chapter Functional Description eise drtato etik ko t s kika ni kinan 2 1 21 VMIGZAVMI 72 Block Diagram nisse disease eg ppa 2 3 2 2 CPU NONE ER EE EA N N EN 2 4 RE EE EE ER DNS 2 4 2 3 1 DRAM FLASH ees ee ese ee ese ee ese ee ee ge ee ge ee ge ee ee Gee ge ee ee ee ee Ge ee ee 2 4 DBZ SRAM ce aces cise SE ties teen GR GR GE EG ED Ge RE Ek tk 2 5 2 3 3 Boot ROM optional i nesen ee ee ee ee ee ee ee ee ee 2 5 2 34 EEPROM ARE EE EE EE EE EE OE N 2 6 2 4 Communication Controller 68EN360 QUICC 2 6 2 4 1 Use of GSEN360 Communication Ponts 2 6 2 4 2 Use of GSEN360 Memory Controller ss 2 7 2 4 3 Use of GSEN360 Interrupt Controller ss 2 7 2 4 4 Use of 6SEN360 DMA Chanel 2 8 2 3 E 2 8 2 5 1 VME Master InterfdCe isssssts kes nov see See mi piyon ya dit is na in 2
8. SPIMOSI SPICLK _SPISEL Row C Signals Serial receive data input to the SCCs 7 Serial transmit data output from the SCCs 0 Request to send outputs indicate that the SCC is ready to transmit data 0 Clear to send inputs indicate to the SCC that data transmission may begin D Carrier detect inputs indicate that the SCC should begin reception of data 1 This output from SCC1 identifies the start of a receive frame Can be used by an Ethernet CAM to perform address matching O This input to SCC1 allows a CAM to reject the current Ethernet frame after it determines the frame address did not match J Input clocks to the SCCs SMAs SI and the baud rate generators 1 A request input to an IDMA channel to start an IDMA transfer 1 An acknowledgement output by the IDMA that an IDMA transfer is in progress 0 A bidirectional signal that indicates the last IDMA transfer in a block of data 1 0 An input to a timer that enables disables the counting function 1 Time reference input to the timer that allows it to function as a counter 7 Output waveform pulse or toggle fromn the timer as a result of a reference value being reached 0 Serial data input to the SPI master 1 serial data output from an SPI slave O Serial data output from the SPI master O serial data input to an SPI slave Output clock from the SPI master O input clock to the SPI slave 1 SPI slave select input
9. Table 2 3 68EN360 CS Line Connection CS5 CXC CS6 RTC CS7 Board Register Note In order to be compatible with the above configuration the board initialization described in the Programming Chapter must be closely adhered to 2 4 3 Use of 68EN360 Interrupt Controller The 68EN360 internal interrupt controller is one part of the VM162 VM172 interrupt control logic The 68360 internal interrupt controller provides programmable interrupt vectors for all internal interrupt re quests For detailled description of these interrupts please refer to the 68EN360 User s Manual Additionally some external signals are connected with 68EN360 dedicated interrupt inputs Signals at this inputs are processed by the 68EN360 to generate autovectored interrupt on fixed levels to the CPU These signal are summarized below Table 2 4 External Signal Connection Generated Autovector ABORT ACFAIL 7 Mailbox SYSFAIL Reserved Reserved Juli 23 1997 PEP Modular Computers Page 2 7 VM162 VM172 Chapter 2 Functional Description Note In order to be compatible with the above configuration the board initialization described in the Programming Chapter must be closely adhered to VME ACFAIL generates a non maskable autovector level 7 interrupt NMI in the same way as the AB ORT button When an ACFAIL NMI is detected it can be differentiated from an ABORT by reading bit 1 of the Board Configuration Register 2 4 4 Use of 68EN
10. 7 Configure CLK lines e COM to full strength e COMI disabled e register access locked OxFF B gt RSR 0x7 B gt SYPCR 0x60008CB3 L gt MCR 0xC000 W gt PLLCR 0x8000 W gt CDVCR 0x83 B gt CLKOCR PEP Modular Computers July 19 1997 Chapter 4 Programming 8 Configure PEPAR register e set IOUTO 2 are PRTYO 2 select RAS1DD function select WEO 3 select AMUX select CASO 3 9 Configure GMR register e set refresh counter period to 24 set refresh cycle length to 3 set DRAM port size to 32 bit assert CS RAS on CPU space enable refresh 10 Configure autovector register e enable autovector on levels 2 3 5 and 7 11 Configure Chip Select lines General Example VM162 VM172 0x51C0 W gt PEPAR 0x18800100 L gt GMR OxAC B gt AVR Note It is important that the Chip Select lines are initialized in the sequence shown below It should also be noted that the following values need to be changed for various configurations of the on board memory see note below CS0 CS0 CSL CS1 CS2 CS2 CS3 CS3 CS4 CS4 FLASH to 0x4000000 negate timing 040 size to 16 MByte port size 32 bit tcyc 3 size to 64 MByte port size 32 bit tcyc 0 bcyc 1 DRAM to 0x0 burst acknowledge 040 size to 16 MByte port size external tcyc DMA VME to 0x87000000 size to 16 MByte port size external tcyc AutoBahn to 0x9000000 size to 16 MByte port size ext
11. but dispense with the usual restrictions associated with serial communication Application specific tailoring is assured through versatile interface options which together with PEP s CXC interface makes this 6U VMEbus CPU ideally suited for communication and automation applica tions With up to 6 serial interfaces resident within the same realestate and support for standard LAN or WAN interfaces provided communicational versatility is guaranteed Two on board EPROM sockets are designed to accommodated ROMed applications and or the PEPbug debug monitor The VM 162 172 is supplied with these sockets empty and the PEPbug programmed into the FLASH memory residing on one of the DM6xx memory piggybacks The PEP VM162 172 Board Support Package is available for several popular real time operating sy stems OS 9 VxWorks VRTX OS and pSOS 1 2 IndustryPack Flexibility Fully integrated within the VM162 172 CPU boards are two IndustryPack carrier interfaces Each inter face accesses an 8 16 bit databus and supports IP class 1 modules The IP concept is based on an open specification allowing vendors to fabricate an independent library of digital analog communication or counter mezzanine plug in modules for example that are compati ble with carrier boards from manufacturers like PEP With a few hundred such mezzanines currently available users can easily find the appropriate interface to a wide variety of industrial requirements In accor
12. with SI6 PB485 ISO piggyback Each of the piggyback options is described in the following Sections Ordering Information Name SI6 10B2 SI6 10B5 SI6 10BT SI6 DUMMY SI6 PB485 ISO Description 10Base2 Thin Ethernet cheapernet interface with RG58 coax connector 10Base5 AUD Ethernet interface piggyback with 15 pin D Sub connector 10BaseT Twisted pair Ethernet interface piggyback with RJ45 connector Front panel without network interface s 6 50 pin D Sub ModPack signal output RS485 optoisolated interface piggyback for 2 wire half duplex e g PROFIBUS connection with 9 pin D Sub connector Order No 15058 15059 15060 15061 Juli 23 1997 PEP Modular Computers Page SI6 1 Appendix SI6 Piggybacks 1 SI6 10B2 The SI6 10B2 is a physical Cheapernet 10Base2 interface to the 68EN360 Controller chip It connects one of the range of PEP CPU boards to a 50Q coax cable via an RG58 BNC T connector The SI6 10B2 has two LEDs fitted a red LED indicates collision detection and a yellow LED for data 1 1 Specifications On board termination None Cheapernet cable is terminated at both ends Max Baud Rate 10 Mbit s as specified by Ethernet 1 2 Connector FO gt Collision 89 Data ol Tx 10Base2 RG58 BNC T Connector ETHERNET Page SI6 2 PEP Modular Computers Juli 23 1997 2 SI6 10B5 Appendix SI6 Piggybacks The SI6 10B5 is a physical AU
13. 00 J3 00 J3 00 J2 00 Ji J50600 213 Jumper JI and J2 End Of Line Termination ER E No internal line termination Default Internal line termination Jumper J3 and J4 Idle Setting Es NEG No internal idle status Default Internal idle status Jumper J5 Isolating Voltage Supply EN Ss Isolating VCC supplied internally Default Isolating VCC supplied externally Jumper J Received Control PES Receive permanently enabled Default Receive enabled Juli 23 1997 PEP Modular Computers Page SI6 7 Appendix SI6 Piggybacks e This page has been intentionally left blank Page SI6 8 PEP Modular Computers Juli 23 1997 Appendix Bootstrap Loader APPENDIX BOOTSTRAP LOADER FOR VM 6 62 VM 6 42 VSBC 32 AND IUC 32 1 Introduction The Bootstrap Loader is a stand alone software located in FLASH memory which allows the user to safely update the con tents of the FLASH and delay the boot process for a specified time The Bootstrap Loader has the capability of programming FLASH memory from MOTOROLA S records or from an abso lute address If the programmed image does not work the Bootstrap Loader can be entered again The memory contents can be examined and another programming cycle initiated The Bootstrap Loader is delivered already installed in DM60x memory piggybacks Please read this user manual before reprog amming any FLASH memory WARNING When programming FLASH memo
14. 5 VM162 VM172 Chapter 1 Introduction 1 5 Features Page 1 6 CPU Options The 68060 processor operating at 50 Mhz provides the highest performance while the 68040 V at 33 MHz sets the standard in the Motorola CISC portfolio 68EN360 The OUICC chip operates as an I O and communication companion providing 4 high speed serial channels timers clocks and Time Slot Assignment TSA Serial Channels All high speed SCC channels are equipped with hardware hand shaking and are available for a variety of applications SCC1 can be configured for either ethernet or RS485 e g PROFIBUS use by fitting the appropriate SI6 piggyback SCC2 SCC4 are configured by default for RS232 operation and can be changed to optoisolated RS232 485 as required by fitting the SC piggyback An SMC1 interface provi des a simple RS232 connection for console debug operations Figure 1 2 MC68EN360 Channel Assignment MC68EN360 Channel Em Assignment ISI Piggyback Interface SI Interface oopopoopooooooo MC68EN360 RS232 with Rx and Tx only Real Time SCC2 SCC3 SCC4 SC Piggyback Interfaces 3x Serial Interfaces for SC Piggyback And CXC DESEN OO OO ars o nono EER EE ano e 0 0 EE CXC Interface CXC Interface The 96 pin interface allows other I O possibilities to be realised by utilising PEP s plug in cards such as the CXM PFB12 CXM CAN CXM LON CXM SCSI or CX
15. 7 Juli 23 1997 PEP Modular Computers Page 2 29 VM162 VM172 Chapter 2 Functional Description 2 10 IndustryPack IP Interface 2 10 1 Overview The VM162 177 interface up to two IndustryPacks IPs referred as Pa and IPb The implementation of the IP interfaces is according to the VITA 4 standard for IP modules The VM162 177 referred also as IP Carrier in this chapter interfaces the two IP slots through a pro grammable IP controller Through this controller a lot of operating functions can be controlled individually per slot For example IP bus speed interrupt priority memory space Reset etc can be programmed individually per IP slot The base addresses for the different IP address spaces like I O ID and memory space are fixed within the address map 2 10 2 Features e upto standard IPs or 1 double sized IP e supports I O ID Memory and Interrupt Acknowledge cycles e supports 8 bit and 16 bit IP cycles e IP slot control register set of two per IP slot e programmable IP bus speed 8 or 32 MHz e individual IP bus speed per slot e 2 interrupts per IP programmable level from 1 to 7 e up to 8 MB linear memory space per IP programmable e separate buffers for each IP slot for data clock and control signals e overload protection fuse separate per IP slot 2 10 3 Optional IP features not supported Page 2 30 e 32 bit IP cycle e DMA transfer compelled DMA Note Since the VM162 17
16. FLASH Each of the piggyback options are described in the following sections Ordering Information Name Description Order No DM600 Memory piggyback with 4 MByte DRAM and 1 MByte FLASH 11852 DM601 Memory piggyback with 16 MByte DRAM and 1 MByte FLASH 11854 DM601 Memory piggyback with 16 MByte DRAM and 4 MByte FLASH 11855 DM602 Memory piggyback with MByte DRAM and 1 MByte FLASH 12765 DM603 Memory piggyback with 32 MByte DRAM and 512 kByte FLASH 13027 DM603 Memory piggyback with 32 MByte DRAM and 4 MByte FLASH 13627 DM604 Memory piggyback with 8 MByte DRAM and 1 MByte FLASH 15911 DM604 Memory piggyback with 8 MByte DRAM and 4 MByte FLASH 15912 PEP Modular Computers July 19 1997 Page MEM 1 Appendix Memory Piggybacks 1 DM600 The DM600 is a memory piggyback fitted with 4MByte DRAM and either 1 or 4MByte FLASH 1 1 Jumper Location Re 1 000 4 2 3 FLASH Bank 0 Bank 1 Jumper J1 Flash Write Protection Setting Open 12 Page MEM 2 Descirption All Flash EPROM write protected No Protection Default Flash bank 1 write protected Default address range Flash bank 0 write protected Default address range 1 MB FLASH 8 x 29F010 upper 512 kB 4008000 40100000 lower 512 kB 4000000 40080000 4 MB FLASH 8 x 29F040 upper 2 MB 4020000 40400000 lower 2 MB 4000000 40200000 PEP Mo
17. HEX 00 00 00 00 04 00 00 00 07 00 00 00 0A 00 00 00 OB F7 00 00 OC 00 00 00 OD 00 00 00 40 00 00 00 82 00 00 00 83 00 00 00 85 00 00 00 87 00 00 00 8D 00 00 00 8F 00 00 00 90 00 00 00 AO 00 00 00 BO 00 00 00 CO 00 00 00 C4 00 00 00 C7 00 00 00 CA 00 00 00 CB F7 00 00 CC 00 00 00 CD 00 00 00 CE 00 08 00 CF 00 0A 00 DO 00 00 00 DE 00 00 00 DF 00 00 00 Size max 64 MB max 64 MB 4 KB max 1 MB 64 KB 2 KB 2 KB 256 MB max 64 MB max 64 MB 4 KB max 1 MB 64 KB 2 KB 2 KB 1 KB 1 KB Device DRAM FLASH reserved reserved reserved reserved reserved reserved reserved 68360 SRAM CXC RTC Register IPa IPb Description 68360 CS1 DRAM on DM60x 32 bit 68360 CSO FLASH on DM60x 32 bit 68360 internal RAM REG mirrored 68360 CS4 mirrored SRAM 68360 CS5 mirrored CXC 68360 CS6 mirrored RTC 68360 CS7 mirrored Board Regs Area Optional Boot ROM 16 bit VMEbus A24 D16 type AM 1F 18 VMEbus A24 D16 type AM 17 10 VMEbus A16 D16 type AM 2D 29 VMEbus A24 D16 type AM 3E 3D 3A 39 VMEbus A16 D32 type AM 2D 29 VMEbus A24 D32 type AM 3E 3D 3A 39 VMEbus A32 D16 type AM 0E 0D 0A 09 VMEbus A32 D32 type AM 0E 0D 04 09 VMEbus A32 D32 type AM 0E 0D 0A 09 68360 CS1 mirrored DRAM 68360 CSO mirrored FLASH 68360 internal RAM REG 68360 CS4 SRAM 68360 CS5 CXC 68360 CS6 RTC 68360 CS7 Board Regs Area IndustryPack slot a I O area amp control In
18. IP Interrupt Control iese ts Skeer ven DEE Re Ee Gee Se ee Ee WEE Ge Oe Ee epav sak 2 31 2 10 8 IP Memory Size COOL uses se esse ese bene SN ESEG bee se Ge Be ee AE ER EG EG EES SA gee 2 32 2 10 9 IP Interface Address Map ss 2 32 2 10 10 IP Interrupt Control Register se ee ee ee ee ee ee Ge ee se 2 33 2 10 11 IP Slot Control Register Ge Ge ee ee ee ee ee ee Ge ee ee 2 34 2410 12 AP CONNOCHONS EE ER EE EE IE EE EE pa 2 35 Chapter MT N NE Aa N AG 3 1 Default Jumper E 3 3 3 1 1 Jumper Default Settings Component Side 3 3 3 1 2 Jumper Default Settings Solder Side 3 3 3 2 Jumper Description Component Side 3 4 Se VMEBOO eene ee 3 5 3 22 EE N EE EE EEN 3 5 3 2 3 Protective Ground Signal Ground 3 5 3 2 4 VME SYSRES RR dca nen geste ava EE OE ER 3 5 329 E e 3 6 3 3 Jumper Description Solder Side 3 7 FIL EA 3 8 332 CPU Power Supply EE 3 8 ntents PEP Modular Computers Juli 23 1997 Table Of Contents 313 CPU Bus EE 3 8 334 SRAM AS OO RE RE EE Eed 3 8 3 39 COMMUNICATIONS ClOCK cr cscvsssssiesdvssssvesseihsvsiisiadecvsbasasdvetsdoodeassaessbentstiesssaeessis 3 9 3 3 6 EEPROM Write Protection siennes 3 9 3 37 AE ELE ORE OD OE N OE HO 3 9 3 3 8 SRAM Data Retention sisi 3 10 33 9 BERRI TIMe OUl sw siviosvviotvovosssyon ged iaa A ee Ed ee sansa EES GERS yon 3 10 3 3 10 Backup Current Test Bridge 3 10 Chapter Propram mming OO EE dees ESSE 4 1 4 1 VMIOZ VMA72 Address Man insir
19. P IRQS is placed within the VME Control Status Register Setting this bit ge nerates an autovectored 5 interrupt on the CPU Typically the on board CPU resets P IRQS during processing the corresponding interrupt service routine Notes The complete VME Control Status Register can be read also from an external VMEbus Master It is addressed on every odd address of the lowest 8 kByte block of the VME board address Only the mailbox interrupt P IRQS can however be set all other bits are write protected from the VME As the P IRQS bit is located at bit 7 of the register it can be directly used as a semaphore due to the fact that Read Modify Write access is supported Although the VM162 VM172 cannot access itself via the VMEbus setting the mailbox interrupt bit on the local side also generates the interrupt to the CPU Juli 23 1997 PEP Modular Computers Page 2 11 VM162 VM172 Chapter 2 Functional Description 2 5 4 VME Address Map from the VME Side The Table below shows the VME board address map for external Master access dependent on the setting of the board address bits within the VME Control Status Register Table 2 7 VME Address Map Board Address Board VME Base Bits Address HEX BADRI3 0 DENDE EEN EE EDE NN EET Er N gee ET TT aw ere DEENSE EDE ETES ENNAN ELE EEN EE ETES wwe ET noeneen gt oram ET CE TE US Note All of the possible board address ranges are located in VME A24 D16 addressing mode It is
20. PEP Version 1 5 or later Juli 23 1997 PEP Modular Computers Page 1 11 VM162 VM172 Chapter 1 Introduction 1 9 Schematic Board Layout lelelelelelelelelelelelslelie 2 000 000 SI6 Piggyback DP SRAM sd MC68040 V A 256 kByte ETHERNET PBs OE SI6 10B2 W MC68060 PROCESSOR SI6 10B5 ad SI6 10BT MC68EN36 N DP SRAM SI6 PB485 ISO 1 MByte Nnectoreseesesees O RJ45 RJ58 or 15 Pin D Sub Connector lellelellslelellslelslelellelelie EE 6 VME Connector P1 RTC 1 kbit EEPROM eagesesa lelelelelslsls RJ45 Mini D Sub controller J Mee ROMI Master slavd optional interface Serial port Connectors Memory Piggyback DM6xx SC Piggyback Interface Oo OO Do IndustryPack A seseseseseseseooe oeeeoeeoeoeeoeee eeeeeeeeeeeeeeeee VME Connector P2 IndustryPack B The IP I O is routed to 2 x 50 pin row connectors on the base board A version with 2 x 50 pin D Sub connectors on the front panel for IP I O may be ordered as an option Page 1 12 PEP Modular Computers Juli 23 1997 VM162 VM172 Chapter Functional Description 2 1 VM162 VM172 Black DETOU oase dese ata ka kiba ki sa da kd 2 3 e
21. SEL other than PBO is used SPI RxD can be used if an SPI SEL other than PBO is used See 68360 User Manual Used on board SMC2 Transmit See note 1 Used on board SMC1 Transmit See note 1 Used on board SMC2 Receive See note 1 Used on board SMC1 Receive See note 1 1 On a standard VM162 VM172 board these signals are already used for UART ports at BU7 and BUS 2 On a standard VM162 VMI72 board these signals are used for SPI to which the EEPROM is already connected PBO is chip select of the EEPROM 3 On PAIS a 24 MHz clock signal is routed via jumper J11 This signal is always needed for PEP standard software serial drivers Dual Functioning Signal Pins 4 These signals are routed both to the base board SI Interface connector ST5C and the CXC con nector and can only be used by one or the other and not both at the same time Due to this a conflict exists if the SCC4 port is to be used with the 1232 piggyback and CXC boards such as CXM SIO3 as both boards access this port The SCC4 port can therefore not be used at the same time by SI piggybacks and CXC boards Juli 23 1997 PEP Modular Computers Page 2 27 VM162 VM172 Chapter 2 Functional Description The CXC ports SER1 SER2 and SER3 are equivalent to ports SCC2 SCC3 and SCC4 resp on the 68xx360 With regard to special CXC capabilities the CXC pinout on the VM162 VM172 has been developed to provide maximu
22. and SRAM is gained with two Gold Caps each with a value of 0 22 Farad In contrast to Lithium cells Gold Caps do not require servicing This short term backup is inten ded for short power failures or for reconfiguring systems An empty Gold Cap needs approximately three hours to charge up with backup times dependant on the temperature memory size and memory manufacturer tolerances A well charged Gold Cap provides a minimum of 10 hours backup time Laboratory tests at PEP indicate a typical backup time of 1 week for both 256kB and IMByte SRAM plus RTC typical onboard backup current is 2 HA Long term data retention is made via the VMEbus 5V Stby line With respect to the VM162 VM172 this voltage can drop to 2 5V with the typical current via the 5V Stby being 30uA at 3V Notes The VM162 VM172 board can be removed from the system and plugged in again without lo sing any information Data retention switches from the VME 5V Stby to the on board Gold Caps au tomatically The on board Gold Caps are continuously reloaded via the 5V Stby line The 5V Stby current is typically 7mA for a few minutes when the Gold Caps are at the beginning of the loading phase fully dischaged 2 7 7 Front Panel Buttons and LED Ports Figure 2 1 LED Port and Button Location Watchdog LED Yellow User General Purpose CPU HALT or RESET Green Red RESET Switch ABORT Switch 2 7 7 1 RESET ABORT Button A RESET button is fitted to the front pa
23. and is accessed over the SPI Serial Peripheral Interface of the 68EN360 1 kbit of this EEPROM memory is free for application relevant data whereas the rest of this EEPROM is reserved This part is used for storing board ID codes Internet Ethernet addresses and boot informa tion Note For more information on the EPROM type please refer to the XICOR X25C02 data sheet For EEPROM internal address mapping also refer to the Programming Chapter in this manual 2 4 Communication Controller 68EN360 QUICC The 68EN360 QUICC Quad IntegratedCommunication Controller serves as an I O controller proces sor on the VM162 VM172 This device is especially optimized for serial communication Therefore it provides an unique internal hardware architecture and supports a variety of communication protocolls and operating modes In addition the QUICC is used for some on board system functions such as DRAM control Tick gene ration and address decoding by operating in the so called companion mode In this mode its own CPU32 core is disabled whereas all other features including its Communication Processor Module CPM are still available In terms of communication tasks the QUICC works as a co processor to the CPU Its internal commu nication hardware is built up with a command programmable Communication Processor 14 dedicated DMA channels 4 Serial Communication Controllers SCC 2 Serial Management Controllers SMC and a Time Slot Assigne
24. enables any cache present they should be invalidated using cinva bc Furthermore the complete address range should not be cachable as caching only makes sense on DRAM and FLASH EPROM Other areas should never be cached and must be switched to serialized in order to prevent the MC68040 MC 68060 from mixing up read and write cycles The easiest way of doing this is to make use of the DTTO register in the following way 807FE040 di dil dtto move l movec The code above sets all addresses below 80000000 to cacheable and non serialized whereas all addresses above are set to non cacheable and serialized July 19 1997 PEP Modular Computers Page 4 7 VM162 VM172 Chapter 4 Programming Accesses to the DRAM and FLASH should be made at 0 and 4000000 All other components addres sed by the MC68EN360 should always be accessed over the mirrored area with Cxxxxxxx as descri bed in the Address Map Section Page 4 8 PEP Modular Computers July 19 1997 Appendix Memory Piggybacks APPENDIX MEMORY PIGGYBACKS A number of piggybacks have been developed for PEP s range of CPU boards to enhance their memory capabilities DM600 piggyback with 4 MByte DRAM and 1 or 4 MByte FLASH e DMO60Ipiggyback with 16 MByte DRAM and 1 or 4 MByte FLASH e DM602 piggyback with 1 MByte DRAM and 1 MByte FLASH e DM603 piggyback with 32 MByte DRAM and 1 or 4 MByte FLASH e DM604 piggypack with 8 MB DRAM and 1 or 4 MByte
25. for ser0 only pf ser0 7 Page BOOT 8 PEP Modular Computers Juli 23 1997 Set the stopbits field to 2 for sert pf ser0 2 4 5 Reset System Syntax rs Description This command exits the Bootstrap Loader and resets the system It terminates the Bootstrap Loader command mode and resets the complete system generating a system reset with the on board watchdog 4 6 Help Syntax or help Description This command prints the online help page Appendix Bootstrap Loader e This page has been intentionally left blank Page BOOT 10 PEP Modular Computers Juli 23 1997 Appendix CXC Controller eXtension Connector APPENDIX CXC CONTROLLER EXTENSION CONNECTOR The Controller eXtension Connector CXC is the local interface It contains a 16 bit data bus 7 address lines and 8 deco ded chip select lines Each select line has 256 bytes In total there are 8 select signals 1 CXC Address Range 2000 CXC CS7 BUO 1C00 CXC CS6 BU8 1800 CXC CS5 BU7 1400 CXC CS4 BU6 1000 CXC CS3 BU5 C00 CXC CS2 BU4 800 CXC CS1 BU3 400 CXC CS0 BU2 CXC BU1 is the controller slot On 5S 8S and 8ES for CXM STAT1 only Juli 23 1997 PEP Modular Computers Page CXC 1 Appendix CXC Controller eXtension Connector p 2 CXC Generic Pinouts Pin Number user defined SER3_CD SER3_TXD 9 user defined GND SER3_RXD 10 IRO 1 IRQ 2 IRQ 3 IRQ 4 user def
26. low cost and also low power version The Table below summerizes the differences between the CPU versions Table 2 1 CPU Options Integer CPU Type Performance Dhrystone 68060 50 y 133779 Floating Point Performance Wheatstone 18 28 high performance es yes Note Performance data based on the same test for all CPU versions of the VM162 VM172 is intended to demonstrate the performance ratio between them The above measurements have been made under the OS 9 operating system version 3 0 with the Ultra C compiler version 1 3 1 2 3 Memory 2 3 1 DRAM FLASH DRAM and FLASH memory is combined on a piggyback with addressing capabiltity for up to 64 MBy tes each It provides a fast 32 bit data access with DRAM Burst support It provides also in system FLASH programming facility thus ROM upgrades are easy and cost effective by simply overwriting existing stored data in FLASH Hardwired write protection of FLASH can be optionally selected by jumper The Table on the following page summarizes the variety of DRAM FLASH modules present available refer also to the Memory Piggybacks Appendix Please consult your sales representative for other pos sible applications Page 2 4 PEP Modular Computers Juli 23 1997 Chapter 2 Functional Description VM162 VM172 2 3 2 2 3 3 Table 2 2 DRAM FLASH Options Name DRAM Size FLASH Size DM600 4 MByte 1 or 4 MByte DM601 16 MByte 1 or 4
27. part of the original guarantee or any new guarantee to cover the repaired or replaced items will be transferred to cover the new or repaired items Any extensions to the original guarantee are considered gestures ofgoodwill and will be defined in the Repair Report returned from PEP with the repaired or re placed item Other than the repair replacement or refund specified above PEP Modular Computers will not accept any liability for any further claims which result directly or indirectly from any warranty claim We specifically exclude any claim for damage to any system or process in which the product was employed or any loss incurred as a result of the product not functioning at any given time The extent of PEP Modular Computers liability to the customer shall not be greater than the original purchase price of the item for which any claim exists PEP Modular Computers makes no warranty or representation either expressed or implied with respect to its pro ducts reliability fitness quality marketability or ability to fulfill any particular application or purpose As a result the products are sold as is and the responsibility to ensure their suitability for any given task remains the purchaser s In no event will PEP be liable for direct indirect or consequential damages resulting from the use of our hardware or software products or documentation even if we were advised of the possibility of such claims prior to the purchase
28. 2 baud 19200 parity n data 8 stop 1 Target pf ser0 19200 1f o 4000000 Host type bootrom hex gt com2 In both examples the programming can be monitored over the term port The characters displayed have the following meaning er Read S record valid and in range et Protected sector touched ee Erase sector ec Copy to buffer program later ep Program record Page BOOT 4 PEP Modular Computers Juli 23 1997 Appendix Bootstrap Loader None of the above characters indicate an error The first sector which includes Reset SP PC and the last sector which includes the Bootstrap Loader itself are protected These sectors are not immediately programmed like the other sectors The contents of these protected sectors are buffered in RAM and programmed at the end of the operation This is done to limit the time the Bootstrap Loader itself is not in FLASH or not startable because if the Bootstrap Loader crashes during this critical period of time it will not start again afterwards WARNING When programming FLASH memory NEVER press the RESET button or cycle power This may da mage the Bootstrap Loader and will consequently leave the board unusable due to damaged FLASH contents The ABORT button may be used to cancel a running operation q suppresses all messages and warnings except error messages Programming over the term port is also supported but in this case the loader programs in the background by default and
29. 2 SPIMOSKSPITXD RRJCT2 PB3 SPIMISO SPIRXD BRGO4 PB8 SMSYN1 DREQ2 PB16 BRGO3 STRBO PB9 SMSYN2 DACK2 PB17 RSTRTI STRBI VCC _CS CXC CSS of 68360 _AS R _W _UDS _LDS VCC Al A2 A3 A4 AS o A Ch EO ra DO D1 D2 D3 D4 D5 PA8 CLK1 BRGO1 LIRCLKA TIN1 PA10 CLK3 BRGO2 L1TCLKA TIN2 GND PA3 TXD2 PB13 _RTS2 L1ST2 GND PB15 _RTS4 _L1RQA_LIST4 PC11 _CD4 _LIRSYNCA GND PA2 RXD2 PB10 SMTXD2 L1CLKOB GND PC6 _CTS2 PC7 _CD2 _TGATE2 GND PC10 CTS4 LITSYNCA SDACK1 _SYSR GND _EDTACK 16 MHz CLOCK GND _CXC CS0 _CXC CS1 GND A6 A7 D6 D7 D8 D9 PB6 SMTXD1 DONEI PBS BRGO2 DACKI PB4 BRGO1 _DREQ1 PB11 SMRXD2 LICLKOA PA14 CLK7 BRGO4 TIN4 PA15 CLK8 _TOUT4 L1TCLKB VCC PA7 TXD4 LIRXDA PA6 RXD4 LITXDA PB7 SMRXD1 _DONE2 PC9 CD3 LIRSYNCB PB14 RTS3 LIROB LIST3 PC8 CTS3 LITSYNCB SDACK2 VCC PA12 CLK5 BRGO3TIN3 PA13 CLK6 _TOUT3 LIRCLKB BRGCLK2 PAS TXD3 LIRXDB PA4 RXD3 LITXDB VCC _CXC CS2 _CXC CS3 _CXC CS4 _CXC CS5 _CXC CS6 _CXC CS7 VCC D10 D11 D12 D13 D14 D15 Page 2 24 PEP Modular Computers Juli 23 1997 Chapter 2 Functional Description 68302 HW Compatible 68 EN 360 Port VM162 VM172 Comment Pin Nr CXC 68302 HW 68 EN 360 Comment Function Compatible Port els fe LS maja fe Im CXC Function 68302 HW 68 EN 360 Compatible Port PA10 bl Yes DAN b2 Yes al3 Yes b13 Yes PC6 14 Yes PC7 Pin N
30. 360 DMA Channels The 68EN360 includes altogether 14 DMA channels which are dedicated to the communication ports SDMA and 2 independant DMA channels DMA With the IDMAs memory to memory transfers are possible with any combination of onboard and A24 D16 VME addresses Note In order to be compatible with CPU VME and DMA VME transfers the board initialization des cribed in the Programming Chapter must be closely adhered to 2 5 VMEbus Interface The VM162 VM172 has a complete VMEbus Master interface with arbiter system clock driver power monitor with system reset driver ACK daisy chain driver and a 7 level VMEbus interrupt handler The VM162 VM172 VMEbus Master interface supports A32 A24 and A16 addressing modes in any combination with D32 D16 and D8 data bus width Arbitration is single level FAIR on BR3 Used as system controller the board has to be placed in slot 1 of the VMEbus backplane furthermost left slot VMEbus system signals ACFAIL and SYSFAIL are processed by the VM162 VM172 to autovecto red interrupt requests see also the Use of 68EN360 Interrupt Controller Section In addition the board provides also a VMEbus Slave interface which consists of a dual ported RAM with programmable board address and a mailbox interrupt facility Page 2 8 PEP Modular Computers Juli 23 1997 Chapter 2 Functional Description VM162 VM172 2 5 1 VME Master Interface 2 5 1 1 Supported Data Transfer Types VMEbus AM Codes
31. 5 00 00 00 85 00 FF FF Note The A32 VME addressing modes begin at VME offset 0 independent of their location within the CPU address map Supervisor use or program data AM codes are generated dependent on the type of CPU access that is running 2 5 2 System Controller Functions 2 5 2 1 Automatic First Slot Detection During power up the VM162 VM172 automatically detects if the board is placed in the far left slot of the system If so it acts automatically as the system controller Note This information is stored in the FSD First Slot Detection bit within the VMEbus Control Status register 2 5 2 2 SYSCLK Generator The VMEbus SYSCLK driver of the VM162 VM172 is controlled directly by the FSD bit That means if the board has detected itself as system controller it will automatically drive SYSCLK to the VME bus If it has detected not to be system controller its SYSCLK driver is automatically disabled Note The system integrator has to ensure that there is only one SYSCLK driver active for the whole sy stem This is especially important where boards with jumper enabled SYSCLK drivers are mixed with VM162 VM172 boards Page 2 10 PEP Modular Computers Juli 23 1997 Chapter 2 Functional Description VM162 VM172 2 5 2 3 SYSRES Generator The VM162 VM172 contains a power monitor which generates on board system reset signal after the on board voltage falls below 4 65 V This on board system reset can also dri
32. 7 provides two independant DMA channels which can also be used for me mory to memory transfere all over the board these DMAs can also be used to transfer data to the IPs From the IPs point of view these transfers do not differ from cycles initiated by the CPU PEP Modular Computers Juli 23 1997 Chapter 2 Functional Description VM162 VM172 2 10 4 IP Interface Controller The IP interface controller builts the bridge between the local CPU and the IP bus Therefore it synchro nizes IP bus cycles with CPU cycles and performs the corresponding bus protocols Besides the IP interface controller provides a set of two control registers Each set is dedicated to one IP slot With these control registers reset interrupt control bus speed and memory space can be control led individually for each IP slot Electrically the IP interface controller consists of a FPGA and external high performance buffers for IP bus and control signals 2 10 5 IP Reset Control By setting resetting bit 4 of the IP slot control register an IP module can be enabled or disabled at any time The Reset Control Bit reflects directly the status on the reset line low active Note After a board reset e g power up VME SYSRES Watchdog the IP reset line becomes active by default low active Therefore the Reset Control Bit has to be set to 1 in advance to further operations with the IP module 2 10 6 IP Clock Control After a board reset the IP clock is se
33. 9 2 5 2 System Controller Functions ss 2 10 2 5 3 VME Slave Interface oui uses sse seke kosse gek Rees se ES Ee ee eek as ssri ee dean spin ek 2 11 2 5 4 WME Address Map from the VME Side eres 2 12 2 5 5 WME Control Status Register 2 13 2 0 Baard Control LOGIC nina 2 14 2 6 1 Boot Decoder LOPIE da EER EE ged iiss vine yin LAS De eek de cout Re ee 2 14 2 6 2 Interrupt Control is Bake EE KA OE ET Er 2 14 Juli 23 1997 VM162 VM172 PEP Modular Computers Page TOC 1 VM162 VM172 Table of Co Page TOC 2 2 03 EE 2 16 2 6 4 Watchdog Timer inner 2 16 2 6 5 Board Control Status Register ss 2 16 27 Special F G NOUS RE N OR EN OR AE Ea 2 18 2 44 ENE AG EE OR N 2 18 2 7 2 Serial EEPROM AAA 2 18 27 3 TICK Timer TEE 2 18 2 7 4 General Purpose Ter 2 18 Ke WER ERR 2 18 2 7 6 Data Retention for RTC and SRA M ees ee ee ee Ge Ge ee ee Ge Ge ee ee Ge ee ee ee 2 19 2 7 7 Front Panel Buttons and LED Porte 2 19 2 8 Serial Communication Potts 2 20 2 8 4 Ethemnet SER4 RE e estesan sesa st ese sosskoson 2 21 2 8 2 SERI SER2 and SER3 Porte 2 22 EE Ge ET 2 23 2 9 ANN ees RA 2 24 2 10 IndustryPack IP Interface des Nos GR GR AG od ee de sa 2 30 2101 Overview EE EE N EE EE Eege 2 30 2102 E 2 30 2 10 3 Optional IP features not supported se ss 2 30 210 4 IP Interface Controller 1 cocsseniseavessepsineowadadesasesassisssolaasssonsttensessensanayess 2 31 21023 IB Reset E 2 31 2 10 6 IP TEE 2 31 2 10 7
34. 9 System 4 1 Software XON XOFF or no Handshake 4 1 1 15 pin Connector 15 pin male 15 pin male 7 GNDO __ 7 GND SIGNAL ground 2 TxD OH Air 3 RD 3 RD 2 TD 4 CTS 4 CTS 5 RTS _ 5 RTS 4 1 2 8 pin RJ45 Connector SMART I O 8 pin RJ45 15 pin male 3 GND 7 GND SIGNAL ground 4 TxD ___ 3 RxD 5 RD 2 TD 2 RTS 5 RTS rors L won 4 1 3 6 pin RJ12 Connector 6 pin RJ12 15 pin male 2 GND e 7 GND SIGNAL ground 3 D 3 RD 4 RD __ 2 TxD 6 RTS 5 RTS 1 CTS A ma 4 CTS Page OS 10 PEP Modular Computers Novemeber 21 1996 4 2 Hardware Handshake 4 2 1 15 pin Connector 15 pin male 15 pin male 7 GND 7 GND SIGNAL ground 2 XD 3 RD 3 RD e 2 TD 4 CIS 10 DTR 10 DIR A CTS 4 2 2 8 pin RJ45 Connector SMART I O 8 pin RJ45 15 pin male 3 GND 7 GND SIGNAL ground 4 TD A 3 Rx 5 RD iii 2MD 7 CTS ii 40 DTR 8 DIR m 4 CTS Appendix OS 9 Cabling e This page has been intentionally left blank Page OS 12 PEP Modular Computers Novemeber 21 1996
35. 996 2 2 Hardware Handshake Select RTS CTS Handshake on the PC Side 2 2 1 15 pin Connector on OS 9 Side 25 pin Connector on PC Side 15 pin male 25 pin female 7 GND 7 GND SIGNAL ground 2 TxD 3 RxD 3 RxD 2 TxD 4 CTS 4 RTS 10 DTR 5 CTS 6 DSR CS 20 DTR 2 2 2 15 pin Connector on OS 9 Side 9 pin Connector on PC Side 15 pin male 9 pin female 7 GND 5 GND SIGNAL ground 2 TxD 2 RxD 3 RxD 3 TxD 4 CTS 7 RTS 10 DTR 8 CTS 6 DSR 1 DCD 4 DTR Appendix OS 9 Cabling e 2 2 3 8 pin RJ45 Connector on OS 9 Side SMART I O 25 pin Connector on PC Side 8 pin RJ45 25 pin female 3 GND 7 GND SIGNAL ground 4 TxD 3 RxD 5 RxD 2 TxD 7 CTS 4 RTS 8 DTR 5 CTS 6 DSR Es 20 DTR 2 2 4 8 pin RJ45 Connector on OS 9 Side SMART I O 9 pin Connector on PC Side 8 pin RJ45 9 pin female 3 GND 5 GND SIGNAL ground 4 TxD 2 RxD 5 RxD 3 TxD 7 CTS 7 RTS 8 DTR 8 CTS 6 DSR a 1 DCD 4 DTR Page OS 8 PEP Modular Computers Novemeber 21 1996 3 OS 9 System lt gt Modem 3 1 15 pin Connector 15 pin male 25 pin male 7 GND 7 GND SIGNAL ground 2 TxD 2 TxD 3 RD 3 RD 4 CTS 5 CTS 5 RTS A RTS 8 DCD 8 DCD 10 DIR 20 DTR 3 2 8 pin RJ45 Connector SMART I O 8 pin RJ45 25 pin male 3 GND 7 GND SIGNAL ground 4 TxD 2 TxD 5 RxD 3 RxD 7 CTS 5 CTS 2 RTS 4 RTS 6 DCD 8 DCD 8 DIR 20 DTR Appendix OS 9 Cabling e 4 OS 9 System lt gt OS
36. A 14 CLK7 BRGO4 TIN4 PA15 CLK8 _TOUT4 L1TCLKB PA7 TXD4 LIRXDA PA6 RXD4 LITXDA PB7 SMRXD1 DONE2 PC9 CD3 LIRSYNCB PB14 RTS3 LIRQB LIST3 PC8 CTS3 LITSYNCB SDACK2 PA12 CLK5 BRGO3 TIN3 PA13 CLK6 _TOUT3 LIRCLKB BRGCLK2 PAS TXD3 LIRXDB PA4 RXD3 LITXDB IRQ 1 IRQ 2 IRQ 3 IRQ 4 user defined user defined user defined user defined user defined SER2_DTR SER3_DTR SER1_DTR SER1_RCLK SER1_TCLK SER1_TXD SER1_RTS SER3_RTS SER3_CD SER1_RXD user defined SER1_CTS SER1_CD SER3_CTS user defined DMA_ACK DMA_REQ user defined SER3_TCLK SER3_RCLK SER3_TXD SER3_RXD user defined SER2_CD SER2_RTS SER2_CTS SER2_TCLK SER2_RCLK SER2_TXD SER2_RXD Juli 23 1997 PEP Modular Computers Page CXC 3 Appendix CXC Controller eXtension Connector 4 Timing A1 A7 AS _LDS _UDS RA W _EDTACK DO D15 _CXC CSx Read Write KEY min max 1 Address valid to AS DS 10ns 2 AS asserted 80ns 3 AS negated to R W invalid 10ns 4 Data in valid to EDTACK Ons 5 _CXC CSx asserted to AS valid 25ns 6 _EDTACK negated to AS negated Ons 90ns 7 Data in hold time Ons 50ns 8 AS negated 5Ons 9 AS R _W asserted to DS asserted 20ns 10 Data out valid to DS asserted 15ns 11 AS DS negated to data out invalid Ons Al A7 address lines _AS address strobe _LDS _UDS lower upper data strobe R W read not write _EDTACK external data transfer acknowledge _CXC CSx _CXC CS0 to CXC
37. Board ID codes Internet Ethernet addresses boot information etc The second half of the EEPROM is available for the user See also the Programming Chapter in this manual For more information on the EEPROM please refer to the XICOR X25C02 data sheet TICK Timer The 68EN360 internal Periodic Interrupt Timer is used by the PEP supported real time operating sy stems as TICK generator For more information please refer to the 68EN360 User s Manual General Purpose Timer There are four 16 bit general purpose timers available which are provided by the 68EN360 Two pair of timers can cascaded internally or externally to form two 32 bit timers Maximum period is 8 1s at 33MHz with a resolution of 30ns For more information please refer to the 68EN360 User s Manual DMA Transfers There are two independant fully programmable DMA channels available which are provided by the 68EN360 These IDMAs provide 32 bit address and 32 bit data capabiltity together with 32 bit byte transfer counters Fixed and rotating priority as well as single buffer auto buffer or buffer chaining is supported by the DMAs With the IDMAs memory to memory transfers are possible with any combi nation of onboard and A23 D16 VME addresses For more information please refer to the 68EN360 User s Manual PEP Modular Computers Juli 23 1997 Chapter 2 Functional Description VM162 VM172 2 7 6 Data Retention for RTC and SRAM Short term data retention for RTC
38. CS7 Recommended Assert EDTACK with CSx and UDS _LDS and data valid during read cycles Latch data with CSx and UDS LDS during write cycles Negate EDTACK with _UDS _LDS invalid Page CXC 4 PEP Modular Computers Juli 23 1997 Appendix CXC Controller eXtension Connector 5 Controller Extension Connectors CXC2 CXCS e e e e e e D D see ee ee eee ee ee eee ee ee e DOU seo ee D e seo seo ee D eee eee ee D see ee ee D D ese ee e D ee ee D e DOU ee D ee seo ee e ee eee ee ee see ee ee ee see eee ee ee seo eee ee ee seo D see ee ee see see ee e ese eee ee D see see e ee e ese eee ee D ee eee ee D ee eee D e e soe see H H D seo seo ee D e seo eee ee D seo eee ee e ee ese ee e e eee seo ee H D seo seo ee D see seo e o ee eee e eee D e e e e e e 8 000000000000 000000000000 ee 0 000000000000 00000000000e cn O eeeeeeeeeeeeeseeeseeseeeeeeeseee O Geeeeeeeeeeeeeeeeeeeeeeeeeeeeeee CS2 CS3 CS4 CS5 CS6 When using an 8TE board on the CXC5 and CXC8 note that a slot will be lost between each board Juli 23 1997 PEP Modular Computers Page CXC 5 Appendix CXC Controller eXtension Connector e This page has been intentionally left blank Page CXC 6 PEP Modular Computers Juli 23 1997 Appendix OS 9 Cabling APPENDIX OS 9 CABLING This Appendix outlines the connection definitions of S 9 systems to various outside media 1 OS 9 S
39. FAIL level 5 autovector Mailbox IRQ level 3 autovector CXC vector prog Single level BR3 FAIR RWD Release When Done Automatic First Slot Detection A32 Access Code A24 Access Code A16 Access Code User Defined HEX 09 0A 0D 0E HEX 39 3A 3D 3E HEX 29 2D HEX 10 17 18 1F Dual ported SRAM 16 software selectable base addresses Two card holders with I O ported to 50 pin flat band cable or D Sub connector on front panel DIN 41612 C 96 pin 3 NMSI ports DMA PEP Modular Computers Juli 23 1997 Chapter 1 Introduction VMEbus Interface Networking SC Interface Power Consumption Temperature VM162 VM172 DIN 41612 C 96 pin P1 P2 connector A32 A24 A16 D32 D16 D8 master A24 D16 slave All Ethernet interfaces conform to IEEE 802 3 and are available on SI6 xx piggybacks Serial Interface from MC68EN360 ports SCC2 SCC3 and SCC4 with standard RS232 configuration VM162 w MC68060 6 5W 50 MHz VM172 w MC68040 8 5W 33 MHz 0 C to 70 C standard 40 C to 85 C extended storage Humidity 0 to 95 non condensing Weight Dimensions Front Panel Functions 440 g with 10BaseT and memory piggybacks 233mm x 160mm 6U format 3 LEDs red Halt yellow Watchdog enabled green General purpose user a With 4 Mbyte DRAM 256 kByte SRAM and I MByte FLASH memory Juli 23 1997 PEP Modular Computers Page 1 9 VM162 VM172 Chapter 1 Introduction 1 7 Ordering
40. I Ethernet interface to the 68EN360 Controller chip 2 1 Specifications On board termination None Cheapernet cable is terminated at both ends Max Baud Rate 10 Mbit s as specified by Ethernet 2 2 Connector Pin 1 Pin 2 Signal Control In circuit Shield Control In circuit A Data out circuit A Control In circuit Shield Data in circuit A Voltage Common Not connected Not connected ETHERNET 10Base5 Pin 9 15 pin D Sub Connector Pin 15 Signal Control In circuit Shield Data out circuit B Data out circuit Shield Data in circuit B 12 Volts GND Not connected Note SI6 10B5 required an external 12V from the base board For more detail please refer to the relevant base board manual Juli 23 1997 PEP Modular Computers Page SI6 3 Appendix SI6 Piggybacks 3 SI6 10BT The SI6 10BT is a physical twisted pair 10BaseT interface to the 68EN360 Controller chip It connects one of the range of PEP CPU boards to an unshielded 10002 twisted pair cable via an RJ45 telephone jack The SI6 10BT has two LEDs fitted a red LED indicates collision detection and a yellow LED for data 3 1 Specifications On board termination 1009 Max Baud Rate 10 Mbit s as specified by Ethernet 3 2 Connector o DE te Collision 00 Data 10BaseT Pin 8 RJ45 Connector Pin 1 ETHERNET Signal TD TD RD Not connected Not connected ei Not c
41. IP slot control register Depending on the memory size bit the memory page bits are relevant or not Default is 8 MByte not paged Page 2 32 PEP Modular Computers Juli 23 1997 Chapter 2 Functional Description VM162 VM172 2 10 10 IP Interrupt Control Register Address IPa NEX CE 00 09 01 IPa NEX CE 00 OB 01 Format byte Access read and write Value after Reset HEX 00 IP Interrupt Control Register Bit map eee ene eee ee ee ee INT1 EN INT1 IL2 INTI IL1 INT1 ILO INTO EN INTO IL2 INTO IL1 INTO ILO INT1_EN 0 gt IP interrupt request on INT1 line disabled 1 gt IP interrupt request on INT1 line enabled INT 1_IL2 0 IP IRQ level for INT1 line 1 or 3 or 5 or 7 INTO_EN 0 gt IP interrupt request on INTO line disabled 1 gt IP interrupt request on INTO line enabled INTO_IL2 0 IP IRQ level for INTO line 2 or 4 or 6 Juli 23 1997 PEP Modular Computers Page 2 33 VM162 VM172 Chapter 2 Functional Description 2 10 11 IP Slot Control Register Address IPa NEX CE 00 09 81 IPa NEX CE 00 OB 81 Format byte Access read and write Value after Reset HEX 00 IP Interrupt Control Register Bit map q pa IP CLK IP RESET M SIZE M PAG2 M_PAG1 M_PAGO IP_CLK 0 gt IP CLOCK 8 MHZ 1 gt IP CLOCK 32 MHZ IP_RESET 0 0 gt IP RESET line active 1 gt IP RESET line not active IP enabled M_SIZE 0 gt IP linear addressable mem space 8 MB 1 gt IP linear addressable mem spac
42. In some ap plications it may be useful to boot either from the VMEbus or the optionally assembled EPROM e es eem Boot from VMEbus enabled se Boot from VMEbus disabled Default 3 2 2 ROM Boot CC Lou E Open Boot from boot ROM disabled Default 3 2 3 Protective Ground Signal Ground EC em Protective ground connected to signal ground P Open Protective ground disconnected from signal ground Default 3 2 4 VME SYSRES As long as the 5V supply is not within the VMEbus specification the VM162 VM172 uses the VMEbus RESET line This behaviour may not be wanted in multi master configurations and can be disconnected ze ie eem On board RESET generator to VME Default P Open On board RESET generator disconnected from VME Juli 23 1997 PEP Modular Computers Page 3 5 VM162 VM172 Chapter 3 Configuration 3 2 5 CXC Mode The enhanced CXC describes the multiplexing of the CXC address lines in order to enhance the address range to 16MByte This is used today in conjunction with the CXM PFB 12 PROFIBUS board Please consult the relevant CXM User s Manual to set the CXC mode COM es eme Enhanced CXC mode enabled loss Enhanced CXC mode disabled Default Page 3 6 PEP Modular Computers Juli 23 1997 VM162 VM172 Chapter 3 Configuration 3 3 Jumper Description Solder Side Figure 3 2 VM162 VM172 Jumper Layout Solder Side Zd J0 99UU0D JWA Ld Jo DaUUOD JWA
43. Information CE CCE VMEbus single board computer comprising MC68060 O 50MHz MC68EN360 25 MHz 256 kByte dual ported SRAM with Goldcap for back up five serial interfaces four available on the front panel as RS232 RJ45 and one available from the choice of SI6 networking piggybacks CXC interface two IP interfaces and PEPbug VMI72 BASE Same as order no 16134 but with 1 MByte dual ported SRAM 16194 VMEbus single board computer comprising MC68040 G 33MHz MC68EN360 G 33 MHz 256 kByte dual ported SRAM with Goldcap for back up five serial interfaces four available on the VIG BASE front panel as RS232 RJ45 and one available from the choice of 16926 SI6 networking piggybacks CXC interface two IP interfaces and PEPbug VM162 BASE Same as order no 16026 but with 1 MByte dual ported SRAM 16193 Memory Piggyback with 4 MByte DRAM and 1 MByte FLASH E memory for VM162 172 oe Memory Piggyback with 4 MByte DRAM and 4 MByte FLASH E memory for VM162 172 ees Memory Piggyback with 16 MByte DRAM and 1 MByte FLASH pie memory for VM162 172 a Memory Piggyback with 16 MByte DRAM and 4 MByte FLASH PETER memory for VM162 172 HE Memory Piggyback with 1 MByte DRAM and 1 MByte FLASH Die memory for the VM162 172 SE Memory Piggyback with 32 MByte DRAM and 512 kByte FLASH Pon memory for the VM162 172 SE Memory Piggyback with 32 MByte DRAM and 2 MByte FLASH DIEGO memory for the VM162 172 Dou Memory Piggyback with 8 MByte DRAM and 1 MByte FLASH
44. M SIO3 Ethernet Interface Three different SI6 piggybacks complete with all the associated control logic are available providing 10Base2 10Base5 or 10BaseT interfaces RS485 Interfaces This is a fully optoisolated RS485 SI6 interfacepiggyback with a 9 pin D Sub connector PEP Modular Computers Juli 23 1997 Chapter 1 Introduction VM162 VM172 IndustryPack Any two IndustryPacks from a wide range may be fitted to cater for the needs of digital analog com munication or counter functions PEP also offers customers a non gratis service that integrates the cho sen IP module and RT OS with the VM162 172 carrier board SC Interface Three RS232 SC Piggybacks are fitted as standard for serial communication These can be replaced by optoisolated RS232 or RS485 piggybacks as required DMA Channels 2 independent channels are provided by the QUICC chip for use by applications requiring DMA trans fer between VMEbus CXC modules DRAM FLASH memory and dual ported SRAM DRAM FLASH This memory complete with a 32 bit wide access bus is placed on a piggyback with addressing capabi lity for up to two memory banks of 64 MByte each The on board programmable FLASH memory al lows the user to produce low cost upgrades by over writing existing stored data and may also be configured as a boot device SRAM This is a dual ported battery backed Goldcap memory area with a 16 bit wide access bus Users of the VMEbus and CPU both ha
45. MByte DM602 1 MByte O or 0 5 or 2 MByte DM603 32 MByte 1 or 4 MByte DM604 8 MBytes 1 or 4 MBytes Note DRAM is accessed with a 5 2 2 2 burst cycle at 25 MHz bus clock 68060 50MHz and with a 6 2 2 2 burst cycle at 33 MHz bus clock 68040 V 33MHz SRAM The SRAM on the VM162 VM172 is organized in one bank with 16 bit wide data access bus It is bak ked by two onboard service free GoldCaps and optionally via VME StandBy Additionally this me mory is dual ported Users of the VMEbus and the onboard CPU both have access to this memory The dual ported SRAM is soldered directly on the base board available with size of 256 kB or 1 MB Boot ROM optional The VM162 VM172 Boot ROM is an optional socket device The sockets support devices up to 512 kB size with a 16 bit wide data access for PLCC EPROMs By default the board s firmware is stored directly in the FLASH on memory piggyback Thus the Boot ROM is not mandatory In case of using a Memory PB without FLASH or if an application requires the board s firmware to be separated from FLASH then the Boot ROM socket can be used Whether starting from FLASH or from Boot ROM is selected by jumper Supported chips for the Boot ROM 128Kx8 256Kx8 512Kx8 PROM or EPROM Standard JEDEC Pinning Juli 23 1997 PEP Modular Computers Page 2 5 VM162 VM172 Chapter 2 Functional Description 2 3 4 EEPROM The EEPROM is a non volatile serial memory device It provides 2 kbit size
46. Time 2 SCC2 SCC3 SCC E Clock SC Piggyback Interfaces 3x Serial Interfaces for SC Piggyback And CXC w a w a a w a a A U EN A UN A W A AM KEU KEU KE 0 20d le ee wo two UN OU UN HO A TEEN Bon n a w e w n e n W e e We n n an n an nn n nn e Une ey CXC Interface This translation between the raw 68EN360 signals and ready configured port on the front panel is very flexible on the VM162 VM172 by using SI and SC piggybacks or even CXMs 5 configured serial ports are available on the front panel connectors The Table on the following page shows the availability of the various logical serial ports on the internal interfaces for physical configuration Page 2 20 PEP Modular Computers Juli 23 1997 Chapter 2 Functional Description VM162 VM172 Table 2 9 Serial Communication Port Configuration Port Name Physical Standards on Front Panel 68EN360 Dedicated Configured Resource Function via SCCI Ethernet Fieldbus 10Base2 10Base5 10BaseT Isol RS485 SCC2 SC PBI or RS232 optoisolated CXM RS485 optoisolated SCC3 SC PB2 or RS232 optoisolated CXM RS485 optoisolated SCC4 SC PB3 or RS232 optoisolated CXM RS485 optoisolated SMCI Terminal Port Default RS232 Note For applications where D Sub connectors are preferred rather than the default RJ45 connector a front panel is available whereby all serial ports can be connected via mini D Sub connectors
47. a aa nda 4 3 4 2 EEN E 4 4 4 3 Initializing the Cache Appendices Memory Piggybacks SI6 Piggybacks Bootstrap Loader Controller eXtension Connector OS 9 Cabling Board Layout Juli 23 1997 VMI62 VMI72 PEP Modular Computers Page TOC 3 VM162 VM172 Table of Contents Page TOC 4 PEP Modular Computers Juli 23 1997 VM162 VM172 Preface Juli 23 1997 PEP Modular Computers Page 0 1 VM162 VM172 Preface Unpacking and Special Handling Instructions This PEP product is carefully designed for a long and fault free life nonetheless its life expectancy can be drastically reduced by improper treatment during unpacking and installation Observe standard anti static precautions when changing piggybacks ROM devices jumper settings etc If the product contains batteries for RTC or memory back up ensure that the board is not placed on conductive surfaces including anti static plastics or sponges These can cause shorts and damage to the batteries or tracks on the board When installing piggybacks switch off the power mains Furthermore do not exceed the specified operational temperature ranges of the board version ordered If batteries are present their temperature restrictions must be taken into account Keep all the original packaging material for future storage or warranty shipments If it is necessary to store or ship the board re pack it as it was originally packe
48. a memory piggyback fitted with 32MByte DRAM and either 0 5MByte or 2MByte Flash EPROM 4 DM603 4 1 Jumper Location Ji e DRAM FLASH Jumper J1 Flash Write Protection ea Ion All Flash EPROM write protected No Protection Default July 19 1997 O PEP Modular Computers Page MEM 5 Appendix Memory Piggybacks 5 DM604 The DM604 is a memory piggyback fitted with 8MByte DRAM and either 1 or 4MByte Flash EPROM 5 1 Jumper Location J2 J1 FLASH ee ee Bank 0 i E li Jumper J1 J2 Flash Write Protection SEN 1 MB FLASH 4 MB FLASH Setting Descirption 8 x 29F010 8 x 29F040 J1 J2 open All Flash EPROM write protected ENE MEEN Flash bank 1 write protected upper 512 kB upper 2 MB Default address range 4008000 4020000 40100000 40400000 Flash bank 0 write protected lower 512 kB lower 2 MB Default address range 4000000 4000000 40080000 40200000 AN July 19 1997 PEP Modular Computers Page MEM 6 Appendix SI6 Piggybacks APPENDIX SI6 PIGGYBACKS A number of piggybacks have been developed for PEP s range of 6U CPU boards to adapt the multi protocol serial channels of the 68EN360 controller chip to one of the following physical interfaces Ethernet 10Base2 Thin with SI6 10B2 piggyback e Ethernet 10Base5 AUI with SI6 10B5 piggyback e Ethernet 10BaseT Twisted Pair with SI6 10BT piggyback e RS485 optoisolated PROFIBUS
49. ameters stored in the serial EEPROM Juli 23 1997 PEP Modular Computers Page 2 13 VM162 VM172 Chapter 2 Functional Description 2 6 Board Control Logic 2 6 1 Boot Decoder Logic The VM162 VM172 gives the user the choice to execute startup procedures from three different me mory areas These are FLASH default on the memory Piggyback or the optional Boot ROM or me mory on the VMEbus The boot device memory is selected by jumpers The boot decoder logic redirects the initial CPU access which is always starting at address 0 HEX to the boot device according the boot jumper setting The boot device is swiched automatically to its de fault address area after the first access on it with its default address For more details please refer to the Programming Chapter in this manual Notes If VMEbus memory is selected to be the default boot device it must be located at VME base address 0 HEX in A24 D16 address space for supervisory program data access AM codes 3E 3D If FLASH or VMEbus memory is selected to be the boot device the optional Boot ROM can be used as a standard ROM for storing program data or application specific parameters 2 6 2 Interrupt Control The interrupt control logic processes internal interrupt requests 68EN360 together with external re quests VME and external autovectored interrupt requests The interrupt control logic is built up using the 68EN360 internal interrupt controller for QUICC
50. ap Loader 4 3 Memory Display Syntax md lt adr gt Description Without parameters specified the FLASH contents starting at 0x4000000 are displayed This function is not limited to FLASH and other address ranges can be specified Note The ResetPC in FLASH is not identical to the ResetPC from the programming source S records memory block 4 4 Port Format Syntax pf lt port gt baud bitschar J parity stops Description Without parameters specified the current serial port settings are displayed port specifies the serial port Valid values are term or serO lt baud gt specifies the baud rate The values 50 75 110 134 5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 and 38400 Baud can be specified lt bitschar gt specifies the bits character Valid values are 7 or 8 lt parity gt specifies if parity should be checked generated The value n specifies none o for odd and e for even parity lt Stops gt specifies the stopbits which will be generated Valid values are 1 or 2 Note No spaces are allowed between the options Options must be separated with the 7 Not all options must be specified but the characters must be present to distinguish the different options from each other The sequence can be aborted after every option Examples Setting term to 300 Baud 7 Bits char odd parity and 2 stopbits pf term 300 7 o n Set the bits character field to 7
51. ctor on PC Side 15 pin male 25 pin female TGND ooo oo 7 GND SIGNAL ground 2 TxD 3 RD 3 RD Ar 2 TXD 4 CTS 5 CTS 5 RTS 6 DSR 8 DCD 20 DTR 2 1 2 15 pin Connector on OS 9 Side 9 pin Connector on PC Side 15 pin male 9 pin female 7 GND e 7 GND SIGNAL ground 2 TxD 2 RxD 3 RD 3 4 CTS 8 CTS 5 RTS 6 DSR 1 DCD 4 DTR Page OS 4 PEP Modular Computers Novemeber 21 1996 Appendix OS 9 Cabling 2 1 3 8 pin RJ45 Connector on OS 9 Side SMART I O 25 pin Connector on PC Side 8 pin RJ45 25 pin female 3 GND 7 GND SIGNAL ground 4 TxD A Bai 5 RD 2 Tx 7 CTS 5 CTS 2 RTS 6 DSR 8 DCD 20 DTR 2 1 4 6 pin RJ12 Connector on OS 9 Side 25 pin Connector on PC Side 6 pin RJ12 25 pin female 2 GND 7 GND SIGNAL ground 3 TxD ii 3 RXD ARD SO TD 6 CTS E 5 CTS 1 RTS 6 DSR 8 DCD 20 DTR November 21 1996 PEP Modular Computers Page OS 5 Appendix OS 9 Cabling e 2 1 5 8 pin RJ45 Connector on OS 9 Side SMART I O 9 pin Connector on PC Side 8 pin RJ45 9 pin female 3 GND _ 5 GND SIGNAL ground ADD ii AARD 5 RD ii 3 TXD 7 CTS 8 CTS 2 RTS 6 DSR 1 DCD 4 DTR 2 1 6 6 pin RJ12 Connector on OS 9 Side 9 pin Connector on PC Side 6 pin RJ12 9 pin female 2 GND 5 GND SIGNAL ground 3 TxD 2 RxD 4 RxD 3 TxD 6 CTS E 8 CTS 1 RTS 6 DSR 1 DCD 4 DTR Page OS 6 PEP Modular Computers Novemeber 21 1
52. ctors for emerging IP signals offer improved EMI protection compared with the on board flat cable connector Each IP module has its own shielded con nector for state of the art industrial cabling All front panels feature a user watch dog and halt status LED reset and abort button switches and where possible the status of the Ethernet communication Page 1 4 PEP Modular Computers Juli 23 1997 Chapter 1 Introduction VM162 VM172 SC and SI6 piggybacks adapt the multi protocol serial channels of the QUICC to the physical inter faces provided on the VM162 172 s front panel and CXC SCC1 channel supports SI6 10B5 Ethernet 10base5 AUD SI6 10B2 Ethernet 10base2 Thin SI6 10BT Ethernet 10baseT Twisted Pair SI6 PB485 ISO Optoisolated RS485 SCC2 to SCC4 channels support SC 2321 Optoisolated RS232 Modem module SC 4851 Optoisolated RS485 piggyback Figure 1 1 Front Panel Options o E o IO O D D gt ees ER 1 So sa 2 OO 8 a o a Col Tx 8 Col Tx os Bo a a Ge ME 10Base2 10BaseT ESE z fe Se ltr s lt 5 ki 15090 TA Zz Fd OS ore ai ee ene O eats E ui ieee Hs cd i E Fa ie ec 1 ESE D D E Ee mo imo De Sem 1 LI D SER2 SER3 SER1 e ad IE z Juli 23 1997 PEP Modular Computers Page 1
53. d Page 0 2 PEP Modular Computers Juli 23 1997 Preface Revision History VM162 VM172 Issue Brief Description of Changes Index Date of Issue 1 First Issue 0 July 1997 This document contains proprietary information of PEP Modular Computers It may not be copied or transmitted by any means passed to others or stored in any retrieval system or media without the prior consent of PEP Modular Computers or its authorized agents The information in this document is to the best of our knowledge entirely correct However PEP Modular Computers cannot accept liability for any inaccuracies or the consequences thereof nor for any liability arising from the use or application of any circuit product or example shown in this document PEP Modular Computers reserve the right to change modify or improve this document or the product described her ein as seen fit by PEP Modular Computers without further notice Juli 23 1997 PEP Modular Computers Page 0 3 VM162 VM172 Preface PEP Modular Computers Two Year Limited Warranty We grant the original purchaser of PEP products the following hardware warranty No other warranties that may be granted or implied by anyone on behalf of PEP are valid unless the consumer has the expressed written consent of PEP Modular Computers PEP Modular Computers warrants their own products excluding software to be free from defects in workmanship and materia
54. dance with the IP specification PEP has implemented an 8 16 bit data width interface operating at 8 or 32MHz that supports interrupts and communicates with the host carrier via a 50 pin connector with embedded address data control and power lines This caters for more than 90 of the available IP modules which do not have DMA support e Up to 2 standard or 1 2x sized IP e Supports I O ID memory amp IRQ e Supports 8 16 bit IP cycles e Prog IP bus speed 8 32 MHz IP e 2 interrupts per IP e 2 8 MB linear memory space IP e Overload protection fuses IP Juli 23 1997 PEP Modular Computers Page 1 3 VM162 VM172 Chapter 1 Introduction 1 3 Controller eXtension Connector Although the VM 162 172 adds a new dimension to computer architecture with its direct Industry Pack interface it is also a continuation of the successful range of PEP s CPU boards with communication pro cessors and CXC capability The CXC extends the already abundant industrial I O capability of the CPU and also allows custom design according to the guidelines laid down in the CXC specification Introduced in 1990 PEP s Controller eXtension Connector CXC concept enables a mezzanine Input Output extension on the VME or on distributed Input Output systems based on CXC as a backplane bus The CXC is based on an open specification allowing unprecedented flexibility in meeting customer re quirements PEP has named these mezzanine plug in modules Controller
55. der s command mode is entered automatically If the user wants to enter the Bootstrap Loader manually e g for re programming the FLASH contents he must use the ABORT button on the front panel Note The ABORT button must not be pushed until the green LED appears because this button generates an NMI and the exception vector tables must be initialized correctly to serve this NMI Pressing the ABORT prior to the green LED leads to HALT in most cases In this case press the RESET button and try again The ABORT button must however be pushed before the green LED stops flashing BootWaitTime because system control is passed to the downloaded binary image afterwards The LED is cycled every 0 25 sec so if 1 second is specified as Boot WaitTime the LED will only flash 2 times CTRL x deletes the complete input line while CTRL a restores the last input line D The start key is a special combination of data appended at the end of the load program Page BOOT 2 PEP Modular Computers Juli 23 1997 Appendix Bootstrap Loader 3 Programming FLASH Memory 3 1 Preparing the Image The image must be compiled linked to run from the FLASH base address 0x4000000 The image must start with the Re setSP ResetPC vectors as usual for ROM FLASH images on 68000 processor boards A binary image must be converted to Motorola S records or loaded to a VME memory board with battery backup FLASH or EPROM population 3 2 Programming with Mot
56. dular Computers July 19 1997 Appendix Memory Piggybacks 2 DM601 The DM601 is a memory piggyback fitted with 16MByte DRAM and either 1 or 4MByte Flash EPROM 2 1 Jumper Location 1 000 432 Bank 0 E E E x Jumper J1 Flash Write Protection W i 1 MB FLASH 4 MB FLASH Setting Descirption 8 x 29F010 8 x 29F040 Open All Flash EPROM write protected ENE MEEN Flash bank 1 write protected upper 512 kB upper 2 MB Default address range 4008000 4020000 40100000 40400000 Flash bank 0 write protected lower 512 kB lower 2 MB Default address range 4000000 4000000 40080000 40200000 AN July 19 1997 PEP Modular Computers Page MEM 3 Appendix Memory Piggybacks 3 DM602 The DM602 is a memory piggyback fitted with IMByte DRAM and either O or IMByte Flash EPROM 3 1 Jumper Location 00 2 00 Ji FLASH Bank 0 Bank 1 Jumper J1 Flash Bank 1 Write Protection Setting Set Descirption No Protection Flash bank 1 write protected Default address range Jumper J2 Flash Bank O Write Protection Setting Set Page MEM 4 Descirption No Protection Flash bank 0 write protected Default address range 1 MB FLASH 8 x 29F010 upper 512 kB 4008000 40100000 1 MB FLASH 29F010 lower 512 kB 4000000 40080000 PEP Modular Computers Appendix Memory Piggybacks The DM603 is
57. dustryPack slot b I O area amp control Enhanced CXC 68360 CS5 IndustryPack slot a memory area IndustryPack slot b memory area Note CXC and ECXC address areas are exclusive to each other July 19 1997 PEP Modular Computers Page 4 3 VM162 VM172 4 2 Initializing the 68EN360 Page 4 4 Chapter 4 Programming Many components of the VM62 A VM42 A are controlled by the MC68EN360 Due to this fact this chip requires a special initialization sequence before any other software can be started The following list describes how the initialization must be performed on the VM62 A VM42 A Note The order of the initialization listed below must not be changed otherwise erratic behaviour of the board may result 1 Set DPRBASE to 0x000000 0x7000001 L gt MBAR in CPU space Example move l 7 di select CPU space move l 7000001 d0 value to write to MBAR movec di dfc select CPU space moves l dO MBAR set MBAR 2 Clear reset status register 3 wm Set system protection register e bus monitor enabled 128 system clocks timeout 4 Set module configuration register bus request MC68040 arbitration ID 3 arbitration synchronous timing mode bus clear out arbitration ID 3 SIM60 registers are Supervisor Data BusClear in arbitration ID 3 interrupt arbitration 3 5 Set PLL enabled and lock access 6 wm Lock access to clock divider control register
58. e 1 MB M_PAG active memory page 1 of 8 1 MB mem pages Page 2 34 PEP Modular Computers Juli 23 1997 Chapter 2 Functional Description VM162 VM172 2 10 12 IP Connectors 7 IPb VO DSUB IPa VO DSUB V The figure above shows the position of IPa and IPb on the VM162 177 Each IP is plugged into the board via a pair of 50 pin IP connectors The rear one near to the VMEbus connector connects the IP bus and control signals whereas the other one near to the frontpanel carries the IP I O signals The IP I O signals are routed from the 50 pin IP I O connector to a 50 pin flatcable connector and also to the 50 pin frontpanel DSUB connector There is a one to one correspondance between the pin si gnal numbers between the IP I O connector flatcable connector and DSUB connector Juli 23 1997 PEP Modular Computers Page 2 35 VM162 VM172 Chapter 2 Functional Description 2 10 12 1 IP VO Connector Pinout Pini Pin25 EE EE pese VO VO 2 10 12 2 IP VO Flat Cable Connector Pinout Pin2 Pin50 EIE EF ee er VO VO Page 2 36 PEP Modular Computers Juli 23 1997 Chapter 2 Functional Description VM162 VM172 2 10 12 3 IP I O DSUB Frontpanel Connector Pinout Pin50 Pin25 Pin26 Pini FE EEE SS ESET IP VO EI IP VO Juli 23 1997 PEP Modular Computers Page 2 37 VM162 VM172 Chapter 2 Func
59. eXtension Modules CXM These 96 pin CXMs are designed to operate with CXC based host modules which includes the VM162 172 Designed primarily to operate in harsh industrial environments this versatile modularity provides not only a cost effective engineering solution but also allows customers a near exhaustive selection of sy stem configurations through a selection of over 30 base CXMs providing analog digital and other I O extensions such as SCSI and fieldbus connection PROFIBUS CAN LON and Bitbus Hence a fea ture of the VM162 172 is that the raw serial signals from the QUICC SCC2 SCC3 and SCC4 chan nels being internally wired to the front panel as well as to the CXC interface Network interfacing is provided if required by ordering the relevant front panel which comes complete with the appropriate SI6 piggyback serial port connectors and 50 pin D Sub IndustryPack connector Naturally to cater for those customers who merely wish to take advantage of the computing power and CXC capablility that the VM162 offers blank front panels without the networking options have been devised 1 4 Front Panel and I O Configuration The illustrated front panels show the possible connections of the SCC1 communications channel for Ethernet RS485 or blank In addition the front panels are available with mini D Sub connectors instead of RJ45 connectors for the 4 standard serial channels The 50 pin subminiature SCSI 2 style D Sub conne
60. en abled for supervisor user data access in accordance to AM codes 3D and 39 Mailbox Interrupt Reg Dual ported SRAM Address Range Address Range HEX HEX Page 2 12 PEP Modular Computers Juli 23 1997 Chapter 2 Functional Description VM162 VM172 2 5 5 VME Control Status Register The VME Control Status Register is a one byte wide register with read write access at default address CD 00 00 05 HEX 7 6 5 4 3 2 1 0 Cer Note All bits except bit 4 First Slot Detection are cleared after reset The firmware of the board initia lizes some of them at startup according to the default parameters stored in the EEPROM Register Description Reset HW Reset PEP SW Slot 1 Other Slot 1 Other Description Pending mailbox IRQ Value stored in Dual port RAM inc mailbox IRQ for EEPROM VME requester enabled Base address fixed using BADRx bits EN_BERR2 Enable bus monitor timer all VME bit 5 cycles timeout after 128us FSD VMEbus First Slot Detection flag bit 4 system controller BADRS Value stored in VME address location of dual ported BADRO EEPROM RAM Equivalent to VME address lines bits 3 0 A23 A20 programmable from 0 F in 1 MByte windows enabled with EN DPR Note All bits are cleared during a reset FSD is set dependent on the slot position of the board in the system The board s firmware initializes EN DIR EN BERR2 and BADR 3 0 during startup follo wing default par
61. ernal tcyc SRAM to 0xA000000 0x4000011 L gt BRO 0x3F000000 L gt ORO 0xC000001 L gt ORI 0x21 L gt BRI 0x1F000006 L gt OR2 0x87000001 L gt BR2 0x1F000006 L gt OR3 0x9000001 L gt BR3 0x1F000006 L gt OR4 0xA000001 L gt BR4 July 19 1997 PEP Modular Computers Page 4 5 VM162 VM172 Chapter 4 Programming e CSS size to 8 kByte port size external tcyc 1 Ox1FFFE006 L gt ORS e CS5 CXC to 0xBF70000 0xBF70001 L BR5 e CS6 size to 2 kByte port size external tcyc 1 Ox1FFFF806 L gt OR6 e CS6 RTC to 0xC000000 0xC000001 L gt BR6 0x1 F000006 L gt OR7 0xD000001 L gt BR7 e CS7 size to 16 MByte port size external tcyc 1 e CS7 on board control to 0xD000000 Note CS1 and CS4 It is important that the values of these Select Lines are changed later after RAM search to the actual configuration of the on board memory For example e A board with 16 MByte DRAM gt ORI OxF000001 L e A board with 256 kByte SRAM OR4 OxFFCOOOO6 L 12 The system software normally determines the real sizes of the DRAM and SRAM installed and re programs the CS lines accordingly The simplest way to achieve this is to write a pattern to the first location and then search for that pattern at meaningful distances e g 256kB 512 kB 1 MB 2 MB 4 MB 8 MB 16 MB If the pattern is found at such an address the original pattern must be altered and then checked to see if the mirro
62. idated with a CRC code to avoid the setting of random parameters If the CRC of the Boot section is not valid the BootWaitTime can be changed but this change has no effect because the bw command does not validate an invalid CRC to avoid undesired side effects In this case the default of 5 seconds is always used To validate an invalid CRC the appropriate utility from an operating system must be used e g ee config from OS 9 Page BOOT 6 PEP Modular Computers Juli 23 1997 Appendix Bootstrap Loader 4 Command Reference 4 1 Boot Wait Syntax bw lt time gt Description Without parameters bw displays the current setting For lt time gt 1 2 5 10 20 and 50 may be specified as time in seconds Other values are not supported 4 2 Load Flash Syntax If ol lt offset gt u q c m lt adr gt I lt len Description Without parameters the FLASH is loaded using S records over the term port lt offset gt is a signed 32 bit offset which is added to every record and can be used to move the S records to the FLASH po sition Note This ontion must be used if 51 or S2 records are used u must be used to download over ser0 q suppress all messages except error messages c clears all untouched sectors and leaves no old code fragments For a Load Flash from an absolute address the m I options must be used Juli 23 1997 PEP Modular Computers Page BOOT 7 Appendix Bootstr
63. imer see also VMEbus Control Status Register Set by on board bus error timer when timeout has been reached Used to identify BERR caused by this timer Enable the watchdog timer It can only be set once and remains enabled until the next reset Triggers the watchdog timer Watchdog timeout 512ms Enables the on board bus error timer It also monitors all on board I O cycles including the time from the VMEbus request to the VMEbus grant Timeout 8us VME ACFAIL signal latched when active in order to distinguish between a level 7 NMI from an ABORT or ACFAIL Enables the green general purpose front panel LED Juli 23 1997 PEP Modular Computers Page 2 17 VM162 VM172 Chapter 2 Functional Description 2 7 Special Functions 2 7 1 2 7 2 2 7 3 2 7 4 2 7 5 Page 2 18 Real Time Clock The RTC V3021 3 wire serial interface is a 1 bit device which is accessible over the CS6 of the 68EN360 Its timekeeping features include e seconds minutes hours day of month month year week day and week number in BCD format e leap year and week number correction e standby supply smaller than 1A For more details please refer to the Programming Chapter in this manual and the V3021 data sheet Serial EEPROM The serial EEPROM is a 1 bit device which is accessible over the SPI Interface 3 wire Interchip of the 68EN360 The first half of the EEPROM 1 kbit is reserved for factory data including
64. ined user defined Vcc user defined SERI RCLK SERI TCLK GND SERI TXD SERI RTS GND SER3 RTS SERI RXD user defined DMA ACK DMA REQ user defined SER3 TCLK SER3 RCLK Vcc user defined 5 1 _CS CXC GND SER2_TCLK 20 Vcc CXC CLK _CS2 28 DI D6 D11 Page CXC 2 PEP Modular Computers Juli 23 1997 3 Appendix CXC Controller eXtension Connector CPU Pinout Cross Reference The table below shows a cross reference of the special CXC released by the 68302 and the 68EN360 Table 3 0 1 Comparsion of 68302 68 EN 360 Function En 68302 Pin 68 EN 360 Pin CXC Function PB11 PB10 PB9 PB8 PB7 WDOG PB6 TOUT2 PB5 TIN2 PB4 TOUTI PB3 TINI PB2 IACKI PB1 IACK6 PBO IACK7 RCLKI TCLKI TXDI RTS1 RTS3 CD3 RXDI BRGI CTSI CDI CTS3 DONE DACK DREO BRG3 TCLK3 RCLK3 TXD3 RXD3 BRG2 CD2 RTS2 CTS2 TCLK2 RCLK2 TXD2 RXD2 PCO RTSI LISTI PCI RTS2 LIST2 PC2 RTS3 LIRQB LIST3 PC3 RTS4 LIRQA LIST4 PBO SPISEL RRJCTI PBI SPICLK RSTRT2 PB2 SPIMOSI SPITXD RRJCT2 PB3 SPIMISO SPIRXD BRGO4 PB8 SMSYN1 DREQ2 PB16 BRGO3 STRBO PB9 _SMSYN2 _DACK2 PB17 _RSTRT1 STRBI PA8 CLK1 BRGO1 L1RCLKA TIN1 PA10 CLK3 BRGO2 LITCLKA TIN2 PA3 TXD2 PB13 _RTS2 L1ST2 PB15 _RTS4 _LIRQA LIST4 PC11 CDA LIRSYNCA PA2 RXD2 PB10 SMTXD2 L1CLKOB PC6 _CTS2 PC7 _CD2 _TGATE2 PC10 CTS4 LITSYNCA SDACK1 PB6 SMTXD1 DONEI PB5 BRGO2 _DACK1 PB4 BRGO1 DREQI PB11 SMRXD2 L1CLKOA P
65. internal 68EN360 and a seven level VMEbus in terrupt handler with the corresponding mask register 2 6 2 1 Internal Requests Internal requests are related to all interrupt requests caused by the 68EN360 sources including the 68EN360 system integration functions watchdog timer periodic interrupt timer and the communica tion processor module RISC controller timers DMAs SCCs and so on For more information please refer to the 68EN360 User s Manual In order to avoid conflicts regarding interrupt levels it is recommended to use IRQ level 4 for 68EN360 CPU internal requests and IRQ level 6 for 68EN360 SIM60 internal requests Note The four IRQ lines specified by CXC are supplied by the 68 EN360 Port C lines and are therefore also processed as internal requests PCO 1 2 3 Page 2 14 PEP Modular Computers Juli 23 1997 Chapter 2 Functional Description VM162 VM172 2 6 2 2 External Autovectored Interrupt Requests Autovectored interrupts are all generated via the 68EN360 pins for external interrupt sources They are summarized in the table below Care must be taken that the relevant 68EN360 register is initialised with respect to the wiring see also the Programming chapter in this manual Table 2 8 External Autovectored Interrupts 68EN360 Pin Autovector ABORT ACFAIL IRQ7 7 TICK IRQ6 6 Mailbox IRQ IRQS 5 SYSFAIL IRQ3 3 2 6 2 3 VME Interrupt Mask Register CS7 1 The VME Interrupt Mask Regi
66. ls for a period of 24 consecutive months from the date of purchase This warranty is not transferable nor extendible to cover any other consumers or long term storage of the product This warranty does not cover products which have been modified altered or repaired by any other party than PEP Mo dular Computers or their authorized agents Furthermore any product which has been or is suspected of being dama ged as aresult of negligence misuse incorrect handling servicing or maintenance or has been damaged as a result of excessive current voltage or temperature or has had its serial number s any other markings or parts thereof altered defaced or removed will also be excluded from this warranty A customer who has not excluded his eligibility for this warranty may in the event of any claim return the product at the earliest possible convenience together with a copy of the original proof of purchase a full description of the ap plication it is used on and a description of the defect to the original place of purchase Pack the product in such a way as to ensure safe transportation we recommend the original packing materials whereby PEP undertakes to repair or replace any part assembly or sub assembly at our discretion or to refund the original cost of purchase if appropriate In the event of repair refund or replacement of any part the ownership of the removed or replaced parts reverts to PEP Modular Computers and the remaining
67. m compatibility between the standard CXC functions In addition all signals are availa ble in order to configure 2 time division multiplexed channels via the CXC ISDN PCM GCI and so on Multi function pins with incompatible functions with regard to the 68302 and 68EN360 called user defined in the generic CXC specification are not part of the VM162 VM172 CXC specification Although the SMCs are configured on the base board these ports are also integrated on the CXC This is because of possible ISDN applications where SMCs can be integrated and other protocols supported by the 68EN360 Note If the RCLK2 signal CXM pin c16 is required jumper J11 24 MHz clock must be opened and the serial drivers delivered by PEP modified Page 2 28 PEP Modular Computers Juli 23 1997 Chapter 2 Functional Description VM162 VM172 Table 2 11 Further Explanation of 68 EN 360 Mnemonics SCC IDMA TIMER SPI Signal Name Receive Data Transmit Data Request to Send Clear to Send Carrier Detect Receive Start Receive Reject Clocks DMA Request DMA Acknowledge DMA Done Timer Gate Timer Input Timer Output SPI Master In Slave Out SPI Master Out Slave In SPI Clock SPI Select Row B Signals RXD4 RXD1 TXD4 TXDI _RTS4 _RTS1 _CTS4 _CTS1 _CD4 _CD1 _RSTRT1 CLK8 CLK1 _DREQ2 _DREQI _DACK2 _DACK1 _DONE2 _DONE1 _TGATE2 _TGATE1 TIN4 TIN1 _TOUT4 _TOUT1 SPIMISO
68. nel to avoid false operation The RESET button triggers the on board system reset generator as well as the VME if jumper J2 is set Together with the RESET button an ABORT button is also fitted to the front panel The ABORT button generates a level 7 IRQ non maskable interrupt which is used for debugging purposes In this case bit 1 of the Board Control Status Register is not set remains 0 2 7 7 2 LED Port The front panel LED port consists of three LEDs with the following functions Red LED CPU in HALT or RESET status Yellow LED Watchdog timer running status Green LED General purpose set via Board Control Status Register The green LED is free to be used by the customer It is set by the software during startup when the 68EN360 is initialized Juli 23 1997 PEP Modular Computers Page 2 19 VM162 VM172 Chapter 2 Functional Description 2 8 Serial Communication Ports The 5 serial ports of the VM162 VM172 are based on the 4 SCCs and 1 SMCs of the 68EN360 These multiprotocol serial ports can be physically translated to the different standards due to application spe cific demands A view of the range of front panels available for the VM162 VM172 can be found in Fi gure 1 1 of this manual Figure 2 2 MC68EN360 Channel Assignment MC68EN360 Channel Assignment E OOIT SI Piggyback Interface SI Interface MC68EN360 GE RS232 with Rx and Tx only BH Real
69. nevecsesenerecoesanenensesenence 2 22 Juli 23 1997 PEP Modular Computers Page 2 1 VM162 VM172 Page 2 2 Chapter 2 Functional Description 2 63 EE 2 23 29 EE 2 24 2 10 IndustryPack IP Interface ON EE 2 30 KEEN 2 30 KT 2 30 2 10 3 Optional IP features NOt supported 2 30 2 10 4 IP Interface Controller ss 2 31 2 10 5 JP HE E 2 31 2 10 6 IP Clock Control EO ER EE N 2 31 2 10 7 IP Interrupt Control 2 31 2 10 8 IP Memory Size Control ss 2 32 2 10 9 IP Interface Address Map ss 2 32 2 10 10 Interrupt Control Register ss 2 33 2 10 11 Slot Control Register uie ses see ss 2 34 2 10 12 ei N ME RE ER EE EG 2 35 PEP Modular Computers Juli 23 1997 VM162 VM172 Chapter 2 Functional Description 2 1 VM162 VM172 Block Diagram ost sspsu 6 ansa a E e ansan e ansan sasan e ansan TE ae ERATI aum zo sperm ao speu zo speu ao speu mue o6 ansa mue 06 ansa suoqqng Do EE RES Ee WIL Tags zaas euas mod weg vaas o I zeg out zes o I zes 0 1 zes O I al O I al qa LES SnApTeT4 1EUZEYIE l TER EH EER scons I test ado i I test ado f I test ado mue m
70. o I sevsa seven seven i etqeoaeta etqeoaera zezeu seen i zezeu gp aac Oh Seel lide es EE ee e ee wee Tas axa axa maa O I dl 0 1 ar li i i 1 tow Th Bopyoyem I las s os ge zouti sng i pue e l zetpueH Our gt 1 a v f Ca 1 YOOTISUTL TRON f l e so JOTS dI 3 TS dI zeqstbey preog Re AN dnyors I EH l o I 5oteuw ZodTen l ER l wo Isos WYS Teng SIOTS dI E See ede ae air e ta I EE SO ree N LO ade wo 1 E pen zea zev TOIS EN SDPJISJUI IXJ soPJISIUI 90e71oqu A peoueyug FI9JUI FWA Moed Axasnpur Cado wowj00g S19JINg 19zTSSNg Li E I ER EE 07089 FRR EES kel Wouda As zum 99 05 09089 EE O9ENASLI Terzes onn HSVIA mwaa E A EE 1 ZOSSEDOZA O I ndo ga Azowayn EE GS qa SS A MA SO gh NE J Page 2 3 PEP Modular Computers Juli 23 1997 VM162 VM172 Chapter 2 Functional Description 2 2 CPU Options By supporting several types of CPUs the VM162 VM172 provides scalable computing power at optimi zed costs The CPU types differ in performance power requirement and supported functions Optional on chip functions are Memory Management Unit MMU and Floating Point Unit FPU There are three categories of VM162 VM172 CPU boards At the top there is the 68060 CPU board which offers 2 to 3 times performance of a the following 68040 CPU board At the low end there is the CPU 68040V board which is the
71. of or during any period since the purchase of the product Please remember that no PEP Modular Computers employee dealer or agent are authorized to make any modification or addition to the above terms either verbally or in any other form written or electronically transmitted without consent Page 0 4 PEP Modular Computers Juli 23 1997 VM162 VM172 Chapter Introduction d d Product CENT DEV li a 1 3 1 2 IndustryPack Flexibility AE EE EE EE N 1 3 1 3 Controller eXtension EE 1 4 1 4 Front Panel and HO Configuration osooso 1 4 EE RE Saddi 1 6 LO SCOT OO a N N po op pankat ea 1 8 1 7 Ordering more NON isi aid kaa kk ka kd eek AN kk kisa ees 1 10 1 8 Related Publications semaines 1 11 1 9 Schematic Board Layout MO EE EE NE HG 1 12 Juli 23 1997 PEP Modular Computers Page 1 1 VM162 VM172 Chapter 1 Introduction m Page 1 2 PEP Modular Computers Juli 23 1997 Chapter 1 Introduction VM162 VM172 1 1 Product Overview PEP s VM162 172 combines high computational performance and flexible I O requirements through its twin IndustryPack and single CXC interface with excellent communication ability afforded by the Mo torola QUICC controller A combination of high performance CPUs Motorola MC68040 MC68060 and the Quad Integrated Communications Controller chip the Motorola MC68EN360 QUICC not only enable computational performances from approximately 35 MIPs to over 100 MIPs
72. onnected 8 Not connected Page SI6 4 PEP Modular Computers Juli 23 1997 Appendix SI6 Piggybacks 3 3 Jumper Location 00 J3 00 J2 00 Ji Jumper J1 Squelch Threshold ER NEE Normal Default 4 5dB reduced threshold Jumper J2 Link Test See Link Test enables Default Link Test disabled Jumper J3 Shielding EE Unshielded 100Q termination Default Shielded 1500 termination Juli 23 1997 PEP Modular Computers Page SI6 5 Appendix SI6 Piggybacks 4 SI6 PB485 ISO The SI6 10BT is an RS485 optoisolated interface piggyback for 2 wire half duplex PROFIBUS connection It has one LED fitted indicating data transmission 4 1 Specifications On board termination Isolation Voltage Max Baud Rate 1500 jumper selectable Optocoupler specified up to 2 5 kV 10 Mbit s as specified by Ethernet 4 2 Connector Mi Pin 1 9 pin D Sub Connector Pin 5 Pin 6 Pin 9 PROFIBUS Sie Tx Transmit L7 O Yellow PEN Signal SHIELD RP RxD TxD CNTR DGND VP RP RxD TxD CNTR OL eet 2 ny ny AJN e Description Shield Protective Ground resp Reserved for power Receive Transmit Data Control Data Ground Voltage Plus Reserver for power Receive Transmit Control Page SI6 6 PEP Modular Computers Juli 23 1997 Appendix SI6 Piggybacks 4 3 Jumper Location J6eee 213
73. or software which searches memory during startup and should not find any old modules e g OS 9 Make sure that the XON XOFF protocol is used on the host side This is a fixed setting and cannot be changed Additio nally make sure that your host does not stop transmission after a number of lines e g OS 9 use the nopause attribute Serial parameters can be modified with the pf command Juli 23 1997 PEP Modular Computers Page BOOT 3 Appendix Bootstrap Loader Example 1 The host is assumed to be an OS 9 development system A serial cable is used to connect the ser0 port of the board to pro gram to t0 of the development system Additionally we assume that we want to program a PEPbug image which is availa ble as a file pbVM42 in a binary image format The serial connection should run at 38400 Baud The following steps must be performed Host xmode t0 baud 38400 nopause iniz tO Target pf ser0 38400 lf Host binex s3 a 4000000 pbvM42 gt t0 Example 2 The host is assumed to be a PC with Windows Windows95 or WindowsNT A serial cable is used to connect the sert port of the board to program to COM2 of the PC Additionally we assume that we want to program a Motorola S record built for address 0 e g the VxWorks file bootrom hex The serial connection should run at 19200 Baud The following steps must be performed Host In a DOS Window configure the COM 2 port to the correct parameters mode com
74. orola S Records Programming is done with the Zf command The If command accepts S1 S2 and S3 records Operation is terminated by the appropriate S9 S8 or S7 record Other types of records are ignored The checksum of every record is checked bad records are refused by the Bootstrap Loader The address range of every record is also checked records that try to overwrite the Bootstrap Loader are refused Additionally every record must match the programmable area exactly To give the user an overview of the available ranges the startup banner includes address information If Sl or S2 record input is preferred please note that these records only include 16 and 24 bit wide addresses Therefore in order to reach the FLASH area an address offset must be specified using the o option of the Jf command Additio nally it must ensured that the code is not larger than the covered address range Note The If command cannot be used to provram Motorola S records to RAM areas For the neccessary serial connection the lower term or upper serO RJ12 front panel connectors can be used The serO port should be preferred because in this configuration it is possible to monitor the progress of the operation via the term port If not otherwise specified sectors which are not touched by the programming operation are not erased If you want to erase all sectors while programming the c option can be specified along with the Ifcommand This is useful f
75. out The port based on the SMC is fixed to RS232 interfaces This port supply RxD TxD interfaces with soft ware handshake XON XOFF capability Usually this port is used as terminal debug port RJ45 Connector N C Not Connected Page 2 23 Juli 23 1997 PEP Modular Computers VM162 VM172 2 9 CXC Interface Chapter 2 Functional Description The Controller Extension Connector CXC is a local mezzanine interface The CXC contains a 16 bit data bus 7 address lines and 8 decoded chip select lines In total there are 8 control signals The base address of the CXC can be programmed via the CSS line of the 68EN360 The 8 CXC chip selects CXC_CSO CXC_CS7 occupy 256 Bytes each and have an address length of 400H 512 Bytes Furthermore the CXC contains 4 IRQ capability 4 edge sensitive IRQs DMA capability 1 channel DREQ DACK serial ports 3 channels Full MODEM and a set of parallel port signals These spe cial CXC functions are based on the 68EN360 resources For general CXC information including generic pinouts and a comparison of the 68 EN 360 and 68302 CPU pinouts on the CXC please refer to the CXC Specification User s Manual and the CXC Appendix attached to this manual Table 2 10 CXC Pinouts using the 68 EN 360 Pin Row A Signals Row B Signals Row C Signals PCO RTSI LISTI PCI RTS2 LIST2 PC2 RTS3 LIRQB LIST3 PC3 RTS4 LIRQA LIST4 PBO SPISEL RRJCTI PB1 SPICLK _RSTRT2 VCC PB
76. r Comment SER1_RCLK SER1_TCLK SER1_TXD SER1_RXD PB13 PB17 SER1_RTS SER1_DTR SER1_CTS SER1_CD Page 2 25 Juli 23 1997 PEP Modular Computers VM162 VM172 Chapter 2 Functional Description CXC Pin Nr 68302 HW Function Compatible SER2 TCLK c Yes Port PA13 68 EN 360 Comment Cannot be used if J6 is set See note 3 c SER2_RTS c Yes PB14 Yes SER2_DTR c SER2_TXD c Yes PAS a SER2 CIS c Yes PC8 SER2_CD cl Yes PC9 CXC 68302 HW SER3_TCLK c5 Yes PA14 SER3_TXD CH Yes PA7 Not usable if SI Module uses SCC4 See note 4 16 15 17 12 11 13 1 68 EN 360 Port PAIS Comment Not usable if SI Module uses SCC4 See note 4 SER3 RXD c9 Not usable if SI Module uses SCC4 See note 4 i al2 Yes b16 Yes Yes PA6 Yes PB15 PB9 PC10 PCI1 Not usable if SI Module uses SCC4 See note 4 Not usable if SI Module uses SCC4 See note 4 Not usable if SI Module uses SCC4 See note 4 Not usable if SI Module uses SCC4 See note 4 Page 2 26 PEP Modular Computers Juli 23 1997 Chapter 2 Functional Description CXC 68302 HW Function Compatible user defined No Notes Reserved Pins 68 EN 360 Port VM162 VM172 Comment Used on board SPI SEL for EEPROM Cannot be used on CXC See note 2 SPI Clk can be used if an SPI SEL other than PBO is used SPI TxD can be used if an SPI
77. r TSA Among many others protocolls supported by the SCCs for example are UART HDLC SDLC Apple Talk Ethernet IEEE 802 3 X 21 and Signaling System 7 The Time Slot Assigner supports building 2 time domain multiplexed TDM channels to be for instance E1 T1 ISDN Basic Primary Rate or User Defined Warning In the PEP supported BSP s for OS 9 version 3 0 PEP makes sure that the proper ini tialization sequence for the QUICC is followed Never change this initialization se quence as unexpected errors may occur 2 4 1 Use of 68EN360 Communication Ports The 68EN360 provides 5 serial ports based on 4 SCCs and 1 SMCs These multiprotocol serial ports can be physically translated to the different standards due to application specific demands This translation is very flexible on the VM162 VM172 by using SI and SC piggybacks or even CXMs 5 configured serial ports are available at front panel connectors Page 2 6 PEP Modular Computers Juli 23 1997 Chapter 2 Functional Description VM162 VM172 2 4 2 Use of 68EN360 Memory Controller Beside its main purpose which is to provide communication power to the VM162 VM172 the I O con troller 68EN360 is also used for some system integration function First of all this is DRAM control and global memory decoding Therefore the 8 CS lines provided by the 68EN360 memory controller are connected to the different memory types or address areas folllowing the scheme in the following Table
78. red pattern changes in the same way If not the search must be continued or if yes the memory size is found Note The MC68040 normally operates in non serialized mode meaning that read accesses can occur before write accesses even if they are programmed in the opposite way It is therefore recommended that especially when changing the patterns a nop instruction should be inserted as this forces all pen ding cycles to be completed 13 Set vector and IRQ level for internal IRQ requester e vector base 0x40 e level 4 0x8040 L gt CICR 14 Set SDMA configuration register 0x770 W gt SDCR 15 If the card is in the first slot enable the VMEbus monitor If bit 4 in VCSR is set then set bit 5 in VCSR 16 Enable on board I O bus error timer Set bit 2 in BCSR Page 4 6 PEP Modular Computers July 19 1997 Chapter 4 Programming VM162 VM172 Address List of Involved Registers MBAR Ox3FF00 CPU space RSR 0xC0001009 SYPCR 0xC0001022 MCR 0xC0001000 PLLCR 0xC0001010 CDVCR 0xC0001014 CLKOCR 0xC000100C PEPAR 0xC0001016 GMR 0xC0001040 AVR 0xC0001008 BRO 0xC0001050 ORO 0xC0001054 BRI OxC0001060 ORI 0xC0001064 BR2 0xC0001070 OR2 0xC0001074 BR3 0xC0001080 OR3 0xC0001084 BR4 0xC0001090 OR4 OxC0001094 BRS OxC00010A0 ORS OxC00010A4 BR6 OxC00010BO OR6 0xC00010B4 BR7 0xC00010C0 OR7 0xC00010C4 CICR 0xC0001540 SDCR 0xC000151E VCSR 0xCD000005 BCSR 0xCD000007 4 3 Initializing the Cache Before the system
79. ry NEVER press the RESET button or cyole power This may da mage the Bootstrap Loader and will consequently leave the board unusable due to damaged FLASH contents The ABORT button may be used to cancel a running operation Juli 23 1997 PEP Modular Computers Page BOOT 1 Appendix Bootstrap Loader 2 System Operation 2 1 Startup After system reset the Bootstrap Loader is started It searches the FLASH memory area for a valid start key If this start key is found the Bootstrap Loader checks the BootWaitTime from serial EEPROM If the time is valid the continuation of the boot process is delayed by this time while flashing the green front panel LED to indicate that the system is alive but waiting for continuation If the time is not valid a default of 5 seconds is used After the BootWaitTime has passed the program in FLASH is started The Bootstrap Loader has two modes of operation non interactive start mode as described above and the interactive com mand mode For normal board operation only the non interactive start mode is used to start a program in FLASH This is done auto matically without any user interaction The interactive command mode is used to re program the FLASH memory contents or change the BootWaitTime The serial term port operates at 9600 Baud 8 bits character 1 stop bit and no parity 2 2 Entering the Command Mode There are two possible cases If no valid start key was found the Bootstrap Loa
80. s AAS ER N OE DE EE EE EE 2 4 23 Memory saesae EE EE EE cn 2 4 KE EE EE 2 4 E E EE 2 5 2 3 3 Boot ROM OPINA sci sses ivvevsseessecesstesedecunsdedsivasnapecsavscensessensinaseasneadutesadeasgeees 2 5 2 34 EE E 2 6 2 4 Communication Controller 6SEN360 QUICC ee ees se ee 2 6 2 4 1 Use of68EN360 Communication Porte 2 6 2 4 2 Use of68EN360 Memory Controller ss 2 7 2 4 3 Use of 68EN360 Interrupt Controller ss 2 7 2 4 4 Use of68EN360 DMA Channels 2 8 KE We 2 8 2 5 1 VME Master Interfaces ce srossseodvencsotoesensonsenssuascesscesens 2 9 2 5 2 System Controller Funentons ese ese ss 2 10 2 5 3 VME Slave Interface ee ese ee ee ee se ee ee Re Ge ee GR SR Ge ee ee ee ee ee 2 11 2 5 4 VME Address Map from the VME Side 2 12 2 5 5 WME Control Status Register 2 13 2 6 Board Control TORIC ja EN inda lb GE GE 2 14 2 6 1 Boot Decoder Logic ss 2 14 2 6 2 Interrupt EE 2 14 EE EE 2 16 2 64 Watchdog teste tnt aati Uae 2 16 2 6 5 Board Control Status Register 2 16 2 7 N di ee enee EE OO ap ke kika 2 18 2 11 Real E 2 18 2 7 2 Serial EEPROM ie Gee ee Ge Gees desas v t Gee See ee tous Seded se bibon 2 18 2 7 3 HEOK EE 2 18 2 7 4 General Purpose Ter 2 18 2 159 DMA FRANS OS ner see antenne e l ete ne nee tienne EEEE 2 18 2 7 6 Data Retention for RTC and SRAM ss 2 19 2 7 7 Front Panel Buttons and LED Ports 2 19 2 8 Serial E 2 20 2 8 1 Ethernet SER4 Port 2 21 2 8 2 SERI SER2 and SER3 POTIS scssseveccesesesercesevenense
81. ster is a one byte wide register with read write access situated at default address CD 00 00 01 HEX All bits are cleared after reset 7 6 5 4 3 2 1 0 Note The firmware of the board initializes this register using the default parameters stored in the EE PROM Register Description Name Value Description EN IRQ7 Enable VME IRQ7 EN_IRQ6 Enable VME IRQ6 EN IROS Enable VME IROS EN_IRQ4 Enable VME IRQ4 EN_IRQ3 Enable VME IRQ3 EN_IRQ2 Enable VME IRQ2 EN IRQI Enable VME IRQ1 SYSFAIL Enable VME SYSFAIL IRQ Juli 23 1997 PEP Modular Computers Page 2 15 VM162 VM172 Chapter 2 Functional Description 2 6 3 Bus Timer The VM162 VM172 provides an 128s timeout timer which monitors the cycle lengths of on board data transfers including on board I O CXC IndustryPack dual ported SRAM and some VME After a timeout occurs it generates an on board BERR signal for error termination This timer is enabled disabled via the Board Control Status Register which also supplies a timeout sta tus bit in order to identify bus errors generated by the on board bus error timer Note During VMEbus cycles the on board bus error timer is reset as soon as the VM162 VM172 gains VMEbus ownership This means that the time gap between a VMEbus request and the start of a VMEbus cycle is monitored by the on board Bus Timer VMEbus cycles themselves are monitored by the separate VME Bus Monitor 2 6 4 Watchdog Timer A 512ms watchdog
82. t to 8 MHz by default After detecting that the assembled IP module supports also 32 MHz by reading information stored within the module s ID PROM the IP clock can be switched to 32 MHz by setting bit 5 of the IP slot control register On the IP interface controller there are implemented in parallel separate clock generators and state ma chines for the different IP bus speeds Therefore each IP slot can operate at its individual bus speed 2 10 7 IP Interrupt Control Both IP IRQ lines INTO an INTI can be used to generate interrupt requests By programming the IRQ level bits the interrupt priority of the corresponding IP slot can be selected in a range of 1 to 7 low to high priority Each IP slot provides two interrupt request lines per definition Both IRQ lines INTO and INT are sup ported per slot by the IP interface controller but for selecting IRQ priotity there are the following re strictions gt INTI IRQ priority can be set only to level 1 3 5 or 7 gt INTO IRQ priority can be set only to level 2 4 or 6 If both IP slots use the same IRQ level IP slot a has automatically a higher priority than IP slot b Note A separate Interrupt Enable bit for each INT must be set before any IP interrupt can be passed from the corresponding IP slot to the CPU After a board reset the complete IP interrupt control logic is reset by default That means the Interrupt Enable bit is cleared as well as the IRQ level bits BIT 2 0
83. the propagation of the process cannot be monitored It is recommended that by default the programming over the ser port should be used If the process must be aborted press the ABORT button and try again 3 3 Programming from an Absolute Address The second possibility to program FLASH memory is to program it from an absolute address The image to program must be located in a visible address range for example on the VMEbus A memory card with battery backup FLASH or EPROM can be used to hold the image to program If we assume that the image is located at 0x87000000 and is 0x 123456 bytes large we must type the following at the command prompt of the Bootstrap Loader 1f m 87000000 1 123456 The characters which are displayed now have the same meaning as if we are programming from S records but the time needed for each step to complete may be longer because the loader tries to program with the largest possible block size that it can manage Again c can be used to clear untouched sectors Background operation is not supported and it is also not possible to specify an offset The programming cannot be aborted with ABORT Juli 23 1997 PEP Modular Computers Page BOOT 5 Appendix Bootstrap Loader 3 4 Boot Wait Time The command bw can be used to display change the current BootWaitTime Available delays are 1 2 5 10 20 50 seconds Note The BootWaitTime is stored in the boot section of the serial EEPROM This section is val
84. timer is also provided by the VM162 VM172 Once enabled via the Board Control Status Register the watchdog timer cannot be reset by software It must be re triggered via the corre sponding bit in the Board Control Status Register periodically within the timeout period Watchdog timer running is a status that is displayed by the yellow front panel LED At timeout the watchdog timer triggers the on board system reset Note If the board s VME SYSRES jumper is set the watchdog timer can reset the whole of the VME system 2 6 5 Board Control Status Register The Board Control Status Register is a one byte wide register with read write access at default address CD 00 00 07 HEX 7 6 5 4 3 2 1 0 087487 Note Information may be lost if the user writes to bit 7 Page 2 16 PEP Modular Computers Juli 23 1997 Chapter 2 Functional Description VM162 VM172 Register Description BERRI bit 5 EN_WDG bit 4 TR_WDG bit 3 EN BERRI bit 2 ACFAIL bit 1 LED_G bit O Access Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Description Set by watchdog timer when timeout has been reached Used to differentiate between resets caused by the watchdog and resets caused by the reset button power up resets can be identified within the 68EN360 Set by VMEbus BUS monitor when timeout has been reached Used to identify BERR caused by this t
85. tional Description m This page has been intentionally left blank Page 2 38 PEP Modular Computers Juli 23 1997 Chapter 3 Configuration VM162 VM172 Chapter Configuration 3 1 Default Jumper Eegeregie 3 3 3 1 1 Jumper Default Settings Component Side 3 3 3 1 2 Jumper Default Settings Solder Side ss 3 3 3 2 Jumper Description Component Side 3 4 32A VME EE 3 5 KE 3 5 3 2 3 Protective Ground Signal Ground ss 3 5 3 2 4 VME SYSRES EN 3 5 3 29 DAE EA EE N EE EE as cs 3 6 3 3 Jumper Description Solder Side 3 7 ki MANS LENTE RR N EE ER EN ER 3 8 3 3 2 CPU SUE OE OE OE RE EE OR 3 8 3 3 3 CPU Bus Clock ss dns een elie RE ee eee 3 8 KE EE 3 8 3 3 5 Communications Clock 3 9 3 3 6 EEPROM Write Protection 3 9 3 3 7 STAG e 3 9 3 3 8 SRAM Data Retention ir Ge RA GR aeee Se ee ee ee ee ee 3 10 KEEN 3 10 3 3 10 Backup Current Test Bridge 3 10 Juli 23 1997 PEP Modular Computers Page 3 1 VM162 VM172 Chapter 3 Configuration m Page 3 2 PEP Modular Computers Juli 23 1997 Chapter 3 Configuration VM162 VM172 3 1 Default Jumper Settings The VM162 VM172 has four wire jumpers which can be configured by the user Additionally the VM162 VM172 has a set of solder jumpers which are factory set The list of default settings are shown below 3 1 1 Jumper Default Settings Component Side Jumper poet Description p Setting p J1 Open Boot from VMEbus memor
86. ve VME SYSRES If the VM162 VM172 is not intended to drive VME SYSRES the signal can be disconnected using a jumper Note In contrast to SYSCLK which may be driven by one board in the system SYSRES may be driven more than once in a system SYSRES originating from another power monitor within the system always resets the VM162 VM172 2 5 2 4 VMEbus Monitor The VM162 VM172 also provides a bus monitor for the VMEbus A 128 us timeout timer monitors VMEbus data transfer cycle lengths and generates a VMEbus BERR signal for error termination This timer is enabled disabled via the VME Control Status Register which also supplies a timeout status bit in order to identify bus errors generated by the VMEbus monitor 2 5 3 VME Slave Interface 2 5 3 1 Dual Ported RAM The VM162 VM172 provides 256 kByte or 1 MByte of on board SRAM which is dual ported between the CPU and VMEbus Read Modify Write cycles TAS instruction used for semaphores are supported in any direction The location of the dual ported SRAM as seen from VME is programmable via the VME Control Status Register There are 16 different base addresses possible with separate enable disable functions all loca ted in VME A23 D 16 space Note The lowest 8 kByte of the dual ported SRAM is reserved for generating mailbox interrupts 2 5 3 2 Mailbox Interrupt An external VMEbus master may interrupt the VM162 VM172 by setting the corresponding mailbox in terrupt bit This bit called
87. ve access to this memory EEPROM A 2 kbit EEPROM is provided on board kbit has been pre programmed with PEP production data lea ving the remaining available space for user application code Juli 23 1997 PEP Modular Computers Page 1 7 VM162 VM172 1 6 Specifications CPUs Comms Controller Real Time Clock Tick Timer Time Out Interrupts System Vectors System Controller Address Modifier Slave Functions IndustryPack Interface CXC Interface Chapter 1 Introduction MC68040 V 33 MHz MC 68060 50 MHz MC68EN360 Companion processor for network support on SI6 piggybacks 1 4 16 32 MByte 32 bit access DRAM 0 5 1 2 4 MByte 32 bit access FLASH Available on DM6xx Memory Piggyback 256 kByte or 1 MByte dual ported SRAM with data retention via Goldcap 2 kbit serial EEPROM for configuration data 2 ROM sockets for up to 1 MByte device optional V3021 with year month week day hour min sec Built in on MC68EN360 providing a programmable periodic interrupt default 10ms 4x16 2x32 bit resolution built in timers on the MC68EN360 On board BERR time out min 8us max 128us 128us VMEbus BERR both with software enable disable Watchdog Enabled by software with front panel LED VME IRO1 IRQ7 interrupts enable disable Mask Register SYSFAIL and ACFAIL handlers Abort switch ACFAIL TICK level 7 autovector level 7 autovector level 6 vector prog SYS
88. y disabled J2 Open Boot from boot ROM disabled J10 Set On board reset generator to VME J11 Open Enhanced CXC mode disabled Open Protective ground disconnected from signal ground J8 solder jumper 3 1 2 Jumper Default Settings Solder Side Jumper Derauit Description p Setting p Dependent on board version J3 CPU type Dependent on board version J12 J15 CPU power supply Dependent on board version Dependent on board version J21 Set BERRI timeout 128us selected J22 Set VCB current test bridge J5 J7 CPU clock speed J19 and J20 SRAM size Juli 23 1997 PEP Modular Computers Page 3 3 VM162 VM172 Chapter 3 Configuration p 3 2 Jumper Description Component Side Figure 3 1 VM162 VM172 Jumper Layout Component Side J8 J1 VME Boot Protective GND PP J2 ROM Boot VME SYSRES J10 Signal GND RJ45 RJ58 or 15 Pin D Sub Connector J11 CXC Mode VME Connector P1 RJ45 Mini D Sub Serial port Connectors eeeeeeseeeeeeeee PI eoeccccceccccccce Ceccccccccscecceces D le essesese eseese 000000 VME Connector P2 eseoooooeooooooo FR see nee oeeeeeeee el Page 3 4 PEP Modular Computers Juli 23 1997 Chapter 3 Configuration VM162 VM172 3 2 1 VME Boot The VM162 VM172 normally boots from the FLASH memory on the DM60x piggyback
89. ystem lt gt Terminal 1 1 Software XON XOFF or no Handshake 1 1 1 15 pin Connector on OS 9 Side 15 pin male 25 pin male 7 GND 7 GND SIGNAL ground 2 TxD 2 TxD 3 RxD 3 RxD 4 CTS Do 4 CTS 5 RTS 5 RTS 6 DSR 8 DCD lan 20 DTR 1 1 2 8 pin RJ45 Connector on OS 9 Side SMART I O 8 pin RJ45 25 pin male 3 GND 7 GND SIGNAL ground 4 TxD 3 RxD 5 RxD 2 TxD 7 CTS E Do 4 RTS 2 RTS 5 CTS 6 DSR 8 DCD 20 DTR November 21 1996 PEP Modular Computers Page OS 1 Appendix OS 9 Cabling e 1 1 3 6 pin RJ12 Connector on OS 9 Side 6 pin RJ12 2 GND 3 TxD 4 RxD 6 CTS 1 RTS 25 pin male m OU A N O NI GND SIGNAL ground RxD TxD RTS CTS DSR DCD DTR Page OS 2 PEP Modular Computers Novemeber 21 1996 Appendix OS 9 Cabling 1 2 Hardware Handshake Set Terminal to CTS DTR Handshake 1 2 1 15 pin Connector on OS 9 Side 15 pin male 25 pin male 7 GND m 7 GND SIGNAL ground 2 TxD 3 RxD 3 RxD L 2 TXD 4 CTIS m 20 DTR 10 DTR CTS 6 DSR 8 DCD 1 2 2 8 pin RJ45 Connector on OS 9 Side SMART I O 8 pin RJ45 25 pin male 3 GND e 7 GND SIGNAL ground 4 TxD 3 RxD 5 RxD 2 TxD 7 CTS 20 DTR 8 DTR 5 CTS 6 DSR 8 DCD November 21 1996 PEP Modular Computers Page OS 3 Appendix OS 9 Cabling 2 OS 9 System lt gt PC 2 1 Software XON XOFF or no Handshake 2 1 1 15 pin Connector on OS 9 Side 25 pin Conne

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