DE1 Development and Education Board User Manual
Contents
1. VGA 0 PIN_A9 VGA Blue 0 VGA B 1 PIN 011 VGA Blue 1 VGA 2 PIN A10 VGA 2 VGA_B 3 PIN_B10 VGA Blue 3 VGA_HS PIN A11 VGA H SYNC VGA VS PIN B11 VGA V SYNC Table 4 8 ADV7123 pin assignments 4 7 Using the 24 bit Audio CODEC The DEI board provides high quality 24 bit audio via the Wolfson WM8731 audio CODEC enCOder DECoder This chip supports microphone in line in and line out ports with a sample rate adjustable from 8 kHz to 96 kHz The WM8731 is controlled by a serial I2C bus interface which is connected to pins on the Cyclone II FPGA A schematic diagram of the audio circuitry is shown in Figure 4 15 and the FPGA pin assignments are listed in Table 4 9 Detailed information for using the WM8731 codec is available in its datasheet which can be found on the manufacturer s web site and from the Datasheet folder on the DE1 System CD ROM VCC33 VCC33 i r R2 R3 ci 10 RI 47K 2k 2k C2 10 R4 47K 2 SCLK DC SDAT RE 4 7K lt 47K I2C ADDRESS READ IS 0x34 I2C ADDRESS WRITE IS 0x35 AGND AGNO 2C SDAT 2C SCLK A_VCC33 GND XTO ES DBVDD LK LK WM8731 RO 4 FEF QFN2E 0 45 AS OA VCC33 AUD XCK TC 100U 3V AUD BCLK 1210 c AUD DACDAT A VCC33 c AUD DACLRCK 9 l AUD ADCLRCK2. r Sequential Read Address n Length o Entire Sdram Load SDRAM Contentto a File Figure 3 5 Accessing the SDRAM 13 AND YAN DEI User Manual A 16 bit word can be written into the SDRAM by entering the address of the desired location specifying the data to be written and pressing the Write button Contents of the location can be read by pressing the Read button Figure 3 5 depicts the result of writing the hexadecimal value 6CA into location 200 followed by reading the same location The Sequential Write function of the Control Panel is used to write the contents of a file into the SDRAM as follows 1 Specify the starting address in the Address box 2 Specify the number of bytes to be written in the Length box If the entire file is to be loaded then a checkmark may be placed in the File Length box instead of giving the number of bytes 3 To initiate the writing of data click on the Write a File to SDRAM button 4 When the Control Panel responds with the standard Windows dialog box asking for the source file specify the desired file in the usual manner The Control Panel also supports loading files with a hex extension Files with a extension are ASCII text files that specify memory values using ASCII characters to represent hexadecimal values For example a file containing the line 0123456789 ABCDEF defines four 16 bit values 0123 4567 89AB CDEF These values will be lo
3. TUA an 10 Red LEDs isi I ri i r1 i ri i i gt ri T is 8 Green LEDs z e SMAExternal Clock s090 gg 45050 Dh dib aM 4 Push button Switches 8Mbyte SDRAM 5 12Kbyte SRAM 4Mbyte Flash Memory Figure 2 1 The DEI board The DEI board has many features that allow the user to implement a wide range of designed circuits from simple circuits to various multimedia projects DEI User Manual The following hardware is provided on the DEI board Altera Cyclone II 2C20 FPGA device Altera Serial Configuration device EPCS4 USB Blaster on board for programming and user API control both JTAG and Active Serial AS programming modes are supported 512 Kbyte SRAM 8 Mbyte SDRAM 4 Mbyte Flash memory SD Card socket 4 pushbutton switches 10 toggle switches 10 red user LEDs 8 reen user LEDs 50 MHz oscillator 27 MHz oscillator and 24 MHz oscillator for clock sources 24 bit CD quality audio CODEC with line in line out and microphone in Jacks VGA DAC 4 bit resistor network with VGA out connector RS 232 transceiver and 9 pin connector PS 2 mouse keyboard connector Two 40 pin Expansion Headers with resistor protection Powered by either a 7 5 V DC adapter or a USB cable In addition to these hardware features the DEI board has software support for standard I O interfaces and a control panel facility for accessing various components Also software is provided for a numbe
4. 10008 3 1210 RU Btt Bc2 0 1 I 1U 0 10 AGND Figure 4 15 Audio CODEC schematic 38 JAN DTE RAN DE1 User Manual AUD_ADCLRCK PIN_A6 Audio CODEC ADC LR Clock AUD_ADCDAT PIN_B6 Audio CODEC ADC Data AUD_DACLRCK PIN_A5 Audio CODEC DAC LR Clock AUD_DACDAT PIN_B5 Audio CODEC DAC Data AUD_XCK PIN_B4 Audio CODEC Chip Clock AUD_BCLK PIN_A4 Audio CODEC Bit Stream Clock 12C_SCLK PIN_A3 120 Data I2C SDAT PIN B3 12C Clock Table 4 9 Audio CODEC pin assignments 4 8 RS 232 Serial Port The DEI board uses the MAX232 transceiver chip and a 9 pin D SUB connector for RS 232 communications For detailed information on how to use the transceiver refer to the datasheet which is available on the manufacturer s web site and from the Datasheet folder on the DE1 System CD ROM Figure 4 16 shows the related schematics and Table 4 10 lists the Cyclone II FPGA pin assignments n Figure 4 16 MAX232 RS 232 chip schematic UART RXD PIN F14 UART Receiver UART TXD PIN G12 UART Transmitter Table 4 10 RS 232 pin assignments User Manual JAN DTE 4 49 PS 2 Serial Port The DEI board includes a standard PS 2 interface and a connector for a PS 2 keyboard or mouse Figure 4 17 shows the schematic of the PS 2 circuit Instructions for using a PS 2 mouse or keyboard can be found by performing an ap
5. methods the DEI board is connected to a host computer via a USB cable Using this connection the board will be identified by the host computer as an Altera USB Blaster device The process for installing on the host computer the necessary software device driver that communicates with the USB Blaster is described in the tutorial Getting Started with Altera s DEI Board This tutorial is available on the DE1 System CD ROM and from the Altera DE1 web pages 24 PE SYN DEI User Manual Configuring the FPGA in JTAG Mode Figure 4 1 illustrates the JTAG configuration setup To download a configuration bit stream into the Cyclone II FPGA perform the following steps Ensure that power is applied to the DE1 board Connect the supplied USB cable to the USB Blaster port on the DEI board see Figure 2 1 Configure the JTAG programming circuit by setting the RUN PROG switch on the left side of the board to the RUN position The FPGA can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the sof filename extension USB Blaster Circuit PROG RUN Quartus JTAG Config Si Programmer JTAG UART Auto Power on Config JTAG Config Port EPCS16 Serial Configuration Device Figure 4 1 The JTAG configuration scheme Configuring the EPCS4 in AS Mode Figure 4 2 illustrates the AS configuration set up To download a configuration bit stream into the EP
6. 3 DEI Control Panel The DEI board comes with a Control Panel facility that allows a user to access various components on the board through a USB connection from a host computer This chapter first presents some basic functions of the Control Panel then describes its structure in block diagram form and finally describes its capabilities 3 1 Control Panel Setup To run the Control Panel application it is first necessary to configure a corresponding circuit in the Cyclone II FPGA This is done by downloading the configuration file USB API sof into the FPGA The downloading procedure is described in Section 4 1 In addition to the USB APlI sof file it is necessary to execute on the host computer the program DEI control panel exe Both of these files are available on the DE1 System CD ROM that accompanies the DEI board in the directory DE control panel Of course these files may already have been installed to some other location on your computer system To activate the Control Panel perform the following steps 1 Connect the supplied USB cable to the USB Blaster port connect the 9V power supply and turn the power switch ON Set the RUN PROG switch to the RUN position Start the Quartus II software Select Tools Programmer to reach the window in Figure 3 1 Click on Add File and in the pop up window that appears select the USB API sof file Next click on the Program Configure box which results in the image displaye
7. CD ROM and it is also available on the Altera DE1 web pages The user is encouraged to read the tutorial first and to treat the information below as a short reference The DEI board contains a serial EEPROM chip that stores configuration data for the Cyclone II FPGA This configuration data is automatically loaded from the EEPROM chip into the FPGA each time power is applied to the board Using the Quartus II software it is possible to reprogram the FPGA at any time and it is also possible to change the non volatile data that is stored in the serial EEPROM chip Both types of programming methods are described below 1 JTAG programming In this method of programming named after the IEEE standards Joint Test Action Group the configuration bit stream is downloaded directly into the Cyclone II FPGA The FPGA will retain this configuration as long as power is applied to the board the configuration is lost when the power is turned off 2 AS programming In this method called Active Serial programming the configuration bit stream is downloaded into the Altera EPCS16 seria EEPROM chip It provides non volatile storage of the bit stream so that the information is retained even when the power supply to the DEI board is turned off When the board s power is turned on the configuration data in the EPCS16 device is automatically loaded into the Cyclone II FPGA The sections below describe the steps used to perform both JTAG and AS programming For both
8. Data 4 FL DQ 5 PIN AA18 FLASH Data 5 FL DQ 6 PIN AB19 FLASH Data 6 FL DQ 7 PIN AA19 FLASH Data 7 FL OE N PIN AA15 FLASH Output Enable FL RST PIN W14 FLASH Reset FL WE N PIN Y14 FLASH Write Enable Table 4 18 Flash pin assignments 45 AYA DEI User Manual Chapter 5 Examples of Advanced Demonstrations This chapter provides a number of examples of advanced circuits implemented on the DEI board These circuits provide demonstrations of the major features on the board such as its audio and video capabilities For each demonstration the Cyclone II FPGA or EPCS4 serial EEPROM configuration file is provided as well as the full source code in Verilog HDL code All of the associated files can be found in the DEI demonstrations folder from the DE1 System CD ROM For each of demonstrations described in the following sections we give the name of the project directory for its files which are subdirectories of the demonstrations folder Installing the Demonstrations To install the demonstrations on your computer perform the following 1 Copy the directory demonstrations into a local directory of your choice It is important to ensure that the path to your local directory contains no spaces otherwise the Nios II software will not work 2 In the directory demonstrations go to the subdirectory fixpaths 3 Run the DEI fixpaths bat batch file In the dialog box that pops up select t
9. Using the DEI Board 24 4 1 Configuring the Cyclone II Betta pe Pa 24 42 LEDS aiite aqa 26 4 3 Using th 7 s ement DISP 38y8 30 D EEG dini ete 31 4 5 Using the Expansion Header esa t FII REA Oe V REN Sa MEE DER Ge RET e diidinan 32 46 Uss VGA E O A 36 4 7 Using the 24 bit A udio CODEGC pa ua Cenni 38 A R R a 39 4 9 PS 2 Serial Poft EEE 40 Using SDRAM SRAIMY Plas 40 Chapter 5 Examples of Advanced Demonstrations 46 5 1 DEL Factory Configuration uu n a Ser e rod bese ecd iun Desa 46 52 Music Synthesizer Demonstration 47 53 de Karaoke Machine RC 50 54 SD Card Music Player a a 52 SYN DEI User Manual Chapter 1 DEI Package The DEI package contains all components needed to use the DEI board in conjunction with a comp
10. files via its CD quality audio DAC circuits We use the Nios II processor to read the music data stored in the SD Card and use the Wolfson WM8731 audio CODEC to play the music The audio CODEC is configured in the slave mode where external circuitry must provide the ADC DAC serial bit clock and left right channel clock LACK to the audio CODEC As shown in Figure 5 11 we provide an Audio DAC Controller to achieve the clock generation and the data flow control The Audio DAC Controller is integrated into the Avalon bus architecture so that the Nios II processor can control the application During operation the Nios II processor will check if the FIFO memory of the Audio DAC Controller becomes full If the FIFO is not full the processor will read a 512 byte sector and send the data to the FIFO of the Audio DAC Controller via the Avalon bus The Audio DAC Controller uses a 48 kHz sample rate to send the data and clock signals to the audio CODEC The design also mixes the data from microphone in with line in for the Karaoke style effects I2C Audio Configuration Line out Nios 11 Audio DAC CPU Controller Linean Bypass ADC to DAC Figure 5 11 Block diagram of the SD music player demonstration 52 N DTE YA DE1 User Manual Demonstration Setup File Locations and Instructions Project directory DE SD Card Audio Bit stream used SD Card Audio sof or pof Nios II Workspace SD Card Audio Form
11. on the DE1 System CD ROM and from the Altera DEI web pages Connect the 7 5V adapter to the DEI board Connect a VGA monitor to the VGA port on the DEI board Connect your headset to the Line out audio port on the DEI board Turn the RUN PROG switch on the left edge of the DEI board to RUN position the PROG position is used only for the AS Mode programming 6 Turn the power on by pressing the ON OFF switch on the DEI board cto Tm SYN DEI User Manual At this point you should observe the following e All user LEDs are flashing e 7 segment displays are cycling through the numbers 0 to F e The VGA monitor displays the image shown in Figure 2 3 and Figure2 4 according to SWO e Set the toggle switch SW9 to the DOWN position you should hear a 1 kHz sound e Set the toggle switch SW9 to the UP position and connect the output of an audio player to the Line in connector on the DEI board on your headset you should hear the music played from the audio player MP3 PC iPod or the like e You can also connect a microphone to the Microphone in connector on the DEI board your voice will be mixed with the music played from the audio player DE1 Board Cyclone Il FPGA Starter Board www terasic com Figure 2 3 The default VGA output pattern when SWO is set to DOWN position Figure 2 4 The default VGA output pattern when SWO is set to UP position AND YAN DEI User Manual Chapter
12. raw data that can be downloaded directly into the SRAM on the DEI board and displayed on the VGA monitor using the VGA controller IP described in the USB project The mgConv tool will also generate Raw Data BW dat and its corresponding TXT format for the black and white version of the image the threshold for judging black or white level is defined in the BW Threshold 8 Terasic Image Converter BW Threshold 128 Band of RGB Red Processed Line File Name Raw_Data Open Bitmap i Save Raw Data Figure 3 13 The image converter window 22 User Manual Image Source R G B Band B amp W Output Result Filter Threshold 640x480 Filter Color Picture R G B N A Raw_Data_Gray Color Picture R G B BW Threshold Raw Data BW optional Raw Data BW txt Grayscale N A N A Raw Data Gray Picture Grayscale N A BW Threshold Raw Data BW Picture Raw Data BW txt Note Raw Data BW txt is used to fill in the MIF Intel Hex format for SRAM 23 AND YAN DEI User Manual Chapter 4 Using the DEI Board This chapter gives instructions for using the DEI board and describes each of its I O devices 4 1 Configuring the Cyclone II FPGA The procedure for downloading a circuit from a host computer to the DEI board is described in the tutorial Quartus II Introduction This tutorial is found in tutorials folder on the DEI System
13. 1 PIN_U21 LED Green 1 LEDG 2 PIN V22 LED Green 2 LEDG 3 PIN V21 LED Green 3 LEDG 4 PIN W22 LED Green 4 LEDG 5 PIN W21 LED Green 5 LEDG 6 PIN Y22 LED Green 6 LEDG 7 Y21 LED Green 7 Table 4 3 Pin assignments for the LEDs 29 NO SYAN DEI User Manual 4 3 Using the 7 segment Displays The DEI Board has four 7 segment displays These displays are arranged into a group of four with the intent of displaying numbers of various sizes As indicated in the schematic in Figure 4 6 the seven segments are connected to pins on the Cyclone II FPGA Applying a low logic level to a segment causes it to light up and applying a high logic level turns it off Each segment in a display is identified by an index from 0 to 6 with the positions given in Figure 4 7 Note that the dot in each display is unconnected and cannot be used Table 4 4 shows the assignments of FPGA pins to the 7 segment displays RN7 HEXO DO 2 AO HEXO Di B0 HEXO D2 5 co 7 g D0 HEX1 330 RN8 A1 HEXO D4 EO B1 m e HEXO D5 Fo Vvcc33 C1 BER VCC33 HEXO_DS 5 50 DI o 1 DO 7 g AT ap 330 E1 2 Fig HEX D1 2 8 Fi HEX1 D2 C1 G1 HEX D3 5 D1 HEX1 D4 Et x L 330 7Segment Display 7Segment Display RN10 HEX1 D5 2 Fi HEX1 DS G1 HEX2 DO 5 2 HEX2 DI 7 8 52 HEX3 D3 2 D3 HEX3 D4 E3 HEX3 D5 5 F3 HEX3 06 G3 Figure 4 7 Position
14. 1 Control Panel is illustrated in Figure 3 3 The IP that performs the control functions is implemented in the FPGA device It communicates with the Control Panel window which is active on the host computer via the USB Blaster link The graphical interface is used to 11 YA DEI User Manual issue commands to the control circuitry The provided IP handles all requests and performs data transfers between the computer and the DEI board DEL DE 1 Control Panel Opes Help Abou SRAM VGA TOOLS Ps2atED FLASH SDRAM LED amp 7 SEG HEX3 HEX2 HEX1 b fo b 1 06 1 05 LED4 LEDS LED2 LED1 LEDOT 1 9 1 08 LEDZ LEDS LEDS LED4 LEDS 1 02 LEDI LEDO USB Blaster PS2 Keyboard Figure 3 3 The DEI Control Panel concept The DEI Control Panel can be used to change the values displayed on 7 segment displays light up LEDs talk to the PS 2 keyboard read write the SRAM Flash Memory and SDRAM load an image pattern to display as VGA output load music to the memory and play music via the audio DAC The feature of reading writing a byte or an entire file from to the Flash Memory allows the user to develop multimedia applications Flash Audio Player Flash Picture Viewer without worrying about how to build a Flash Memory Programmer 3 2 Controlling the LEDs and 7 Segment Displays A simple function of the
15. ASH tab in the Control Panel DE1 Control Panel Open Help About SRAM PS2 amp LED FLASH Random Access Address 0 wDATA 00 DATA 00 Ji Write Read Sequential Write Address g Length p File Length Write a File to FLASH Sequential Read Address 0 Length 0 Entire Flash Load FLASH Content to a File Figure 3 6 Flash memory control window A byte of data can be written into a random location on the Flash chip as follows 1 Click on the Chip Erase button The button and the window frame title will prompt you to wait until the operation is finished which takes about 20 seconds 2 Enter the desired address into the Address box and the data byte into the wDATA box Then click on the Write button 15 AND SAN DEI User Manual To read a byte of data from a random location enter the address of the location and click on the Read button The rDATA box will display the data read back from the address specified The Sequential Write function is used to load a file into the Flash chip as follows 1 Specify the starting address and the length of data in bytes to be written into the Flash memory You can click on the File Length checkbox to indicate that you want to load the entire file 2 Click on the Write a File to Flash button to activate the writing process 3 When the Control Panel responds with the standard Windows dialog box asking for the source file specify the desired file in t
16. Altera DE1 Board JA DTE RYAN DE1 Development and Education Board User Manual Version 1 1 Copyright 2006 Altera Corporation Altera DE1 Board Chapt r I DEI Package aaa aaa asasssqssassssssessssasqaassasssesasossssasssssssssssssssasssssssssasseassssssssssssssassasss 1 1 1 Package Contents usun e D 1 13 The DEI Board Assembly u in P tO 2 1 3 Getting 1 3 Chapter 2 Altera DEI Board ssaccscseesssctsssescosssencssesssssnensssenscsssunsvonsvessvenssvecevesoun cesnasunstausvenstensoassteadeense 4 2 1 Layout and Components PCR sandinn iiae E ieia 4 24 Block Diagram of th DEI Board aqasha n Rd reddi md tasas decis 6 2 3 Power up the zoo C 8 Chapter 3 DEL Control 10 3 1 Control Panel aeae e ee qupa 10 3 2 Controlling the LEDs and 7 Segment Displays eee 12 3 3 SDRAM SRAM Controller and Programmer eene 13 39 Flash Memory PEOBFOHIBIEE enero cA dom EMI Mu E 14 3 5 Overall Structure of the DET Control Panel a 16 36 TOOLS Multi Port SRAM SDRAM Flash Conttroller 18 3 7 VGA Display 2 19 Chapter 4
17. CS 16 serial EEPROM device perform the following steps Ensure that power is applied to the DEI board Connect the supplied USB cable to the USB Blaster port on the DEI board see Figure 2 1 Configure the JTAG programming circuit by setting the RUN PROG switch on the left side of the board to the PROG position The EPCS4 chip can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the pof filename extension Once the programming operation is finished set the RUN PROG switch back to the RUN position and then reset the board by turning the power switch off and back on this action causes the new configuration data in the EPCSA device to be loaded into the FPGA chip 25 AND SAN DEI User Manual USB Blaster Circuit RUN PROG Quartus Il Mode Programmer iii JTAG Config Port AS Mode Auto Power on Config EPCS16 Serial Configuration Device Figure 4 2 The AS configuration scheme In addition to its use for JTAG and AS programming the USB Blaster port on the DEI board can also be used to control some of the board s features remotely from a host computer Details that describe this method of using the USB Blaster port are given in Chapter 3 4 2 Using the LEDs and Switches The DEI board provides four pushbutton switches Each of these switches is debounced using a Schmitt Trigger circuit as indicated in Figure 4 3 The four outputs called K
18. Control Panel is to allow setting the values displayed on LEDs and 7 segment displays In the window shown in Figure 3 2 the values to be displayed by the 7 segment displays which are named HEX7 0 can be entered into the corresponding boxes and displayed by pressing the Set button Choosing the LED tab leads to the window in Figure 3 4 Here you can turn the individual LEDs on by selecting them and pressing the Set button The ability to set arbitrary values into simple display devices is not needed in typical design activities However it gives the user a simple mechanism for verifying that these devices are functioning correctly in case a malfunction is suspected Thus it can be used for troubleshooting purposes 12 DEI User Manual r LED SEG DE DE1 Control Panel Open Help About SRAM PS2 amp LED Figure 3 4 Controlling LEDs and the LCD display 3 3 SDRAM SRAM Controller and Programmer The Control Panel can be used to write read data to from the SDRAM and SRAM chips on the DEI board We will describe how the SDRAM may be accessed the same approach is used to access the SRAM Click on the SDRAM tab to reach the window in Figure 3 5 DE1 Control Panel Open Help About SRAM PS2 amp LED r Random Access Write ea Address 200 ECA r DATA 2604 r Sequential Write Address n Length o File Length Write a File to SDRAM
19. DRAM Memory Host Port User Port Async 3 lt gt User Port 2 Async 2 User Port 1 Async 1 SRAM Controller SRAM Memory OSD Memory gt VGA DAC Controller VGA DAC Host Port User Port 3 Async 3 4 User Port 2 Async 2 lt gt User Port 1 Async 1 Flash Controller Flash Memory 1 Khz Sine Wave Look up Table eo Audio DAC Controller Figure 3 7 The DE1 Control Panel block diagram Ly LCD CRT Monitor Audio DAC a Users can connect circuits of their own design to one of the User Ports of the SRAM SDRAM Flash controller Then they can download binary data into the SRAM SDRAM Flash Once the data is downloaded to the SDRAM Flash users can configure the memory controllers so that their circuits can read write the SDRAM Flash via the User Ports connected 17 AND YAN DEI User Manual 3 6 TOOLS Multi Port SRAM SDRAM Flash Controller The TOOLS page of the Control Panel GUI allows selection of the User Ports We will illustrate a typical process by implementing a Flash Music Player The music data is loaded into the Flash memory User Port 1 in the Flash Controller is used to send the music data to the Audio DAC Controller and hence to the audio output jack You can implement this application as follows 1 Erase the Flash memory as explained in Sec
20. EYO KEY3 of the Schmitt Trigger device are connected directly to the Cyclone II FPGA Each switch provides a high logic level 3 3 volts when it is not pressed and provides a low logic level 0 volts when depressed Since the pushbutton switches are debounced they are appropriate for use as clock or reset inputs in a circuit Pushbutton depressed Pushbutton released Before Debouncing Schmitt Trigger Debounced lt gt Figure 4 3 Switch debouncing There are also 10 toggle switches sliders on the DEI board These switches are not debounced and are intended for use as level sensitive data inputs to a circuit Each switch is connected directly to a pin on the Cyclone II FPGA When a switch is in the DOWN position closest to the edge of the board it provides a low logic level 0 volts to the FPGA and when the switch is in the UP position it provides a high logic level 3 3 volts 26 AN DTE SYAN DE1 User Manual There are 27 user controllable LEDs on the DEI board Eighteen red LEDs are situated above the 18 toggle switches and eight green LEDs are found above the pushbutton switches the 9 green LED is in the middle of the 7 segment displays Each LED is driven directly by a pin on the Cyclone II FPGA driving its associated pin to a high logic level turns the LED on and driving the pin low turns it off A schematic diagram that shows the pushbutton and toggle switches is given in Figure 4 4 A schemati
21. IN_N3 SDRAM Clock Enable DRAM_CLK PIN_U4 SDRAM Clock DRAM_WE_N PIN R8 SDRAM Write Enable DRAM CS N PIN T6 SDRAM Chip Select Table 4 16 SDRAM pin assignments SRAM ADDR O PIN AA3 SRAM Address 0 SRAM ADDR 1 PIN AB3 SRAM Address 1 SRAM ADDR 2 PIN AA4 SRAM Address 2 SRAM ADDR 3 PIN 4 SRAM Address 3 SRAM_ADDRI4 PIN 5 SRAM Address 4 SRAM ADDR S PIN AB10 SRAM Address 5 SRAM ADDR 6 PIN AA11 SRAM Address 6 SRAM ADDR 7 PIN AB11 SRAM Address 7 SRAM ADDR S PIN SRAM Address 8 SRAM ADDR 9 PIN W11 SRAM Address 9 SRAM ADDR 10 PIN R11 SRAM Address 10 SRAM ADDR 11 PIN T11 SRAM Address 11 SRAM ADDR 12 PIN Y10 SRAM Address 12 SRAM ADDR 13 PIN U10 SRAM Address 13 43 YA DEI User Manual SRAM ADDR 14 PIN R10 SRAM Address 14 SRAM ADDR 15 PIN T7 SRAM Address 15 SRAM ADDR 16 PIN Y6 SRAM Adaress 16 SRAM ADDR 17 PIN Y5 SRAM Address 17 SRAM DQ 0 PIN 6 SRAM Data 0 SRAM PIN SRAM Data 1 SRAM_DQ 2 PIN AA7 SRAM Data 2 SRAM DQ 3 PIN AB7 SRAM Data 3 SRAM 4 PIN 8 SRAM Datal4 SRAM DQ 5 PIN 8 SRAM Data 5 SRAM DOQ 6 PIN AA9 SRAM Data 6 SRAM DQ 7 PIN AB9 SRAM Data 7 SRAM 8 PIN Y9 SRAM Data 8 SRAM DQ 9 PIN W9 SRAM Data 9 SRAM DQ 10 PIN V9 SRAM Data 10 SRAM DQ 11 PIN U9 SRAM Data 11 SRAM DQ 12 PIN R9 SRAM Data 12
22. P1 GPIO 0 AD d E A1 IO A2 B IO A3 P IO E IO A5 P IO A7 AS IO AS GND VCC5 O75 aio 2 IO ATi 1GND A12 P IO A13 OATS D I A lt A18 1 IO ATS 10_A20 P I0 A21 IO A22 2 P IO A23 IO A24 P lo A25 VCC33 O q 8 s 15 z 55 IO A30 IO A31 A32 g P IO A33 A34 IO A35 IO B0 4 N IO B1 IO B2 83 19 85 D 19 37 9 E GND VCC5 O75 B1B 9 E Bii 9ND p XE B18 M IO B17 C D 10 818 P 10 819 10 820 9 4 19 821 ES dE D GND sO ae j IO 827 Q D IO B32 P IO 833 34 835 Figure 4 10 Schematic diagram of the expansion headers GPIO O 0 PIN A13 GPIO Connection O 0 33 User Manual GPIO_0 1 PIN_B13 GPIO Connection 0 1 GPIO O 2 PIN A14 GPIO Connection O 2 GPIO_0 3 PIN_B14 GPIO Connection 0 3 GPIO O 4 PIN A15 GPIO Connection O 4 GPIO O 5 PIN B15 GPIO Connection O 5 GPIO O 6 PIN A16 GPIO Connection O 6 GPIO O 7 PIN B16 GPIO Connection O 7 GPIO O 8 PIN A17 GPIO Connection O 8 GPIO O 9 PIN B17 GPIO Connection O 9 GPIO 0O 10 PIN A18 GPIO Connection 0 10 GPIO_0 11 PIN_B18 GPIO Connection 0 11 GPIO_0 12 PIN_A19 GPIO Connection 0 12 GPIO O 13 PIN_B19 GPIO Connection 0 13 GPIO_0 14 PIN_A20 GPIO Co
23. RAM A9 SDRAM 1Mx16x4 TSOP 54 GND DRAM D15 GND DRAM D14 DRAM D13 R_vCC33 DRAM_D12 DRAM_D11 GND DRAM D10 DRAM D9 R_VCC33 DRAM D8 GND DRAM UDOM DRAM CLK DRAM CKE DRAM A11 DRAM A9 DRAM A8 DRAM A7 DRAM A6 DRAM A5 DRAM A4 GND Figure 4 23 SDRAM schematic U7 15611 25616 TSOP 44 Figure 4 24 SRAM schematic 41 SRAM A17 SRAM A16 SRAM A15 SRAM OE SRAM UB SRAM LB SRAM D15 SRAM D14 SRAM D13 SRAM D12 GND R_VCC33 SRAM_D11 SRAM_D10 SRAM D9 SRAM D8 SRAM A14 SRAM A13 SRAM A12 SRAM A11 SRAM A10 DE 1 User Manual U9 FLASH A16 1 FLASH A15 gt 15 FLASH_A14 5 FLASH A13 acis FLASH A12 5 FLASH AT amp H FLASH_A10 z FLASH_A9 gl FLASH_A20 8 FLASH A21 40 FLASH_WE 11 WE FLASH RESET 12 12 ne tN FLASH A19 4g RYIBY FLASH A18 17 MS FLASH_AS FLASH_A7 19 7 FLASH A6 20 FLASH_A5 gt FLASH_A4 22 28 FLASH A3 2315 FLASH A2 al S29AL032DTFN FLASH_OE TSOP 48 ate 48 FLASH_A17 pie oND A FLASH AQ OND on Ld FLASH D7 42 lt FLASH D6 rr X FLASH D5 co a8 lt FLASH D4 M Lar F VCC33 p 35 lt FLASH_D3 p FLASH_D2 MO FLASH D1 i 29 FLASH_D0 Q0 28 FLASH_OE 2L n isND 26 FLASH_CE 26 AA OF_vCC33 AQ R24 4 7K Figure 4 25 Flash sche
24. RAM page of the Control Panel and load the file picture dat into SRAM Select the TOOLS page and choose Asynchronous 1 for the SRAM multiplexer port as shown in Figure 3 10 Click on the Configure button to activate the multi port setup DE1 Control Panel Open Help About PS2 amp LED SRAM SDRAM Multiplexer Host USB Port z FLASH Multiplexer Host USB Port Y SRAM Multiplexer Configure Board Test Figure 3 10 Use the Asynchronous Port 1 to access the image data in the SRAM e The FPGA is now configured as indicated in Figure 3 11 Select the VGA page and deselect the checkbox Default Image e The VGA monitor should display the picture dat image from the SRAM as depicted in Figure 3 12 You can turn off the cursor by deselecting the Cursor Enable checkbox 20 NBIS YA DEI User Manual JTAG 7 SEG LUT 7 SEG USB Blaster _JTAG Link f lt gt Serial to Parallel Hardware i onversion LED PS 2 Keyboard USB bink Command Controller y Host Port User Port 3 Async 3 4 SDRAM SDRAM User Port2 Async2 lt X Controller Memory User Port 1 Async 1 4 Host Port User Port 3 Async 3 SRAM SRAM I Board User Port 2 Async 2 4 gt Controller Memory Use
25. SRAM DQ 13 PIN W8 SRAM Data 13 SRAM DQ 14 PIN V8 SRAM Data 14 SRAM DQ 15 PIN U8 SRAM Data 15 SRAM WE N PIN AA10 SRAM Write Enable SRAM OE N PIN T8 SRAM Output Enable SRAM UB N PIN W7 SRAM High byte Data Mask SRAM LB N PIN Y7 SRAM Low byte Data Mask SRAM CE N PIN AB5 SRAM Chip Enable Table 4 17 SRAM pin assignments FL ADDR 0 PIN AB20 FLASH Address 0 FL ADDR 1 PIN AA14 FLASH Address 1 FL ADDR 2 PIN Y16 FLASH Address 2 FL ADDR 3 PIN R15 FLASH Address 3 FL ADDR 4 PIN T15 FLASH Address 4 FL ADDR 5 PIN U15 FLASH Address 5 FL ADDR 6 PIN V15 FLASH Address 6 FL ADDR 7 PIN W15 FLASH Address 7 44 User Manual FL_ADDRI8 PIN_R14 FLASH Address 8 FL ADDR 9 PIN Y13 FLASH Address 9 FL ADDR 10 PIN R12 FLASH Address 1 0 FL ADDR 11 PIN T12 FLASH Address 11 FL ADDR 12 PIN AB14 FLASH Address 12 FL ADDR 13 PIN AA13 FLASH Address 13 FL ADDR 14 PIN 3 FLASH Address 14 FL ADDR 15 PIN AA12 FLASH Address 15 FL ADDR 16 PIN AB12 FLASH Address 16 FL ADDR 17 PIN AA20 FLASH Address 17 FL ADDR 18 PIN U14 FLASH Address 18 FL ADDR 19 PIN V14 FLASH Address 19 FL ADDR 20 PIN U13 FLASH Address 20 FL ADDR 21 PIN R13 FLASH Address 21 FL DQ 0 PIN AB16 FLASH Data 0 FL DQ 1 PIN AA16 FLASH Data 1 FL DQ 2 PIN AB17 FLASH Data 2 FL DQ 3 PIN AA17 FLASH Data 3 FL 4 PIN AB18 FLASH
26. aded consecutively into the memory The Sequential Read function is used to read the contents of the SDRAM and place them into a file as follows 1 Specify the starting address in the Address box 2 Specify the number of bytes to be copied into the file in the Length box If the entire contents of the SDRAM are to be copied which involves all 8 Mbytes then place a checkmark in the Entire SDRAM box 3 Press Load SDRAM Content to a File button 4 When the Control Panel responds with the standard Windows dialog box asking for the destination file specify the desired file in the usual manner 3 4 Flash Memory Programmer The Control Panel can be used to write read data to from the Flash memory chip on board It can be used to e Erase the entire Flash memory Write one byte to the memory 14 AND YAN DEI User Manual e Read one byte from the memory e Write a binary file to the memory e Load the contents of the Flash memory into a file Note the following characteristics of the Flash memory e The Flash memory chip is organized as 4 M x 8 bits e You must erase the entire Flash memory before you can write into it Be aware that the number of times a Flash memory can be erased is limited e The time required to erase the entire Flash memory is about 20 seconds Do not close the DEI Control Panel in the middle of the operation To open the Flash memory control window shown in Figure 3 6 select the FL
27. and index of each segment in a 7 segment display 30 DEI User Manual 0 PIN_J2 Seven Segment Digit 0 0 HEXO 1 PIN J1 Seven Segment Digit 0 1 HEXO 2 PIN H2 Seven Segment Digit O 2 HEXO 3 PIN H1 Seven Segment Digit 0 3 HEXO 4 PIN F2 Seven Segment Digit O 4 HEXO 5 PIN F1 Seven Segment Digit O 5 HEXO 6 PIN E2 Seven Segment Digit O 6 HEX1 0 PIN_E1 Seven Segment Digit 1 0 HEX1 1 PIN H6 Seven Segment Digit 1 1 HEX1 2 PIN H5 Seven Segment Digit 1 2 HEX1 3 PIN H4 Seven Segment Digit 1 3 HEX1 4 PIN G3 Seven Segment Digit 1 4 HEX1 5 PIN D2 Seven Segment Digit 1 5 HEX1 6 PIN D1 Seven Segment Digit 1 6 2 0 PIN G5 Seven Segment Digit 2 0 2 1 PIN G6 Seven Segment Digit 2 1 HEX2 2 PIN C2 Seven Segment Digit 2 2 2 3 PIN C1 Seven Segment Digit 2 3 2 4 PIN Seven Segment Digit 2 4 2 5 PIN E4 Seven Segment Digit 2 5 2 6 PIN 03 Seven Segment Digit 2 6 HEX3 0 PIN_F4 Seven Segment Digit 3 0 HEX3 1 PIN_D5 Seven Segment Digit 3 1 HEX3 2 PIN_D6 Seven Segment Digit 3 2 HEX3 3 PIN_J4 Seven Segment Digit 3 3 HEX3 4 PIN_L8 Seven Segment Digit 3 4 HEX3 5 PIN_F3 Seven Segment Digit 3 5 HEX3 6 PIN_D4 Seven Segment Digit 3 6 Table 4 4 Pin assignments for the 7 segment displays 4 4 Clock Inputs The DEI board includes three oscillators that produce 27 MHz 24Mhz an
28. at your SD card into FAT16 format To play a music file with this demonstration the file must use the 48 KHz sample rate WAV format Copy one or more such WAV files onto the FAT16 formatted SD Card Due to a limitation in the software used for this demonstration it is necessary to reformat the whole SD Card if any WAV file that has been copied onto the card needs to be later removed from the SD Card Load the bit stream into the FPGA Run the Nios II IDE under the workspace SD Card Audio Connect a headset or speaker to the DEI board and you should be able to hear the music played from the SD Card Figure 5 12 illustrates the setup for this demonstration Speaker SD Card with Music File WAV Audio DAC Controller NIOSII SD Driver Figure 5 12 The setup for the SD music player demonstration 53 AYA DEI User Manual Copyright 2005 Altera Corporation All rights reserved Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending applications mask work rights and copyrights Altera warrants performanc
29. c diagram that shows the LED circuitry appears in Figure 4 5 A list of the pin names on the Cyclone II FPGA that are connected to the toggle switches is given in Table 4 1 Similarly the pins used to connect to the pushbutton switches and LEDs are displayed in Tables 4 2 and 4 3 respectively RN21 EH 100K u5 GND 0 j 20 oVCC33 RN22 KEYINO 11 2 4 KEYO T Pi I KEYINi a 45 B5 12 Fi KEY1 1 KEYINJ B KEY2 1 KEYIN3 6 ne Bs 14 7 KEY3 X 3 A4 15 KEYO KEY1 KEY2 KEY3 16 1 4 1 qp 1 4 4 x 37 x 120 3 24053 XJA 82 PBSW PBSW PBSW PBSW DIR G GND ka GND vcCa3 GND 74HC245 TSSOP 20 swo SW1 sw2 sw3 sw4 SW5 SW6 Sw7 GND 5 GND 5 GND 5 GND 5 GND 5 GND Ls GND 5 GND 1 VCC33 1 VCC33 VCC33 VCC33 1 VCC33 1 VCC33 1 VCC33 21 veca SW 2 SW1 2 SW2 2 SW3 2 SW4 2 SW5 2 SW6 2 SW GND 3 GND 3 GND 3 GND 3 GND 3 GND 3 GND 3 GND GND 4 GND 4 GND 4 GND 4 GND GND 4 GND 4 GND DPDTSW DPDTSW DPDT Sw DPDT Sw DPDT Sw DPDT Sw DPDT Sw DPDT Sw swe swg 5 GND 5 GND veca a veca 2 SW8 Sw9 3 GND 3 GND 4 GND 4 GND DPDTSw DPDTSW lt p Figure 4 4 Schematic diagram of the pushbutton and toggle switche
30. ction 1 10 GPIO 1 11 PIN D14 GPIO Connection 1 11 GPIO 1 12 PIN D15 GPIO Connection 1 12 GPIO 1 13 PIN D16 GPIO Connection 1 13 GPIO 1 14 PIN C17 GPIO Connection 1 14 GPIO 1 15 PIN C18 GPIO Connection 1 15 GPIO 1 16 PIN C19 GPIO Connection 1 16 GPIO 1 17 PIN C20 GPIO Connection 1 17 GPIO 1 18 PIN D19 GPIO Connection 1 18 GPIO 1 19 PIN D20 GPIO Connection 1 19 GPIO 1 20 PIN E20 GPIO Connection 1 20 GPIO 1 21 PIN F20 GPIO Connection 1 21 GPIO 1 22 PIN E19 GPIO Connection 1 22 GPIO 1 23 PIN E18 GPIO Connection 1 23 GPIO 1 24 PIN G20 GPIO Connection 1 24 GPIO 1 25 PIN G18 GPIO Connection 1 25 GPIO 1 26 PIN G17 GPIO Connection 1 26 GPIO 1 27 PIN H17 GPIO Connection 1 27 GPIO 1 28 PIN J15 GPIO Connection 1 28 GPIO 1 29 PIN H18 GPIO Connection 1 29 GPIO 1 30 PIN N22 GPIO Connection 1 30 GPIO 1 81 PIN N21 GPIO Connection 1 31 GPIO 1 32 PIN P15 GPIO Connection 1 32 GPIO 1 33 PIN N15 GPIO Connection 1 33 GPIO 1 34 PIN P17 GPIO Connection 1 34 GPIO 1 35 PIN P18 GPIO Connection 1 35 Table 4 7 Pin assignments for the expansion headers 35 N YA DE1 User Manual 4 6 Using VGA The DEI board includes a 16 pin D SUB connector for VGA output The VGA synchronization signals are provided directly from the Cyclone II FPGA and a 4 bit DAC using resistor network is used to produce the analog data signals red green and blue The associated schematic is given in Figure 4 11 and can supp
31. d 50 MHz clock signals The board also includes an SMA connector which can be used to connect an external clock source to the board The schematic of the clock circuitry is shown in Figure 4 8 and the associated pin assignments appear in Table 4 5 31 User Manual 50MHZ EXT CLOCK VCC23 EXT CLOCK 0 10 0 10 L GND GND GND GND J5 GND Figure 4 8 Schematic diagram of the clock circuit CLOCK 27 D12 PIN E12 27 MHz clock input CLOCK 50 PIN L1 50 MHz clock input CLOCK 24 PIN A12 PIN B12 24 MHz clock input from USB Blaster EXT CLOCK PIN M21 External SMA clock input Table 4 5 Pin assignments for the clock inputs 4 5 Using the Expansion Header The DEI Board provides two 40 pin expansion headers Each header connects directly to 36 pins on the Cyclone II FPGA and also provides DC 5V VCC5 DC 3 3V VCC33 and two GND pins Figure 4 10 shows the related schematics Each pin on the expansion headers is connected to a resistor that provide protection from high and low voltages The figure shows the protection circuitry for only four of the pins on each header but this circuitry is included for all 72 data pins Table 4 7 gives the pin assignments 32 AND YAN DEI User Manual GFIO B24 GPIO_ 825 826 IO A24 B28 B28 lO A26 GPIO B27 RN29 47 RN30 47 J
32. d in the figure Now click Start to download the configuration file into the FPGA 5 Start the executable control panel exe on the host computer The Control Panel user interface shown in Figure 3 2 will appear 6 Open the USB port by clicking Open gt Open USB Port 0 The DEI Control Panel application will list all the USB ports that connect to DEI boards The DEI Control Panel can control up to 4 DEI boards using the USB links The Control Panel will occupy the USB port until you close that port you cannot use Quartus II to download a configuration file into the FPGA until you close the USB port 10 JAN DTE 4 DE1 User Manual 7 The Control Panel is now ready for use experiment by setting the value of some 7 segment display and observing the result on the DE1 board Chain1 cdf Hardware Setup i USB Blaster USB 0 ph Start i Stop n Auto Detect X Delete 2 Add File lig Change File agb Save File Add Device T ir Poor D DE2 system DE2 control panel DE2 USB API sot EP2C35F672 Figure 3 1 Quartus II Programmer window DEI DE1 Control Panel Open Help About r LED SEG HEX3 HEX 2 HEX 1 HEX 0 Set EEDEN WERSI MERSI MEDIS WE J HEDSU PS 2 Keyboard Clear Figure 3 2 The DEI Control Panel CER ET The concept of the DE
33. dresses where you can get help if you encounter problems Getting Help Altera Corporation 101 Innovation Drive San Jose California 95134 USA Email university altera com Terasic Technologies No 356 Sec 1 Fusing E Rd Jhubei City HsinChu County Taiwan 302 Email support terasic com Web www del terasic com SYAN DEI User Manual Chapter 2 Altera DE1 Board This chapter presents the features and design characteristics of the DEI board 2 1 Layout and Components A photograph of the DEI board is shown in Figure 2 1 It depicts the layout of the board and indicates the location of the connectors and key components USB VGA Blaster Mic Line Line Video nm Port in n Out Port ort 7 5V DC Power Supply Connector t t t d EMEN B iunc uM 24 bit Audio CODEC lt gt PS 2 Port Power ON OFF Switch 27Mhz Oscillator 50Mhz Oscillator 24Mhz Oscillator Altera USB Blaster Controller chipset Expansion Header 2 JP2 with Resister Protection Expansion Header 1 1 with Resister Protection Altera ae Ime Altera90nm Cyclone onfiguration Device U z RUN PROG Switch MM FPGAwith20KLEs forJTAG AS Modes 88 S ss HE SD Card Socket M oav o 588 B Refs t TC TC TCU By ni if ust n RMIZ RNS En is S OW T SEG Display Module
34. e of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to im writing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services This document is being provided on an as is basis and as an accommodation and therefore all warranties representations or guarantees of any kind whether express implied or statutory including without limitation warranties of merchantability non infringement or fitness for a particular purpose are specifically disclaimed 54
35. e used to play audio from an appropriate sound source The Verilog source code for this demonstration is provided in Default folder which also includes the necessary files for the corresponding Quartus II project The top level Verilog file called Default v can be used as a template for other projects because it defines ports that correspond to all of the user accessible pins on the Cyclone II FPGA 5 2 Music Synthesizer Demonstration This demonstration shows how to implement a Multi tone Electronic Keyboard using DE1 board with a PS 2 Keyboard and a speaker Figure 5 1 shows the setup of the demonstration PS 2 Keyboard is used as the piano keyboard for input The Cyclone II FPGA on the DEI board serves as the Music Synthesizer SOC to generate music and tones The VGA connected to the DEI board is used to show which key is pressed during the playing of the music Figure 5 2 shows the block diagram of the design of the Music Synthesizer There are four major blocks in the circuit DEMO SOUND PS2 KEYBOARD STAFF and TONE GENERATOR The DEMO SOUND block stores a demo sound for user to play PS2 KEYBOARD handles the users input from PS 2 keyboard The STAFF block draws the corresponding keyboard diagram on VGA monitor when key s are pressed The TONE GENERATOR is the core of music synthesizer SOC User can switch the music source either from 52 KEYBOAD or the DEMO SOUND block using SW9 To repeat the demo sound user
36. he directory DEI demonstrations in your local directory where you copied the files to Click OK 4 When fixpaths is finished press any key to complete the process 51 DEI Factory Configuration The DEI board is shipped from the factory with a default configuration that demonstrates some of the basic features of the board The setup required for this demonstration and the locations of its files are shown below Demonstration Setup File Locations and Instructions Project directory DEI Default Bit stream used DEI Default sof or Default pof 46 AND YAN DEI User Manual e Power on the DE1 board with the USB cable connected to the USB Blaster port If necessary that is if the default factory configuration of the DEI board is not currently stored in EPCS4 device download the bit stream to the board by using either JTAG or AS programming e You should now be able to observe that the 7 segment displays are displaying a sequence of characters and the red and green LEDs are flashing Optionally connect a VGA display to the VGA D SUB connector When connected the VGA display should show a pattern of colors Optionally connect a powered speaker to the stereo audio out jack e Place toggle switch SW9 in the UP position to hear a 1 kHz humming sound from the audio out port Alternatively if switch SW9 is DOWN the microphone in port can be connected to a microphone to hear voice sounds or the line in port can b
37. he usual manner The Sequential Read function is used to read the data stored in the Flash memory and write this data into a file as follows 1 Specify the starting address and the length of data in bytes to be read from the Flash memory You can click on the Entire Flash checkbox to indicate that you want to copy the entire contents of the Flash memory into a specified file 2 Click on the Load Flash Content to a File button to activate the reading process 3 When the Control Panel responds with the standard Windows dialog box asking for the destination file specify the desired file in the usual manner 3 5 Overall Structure of the DE1 Control Panel The DEI Control Panel facility communicates with a circuit that is instantiated in the Cyclone II FPGA This circuit is specified in Verilog code which makes it possible for a knowledgeable user to change the functionality of the Control Panel The code is located inside the DE demonstrations directory on the DE1 System CD ROM To run the Control Panel the user must first set it up as explained in Section 3 1 Figure 3 7 depicts the structure of the Control Panel Each input output device is controlled by a controller instantiated in the FPGA chip The communication with the PC is done via the USB Blaster link A Command Controller circuit interprets the commands received from the PC and performs the appropriate actions The SDRAM SRAM and Flash Memory controllers have three user selectab
38. l e Sampling frequency 8 to 96 KHz e Applications for MP3 players and recorders PDAs smart phones voice recorders etc VGA output e Uses 4 bit resistor network DAC e With 15 pin high density D sub connector e Supports up to 640x480 at 60 Hz refresh rate e Can be used with the Cyclone II FPGA to implement a high performance TV Encoder Serial ports e One RS 222 port e One PS 2 port e DB 9 serial connector for the RS 232 port e PS 2connector for connecting a PS2 mouse or keyboard to the DEI board Two 40 pin expansion headers e 72 Cyclone II I O pins as well as 8 power and ground lines are brought out to two 40 pin expansion connectors e 40 pin header is designed to accept a standard 40 pin ribbon cable used for IDE hard drives e Resistor protection is provided 2 3 Power up the DE1 Board The DEI board comes with a preloaded configuration bit stream to demonstrate some features of the board This bit stream also allows users to see quickly if the board is working properly To power up the board perform the following steps 1 Connect the provided USB cable from the host computer to the USB Blaster connector on the DEI board For communication between the host and the DEI board it is necessary to install the Altera USB Blaster driver software If this driver is not already installed on the host computer it can be installed as explained in the tutorial Getting Started with Altera s DEI Board This tutorial is available
39. le asynchronous ports in addition to the Host port that provides a link with the Command Controller The connection between the VGA DAC Controller and the FPGA memory allows displaying of the default image shown on the left side of the figure which is stored in an M4K block in the Cyclone II chip The connection between the Audio DAC Controller and a lookup table in the FPGA is used to produce a test audio signal of 1 KHz 16 JAN DTE RYA DE1 User Manual To let users implement and test their IP cores written in Verilog without requiring them to implement complex API Host control software and memory SRAM SDRAM Flash controllers we provide an integrated control environment consisting of a software controller in C a USB command controller and a multi port SRAM SDRAM Flash controller USB Blaster JTAG Link Hardware 4 USB Link About Ps2a7stG FLASH SDRAM SRAM DE1 Board Cursor X 0 ERR Cursor Y 0 ter F Defautimage Cursor Enable PC Side DE1 Control Panel JTAG 7 SEG LUT 7 SEG Serial to Parallel Conversion Terasic Command Controller T PS 2 Keyboard Controller LED PS 2 Keyboard Host Port User Port 3 Async 3 lt gt User Port 2 Async 2 lt User Port 1 Async 1 4 9 SDRAM Controller S
40. lled the front porch d where the RGB signals must again be off before the next hsync pulse can occur The timing of the vertical synchronization vsync is the same as shown in Figure 4 12 except that a vsync pulse signifies the end of one frame and the start of the next and the data refers to the set of rows in the frame horizontal timing Figures 4 13 and 4 14 show for different resolutions the durations of time periods a b c and d for both horizontal and vertical timing The pin assignments between the Cyclone II FPGA and the VGA connector are listed in Table 4 8 An example of code that drives a VGA display is described in Sections 5 2 and 5 3 Back porch b Front porch d Display interval c DATA HSYNC E Synca Figure 4 12 VGA horizontal timing specification Configuration Resolution HxV Pixel clock Mhz VGA 60Hz 640x480 3 8 1 9 25 4 0 6 25 640 Figure 4 13 horizontal timing specification Configuration Resolution HxV a lines b lines c lines d lines VGA 60Hz 640x480 2 33 480 10 Figure 4 14 VGA vertical timing specification VGA R 0 PIN_D9 VGA Red 0 VGA R 1 PIN_C9 VGA 1 VGA R 2 PIN_A7 VGA Red 2 VGA R 3 PIN_B7 VGA Red 3 VGA_G 0 PIN_B8 VGA Green 0 VGA G 1 PIN_C10 VGA Green 1 VGA_G 2 PIN_B9 VGA Green 2 VGA_G 3 PIN A8 VGA Green 3 User Manual
41. matic ADDR O PIN W4 SDRAM Address 0 DRAM ADDR 1 W5 SDRAM Address 1 DRAM ADDR 2 PIN Y3 SDRAM Address 2 ADDR 3 PIN Y4 SDRAM Address 3 DRAM_ADDRI4 PIN_R6 SDRAM Address 4 DRAM_ADDR 5 PIN_R5 SDRAM Address 5 ADDR 6 PIN P6 SDRAM Address 6 DRAM_ADDRI7 PIN P5 SDRAM Address 7 DRAM 8 PIN P3 SDRAM Address 8 ADDR 9 SDRAM Address 9 DRAM_ADDR 10 PIN_W3 SDRAM Address 10 _ 11 PIN_N6 SDRAM Address 11 DRAM DQ 0 PIN Ut SDRAM Data 0 DRAM DQ 1 PIN U2 SDRAM Data 1 DRAM DQ 2 PIN V1 SDRAM Data 2 DRAM DQ 3 PIN V2 SDRAM Data 3 DRAM_DQ 4 PIN_W1 SDRAM Datal4 DRAM DQ 5 PIN W2 SDRAM Data 5 DRAM DQ 6 PIN Y1 SDRAM Data 6 42 User Manual DRAM DQ 7 PIN Y2 SDRAM Data 7 DRAM DQ 8 SDRAM Data 8 DRAM DQ 9 PIN 2 SDRAM Data 9 DRAM DQ 10 PIN P1 SDRAM Data 10 DRAM DQ 11 PIN P2 SDRAM Data 11 DRAM DQ 12 PIN R1 SDRAM Data 12 DRAM DQ 13 PIN R2 SDRAM Data 13 DRAM_DQ 14 PIN_T1 SDRAM Data 14 DRAM DQ 15 PIN T2 SDRAM Data 15 DRAM BA 0 PIN U3 SDRAM Bank Address 0 DRAM 1 PIN V4 SDRAM Bank Address 1 DRAM_LDQM PIN_R7 SDRAM Low byte Data Mask DRAM_UDQM PIN_M5 SDRAM High byte Data Mask DRAM_RAS_N PIN_T5 SDRAM Row Address Strobe DRAM_CAS_N PIN_T3 SDRAM Column Address Strobe DRAM_CKE P
42. nnection 0 14 GPIO_0 15 PIN_B20 GPIO Connection 0 15 GPIO O 16 PIN_C21 GPIO Connection 0 16 GPIO_0 17 PIN_C22 GPIO Connection 0 17 GPIO 18 PIN_D21 GPIO Connection 0 18 GPIO 0O 19 PIN_D22 GPIO Connection 0 19 20 PIN E21 GPIO Connection 0 20 GPIO 0 21 PIN E22 GPIO Connection 0 21 GPIO 0 22 PIN F21 GPIO Connection 0 22 GPIO 23 PIN F22 GPIO Connection 0 23 GPIO 24 PIN G21 GPIO Connection 0 24 GPIO 25 PIN G22 GPIO Connection O 25 GPIO 26 PIN J21 GPIO Connection O 26 GPIO 0 27 PIN J22 GPIO Connection 0 27 GPIO 28 PIN K21 GPIO Connection O 28 GPIO 29 PIN K22 GPIO Connection 0 29 GPIO 30 PIN_J19 GPIO Connection 0 30 GPIO O 31 PIN J20 GPIO Connection O 31 GPIO 32 PIN J18 GPIO Connection 0 32 GPIO O 33 PIN K20 GPIO Connection 0 33 GPIO O 34 PIN L19 GPIO Connection 0 34 GPIO 35 PIN L18 GPIO Connection 0 35 GPIO 1 0 PIN H12 GPIO Connection 1 0 GPIO 1 1 PIN H13 GPIO Connection 1 1 34 User Manual GPIO 1 2 PIN H14 GPIO Connection 1 2 GPIO 19 PIN G15 GPIO Connection 1 3 GPIO 1 4 PIN E14 GPIO Connection 1 4 GPIO 1 5 PIN E15 GPIO Connection 1 5 GPIO 1 6 PIN F15 GPIO Connection 1 6 GPIO 1 7 PIN G16 GPIO Connection 1 7 GPIO 1 8 PIN F12 GPIO Connection 1 8 GPIO 1 9 PIN F13 GPIO Connection 1 9 GPIO 1 10 PIN C14 GPIO Conne
43. onfiguration device and USB Blaster circuit Altera s EPCS4 Serial Configuration device On board USB Blaster for programming and user API control JTAG and AS programming modes are supported SAN DEI User Manual SRAM 512 Kbyte Static RAM memory chip e Organized as 256K x 16 bits e Accessible as memory for the Nios II processor and by the DE1 Control Panel SDRAM e 8 Mbyte Single Data Rate Synchronous Dynamic RAM memory chip e Organized as 1M x 16 bits x 4 banks e Accessible as memory for the Nios II processor and by the DE1 Control Panel Flash memory e 4 Mbyte NOR Flash memory e 8 bit data bus e Accessible as memory for the Nios II processor and by the DEI Control Panel SD card socket e Provides SPI mode for SD Card access e Accessible as memory for the Nios II processor with the DEI SD Card Driver Pushbutton switches 4 pushbutton switches e Debounced by a Schmitt trigger circuit e Normally high generates one active low pulse when the switch is pressed Toggle switches e 10 toggle switches for user inputs e switch causes logic 0 when in the DOWN closest to the edge of the DEI board position and logic 1 when in the UP position Clock inputs e 50 MHz oscillator e 27 MHz oscillator e 24 MHz oscillator e SMA external clock input Audio CODEC Wolfson WM8731 24 bit sigma delta audio CODEC e Line level input line level output and microphone input jacks 7 NO AYA DEI User Manua
44. ort standard VGA resolution 640x480 pixels at 25 MH2 hand E VGA RO AA VGA R1 E A Ph hd VGA R2 VGARS R RN1 2K 2 RO603 4R N 3 z ANE 8 1 8 pa z a SAN Ea RN2 ik aa ARNA La VGA G0 SHIELDO Hi aN 32 SHIELD RN3 XK G RO603 4R N brn CINNE GND Pe AALS miki a RN4 1K R0603 4R N RD A VGA 80 Wo VGA 81 L2 D AT VGA B2 1 83 RN5 E RO603 4R N VGA_VSYNC pa zl A8 RN8 1K R0603 4R N R 0603 R13 120 VGA HSYNC VGA VSYNC lt Figure 4 11 VGA circuit schematic The timing specification for VGA synchronization and RGB red green blue data can be found on various educational web sites for example search for VGA signal timing Figure 4 12 illustrates the basic timing requirements for each row horizontal that is displayed on a VGA monitor An active low pulse of specific duration time a in the figure is applied to the horizontal synchronization Async input of the monitor which signifies the end of one row of data and the start of the next The data RGB inputs on the monitor must be off driven to 0 V for a time period called the back porch b after the hsync pulse occurs which is followed by the display interval c 36 DEI User Manual During the data display interval the RGB data drives each pixel in turn across the row being displayed Finally there is a time period ca
45. ovides a tool with the associated IP that allows the user to display an image via the VGA output port To illustrate this feature we will show how an image can be displayed on a VGA monitor Perform the following steps to display a default image e Select the VGA tab in the Control Panel to reach the window in Figure 3 9 DEL DE1 Control Panel Open Help About PS2 amp LED DE1 Board Cyclone II FPGA Starter Board Cursor X O ter asic Cursor Y 0 www terasic com v Default Image Cursor Enable Figure 3 9 Displayed image and the cursor controlled by the scroll bars Make sure that the checkboxes Default Image and Cursor Enable are checked Connect VGA monitor to the DEI board and you should see on the screen the default image shown in Figure 3 9 The image includes a cursor which can be controlled by means of the X Y axes scroll bars on the DE1 Control Panel 19 DE1 User Manual JAN DTE RAN The image in Figure 3 9 is stored in an M4K memory block in the Cyclone II FPGA It is loaded into the M4K block in the MIF Hex Intel format during the default bit stream configuration stage We will next describe how you can display other images and use your own images to generate the binary data patterns that can be displayed on the VGA monitor Another image is provided in the file picture dat in the folder DEI demonstrationsWictures on the DE1 System CD ROM You can display this image as follows Select the S
46. propriate search on various educational web sites The pin assignments for the associated interface are shown in Table 4 11 5 5 R36 R37 2K 2K PS2 DAT R 120 PS2 CLK AVAL I ves 1 NCO TOP D1 D2 en BAT54S BAT54S i 3 vec GND 4 GND 2 2 EIL s8 62 GND eK 010 GND SHIELDO 10 O2 j SHEL ND 9 SHIELD2 GND VCC33GND VvCC33 n a 9 N Figure 4 17 PS 2 schematic PS2_CLK PIN_H15 PS 2 Clock PS2_DAT PIN_J14 PS 2 Data Table 4 11 PS 2 pin assignments 4 10 Using SDRAM SRAM Flash The DEI board provides an 8 Mbyte SDRAM 512 Kbyte SRAM and 4 Mbyte 1 Mbyte on some boards Flash memory Figures 4 23 4 24 and 4 25 show the schematics of the memory chips The pin assignments for each device are listed in Tables 4 16 4 17 and 4 18 The datasheets for the memory chips are provided in the Datasheet folder on the DE1 System CD ROM 40 DE1 User Manual R_VCC33 DRAM_DO R_VCC33 DRAM_D1 DRAM_D2 GND DRAM D3 DRAM D4 R_VCC33 DRAM_D5 DRAM_D6 GND DRAM_D7 R_VCC33 DRAM_LDQM DRAM_WE DRAM_CAS DRAM_RAS DRAM_CS DRAM_BAO DRAM_BA1 DRAM A10 DRAM DRAM A1 DRAM A2 DRAM A3 R_VCC33 SRAM_AO SRAM_A1 SRAM_A2 SRAM_A3 SRAM_A4 SRAM_CE SRAM_DO SRAM_D1 SRAM_D2 SRAM_D3 R_VCC33 GND SRAM_D4 SRAM_D5 SRAM_D6 SRAM_D7 SRAM_WE SRAM_A5 SRAM_A6 SRAM_A7 SRAM A8 S
47. r Port 1 Async 1 OSD VGA DAC VGA LCD CRT Memory Controller DAC Monitor PC Side DE1 Control Panel Host Port User Port Async 3 4 Flash Flash User Port 2 Async2 Controller Memory User Port 1 Async 1 1 Khz Sine Wave Audio DAC Audio Look up Table Controller DAC Figure 3 11 Multi Port Controller configured to display an image from the SRAM Figure 3 12 A displayed image 21 SYAN DEI User Manual You can display any image file by loading it into the SRAM chip or into an M4K memory block in the Cyclone II chip This requires generating a bitmap file which may be done as follows 1 2 Load the desired image into an image processing tool such as Corel PhotoPaint Resample the original image to have a 640 x 480 resolution Save the modified image in the Windows Bitmap format Execute DEI control paneNmgConv exe an image conversion tool developed for the DEI board to reach the window in Figure 3 13 Click on the Open Bitmap button and select the 640 x 480 Grayscale photo for conversion When the processing of the file is completed click on the Save Raw Data button and a file named Data Gray dat will be generated and stored in the same directory as the original image file You can change the file name prefix from Raw Data to another name by changing the File Name field in the displayed window Raw Data Gray dat is the
48. r of demonstrations that illustrate the advanced capabilities of the DEI board In order to use the DEI board the user has to be familiar with the Quartus II software The necessary knowledge can be acquired by reading the tutorials Getting Started with Altera s DEI Board and Quartus II Introduction which exists in three versions based on the design entry method used namely Verilog VHDL or schematic entry These tutorials are provided in the directory DEI tutorials on the DE1 System CD ROM that accompanies the DEI board and can also be found on Altera s DEI web pages BYA DEI User Manual 2 22 Block Diagram of the DE1 Board Figure 2 2 gives the block diagram of the DE1 board To provide maximum flexibility for the user all connections are made through the Cyclone II FPGA device Thus the user can configure the FPGA to implement any system design SD Card Socket Triple 4 bit VGA DAC Cyclone Il NOR Fash MB FPGA SDRAM 8 Mbytes 2C20 User Red LEDs 10 SRAM 512 Kbytes PS 2 amp RS 232 Ports 7 Segment Display 4 Toggle Switches 10 Expansion Headers 2 Pushbutton Switches 4 EPCS4 Config uds Device Blaster Figure 2 2 Block diagram of the DEI board Following is more detailed information about the blocks in Figure 2 2 Cyclone II 2C35 FPGA 18 752 LEs 52 MAK RAM blocks 240K total RAM bits 26 embedded multipliers 4 PLLs 315 user I O pins FineLine BGA 484 pin package Serial C
49. s 27 DE1 User Manual LEDR1LEDR ZA LEDR2 LEDR LEDR3LEDR GND RN16 A LED5 LED6 LED LEDR4LEDR ZA LEDR5LEDR ZA 330 LEDR6 LEDR ZA LEDR7 LEDR LEDR8LEDR ZA RN17 GND LEDR9LEDR GND A LEDGOLEDG A LEDG1LEDG A LEDG3LEDG GND LEDG7LEDG GND Figure 4 5 Schematic diagram of the LEDs SW 0 PIN L22 Toggle Switch 0 SW 1 PIN L21 Toggle Switch 1 SWI 2 PIN M22 Toggle Switch 2 5 13 PIN 12 Toggle Switch 3 5 4 PIN W12 Toggle Switch 4 9 2 Toggle Switch 5 SW 6 PIN 011 Toggle Switch 6 SWIT PIN M2 Toggle Switch 7 28 User Manual SW 8 PIN M1 Toggle Switch 8 SW 9 PIN L2 Toggle Switch 9 Table 4 1 Pin assignments for the toggle switches KEY 0 PIN_R22 Pushbutton 0 KEY 1 PIN R21 Pushbutton 1 KEY 2 PIN_T22 Pushbutton 2 KEY 3 PIN_T21 Pushbutton 3 Table 4 2 Pin assignments for the pushbutton switches LEDR O PIN R20 LED Red 0 LEDR 1 PIN R19 LED Red 1 LEDR 2 PIN U19 LED Red 2 LEDR 3 PIN Y19 LED Red 3 LEDRI4 PIN T18 LED 4 LEDR 5 PIN V19 LED Red 5 LEDRI6 PIN Y18 LED Red 6 LEDR 7 PIN U18 LED 7 LEDRI8 PIN R18 LED Red 8 LEDR 9 PIN R17 LED Red 9 LEDG O PIN U22 LED Green 0 LEDG
50. s can press KEYI The TONE GENERATOR has two tones 1 String 2 Brass which can be controlled by SWO 47 N YA DE1 User Manual The audio codec used on the DE1 board has two channels which can be turned ON OFF using SW1 and SW2 Speaker Line Out VGA Out j CDEFGABCDEFGABCDEFGAB VGA LCD CRT Monitor Music Synthesizer Algorithms for Audio Processing Figure 5 1 The Setup of the Music Synthesizer Demonstration CYCLONE 2020 VGA VS DEMO1 CODE VGA CLOCK DEMO2 CODE VGA RIS W VGA G 3 1 VGABI3 E SOUND2_CODE i Figure 5 2 Block diagram of the Music Synthesizer design 48 SYN DEI User Manual Demonstration Setup File Locations and Instructions e Project directory DEI Synthesizer Bit stream used DEI Synthesizer sof or Synthesizer pof Connect a PS 2 Keyboard to the DEI board Connect the VGA output of the DEI board to a VGA monitor both LCD and CRT type of monitors should work Connect the Lineout of the DEI board to a speaker Load the bit stream into FPGA 9 Make sure all the switches SW 9 0 are set to 0 Down Position e Press KEYI on the DEI board to start the music demo e Press KEYO on the DEI board to reset the circuit Figure 5 3 illustrates the usage of the switches pushbuttons KEYs PS 2 Keyboard e Switches and Pushbuttons 0 Reset Circuit KEY 1 Repeat the Demo M
51. structions Project directory DE1_i2sound Bit stream used DE1_i2sound sof or DE1_i2sound pof Connect a microphone to the microphone in port pink color on the DE1 board Connect the audio output of a music player such as an MP3 player or computer to the line in port blue color on the DE1 board Connect headset speaker to the line out port green color on the board Load the bit stream into the FPGA You should be able to hear a mixture of the microphone sound and the sound from the music player Press KEYO to adjust the volume it cycles between volume levels 0 to 9 Figure 5 8 illustrates the setup for this demonstration MP3 Any Audio Output 4 SD Card with Music File WAV Clock Data Frequency Generator Figure 5 8 The setup for the Karaoke Machine 51 SYN DEI User Manual 5 4 SD Card Music Player Many commercial media audio players use a large external storage device such as an SD card or CF card to store music or video files Such players may also include high quality DAC devices so that good audio quality is produced The DE1 board provides the hardware and software needed for SD card access and professional audio performance so that it is possible to design advanced multimedia products using the DE1 board In this demonstration we show how to implement an SD Card Music Player on the DEI board in which the music files are stored in an SD card and the board can play the music
52. tion 3 4 Then write a music file into the Flash memory You can use the file music wav in the directory demonstrationsvnusic on the DE1 System CD ROM 2 In the DEI Control Panel select the TOOLS tab to reach the window in Figure 3 8 DE DE1 Control Panel Open Help About PS2 amp LED SRAM SDRAM Multiplexer Host USB Port m FLASH Multiplexer Asynchronous 1 SRAM Multiplexer Host USB Port Y Figure 3 8 TOOLS window of the DEI Control Panel 3 Select the Asynchronous 1 port for the Flash Multiplexer and then click on the Configure button to activate the port You need to click the Configure button to enable the connection from the Flash Memory to the Asynchronous Port 1 of the Flash Controller indicated in Figure 3 7 4 Set toggle switches SW1 and SWO to OFF DOWN position and ON UP position respectively 5 Plug your headset or a speaker into the audio output jack and you should hear the music 18 AND YAN DEI User Manual played from the Audio DAC circuit 6 Note that the Asynchronous Port 1 is connected to the Audio DAC part as shown in Figure 3 7 Once you selected Asynchronous Port 1 and clicked the Configure button the Audio DAC Controller will communicate with the Flash memory directly In our example the AUDIO DAC Verilog module defines a circuit that reads the contents of the Flash memory and sends it to the external audio chip 3 7 VGA Display Control The Control Panel pr
53. usic SW 0 OFF BRASS ON STRING SWI 9 OFF DEMO ON PS2 KEYBOARD Channel 1 ON OFF SW 2 Channel 2 ON OFF e PS 2 Keyboard Q 4 A 5 w 5 s 6 E 6 D 7 F 1 T 1 G 2 Y 2 H 3 J 4 AYA DEI User Manual 4 K 5 5 L 6 P 6 7 1 Figure 5 3 Usage of the Key 5 3 A Karaoke Machine This demonstration uses the microphone in line in and line out ports on the DEI board to create a Karaoke Machine application The Wolfson WM8731 audio CODEC is configured in the master mode where the audio CODEC generates AD DA serial bit clock BCK and the left right channel clock LRCK automatically As indicated in Figure 5 7 the I2C interface is used to configure the Audio CODEC The sample rate and gain of the CODEC are set in this manner and the data input from the line in port is then mixed with the microphone in port and the result is sent to the line out port For this demonstration the sample rate is set to 48 kHz Pressing the pushbutton KEYO reconfigures the gain of the audio CODEC via the I2C bus cycling through one of the ten predefined gains volume levels provided by the device I2C Audio Line out Configuration Push Button Line in Bypass ADC to DAC Figure 5 7 Block diagram of the Karaoke Machine demonstration 50 N DTE YA DE1 User Manual Demonstration Setup File Locations and In
54. uter that runs the Microsoft Windows software 1 4 Package Contents Figure 1 1 shows a photograph of the DEI package Altera Design Software Suite Version 6 0 for Windows HED Development amp Education Board Figure 1 1 The DEI package contents The DEI package includes e DEI board e USB Cable for FPGA programming and control e CD ROM containing the DEI documentation and supporting materials including the User Manual the Control Panel utility reference designs and demonstrations device datasheets tutorials and a set of laboratory exercises 1 NBDr amp 5 DEI User Manual e CD ROMs containing Altera s Quartus II 6 0 Web Edition software and the Nios II 5 0 embedded processor e Bag of six rubber silicon covers for the DEI board stands The bag also contains some extender pins which can be used to facilitate easier probing with testing equipment of the board s I O expansion headers e Clear plastic cover for the board e 9V DC wall mount power supply 1 2 The DE1 Board Assembly To assemble the included stands for the board e Assemble a rubber silicon cover as shown in Figure 1 2 for each of the six copper stands on the DEI board e The clear plastic cover provides extra protection and is mounted over the top of the board by using additional stands and screws r Figure 1 2 The feet for the DE1 board JAN DTE RYA DE1 User Manual 1 3 Here are the ad
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