NI 5793R User Manual and Specifications
Contents
1. 4400 MHz LPF ie g A RX NI 5793 Component Level Intellectual Property CLIP The LabVIEW FPGA Module includes component level intellectual property CLIP for HDL IP integration NI FlexRIO devices support two types of CLIP user defined and socketed e User defined CLIP allows you to insert HDL IP into an FPGA target enabling VHDL code to communicate directly with an FPGA VI e Socketed CLIP provides the same IP integration of the user defined CLIP but also allows the CLIP to communicate directly with circuitry external to the FPGA Adapter module socketed CLIP allows your IP to communicate directly with both the FPGA VI and the external adapter module connector interface The following figure shows the relationship between an FPGA VI and the CLIP 10 NI 5793R User Manual and Specifications ni com Figure 6 CLIP and FPGA VI Relationship NI FlexRIO FPGA Module FPGA User Defined CLIP CLIP Socket User Defined 4 7 Labview 4 Saad Adan CLIP FPGAVI p ockete apter i cup K Eed A Module gt rt yi DRAM 0 DRAM 1 CLIP Socket CLIP Socket i Adapter Module i External V O Connector Socketed Socketed CLIP CLIP The NI 5793 ships with socketed CLIP items that add module I O to the LabVIEW project NI 5793 CLIP 1 NI 5793 CLIP This CLIP2. 104 12 Response dBc 14 4 16 4 18 4 20 T T T T T 1 50E 08 1 00E 0 5 00E 07 0 00E 00 5 00E 07 1 00E 08 1 50E 08 Frequency Offset Hz Frequency Settling Time Settling Umit eucaannsananuiiriainniaa lt 50 ms per 100 MHz step Phase Noise Note All values are nominal Table 10 Phase Noise at 2 4 GHz Offset Frequency Loop Phase Noise dBc Hz 1 kHz 85 10 kHz 95 3 All LO step size specifications are assumed to be with fractional mode enabled and a 100 kHz LO step size The settling time specification only includes frequency settling and it excludes any residual amplitude settling that may occur as a result of large frequency changes Driver and operating system timing can affect transition times This specification reflects only hardware settling 4 NI 5793R User Manual and Specifications National Instruments 27 Table 10 Phase Noise at 2 4 GHz Continued Offset Frequency Loop Phase Noise dBc Hz 100 kHz 97 1 MHz 100 10 MHz 110 Figure 12 Phase Noise 50 900 MHz 2 4 GHz 44 GHz 70 a a Z _g99 2 O zZ 2 S 110 aM 130 4 N 150 T T T T T 10 100 1k 10k 100k 1M 10M Offset Frequency Hz Baseband Characteristics Digital to Analog Converters DAC gt Part number TI DAC 3482 ReSOlUtION ccecccecceesecessceesseeceseecsseeeesaees 16 bits
3. NI 5793R User Manual and Specifications National Instruments 17 e The CPTR period must be the same across all devices Devices can have different Sample Clock frequencies if the device Sample Clocks have a fixed phase relationship e Route the FPGA I O lines to all the devices that you are synchronizing Synchronization Versions The synchronization library provides two alignment methods depending on user needs FPGA self synchronization and host driven synchronization Both synchronization methods produce the same quality of synchronization but differ in their requirements and versatility of operation FPGA Self Synchronization FPGA self synchronization does not require host involvement Using the host VIs is optional The FPGAs can all independently align their CPTRs To perform a self synchronization your devices must meet the following requirements e Sample Clocks are locked to the same Reference Clock e Sample Clocks are an integer multiple of the Reference Clock e All the devices are fewer than 60 degrees out of phase with each other Note FPGA self synchronization is repeatable only if the devices meet all the requirements If the devices do not meet the requirements use host driven synchronization Host Driven Synchronization Host driven synchronization allows you to perform the following actions e Decouple the Sample Clock and the Reference Clock e Use an external Sample Clock Set the CPTR period manu
4. 0 DIO Port 0 Wr Data 0 DIO Port 0 Rd Data 1 DIO Port 0 Wr Data 1 DIO Port 0 Rd Data 2 DIO Port 0 Wr Data 2 DIO Port 0 Rd Data 3 DIO Port 0 Wr Data 3 DIO Port 0 WE DIO Port 0 0 A A DIO Port 0 1 DIO Port 0 2 A y Y F DIO Port 0 3 4 A J PISE DIO Port 1 Rd Data 0 DIO Port 1 Wr Data 0 DIO Port 1 Rd Data 1 DIO Port 1 Wr Data 1 DIO Port 1 Rd Data 2 DIO Port 1 Wr Data 2 DIO Port 1 Rd Data 3 DIO Port 1 Wr Data 3 DIO Port 1 WE DIO Port 4 0 y JE DIO Port 1 1 AUX I O DIO Port 4 2 y y DIO Port 1 3 A i PFI 0 Rd Data PFI O Wr Data PFI 1 Rd Data PFI 1 Wr Data PFI 2 Rd Data PFI 2 Wr Data PFI 3 Rd Data PFI 3 Wr Data PFIO Vv y PFI1 KAN A T y y J PFI2 y cq PFI3 PFI lt 0 3 gt WE y y T The following figure shows the NI 5793 low pass filter bank NI 5793R User Manual and Specifications National Instruments 9 Figure 5 NI 5793 Low pass Filter Bank 3800 MHz LPF Coe gt ie ae 2400 MHz LPF i RX 1800 MHz LPF ARL RX 1068 MHz LPF E x E _ AS Z _ X J 711 MHz LPF ea Ee RX 474 MHz LPF E ET RX w 16 MHz LPF TU RX
5. 14 6 oz YON seereh elit E sea a TX OUT LO OUT LO IN CLK IN CLK OUT POWT Jena nA A E N ici me 6 W AUX I O Port 0 DIO lt 0 3 gt Port 1 DIO lt 0 3 gt and PFI lt 0 3 gt Number of channels s seeseeeeeeseeseeeeeeresrerereee 12 bidirectional 8 DIO and 4 PFI Connector type cecesccesceeseceneeeeeceeeeseceeeenseeeee HDMI Interface standard cecesceececceceeceeeeseeseeneeee 3 3 V LVCMOS NI 5793R User Manual and Specifications National Instruments 29 Interface logic Maximum Vy cccceccescesessesceeseeseeseeseeseeeees 0 8 V Minimum V ppeeeeescseeceeeseeceeeeeeseeeeeeeeeeeeeees 2 0 V Maximum VoL sessesesessesesseessssersesersssrsesseee 0 4 V Minimum Vp esseescescesesseesenceeseeeeeseeseeeees 2 7V Maximum Vp eeececceseeseecesceeseeseeeeeeeeeeeeees 3 6 V Lice NEN EN AOS AE Oa ots 50 Q 20 Tout DO icuecitati ne ecg ieee mA Pull down resistOr ccceeseseeseesereeseneeeceseeeeeeee 150 kQ Recommended operating voltage ceeeeee 0 3 V to 3 6 V Overvoltage protection sssees eseese E10 V Maximum toggle frequency ceeseseeseereereeee 6 6 MHz 5 V MAXIMUM POW ceeeeeeeeeereeeeeeeeeeeee 10 mA 5 V voltage tolerance e eeeeseeeeeeseeererseeee 42Vto5V Environment Maximum altitude cccccccccsesseeseesseeeeesteeee 2 000 m at 25 C ambient temperature Pollution Degree ececesccecceeceeeseeseeseeseeneeee 2 Indoor use only Operating
6. compiling the VI The Generating Intermediate Files window displays the code generation process The Compilation Status window displays the progress of the compilation The compilation takes several minutes Click Close in the Compilation Status window Save and close the VI Save the project Creating a Host VI 1 10 11 12 In the Project Explorer window right click My Computer and select New VI to open a blank VI Select Window Show Block Diagram to open the VI block diagram Add the Open FPGA VI Reference function from the FPGA Interface palette to the block diagram Right click the Open FPGA VI Reference function and select Configure Open FPGA VI Reference In the Configure Open FPGA VI Reference dialog box select VI in the Open section In the Select VI dialog box select your project under your device and click OK Click OK in the Configure Open FPGA VI Reference dialog box The target name appears under the Open FPGA VI Reference function in the block diagram Open the FPGA Interface palette Add any Read Write Control or Invoke Method nodes necessary to configure and communicate with your FPGA VI Add the Close FPGA VI Reference function to your block diagram Wire the FPGA VI Reference function to the Close FPGA VI Reference function Save and close the VI NI 5793R User Manual and Specifications National Instruments 15 13 Save the project Run the Host VI 1 Open the front panel of y
7. 25 Amplitude settling time eeeeeeeeeseeneereeee lt 0 25 dB in less than 10 ms typical Maximum DC voltage ccceeeeeeseteeeteeeee 0 5 VDC Figure 10 LO Output Power vs LO Frequency LO Output Power dBm oa T T T T T T T 200M 700M 1 2G 1 7G 22G 27G 3 2 G 3 7 G 4 4 G LO Frequency Hz LO IN Front Panel Connector Frequency Tan Ges seinni riria i 200 MHz to 4 4 GHz Input POWETS seisesscisessctseidcssais cdecsessetactbotsestostettsses 3 dBm 3 dB nominal Input impedants sessticevetecetsesseessoniesyeseees 50Q Tip t VSWR oan cisesieces saison ccdcceaaiicchadee vasavssetenesstecass 1 78 1 Absolute maximum Powe eceseeeeereeeeeeeees 15 dBm Maximum DC powel cccceccseeceseeeeeeseeneeee 0 5 Voc TX OUT Frequency Characteristics FPreQUuency TaN GO sis niarit reinn r ENESE 200 MHz to 4 4 GHz Instantaneous bandwidth 6 dB c ceeeeee 200 MHz Tuning resolution cccccccccssseeseeseeseestesneseeseees lt 250 kHz Instantaneous bandwidth is 200 MHz at 6 dB Instantaneous bandwidth is 130 MHz at 3 dB 2 Tuning resolution combines LO step size capability and frequency shift DSP implemented on the FPGA 26 NI 5793R User Manual and Specifications ni com LO step size Integer MOE ceceeeeseseeeeeeeteeeeeeseeeeeeees 4 MHz 6 MHz 12 MHz 24 MHz Fractional mode cccesceeceeseeseeeeseeeeeeees 100 kHz step size Figure 11 TX OUT Frequency Response
8. all units shipped from the factory Unless otherwise noted typical values cover the expected performance of units over ambient temperature ranges of 23 C 5 C with a 90 confidence level based on measurements taken during development or production Nominal values or supplemental information describe additional information about the product that may be useful including expected performance that is not covered under Specifications or Typical values Nominal values are not covered by warranty Related Information Front Panel and Connector Pinouts on page 5 Connecting Cables on page 3 NI 5793 User Manual and Specifications on page 1 NI 5793R User Manual and Specifications National Instruments 21 TX OUT Amplitude Characteristics Power range OUIPUE eit cin teed Geass Noise floor to 8 dBm nominal Output resolution ceeeceeseeseeseeseeeeeeeeees 0 25 dB nominal Amplitude settling time ec eeeeeeeeeee lt 0 5 dB within 1 ms nominal Absolute Amplitude Accuracy ei Note All values are typical Table 5 Transmit Absolute Amplitude Accuracy Frequency Temperature 23 C 5 C dB gt 200 MHz to 1 GHz 0 8 1 GHz to 2 GHz 1 3 2 GHz to 3 GHz 1 3 3 GHz to 4 4 GHz 1 8 Note Absolute amplitude accuracy uses a correction coefficient in EEPROM to improve performance The TX amplitude accuracy applies to the output power level from 12 dBm to 4 dBm 22 NI 5793R User Ma
9. and Descriptions Continued Document Location Description LabVIEW Examples Available in NI Example Contains examples of how to run Finder FPGA VIs and Host VIs on your device IPNet ni com ipnet Contains LabVIEW FPGA functions and intellectual property to share NI FlexRIO product ni com flexrio Contains product information and page data sheets for NI FlexRIO devices Key Features The NI 5793 includes the following key features RF frequency range ceceececscceseeeeeeeeseeneeee 200 MHz to 4 4 GHz DA Gari thatieseshvecchachinaicnein naires 16 bit dual channel at 250 MS s 500 MS s with 2x interpolation I and Q Phase NOISSSsissisd cacvasee civsapess tetas sestonsuetegeesersetecs lt 95 dBc Hz 10 kHz offset 2 4 GHz carrier Transmit TIX TP 3 ecurine 17 dBm at 2 GHz Instantaneous bandwidth eee eeeetereeeeee 200 MHz Front Panel and Connector Pinouts Table 2 shows the front panel connector and signal descriptions for the NI 5793 A N Caution To avoid permanent damage to the NI 5793 disconnect all signals connected to the NI 5793 before powering down the module and connect signals only after the adapter module has been powered on by the NI FlexRIO FPGA module A N Caution Connections that exceed any of the maximum ratings of any connector on the NI 5793R can damage the device and the chassis NI is not liable for any damage resulting from such connections NI 5793R User Manua
10. lt your project name gt lvproj Select the destination folder for the new file specify a file name and click OK Use this FPGA VI with the NI 579x Configuration Design Library 14 NI 5793R User Manual and Specifications ni com 12 13 14 15 16 17 In the Project Explorer window expand IO Module Tree View Use any of the elements under IO Module NI 5791 NI 5791 in the block diagram of the FPGA VI Note Ifyou are using the NI 5793 CLIP use Tx I and Tx Q in a single cycle Timed Loop running on IO Module Sample Clock the 250 MHz clock This CLIP provides one sample per cycle at the 250 MHz rate Note Ifyou are using the NI 5793 Multiple Sample CLIP use Tx I N Tx I N 1 Tx Q N and Tx Q N 1 from the CLIP IO Node in a single cycle Timed Loop running on the IO Module Half Sample Clock the 125 MHz clock This CLIP provides two samples per cycle at the 125 MHz rate m m ei Note For either CLIP if you are using the DSP Instrument Design Library you must use the 2 samples per cycle 2x overclocking instances of the DSP VIs These VIs should be in a single cycle Timed Loop running on the IO Module Half Sample Clock and you should wire the IO Module Sample Clock to their clock x 2 terminals Add any FPGA code controls and indicators that you need Refer to Streaming Ivproj for example FPGA code controls and indicators Click the Run button LabVIEW creates a default build specification and begins
11. measurement control and laboratory use e EN 61326 1 IEC 61326 1 Class A emissions Basic immunity e EN 55011 CISPR 11 Group 1 Class A emissions e AS NZS CISPR 11 Group 1 Class A emissions e FCC 47 CFR Part 15B Class A emissions e ICES 001 Class A emissions Note In the United States per FCC 47 CFR Class A equipment is intended for use in commercial light industrial and heavy industrial locations In Europe Canada Australia and New Zealand per CISPR 11 Class A equipment is intended for use only in heavy industrial locations Note Group 1 equipment per CISPR 11 is any industrial scientific or medical equipment that does not intentionally generate radio frequency energy for the treatment of material or inspection analysis purposes ei Note For EMC declarations certifications and additional information refer to the Online Product Certification section CE Compliance This product meets the essential requirements of applicable European Directives as follows e 2006 95 EC Low Voltage Directive safety e 2004 108 EC Electromagnetic Compatibility Directive EMC NI 5793R User Manual and Specifications National Instruments 31 Online Product Certification To obtain product certifications and the DoC for this product visit ni com certification search by model number or product line and click the appropriate link in the Certification column Environmental Management NI i
12. CONNECT Signals and Learn About Your Adapter Module NI FlexRIO FPGA Module Installation Guide and Specifications RAS ie NI FlexRIO Adapter Module User Guide and Specifications LEARN About LabVIEW FPGA Module Are You New to PROGRAM Your NI FlexRIO System in LabVIEW FPGA LabVIEW FPGA Module Module Yes No No LabVIEW FPGA gt NI FlexRIO lt gt LabVIEW Module Help Help Examples Table 1 NI FlexRIO Documentation Locations and Descriptions Guide and Specifications manuals Document Location Description NI FlexRIO FPGA Available from the Start Contains installation instructions for Module Installation menu and at ni com your NI FlexRIO system and specifications for your FPGA module NI 5793R User Manual and Specifications this Available from the Start menu and at ni com Contains signal information examples CLIP details and manuals document manuals specifications for your adapter module LabVIEW FPGA Module Embedded in LabVIEW Contains information about the basic Help Help and at ni com functionality of the LabVIEW FPGA Module NI FlexRIO Help Available from the Start menu and at ni com manuals Contains FPGA Module adapter module and CLIP configuration information 4 NI 5793R User Manual and Specifications ni com Table 1 NI FlexRIO Documentation Locations
13. Compliance Information at ni com legal export compliance for the National Instruments global trade compliance policy and how to obtain relevant HTS codes ECCNs and other import export data 2013 National Instruments All rights reserved 373949B 01 May13
14. Data TAE sicccsecies csaceceastiens EEEE 250 MS s VQ data rate c ceccccccssscssesesscsesestesestesesees 1 84 kS s to 250 MS s 5 DACs are dual channel components with each channel assigned to I and Q respectively 6 The NI 5793 interpolates the data rate using Fractional Interpolation DSP blocks implemented in the LabVIEW FPGA target See lt resource here gt for information about how to use Frequency Shift DSP blocks 28 NI 5793R User Manual and Specifications ni com CLK IN Front Panel Connector Frequency Reference Clock ceceeceeseeseeseeseeeeeeeeees 10 MHz Sample Clock ccceccececeseeteetecneeneeeeee 250 MHz Amplitude SQUALC a a wees 0 7 Vpk pk to 5 0 Vpk pk into 50 Q typical Sine aa ar 1 4 Vok pk to 5 0 Vok pk el VRMS to 3 5 Vrms into 50 Q typical Input impedance eeeseesecsscneceeesenseeseeneene 50 Q nominal Coupling tsessatesssshiacusclerscesacueista rE AC CLK OUT Front Panel Connector Interface standard ccceecsccesceseeeeeeseeseeneene 3 3 V LVCMOS Interface logic Maximum Vo scccccssessscessessecessesseceseesseeees 0 55 V Minimum V opp eeseescesceeescessenseeseeeeeeeeeeeeees 2 7V Maximum V 0p eeeescescsscssescenceeseeseeeeeseeseeeees 3 6V Output impedance ee eeeeeeeeeereeee 50 Q 20 Coupling coercion iniii DC Tout DG nie shishslinenineed bused Ss mA Dimensions and Weight DIMENSIONS 1 5035 a ees Seales dees 12 9 x 2 0 x 12 1 cm 5 1 x 0 8 x 4 7 in Weel AEE cost A E eas 413 g
15. Environment Ambient temperature range Relative humidity range Storage Environment Ambient temperature range Relative humidity range Operational shock 30 NI 5793R User Manual and Specifications ni com 0 C to 55 C Tested in accordance with IEC 60068 2 1 and IEC 60068 2 2 10 to 90 noncondensing Tested in accordance with IEC 60068 2 56 40 C to 70 C Tested in accordance with IEC 60068 2 1 and IEC 60068 2 2 5 to 95 noncondensing Tested in accordance with IEC 60068 2 56 30 g peak half sine 11 ms pulse Tested in accordance with IEC 60068 2 27 Test profile developed in accordance with MIL PRF 28800F Random vibration Operating sss isc siesistasiasiasasseecaesaeecsccsseccaaees 5 Hz to 500 Hz 0 3 gims Nonoperating ccccecceeceeeeecereereeseeseeeenes 5 Hz to 500 Hz 2 4 gims Tested in accordance with IEC 60068 2 64 Nonoperating test profile exceeds the requirements of MIL PRF 28800F Class 3 Compliance and Certifications Safety This product is designed to meet the requirements of the following electrical equipment safety standards for measurement control and laboratory use e IEC 61010 1 EN 61010 1 e UL 61010 1 CSA 61010 1 Note For UL and other safety certifications refer to the product label or the Online Product Certification section Electromagnetic Compatibility This product meets the requirements of the following EMC standards for electrical equipment for
16. MC compliance operate this device according to the documentation NATIONAL INSTRUMENTS The following figure shows an example of a properly connected NI FlexRIO device Figure 1 NI FlexRIO Device NI FlexRIO NI FlexRIO Adapter Module FPGA Module NI FlexRIO Device Related Information NI 5793 Specifications on page 21 Contents Electromagnetic Compatibility Guidelines cccccccseeseesceseeseeeeeseeeseeseeaeceeseaecaecaeeeeeeeeeeetaees 3 Connecting Cables s vcxcssesscassesscaxecs ses cacted sxe fonsendessesunsecdee coddsaaitya cvesete eteesnessdetiens neds ea ESEESE SRT caenay 3 How to Use Your NI FlexRIO Documentation Set ccccceescesscsseeseeeeceseceeeeeeeceaeeeeeeeeeees 4 Key PG Att 2 ci eas tves vives ctnvesacdensiaves senses ds desta E ecidsdsuveuaceessdcwessasdeuseveesdasuscvans ET 5 Front Panel and Connector Pimouts ccceeeeessceecsceececesceseseeeceeesceacsesscsaeeessecesseseeeecaesateeenenees 5 AUX T O Connector iis is sss sscisaiss E oad eso see sasha sovtoeusedssioss sdosbte caste sade dpa sesceseso edhe 7 Block Dita praimiysessscsissscuvensecdsascseictvyosteccestensestysausousediessesveas SASKARES ds lbsdecs dasveashsussstboussuarcssos 8 NI 5793 Component Level Intellectual Property CLIP 0 ceceeseseeeseeseeeceeeeceeeeeeeeeeeees INS 7 SiC TP asses EE e E AENEA S aati eases ee ee Programmable Chips si csiicesscatessesssteieesvessetecssens sh uvaveseeonedestsnseee Using Y
17. OUT Frequency Character istics c cccccscesscsescesecsseeseeecesecseeeeecseeseceaeeseeeeeeaeseaeenes 26 Baseband Characteristicses ssseiiesssssisedeees sseisetvecs consseiness seine ness ie E a r EEEE E 28 AUX I O Port 0 DIO lt 0 3 gt Port 1 DIO lt 0 3 gt and PFI lt 0 3 gt ne 29 ENVITONMEN t saniaisen iausir enren Ea EEEa SESEK ES AREE i ea 30 Compliance and Certifications ccccccccessesscescessesecsccescecseeseeseeeceeceaecaecaeeseecsecaeeaeeeeees 31 Installing PXT EMC Filler Pamels cccssssssssessesessossecetorsroeesncanetoseesncusesasoeoncesesaresosesaes 32 Whereto Go for Support 0 205 Aaa aid ae ne aces ene et tesa teenie ote 33 Electromagnetic Compatibility Guidelines This product was tested and complies with the regulatory requirements and limits for electromagnetic compatibility EMC stated in the product specifications These requirements and limits are designed to provide reasonable protection against harmful interference when the product is operated in the intended operational electromagnetic environment This product is intended for use in industrial locations However harmful interference may occur in some installations when the product is connected to a peripheral device or test object or if the product is used in residential or commercial areas To minimize interference with radio and television reception and prevent unacceptable performance degradation install and use this product i
18. USER MANUAL AND SPECIFICATIONS NI 5793R RF Transmitter Adapter Module The NI 5793 is an RF transmitter adapter module designed to work in conjunction with your NI FlexRIO FPGA module The NI 5793 features the following connectors and chips 2 channel 250 MS s 500 MS s after interpolation digital to analog converter DAC with 16 bit accuracy LO input and LO output connectors to support LO sharing for multiple channel applications Timing chip with clocking options from the backplane and the front panel Programmable attenuation Selectable transmit filters The following front panel connectors LOOUT CLKIN CLK OUT LOIN TX OUT This document contains signal information and lists the specifications of the NI 5793R which is composed of the NI FlexRIO FPGA module and the NI 5793 This document also contains tutorial sections that demonstrate how to acquire data using a LabVIEW FPGA Example VI and how to create and run your own LabVIEW project with the NI 5793R M AM wv Note MI 5793R refers to the combination of your NI 5793 adapter module and your NI FlexRIO FPGA module NI 5793 refers to your NI 5793 adapter module only Note The NI 5793 is only compatible with the NI PXIe 796xR FPGA modules Note Before configuring your NI 5793R you must install the appropriate software and hardware Refer to the NJ FlexRIO FPGA Module Installation Guide and Specifications for installation instructions Note For E
19. ally Host driven synchronization requires an additional FPGA I O line and host involvement for CPTR alignment Note Host driven synchronization is repeatable only if the phase relationships between devices remain constant Host driven synchronization guarantees that the maximum phase offset between the master and slave device is one half of a Sample Clock period The phase offset approaches zero as the phase relationships between the devices approach zero Note The phase relationship between the device and the Reference Clock does not affect host driven synchronization Synchronization Example You can find examples of both FPGA code and host code for synchronization at lt labview gt examples instr ni579x Streaming 18 NI 5793R User Manual and Specifications ni com How Synchronization Works When you share triggers between multiple devices propagation delays on the signal path cause the trigger to arrive at different times on each device The synchronization library uses the CPTR to slow down the trigger evaluation rate All devices must produce a CPTR signal that is equal in frequency and phase aligned The synchronization FPGA VIs produce and align a CPTR that occurs simultaneously across all the FPGAs The CPTR is periodic and the Sample Clock rate controls the CPTR period When you power on the FPGAs the CPTRs are not aligned The alignment FPGA VI and the host VI align the CPTRs The following figure shows the relatio
20. ation TX Sideband Image Suppression e Note All values are nominal 24 NI 5793R User Manual and Specifications ni com Table 8 Image Suppression Frequency Temperature 23 C 5 C dBc gt 200 MHz to 1 GHz 50 gt 1 GHz to 2 GHz 50 gt 2 GHz to 3 GHz 50 gt 3 GHz to 4 4 GHz 45 Note The image suppression specifications hold at the center frequency of the transmitted instantaneous bandwidth after the device performs a recent single point I Q impairment self correction TX LO Residual Power Note All values are nominal Table 9 TX LO Residual Power Frequency Temperature 23 C 5 C dBm gt 200 MHz to 1 GHz 48 gt 1 GHz to 2 GHz 48 gt 2 GHz to 3 GHz 48 gt 3 GHz to 4 4 GHz 45 ei Note This specification holds at the center frequency of the transmitted instantaneous bandwidth 100 MHz maximum after the device performs a recent single point I Q impairment self correction The measurement is performed with 0 dB of TX attenuation LO OUT Front Panel Connector Frequency Lange eeeeeeeeeereeseeereeeteeeeeeneeees 200 MHz to 4 4 GHz POWOD inissecicckevesb encan e eaa aiina 3 dBm 3 dB nominal Output power resolution ss sessiseeseeseserseeeeee 0 15 dB Output Impedance ceeeceeceeceseeeeeeeseeseeneeee 50 Q nominal Output VSWR nensi iiia 1 78 1 NI 5793R User Manual and Specifications National Instruments
21. fig v1 FPGA Public ni579x Config FPGA Template vi The FAM Support installer installs this VI on your system Configure your FPGA target to contain a FIFO with the following configuration Name reg host instruction fifo 0 e Type Host to Target DMA e Requested number of elements 1 023 Data type U64 e Arbitration for read Arbitrate if multiple requestors only Number of elements per read 1 16 NI 5793R User Manual and Specifications ni com Host VI Requirements Configure your host VI to use the NI 579x Configuration Design Library using the following configuration 1 Create a Register Bus object for your device and initialize the session using ni579x Open vi 2 Use any of the NI 579x Configuration Design Library Host VIs using the Register Bus object returned by the ni579x Open VI 3 To access the Host VIs select Functions Instrument I O Instrument Drivers NI 579x Configuration 4 Close the session using the ni579x Close VI Synchronization Overview Synchronization coordinates Sample Clock cycles across multiple NI FlexRIO devices Sources of error such as common clock propagation delay cabling and cable lengths analog delays in the FPGA module and or adapter module and skew jitter in the common clock can affect frequency and phase relationships between devices Use the programming example to synchronize across multiple NI FlexRIO adapter modules Synchronization aligns the devices so that t
22. generates one sample per clock cycle at a default sample rate of 250 MHz You can set a lower sample rate by using an external Sample Clock This CLIP provides access to I and Q data for one RF transmit channel The CLIP also provides a User Command interface for common configurations of the base band clocking programmable attenuator transmit filters LO filters and RF path which includes the ability to import and export the LO The baseband clocking can be configured using one of the following settings e Internal Sample Clock e Internal Sample Clock locked to an external Reference Clock through the CLK IN connector e External Sample Clock through the CLK IN connector e Internal Sample Clock locked to an external Reference Clock through the Sync Clock NI 5793 Multiple Sample CLIP This CLIP generates two samples per clock cycle at a clock rate that is half the sample rate This CLIP provides access to I and Q data for one RF transmit channel The CLIP also provides a User Command interface for common configurations of the base band clocking programmable attenuator transmit filters LO NI 5793R User Manual and Specifications National Instruments 11 filters and RF path which includes the ability to import and export the LO The baseband clocking can be configured using one of the following settings e Internal Sample Clock e Internal Sample Clock locked to an external Reference Clock through the CLK IN connector e Exte
23. he devices are synchronized to the nearest Sample Clock cycle The devices may be offset by up to one half of one Sample Clock cycle if the devices are 180 degrees out of phase If the devices are zero degrees out of phase device alignment offset is also zero degrees devices Caution Before attempting to synchronize your NI FlexRIO devices notice the 4 Note For the best synchronization results minimize the phase offset between A following caveats e Synchronization does not account for differences in analog signal paths Synchronization does not account for data pipeline delays that occur before and after the synchronization VIs For example synchronization does not account for ADC DAC pipeline delays e The synchronized edge is always delayed relative to the unsynchronized edge The application is responsible for accounting for this delay if necessary The synchronization VIs provide the actual synchronization delay value e Lock all devices to a common time reference Use the Reference Clock as the time reference e Set the synchronization registers for the Reference Clock to zero e Synchronization does not account for propagation delays of the Reference Clock e All Sample Clocks must have a fixed phase relationship with each other e The Common Periodic Time Reference CPTR period must be greater than the maximum propagation delay of a signal from the master device to any slave device across the selected FPGA I O line
24. k source controls the sample rate and other timing functions on the device The following table contains information about the possible NI 5793 clock sources 20 NI 5793R User Manual and Specifications ni com Table 4 NI 5793R Clock Sources Clock Frequency Source Options Sample Clock 250 MHz Free running and internally sourced e External through the CLK IN front panel connector Reference Clock 10 MHz Free running and internally sourced e External through the CLK IN front panel connector e Sourced through PXI CLK 579x Sample Projects The NI 5793 software contains sample projects that are a starting point for application development The projects are available in LabVIEW under Create Project Sample Projects NI 579X NI 5793 Specifications Specifications are warranted by design and under the following conditions unless otherwise noted e Chassis fan speed is set to High In addition NI recommends using slot blockers and EMC filler panels in empty module slots to minimize temperature drift The NI 5793 uses NI LabVIEW and LabVIEW FPGA software Specifications describe the warranted product performance over ambient temperature ranges of 0 C to 55 C unless otherwise noted Typical values describe useful product performance beyond specifications that are not covered by warranty and do not include guardbands for measurement uncertainty or drift Typical values may not be verified on
25. l and Specifications National Instruments 5 Table 2 NI 5793 Front Panel Connectors ALL COAX 5VDCM 200 MHz RF Transmitter IAL PORTS MAX 50 W 033 VDC 4 4 GHz Device Front Panel Connector Signal Description LO OUT Local oscillator output 12 dBm maximum 0 dBm gt PONTRUMENTs CLK IN Reference Clock input 50 Q single ended 20 dBm mee maximum CLK OUT Exported clock output DC coupled 0 V to 2V LO IN Local oscillator input 20 dBm maximum TX OUT Transmit channel 20 dBm maximum AUXTO Refer to the table below for signal list and descriptions Related Information NI 5793 Specifications on page 21 6 NI 5793R User Manual and Specifications ni com AUX I O Connector Table 3 NI 5793 AUX 1 0 Connector Pin Assignments AUX I O Connector Pin Signal Signal Description 1 DIO Port 0 0 Bidirectional single ended SE digital I O DIO data channel al i 2 GND Ground reference for signals a 17 3 DIO Port 0 1 Bidirectional SE DIO data channel k 13 4 DIO Port 0 2 Bidirectional SE DIO data channel 12 5 GND Ground reference for signals 9 6 DIO Port 0 3 Bidirectional SE DIO data channel 6C_J 7 DIO Port 1 0 Bidirec
26. n strict accordance with the instructions in the product documentation Furthermore any modifications to the product not expressly approved by National Instruments could void your authority to operate it under your local regulatory rules AN Caution To ensure the specified EMC performance operate this product only with shielded cables and accessories Caution To ensure the specified EMC performance the length of all I O cables must be no longer than 3 m 10 ft A N Caution To ensure the specified EMC performance you must install PXI EMC Filler Panels National Instruments part number 778700 1 in adjacent chassis slots Related Information Installing PXI EMC Filler Panels on page 32 Connecting Cables 1 Use any shielded 50 Q SMA cable to connect signals to the connectors on the front panel of your device 2 Use the SHH19 H19 AUX cable NI part number 152629 01 or 152629 02 to connect to the digital I O DIO and programmable function interface PFI signals on the AUX I O connector NI recommends using the SCB 19 connector block to access the DIO and PFI signals Related Information NI 5793 Specifications on page 21 NI 5793R User Manual and Specifications National Instruments 3 How to Use Your NI FlexRIO Documentation Set Refer to Figure 2 and Table 1 to learn how to use your FlexRIO documentation set Figure 2 How to Use Your NI FlexRIO Documentation Set INSTALL Hardware and Software
27. nship between the CPTRs the Reference Clock and the Sample Clock Figure 7 CPTR Alignment Reference Clock Sample Clock CPTR Device A CPTR Device B ei Note Lock Device A and Device B to a common clock Once the CPTRs are aligned synchronize an edge across multiple FPGAs The master device distributes the signal across an FPGA I O line All devices monitor the same FPGA I O line The edge is synchronized at the next CPTR edge After all the device CPTRs are aligned an edge sent out on the FPGA I O lines is read at the same clock cycle across all the devices Note The quality of synchronization is only as good as the quality of Sample Clock locking Some static skew may exist You can calibrate to eliminate this skew if necessary The following figure shows the relationship between the time that the master device reads a Reference Trigger Ref Trig and the time that all the devices read the synchronized version of the Reference Trigger Synchronized Ref Trig This synchronization requires CPTR alignment on all the devices Figure 8 Reading the Reference Triggers Sample Clock CPTR Device A CPTR Device B Ref Trig Synchronized Ref Trig NI 5793R User Manual and Specifications National Instruments 19 Synchr
28. nual and Specifications ni com Figure 9 TX Output Power TX Output Power dBm l T T T T T T T 200M 700M 12G 17G 22G 27G 32G 37G 44G Frequency Hz Noise Density ei Note All values are typical Frequency Temperature 23 C 5 C dBm Hz gt 200 MHz to 1 GHz 138 gt 1 GHz to 2 GHz 138 gt 2 GHz to 4 4 GHz 138 Note Performance is measured with 0 dB of TX attenuation Output Voltage Standing Wave Ratio VSWR DOHA eere ee ee E N 1 6 1 gt 2 0 GHz and lt 3 0 GHZ ccccceceeeceeecesseeees 1 4 1 30 GHZ n a abate 1 7 1 1 Note The VSWR is measured with 10 dB of TX attenuation NI 5793R User Manual and Specifications National Instruments 23 TX OUT Third Order Intermodulation IP 3 Note All values are typical Table 6 TX IP3 Frequency Temperature 23 C 5 C dBm gt 200 MHz to 1 GHz 19 gt 1 GHz to 2 GHz 17 gt 2 GHz to 3 GHz 13 gt 3 GHz to 3 9 GHz 11 gt 3 9 to 4 4 GHz 8 Note Values are based on two input tones spaced 1 3 MHz apart with 5 dB of TX attenuation Second Order Intermodulation IP gt Note All values are typical Table 7 IP Frequency Temperature 23 C 5 C dBm gt 200 MHz to 1 GHz 25 gt 1 GHz to 2 GHz 25 gt 2 GHz to 3 GHz 25 gt 3 GHz to 4 4 GHz 35 Note Values are based on two input tones spaced 1 3 MHz apart with 5 dB of TX attenu
29. onization Checklist Verify that the project settings in the system the project the host VI and the FPGA VI are configured as follows e System settings Route the FPGA I O lines to all the devices Depending on your chassis size you may have to route PXI trigger lines using Measurement amp Automation Explorer MAX Refer to the Measurement amp Automation Explorer MAX Help at ni com manuals for more information about routing PXI trigger lines with MAX e Project settings Configure the adapter module IoModSyncClock either PXI CLK10 or DStarA if you are not driving the adapter module CLK IN connector Add the FPGA Reference Clock Configure the Reference Clock to have zero synchronization registers In the FPGA IO Property dialog box set Number of Synchronization Registers for Read to 0 Add the FPGA I O lines that you are synchronizing Do not remove synchronization registers e Host VI Configure the adapter module clock source based on the project settings Lock the adapter module clock to the clock source Run the Synchronization VI Refer to the example FPGA code at lt labviewdir gt examples instr ni579x Streaming e FPGA VI Configure the CPTR period The synchronization library ensures that the CPTR period is the same on the host and the FPGA Refer to the example FPGA code at lt labviewdir gt examples instr ni579x Streaming Clocking The NI 5793 cloc
30. our NI 5793R with a LabVIEW FPGA Example VI Using the Included Streaming Example ccccccsessesseeseeseeeeeeeeeeeeeeees iss Creating a LabVIEW Project and Running a VI on an FPGA Target eceeeeeeeteees 14 NI 579x Configuration Design Library cceceessssseceeseeseseceseeeceeeseceseecsavsccnesaceeesaeeenaeaes 16 FPGA VI Requirements 16 Host VI Requirements sok Synchronization Overview 17 Synchronization Versions sccsccssssssssscesecsecsceeseeseeseceaccaseseeeseeseeeceaecaeeaeeeseeeeeeeseaeensente 18 Synchronization Example csccsssssscssscsscecssccsssssscescssessssscsssssecsesesscesessccstesescesseseeees 18 How Synchronization WOrks cists ceevsese cat sveinesece seddiysescuseneds sane aeee Ee e EE Ea Eiaa Nia 19 Synchronization Checklist ecccssessesssessceeceecseesseesecaceaecseeeeeeseeeeceaecaeeeaesseseeeeaeeneente 20 Clocking a 379x Sample Projecto wisich css seevessavests cunsuycsucootsetests sig sipssiesedestesdestandgsbassaadasstessassveasSaasdbestietens 21 INES 793 Speciicalions ecin Mae hers nisd se aa NE annie iain 21 I OY cesses tea ctssccse essa bevcasen ete cee a eos 22 LO OUT Front Panel Connectors seis csecssessssssvessesessscessoateselervect sussvcdzeotosssansteebetassndeessetees 25 LO IN Front Panel Connect0t si scissassiasids isisisi cencevesets sts aeciecrsdstasstastastasvanstessdusese 26 2 NI 5793R User Manual and Specifications ni com TX
31. our host VI 2 Click the Run button to run the VI NI 579x Configuration Design Library The NI 579x Configuration Design Library consists of host and FPGA VIs that provide an interface to configure the hardware on the NI 5793 The library allows you to perform the following actions e Configure the mixers e Configure the RF signal path including attenuators amplifiers and filters e Read from and write to the EEPROM e Configure the output power for the Tx channel e Configure the clocks e Reinitialize the CLIP Query for CLIP errors The NI 579x Configuration Design Library relies on the Register Bus Design Library The Register Bus provides a packet based configuration interface which exposes all of the address spaces of the configurable chips and subsystems of the adapter module without requiring hundreds of controls and indicators on your FPGA VI front panel The NI 579x Configuration Design Library host VIs all require a register bus object for the device you want to configure Create the register bus object using Open Session vi or use ni579x Open vi For more information about how to use the NI 579x Configuration Design Library refer to the example located at lt labview gt examples instr ni579x Streaming Streaming lvproj FPGA VI Requirements Copy all the controls indicators and FPGA logic required to use the NI 579x Configuration Design Library from the following VI lt labview gt instr lib ni579x Con
32. parately For more installation information refer to the NJ FlexRIO FPGA Module Installation Guide and Specifications 1 Remove the captive screw covers 2 Install the PXI EMC filler panels by securing the captive mounting screws to the chassis as shown in the figure below Make sure that the EMC gasket is on the right side of the PXI EMC filler panel 32 NI 5793R User Manual and Specifications ni com Figure 13 PXI EMC Filler Panels and Chassis 1 Captive Screw Covers 2 Captive Mounting Screws 3 EMC Gasket Note You must populate all slots with a module or a PXI EMC filler panel to ensure proper module cooling Do not over tighten screws 2 5 lb in maximum For additional information about the use of PXI EMC filler panels in your PXI system visit ni com info and enter emcpanels Related Information Electromagnetic Compatibility Guidelines on page 3 Where to Go for Support The National Instruments Web site is your complete resource for technical support At ni com support you have access to everything from troubleshooting and application development self help resources to email and phone assistance from NI Application Engineers A Declaration of Conformity DoC is our claim of compliance with the Council of the European Communities using the manufacturer s declaration of conformity This system affords the user protection for electromagnetic compatibility EMC and product safety You can obtain
33. reating your LabVIEW FPGA application This section explains how to use an existing LabVIEW FPGA example project to generate samples with the NI 5793R Note The examples available for your device are dependent on the version of the software and driver you are using For more information about which software versions are compatible with your device visit ni com info enter rdsoftwareversion in the text field and click the NI FlexRIO link in the results The NI 5793R example project includes the following components e A LabVIEW FPGA VI that can be compiled and run on the FPGA embedded in the hardware At least one VI that runs on Windows and interacts with the LabVIEW FPGA VI Note In the LabVIEW FPGA Module software NI FlexRIO adapter modules are referred to as JO Modules Using the Included Streaming Example Complete the following steps to run an example that acquires a waveform using the NI 5793 Connect an antenna to the TX OUT connector on the front panel of the NI 5793 Launch LabVIEW Select File Open Project Navigate to lt labview gt examples instr ni579x Streaming Select Streaming lvproj Qe E a eT In the Project Explorer window select Tx Streaming Host vi under My Computer to open the host VI The Open FPGA VI Reference function in this VI uses the NI 7966R as the FPGA target by default If you are using an NI FlexRIO FPGA module other than the NI 7966R complete the following steps to change to the FPGA VI
34. rnal Sample Clock through the CLK IN connector e Internal Sample Clock locked to an external Reference Clock through the Sync Clock This CLIP also contains a FAM Registers Bus interface which is a low level bus interface that directly programs registers on all programmable devices such as the digital to analog converter DAC Programming registers on these devices allows for more advanced configuration Note You cannot configure the LO using the User Command interface Use the FAM Registers Bus interface to program the LO synthesizer then use the User Command interface to configure the LO filters Refer to the MI FlexRIO Help for more information about NI FlexRIO CLIP items how to configure the NI 5793 with a socketed CLIP and for a list of available socketed CLIP signals Programmable Chips You can program the following chips from the CLIP Chip Part Number DAC TI DAC3482 Clock Distribution ADI AD9511 Frequency Phase Adjust DAC ADI AD5541 EEPROM SST25VF080B Programmable RF Attenuator Peregrine PE43703 Using Your NI 5793R with a LabVIEW FPGA Example VI Note You must install the software before running this example Refer to the NI FlexRIO FPGA Installation Guide and Specifications for more information about installing your software 12 NI 5793R User Manual and Specifications ni com The NI FlexRIO Adapter Module Support software includes an example project to help you get started c
35. s committed to designing and manufacturing products in an environmentally responsible manner NI recognizes that eliminating certain hazardous substances from our products is beneficial not only to the environment but also to NI customers For additional environmental information refer to the Minimize Our Environmental Impact web page at ni com environment This page contains the environmental regulations and directives with which NI complies as well as other environmental information not included in this document Waste Electrical and Electronic Equipment WEEE a4 EU Customers At the end of the product life cycle all products must be sent to a 7 WEEE recycling center For more information about WEEE recycling centers National Instruments WEEE initiatives and compliance with WEEE Directive 2002 96 EC on Waste Electrical and Electronic Equipment visit ni com environment weee htm ETRE ais eiedl HE RoHS OGD HAAA National Instruments 46 t E ETAR BP m h REH A M466 ROHS XF National Instruments F E ROHS GHEE REE ni com environment rohs_ chinao For information about China RoHS ot Wy compliance go to ni com environment rohs_china Installing PXI EMC Filler Panels To ensure specified EMC performance PXI EMC filler panels must be properly installed in your NI FlexRIO system The PXI EMC filler panels National Instruments part number 778700 01 must be purchased se
36. the DoC for your product by visiting ni com certification If your product supports calibration you can obtain the calibration certificate for your product at ni com calibration NI 5793R User Manual and Specifications National Instruments 33 National Instruments corporate headquarters is located at 11500 North Mopac Expressway Austin Texas 78759 3504 National Instruments also has offices located around the world to help address your support needs For telephone support in the United States create your service request at ni com support and follow the calling instructions or dial 512 795 8248 For telephone support outside the United States visit the Worldwide Offices section of ni com niglobal to access the branch office Web sites which provide up to date contact information support phone numbers email addresses and current events Refer to the NI Trademarks and Logo Guidelines at ni com trademarks for information on National Instruments trademarks Other product and company names mentioned herein are trademarks or trade names of their respective companies For patents covering National Instruments products technology refer to the appropriate location Help Patents in your software the patents txt file on your media or the National Instruments Patent Notice at ni com patents You can find information about end user license agreements EULAs and third party legal notices in the readme file for your NI product Refer to the Export
37. the LabVIEW FPGA CLIP 8 NI 5793R User Manual and Specifications ni com Figure 4 NI 5793 Connector Signals and CLIP Signal Block Diagram NI 5793 Adapter Module LabVIEW FPGA CLIP To RF Mixer DAC Data 45 TK 16 DAC ee TxQ DAC Clock Interface To RF Mixer Synchronize DAC DAC SPI Sample Clock OUT3 Sample Clock PLL gt Sample Clock 1 5x gt Half Sample Clock CLK IN gt CLK1 AD9511 d REF IN OUTI gt CLK2 Li OUT4 cp SPi e o I gt PLL Locked J CLK OUT O rh Sync Clock gt Register Bus Idle Register Bus Address SPI Register Register Bus Read Data Engine Bus 4 Register Bus Read Register Write Data e Register Bus Write y Initialization Done gt User Error gt User Return gt User Command Idle lt User Command Enable PLL i _ User Command Commit External Sample CLK User Command Status External Ref CLK lt User Data 0 RF Filter Control 7 User Data 1 PLL Loop Filter Clock DAC DAC SPI 1 RF LO and Attenuators SPI Enable VCXO Calibration EEPROM Microcontroller J J RF Filters From RF LO gt LO Locked DIO Port 0 Rd Data
38. tional SE DIO data channel i 3 8 GND Ground reference for signals RUF 9 DIO Port 1 1 Bidirectional SE DIO data channel 10 DIO Port 1 2 Bidirectional SE DIO data channel 11 GND Ground reference for signals 12 DIO Port 1 3 Bidirectional SE DIO data channel 13 PFIO Bidirectional SE DIO data channel 14 NC No connect 15 PFI1 Bidirectional SE DIO data channel 16 PFI2 Bidirectional SE DIO data channel 17 GND Ground reference for signals 18 5 V 5 V power 10 mA maximum 19 PFI3 Bidirectional SE DIO data channel Caution The AUX I O connector accepts a standard third party HDMI cable but the AUX I O port is not an HDMI interface Do not connect the AUX I O port on the NI 5793 to the HDMI port of another device NI is not liable for any damage resulting from such signal connections NI 5793R User Manual and Specifications National Instruments 7 Block Diagram The following figure shows the NI 5793 block diagram Figure 3 NI 5793 Block Diagram LO OUT ADF 4351 Synthesizer LO TX LO Filter Bank TI DAC3482 al A on 16 Bit Wik e xy eH L 204 MHz LPF 31 75 dB Maximum 90 TX OUT 0 25 dB Step 0 TI DAC3482 HHAH Samii lt v 16 Bit 4 4 GHz TX RF 204 MHz LPF LPF Filter Bank ae 44 MHz HPF The following figure shows the connections between the NI 5793 and
39. to support your target a Specify the center frequency in the LO Frequency Hz control b On the block diagram right click the Open FPGA VI Reference PXI 7966R function and select Configure Open FPGA VI Reference c Inthe Configure Open FPGA VI Reference dialog box click the Browse button next to the Bitfile button d In the Select Bitfile dialog box that opens select the bitfile for your desired target The bitfile name is based on the adapter module example type and FPGA module e Click the Select button f Click OK in the Configure Open FPGA VI Reference dialog box g Save the VI 7 On the front panel in the RIO Device pull down menu select an NI 5793 resource that corresponds with the target configured in step 6 8 Configure your measurement a Specify the center frequency in the LO Frequency Hz control b Specify the output power in the Output Power control c Specify the sample rate in the Sample Rate S s control NI 5793R User Manual and Specifications National Instruments 13 10 11 12 d Specify the tone frequency to generate in the Tone Frequency Hz control Click the Run button to run the VI The VI generates a tone frequency offset from the specified LO frequency You need an external measurement device to acquire this signal Click the STOP button to stop the VI Close the VI Creating a LabVIEW Project and Running a VI on an FPGA Target This section explains how to set up yo
40. ur target and create an FPGA VI and host VI for data communication This section focuses on proper project configuration proper CLIP configuration and how to access 5793 I O nodes For more detailed information about acquiring data on your NI 5793R refer to the streaming example available in Creating a Project 1 2 3 4 5 6 Launch LabVIEW or if LabVIEW is already running select File Create Project In the Create Project dialog box select LabVIEW FPGA Project and click Finish Select FlexRIO on My Computer and click Next Either discover a LabVIEW FPGA target in your system or create a new system and specify an FPGA target for which to construct a project Click Finish in the Project Preview dialog box Click File Save and specify a name for the project Creating an FPGA Target VI 1 2 3 4 5 10 11 In the Project Explorer window expand FPGA Target Right click FPGA Target and select New FPGA Base Clock Right click IO Module in the Project Explorer window and select Properties Select Enable IO Module Select the NI 5793 from the IO Module list The available CLIP for the NI 5793 is displayed in the Component Level IP pane Select NI 5793 in the Name list of the Component Level IP pane Click OK Select File Open and select lt labview gt instr lib ni579x config v1 FPGA Public ni579x Config FPGA Template vi Select File Save As Select Copy Open Additional Copy and check Add Copy to
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