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PPCBug Diagnostics Manual

1. VGA543X EXIN Extended Registers Running PASSED If the test fails then the display appears as follows el VGA543X EXIN Extended Registers Running FAILE VGA543X EXTN Test Failure Data Read register Index Register loaded with Value read Expected 3 113 Test Descriptions GRPH Graphics Controller Registers Command Input PPC1 Diag gt VGA543X GRPH Description This test verifies the correct operation of the VGA Graphics Controller Registers The test proceeds as follows 1 Each Graphics Controller Register is initialized with one of 256 possible values with reserved bits being masked off to a value of zero 2 The Graphics Controller Register is read back to verify that the data that was written to the register in step 1 was written correctly Response Messages After the command has been issued the following line is printed VGA543X GRPH Graphics Control Registers Running gt If all parts of the test are completed correctly then the test passes VGA543X GRPH Graphics Control Registers Running PASSED If the test fails then the display appears as follows VGA543X GRPH Graphics Control Registers Running FAILED VGA543X GRPH Test Failure Data error message If the error is in one of the index registers then error message is Index register Value read Expected Otherwise error
2. If all parts of the test are completed correctly then the test passes D EC XRE GA Extended PCI register Access Running PASSED If any part of the test fails then the display appears as follows D EC XRE GA Extended PCI register Access Running FAILED DE C XREGA Test Failure Data error message Refer to the section DEC Error Messages for a list of the error messages and their meaning DEC Error Messages DEC Ethernet Controller Tests The DEC test group error messages generally take the following form DEC CLOAD Continuous Load DEC CLOAD Test Failure Data Ethernet packet data mismatch Running FAILED Iter nnnn Element nnn Value sent xxxx Value returned xxxx The first line of the test failure data identifies what type of failure occurred The following line provides additional information about the failure Table 3 4 DEC Error Messages Error Message Initialization Error Init Block Address mismatch Symptom or Cause Init Block address given to controller was not properly stored after initialization Initialization Error Transmit Ring Size mismatch Controller did not properly detect Transmit Descriptor Ring size after initialization Initialization Error Receive Ring Size mismatch Controller did not properly detect Recei
3. You can use the CF command to select the ports to be tested This example uses the CF command to select port 0 skipping 1 Example PPCl Diag CF UART External Loopback Port Mask 00000002 01 Bit 0 selects port 0 Bit 1 selects port 1 etc see note below The next parameter is the port selection mask This mask is used during testing to identify which ports are to be tested The default is to test every port except the console port The External Loopback Port Mask is used for the LPBKE test suite Test Descriptions BAUD Baud Rates Command Input PPCl Diag UART BAUD Description This test transmits 18 characters at various baud rates The data is received and compared If any protocol errors are created or the data is not correct when received the test failed The bauds tested are 300 9600 1200 19200 2400 38400 Response Messages After the command has been issued the following line is printed UART BAUD Baud RatesS 6 Running If all parts of the test are completed correctly then the test passes UART BAUD Baud Baies Running PASSED If any part of the test fails then the display appears as follows UART BAUD Baud Baies e Running FAILED UART BAUD Test Failure Data error message Refer to the section LLART Error Messages for a list of the error messages and their meaning UART Serial Input Output Tests IRQ Interrupt Reque
4. Diagnostic Utilities Example PPC1 Diag gt le scc SCC ACCESS Device Register Access Running gt PASSED SCC IRQ Interrupt Request Running FAILED SCC IRQ Test Failure Data error message SCC D IRQ Interrupt Request Running FAILE SCC IRQ Test Failure Data error message SCC IRQ Interrupt Request Running BREAK Break Detected PPCl Diag LF Line Feed Suppression Mode Entering LF on a command line sets the internal line feed mode flag of the diagnostic monitor The duration of the LF command is the life of the user command line in which it appears The default state of the internal line feed mode flag is clear which causes the executing test title status line s to be terminated with a line feed character scrolled The line feed mode flag is normally used by the diagnostic monitor when executing a System Mode self test Although rarely invoked as a user command the LF command is available to the diagnostic user Example PPC1 Diag gt LF RAM RAM ADR Addressability Running PASSED display of subsequent RAM test messages overwrite this line PPCl Diag Utilities LN Loop Non Verbose Mode The LN command modifies the way a failed test is endlessly repeated The LN command has no effect until a test failure occurs at which time if the LN command has
5. L2CACHE Level 2 Cache Tests WEBEL Write Back w Flush Command Input PPCl Diag l2cache wbfl Description This test performs a write read test on the L2 Cache This test verifies that the device can be both accessed and that the L2 Cache Flush control works The test flow is as follows Turn off the cache Write an incrementing pattern to memory and verify that the pattern is in memory Turn on the cache with WriteBack Write a decrementing pattern to the cache Turn off the cache Verify that the incrementing pattern is still in memory Turn on the cache with WriteBack Flush the cache which should flush the cache contents to memory Turn off the cache Verify that the decrementing pattern is in memory Response Messages After the command has been issued the following line is printed L2CACHE WBFL L2 Cache WriteBack w Flush Running If all parts of the test are completed correctly then the test passes L2CACHE WBFL L2 Cache WriteBack w Flush Running gt PASSED If any part of the test fails then the display appears as follows L2CACHE WBFL L2 Cache WriteBack w Flush Running FAILED L2CACHE WBFL Test Failure Data error message Refer to the section L2CACHE Error Messages for a list of the error messages and their meaning Test Descriptions WBINV Write Back w Invalidate Command Input PPC1 Diag gt l2cache wbinv Description This test per
6. PASSED If the test fails then the display appears as follows RTC CLK MK48Txx Real Time Clock Running FAILED RIC CLK Test Failure Data error message Here error message is one of the following If the check for low battery fails RIC low battery The RTC time registers are configured for constant updating by the clock internal counters The seconds register is read initially and then monitored read to verify that the seconds value changes A predetermined number of reads are made of the seconds register RTC MK48Txx Timekeeping Tests If the predetermined number of reads are made before the seconds register changed the following message is printed RTC not running The RTC time registers are configured for reading A pre determined number of MPU do nothing loops are executed If the seconds register changes before the full count of MPU loops is executed the following message is printed RTC did not freeze for reading If the real time clock registers fail the data pattern test Data Miscompare Error Address Expected Actual The following message indicates a programming error and should never be seen by the diagnostics user WARNING Real Time Clock NOT compensated for test delay Test Descriptions RAM Battery Backed Up RAM Command Input PPCl Diag rtc ram Description This test performs a data test on each BB
7. Running FAILED VGA543x BLT Test Failure Data Memory compare error in bitblt test byte is__ should be_ 3 110 VGA543X Video Diagnostics Tests CRTC CRT Controller Registers Command Input PPC1 Diag gt VGA543X CRTC Description This test verifies the correct operation of the VGA CRT Controller Registers The test proceeds as follows 1 Each CRT Controller Register is initialized with one of 256 possible values with reserved bits being masked off to a value of zero 2 The CRT Controller Register is read back to verify that the data that was written to the register in step 1 was written correctly Response Messages After the command has been issued the following line is printed VGA543X CR If all parts C CRT Controller Registers Running of the test are completed correctly then the test passes VGA543X CR If the test f C CRT Controller Registers Running PASSED ails then the display appears as follows VGA543X CRIC CRT Controller Registers Running FAILED VGA543X CRIC Test Failure Data Data Register Index Value Read Expected 3 111 Test Descriptions DSTATE DAC State Register Command Input PPCl Diag vga543x dstate Description Test the DAC State Register This test verifies that the VGA controller changes when set to the various mode states Response Messages After the command has been
8. FAILED UART LPBK Test Failure Data error message Refer to the section LLART Error Messages for a list of the error messages and their meaning UART Serial Input Output Tests LPBKE External Loopback Command Input PPC1 Diag gt UART lpbke Description This test transmits 18 characters at 9600 baud The data is received and compared If any protocol errors are created or the data is not correct when received the test failed This test also verifies that modem control lines may be asserted and deasserted and that these signals are received back by the UART This test does require an external loopback connector to be installed For this test the following connections need to be made in the loopback connector TxD connected to RxD DTR connected to DCD and DSR RTS connected to CTS and RI Response Messages After the command has been issued the following line is printed UART LPBKE External Loopback Running If all parts of the test are completed correctly then the test passes UART LPBKE External Loopback Running PASSED If any part of the test fails then the display appears as follows UAR LPBKE External Loopback Running gt FAILED UART LPBKE Test Failure Data error message Refer to the section LLART Error Messages for a list of the error messages and their meaning Test Descrip
9. Running If all parts of the test are completed correctly then the test passes SCC ILPBCK Internal Loopback Running PASSED If any part of the test fails then the display appears as follows SCC ILPBCK Internal Loopback Running FAILED SCC ILPBCK Test Failure Data error message Refer to the section SCC Error Messages for a list of the error messages and their meaning 3 103 Test Descriptions IRQ Interrupt Request Command Input PPCl Diag scc irq Description This test verifies that the Z85230 can generate interrupts to the local processor This is done using the baud rate zero counter interrupt from the Z85230 Response Messages After the command has been issued the following line is printed SCC IRQ Interrupt Request Running If all parts of the test are completed correctly then the test passes SCC IRQ Interrupt Request Running PASSED If any part of the test fails then the display appears as follows SCC IRQ Interrupt Request Running FAILED SCC IRQ Test Failure Data error message Refer to the section SCC Error Messages for a list of the error messages and their meaning 3 104 SCC Serial Communication Controller Z85230 Tests MDMC Modem Control Command Input PPCl Diag SCC MDMC Description This test verifies that the Z85230 can negate asser
10. The test block is the memory range specified by the RAM test group configuration parameters The test proceeds as follows 1 A random pattern is written throughout the test block 2 The random pattern complemented is written throughout the test block 3 The complemented pattern is verified 4 The random pattern is rewritten throughout the test block 5 The random pattern is verified This test is coded to use only 32 bit data entities Each time this test is executed the random seed in the RAM test group configuration parameters is post incremented by 1 Response Messages After the command has been issued the following line is printed RAI RADM Random Bdtas x eee err Running If all parts of the test are completed correctly then the test passes RAI RNDM Random Data Running PASSED If the test fails then the display appears as follows RAI RNDM Random Data Running FAILE D RAM RNDM Test Failure Data Data Miscompare Error Address Expected Actual Test Descriptions RTC MK48Txx Timekeeping Tests These tests check the BBRAM and clock portions of the MK48Txx Real Time Clock RTC chips Entering RTC without parameters causes all RTC tests to execute in the order shown in the table below except as noted To run an individual test add that test name to the RTC command The individual tests are described in alphabetical order on t
11. bit not set Address Expected __ Actual Interrupt Status DIP bit not set Address Expected __ Actual SCSI Status Zero Reg set during single step Address Expected __ Actual Test Timeout during INTI Address Expected __ Actual SIR not detected during INTERRUPT SCRIPTS Test ERRUPT SCRIPTs Test Reg not initially clear Address Expected __ Actual Address Expected _ Actual Test Timeout during JUMP SCRIPTs Test Address Expected __ Actual SIR not detected during JUMP SCRIPTs Test Address Expected Ac tua Jump if True and Compare True Jump not taken wr Jump if rue and Compare False Jump taken Jump if False and Compare True Jump taken wr Jump if rue and Compare False Jump not taken Test Timeout during Memory Move SCRIPTs Test Address Expected __ Actual _ SIR not detected during Memory Move SCRIPTs Test Address Expected _ Actual __ 3 57 Test Descriptions SFIFO SCSI FIFO Command Input PPCl Diag ncr sfifo Description This procedure tests the basic ability to write data into the SCSI FIFO and retrieve it in the same order as written The SCSI FIFO is checked for an empty condition following a software reset then the SFWR bit is set and verified The FIFO is then filled with 8 bytes of data veri
12. eese Running PASSED If any failures occur the following is displayed more descriptive text then follows 48536 LNK Linked Counter eese Running FAILED 28536 LNK Test Failure Data error message If the test fails because terminal count does not generate an interrupt request within a reasonable amount of time the following message is displayed No Terminal Count occurred with in time limit 3 125 Test Descriptions REG Register Command Input PPCl Diag z8536 reg Description This test verifies that all of the Z8536 registers can be written and read Data patterns verify that every read write bit can be modified Response Messages After the command has been issued the following line is printed 29530 REGS REGLUSCESL i 2e ente NEEN Running If all parts of the test are completed correctly then the test passes 28996 REG Register e ree eee ss Running PASSED If any failures occur the following is displayed more descriptive text then follows 28536 REG Registers iesosee lk wr teen 28536 REG Test Failure Data error message D Running FAILE If the test fails because the pattern written doesn t match the data read back from the Z8536 register the following message is displayed Register xxx Miscompare Error Address Expected _ Actual _ 3 126 Related Documentation Moto
13. for mber of bytes from the source address to the destination address Response Messages After the command has been issued the following line is printed NCR SCRIPTS NCR 53C8xx SCRIPTs Processor Running If all parts of the test are completed correctly then the test passes NCR SCRIPTS NCR 53C8xx SCRIPTs Processor Running gt PASSED If any part of the test fails then the display appears as follows NCR SCRIPTS NCR 53C8xx SCRIPTs Processor Running FAIL NCR SCRIPTS Test Failure Data error message Here error message is one of the following Test Initialization Error Not Enough Memory Need Actual Test Initialization Error Memory Move Byte Count to Large Max 00ffffff Requested l est Initialization Error Test Memory Base Address Not 32 Bit Aligned SCSI Interrupt Enable Reg not initially clear Address Expected Actual __ t DMA Interrupt Enable Reg not initially clear Address Expected Actual __ t ED 3 56 NCR 53C8xx SCSI I O Processor Tests SCSI Status Zero Reg not initially clear Address Expected __ Actual DMA Status Reg not initially clear Address Expected __ Actual Interrupt Status Reg not initially clear Address Expected __ Actual SCSI First Byte Received SCSI First Byte Received Reg not set Address Expected __ Actual DMA Status SSI
14. D DI DI D EC CLOAD Con If all parts of EC CLOAD Con If any part of EC CLOAD Con tinuous I the test tinuous I Running are completed correctly then the test passes Running PASSI the test fails then the display appears as tinuous I error message EC ClOAD Test Failure Data Running FAILI ED follows ED Refer to the section DEC Error Messages for a list of the error messages and their meaning 3 7 Test Descriptions CNCTR Connector Command Input PPCl Diag dec cnctr Description This test verifies that the data path through the external AUI or TP twisted pair connection is functional by transmitting and receiving packets and comparing the data This test requires the presence of an external loopback plug for AUI or TP Note Itis recommended that the board under test not be connected to a live network while this test is running The suggested loopback setup for AUI is an AUI to thinnet transceiver attached to a BNC tee with terminators on each arm of the tee For TP setup an external shunt needs to be put in the TP socket it cannot be connected to a live network Response Messages After the command has been issued the following line is printed DEC CNGIR CONMECEOE ae diastase ater niet ag Running If all parts of the test are completed correctly then the test passes DEG CNET
15. Transmit of Ethernet Packet Failed Underflow Transmitter truncated a error UFLO message due to data unavailability Transmit of Ethernet Packet Failed Excessiv IEEE ANSI 802 3 defined Deferral EXDEF excessive deferral of transmitted packet Receive of Ethernet Packet Failed Invalid Packet Checksum vs Data is invalid indicating bad transmission of packet FRAM t Packet Failed Receive of Ethern Framing Error Some bits were missing on an incoming byte in a frame condition t Packet Failed Overflow Receive of Ethern OFLO FIFO unable to store incoming packet usually because packet is too large to fit in buffer BUFF t Packet Failed Receive of Ethern Buffer error Buffer is not available to receive incoming frame usually because ownership has not been given back to controller 3 17 Test Descriptions Table 3 4 DEC Error Messages Continued Error M essage Time out waiting for Interrupt Symptom or Cause An expected interrupt either from Initialization Transmit or Receive was never received indicating some other problem has occurred Memory Error interrupt encountered MERR Interrupt that occurs when the controller cannot access the memory bus Time Out interrupt ncountered BABL Interrupt indicating that transmitter has taken too long to transmit a frame Collis
16. 0 and 1 Response Messages After the command has been issued the following line is printed RAM ADR Addressability Running If all parts of the test are completed correctly then the test passes RAM ADR Addressability Running PASSED 3 73 Test Descriptions If the test fails then the display appears as follows RAM ADR Addressability Running FAILED RAM ADR Test Failure Data Data Miscompare Error Address Expected Actual 3 74 RAM Local RAM Tests ALTS Alternating Ones Zeros Command Input PPCl Diag RAM ALTS Description This test verifies addressing of memory in the range specified by the configuration parameters for the RAM test group Addressing errors are sought by using a memory locations address as the data for that location This test is coded to use only 32 bit data entities The test proceeds as follows 1 Location n is written with data of all bits 0 2 The next location 1 4 is written with all bits 1 8 Steps 1 and 2 are repeated throughout the specified memory range 4 The memory is read and verified for the correct data pattern s and any errors are reported Response Messages After the command has been issued the following line is printed RAM ALTS Alternating Ones Zeroes Running If all parts of the test are completed correctly then the test passes R
17. DE 2 4 debugger directory 1 2 prompt 1 2 DEC error messages 3 15 DEC Ethernet Controller Tests 3 5 DEC21x40 error messages 3 15 decimal number 4 DEM 2 4 description of PPCBug 1 2 Device Access ACC1 3 44 Device Register Access ACCESS 3 98 Device Register Access REGA 3 66 DFIFO 3 48 diagnostics directory 1 2 facilities 1 3 firmware 2 1 prompt 1 2 test groups 3 1 utilities 2 1 directories 1 3 directories switching 1 3 2 13 Disable Updating DISUPD 3 35 Display Error Counters DE 2 4 Display Error Messages DEM 2 4 Display Pass Count DP 2 5 Display Revise Self Test Mask MASK 2 11 DISUPD 3 35 DMA Receive Transmit DMA 3 100 DMA FIFO DFIFO 3 48 DP 2 5 DSTATE 3 112 E electro magnetic interference 6 ELPBCK 3 102 EMI protection 6 Enable Updating ENUPD 3 36 ENUPD 3 36 ERREN 3 9 error counters 2 4 2 15 error detection 3 81 error messages accumulate 2 2 buffer 2 2 clear 2 3 DEC21x40 3 15 display 2 4 KBD8730x 3 30 L2CACHE 3 42 PCIBUS 3 71 SCC 3 42 3 106 UART 3 67 Ethernet Controller Tests DEC21x40 3 5 examples of command entry 1 4 Extended PCI Register Access XREGA 3 14 Extended Registers EXTN 3 113 External Loopback ELPBCK 3 102 External Loopback LPBKE 3 65 EXTN 3 113 G general commands 2 1 Generic PCI PMC Slot Tests PCIBUS 3 69 Graphics Controller Register 3 115 Graphics Controller Registers GRPH 3 114 graphics tests 3 108 GRPH 3 114 H h
18. Numerics 53C8xx SCSI I O Processor Tests NCR 3 43 A abbreviations acronyms and terms to know GL 1 ACC1 3 44 ACC2 3 46 ACCESS 3 98 Address and Data Parity Error status 3 9 addressing memory 3 73 ADR 3 73 3 89 AEM 2 2 ALARM 3 91 ALARM interrupt ALARM 3 91 Alternating Ones Zeros ALTS 3 75 ALTS 3 75 Append Error Messages Mode AEM 2 2 assertion 4 asterisk 4 ATTR 3 109 Attribute Register ATTR 3 109 AUI connection 3 8 B Battery Backed Up RAM RAM 3 94 BAUD 3 62 Baud Rates BAUD 3 62 Baud Rates BAUDS 3 99 BAUDS 3 99 BBRAM addressing ADR 3 89 binary number 4 Index Bit Blitter BLT 3 110 Bit Toggle BTOG 3 76 Bit Toggle ERREN PERREN SERREN 3 9 BLT 3 110 BTOG 3 76 byte 4 C CEM 2 3 CF 2 3 Chip Initialization CINIT 3 6 CINIT 3 6 CL1283 parallel Interface Tests 3 3 Clear Zero Error Counters ZE 2 15 Clear Error Messages CEM 2 3 CLK 3 92 CLOAD 3 7 clock function real time 3 92 CNCTR 3 8 CNT 3 123 CODE 3 78 Code Execution Copy CODE 3 78 Color Palette PAL 3 116 command entry examples 1 3 commands root level 2 1 configuration parameters 2 3 Connector CNCTR 3 8 Continuous Load CLOAD 3 7 controller Cirrus Logic 3 117 conventions 4 Counter CNT 3 123 Counter Timer Tests 28536 3 122 IN 15 lt moz Index CRT Controller Registers CRTC 3 111 CRTC 3 111 D DAC State Register DSTATE 3 112 Data Patterns PATS 3 80
19. Random Data RNDM 3 87 Real Time Clock Function CLK 3 92 Receive Transmit DMA DMA 3 100 REF 3 85 REG 3 4 3 22 3 60 3 70 3 126 REGA 3 12 3 66 Register REG 3 4 3 22 3 60 3 126 Register Access ACC2 3 46 related documentation A 1 related specifications A 8 restart mode 3 2 RNDM 3 87 root level command examples 1 4 root level commands 2 1 RTC MK48Txx Timekeeping Tests 3 88 S safety precaution 5 SCC Serial Communication Controller Z85230 Tests 3 96 SCC error messages 3 106 scope 2 1 IN 18 SCRIPTS 3 55 SCRIPTS Processor SCRIPTs 3 55 SCSI FIFO SFIFO 3 58 SCSI I O Processor Tests NCR 3 43 SD 1 3 2 13 SE 2 13 Self Test ST 2 14 Self Test Mask 2 11 SEQR 3 119 Sequencer Controller Register 3 119 Sequencer Registers SEOR 3 119 Serial Communication Controller Z85230 Tests SCC 3 96 Serial Input Output Tests UART 3 61 SERREN 3 9 servicing 5 SFIFO 3 58 Single Packet Send Receive SPACK 3 13 Single Step Mode 3 55 SIZE 3 38 SPACK 3 13 ST 2 14 Stop On Error Mode SE 2 13 subcommands 1 3 subdirectory level command examples 1 4 switch directories 1 3 Switch Directories SD 2 13 System Mode 2 10 T terminology 4 test descriptions 3 1 test directory 2 11 test failure 2 11 Test Group Configuration Parameters Editor CF 2 3 Timekeeper 3 94 U UART Serial Input Output Tests 3 61 UART error messages 3 67 uppercase 2 2 3 2 utilit
20. Sta DMA Stat trol INT bit will not clear Expected _ Actual _ Expected __ Actual _ tor type tus Expected __ Actual __ tor Expected __ Actual __ te IRQ Level _ VBR _ tus Expec Interrupt us Expec Unexpected Ve ted Actual Senf Sieg ted _ Actual ctor taken t Enable Reg will not mask interrupts Status Expected __ Actual __ Vector Expected __ Actual __ State IRQ Level _ VBR _ Interrupt did not occur Status Expected __ Actual __ Vector Expected __ Actual __ State IRQ Level _ VBR _ Interrupt Sta Status Expec Vector Expec tus bit did not set ted _ Actual ted __ Actual State IRQ I Interrupt Con Address vel _ VBR _ trol INT bit will not clear Expected __ Actual _ 3 51 Test Descriptions Bus Error Information Address Data Access Size __ Access Type Address Space Code _ Vector Number Unsolicited Exception Program Counter Vector Number Status Register Interrupt Level 3 52 NCR 53C8xx SCSI I O Processor Tests PCI PCI Access Command Input PPCl Diag ncr pci Description This procedure tests the basic ability to access the PCI Configuration register address space for the NCR 53C8xx device It performs a read of the address space and copies it into local memory and checks for bus errors and other catastrophic erro
21. the failure Table 3 7 KBD8730x Error Messages Error Message Buffer Empty Failure during command XX Writing byte XX to controller port 60h Keyboard Controller timed out waiting for Input Symptom or Cause Keyboard controller never became ready to receive command or data byte Possible problem with keyboard controller embedded firmware Failure during Keyboard command XX Time out possible device not present Failure of keyboard controller or keyboard device to send back a byte as a result of a command given to the keyboard device Indicates problem with keyboard controller embedded firmware or the keyboard device itself Failure during Mouse command XX Time out possible device not present Failure of keyboard controller or mouse device to send back a byte as a result of a command given to the mouse device Indicates problem with keyboard controller embedded firmware or the mouse device itself 3 30 KBD8730x Keyboard Controller Tests Table 3 7 KBD8730x Error Messages Continued Error Message Symptom or Cause Failure during command XX Failure of keyboard Keyboard Controller timed out waiting for Output controller to send back a Buffer Full byte as a result of a command given to the keyboard controller itself Indicates a possible problem with the keyboard controller embedded firmware or hardware Controller Command mismatch error Command byte read
22. 3 Related Specifications Continued Document Title and Source PowerPC Microprocessor Common Hardware Reference Platform A System Architecture CHRP Version 1 0 Literature Distribution Center for Motorola Telephone 800 441 2447 FAX 602 994 6430 or 303 675 2150 E mail ldcformotorola hibbertco com OR APDA Apple Computer Inc P O Box 319 Buffalo NY 14207 Telephone 800 282 2732 FAX 716 871 6511 OR IBM 1580 Route 52 Bldg 504 Hopewell Junction NY 12533 6531 Telephone 800 PowerPC OR Morgan Kaufmann Publishers Inc 340 Pine Street Sixth Floor San Francisco CA 94104 3205 USA Telephone 415 392 2665 FAX 415 982 2665 Publication Number TB338 D MPRPPCHRP 01 ISBN 1 55860 394 8 PowerPC Reference Platform PRP Specification Third Edition Version 1 0 Volumes I and II International Business Machines Corporation Power Personal Systems Architecture 11400 Burnet Rd Austin TX 78758 3493 Document Specification Ordering Telephone 1 800 PowerPC Telephone 1 800 769 3772 Telephone 708 296 9332 MPR PPC RPU 02 ATX Specification Version 2 01 created by Intel Corporation available on the World Wide Web through Teleport Internet Services at URL http www teleport com atx index htm Related Specifications Table A 3 Related Specifications Continued with Collision Detection CSMA CD Access Method and Physical Layer Specifications Institute of Electrical a
23. Clock Data line is stuck high low There is a problem with the interface to the mouse device or the mouse device itself One of the data or clock lines is not operating correctly Mouse Interface test failed Invalid test result from controller Indicates a complete failure of the interface test to the mouse device May be a problem with the embedded firmware itself Mouse Read ID failed returning XX should be XX Mouse is sending the wrong ID byte s back indicating wrong device type being used or a problem with the device 3 33 Test Descriptions L2CACHE Level 2 Cache Tests This section describes the individual Level 2 L2 Cache tests Entering L2CACHE without parameters causes all L2CACHE tests to run in the order shown in the table below except as noted To run an individual test add that test name to the LZCACHE command The individual tests are described in alphabetical order on the following pages Table 3 8 L2CACHE Test Group Name Description IWBFL WrieBackw Flush WBINV Write Back w Invalidate WRTHRU WriteThru DISUPD Disable Updating ENUPD Enable Updating PATTERN WriteThru Pattern Executed only when specified SIZE Verify Cache Size 3 34 PPCIDIAA UM1A3 L2CACHE Level 2 Cache Tests DISUPD Disable Updating Command Input PPCl Diag 1l2cache disupd Description This test performs a write read test on the L2 C
24. DIR JCACHE L2 Cache DIR Loop Always Mode Loop Continuous Mode Loop on Error Mode Line Feed Mode Loop Non Verbose Mode Self Test Mask NCR 53C8XX SCSI I O Processor Tests DIR Non Verbose Mode PAR8730X Parallel Interface PC8730x Tests DIR PCIBUS PCI PMC Generic Press RETURN to continue RETURN Figure 2 1 Help Screen Sheet 1 of 2 Utilities Quick Self Test DIR Random Access Memory Tests DIR MK48Txx Timekeeping DIR Serial Communication Controller Z85C230 Tests DIR Stop on Error Mode Self Test DIR Serial Input Output Tests DIR VGA543X VGA Controller GD543X Tests DIR VME2 VME2Chip2 Tests DIR 28536 z8536 Counter Timer Input Output Tests DIR Z Zero Errors ZF Zero Pass Count PPC1 Diag gt Figure 2 1 Help Screen Sheet 2 of 2 To bring up a menu of all the RAM memory tests enter PPC1 Diag gt he ram RAI Random Access Memory Tests DIR ADR Addressability ALTS Alternating Ones Zeroes BTOG Bit Toggle CODE Code Execution Copy ARCH March Address PATS Patterns PED Local Parity Memory Error Detection PERM Permutations QUIK Quick Write Read REF Memory Refresh Test RNDM Random Data PPC1 Diag gt To review a description of an individual test enter the full name PPCl Diag he ram code RAM Random Access Memory Tests DIR CODE Code Executi
25. Error Address Expected __ Actual SCID Register Error Address Expected Actual _ DSA Register Error Address Expected Actual TEMP Register Error Address Expected Actual DMA Next Address Error Address Expected Actual Register Access Error Bus Error Information Address Data Access Size __ Access Type _ Address Space Code _ Vector Number Unsolicited Exception Program Counter Vector Number Status Register Interrupt Level Notes 1 All error message data is displayed as hexadecimal values 2 The Unsolicited Exception information is only displayed if the exception was not a Bus Error 3 Access Size is displayed in bytes 4 Access Type is 0 write or 1 read 3 47 Test Descriptions DFIFO DMA FIFO Command Input PPC1 Diag gt NCR DFIFO Description This procedure tests the basic ability to write data into the DMA FIFO and retrieve it in the same order as written The DMA FIFO is checked for an empty condition following a software reset then the FBL2 bit is set and verified The FIFO is then filled with 16 bytes of data in the four byte lanes verifying the byte lane full or empty with each write Next the FIFO is read verifying the data and the byte lane full or empty with each read If no errors are detected the NCR device is reset otherwise the device is left in the test state Respon
26. Motorola Telephone 800 441 2447 FAX 602 994 6430 or 303 675 2150 E mail ldcformotorola hibbertco com OR IBM Microelectronics Mail Stop A25 862 1 MPR604UMU 01 PowerPC Marketing 1000 River Street Essex Junction Vermont 05452 4299 Telephone 1 800 PowerPC Telephone 1 800 769 3772 FAX 1 800 POWERfax FAX 1 800 769 3732 Document Title and Source PowerPC Microprocessor Family The Programming Environments MPCFPE AD Literature Distribution Center for Motorola Telephone 800 441 2447 FAX 602 994 6430 or 303 675 2150 E mail ldcformotorola hibbertco com OR IBM Microelectronics Mail Stop A25 862 1 MPRPPCFPE 01 PowerPC Marketing 1000 River Street Essex Junction Vermont 05452 4299 Telephone 1 800 PowerPC Telephone 1 800 769 3772 FAX 1 800 POWERfax FAX 1 800 769 3732 MPC2604GA Integrated Secondary Cache for PowerPC Microprocessors MPC2604GA Data Sheets Literature Distribution Center for Motorola Telephone 800 441 2447 FAX 602 994 6430 or 303 675 2150 E mail ldcformotorola hibbertco com A 4 Manufacturers Documents Table A 2 Manufacturers Documents Continued Document Title and Source Alpine VGA Family CL GD543X 4X Technical Reference Manual Fourth Edition Cirrus Logic Inc or nearest Sales Office 3100 West Warren Avenue Fremont California 94538 6423 Telephone 510 623 8300 FAX 510 252 6020 Publication Number 385439 DECchip 21
27. Patterns geeseewe ee pue eee Running PASSED If the test fails then the display appears as follows RAI PATS Patterns a5 sates 9m ops site Running FAILED RAM PATS Test Failure Data Data Miscompare Error Address Expected Actual RAM Local RAM Tests PED Local Parity Memory Error Detection Command Input PPC1 Diag gt RAM PED Description The memory range and address increment is specified by the RAM test directory configuration parameters Refer to CF Test Group Configuration Parameters Editor in Chapter 2 First each memory location to be tested has the data portion verified by writing verifying all zeros and all ones Each memory location to be tested is tested once with parity interrupt disabled and once with parity interrupt enabled Parity checking is enabled and data is written and verified at the test location that causes the parity bit to toggle on and off verifying that the parity bit of memory is good Next data with incorrect parity is written to the test location The data is read and if a parity error exception does occur the fault address is compared to the test address If the addresses are the same the test passed and the test location is incremented until the end of the test range has been reached Response Messages After the command has been issued the following line is printed RAM PED Local Parity Memory Detection
28. RAMs to control the input of the row addresses GL 10 Glossary Raven The PowerPC to PCI local bus bridge chip developed by Motorola for the MVME2600 and MVME3600 series of boards It provides the necessary interface between the PowerPC 60x bus and the PCI bus and acts as interrupt controller Reduced Instruction Set Computer RISC RFI RGB RISC ROM RTC SBC SCSI SCSI 2 Fast Wide serial port SIM SIMM A computer in which the processor s instruction set is limited to constant length instructions that can usually be executed in a single clock cycle Radio Frequency Interference The three separate color signals Red Green and Blue Used with color displays an interface that uses these three color signals as opposed to an interface used with a monochrome display that requires only a single signal Both digital and analog RGB interfaces exist See Reduced Instruction Set Computer RISC Read Only Memory Real Time Clock Single Board Computer Small Computer Systems Interface An industry standard high speed interface primarily used for secondary storage SCSI 1 provides up to 5 Mbps data transfer An improvement over plain SCSI and includes command queuing Fast SCSI provides 10 Mbps data transfer on an 8 bit bus Wide SCSI provides up to 40 Mbps data transfer on a 16 or 32 bit bus A connector that can exchange data with an I O device one bit at a time It may operate synchronously or asynch
29. Running gt If the board under test does not support Parity error detection the test is bypassed RAI PED Local Parity Memory Detection Running BYPASS If all parts of the test are completed correctly then the test passes RAI PED Local Parity Memory Detection Running PASSED If any part of the test fails then the display appears as follows RAI PED Local Parity Memory Detection Running FAILED RAM PED Test Failure Data error message Test Descriptions Here error message is one of the following If a data verification error occurs Data Miscompare Error Address Expected Actual If an unexpected exception such as a parity error being detected as the parity bit was being toggled Unexpected Exception Error Vector Address Under Test If no exception occurred when data with bad parity was read Parity Error Detection Exception Did Not Occur Exception Vector Address Under Test If the exception address was different from that of the test location Fault Address Miscompare Expected Actual 3 82 RAM Local RAM Tests PERM Permutations Command Input PPCl Diag RAM PERM Description This command performs a test which verifies that the memory in the test range can accommodate 8 bit 16 bit and 32 bit writes and reads in any combination The test
30. as thick Ethernet An Ethernet implementation in which the physical medium is a single shielded 50 ohm RG58A U coaxial cable capable of carrying data at 10 Mbps for a length of 185 meters also referred to as AUI or thinnet Also known as thin Ethernet An Ethernet implementation in which the physical medium is an unshielded twisted pair UTP of wires capable of carrying data at 10 Mbps for a maximum distance of 185 meters Also known as twisted pair Ethernet An Ethernet implementation in which the physical medium is an unshielded twisted pair UTP of wires capable of carrying data at 100 Mbps for a maximum distance of 100 meters Also known as fast Ethernet Asynchronous Communications Interface Adapter Advanced Interactive eXecutive IBM version of UNIX The main overall design in which each individual hardware component of the computer system is interrelated The most common uses of this term are 8 bit 16 bit or 32 bit architectural design systems American Standard Code for Information Interchange This is a 7 bit code used to encode alphanumeric information In the IBM compatible world this is expanded to 8 bits to encode a total of 256 alphanumeric and control characters GL 1 2 o0o00r o Glossary ASIC AUI BBRAM bi endian big endian BIOS BitBLT BLT board bpi bps bus cache Application Specific Integrated Circuit Attachment Unit Interface Battery Backed up Random Access Memo
31. been previously encountered in the user command line further printing of the test title and pass fail status is suppressed This is useful for more rapid execution of the failing test i e the LN command contributes to a tighter loop Example PPC1 Diag gt LN RAM ADR RAM ADR RAM ADR Addressability Running PASSED Pass Count 1 Errors This Pass 0 Total Errors 0 RAI ADR Addressability Running PASSED Pass Count 2 Errors This Pass 0 Total Errors 0 RAI ADR Addressability Running PASSED Pass Count 3 Errors This Pass 0 Total Errors 0 RAI ADR Addressability Running BREAK Break Detected PPCl Diag MASK Display Revise Self Test Mask Using MASK with an argument enables disables the specified test from running under self test The argument must be a specific test name If mask is invoked without arguments the current self test mask showing disabled tests is displayed The mask command is a toggle command if the specified test name mask was set it will be reset if it was reset it will be set After the toggle the new self test mask is displayed If the mask command is invoked with an invalid test name or a test directory as opposed to a specific test name an appropriate error message is output Diagnostic Utilities When the mask command is used on a PowerP
32. bri eot R 3 69 Table cT PCIBUS Error Ne eua Silo ads ee E EM DUAE aaa 3 71 Table 3 16 RAM Testen 3 72 Tabi REC Tes TO iio ogebsus pl dor Garda cteddes po tio M Hd 3 88 Table 3 18 SCC Test E 3 96 Table OU SCL Error Mesi 2 oiistibr oM eee cere ere Nee een ere ener rere 3 106 Table 220 VGA MSX Test Steenbergen gem et 3 108 test MER Tes DEOUDS eati te er ener RU FH E Aare E ux i b 3 121 Table 3 22 20000 Test GIOP eeraa aonane a Eni UEM IBEN iG 3 122 xii General Information Introduction This manual describes the complete set of hardware diagnostics included in the PPCBug Debugging Package intended for testing and troubleshooting of Motorola s PowerPC based boards This member of the PPCBug firmware family known as PPCBug diagnostics is implemented on these Motorola PowerPC based products a MVME230x VME Processor Modules MVME260x Single Board Computers MVME360x VME Processor Modules MVME460x VME Dual Processor Modules MTX Embedded ATX Motherboards L UU vo They are collectively referred to in this manual as the PowerPC board or board When necessary to refer to them individually they are called the MVME230x MVME260x MVME360x MVME460x and MTX respectively This introductory chapter includes information about the operation and use of the diagnostics Chapter 2 contains descriptions of the diagnostic utilities Chapter 3 contains descriptions of the diagnostic test routines Before using the PPCBug diag
33. hooked up to the Ethernet port with the exception of the CNCTR test which needs external loopback plugs in the external connector 3 5 Test Descriptions CINIT Chip Initialization Command Input PPCl Diag dec cinit Description This test checks the DEC chip initialization sequence for proper operation while using interrupts and reading the initialization blocks and rings structures used for Ethernet communications Response Messages After the command has been issued the following line is printed DEC CINIT Chip Initra alizationi esasen Running If all parts of the test are completed correctly then the test passes DEC CINIT ChipoInitlalTzaLbloniz 4 vega Running PASSED If any part of the test fails then the display appears as follows DEC CINIT Chip Initialization Running FAILED DEC CINIT Test Failure Data error message Refer to the section DEC Error Messages for a list of the error messages and their meaning CLOAD Continuous Load Command Input PPCl Diag DEC CLOAD Description DEC Ethernet Controller Tests This test verifies that a continuous load can be placed on the controller by transmitting receiving a sequence of packets totalling at least 1 megabyte of throughput comparing the input data with the output data Response Messages After the command has been issued the following line is printed
34. message iS Data register Value read Expected 3 114 VGA543X Video Diagnostics Tests MISC Miscellaneous Register Command Input PPCl Diag VGA543X MISC Description This test verifies the correct operation of the VGA Miscellaneous Control Register The test proceeds as follows 1 Each Graphics Controller Register is initialized with one of 256 possible values with reserved bits being masked off to a value of zero 2 The Graphics Controller Register is read back to verify that the data that was written to the register in step 1 was written correctly Response Messages After the command has been issued the following line is printed VGA543X MISC Miscellaneous Registers Running If all parts of the test are completed correctly then the test passes VGA543X MISC Miscellaneous Registers Running PASSED If the test fails then the display appears as follows el VGA543X MISC Miscellaneous Registers Running FAILE VGA543X MISC Test Failure Data Read Register Write Register Value read Expected 3 115 Test Descriptions PAL Color Palette Command Input PPC1 Diag gt VGA543X PAL Description This test verifies the correct operation of the 256 possible color palette entries Each palette red green and blue entry is verified by checking for the setting of all bits to 1s and 0s Response Messages After the command has been issued t
35. of 525 horizontal lines with the NTSC system One frame consists of two Fields On EGA and VGA a section of circuitry that can provide hardware assist for graphics drawing algorithms by performing logical functions on data written to display memory Hardware Abstraction Layer The lower level hardware interface module of the Windows NT operating system It contains platform specific functionality GL 5 J oooro 2 o0o00r o Glossary hardware HCT 1 0 IBC IDC IDE IEEE interlaced IQ Signals ISA bus ISASIO A computing system is normally spoken of as having two major components hardware and software Hardware is the term used to describe any of the physical embodiments of a computer system with emphasis on the electronic circuits the computer and electromechanical devices peripherals that make up the system Hardware Conformance Test A test used to ensure that both hardware and software conform to the Windows NT interface Input Output PCI ISA Bridge Controller Insulation Displacement Connector Integrated Drive Electronics A disk drive interface standard Also known as ATA Advanced Technology Attachment Institute of Electrical and Electronics Engineers A graphics system in which the even scanlines are refreshed in one vertical cycle field and the odd scanlines are refreshed in another vertical cycle The advantage is that the video bandwidth is roughly half that requi
36. oooro 2 o0o00r o Glossary PowerPC 603 PowerPC 604 The second implementation of the PowerPC family of microprocessors This CPU incorporates a memory management unit with a 64 entry buffer and an 8KB instruction and data cache It provides a selectable 32 bit or 64 bit data bus and a separate 32 bit address bus PowerPC 603 is used by Motorola Inc under license from IBM The third implementation of the PowerPC family of microprocessors currently under development PowerPC 604 is used by Motorola Inc under license from IBM PowerPC Reference Platform PRP A specification published by the IBM Power Personal Systems Division which defines the devices interfaces and data formats that make up a PRP compliant system using a PowerPC processor PowerStack RISC PC System Board PRP PRP compliant PRP Spec PROM PS 2 QFP RAM RAS A PowerPC based computer board platform developed by the Motorola Computer Group It supports Microsoft s Windows NT and IBM s AIX operating systems See PowerPC Reference Platform PRP See PowerPC Reference Platform PRP See PowerPC Reference Platform PRP Programmable Read Only Memory Personal System 2 IBM Quad Flat Package Random Access Memory The temporary memory that a computer uses to hold the instructions and data currently being worked with All data in RAM is lost when the computer is turned off Row Address Strobe A clock signal used in dynamic
37. read indirectly through the RAP index register and CSR BCR data registers This test verifies that the registers can be accessed and that the data paths to the device are functioning Response Messages After the command has been issued the following line is printed DEC IOR I O Resource Register Access Running DEC IOR I O Resource Register Access Running FAILED DEC IOR Test Failure Data error message Refer to the section DEC Error Messages for a list of the error messages and their meaning Test Descriptions REGA PCI Header Register Access Command Input PPCl Diag DEC REGA Description This test performs a read test on the Vendor ID and the Device ID registers in the DEC PCI header space and verifies that they contain the correct values This test verifies that the registers can be accessed and that the data paths to the device are functioning Response Messages After the command has been issued the following line is printed DEC REGA PCI Register Access Running If all parts of the test are completed correctly then the test passes DEC REGA PCI Register Access Running PASSED If any part of the test fails then the display appears as follows DEC REGA PCI Register Access Running FAILED DEC REGA Test Failure Data error message Refer to t
38. shown in the following table To run an individual test add that test name to the Z8536 command The individual tests are described in alphabetical order on the following pages Table 3 22 Z8536 Test Group Name Description CNT Counter LNK Linked Counter IRQ Interrupt REG Register 3 122 Z8536 Counter Timer Tests CNT Counter Command Input PPC1 Diag gt z8536 cnt Description This test verifies the functionality of the counter in the Z8536 chip Response Messages After the command has been issued the following line is printed 2895306 ONE COUlter u1zu 9e ecd tech eri Running If all parts of the test are completed correctly then the test passes 285306 CENT Create EE ee IC eS Running PASSED If any failures occur the following is displayed more descriptive text then follows 28536 CNT COUNEST eebe dE ede eeu Ae Running FAILED 28536 CNT Test Failure Data error message If the test fails because one of the counters does not generate an interrupt request in the correct time frame the following message is displayed 28536 Timer A B C No Terminal Count Counter has not generated a Terminal Count IRQ in allotted time 3 123 Test Descriptions IRQ Interrupt Command Input PPC1 Diag gt Z8536 IRQ Description This test verifies that the Z8536 can generate interrupts Response Messages After the command has been issued t
39. the command has been issued the following line is printed L2CACHE PATTERN L2 Cache WriteThru Pattern Running If all parts of the test are completed correctly then the test passes L2CACHE PATTERN L2 Cache WriteThru Pattern Running PASSED If any part of the test fails then the display appears as follows L2CACHE PATTERN L2 Cache WriteThru Pattern Running FAILED L2CACHE PATTERN Test Failure Data error message Refer to the section L2CACHE Error Messages for a list of the error messages and their meaning Test Descriptions SIZE Verify Cache Size Command Input PPCl Diag l2cache size Description The main objective of this test is to verify the size of the L2 Cache as indicated by the CPU Type Register An error is reported if the size is incorrect Response Messages After the command has been issued the following line is printed SIZE Verify Cache Size Running If all parts of the test are completed correctly then the test passes SIZE Verify Cache Size Running PASSED If any part of the test fails then the display appears as follows SIZE Verify Cache Size Running FAILED L2CACHE SIZE Test Failure Data error message Refer to the section L2CACHE Error Messages for a list of the error messages and their meaning
40. then the display appears as follows LAI RTC Al kel K48Txx Alarm Interupt Running FAILED RTC ALARM Test Failure Data error message Here error message is one of the following If the expected interrupt IRQ8 did not occur error message is Interrupt failed to occur Int Stat Reg xx hex where xx is the contents in hex of the Interrupt Status Register of the PCI to_ISA Bridge If an interrupt other than IRQ8 occurred error message is Spurious interrupt occurred instead of IRQ8 Int Stat Reg xx hex If interrupt IROS did occur but the AF Alarm Flag was not set error message is AF Alarm Flag bit was not set Test Descriptions CLK Real Time Clock Function Command Input PPCl Diag RTC CLK Description This test verifies the functionality of the Real Time Clock RTC This test does not check clock accuracy This test requires approximately nine seconds to run At the conclusion of the test nine seconds are added to the clock time to compensate for the test delay Because the clock can only be set to the nearest second this test may induce one second of error into the clock time Response Messages After the command has been issued the following line is printed RTC CLK MK48Txx Real Time Clock Running If all parts of the test are completed correctly then the test passes RTC CLK MK48Txx Real Time Clock Running
41. 0 272 9959 Publication Number PC87308VUL PC16550 UART National Semiconductor Corporation Customer Support Center or nearest Sales Office 2900 Semiconductor Drive P O Box 58090 Santa Clara California 95052 8090 Telephone 1 800 272 9959 PC16550DV MK48T59 CMOS 8K x 8 TIMEKEEPER SRAM Data Sheet SGS Thomson Microelectronics Group Faxback Document on Demand system Carrollton TX Telephone 972 4667 7788 M48T59 SYM 53CXX was NCR 53C8XX Family PCI SCSI I O Processors Programming Guide Symbios Logic Inc 1731 Technology Drive suite 600 San Jose CA 95110 Telephone 408 441 1080 Hotline 1 800 334 5454 T72961I1 SCC Serial Communications Controller User s Manual for Z85230 and other Zilog parts Zilog Inc 210 East Hacienda Ave mail stop C1 0 Campbell California 95008 6600 Telephone 408 370 8016 FAX 408 370 8056 DC 8293 02 Manufacturers Documents Table A 2 Manufacturers Documents Continued Document Title and Source Z8536 CIO Counter Timer and Parallel I O Unit Product Specification and User s Manual in Z8000 Family of Products Data Book Zilog Inc 210 East Hacienda Ave mail stop C1 0 Campbell California 95008 6600 Telephone 408 370 8016 FAX 408 370 8056 Publication Number DC 8319 00 W83C553 Enhanced System I O Controller with PCI Arbiter PIB Winbond Electronics Corporation Winbond Systems Laborato
42. 040 Ethernet LAN Controller for PCI Hardware Reference Manual Digital Equipment Corporation Maynard Massachusetts DECchip Information Line Telephone United States and Canada 1 800 332 2717 TTY United States only 1 800 332 2515 Telephone outside North America 1 508 568 6868 EC N0752 72 DECchip 21140 PCI Fast Ethernet LAN Controller Hardware Reference Manual Digital Equipment Corporation Maynard Massachusetts DECchip Information Line Telephone United States and Canada 1 800 332 2717 TTY United States only 1 800 332 2515 Telephone outside North America 1 508 568 6868 EC QCOCA TE PC87303VUL Super I O Sidewinder Lite Floppy Disk Controller Keyboard Controller Real Time Clock Dual UARTs IEEE 1284 Parallel Port and IDE Interface National Semiconductor Corporation Customer Support Center or nearest Sales Office 2900 Semiconductor Drive P O Box 58090 Santa Clara California 95052 8090 Telephone 1 800 272 9959 PC87303VUL A Related Documentation Table A 2 Manufacturers Documents Continued Document Title and Source PC87308VUL Super I OIM Enhanced Sidewinder Lite Floppy Disk Controller Keyboard Controller Real Time Clock Dual UARTs IEEE 1284 Parallel Port and IDE Interface National Semiconductor Corporation Customer Support Center or nearest Sales Office 2900 Semiconductor Drive P O Box 58090 Santa Clara California 95052 8090 Telephone 1 80
43. 17 PELM E 3 118 SEUR Sequencer Kee ocsocciriar iride bonne nro I URORAROR CURE 3 119 Ka Ee 3 120 VIE VME Interface ASIC Tests 4 5 cv oap pe rri vere RE Do RE EEG Gp kA Ces 3 121 Z836 Counter imer Dessau eben P du Fro AAAA 3 122 E CR ET Ga ui eM Menu PED ice ME MI 3 123 Herd gm 3 124 EINE Egger eee oe c e id 3 125 Kb 040 3 126 Motorola Computer Group Lie DER acie nce sene peti been A 1 Manutacturers Docurmenits euis terit bakia lason ia XUI Rege ka gk RE A 3 Related Speci fications eerst nena iain en A 8 Abbreviations Acronyms and Terms to Know sse GL 1 List of Figures Figure 2 1 Help Screen Sheet 1 of 2 sescenti Rp Rp b Eam 2 6 List of Tables Table 2 1 Diagnose Riet 2 1 Table 3 L Diagnoshie Test i106 usen epa tnb ri n kx toi ixi Qu eda HER 3 1 Table 3 2 E Test GrOUP pte Apte kt EIER Para LL iana 3 3 Tables DEC Tesh Group aci bestie bp spe or nina e n br ade 3 5 Table o DEC Error i ci PU 3 15 Table os TSA E 3 20 Tabie a G EE 3 23 Table 2 7 KEDE 700 Error Messages arreire prodi t ee dk ried 3 30 Table F8 E 3 34 Table 3 9 L2C ACHE Error Messages ni scena mai aa 3 42 Table 3 10 NCR Tesi Group seis eno tete rnnt en ehe iion Rua bk de agde iE 3 43 Table o 11 PAR8730x Test COXRUIDL aiiis eese tpe tiis rcp daa Ei cendE 3 59 Table 3 12 UART Test GOUD a enses e o ES epit MK Rn d ic PERS cum 3 61 Table 3 15 VLART WE 3 67 Table 2 18 PCIBUS Tesh GUP cesoeedeenian
44. 8xx Interrupts Running PASSED If any part of the test fails then the display appears as follows NCR IRQ NCR 53C8xx Interrupts Running FAILED NCR IRQ Test Failure Data error message Here error message is one of the following l est Initialization Error Not Enough Memory Need Actual Test Initialization Error Memory Move Byte Count to Large Max 00ffffff Requested Test Initialization Error Test Memory Base Address Not 32 Bit Aligned SCSI Status Zero SGI Address y Interrupt Status SI Address sn E SCSI Status Zero SGI E bit not set xpected Actual __ P bit not set xpected Actual __ t E bit will not clear Address B xpected Actual __ t 3 50 Interrupt Sta Address Interrupt Con Address SCSI Interrup NCR 53C8xx SCSI I O Processor Tests tus SIP bit will not clear Expected __ Actual trol Reg not initially clear Expected __ Actual t Enable SGE bit not set Address Expected __ Actual _ Interrupt Control IEN bit not set Address Expected _ Actual _ Interrupt Status bit did not set Status Expected __ Actual __ Vector Expected __ Actual __ State IRQ Level _ VBR _ Interrupt Con Address SCSI Interrup Address Incorrect Vec Sta Vec Sta SCSI Interrupt
45. AI ALTS Alternating Ones Zeroes Running PASSED If the test fails then the display appears as follows RAI ALTS Alternating Ones Zeroes Running FAILE D RAM ALTS Test Failure Data Data Miscompare Error Address Expected Actual 3 75 Test Descriptions BTOG Bit Toggle Command Input PPCl Diag ram btog Description The memory range is specified by the RAM test directory configuration parameters Refer to CF Test Group Configuration Parameters Editor in Chapter 2 The RAM test directory configuration parameters also determine the value of the global random data seed used by this test The global random data seed is incremented after it is used by this test This test uses the following test data pattern generation algorithm 1 Random data seed is copied into a work register 2 Work register data is shifted right one bit position 3 Random data seed is added to work register using unsigned arithmetic 4 Data in the work register may or may not be complemented 5 Data in the work register is written to current memory location If the RAM test directory configuration parameter for code cache enable equals Y the microprocessor code cache is enabled This test is coded to operate using the 32 bit data size only Each memory location in the specified memory range is written with the test data pattern Each memory location in t
46. C board system the mask values are preserved in non volatile memory This allows the system to be completely powered down without disturbing the self test mask Example PPCl Diag mask ram adr Update Non Volatile RAM Y N y RAM ADR PPCl Diag mask RAM ADR PPCl Diag NV Non Verbose Mode Upon detecting an error the tests display a substantial amount of data To avoid the necessity of watching the scrolling display you can choose a mode that suppresses all messages except test name and PASSED or FAILED This mode is called non verbose and you can invoke it prior to calling a command by entering NV Example PPCl Diag nv uart lpbke UART LPBKE External Loopback Running FAILED PPC1 Diag gt NV causes the monitor to run the UART external loopback test but show only the name of the test and the results pass fail PPCl Diag uart lpbke UART LPBKE External Loopback Running FAILED UART LPBKE Test Failure Data RTS loopback to CTS or RI Failed COM2 PPCl Diag Without nv the failure data is displayed Utilities SD Switch Directories The SD command allows you to switch back and forth between PPCBug s diagnostic directory the prompt reads ppci Diag gt and the debug directory the prompt reads ppci Diag gt If you are in the diagnostic directory and enter SD you will return to the debug directory At this point only
47. CRATCH register by walking a 1 bit through a field of zeros and walking a 0 bit through a field of ones If no errors are detected the NCR device is reset otherwise the device is left in the test state Response Messages After the command has been issued the following line is printed NCR ACC1 Device Access lee eee Running If all parts of the test are completed correctly then the test passes NCR ACC Device AGCOSS Leo ee err ex alae Running PASSED If any part of the test fails then the display appears as follows NCR ACCT Device ACCESS A werde EIN ee Neie Running FAILED NCR ACC1 Test Failure Data error message Here error message is one of the following SCRATCH Register is not initially cleared Device Access Error Address Expected Actual M Device Access Error NCR 53C8xx SCSI I O Processor Tests Bus Error Information Address Data Access Size __ Access Type _ Address Space Code _ Vector Number Unsolicited Exception Program Counter Vector Number Status Register Interrupt Level Notes 1 All error message data is displayed as hexadecimal values 2 The Unsolicited Exception information is only displayed if the exception was not a Bus Error 3 Access Size is displayed in bytes 4 Access Type is 0 write or 1 read 3 45 Test Descriptions ACC2 Register Access Command Input PPC1 Diag gt ner
48. D VGA543X PCI Test Failure Data PCI register test failure 3 117 Test Descriptions PELM Pixel Mask Register Command Input PPC1 Diag gt VGA543X PELM Description This test verifies the correct operation of the VGA Pixel Mask Register The test proceeds as follows 1 The Pixel Mask Register is initialized with one of 256 possible values with reserved bits being masked off to a value of zero 2 The Pixel Mask Register is read back to verify that the data that was written to the register in step 1 was written correctly Response Messages After the command has been issued the following line is printed VGA543X PELM Pixel Mask Register Running gt If all parts of the test are completed correctly then the test passes VGA543X PELM Pixel Mask Register Running PASSED If any part of the test fails then the display appears as follows VGA543X PELM Pixel Mask Register Running gt FAILED VGA543X PELM Test Failure Data Value read Expected 3 118 VGA543X Video Diagnostics Tests SEQR Sequencer Registers Command Input PPCl Diag VGA543X SEQR Description This test verifies the correct operation of the VGA Sequencer Controller Registers The test proceeds as follows 1 Each Sequencer Controller Register is initialized with one of 256 possible values with reserved bits being masked off to a value of zero 2 The Sequencer Controller
49. EAD rU tel a dt on vadat d x PU ea 1 3 Installation Configuration and Start U Porcuna 1 6 Tintroduchiofiasccesnnr n EAEE aT 2 1 Eeer 2 1 AEM Append Error Messages Mlogde eearieocteg eee erunt Zeen 22 CEM C par Eror Deele 2 3 CF Test Group Configuration Parameters Editor o eee rie 2 3 DE E 2 4 DEM Display Error Eed vtl EH RARO DURO S ede 2 4 IU UC Hy c DEO t 2 5 HE Helpings reno boa cippo ones bnt ederet utc onu 2 5 HEX Heip Es li E 2 8 LA Loop Always enger 2 8 LE Loop Continye Mode ssepe ptt iot terea e EDO a bx cte 2 9 LE Loop On Ertur Mode oce terri teer EE 2 9 LY Line Peed Suppression Modes consect epit i e 2 10 LIN Loop Non Verbose iade usce eorr pr e ARCH dE iR EERRE SES MA 2 11 MASK Display Revise Self Test Mask esee 2 11 NV Non Verbose ICI ues pecie ci omete ny C Rene a DU RC 2 12 SD Switch Ri s 2 13 SE ST 2 13 ST and QST Self Test and Quick Self Test nnt 2 14 ZE Cleat Zero Error EE 2 15 EE 2 15 GET28S Parallel Interit Doubs creron AE 33 REG HEET ieniemienie ERA EENE EN A A ESE ES 3 4 DEC Ethernet Controller Test scrise abbat duc ep va sd n Rae ER 3 5 CNIT e ri irc E 3 6 LOAD Continuous Lost saccis dretter 3 7 VR n EREE 3 8 ERREN PERREN SERREN Bit Toggle tore mte F9 ILR Interrupt Line Register ACCESS cicsiintssainisenansocsinesiseseniaoiearecssasiescsindae 3 10 IOR Ef a 3 11 REGA PCI Header Register Access ia reridty bo
50. EXT Keyboard Controller Extended Test Running gt If all parts of the test are completed correctly then the test passes KBD8730x KCEXT Keyboard Controller Extended Test Running gt PASSED If any part of the test fails then the display appears as follows KBD8730x KCEXT Keyboard Controller Extended Test Running gt FAILED KBD8730x KCEXT Test Failure Data error message Refer to the section KBD8730x Error Messages for a list of the error messages and their meaning Test Descriptions MSCONF Mouse Device Confidence Extended Command Input PPC1 Diag gt kbd8730x msconf Description This test performs an interface test of the keyboard controller to ensure correct operation of the interface to the mouse device Response Messages After the command has been issued the following line is printed KBD8730x MSCONF Mouse Device Confidence Extended Running gt If all parts of the test are completed correctly then the test passes KBD8730x MSCONF Mouse Device Confidence Extended Running gt PASSED If any part of the test fails then the display appears as follows KBD8730x MSCONF Mouse Device Confidence Extended Running FAILED KBD8730x MSCONF Test Failure Data error message Refer to the section KBD8730x Error Messages for a list of the error messages and their meaning KBD8730x Keyboard Controller Tes
51. M An improved VGA monitor standard that provides at least 256 simultaneous colors and a screen resolution of 800 x 600 pixels One way broadcast of digital information The digital information is injected in the broadcast TV signal VBI or full field The transmission medium could be satellite microwave cable etc The display medium is a regular TV receiver See 10base 5 See 10base 2 See 10Base T Universal Asynchronous Receiver Transmitter GL 12 Glossary Universe UV UVGA ASIC developed by Tundra in consultation with Motorola that provides the complete interface between the PCI bus and the 64 bit VMEbus UltraViolet Ultra Video Graphics Array An improved VGA monitor standard that provides at least 256 simultaneous colors and a screen resolution of 1024 x 768 pixels Vertical Blanking Interval VBI VESA bus VGA virtual address VL bus VMEchip2 VME2PCI volatile memory VRAM The time it takes the beam to fly back to the top of the screen in order to retrace the opposite field odd or even VBI is in the order of 20 TV lines Teletext information is transmitted over 4 of these lines lines 14 17 Video Electronics Standards Association or VL bus An internal interconnect standard for transferring video information to a computer display system Video Graphics Array IBM The third and most common monitor standard used today It provides up to 256 simultaneous colors and a scree
52. MA Interrupt Enable SSTATO SCSI Status Zero DSTAT DMA Status ISTAT Interrupt Status SFBR SCSI First Byte Received a Sets SCSI outputs in high impedance state disables interrupts using the MIEN and sets NCR device for Single Step Mode a Loads the address of a simple INTERRUPT instruction SCRIPT into the DMA SCRIPTs Pointer register The SCRIPTs processor is started by hitting the STD bit in the DMA Control Register Single Step is checked by verifying that ONLY the first instruction executed and that the correct status bits are set Single Step Mode is then turned off and the SCRIPTs processor started again The INTERRUPT instruction should then be executed and a check for the correct status bits set is made a Loads the address of the JUMP instruction SCRIPT into the DMA SCRIPTS Pointer register and the SCRIPTs processor is automatically started JUMP if TRUE Compare True Compare False conditions are checked then JUMP if 3 55 Test Descriptions FALSE Compare True Compare False conditions are checked a Builds the Memory Move instruction SCRIPT in a script buffer to allow the Source Address Destination Address and Byte Count to be changed by use of the config command If a parameter is changed the only check validity is the Byte Count during test structures initialization The Memory Move SCRIPT copies the specified nu
53. N bit toggle Running FAILED DEC ERREN Test Failure Data error message Refer to the section DEC Error Messages for a list of the error messages and their meaning 3 9 Test Descriptions ILR Interrupt Line Register Access Command Input PPCl Diag DEC ILR Description This test sends all possible byte patterns 0x00 OxFF to the Interrupt Line register in the PCI register space It verifies that the register can be read and written for all possible bit combinations It checks that the byte read is the same as the byte previously written to verify that the register holds data correctly Response Messages After the command has been issued the following line is printed DEC ILR Interrupt Line Register Access Running gt If all parts of the test are completed correctly then the test passes DEC ILR Interrupt Line Register Access Running PASSED If any part of the test fails then the display appears as follows DEC ILR Interrupt Line Register Access Running FAILED DEC ILR Test Failure Data error message Refer to the section DEC Error Messages for a list of the error messages and their meaning DEC Ethernet Controller Tests IOR I O Resource Register Access Command Input PPCl Diag dec ior Description This test reads all the I O resource registers pointed to by the PCI Base Address register and all the indexed registers
54. PPCBug Diagnostics Manual PPCDIAA UM1 Notice While reasonable efforts have been made to assure the accuracy of this document Motorola Inc assumes no liability resulting from any omissions in this document or from the use of the information obtained therein Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes No part of this material may be reproduced or copied in any tangible medium or stored in a retrieval system or transmitted in any form or by any means radio electronic mechanical photocopying recording or facsimile or otherwise without the prior written permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not announced in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Restricted Rights Legend If the documentation contained herein is supplied directly or indirectly to the U S Government the following notice shall apply unless otherwise agreed to in writing by Motorola Inc Use duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph c 1 ii of the Rights in Technical Dat
55. Quick Write Reads ise diete retain Hia rti 3 84 REP Menon ESTE TEONE Loescicedati toque uenia ii bui RR ba d 3 85 RINDM Random eege En la p Sains 3 87 RIC MEKABTxx Timekeeping Tests anenee nina koi qe mu IE o tci n 3 88 ADR MK48 Tsk BBRAM Addressing coaches ie omite tts 3 89 ALARM Alaren IntetgipE cec sprite ppneh Ete sk o bur pe x UGG EXER d cin 3491 CLK Real Time lock PUIGUDEL uu nenas diste eibi ise mdp IEEE 3 92 EAM Battery Backed Lp RAM aethere tee npe px ipto 3 94 WATCHDOG Watchdog Time Out Reset 1 rr rnetiete nter 3 95 SCC Serial Communication Controller 785230 Tests 3 96 ACCESS Device Register AER easet nre ioter a 3 98 BAUDS Dand ro guerre dE 399 DMA Receive Transmit DIM A cte cesta verexsussavanssievonxonsanavscnsoezse 3 100 ELPBCK External Loopback Luise roi te prr ir gege 3 102 ILPBCK Inhertial Loopback acie icti ie Fe iod tiene ine 3 103 IRO Interrapt ISequiesbeoescn inse edpaptridscirtn EAE KRE Ue AN AE geg 3 104 MOME Modem Control issuer nies ap mt donde pague ea in dieses 3 105 VARI GI geckegen 3 106 VG AS4SX Video KE 3 108 ATTR e Register ceci x rni EEEn Ea tava X UNE aA RE 3 109 BET Bit Diet M 3 110 CRTC CRT Controller Registers i ciscasdainasrsaeralaanenieaacamsuaie sina 3 111 IER 3 112 EXTN E 3 113 GRPEH Graphics Controller Register S rnp 3 114 MISC Miscellaneous Register susra anuencia aeui aE 3 115 e 3 116 Pl PC Header Seenen keen 3 1
56. R Re Running PASSED If any part of the test fails then the display appears as follows DEC CNCIR CONNECT OL ee ENEE e Running FAILED DEC CNCTR Test Failure Data error message Refer to the section DEC Error Messages for a list of the error messages and their meaning You can use the CF command to select the port to be tested whether AUI or TP The following example uses the CF command to select port 1 the TP port skipping port 0 the AUI port Example PPC1 Diag gt CF DEC DEC Configuration Data Port Select 00000000 1 3 8 DEC Ethernet Controller Tests ERREN PERREN SERREN Bit Toggle Command Input PPCl Diag DEC ERREN Description This test toggles the PERREN and SERREN Address and Data Parity Error status bits in the command register found in the PCI header address space to verify that this register functions properly Each bit is toggled written and then read to verify that they are indeed toggled Response Messages After the command has been issued the following line is printed DEC ERREN PERREN and SERREN bit toggle Running If all parts of the test are completed correctly then the test passes DEC ERREN PERREN and SERREN bit toggle Running PASSED If any part of the test fails then the display appears as follows DEC ERREN PERREN and SERRE
57. RAM location of the MK48Txx Timekeeper RAM RAM contents are unchanged upon completion of test regardless of pass or fail test return status This test is coded to test only byte data entities The test proceeds as follows For each of the following patterns 1 3 7 f 1f 3 7t for each valid byte of the Timekeeper RAM 1 Write and verify the current data test pattern 2 Write and verify the complement of the current data test pattern Response Messages After the command has been issued the following line is printed RIC RAM MK48Txx Battery Backed Up RAM Running gt If all parts of the test are completed correctly then the test passes RIC RAM MK48Txx Battery Backed Up RAM Running PASSED If the test fails then the display appears as follows RTC RAM MK48Txx Battery Backed Up RAM Running FAILED RTIC RAM Test Failure Data error message Here error message is the following Data Miscompare Error Address Expected Actual RTC MK48Txx Timekeeping Tests WATCHDOG Watchdog Time Out Reset Command Input PPCl Diag rtc watchdog Description aS Caution This test sets the Real Time Clock s Watchdog Timer to time out in one second If the Watchdog Timer is functional the WDF Watchdog Flag bit will be set and a microprocessor reset will be generated If this test passe
58. Register is read back to verify that the data that was written to the register in step 1 was written correctly Response Messages After the command has been issued the following line is printed VGA543X SEOR Sequencer Registers Running If all parts of the test are completed correctly then the test passes VGA543X SEQR Sequencer Registers Running PASSED If the test fails then the display appears as follows el VGA543X SEQR Sequencer Registers Running FAILE VGA543X SEQR Test Failure Data error message If the error is in one of the index registers then error message is Index register Value read Expected Otherwise error message iS Data register Value read Expected 3 119 Test Descriptions VRAM Video Memory Command Input PPC1 Diag gt VGA543X VRAM Description This test verifies the first 1 megabyte of video RAM Each location is written as a 16 bit value with alternating 1s and Os The test restores each memory location as it is tested Response Messages After the command has been issued the following line is printed VGA543X VRAM Cirrus vga543x VRAM Test Running If all parts of the test are completed correctly then the test passes VGA543X VRAM Cirrus vga543x VRAM Test Running PASSED If any part of the test fails then the display appears as follows
59. Test Group Configuration Parameters Editor DE Display Error Counters DEM Display Error Messages DP Display Pass Count HE Help HEX Help Extended LA Loop Always Mode LC Loop Continue Mode LE Loop On Error Mode LF Line Feed Suppression Mode LN Loop Non Verbose Mode MASK Display Revise Self Test Mask NV Non Verbose Mode QST Quick Self Test SD Switch Directories 2 1 Diagnostic Utilities Table 2 1 Diagnostic Utilities Continued Command Description SE Stop On Error Mode ST Self Test ZE Clear Zero Error Counters ZP Zero Pass Count Notes You may enter command names in either uppercase or lowercase Terminate all command lines by pressing the RETURN key AEM Append Error Messages Mode The AEM command allows you to accumulate error messages in the internal error message buffer of the diagnostic monitor This command sets the internal append error messages flag of the diagnostic monitor The default of the internal append error messages flag is clear The internal flag is not set until it is encountered in the command line by the diagnostic monitor The contents of the buffer can be displayed with the DEM command When the internal append error messages flag has not been set or has been cleared with CEM the diagnostic error message buffer is erased cleared of all character data before each test is executed The duration of this command is for the life of the command
60. U DCE DLL DMA DOS dpi DRAM DTE ECC ECP EEPROM EIDE EISA bus EPP Central Processing Unit The master computer unit in a system Data Circuit terminating Equipment Dynamic Link Library A set of functions that are linked to the referencing program at the time it is loaded into memory Direct Memory Access A method by which a device may read or write to memory directly without processor intervention DMA is typically used by block I O devices Disk Operating System dots per inch Dynamic Random Access Memory A memory technology that is characterized by extreme high density low power and low cost It must be more or less continuously refreshed to avoid loss of data Data Terminal Equipment Error Correction Code Extended Capability Port Electrically Erasable Programmable Read Only Memory A memory storage device that can be written repeatedly with no special erasure fixture EEPROMs do not lose their contents when they are powered down Enhanced Integrated Drive Electronics An improved version of IDE with faster data rates 32 bit transactions and DMA Also known as Fast ATA 2 Extended Industry Standard Architecture bus IBM An architectural system using a 32 bit bus that allows data to be transferred between peripherals in 32 bit chunks instead of 16 bit or 8 bit that most systems use With the transfer of larger bits of information the machine is able to perform much faster than the sta
61. VGA543X VRAM Cirrus vga543x VRAM Test Running FAILED VGA543X VRAM Test Failure Data Data Error Expected Actual Address 3 120 VME2 VME Interface ASIC Tests VME2 VME Interface ASIC Tests This section lists the individual VMEchip 2 tests but does not describe them These tests are available only on the MVME160x PowerPC boards For all other PowerPC boards these tests are bypassed Entering VME2 without parameters causes all VME2 tests to execute in the order shown in the table below To run an individual test add that test name to the VME2 command Table 3 21 VME2 Test Group Name Description REGA Register Access REGB Register Walking Bit TMRA Tick Timer 1 Increment TMRB Tick Timer 2 Increment TMRC Prescaler Clock Adjust TMRD Tick Timer 1 No Clear On Compare TMRE Tick Timer 2 No Clear On Compare TMRF Tick Timer 1 Clear On Compare TMRG Tick Timer 2 Clear On Compare TMRH Tick Timer 1 Overflow Counter TMRI Tick Timer 2 Overflow Counter TMRJ Watchdog Timer Counter SWIA Software Interrupts Polled Mode SWIB Software Interrupts Processor Interrupt Mode SWIC Software Interrupts Priority 3 121 Test Descriptions Z8536 Counter Timer Tests This section describes the individual Z8536 CIO counter timer tests These tests are not available on the MVME230x PowerPC boards Entering Z8536 without parameters causes all Z8536 tests to execute in the order
62. Z8536 Z8536 Counter Timer Tests All except MVME230x 3 1 Notes 1 You may enter command names in either uppercase or lowercase 2 Some diagnostics depend on restart defaults that are set up only in a particular restart mode Refer to the documentation on a particular diagnostic for the correct mode CL1283 Parallel Interface Tests CL1283 Parallel Interface Tests This section describes the CL1283 parallel Interface CL1283 tests Note These tests apply only to the MTX boards They are not available on the other PowerPC boards MVME230x MVME260x MVME360x MVME460x and PMCspan Entering CL1283 without parameters causes all CL1283 tests to execute in the order shown in the following table To run an individual test add that test name to the CL1283 command The individual tests are described in alphabetical order on the following pages Table 3 2 CL1283 Test Group Name Description REG Register 3 3 Test Descriptions REG Register Command Input PPC1 Diag gt CL1283 REG Description This test verifies that the CL1283 registers can be read and written Data patterns verify that every read write bit can be modified Response Messages After the command has been issued the following line is printed CL1283 REG c11283 Register Access Running If all parts of the test are completed correctly then the test passes CL1283 REG c11283 Registe
63. a and Computer Software clause at DFARS 252 227 7013 Motorola Inc Computer Group 2900 South Diablo Way Tempe Arizona 85282 Preface The PPCBug Diagnostics Manual provides general information installation procedures and a diagnostic firmware guide for the PPC1Bug Debugging Package All information contained herein is specific to Motorola s PowerPC based boards MVME230x VME Processor Modules MVME260x Single Board Computers MVME360x VME Processor Modules MVME460x VME Dual Processor Modules and MTX Embedded ATX Motherboards In this manual they are collectively referred to as the PowerPC board or board When necessary to refer to them individually they are called the MVME230x MVME260x MVME360x MVME460x and MTX This manual covers release 3 3 of PPC1Bug dated 06 20 97 Use of the PPCBug debugger the debugger command set the one line assembler disassembler and system calls for the debugging package are all described in the two volume PPCBug Firmware Package User s Manual PPCBUGA1 UMS and PPCBUGA2 UMD Refer also to the lists of publications in Appendix A Related Documentation for other documents that may provide helpful information This manual is intended for anyone who wants to design OEM systems supply additional capability to an existing compatible system or work in a lab environment for experimental purposes A basic knowledge of computers and digital logic is assumed Conventions The following conven
64. a command byte and reads it back from the PC8730x keyboard controller to place it in correct operation mode and test that the registers can be accessed and that the data paths to the device are functioning It then issues a keyboard controller self command to invoke the internal diagnostics that are performed in the keyboard controller itself Response Messages After the command has been issued the following line is printed KBD8730x KCCONF Keyboard Controller Confidence Running If all parts of the test are completed correctly then the test passes KBD8730x KCCONF Keyboard Controller Confidence Running PASSED If any part of the test fails then the display appears as follows KBD8730x KCCONF Keyboard Controller Confidence Running FAILED KBD8730x KCCONF Test Failure Data error message Refer to the section KBD8730x Error Messages for a list of the error messages and their meaning KBD8730x Keyboard Controller Tests KCEXT Keyboard Mouse Controller Extended Test Command Input PPC1 Diag KBD8730x KCEXT Description This test performs all the functions in the keyboard controller confidence tests kcconf tests the keyboard controller RAM locations by writing all possible byte values 0x00 0xff to all possible RAM locations and tests the Password functionality of the controller Response Messages After the command has been issued the following line is printed KBD8730x KC
65. acc2 Description This procedure tests the basic ability to access the NCR 53C8xx registers by checking the state of the registers from a software reset condition and checking their read write ability Status registers are checked for initial clear condition after a software reset Writable registers are written and read with a walking 1 through a field of zeros If no errors are detected the NCR device is reset otherwise the device is left in the test state Response Messages After the command has been issued the following line is printed NCR ACC2 Register AcceSS 0e a eens Running If all parts of the test are completed correctly then the test passes NCR ACC2 Register Access lees Running PASSED If any part of the test fails then the display appears as follows NCR ACC2 Register Access llle eee Running FAILED NCR ACC2 Test Failure Data error message Here error message is one of the following IS Register is not initially cleared A SSTATO Register is not initially cleared A SSTAT1 Register is not initially cleared SSTAT2 Register is not initially cleared SIEN Register Error Address Expected __ Actual _ 3 46 NCR 53C8xx SCSI I O Processor Tests SDID Register Error Address Expected __ Actual SODL Register Error Address Expected _ Actual _ SXFER Register
66. ache The main objective of this test is to exercise the L2 Cache with Cache Updating disabled The test flow is as follows Turn on the cache with updating and WriteBack Write an incrementing pattern to cache original region Verify the incrementing pattern Turn off cache updating Write a decrementing pattern to displacing memory region Turn off the cache Write decrementing pattern to original memory region Verify the decrementing pattern Turn on the cache with WriteBack Verify the decrementing pattern in the cache Response Messages After the command has been issued the following line is printed L2CACHE DISUPD L2 Cache Disable Updating Running If all parts of the test are completed correctly then the test passes L2CACHE DISUPD L2 Cache Disable Updating Running gt PASSED If any part of the test fails then the display appears as follows L2CACHE DISUPD L2 Cache Disable Updating Running gt FAILED L2CACHE DISUPD Test Failure Data error message Refer to the section L2CACHE Error Messages for a list of the error messages and their meaning Test Descriptions ENUPD Enable Updating Command Input PPCl Diag l2cache enupd Description This test performs a write read test on the L2 Cache The main objective of this test is to exercise the L2 Cache with Cache Updating enabled The test flow is as follows Turn on the cache with WriteBack Write an incrementin
67. after the command RAM ADR the command line would read PPCl Diag RAM ADR RTC CLK Spaces are not required before or after the semicolon but are shown here for legibility Spaces are required between commands and their arguments Several commands may be combined on one line General Information Installation Configuration and Start Up The PPCBug firmware is installed by Motorola at the factory when your PowerPC board is manufactured Refer to your PowerPC board installation manual and ensure that all necessary hardware preparation board installation connection of peripherals and hardware configuration including console selection and configuration of Software Readable Headers where applicable has been correctly done After your hardware has been set up according the installation manual refer to the PPCBug Firmware Package User s Manual for the start up procedure before powering up the system 1 6 Diagnostic Utilities Introduction This chapter contains descriptions and examples of the various diagnostic utilities available in PPCBug Utilities In addition to individual or sets of tests the diagnostic package supports the utilities root level commands or general commands listed in the table below and described on the following pages Table 2 1 Diagnostic Utilities Command Description AEM Append Error Messages Mode CEM Clear Error Messages CF
68. again and avoids accessing the slower hard or floppy disk drive CAS Column Address Strobe The clock signal used in dynamic RAMs to control the input of column addresses CD Compact Disc A hard round flat portable storage unit that stores information digitally CD ROM Compact Disk Read Only Memory CFM Cubic Feet per Minute CHRP See Common Hardware Reference Platform CHRD CHRP compliant See Common Hardware Reference Platform CHRD CHRP Spec See Common Hardware Reference Platform CHRP CISC Complex Instruction Set Computer A computer whose processor is designed to sequentially run variable length instructions many of which require several clock cycles that perform complex tasks and thereby simplify programming CODEC COder DECoder Color Difference CD The signals of R Y and B Y without the luminance Y signal The Green signals G Y can be extracted by these two signals Common Hardware Reference Platform CHRP A specification published by Apple IBM and Motorola which defines the devices interfaces and data formats that make up a CHRP compliant system using a PowerPC processor Composite Video Signal CVS CVBS Signal that carries video picture information for color brightness and synchronizing signals for both horizontal and vertical scans Sometimes referred to as Baseband Video cpi characters per inch cpl characters per line GL 3 J oooro 2 o0o00r o Glossary CP
69. alfword 4 HE 1 3 2 5 IN 16 header verification 3 117 Help HE 2 5 Help command 1 3 Help Extended HEX 2 8 help screen 1 3 2 5 HEX 2 8 hexadecimal character 4 I I O processor tests 3 43 I O Resource Register Access IOR 3 11 ILPBCK 3 103 ILR 3 10 indexed registers 3 11 initialization chip 3 6 installation 1 6 Internal Loopback ILPBCK 3 103 Internal Loopback LPBK 3 64 Interrupt IRQ 3 21 3 124 Interrupt Line Register Access ILR 3 10 Interrupt Request IRQ 3 63 3 104 Interrupts IRQ 3 50 IOR 3 11 IRQ 3 21 3 50 3 63 3 104 3 124 ISABRDGE PCI ISA Bridge Tests 3 20 K KBCONF 3 24 KBD8730x 3 23 KBD8730x error messages 3 30 KBFAT 3 25 KCCONF 3 26 KCEXT 3 27 Keyboard Controller Confidence Ex tended KCCONF 3 26 Keyboard Device Confidence Extended KBCONF 3 24 Keyboard Test KBFAT 3 25 Keyboard Mouse Controller Extended Test KCEXT 3 27 L L2CACHE 3 34 L2CACHE Error Messages 3 42 LA 2 8 LC 2 9 LE 2 9 Level 2 Cache Tests L2CACHE 3 34 LF 2 10 Line Feed Suppression Mode LF 2 10 Linked Counter LNK 3 125 LN 2 11 LNK 3 125 Local Parity Memory Error Detection PED 3 81 Local RAM Tests RAM 3 72 Loop Always Mode LA 2 8 Loop Non Verbose Mode LN 2 11 loopback plug 3 8 Loop Continue Mode LC 2 9 Loop On Error Mode LE 2 9 lowercase 2 2 3 2 LPBK 3 64 LPBKE 3 65 manual terminology 4 manufacturers documents A 3 MARCH 3 79 marc
70. all of the PC8730x registers can be written and read Data patterns verify that every read write bit can be modified Response Messages After the command has been issued the following line is printed PAR8730x REG PC8730x Parallel Port s Register Data Running If all parts of the test are completed correctly then the test passes PAR8730x REG PC8730x Parallel Port s Register Data Running PASSED If any failures occur the following is displayed more descriptive text then follows PAR8730x REG PC8730x Parallel Port s Register Data Running FAILED If the test fails because the pattern written doesn t match the data read back from the PAR8730x register the following is printed PAR8730x REG Test Failure Data Register xxx Miscompare Error Address Expected _ Actual _ UART Serial Input Output Tests UART Serial Input Output Tests These sections describe the individual UART tests Entering UART without parameters causes all UART tests to run in the order shown in the table below except as noted To run an individual test add that test name to the UART command The individual tests are described in alphabetical order on the following pages Table 3 12 UART Test Group Name Description REGA Register Access IRO Interrupt Request BAUD Baud Rate tests LPBK Internal loopback Executed only when specified LPBKE External Loopback
71. and Sales Department 345 East 47th Street New York New York 10017 21633 Telephone 1 800 678 4333 OR Microprocessor system bus for 1 to 4 byte data TEC 821 BUS Bureau Central de la Commission Electrotechnique Internationale 3 rue de Varemb Geneva Switzerland Related Specifications Table A 3 Related Specifications Continued Document Title and Source Publication Number IEEE Common Mezzanine Card Specification CMC P1386 Draft 2 0 Institute of Electrical and Electronics Engineers Inc Publication and Sales Department 345 East 47th Street New York New York 10017 21633 Telephone 1 800 678 4333 IEEE PCI Mezzanine Card Specification PMC P1386 1 Draft 2 0 Institute of Electrical and Electronics Engineers Inc Publication and Sales Department 345 East 47th Street New York New York 10017 21633 Telephone 1 800 678 4333 Bidirectional Parallel Port Interface Specification IEEE Standard 1284 Institute of Electrical and Electronics Engineers Inc Publication and Sales Department 345 East 47th Street New York New York 10017 21633 Telephone 1 800 678 4333 Peripheral Component Interconnect PCI Local Bus Specification PCI Local Bus Revision 2 0 Specification PCI Special Interest Group 2575 NE Kathryn St 17 Hillsboro OR 97124 Telephone 800 433 5177 inside the U S or 503 693 6232 outside the U S FAX 503 693 8344 A 9 Related Documentation Table A
72. ard the equipment chassis and enclosure must be connected to an electrical ground The equipment is supplied with a three conductor AC power cable The power cable must be plugged into an approved three contact electrical outlet The power jack and mating plug of the power cable meet International Electrotechnical Commission IEC safety standards Do Not Operate in an Explosive Atmosphere Do not operate the equipment in the presence of flammable gases or fumes Operation of any electrical equipment in such an environment constitutes a definite safety hazard Keep Away From Live Circuits Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified maintenance personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Do not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power and discharge circuits before touching them Do Not Service or Adjust Alone Do not attempt internal service or adjustment unless another person capable of rendering first aid and resuscitation is present Use Caution When Exposing or Handling the CRT Breakage of the Cathode Ray Tube CRT causes a high velocity scattering of glass fragments implosion To prevent CRT implosion avoid rough handling or jarring of the equipment Han
73. are completed correctly then the test passes SCC BAUDS Baud RACES ss oi eet er Running PASSED If any part of the test fails then the display appears as follows SCC BAUDS Baud EE Running FAILED SCC BAUDS Test Failure Data error message Refer to the section SCC Error Messages for a list of the error messages and their meaning Test Descriptions DMA Receive Transmit DMA Command Input PPCl Diag SCC DMA Description This test will verify that the SCC can transmit and receive via internal loopback a 256 byte block of data that consists of all numbers between 0x00 and OxFF The test will be performed under DMA control A match of the contents of the transmit and receive buffers will be verified Due to the nature of DMA use of the i82378 SIO IC is also necessary Note Because of the design of the Z85230 when DMA testing is performed data is still transmitted out of the device on the TxD line This may cause problems with terminals modem printers and any other device attached Response Messages After the command has been issued the following line is printed SCC DMA DMA Testis uve ec deters wae er de Running If all parts of the test are completed correctly then the test passes SCC DMAS DMA TEST Eeer Reste e rein rh the Running PASSED If all parts of the test are not completed correctly then the test does not pass The receiver buffer m
74. articular assertion and assert refer to a signal that is active or true negation and negate indicate a signal that is inactive or false These terms are used independently of the voltage level high or low that they represent For PPCBug data and address sizes are defined as follows Q A byte is eight bits numbered 0 through 7 with bit 0 being the least significant T A halfword is 16 bits numbered 0 through 15 with bit 0 being the least significant T A word is 32 bits numbered 0 through 31 with bit 0 being the least significant In addition commands that act on halfwords or words over a range of addresses may truncate the selected range so as to end on a properly aligned boundary Safety Summary Safety Depends On You The following general safety precautions must be observed during all phases of operation service and repair of this equipment Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design manufacture and intended use of the equipment Motorola Inc assumes no liability for the customer s failure to comply with these requirements The safety precautions listed below represent warnings of certain dangers of which Motorola is aware You as the user of the product should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment Ground the Instrument To minimize shock haz
75. ay not be filled with the data before terminal count This results in either one or both controllers giving error messages SOC DMA DMA Testus cjue arro aye tatters doses erts Running FAILED SCC DMA Test Failure Data error message 3 100 SCC Serial Communication Controller Z85230 Tests In the first case the Serial Port 3 Receiver Z85230 Port A Rx 182378 DMA Controller 1 and Channel 0 has reached terminal count before receiving all the data In the second case the Serial Port 4 Receiver 785230 Port B Rx 182378 DMA Controller 2 and Channel 5 has reached terminal count before receiving all the data If the receiver buffer is filled with data before terminal count it may still be an incorrect match to the data transmitted This results in an error SOC DMA DMA Test ev RR ee SE ays Running FAILE D SCC DMA Test Failure Data error message The Verify Counter used in this error message gives the amount of data transferred correctly The values in the two buffers that did not match are shown also Refer to the section SCC Error Messages for a list of the error messages and their meaning 3 101 Test Descriptions ELPBCK External Loopback Command Input PPCl Diag SCC ELPBCK Description This test transmits 256 characters at 38400 baud The data is received and compared If any protocol errors are created or the data is not correct when received the test fails This
76. back ILPBCK Internal Loopback MDMC Modem Control DMA Receive Transmit DMA Note These tests number the ports of the Z85230 starting with the first Z85230 channel 0 as being port A the second channel 1 as being port B For the Power PC family of boards there are only ports A and B You can use the CF command to select the ports to be tested The following example uses the CF command to select port 1 skipping port 0 SCC Serial Communication Controller Z85230 Tests Example PPCl Diag CF SCC SCC Memory Space Base Address 80000840 RETURN Internal Loopback Baud Rates Port Mask 00000003 2 Bit 0 selects port 0 Bit 1 selects port 1 see note below External Loopback Modem Control Port Mask 00000003 The first parameter is the base address space for the Z85230 devices This is preset for the PowerPC family of boards and should not be changed The next two parameters are the port selection masks These masks are used during testing to identify which ports are to be tested The default is to test every port The Internal Loopback Baud Rates Port Mask is used for the BAUDS and ILPBCK test suites The External Loopback Modem Control Port Mask is only used for the ELPBCK and MDMC test suites Test Descriptions ACCESS Device Register Access Command Input PPCl Diag SCC ACCESS Description This test performs a write read test on two registers in the Z85230 This test verifies that t
77. cess Running gt If all parts of the test are completed correctly then the test passes PCIBUS REG PCI PMC Slot Register Access Running PASSED If any part of the test fails then the display appears as follows PCIBUS REG PCI PMC Slot Register Access Running FAILED error message Refer to the section PCIBUS Error Messages for a list of the error messages and their meaning 3 70 PCIBUS Generic PCI PMC Slot Tests PCIBUS Error Messages Error Message The PCIBUS test group error messages generally take the following form PCIBUS REG PCOT PMC m asse osesiss Running FAILED BIST failed to complete The first line of the test failure data identifies what type of failure occurred Table 3 15 PCIBUS Error Messages Symptom or Cause BIST failed to complete The Built In Self Test of the PCI or PMC device did not complete before timing out Interrupt Line Register Write Error The value read from the Interrupt Line Register does match what was written 3 71 Test Descriptions RAM Local RAM Tests These sections describe the individual Random Access Memory RAM tests Entering RAM without parameters causes all RAM tests to execute in the order shown in the table below To run an individual test add that test name to the RAM command The individual tests are described in alphabetical order on
78. command has been issued the following line is printed RAI MARCH March Address Running If all parts of the test are completed correctly then the test passes RAI MARCH March Address Running PASSED If the test fails then the display appears as follows RAI MARCH March Address Running gt FAILED RAM MARCH Test Failure Data Data Miscompare Error Address Expected Actual 3 79 Test Descriptions PATS Data Patterns Command Input PPCl Diag RAM PATS Description If the test address range test range is less than 8 bytes the test immediately returns pass status The effective test range end address is reduced to the next lower 8 byte boundary if necessary Memory in the test range is filled with all ones SFFFFFFFF For each location in the test range the following patterns are used 00000000 01010101 03030303 07070707 SOFOFOFOF S1F1F1F1F S3F3F3F3F STEFTFTFTF Each location in the test range is individually written with the current pattern and the 1 s complement of the current pattern Each write is read back and verified This test is coded to use only 32 bit data entities Response Messages After the command has been issued the following line is printed RAI PATS Patterns sesers 9 Ree Running If all parts of the test are completed correctly then the test passes RAI PATS s
79. dling of the CRT should be done only by qualified maintenance personnel using approved safety mask and gloves Do Not Substitute Parts or Modify Equipment Because of the danger of introducing additional hazards do not install substitute parts or perform any unauthorized modification of the equipment Contact your local Motorola representative for service and repair to ensure that safety features are maintained Dangerous Procedure Warnings Warnings such as the example below precede potentially dangerous procedures throughout this manual Instructions contained in the warnings must be followed You should also employ all other safety precautions which you deem necessary for the operation of the equipment in your operating environment Dangerous voltages capable of causing death are present in A this equipment Use extreme caution when handling testing WARNING and adjusting The computer programs stored in the Read Only Memory of this device contain material copyrighted by Motorola Inc 1997 and may be used only under a license such as contained in Motorola s software licenses The software described herein and the documentation appearing herein are furnished under a license agreement and may be used and or disclosed only in accordance with the terms of the agreement The software and documentation are copyrighted materials Making unauthorized copies is prohibited by law No part of the software or documentation may be reprod
80. e The standard format for recording storing and playing digital music Multimedia Personal Computer The PowerPC to PCI bus bridge chip developed by Motorola for the Ultra 603 Ultra 604 system board It provides the necessary interface between the MPC603 MPC604 processor and the Boot ROM secondary cache the DRAM system memory array and the PCI bus Motorola s component designation for the PowerPC 601 microprocessor Motorola s component designation for the PowerPC 603 microprocessor Motorola s component designation for the PowerPC 604 microprocessor Multi Processor Interrupt Controller MicroProcessing Unit Mean Time Between Failures A statistical term relating to reliability as expressed in power on hours poh It was originally developed for the military and can be calculated GL 7 J oooro 2 o0o00r o Glossary multisession non interlaced nonvolatile memory NTSC NVRAM OEM OMPAC OS OTP palette parallel port PCI local bus several different ways yielding substantially different results The specification is based on a large number of samplings in one place running continuously and the rate at which failure occurs MTBF is not representative of how long a device or any individual device is likely to last nor is ita warranty but rather a gauge of the relative reliability of a family of products The ability to record additional information such as digitized photograp
81. e Verify the incrementing pattern Turn off the cache Verify that the incrementing pattern is in memory Write decrementing pattern to memory Verify the decrementing pattern Turn on the cache with WriteThru and verify the incrementing pattern in cache Response Messages After the command has been issued the following line is printed L2CACHE WRTHRU L2 Cache WriteThru Running If all parts of the test are completed correctly then the test passes L2CACHE WRTHRU L2 Cache WriteThru Running PASSED If all parts of the test are not completed correctly then the test does not pass L2CACHE WRTHRU L2 Cache WriteThru Running FAILED L2CACHE WRTHRU Test Failure Data error message Refer to the section L2CACHE Error Messages for a list of the error messages and their meaning 3 41 Test Descriptions L2CACHE Error Messages The L2 Cache test group error messages generally take the following form J2CACHE DISUPD L2 Cache Disable Updating Running FAILED ZCACHE DISUPD Test Failure Data Data Miscompare Failure Address 200040000 Expected 200000000 Actual FFFFFFFF The first line of the failure identifies what type of failure occurred The following line provides additional information about the failure Table 3 9 L2CACHE Error Messages Error Message Symptom or Cause f l2cache init internal error une
82. e Tests This section describes the individual Isabrdge PCI ISA Bridge tests Entering ISABRDGE without parameters causes all ISABRDGE tests to execute in the order shown in the following table To run an individual test add that test name to the ISABRDGE command The individual tests are described in alphabetical order on the following pages Table 3 5 ISABRDGE Test Group Name Description REG Register IRO Interrupt ISABRDGE PCI ISA Bridge Tests IRQ Interrupt Command Input PPCl Diag ISABRDGE IRQ Description This test verifies that the ISABRDGE can generate interrupts Response Messages After the command has been issued the following line is printed ISABRDGE RO Je Ree enge Me ee Running If all parts of the test are completed correctly then the test passes ISABRDGE IRO Interr pt s 9e see e e aie eo Running PASSED If any failures occur the following is displayed more descriptive text then follows ISABRDGE IRQ Intterr pt 0 2 4 ces etie tuy ieu Running FAILED If the test fails because an interrupt request from the ISABRDGE is pending after masking the ISABRDGE interrupt in the IEN register the following is displayed ISABRDGE IRQ Test Failure Data Unexpected ISABRDGE IRQ pending Address Expected Actual This test makes use of the ISABRDGE counters to generate the test interrupt If after running the counter
83. ess XXXxxXxx Channel xx Baud Rate E Data transmitted does not match data received Transmitter Ready Time Out SCC Base Address XXXxxXxxx Channel xx Baud Rate XXxx The selected ports transmitter never indicated ready to transmit Receiver Ready Character Available Time Out SCC Base Address XXXxxxXxx Channel xx Baud Rate E The receiver has not received a character in the allotted time RTS negation failed to negate CTS SCC Base Address XXXxxXxxx Channel Xx DTR assertion failed to assert DCD When DTR was driven SCC Base Address XXXXXxxx Channel xx DCD did not follow DTR negation failed to negate DCD SCC Base Address XXXXXXXX Channel Xx RTS assertion failed to assert CTS When RTS was driven SCC Base Address XXXXXXXX Channel xx CTS did not follow SCC DMA 1 Error Time out before Terminal Count SCC Base Address xxxxxxxx The receiver controller 1 did not receive all the data before TC SCC DMA 2 Error Time out before Terminal Count SCC Base Address xxXxxxxxx The receiver controller 2 did not receive all the data before TC SCC DMA Error Data Miscompare Error SCC Base Address XXXXXXXxx SCC Channel xx Verify Counter Xx xmit buffer XXXXXXXX receive buffer XXXXXXxxx Data transmitted does not match data received 3 107 Test Descriptions VGA543X Video Diagnostics Tests These sect
84. forms a write read test on the L2 Cache This test verifies that the device can be both accessed and that the L2 Cache Invalidate control is working The test flow is as follows Turn off the cache Write an incrementing pattern to memory Turn on the cache with WriteBack Write a decrementing pattern to cache while invalidating the cache Flush the cache which should have no effect Verify that the incrementing pattern is still in memory Response Messages After the command has been issued the following line is printed L2CACHE WBINV L2 Cache WriteBack w Invalidate Running If all parts of the test are completed correctly then the test passes L2CACHE WBINV L2 Cache WriteBack w Invalidate Running gt PASSED If any part of the test fails then the display appears as follows CACHE WBINV L2 Cache WriteBack w Invalidate Running FAILE D 2CACHE WBINV Test Failure Data error message Refer to the section L2CACHE Error Messages for a list of the error messages and their meaning 3 40 L2CACHE Level 2 Cache Tests WRTHRU WriteThru Command Input PPCl Diag l2cache wrthru Description This test performs a write read test on the L2 Cache This test verifies that the device can be both accessed and that the L2 Cache WriteThru control is working The test flow is as follows Turn on the cache with WriteThru Write an incrementing pattern to memory and the cach
85. from Value written XX Value read XX keyboard controller does not equal what was sent Indicates possible problem with bus interface to keyboard controller or its embedded firmware Keyboard Controller Failed Self Test 0xAA Keyboard controller self test command returned result that indicates a failure May indicate a problem with the embedded firmware Controller RAM mismatch error The value read from one of Value written XX Value read XX the keyboard controller RAM locations does not equal to what was written indicating a possible problem with the controller or it s embedded firmware Invalid result from Password Test command The password test command failed returning an invalid result indicating that there may be a problem with the embedded firmware 3 31 Test Descriptions Table 3 7 KBD8730x Error Messages Continued doesn t Error Message Password Test failed password should exist but Symptom or Cause A password that was given to the keyboard controller was not stored properly indicating a possible problem with the embedded firmware but does Password Test failed password should not exist There was a failure in clearing out the password from the keyboard controller indicating a possible problem with the embedded firmware Exception Unsolicited Exception Time IP NNNN Vector NNNN An unexpected interrupt occurred indicati
86. fying the byte count with each write Next the SFWR bit is cleared and the FIFO read verifying the byte count with each read If no errors are detected the NCR device is reset otherwise the device is left in the test state Response Messages After the command has been issued the following line is printed ole GREEN Running If all parts of the test are completed correctly then the test passes NCR SEIEOf SCSI FIFOs costes ae Rhe EE a oe e Running PASSED If any part of the test fails then the display appears as follows NCR SEIPO SCSI EIEO 4 eg eng ea oe Running FAILED NCR SFIFO Test Failure Data error message Here error message is one of the following SCSI FIFO is not initially empty SCSI FIFO writes not enabled SCSI FIFO Count Error Address Expected Actual __ t SCSI FIFO Error Address M Expected Actual __ PN PAR8730x Parallel Port Test PAR8730x Parallel Port Test This section describes the PC8730x parallel port test This test is performed using only one processor You may enter PAR8730x with or without specifying the REG test REG is the only test in the PAR8730x group The REG test is described on the following page Table 3 11 PAR8730x Test Group Name REG Description Register Test Descriptions REG Register Command Input PPC1 Diag gt PAR8730x REG Description This test verifies that
87. g pattern to cache original region Verify the incrementing pattern Turn off cache Write a decrementing pattern to original memory region Turn on the cache with WriteBack and enable updating Write decrementing pattern to displacing memory region Verify the incrementing pattern from the original region Response Messages After the command has been issued the following line is printed L2CACHE ENUPD L2 Cache Enable Updating Running If all parts of the test are completed correctly then the test passes L2CACHE ENUPD L2 Cache Enable Updating Running PASSED If any part of the test fails then the display appears as follows jJJCACHE ENUPD L2 Cache Enable Updating Running FAILED 2CACHE ENUPD Test Failure Data error message Refer to the section L2CACHE Error Messages for a list of the error messages and their meaning L2CACHE Level 2 Cache Tests PATTERN WriteThru Pattern Command Input PPCl Diag l2cache pattern Description This test performs a write read test on the L2 Cache The main objective of this test is to exercise the L2 Cache WriteThru control using multiple bit patterns The test flow is as follows Turn on the cache with WriteThru Write an incrementing pattern to memory and the cache Verify pattern is in the cache Turn off the cache Verify the pattern is outside of cache Response Messages After
88. g to the command For details on extended self test operation refer to the PPCBug Firmware Package User s Manual Example PPCl Diag qst RAM ADR Addressability Running PASSED UART REGA Register Access ees Running PASSED UART TRO JEE EE AEN Jie See en LEER Running PASSED UART BAUD Baud Rate eel ges Running PASSED UART LPBK Internal Loopback Running PASSED Z8536 CNI COuUnter c 4er ce a aa e Running PASSED 28536 INK Linked Counter Running PASSED 48536 IRO Interrupts 6e weg euer eg Running PASSED all tests in quick self test directory are run PPCl Diag Utilities ZE Clear Zero Error Counters The error counters originally come up with the value of zero but it is occasionally desirable to reset them to zero at a later time This command resets all of the error counters to zero Example PPCl Diag ze PPCl Diag This clears all error counters ZP Zero Pass Count Invoking the ZP command resets the pass counter to zero This is frequently desirable before typing in a command that invokes the Loop Continue mode Entering this command on the same line as LC results in the pass counter being reset on every pass Example Pass Count 1 Pass Count 1 Pass Count 1 lt BREAK gt Errors RAI ADR Addressabil Errors RAI ADR Addressabil pA epen ad a taS R
89. ge Unsolicited Exception Vector XX Symptom or Cause An unexpected exception occurred Data Miscompare Error Address XXXXXXXX Register Index XX Expected XX Actual XX Data write does not match data read Transmit buffer failed to empty channel d Transmitter buffer remained full Time out waiting for transmitter interrupt channel XX During Interrupt testing no interrupt was generated or received Baud rate failure expected d took d channel XX Measured baud rate was not the same as that expected Receiver line status interrupt occurred channel XX additional error information Data transmission error occurred Possible errors are framing parity or data overrun 3 67 Test Descriptions Table 3 13 UART Error Messages Continued Error Message Unexpected modem status interrupt occurred channel XX Symptom or Cause An unexpected change of modem signals was received during testing Transmit Receive character mismatch channel XX Data transmitted does not match data received Receiver Ready Character Available Time Out PC16550 Base Address XXXXXXXX Channel XX Baud Rate XXXX The receiver has not received a character in the allotted time DTR loopback to DSR and DCD Failed Channel XX When DTR was driven DCD or DSR did not follow RTS loopback to CTS and RI Failed Channel xx W
90. ges Error Message Exception Vector XX Symptom or Cause An unexpected exception occurred Data Miscompare Error Address XXXXXXXX Register Index st XX Expected XX actual Expected st Actual sx Interrupt Level SCC Base Address XXXXXXxxx Channel xx Exception Vector Serviced Error Data write does not match data read Incorrect vector taken or provided during interrupt service Exception failed to occur Vector Expected st Interrupt Level X Interrupt Not Stuck At Vector xxx Interrupt Level x SCC Base Address XXXXXXXX Channel Xx Error SCC Base Address XXXXXXxx Channel xx During Interrupt testing no interrupt was generated or received A preexisting interrupt could not be cleared SCC Receiver Status XXX SCC Base Address XXXXXXxxx Channel xx Baud Rate XXxx Error Additional error info Data transmission error occurred Possible error are framing parity or data overrun 3 106 SCC Serial Communication Controller Z85230 Tests Table 3 19 SCC Error Messages Continued Error Message SCC Receiver Error Status st Break Sequence detected in the RXD stream SCC Base Address XXXXXXXX Channel Xx Baud Rate XXXX Symptom or Cause An unexpected break was received during testing Transmit Receive Character Miscompare Error Expected x Actual xx SCC Base Addr
91. h pattern 3 79 MASK 2 11 MDMC 3 105 Memory Addressing ADR 3 73 memory march test 3 79 Memory Refresh Testing REF 3 85 MIEN 3 55 MISC 3 115 Miscellaneous Register MISC 3 115 MK48Txx BBRAM Addressing ADR 3 89 MK48Txx Timekeeping Tests RTC 3 88 Modem Control MDMC 3 105 monitor IN 17 xXmoz lt moz Index debug 1 2 Motorola Computer Group documents A 1 Mouse Device Confidence Extended MSCONF 3 28 Mouse Test MSFAT 3 29 MSCONF 3 28 MSFAT 3 29 N NCR 53C8xx SCSI I O Processor Tests 3 43 negation 4 Non Verbose Mode NV 2 12 NV 2 12 O overview of firmware 1 1 P PAL 3 116 PAR8730x Parallel Port Test 3 59 parallel interface tests 3 3 Parallel Interface Tests CSL1283 3 3 Parallel Port Test PAR8730x 3 59 pass count 2 5 PATS 3 80 PATTERN 3 37 pattern march 3 79 PC8730x Keyboard Controller Tests 3 23 PCI 3 53 3 117 PCI Access PCI 3 53 PCI Header Register Access REGA 3 12 PCI Header Verification PCI 3 117 PCI ISA Bridge Tests 3 20 PCI PMC Slot Register Access REG 3 70 PCIBUS 3 69 PCIBUS Error Messages 3 71 PED 3 81 PELM 3 118 PERM 3 83 Permutations PERM 3 83 PERREN 3 9 Pixel Mask Register PELM 3 118 PowerPC board 1 1 PPC1 Bug gt 1 2 PPC1 Diag gt 1 2 PPCBug general information 1 1 overview 1 1 Q OST 2 14 Quick Self Test OST 2 14 Quick Write Read QUIK 3 84 QUIK 3 84 R RAM 3 94 RAM Local RAM Tests 3 72
92. he following pages Table 3 17 RTC Test Group Name Description RAM Batter Backed Up RAM ADR BBRAM Addressing ALARM Alarm Interrupt Executed only when specified CLK Real Time Clock Function WATCHDOG Watchdog Time Out Reset RTC MK48Txx Timekeeping Tests ADR MK48Txx BBRAM Addressing Command Input PPCl Diag RTC ADR Description This test is designed to assure proper addressability of the MK48Txx BBRAM The algorithm used is to fill the BBRAM with data pattern a a single address line of the MK48Txx is set to one and pattern b is written to the resultant address All other locations in the BBRAM are checked to ensure that they were not affected by this write The a pattern is then restored to the resultant address All address lines connected to the MK48Txx are tested in this manner Since this test overwrites all memory locations in the BBRAM the BBRAM contents are saved in debugger system memory prior to writing the BBRAM The RTC test group features a configuration parameter which overrides automatic restoration of the BBRAM contents The default for this parameter is to restore BBRAM contents upon test completion Response Messages After the command has been issued the following line is printed RTC ADR MK48Txx RAM Addressing Running If all parts of the test are completed correctly then the test passes RTC ADR MK48Txx RAM Add
93. he device can be both accessed and that the data paths to the device are functioning Response Messages After the command has been issued the following line is printed SCC ACCESS Device Register Access Running gt If all parts of the test are completed correctly then the test passes SCC ACCESS Device Register Access Running PASSED If any part of the test fails then the display appears as follows SCC ACCESS Device Register Access Running FAILED SCC ACCESS Test Failure Data error message Refer to the section SCC Error Messages for a list of the error messages and their meaning SCC Serial Communication Controller Z85230 Tests BAUDS Baud Rates Command Input PPCl Diag scc bauds Description This test transmits 256 characters at various baud rates The data is received and compared If any protocol errors are created or the data is not correct when received the test failed The bauds tested are 1200 9600 2400 19200 4800 38400 Note Because of the design of the Z85230 when internal loopback testing is performed data is still transmitted out of the device on the TxD line This may cause problems with terminals modem printers and any other device attached Response Messages After the command has been issued the following line is printed SCC BAUDS Baud Rates cele ee NN Sie Running If all parts of the test
94. he following line is printed 28536 IRO E EE Running If all parts of the test are completed correctly then the test passes Z06536 IRQ INCE TUP he 654 x is ener star suave ete eina Running PASSED If any failures occur the following is displayed more descriptive text then follows el Ee e EE eee eis Running FAILE 28536 CNT Test Failure Data error message If the test fails because an interrupt request from the Z8536 is pending after masking the Z8536 interrupt in the IEN register the following is displayed Unexpected z8536 IRQ pending Address Expected Actual M This test makes use of the Z8536 counter to generate the test interrupt If after running the counters to terminal count an interrupt has not been requested by the Z8536 the following message is displayed z8536 IRQ not pending in IST register Address Expected Actual M 3 124 Z8536 Counter Timer Tests LNK Linked Counter Command Input PPCl Diag 28536 LNK Description This test verifies the functionality of the timers in the Z8536 Counter 1 output is linked to counter 2 input This test does not check timer accuracy Response Messages After the command has been issued the following line is printed 48536 LNK Linked Counter eee Running gt If all parts of the test are completed correctly then the test passes 28536 INK Linked Counter
95. he following line is printed VGA543X PAL Palette Register Running If all parts of the test are completed correctly then the test passes VGA543X PAL Palette Register Running PASSED If the test fails then the display appears as follows VGA543X PAL Palette Register Running FAILED VGA543X PAL Test Failure Data Palette index Value read red green blue 3 116 VGA543X Video Diagnostics Tests PCI PCI Header Verification Command Input PPCl Diag vga543x pci Description This is the PCI header verification test the purpose of which is to verify that the system has either a Cirrus Logic 5430 or 5434 graphics controller The test proceeds as follows 1 Searches the PCI bus for the Cirrus Logic 5434 controller by looking at the chip identification register If a Cirrus Logic 5434 is found the test passes 2 Searches the PCI bus for the Cirrus Logic 5430 controller by looking at the chip identification If a Cirrus Logic 5430 is found the test passes Response Messages After the command has been issued the following line is printed VGA543X PCI Cirrus vga543x PCI Access Running If all parts of the test are completed correctly then the test passes VGA543X PCI Cirrus vga543x PCI Access Running PASSED If the test fails then the display appears as follows VGA543X PCI Cirrus vga543x PCI Access Running FAILE
96. he section DEC Error Messages for a list of the error messages and their meaning DEC Ethernet Controller Tests SPACK Single Packet Send Receive Command Input PPCl Diag DEC SPACK Description This test verifies that the DEC Ethernet Controller can successfully send and receive an Ethernet packet using interrupts in internal loopback mode Response Messages After the command has been issued the following line is printed DEC SPACK Single Packet Xmit Recv Running If all parts of the test are completed correctly then the test passes DEC SPACK Single Packet Xmit Recv Running gt PASSED If any part of the test fails then the display appears as follows DEC SPACK Single Packet Xmit Recv Running FAILED DEC SPACK Test Failure Data error message Refer to the section DEC Error Messages for a list of the error messages and their meaning Test Descriptions XREGA Extended PCI Register Access Command Input PPC1 Diag gt DEC XREGA Description This test performs a read test on all of the registers in the DEC PCI header space and verifies that they contain the correct values This test verifies that the registers can be accessed and that the data paths to the device are functioning Response Messages After the command has been issued the following line is printed D EC XRE GA Extended PCI register Access Running
97. he specified memory range is then written with the test data pattern complemented before it is written The memory under test is read back to verify that the complement test data is properly retained Each memory location in the specified memory range is then written with the test data pattern The memory under test is read back to verify that the test data is properly retained 3 76 RAM Local RAM Tests Response Messages After the command has been issued the following line is printed RAI BIOG Bit Toggle isro Erkia ae aA Running If all parts of the test are completed correctly then the test passes RAI BIOG Bit TOGGLS weree deer Nee ee de Running PASSED If the test fails then the display appears as follows D RAI BIOG Bit Toggle il eR R Ye Running FAILE RAM BTOG Test Failure Data Data Miscompare Error Address Expected Actual 3 77 Test Descriptions CODE Code Execution Copy Command Input PPC1 Diag gt RAM CODE Description Copy test code to memory and execute The code in the memory under test copies itself to the next higher memory address and executes the new copy This process is repeated until there is not enough memory as specified by the configuration parameters to perform another code copy and execution Response Messages After the command has been issued the following line is printed RAM CODE Code Exec
98. hen RTS was driven CTS or RI did not follow 3 68 PCIBUS Generic PCI PMC Slot Tests PCIBUS Generic PCI PMC Slot Tests These sections describe the individual PCIBUS tests These tests are available on all PowerPC boards Entering PCIBUS without parameters causes all PCIBUS tests to run in the order shown in the table below except as noted To run an individual test add that test name to the PCIBUS command The individual tests are described in alphabetical order on the following pages Table 3 14 PCIBUS Test Group Name Description REG Register Access Test Descriptions REG PCI PMC Slot Register Access Command Input PPCl Diag pcibus reg Description The purpose of this function is to test any available PCI or PMC slots on PowerPC based boards The test loops through all possible slots for the current board The test then checks to see if the slot is inhabited if not the test is not performed If a device is present its own Built In Self Test is run if possible and the interrupt line register is written with a sixteen byte pattern Each of these bytes written is verified and finally the register is restored to its initial value Note The test will pass if all the conditions are met or if the slot is not populated some boards have multiple slots Response Messages After the command has been issued the following line is printed PCIBUS REG PCI PMC Slot Register Ac
99. hs on a CD ROM after a prior recording session has ended A video system in which every pixel is refreshed during every vertical scan A non interlaced system is normally more expensive than an interlaced system of the same resolution and is usually said to have a more pleasing appearance A memory in which the data content is maintained whether the power supply is connected or not National Television Standards Committee USA Non Volatile Random Access Memory Original Equipment Manufacturer Over Molded Pad Array Carrier Operating System The software that manages the computer resources accesses files and dispatches programs One Time Programmable The range of colors available on the screen not necessarily simultaneously For VGA this is either 16 or 256 simultaneous colors out of 262 144 A connector that can exchange data with an I O device eight bits at a time This port is more commonly used for the connection of a printer to a system Peripheral Component Interconnect local bus Intel A high performance 32 bit internal interconnect bus used for data transfer to peripheral controller components such as those for audio video and graphics GL 8 Glossary PCMCIA bus PCR PDS PHB physical address PIB pixel PLL PMC POWER PowerPC PowerPC 601 Personal Computer Memory Card International Association bus A standard external interconnect bus which allows peripherals adher
100. ice Confidence Extended Running gt FAILE D KBD8730x kbconf Test Failure Data error message Refer to the section KBD8730x Error Messages for a list of the error messages and their meaning KBD8730x Keyboard Controller Tests KBFAT Keyboard Test Command Input PPCl Diag kbd8730x kbfat Description This test performs all the tests found in the keyboard device confidence extended kbconf tests issues an echo test to the keyboard device issues a reset command to the keyboard device and reads the keyboard device ID from the keyboard to ensure that the keyboard is plugged in and functioning correctly These tests can only function with a keyboard device present Response Messages After the command has been issued the following line is printed KBD8730x KBFAT Keyboard Test s s Running If all parts of the test are completed correctly then the test passes KBD8730x KBFAT Keyboard Test Running PASSED If any part of the test fails then the display appears as follows KBD8730x KBFAT Keyboard Test Running FAILED KBD8730x KBFAT Test Failure Data error message Refer to the section KBD8730x Error Messages for a list of the error messages and their meaning Test Descriptions KCCONF Keyboard Controller Confidence Extended Command Input PPCl Diag KBD8730x KCCONF Description This test writes
101. ies 2 1 utility command entry 1 4 V Verify Cache Size SIZE 3 38 VGA controller 3 112 VGA CRT Controller Register 3 111 VGA543X Video Diagnostics Tests 3 108 Video Diagnostics Tests VGA543X 3 108 Video Memory VRAM 3 120 VME Interface ASIC Tests VME2 3 121 VME2 3 121 VME2 tests 3 121 VMEchip2 3 121 VRAM 3 120 W warnings 5 6 WATCHDOG 3 95 Watchdog Time Out Reset WATCH DOG 3 95 WBEL 3 39 WBINV 3 40 word 4 Write Back w Flush WBFL 3 39 Write Back w Invalidate WBINV 3 40 write read 3 84 WriteThru WRTHRU 3 41 WriteThru Pattern PATTERN 3 37 WRTHRU 3 41 X XREGA 3 14 Z Z8536 Counter Timer Tests 3 122 ZE 2 15 Zero Pass Count ZP 2 15 IN 19 lt ke KA Index ZP 2 15 IN 20
102. ing to the standard to be plugged in and used without further system modification PCI Configuration Register Processor Direct Slot PCI Host Bridge A binary address that refers to the actual location of information stored in secondary storage PCI to ISA Bridge An acronym for picture element and is also called a pel A pixel is the smallest addressable graphic ona display screen In RGB systems the color of a pixel is defined by some Red intensity some Green intensity and some Blue intensity Phase Locked Loop PCI Mezzanine Card Performance Optimized With Enhanced RISC architecture IBM The trademark used to describe the Performance Optimized With Enhanced RISC microprocessor architecture for Personal Computers developed by the IBM Corporation PowerPC is superscalar which means it can handle more than one instruction per clock cycle Instructions can be sent simultaneously to three types of independent execution units branch units fixed point units and floating point units where they can execute concurrently but finish out of order PowerPC is used by Motorola Inc under license from IBM The first implementation of the PowerPC family of microprocessors This CPU incorporates a memory management unit with a 256 entry buffer and a 32KB unified instruction and data cache It provides a 64 bit data bus and a separate 32 bit address bus PowerPC 601 is used by Motorola Inc under license from IBM GL 9 J
103. ion Error interrupt ncountered CERR Interrupt indicating that the AUI port collision inputs failed to activate in a timely manner after a frame was transmitted ncountered Missed Fram interrupt MISS Interrupt indicating that the receiver missed an incoming frame because there was no place to put it no buffers owned by controller Jabber Error interrupt encountered JAB Interrupt indicating that the twisted pair transmission limit has been exceeded RCVCCO Collision Counter Overflow interrupt ncountered Too many collisions have occurred 3 18 DEC Ethernet Controller Tests Table 3 4 DEC Error Messages Continued Error Message Receive interrupt occurred but no data available Symptom or Cause Controller interrupted indicating that data has been received but the incoming byte count does not reflect this Received packet is the wrong size Size of packet is not the same size as it was when it was sent Requested packet size of d illegal ust be in range NN to NNN Size of packet to send is out of boundaries as defined by standard Ethernet packet sizings Ethernet packet data mismatch Iter NNN Element NN Value sent XXXX Value returned XXXX Data in packet received does not equal data in the packet that was sent 3 19 Test Descriptions ISABRDGE PCI ISA Bridg
104. ions describe the individual Video Graphics Array VGA tests These tests are not available on the MVME230x MVME260x or MTX PowerPC boards Entering VGA543X without parameters causes all VGA tests to execute in the order shown in the table below To run an individual test add that test name to the VGA543X command The individual tests are described in alphabetical order on the following pages Table 3 20 VGA543X Test Group Name Description ATTR Attribute Registers CRTC CRT Controller Registers DSTATE DAC State Register EXTN Extended Registers GRPH Graphics Controller MISC Miscellaneous Register PAL Color Palette PCI PCI Header Verification PELM Pixel Mask Register SEOR Sequencer Registers VRAM Video Memory BLT Bit Blitter 3 108 ATTR Attribute Register Command Input VGAB543X Video Diagnostics Tests PPC1 Diag gt VGA543X ATTR Description This test verifies the correct operation of the VGA Attribute Registers The test proceeds as follows 1 Each Attribute Register is initialized with one of 256 possible values with reserved bits being masked off to a value of zero 2 The Attribute Register is read back to verify that the data that was written to the register in step 1 was written correctly Response Messages After the command VGA543X ATTR Attri has been issued the following line is printed bute Registers Running gt If all parts of the tes
105. ire tritpen inihi icu 3 12 SPACK Single Packet Bend Bemtgen riri tro PH REIR a R tM A 3 13 AREGA Extended PCI Register Access uus vip prion eia ipt uen 3 14 DEC Enor Mop PER 3 15 IK PLI7 DS Bridge Obesidad adito ton DR enini 3 20 asi eu eer re eres arene 3 21 REG Rep gel eurea E cinoma 3 22 REDS73Us Keyboard Controller TOSIe osa caedes tiun iR UEM Ap GANE 3 23 KBCONF Keyboard Device Confidence Extended 3 24 KBBAT Keyboard Desbiusceexienss treinta rbi bx EE EURO NE RN x RR RA 2 25 KCCONF Keyboard Controller Confidence Extended 3 26 KCEXT Keyboard Mouse Controller Extended Test 3 27 MSCONE Mouse Device Confidence Extended 3 28 MSERT Mouse TES iocans ia idunt br m dpa diu ed UE EAE 3 29 KBDS8730x Error Messages iaces nen etii ti erc pev Apt R tieess 3 30 Ee er Kee o o 3 34 DISUPD ER E 3 35 ENUPL Enable LIOS usscsosesso necnon hte anaana e a a pte KS uan 3 36 PATTERN Meter Patleff ssnsmanomemonissonsomanamrana 3 37 ca RR Veri E OE a 3 38 WEBEL Write Back w 7 FIGS soczscsccscsssiatscccessuceseasdsteneveesguisessstectoeieeveaiandaaess 3 39 WBINV Write Back w Invalidate eee 3 40 WEFHEU Write DB oieecistonpniaondqemqum qubd anan aonn 3 41 LACACHE Error Messages iiei ie aoak E EE EEE E EREN NEES 3 42 NCR 53C8xx SCSI I O Processor Tests siccccccesiscescnssnssessesnst
106. issued the following line is printed VGA543X DSTATE DAC State Registers Running gt If all parts of the test are completed correctly then the test passes VGA543X DSTATE DAC State Registers Running PASSED If the test fails then the display appears as follows VGA543X DSTATE DAC State Registers Running FAILED VGA543X DSTATE Test Failure Data Unexpected state read from DAC State Reg Depending upon which mode failed then the display appears as follows Expected read mode 11B Found Or Expected write mode 11B Found 3 112 VGA543X Video Diagnostics Tests EXTN Extended Registers Command Input PPCl Diag VGA543X EXTN Description This test verifies that the Extended Sequencer Graphics CRT Controller and Pel Mask Registers are correctly functioning Each possible pattern for each of the registers is used with reserved bits being masked to a value of zero 1 Each extended register is initialized with one of 256 possible values with reserved bits being masked off to a value of zero 2 The extended register is read back to verify that the data that was written to the register in step 1 was written correctly Response Messages After the command has been issued the following line is printed VGA543X EXIN Extended Registers Running If all parts of the test are completed correctly then the test passes
107. line To break the loop press the BREAK key on the diagnostic video display terminal Certain tests disable the BREAK key interrupt so it may become necessary to press the abort or reset switches on the PowerPC board front panel Example PPC1 Diag gt lc ram adr RAI ADR Addressability Running PASSED Pass Count 1 Errors This Pass 0 Total Errors 0 RAM ADR Addressability Running PASSED Pass Count 2 Errors This Pass 0 Total Errors 0 RAI ADR Addressability Running PASSED Pass Count 3 Errors This Pass 0 Total Errors 0 RAI ADR Addressability Running BREAK Break Detected PPCl Diag LE Loop On Error Mode Occasionally when an oscilloscope or logic analyzer is in use it becomes desirable to repeat a test endlessly loop while an error is detected The LE command modifies the way a failed test is endlessly repeated The LE command has no effect until a test failure occurs at which time if the LE command has been previously encountered in the user command line the failed test is re executed as long as the previous execution returns failure status To break the loop press the BREAK key on the diagnostic video display terminal Certain tests disable the BREAK key interrupt so it may become necessary to press the abort or reset switches on the PowerPC board front panel
108. line being parsed by the diagnostic monitor Example PPCl Diag aem ram ref RAM REF Memory Refresh Test Running FAILE D error message written to error message buffer PPCl Diag 2 2 Utilities CEM Clear Error Messages This command allows you to clear the internal error message buffer of the diagnostic monitor manually Example PPC1 Diag gt cem error message buffer is cleared PPC1 Diag gt CF Test Group Configuration Parameters Editor The CF parameters control the operation of all tests in a test group For example the RAM test group has parameters such as starting address ending address parity enable etc At the time of initial execution of the diagnostic monitor the default configuration parameters are copied from the firmware into the debugger work page Here you can modify the configuration parameters via the CF command When you invoke the CF command you are interactively prompted with a brief parameter description and the current value of the parameter You may enter a new value for that parameter or a RETURN to accept the current value and proceed to the next configuration parameter To discontinue the interactive process enter a period followed by RETURN You may specify one or more test groups as argument s immediately following the CF command on the command line If no arguments follow the CF command the parameters for all test groups are p
109. n resolution of 640 x 480 pixels A binary address issued by a CPU that indirectly refers to the location of information in primary memory such as main memory When data is copied from disk to main memory the physical address is changed to the virtual address See VESA Local bus VL bus MCG second generation VMEbus interface ASIC Motorola MCG ASIC that interfaces between the PCI bus and the VME chip2 device A memory in which the data content is lost when the power supply is disconnected Video Dynamic Random Access Memory Memory chips with two ports one used for random accesses and the other capable of serial accesses Once the serial port has been initialized with a transfer cycle it can operate independently of the random port This frees the random GL 13 J oooro 2 o0o00r o Glossary Windows NT XGA Y Signal port for CPU accesses The result of adding the serial port is a significantly reduced amount of interference from screen refresh VRAMs cost more per bit than DRAMs The trademark representing Windows New Technology a computer operating system developed by the Microsoft Corporation EXtended Graphics Array An improved IBM VGA monitor standard that provides at least 256 simultaneous colors and a screen resolution of 1024 x 768 pixels Luminance This determines the brightness of each spot pixel on a CRT screen either color or B W systems but not the color GL 14
110. nd Electronics Engineers Inc Publication and Sales Department 345 East 47th Street New York New York 10017 21633 Telephone 1 800 678 4333 Document Title and Source Ve Number IEEE Standard for Local Area Networks Carrier Sense Multiple Access IEEE 802 3 Information Technology Local and Metropolitan Networks Part 3 Carrier Sense Multiple Access with Collision Detection CSMA CD Access Method and Physical Layer Specifications Global Engineering Documents 15 Inverness Way East Englewood CO 80112 5704 Telephone 1 800 854 7179 Telephone 303 792 2181 This document can also be obtained through the national standards body of member countries ISO IEC 8802 3 Interface Between Data Terminal Equipment and Data Circuit Terminating Equipment Employing Serial Binary Data Interchange EIA 232 D Electronic Industries Association Engineering Department 2001 Eye Street N W Washington D C 20006 ANSI EIA 232 D Standard A 11 A A Related Documentation Glossary Abbreviations Acronyms and Terms to Know This glossary defines some of the abbreviations acronyms and key terms used in this document 10Base 5 10Base 2 10Base T 100Base TX ACIA AIX architecture ASCII An Fthernet implementation in which the physical medium is a doubly shielded 50 ohm coaxial cable capable of carrying data at 10 Mbps for a length of 500 meters also referred to as thicknet Also known
111. ndard ISA bus system Enhanced Parallel Port GL 4 Glossary EPROM ESCC ESD Ethernet Falcon fast Ethernet FDC FDDI FIFO firmware frame graphics controller HAL Erasable Programmable Read Only Memory A memory storage device that can be written once per erasure cycle and read many times Enhanced Serial Communication Controller Electro Static Discharge Damage A local area network standard that uses radio frequency signals carried by coaxial cables The DRAM controller chip developed by Motorola for the MVME2600 and MVME3600 series of boards It is intended to be used in sets of two to provide the necessary interface between the Power PC60x bus and the 144 bit ECC DRAM system memory array and or ROM Flash See 100Base TX Floppy Disk Controller Fiber Distributed Data Interface A network based on the use of optical fiber cable to transmit data in non return to zero invert on 1s NRZI format at speeds up to 100 Mbps First In First Out A memory that can temporarily hold data so that the sending device can send data faster than the receiving device can accept it The sending and receiving devices typically operate asynchronously The program or specific software instructions that have been more or less permanently burned into an electronic component such as a ROM read only memory or an EPROM erasable programmable read only memory One complete television picture frame consists
112. ng a possible bus error or faulty interface to the keyboard controller Keyboard Interface test failed Clock Data line is stuck high low There is a problem with the interface to the keyboard device or the keyboard device itself One of the data or clock lines is not operating correctly Keyboard Interface test failed Invalid test result from controller There was a complete failure of the interface test to the keyboard device May be a problem with the embedded firmware itself Keyboard Echo test failed Invalid result code XX The echo test to the keyboard failed indicating that the keyboard may not be present or working properly 3 32 KBD8730x Keyboard Controller Tests Table 3 7 KBD8730x Error Messages Continued Error Message Keyboard Internal Diagnostic test failure Check keyboard Invalid result code x from Keyboard Internal Diagnostic test Symptom or Cause The keyboard device internal diagnostics test failed indicating a problem with the keyboard device itself Invalid ACK from Keyboard Read ID test Getting XX Keyboard device failed to send an Acknowledge byte indicating that it may be not present or working correctly Keyboard Read ID failed First Second byte XX should be XX Keyboard sending the wrong ID byte s back indicating wrong device type being used or a problem with the device Mouse Interface test failed
113. nostics you should ensure that your PowerPC board and other hardware have been properly configured and connected according to the installation guide for your PowerPC board You also need the two volume manual for the PPCBug Debugging Package PPCBug Firmware Package User s Manual It contains a complete description of PPCBug the start up procedure descriptions of all general software debugging commands and other information you need to know about the debugger 1 1 General Information Overview of PPCBug Firmware The PPCBug firmware consists of three parts A command driven user interactive software debugger described in the PPCBug Firmware Package User s Manual A command driven diagnostics package for the PowerPC board hardware described in this manual The diagnostic firmware contains a battery of utilities and tests for exercise test and debug of hardware in the PowerPC board environment The diagnostics are menu driven for ease of use a A user interface or debug diagnostics monitor that accepts commands from the system console terminal The tests described in this manual are called commands are input and results reported via this monitor the common system monitor used for the debugger and the diagnostics The monitor is command line driven and provides input output facilities command parsing error reporting interrupt handling and a multi level directory for menu selection Debugger and Diagnos
114. on Copy PPCl Diag This displays information on the RAM Code Execution Copy test routine Diagnostic Utilities HEX Help Extended The HEX command goes into an interactive continuous mode of the HE command The prompt displayed for HEX is the question mark You may then type the name of a directory or command You must type QUIT to exit Example PPCl Diag HEX Extended Help Type QUIT to Exit lc LC Loop Continuous Mode ISABRDGE irq ISABRDGE ISA Bridge Tests DIR IRO Interrupt Request quit PPCl Diag LA Loop Always Mode To repeat a test or series of tests endlessly enter the prefix LA The LA command modifies the way that a failed test is endlessly repeated The LA command has no effect until a test failure occurs at which time if the LA command has been previously encountered in the user command line the failed test is endlessly repeated To break the loop press the BREAK key on the diagnostic video display terminal Certain tests disable the BREAK key interrupt so it may become necessary to press the abort or reset switches on the PowerPC board front panel Example PPC1 Diag gt la ram adr RAM ADR Addressability Running gt PASSED no errors detected so LA is ignored PPCl Diag 2 8 Utilities LC Loop Continue Mode To repeat a test or series of tests endlessly enter the prefix LC This loop includes everything on the command
115. ons a refresh wait cycle is executed After the wait cycle the data is read and if the previously entered data pattern does not match the data pattern read in a failure occurs If the data patterns match then the test is passed Response Messages After the command has been issued the following line is printed RAI REF Memory Refresh Test Running If all parts of the test are completed correctly then the test passes RAI REF Memory Refresh Test Running PASSED If any part of the test fails then the display appears as follows RAI REF Memory Refresh Test Running FAILED RAM REF Test Failure Data error message Here error message is one of the following If the real time clock is not functioning properly one of the following is printed RIC is stopped invoke SET command Test Descriptions Or RTC is in write mode invoke SET command Or RIC is in read mode invoke SET command If a data verification error occurs before the refresh wait cycle Immediate Data Miscompare Error Address Expected Actual If a data verification error occurs following the refresh wait cycle Unrefreshed Data Miscompare Error Address Expected Actual 3 86 RAM Local RAM Tests RNDM Random Data Command Input PPCl Diag RAM RNDM Description
116. ormation refer to the following table for manufacturers data sheets or user s manuals As an additional help a source for the listed document is also provided Please note that in many cases the information is preliminary and the revision levels of the documents are subject to change without notice To further assist your development effort Motorola has collected some of the non Motorola documents in this list from the suppliers This bundle can be ordered as part number LK PCIKIT2 Table A 2 Manufacturers Documents Literature Distribution Center for Motorola Telephone 800 441 2447 FAX 602 994 6430 or 303 675 2150 E mail Idcformotorola hibbertco com OR IBM Microelectronics Mail Stop A25 862 1 PowerPC Marketing 1000 River Street Essex Junction Vermont 05452 4299 Telephone 1 800 PowerPC Telephone 1 800 769 3772 FAX 1 800 POWERfax FAX 1 800 769 3732 Document Title and Source EEN Number PowerPC 603 RISC Microprocessor Technical Summary MPC603 D Literature Distribution Center for Motorola Telephone 800 441 2447 FAX 602 994 6430 or 303 675 2150 E mail ldcformotorola hibbertco com PowerPC 603 RISC Microprocessor User s Manual MPC603UM AD MPR603UMU 01 A A Related Documentation Table A 2 Manufacturers Documents Continued Publication Number PowerPC 604 RISC Microprocessor User s Manual MPC604UM AD Literature Distribution Center for
117. osdessecsvossisvesvoresasten 3 43 ALUL e Der E ACE ai gatiarn odisse dta iip m i E 3 44 e Register AQCeSS Lo nada E HR RR 3 46 DEB DMA BUS isesecscdienc t nd tede acide denken iiA deu aa dU 3 48 He ences tbo sides diii Cum des R e p aM EMEN iE 3 50 I REM t P 3455 SCRIPTS SCRIPTS ERIOGBBOE acad naci tinc cn ine alien 3 55 CLR ES NONI M NN 3 58 PARS 30x Parallel Port DB uu aens ein Pte ducc dona UN Dat A rada 3 99 an eE E E E EES 3 60 UART Serial Input Output TSB egiegegteteeemgrgeeeieueeugeegeeggbeieriegeeg 3 61 BAUT Panid Ral E 3 62 TIRO Interiupt EM ageet eana E 3 63 LPBK Internal Loopback srscrcr e ea are raa 3 64 EPBKE External Loopback cancncuanciuirnindainannienneies 3 65 REGA Device Register ACCES ucnun dekanai 3 66 VART WE 3 67 PCIBUS Generic PCI PMC Slot Tests 3 69 REG PCI PMC Slof Register ACEOIS uiae pda bed dp rad dU UA EEG 3 70 PUCIBUS Error NIS ose diei e x Pal rao bod puerpera 3 71 RAM Local RAM Teste ccsscsiscsiasssniscissnnasiarennncnennimnnnrarneaonannuanaes 3 72 ADR Memory Acitesetne scenes deed triticum arti n equa dre pu NUR 3 73 ALIS Alternating Mr Ou EE 3 75 BTG Bit Toggle tt ten RII ee n M E EORR RUD IRE E cedi 3 76 CODE Code Exerollan fC esencesoisasin Puit QU M PH 3 78 MARCH Mareh Pater th M 3 79 Dios Liata EE 3 80 PED Local Parity Memory Error Detection secas osito iens 3 81 PERM Permuta ONS rimena oda etui ESI DX PA CHIEN I one Ea duse Eia 3 83 OUTK
118. pt for two that only execute if specified Subdirectory Level Command Individual Test Entering the name of a test group followed by the name of an individual test from that group causes just that test to execute For example to call up a particular Random Access Memory RAM test enter PPCl Diag RAM ADR This causes the monitor to find the RAM test group subdirectory and then to execute the Memory Addressing test command ADR from that subdirectory To call up a particular DEC test enter PPCl Diag DEC REGA 1 4 Command Entry This causes the monitor to find the DEC test group subdirectory and then to execute the PCI Register Access command REGA from that subdirectory Multiple Subdirectory Level Commands Individual Tests If the first part of a command is a test group name any number and or sequence of tests from that test group may be entered after the test group name so long as the debugger s input buffer size limit is not exceeded For example PPCl Diag RAM PATS ADR This causes both the Data Patterns PATS and the Memory Addressing ADR tests from the RAM test group to execute Multiple Root Level Commands Test Groups Multiple commands may be entered If a command expects parameters and another command is to follow it separate the two with a semicolon For example to invoke the command RTC CLK to execute the Real Time Clock Function test from the MK48Txx Real Time Clock test group
119. r Access Running PASSED If the board does not support the CL1283 the following is displayed CL1283 REG c11283 Register Access Running BYPASSED If any failures occur the following is displayed more descriptive text then follows CL1283 REG c11283 Register Access Running FAILED If the test fails because the pattern written does not match the one read back from the CL1283 register the following is printed CS4231 INDIRECT Local Parity Memory Detection Running FAILED c11283 Register xxx Expected bitt to be high low Actual reg value xx DEC Ethernet Controller Tests DEC Ethernet Controller Tests These sections describe the individual DEC21x40 Ethernet Controller tests Entering DEC without parameters causes all DEC tests to run in the order shown in the table below except as noted To run an individual test add that test name to the DEC command The individual tests are described in alphabetical order on the following pages Table 3 3 DEC Test Group Name Description REGA Register Access XREGA Extended Register Access SPACK Single Packet Transmit and Receive ILR Interrupt Line Register Access ERREN PERREN and SERREN Bit Toggle IOR I O Resource Register Access CINIT Chip Initialization Executed only when specified CLOAD Continuous Load CNCTR Connector None of these tests need any external hardware
120. range is the memory range specified by the RAM test group configuration parameters for starting and ending address If the test address range test range is less than 16 bytes the test immediately returns pass status The effective test range end address is reduced to the next lower 16 byte boundary if necessary This test performs three data size test phases in the following order 8 16 and 32 bits Each test phase writes a 16 byte data pattern using its data size to the first 16 bytes of every 256 byte block of memory in the test range The 256 byte blocks of memory are aligned to the starting address configuration parameter for the RAM test group The test phase then reads and verifies the 16 byte block using 8 bit 16 bit and 32 bit access modes Response Messages After the command has been issued the following line is printed RAI PERM Permutations ee ee eee Running gt If all parts of the test are completed correctly then the test passes RAI PERM Permutations A Running PASSED If the test fails then the display appears as follows RAI PERM Perm tationls w 4 deste races REesrgese Running FAILED RAM PERM Test Failure Data Data Miscompare Error Address Expected Actual Test Descriptions QUIK Quick Write Read Command Input PPCl Diag ram quik Description Each pass of this test fills the test range with a data pat
121. red for a non interlaced system of the same resolution This results in less costly hardware It also may make it possible to display a resolution that would otherwise be impossible on given hardware The disadvantage of an interlaced system is flicker especially when displaying objects that are only a few scanlines high Similar to the color difference signals R Y B Y but using different vector axis for encoding or decoding Used by some USA TV and IC manufacturers for color decoding Industry Standard Architecture bus The de facto standard system bus for IBM compatible computers until the introduction of VESA and PCI Used in the reference platform specification IBM ISA Super Input Output device GL 6 Glossary ISDN LAN LED LFM little endian MBLT MCA bus MCG MFM MIDI MPC MPC105 MPC601 MPC603 MPC604 MPIC MPU MTBF Integrated Services Digital Network A standard for digitally transmitting video audio and electronic data over public phone networks Local Area Network Light Emitting Diode Linear Feet per Minute A byte ordering method in memory where the address n of a word corresponds to the least significant byte In an addressed memory word the bytes are ordered left to right 3 2 1 0 with 3 being the most significant byte Multiplexed BLock Transfer Micro Channel Architecture Motorola Computer Group Modified Frequency Modulation Musical Instrument Digital Interfac
122. resented so you may change them if you wish Examples PPC1 Diag cf RAM Configuration Data Starting Ending Address Enable Y N N RETURN Starting Address 00004000 RETURN Ending Address 00F84FFC RETURN 2 3 Diagnostic Utilities Random Data Seed 12301983 RETURN March Address Pattern 00000000 RETURN Instruction Code Cache Enable Y N Y RETURN PPCl Diag cf scc SCC Configuration Data SCC Memory Space Base Address 80000840 RETURN Internal Loopback Baud Rates Port Mask 00000003 RETURN External Loopback Modem Control Port Mask 00000003 RETURN PPC1 Diag gt DE Display Error Counters Each test or command in the diagnostic monitor has an individual error counter As errors are encountered in a particular test that error counter is incremented If you were to run a self test or just a series of tests the results could be broken down as to which tests passed by examining the error counters To display all error counters after the conclusion of a test enter DE DE displays the results of a particular test if the name of that test follows DE Only nonzero values are displayed Example PPCl Diag de ram addr PPCl Diag DEM Display Error Messages This command allows you to display dump the internal error message buffer of the diagnostic monitor manually Example PPCl Diag dem contents of error message buffer are displayed PPCl Diag 2 4 Utilitie
123. ressing Running gt PASSED If any part of the test fails then the display appears as follows RTC ADR MK48Txx RAM Addressing Running gt FAILED RTC ADR Test Failure Data error message Test Descriptions Here error message is one of the following If debugger system memory cannot be allocated for use as a save area for the BBRAM contents RAM allocate memc next memc size If the BBRAM cannot be initialized with pattern a Data Verify Error Address Expected _ Actual Memory initialization error If a pattern b write affects any BBRAM location other than the resultant address Data Verify Error Address Expected __ Actual _ Memory addressing error wrote __ to 3 90 RTC MK48Txx Timekeeping Tests ALARM Alarm Interrupt Command Input PPCl Diag rtc alarm Description This test sets the alarm of the Real Time Clock RTC MK48Txx to go off every second and verifies that interrupt IRQ8 occurs and the AF Alarm Flag bit of the RTC is set Response Messages After the command has been issued the following line is printed RIC ALARM MK48Txx Alarm Interrupt Running gt If all parts of the test are completed correctly then the test passes RTC ALARM MK48Txx Alarm Interrupt Running PASSED LAI If any part of the test fails
124. rola Computer Group Documents The publications listed below are on related products and some may be referenced in this document If not shipped with this product manuals may be purchased by contacting your local Motorola sales office Please note that exact titles and part numbers of the documents are subject to change without notice Table A 1 Motorola Computer Group Documents Document Title Sane MVME2600 Series Single Board Computer Installation and Use V2600A IH MVME2600 Series Single Board Computer Programmer s Reference V2600A PG Guide MVME3600 Series Single Board Computer Installation and Use V3600A IH MVME4600 Series VME Processor Module Installation and Use 4 V4600A IH MVME3600 4600 Series VME Processor Modules Programmer s Reference V3600A PG Guide MVME2300 VME Processor Module Installation and Use V2300A IH MVME2300 VME Processor Module Programmer s Reference Guide V2300A PG MTX Embedded ATX Motherboard Installation and Use MTXA IH MTX Embedded ATX Motherboard Programmer s Reference Guide MTXA PG PMCSpan PMC Adapter Carrier Module Installation and Use PMCSPANA IH PPCBug Firmware Package User s Manual Parts 1 and 2 2 3 4 5 6 PPCBUGA1 UM PPCBUGA2 UM PPCBug Diagnostics Manual 3 BP PPCDIAA UM MVME712M Transition Module and P2 Adapter Board Installation and VME712MA IH Use MVME 761 Transition Module Installation and Use VME761A IH A Rela
125. ronously and may include start bits stop bits and or parity Serial Interface Module Single Inline Memory Module A small circuit board with RAM chips normally surface mounted on it designed to fit into a standard slot GL 11 J o0ooro 2 o0o00r o Glossary SIO SMP SMT software SRAM SSBLT standard s SVGA Teletext thick Ethernet thin Ethernet twisted pair Ethernet UART Super I O controller Symmetric MultiProcessing A computer architecture in which tasks are distributed among two or more local processors Surface Mount Technology A method of mounting devices such as integrated circuits resistors capacitors and others on a printed circuit board characterized by not requiring mounting holes Rather the devices are soldered to pads on the printed circuit board Surface mount devices are typically smaller than the equivalent through hole devices A computing system is normally spoken of as having two major components hardware and software Software is the term used to describe any single program or group of programs languages operating procedures and documentation of a computer system Software is the real interface between the user and the computer Static Random Access Memory Source Synchronous BLock Transfer A set of detailed technical guidelines used as a means of establishing uniformity in an area of hardware or software development Super Video Graphics Array IB
126. rrupt Line register mismatch error Value sent NNN Value returned NNN The value read is not the same as what was written indicating that there is a problem storing data in the PCI Header register space Unable to set reset the PERREN SERREN bit in the PCI command register Inability to toggle bits in the PCI command register which may indicate faulty interface to the PCI header registers Unsolicited Exception Exception Time IP NNN Vector NNN An interrupt occurred where it was not supposed to usually because of a bus error indicating a basic system problem interfacing to the controller 3 16 DEC Ethernet Controller Tests Table 3 4 DEC Error Messages Continued Transmit of LCAR Error Message Ethernet Packet Failed Lost Carrier Symptom or Cause Carrier Signal got lost during a packet transmit in AUI or TP twisted pair mode Checksum CRC Transmit of Ethernet Packet Failed Lat A Collision occurred after Collision LCOL the slot time of the channel had elapsed Transmit of Ethernet Packet Failed Too many Transmit failed too many Retries RTRY times indicating a transmission problem over the network Transmit of Ethernet Packet Failed Buffer Error ENP flag not found at the BUFF end of a transmitted frame and the next packet is not owned by controller
127. rs during this process If no errors are detected the NCR device is reset otherwise the device is left in the test state Response Messages After the command has been issued the following line is printed NCR PCL PCI ACCESS ok iis wr x x esu ee Running If all parts of the test are completed correctly then the test passes NCR PLS PCL ACCESS oi ek ye e eR Running PASSED If any part of the test fails then the display appears as follows WER PCI POT ACCESS ie eben eim es Running FAILED NCR PCI Test Failure Data error message Here error message is one of the following Unsolicited Exception Exception Time IP XXXXXXX Vector nnnn Test Descriptions If it happens that the exception is a bus error more information follows Data Access Machine Check Information Address xXxXXXXXX Data dddddddd Access Size nnnn Access Type XXXX Address Space Code xxxx bus error vector XXXXXXXX Notes 1 All error message data is displayed as hexadecimal values 2 Access Size is displayed in bytes 3 Access Type is 0 write or 1 read 3 54 NCR 53C8xx SCSI I O Processor Tests SCRIPTS SCRIPTs Processor Command Input PPCl Diag NCR SCRIPTS Description This test initializes the test structures and makes use of the diagnostic registers for test as follows a Verifies that the following registers are initially clear SIEN SCSI Interrupt Enable DIEN D
128. ry Having big endian and little endian byte ordering capability A byte ordering method in memory where the address n of a word corresponds to the most significant byte In an addressed memory word the bytes are ordered left to right 0 1 2 3 with 0 being the most significant byte Basic Input Output System This is the built in program that controls the basic functions of communications between the processor and the I O peripherals devices Also referred to as ROM BIOS Bit Boundary BLock Transfer A type of graphics drawing routine that moves a rectangle of data from one area of display memory to another The data specifically need not have any particular alignment BLock Transfer The term more commonly used to refer to a PCB printed circuit board Basically a flat board made of nonconducting material such as plastic or fiberglass on which chips and other electronic components are mounted Also referred to as a circuit board or card bits per inch bits per second The pathway used to communicate between the CPU memory and various input output devices including floppy and hard disk drives Available in various widths 8 16 and 32 bit with accompanying increases in speed A high speed memory that resides logically between a central processing unit CPU and the main memory This temporary memory holds the data and or GL 2 Glossary instructions that the CPU is most likely to use over and over
129. ry 2730 Orchard Parkway San Jose CA 95134 Telephone 1 408 943 6666 FAX 1 408 943 6668 W83C553 Universe User Manual Tundra Semiconductor Corporation 603 March Road Kanata ON K2K 2M5 Canada Telephone 1 800 267 7231 Telephone 613 592 1320 OR 695 High Glen Drive San Jose California 95133 USA Telephone 408 258 3600 FAX 408 258 3659 Universe Part Number 9000000 MD303 01 A A Related Documentation Related Specifications For additional information refer to the following table for related specifications As an additional help a source for the listed document is also provided Please note that in many cases the information is preliminary and the revision levels of the documents are subject to change without notice Table A 3 Related Specifications Document Title and Source Publication Number ANSI Small Computer System Interface 2 SCSI 2 Draft Document X3 131 1990 Global Engineering Documents 15 Inverness Way East Englewood CO 80112 5704 Telephone 1 800 854 7179 Telephone 303 792 2181 VME64 Specification ANSI VITA 1 1994 VITA VMEbus International Trade Association 7825 E Gelding Drive Suite 104 Scottsdale Arizona 85260 3415 Telephone 602 951 8866 FAX 602 951 0720 NOTE An earlier version of this specification is available as Versatile Backplane Bus VMEbus ANSI IEEE Institute of Electrical and Electronics Engineers Inc Standard 1014 1987 Publication
130. s DP Display Pass Count HE Help A count of the number of passes in Loop Continue LC mode is kept by the monitor This count is displayed with other information at the conclusion of each pass To display this information without using LC enter DP Example PPC1 Diag gt dp Pass Count 19 PPC1 Diag gt The Help command provides on line documentation Entering HE at the diagnostics prompt PPc1 Diag gt displays a menu of the top level directory of utility commands and test group names if no parameters are entered or the menu of a subdirectory if the name of that subdirectory or test group name is entered following HE The display of the top level directory lists DIR after the name of each command that has a subdirectory Note If HE is entered to the debugger prompt ppci Bug gt the debugger commands will be displayed Examples To display the menu of all utility and test group names enter PPC1 Diag gt he see Figure 2 1 When a men is too long to fit on the screen it pauses until you press RETURN again 2 5 Diagnostic Utilities PPC1 Diag gt he Append Error Messages Mode Clear Error Messages Configuration Editor Parallel Interface CL1283 Tests DIR cs4231 Audio Codec DIR Display Errors Ethernet Controller DEC21x40 Tests DIR Display Error Messages Display Pass Count Help on Tests Commands Help Extended E ISA Bridge Tests DIR KBD8730X Keyboard Mouse Controller Tests
131. s the Real Time Clock will reset the board Response Messages After the command has been issued the following line is printed RTC WATCHDOG MK48Txx Battery Backed Up RAM Running If all parts of the test are completed correctly then the test passes by resetting the board If the test fails then the display appears as follows RTC WATCHDOG MK48Txx Battery Backed Up RAM Running FAILE D RIC WATCHDOG Test Failure Data error message Here error message is the following If the Watchdog Timer failed to reset the microprocessor when a time out condition occurred error message is Processor reset failed to occur If the WDT bit failed to be set when a time out condition occurred error message is WDF Watchdog Flag bit was not set Test Descriptions SCC Serial Communication Controller 285230 Tests These sections describe the individual Serial Communication Controller SCC tests These tests are not available on the MVME230x boards Entering SCC without parameters causes all SCC tests to run in the order shown in the table below except as noted To run an individual test add that test name to the SCC command The individual tests are described in alphabetical order on the following pages Table 3 18 SCC Test Group Name Description IRQ Interrupt Request Executed only when specified BAUDS Baud Rates ELPBCK External Loop
132. s to terminal count an interrupt has not been requested by the ISABRDGE the following message is displayed ISABRDGE IRQ Test Failure Data ISABRDGE IRQ not pending in IST register Address Expected Actual Test Descriptions REG Register Command Input PPC1 Diag gt ISABRDGE REG Description This test verifies that the ISABRDGE registers can be written and read Data patterns verify that every read write bit can be modified Response Messages After the command has been issued the following line is printed TSABRDGE REG Register e pr re rhe Running If all parts of the test are completed correctly then the test passes ISABRDGE REG Register eee Running PASSED If any failures occur the following is displayed more descriptive text then follows ISABRDGE REG Register e nie a Running FAILED If the test fails because the pattern written does not match the data read back from the ISABRDGE register the following is printed ISABRDIGE LNK Test Failure Data Register xxx Miscompare Error Address Expected _ Actual _ KBD8730x Keyboard Controller Tests KBD8730x Keyboard Controller Tests These sections describe the individual PC8730x Keyboard Controller Mouse and Keyboard Device tests Entering KBD8730x without parameters causes all KBD8730x tests to run in the order
133. se Messages After the command has been issued the following line is printed NCR BEIEO DMA FIFO 2 34 6 279 ee CN Running If all parts of the test are completed correctly then the test passes NCR DEIFO DME EEXEO ge Ne IUe Running PASSED If any part of the test fails then the display appears as follows NER DEIFOS DMA FIFO osas ekanda Berane beso fe Running FAILED NCR DFIFO Test Failure Data error message Here error message is one of the following DMA FIFO is not initially empty DMA FIFO Byte Control not enabled Address Expected Actual __ t M DMA FIFO Byte Control Error Address Expected Actual __ t M 3 48 NCR 53C8xx SCSI I O Processor Tests DMA FIFO Empty Full Error Address Expected __ Actual _ DMA FIFO Parity Error Address Expected __ Actual __ DMA FIFO Byte Lane _ DMA FIFO Error Address Expected __ Actual __ DMA FIFO Byte Lane _ 3 49 Test Descriptions IRQ Interrupts Command Input PPCl Diag NCR IRQ Description This test verifies that interrupts can be generated and received and that the appropriate status is set Response Messages After the command has been issued the following line is printed NCR IRQ NCR 53C8xx Interrupts Running If all parts of the test are completed correctly then the test passes NCR IRQ NCR 53C
134. shown in the table below except as noted To run an individual test add that test name to the KBD8730x command The individual tests are described in alphabetical order on the following pages Table 3 6 KBD8730x Test Group Name Description KCCONF Keyboard Controller Confidence KBCONF Keyboard Device Confidence Extended MSCONF Mouse Device Confidence Extended Executed only when specified KCEXT Keyboard Mouse Controller Extended Test KBFAT Keyboard Test MSFAT Mouse Test There are no configuration parameters for these tests The KBFAT and MSFAT tests assume that there is a keyboard and a mouse present otherwise they will fail The other tests need not have any keyboard or mouse connected in order to operate successfully Test Descriptions KBCONF Keyboard Device Confidence Extended Command Input PPC1 Diag gt KBD8730x KBCONF Description This test performs an interface test of the keyboard controller to ensure correct operation of the interface to the keyboard device Response Messages After the command has been issued the following line is printed KBD8730x kbcon Keyboard Device Confidence Extended Running gt If all parts of the test are completed correctly then the test passes KBD8730x kbconf Keyboard Device Confidence Extended Running gt PASSED If any part of the test fails then the display appears as follows KBD8730x kbconf Keyboard Dev
135. st Command Input PPCl Diag UART IRQ Description This test verifies that the UARTs can generate interrupts to the local processor This is done using the transmitter empty interrupt from the UART under test Response Messages After the command has been issued the following line is printed UART IRQ Interrupt Request Running If all parts of the test are completed correctly then the test passes UART IRQ Interrupt Request Running gt PASSED If any part of the test fails then the display appears as follows UART IRQ Interrupt Request Running gt FAILED UART IRQ Test Failure Data error message Refer to the section LLART Error Messages for a list of the error messages and their meaning Test Descriptions LPBK Internal Loopback Command Input PPCl Diag UART lpbk Description This test transmits 18 characters at 9600 baud The data is received and compared If any protocol errors are created or the data is not correct when received the test failed Response Messages After the command has been issued the following line is printed UART LPBK Internal Loopback Running If all parts of the test are completed correctly then the test passes UART LPBK Internal Loopback Running PASSED If any part of the test fails then the display appears as follows UART LPBK Internal Loopback Running
136. t are completed correctly then the test passes VGA543X ATTR Attri If the test fails then VGA543X ATTR Attribute Registers VGA543X ATTR Test Fail Read Register Value Read bute Registers Running gt PASSED the display appears as follows ics E d aere ees Running FAILE el ure Data Index register Expected 3 109 Test Descriptions BLT Bit Blitter Command Input PPCl Diag vga543x blt Description This test verifies that the Bit Blitter of the Cirrus Logic CL 543X chip is functioning correctly by invoking a blitter operation to copy a block of data from system memory to video DRAM then invoking a blitter operation to copy the block from one area in video DRAM to another and then finally a blitter operation to copy the block of data back into system memory The contents of the original block of system memory are compared to that of the destination block The test fails if the block which was blittered does not match the original block Response Messages After the command has been issued the following line is printed VGA543x BLT Cirrus vga543x bitblt Running If all parts of the test are completed correctly then the test passes VGA543x BLT Cirrus vga543x bitblt Running PASSED If any part of the test fails then the display appears as follows VGA543x BLT Cirrus vga543x bitblt
137. t selected modem control lines and that the appropriate input control functions properly This test does require an external loopback connector to be installed For this test the following connections need to be made in the loopback connector DTR connected to DCD RTS connected to CTS and DSR Note that DTR is asserted through the Z8536 not the Z85230 in this test Response Messages After the command has been issued the following line is printed SCC MMC Modem Control ts Running If all parts of the test are completed correctly then the test passes SC MORE Modem Control eene eR Running PASSED If any part of the test fails then the display appears as follows SCC MDMC Modem Control eee Running FAILED SCC MDMC Test Failure Data error message Refer to the section SCC Error Messages for a list of the error messages and their meaning 3 105 Test Descriptions SCC Error Messages The SCC test group error messages generally take the following form SCC BAUDS Baud Rates SCC BAUDS Test Failure Data Transmit Receive Character Miscompare Error Expected 55 Actual 5F SCC Base Address 80000840 Channel 01 Baud Rate 1200 Running FAILED The first line of the failure identifies what type of failure occurred The following line provides additional information about the failure Table 3 19 SCC Error Messa
138. ted Documentation Notes 1 Although not shown in the above list each Motorola Computer Group manual publication number is suffixed with characters that represent the revision level of the document such as xx2 the second revision of a manual a supplement bears the same number as the manual but has a suffix such as xx2A1 the first supplement to the second revision of the manual 2 Motorola documents marked with a in the above list can be purchased as a set under part number LK 2600A The content of this set is revised as needed and without any notice to the customer 3 Motorola documents marked with a in the above list can be purchased as a set under part number LK 3600A The content of this set is revised as needed and without any notice to the customer 4 Motorola documents marked with a 4 in the above list can be purchased as a set under part number LK 4600 The content of this set is revised as needed and without any notice to the customer 5 Motorola documents marked with a 5 in the above list can be purchased as a set under part number LK 2300 The content of this set is revised as needed and without any notice to the customer 6 Motorola documents marked with a in the above list can be purchased as a set under part number LK MTX The content of this set is revised as needed and without any notice to the customer Manufacturers Documents Manufacturers Documents For additional inf
139. tern by writing the current data pattern to each memory location from a local variable and reading it back into that same register The local variable is verified to be unchanged only after the write pass through the test range This test uses a first pass data pattern of 0 and FFFFFFFF for the second pass This test is coded to use only 32 bit data entities Response Messages After the command has been issued the following line is printed RAI QUIK Quick Write Read Running If all parts of the test are completed correctly then the test passes RAI QUIK Quick Write Read Running PASSED If the test fails then the display appears as follows RAI QUIK Quick Write Read Running FAILED RAM QUIK Test Failure Data Data Miscompare Error Expected Actual RAM Local RAM Tests REF Memory Refresh Testing Command Input PPCl Diag RAM REF Description The memory range and address increment is specified by the RAM test directory configuration parameters Refer to CF Test Group Configuration Parameters Editor in Chapter 2 First the real time clock is checked to see if it is functioning properly Second each memory location to be tested has the data portion verified by writing verifying all zeros and all ones Next a data pattern is written to the test location After all the data patterns are filled for all test locati
140. test does require an external loopback connector to be installed For this test the following connections need to be made in the loopback connector TxD connected to RxD Response Messages After the command has been issued the following line is printed SCC ELPBCK External Loopback Running If all parts of the test are completed correctly then the test passes SCC ELPBCK External Loopback Running PASSED If any part of the test fails then the display appears as follows SCC ELPBCK External Loopback Running FAILED SCC ELPBCK Test Failure Data error message Refer to the section SCC Error Messages for a list of the error messages and their meaning 3 102 SCC Serial Communication Controller Z85230 Tests ILPBCK Internal Loopback Command Input PPCl Diag SCC ILPBCK Description This test transmits 256 characters at 38400 baud The data is received and compared If any protocol errors are created or the data is not correct when received the test failed Note Because of the design of the Z85230 when internal loopback testing is performed data is still transmitted out of the device on the TxD line This may cause problems with terminals modem printers and any other device attached Response Messages After the command has been issued the following line is printed SCC ILPBCK Internal Loopback
141. the following pages Table 3 16 RAM Test Group Name Description MARCH March Pattern QUIK Quick Write Read ALTS Alternating Ones Zeros PATS Data Patterns ADR Memory Addressing CODE Code Execution Copy PERM Permutations RNDM Random Data BTOG Bit Toggle PED Parity Error Detection REF Memory Refresh 3 72 RAM Local RAM Tests ADR Memory Addressing Command Input PPCl Diag RAM ADR Description This is the memory addressability test the purpose of which is to verify addressing of memory in the range specified by the configuration parameters for the RAM test group Addressing errors are sought by using a memory locations address as the data for that location This test is coded to use only 32 bit data entities The test proceeds as follows 1 2 A Locations Address is written to its location n The next location 1 4 is written with its address complemented The next location 8 is written with the most significant MS 16 bits and least significant LS 16 bits of its address swapped with each other Steps 1 2 and 3 are repeated throughout the specified memory range The memory is read and verified for the correct data pattern s and any errors are reported The test is repeated using the same algorithm as above steps 1 through 5 except that inverted data is used to insure that every data bit is written and verified at both
142. the debug commands for PPC1Bug can be entered If you are in the debug directory and enter SD you will return to the diagnostic directory You may enter either the diagnostic or debug commands from the diagnostics directory Example PPCl Diag sd PPCl Bug sd PPCl Diag SE Stop On Error Mode Sometimes you may want to stop a test or series of tests at the point where an error is detected SE accomplishes that for most of the tests To invoke SE enter it before the test or series of tests that is to run in Stop On Error mode Example PPCl Diag se dec ior ilr scc dma irq DEC IOR I O Resource Register Access Running PASSED DEC ILR Interrupt Line Register Access Running PASSED SCC DMA DMA IGSEo ue magnx uvam n Running FAILED error message error encountered in DMA test so IRQ test not run PPCl Diag Diagnostic Utilities ST and QST Self Test and Quick Self Test The diagnostics monitor provides an automated test mechanism called self test This mechanism runs all the tests included in an internal self test directory Entering the OST command executes the suite of self tests that are run at start up Entering ST causes more tests to execute than does OST but also requires more test time The commands HE ST and HE OST list the top level commands of the self test directory in alphabetical order Each test for that particular command is listed in the section pertainin
143. tic Directories When using PPCBug you operate out of either the debugger directory or the diagnostic directory a If you are in the debugger directory the debugger prompt PPC1 Bug gt is displayed and you have all of the debugger commands at your disposal a If you are in the diagnostic directory the diagnostic prompt PPCl Diag is displayed and you have all of the diagnostic commands at your disposal as well as all of the debugger commands 1 2 Command Entry To use the diagnostics you must be in the diagnostic directory If the prompt ppci Bug gt is displayed you are in the debugger directory and must switch to the diagnostic directory by entering SD the debugger s Switch Directories command The diagnostic prompt rPci piag is then be displayed You may examine the commands in the particular directory that you are currently in by using the Help HE command Because PPCBug is command driven it performs various operations in response to commands that you enter at the keyboard PPCBug executes the command and the prompt reappears However if you enter a command that causes execution of user target code e g GO then control may or may not return to PPCBug depending on the outcome of the user program The Help HE command displays a menu of all available diagnostic functions i e the tests and utilities Several tests have a subtest menu which may be called using the HE command In addition some utilities ha
144. tions REGA Device Register Access Command Input PPCl Diag UART REGA Description This test performs a read test on all registers in the PC16550 UARTS It also verifies that the UART scratch registers are readable and writable This test verifies that the device can be both accessed and that the data paths to the device are functioning Response Messages After the command has been issued the following line is printed UART REGA Register Access Running If all parts of the test are completed correctly then the test passes UART REGA Register Access Running PASSED If any part of the test fails then the display appears as follows UAR REGA Register Access Running FAILED UART REGA Test Failure Data error message Refer to the section LLART Error Messages for a list of the error messages and their meaning UART Serial Input Output Tests UART Error Messages The UART test group error messages generally take the following form UART BAUD Baud Rates elus UART BAUD Test Failure Data Data Miscompare Error Address XXXXXXXX Register Index XX Expected XX Actual XX Running FAILED The first line of the test failure data identifies what type of failure occurred The following line provides additional information about the failure Table 3 13 UART Error Messages Error Messa
145. tions are used in this document bold is used for user input that you type just as it appears Bold is also used for commands options and arguments to commands and names of programs directories and files italic is used for names of variables to which you assign values Italic is also used for comments in screen displays and examples courier is used for system output e g screen displays reports examples and system prompts RETURN represents the carriage return or ENTER key CTRL represents the control key Execute control characters by pressing the CTRL key and the letter simultaneously e g CTRL d Manual Terminology Throughout this manual a convention has been maintained whereby data and address parameters are preceded by a character which specifies the numeric format as follows dollar E specifies a hexadecimal character Ox Zero x percent specifies a binary number amp ampersand specifies a decimal number Unless otherwise specified all address references are in hexadecimal throughout this manual An asterisk following the signal name for signals which are level significant denotes that the signal is true or valid when the signal is low An asterisk following the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on high to low transition In this manual assertion and negation are used to specify forcing a signal to a particular state In p
146. ts MSFAT Mouse Test Command Input PPCl Diag KBD8730x MSFAT Description This test performs all the tests found in the mouse device confidence extended msconf tests reads the Mouse Device Type byte from the mouse device and reads the status bytes from the mouse device to ensure that the mouse is plugged in and functioning correctly These tests can only function with a mouse device present Response Messages After the command has been issued the following line is printed KBD8730x MSFAT Mouse Test A Running If all parts of the test are completed correctly then the test passes KBD8730x MSFAT Mouse Test eese Running PASSED If any part of the test fails then the display appears as follows KBD8730x MSFAT Mouse Test eese Running FAILED KBD8730x MSFAT Test Failure Data error message Refer to the section KBD8730x Error Messages for a list of the error messages and their meaning Test Descriptions KBD8730x Error Messages The KBD8730x test group error messages generally take the following form Failure during command XX KBD8730x KBFAT Keyboard Test Running FAILED KBD8730x KBFAT Test Failure Data Keyboard Controller timed out waiting for Output Buffer Full The first line of the test failure data identifies what type of failure occurred The following line provides additional information about
147. uced transmitted transcribed stored in a retrieval system or translated into any language or computer language in any form or by any means without the prior written permission of Motorola Inc Disclaimer of Warranty Unless otherwise provided by written agreement with Motorola Inc the software and the documentation are provided on an as is basis and without warranty This disclaimer of warranty is in lieu of all warranties whether express implied or statutory including implied warranties of merchantability or fitness for any particular purpose This equipment generates uses and can radiate electro magnetic A energy It may cause or be susceptible to electro magnetic WARNING interference EMI if not installed and used in a cabinet with adequate EMI protection Motorola and the Motorola symbol are registered trademarks of Motorola Inc Delta Series VMEmodule and VMEsystem are trademarks of Motorola Inc PowerPC is a trademark of IBM and is used by Motorola with permission Timekeeper is a trademark of SGS Thomson Microelectronics AIX is a trademark of IBM Corp All other products mentioned in this document are trademarks or registered trademarks of their respective holders Copyright Motorola Inc 1997 All Rights Reserved Printed in the United States of America June 1997 Contents EES EES 1 1 e 1 2 Debugger and Diagnostic DEHeCIORIS accesos pape REUS a DID GERA HIM CLiR 12 Command BUE aec rc
148. unning gt PASSE his Pass 0 Total Errors 0 SE Running PASSE his Pass 0 Total Errors 0 JV i daher ais Running PASSE Brrors RAI ADR Addressabil PPCl Diag Break Detected PPCl Diag lc ram adr zp RAI ADR Addressabil his Pass 0 Total Errors 0 Ey DLP iis Running 2 15 Diagnostic Utilities Test Descriptions Detailed descriptions of PPCBug s diagnostic tests are presented in this chapter The test groups are described in the order shown in the following table Note that some test groups do not run on all PowerPC boards The column PowerPC Board lists the boards on which each group of tests will run Table 3 1 Diagnostic Test Groups Test Group Description PowerPC Board CL1283 Parallel Interface CL1283 Tests MTX DEC DEC21x40 Ethernet Controller Tests Al ISABRDGE PCI ISA Bridge Tests All KBD8730X PC8730x Keyboard Mouse Tests All L2CACHE Level 2 Cache Tests All NCR NCR 53C8xx SCSI2 I O All Processor Tests PAR8730X Parallel Interface PC8730x Tests All UART Serial Input Output Tests All PCIBUS PCI PMC Generic Tests All RAM Local RAM Tests All RTC MK48Txx Timekeeping Tests All SCC Serial Communication All except MVME230x Controller Z85C230 Tests VGA543X Video Diagnostics Tests MVME360x MVME460x VME2 VMEchip2 VME Interface ASIC Tests None
149. ution Copy lee Running If all parts of the test are completed correctly then the test passes RAM CODE Code Execution Copy lee Running PASSED The test failure mode is typified by the nonjudicial of the passzp message above after more than about 1 minute which indicates that the MPU has irrecoverably crashed Hardware reset is required to recover from this error 3 78 RAM Local RAM Tests MARCH March Pattern Command Input PPCl Diag ram march Description This is the memory march test the purpose of which is to verify addressing of memory in the range specified by the configuration parameters for the RAM test group Addressing errors are sought by writing a pattern and its complement to each location This test is coded to use only 32 bit data entities The test proceeds as follows 1 Starting at the beginning test address and proceeding towards the ending address each location is written with the starting pattern 2 Starting at the beginning test address and proceeding towards the ending address each location is verified to contain the starting pattern and is written with the complement of the starting pattern 3 Starting at the ending test address and decreasing to the starting test address each location is verified to contain the complement of the starting pattern and is then written with the starting pattern Response Messages After the
150. ve Descriptor Ring size after initialization Initialization Error Logical Ethernet Address Filter byte N mismatch Controller not properly storing Nth byte of the Logical Ethernet filter address after initialization Initialization Error Physical Ethernet Address byte N mismatch Controller not properly storing Nth byte of the Physical Ethernet Address after initialization Initialization Error Mode Register mismatch Controller not properly storing the operating mode register after initialization 3 15 Test Descriptions Table 3 4 DEC Error Messages Continued Error Message Initialization Error Receive Descriptor Ring address mismatch Symptom or Cause Controller not properly storing the address of the Receive Descriptor ring after initialization Initialization Error Transmit Descriptor Ring address mismatch Controller not properly storing the address of the Transmit Descriptor ring after initialization Not enough diagnostics memory to accommodate DEC buffers There was not enough diagnostics memory space available for use by the Initialization block Descriptor Rings and buffers PCI XXX register contains invalid data Detected Value NNN Should Be NNN The PCI Header Register as listed contains a bad value other than a fixed predetermined constant May indicate a bad device or faulty interface to it Inte
151. ve subfunctions and as such have subfunction menus Command Entry Enter the name of a diagnostic command when the prompt PPC1 Diag appears and then press the RETURN or ENTER key The command may be the name of a diagnostic utility routine and may include one or more arguments or it may be the name of one or more test groups listed in a main root directory and may include one or more subcommands individual test names listed in the subdirectory for a particular test group The utility routines are described in Chapter 2 The test groups are described in Chapter 3 Examples of command entry for both are given below 1 3 General Information Root Level Command Utility The utility or root level commands affect the operation of the tests that are subsequently run A test group name may be entered on the same command line For example PPC1 Diag gt CF RAM causes an interactive dialog to begin in which you may enter parameters for the RAM tests Command entry may also include a subcommand individual test name For example PPCl Diag HE DEC2 ERREN causes a help screen to appear that gives information about the ERREN test in the DEC test group Root Level Command Test Group Entering just the name of a test group causes all individual tests that are part of that group to execute in sequence with some exceptions For example PPCl Diag RAM causes all Random Access Memory RAM tests to execute exce
152. xpected cmd 0xYY Init function called with something other than INIT DONE or SETUP L2 Cache Size Miscompare Error Address 08X Cache Size does not match Expected s Actual s expected Data Miscompare Failure Data write does not match Address 00040000 Expected 00000000 Actual data read FFFFFFFF 3 42 NCR 53C8xx SCSI I O Processor Tests NCR 53C8xx SCSI I O Processor Tests These sections describe the individual NCR 53C8xx SCSI I O Processor tests Entering NCR without parameters causes all NCR tests in the order shown in the table below To run an individual test add that test name to the NCR command The individual tests are described in alphabetical order on the following pages Table 3 10 NCR Test Group Name Description PCI PCI Access ACC Device Access ACC2 Register Access SFIFO SCSI FIFO DFIFO DMA FIFO SCRIPTS SCRIPTs Processor IRQ Interrupts The error message displays following the explanation of an NCR test pertain to the test being discussed 3 43 Test Descriptions ACC Device Access Command Input PPC1 Diag gt NCR ACC1 Description This procedure tests the basic ability to access the NCR 53C8xx device 1 All device registers are accessed read on 8 bit and 32 bit boundaries No attempt is made to verify the contents of the registers 2 The device data lines are checked by successive writes and reads to the S

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