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DAQ PCI E Series User Manual - NI Discussion Forums

1. Differential DIFF R AIGND AIGND See text for information on bias resistors NOT RECOMMENDED ACH ACH Oy y 1 1 Single Ended I Ground oN Referenced RSE AIGND Ground loop losses Vgs are added to measured signal Ecl ACH Y I ACH Y v AISENSE E Vi AISENSE f I Q Single Ended Nonreferenced NRSE R 5 ANN AIGND AIGND See text for information on bias resistors National Instruments Corporation Figure 4 4 Summary of Analog Input Connections 4 15 PCI E Series User Manual Chapter 4 Connecting Signals Differential Connection Considerations DIFF Input Configuration PCI E Series User Manual A differential connection is one in which the PCI E Series device AI signal has its own reference signal or signal return path These connections are available when the selected channel is configured in DIFF input mode The input signal is tied to the positive input of the PGIA and its reference signal or return is tied to the negative input of the PGIA In DIFF input mode the AI channels are paired with ACH lt i gt as the signal input and ACH lt i 8 gt as the signal reference For example ACHO is paired with ACH8 ACHI is paired with ACHO and so on Therefore with a differential configuration for every channel up to eight AI channels are available up to 32 channels on the NI PCI 6031E NI PCI 6
2. 42 V Installation Category II Environmental Operating temperature sss 0 to 55 C Storage temperature esses 20 to 70 C Humidity ue 10 to 90 RH noncondensing Maximum altitude eese 2 000 meters Pollution degree indoor use only 2 PCI E Series User Manual A 22 ni com Safety Appendix A Specifications for PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI G033E The PCI E Series devices meet the requirements of the following standards for safety and electrical equipment for measurement control and laboratory use e EN 61010 1 1993 A2 1995 IEC 61010 1 1990 A2 1995 e UL 3101 1 1993 UL 3111 1 1994 UL 3121 1998 e CAN CSA c22 2 no 1010 1 1992 A2 1997 Electromagnetic Compatibility CE C Tick and FCC Part 15 Class A Compliant Electrical emissions eeee EN 55011 Class A at 10 m FCC Part 15A above 1 GHz Electrical immunity ss Evaluated to EN 61326 1998 Table 1 Note For full EMC compliance you must operate this device with shielded cabling In addition all covers and filler panels must be installed Refer to the Declaration of Conformity DoC for this product for any additional regulatory compliance information To obtain the DoC for this product click Declaration of Conformity at ni com hardref ns This Web site lists the DoCs by product family Sel
3. 90 dB Stability Offset temperature coefficient PEGA vies neuere ena 5 uV C A tists erheesios 120 uV C Gain temperature coefficient 8 ppm C National Instruments Corporation A 17 PCI E Series User Manual Appendix A Specifications for PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E Analog Output PCI MIO 16XE 10 and NI PCI 6031E Only PCI E Series User Manual Output Characteristics Number of channels 2 voltage Resolution ooococccnnnoonnncconanananoconanananoconnno 16 bits 1 in 65 536 Max update rate sess 100 kS s Type 0 DAG sisas Double buffered FIFO buffer SiZO ooooncnicninnnocnnnnconanancnnos 2 048 samples Data transfers ccccccccncninnnnnanananannnnnnnnnns DMA interrupts programmed I O DMA modes uh Scatter gather single transfer demand transfer Transfer Characteristics Relative accuracy INL 0 5 LSB typ 1 LSB max DNE ERU QAM 1 LSB max Monotonicity seen 16 bits guaranteed Offset error After calibration 305 uV max Before calibration 20 mV max Gain error relative to internal reference After calibration 30 5 ppm max Before calibration 2 000 ppm max Voltage Output Rang uie 10 V O to 10 V software sele
4. x25 V powered on 15 V powered off Inputs protected PCI MIO 16XE 10 NEPCE6032E zii ACH lt 0 15 gt AISENSE NI PCI 6031E NI PCI 6033E ACH lt 0 63 gt AISENSE AISENSE2 FIFO buffer size eese 512 samples Data transfers eeeeeeeeeee DMA interrupts programmed I O DMA modes eee Scatter gather single transfer demand transfer Configuration memory size 512 words Transfer Characteristics Relative accuracy sese 0 75 LSB typ 1 LSB max DNE i negate etes 0 5 LSB typ 1 LSB max No missing codes esses 16 bits guaranteed Offset error Pregain error after calibration 3 uV max Pregain error before calibration 2 2 mV max Postgain error after calibration 76 uV max Postgain error before calibration 102 mV max Gain error relative to calibration reference After calibration gain 1 30 5 ppm of reading max Before calibration 2 150 ppm of reading max With gain error adjusted to 0 at gain 1 A A E 200 ppm of reading max O National Instruments Corporation A 15 PCI E Series User Manual Appendix A Specifications for PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI G033E Amplifier Characteristics Input impedance Normal powered on 100 GQ i
5. Trigger Figure 3 9 Inside Region Analog Triggering Mode PCI E Series User Manual 3 14 ni com Chapter 3 Hardware Overview In high hysteresis analog triggering mode the trigger is generated when the signal value is greater than highValue with the hysteresis specified by lowValue highValue lowValue Trigger Figure 3 10 High Hysteresis Analog Triggering Mode In low hysteresis analog triggering mode the trigger is generated when the signal value is less than lowValue with the hysteresis specified by highValue highValue lowValue Trigger Lief U Figure 3 11 Low Hysteresis Analog Triggering Mode The analog trigger circuit generates an internal digital trigger based on the Al signal and the user defined trigger levels This digital trigger can be used by any of the timing sections of the DAQ STC including the AI AO and general purpose counter timer sections For example the Al section can be configured to acquire n scans after the Al signal crosses a specific threshold As another example the AO section can be configured to update its outputs whenever the AI signal crosses a specific threshold O National Instruments Corporation 3 15 PCI E Series User Manual Chapter 3 Hardware Overview Digital 1 0 The PCI E Series devices contain eight lines of DIO for general purpose use You can individually software configure eac
6. 0 3 LSB typ 0 5 LSB max Before calibration 4 LSB max PCI E Series User Manual A 6 ni com Appendix A Specifications for PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E DNL After calibration 0 3 LSB typ 1 0 LSB max Before calibration 3 LSB max Monotonicity eese 12 bits guaranteed after calibration Offset error After calibration esee 1 0 mV max Before calibration 200 mV max Gain error relative to internal reference After calibration 0 01 of output max Before calibration 0 5 of output max Gain error relative to external reference 0 to 0 67 of output max not adjustable Voltage Output Ranges cete treten x10 V 0 to 10 V xEXTREF 0 to EXTREF software selectable Output coupling eee DC Output impedance esses 0 1 Q max Current drive s ecce ge 5 mA max Protection nati Short circuit to ground Power on state 0 V 200 mV External reference input National Instruments Corporation Range euet a 11 V Overvoltage protection x25 V powered on x15 V powered off Input impedance 10 kQ Bandwidth 3 dB 1 MHz A 7 PCI E Series User Manual Appen
7. 42 V Installation Category II Environmental Operating temperature esss 0 to 55 C Storage temperature essesss 55 to 150 C Hide 10 to 90 RH noncondensing Maximum altitude eese 2 000 meters Pollution degree indoor use only 2 Safety The PCI E Series devices meet the requirements of the following standards for safety and electrical equipment for measurement control and laboratory use e EN 61010 1 1993 A2 1995 IEC 61010 1 1990 A2 1995 e UL3101 1 1993 UL 3111 1 1994 UL 3121 1998 e CAN CSA c22 no 1010 1 1992 A2 1997 Electromagnetic Compatibility CE C Tick and FCC Part 15 Class A Compliant Electrical emissions eene EN 55011 Class A at 10 m FCC Part 15A above 1 GHz Electrical immunity Evaluated to EN 61326 1998 Table 1 PCI E Series User Manual A 12 ni com Appendix A Specifications for PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E B Note For full EMC compliance you must operate this device with shielded cabling In addition all covers and filler panels must be installed Refer to the Declaration of Conformity DoC for this product for any additional regulatory compliance information To obtain the DoC for this product click Declaration of Conformity at ni com hardref nsf This Web site lists the DoCs by product family Select the appropriate product family follow
8. eee 3 9 Analog OUtp t 5 eret Ett er telo te e deme eee 3 10 Analog Output Reference Selection esee 3 11 Analog Output Polarity Selection sese 3 11 Analog Output Reglitch Selecti0M oooonoconcninnnccnncnnnncnnnnancnncrncnncnnn cancion nonnnnos 3 12 National Instruments Corporation vij PCI E Series User Manual Contents Analog Trigger aecenas e e dap e eset Red 3 12 Digital VO siii RS DUPgagp ei quei eed 3 16 Timing Signal Routing 5 eme ee er seb ie EI e ETE P Sha Eee soda 3 16 Programmable Function Inputs eese ene 3 17 Device and RTSI Clocks ett eed Rene Hte tiet tete 3 18 RTSI Triggers ihid HERRERA TREES 3 18 Chapter 4 Connecting Signals I OGConnector dae meti aD ELO RU qe HER be reet 4 1 T O Connector Signal Descriptions eesseeeeeeeeenee 4 4 I O Signal Summary PCI MIO 16E 1 PCI MIO 16E 4 and hUNEGIEJU A LE 4 7 I O Signal Summary PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E sese 4 8 TO Signal Summary PCI MIO 16XE 50 sese 4 10 Analog Input Signal Connections eesesseeseeeeeeeeeee nennen eene 4 12 Types ot Signal SOUIG S ys pcs te eed wpe ee e e ten petiere 4 13 Floating Signal Sources sninn ee e EE ai a E ES 4 14 Ground Referenced Signal Sources serene 4 14 Input Configurations oe ado n glia ge e 4 14 Diffe
9. Gain temperature coefficient Number of channels Specifications for PCI MIO 16XE 50 25 uV C 15 ppm C 8 input output Compatibility eee TTL CMOS Digital logic levels Level Min Max Input low voltage OV 0 8 V Input high voltage 2V 5V Input low current 320 uA Input high current 10 uA Output low voltage ly 24 mA 0 4 V Output high voltage lop 13 mA 4 35 V Power on state Data transfers iruindar Max transfer rate ccccccccnnnnnnnnnnnanononon Constant sustainable rate Number of channels Resolution Counter timers 0oocoooconcncnnnnnnnononoss Frequency scaler Compatibility eee National Instruments Corporation A 29 Input high impedance Programmed I O 50 kwords s system dependent 1 to 10 kwords s typical 2 up down counter timers frequency scaler 24 bits 4 bits TTL CMOS PCI E Series User Manual Appendix A Specifications for PCI MIO 16XE 50 Base clocks available Counter timers eeeeeee 20 MHz 100 kHz Frequency scaler 10 MAz 100 kHz Base clock accuracy 0 01 Max source frequency sess 20 MHz Min source pulse duration 10 ns edge d
10. eee None Data transfers occccccccnnnnnnnnnnanananananonons DMA interrupts programmed I O DMA modes 2 nti Scatter gather single transfer demand transfer National Instruments Corporation A 27 PCI E Series User Manual Appendix A PCI E Series User Manual Specifications for PCI MIO 16XE 50 Transfer Characteristics Relative accuracy INL NETZ i hose eee aa Monotonicity eere Offset error After calibration Before calibration Lm 0 5 LSB max 1 LSB max 12 bits guaranteed YR 0 5 mV max ibus x85 mV max Gain error relative to calibration reference After calibration Before calibration Voltage Output LN eee Output coupling esses Output impedance eee Current drive iussisse hene Protection iioi eod uiia Power on state occcccccnnnnonnnanannnnnnnnnnos Dynamic Characteristics Settling time for full scale step Slew tate i x neve ei neis Glitch energy at midscale transition Magnitude sess A 28 s 0 01 of output max 1 of output max 10 V DC 0 1 Q max uen 5 mA Short circuit to ground 0 V x 85 mV ait 30 mV Duration eee ni com Digital 1 0 Timing 1 0 Appendix A Stability Offset temperature coefficient
11. gt CONVERT PFI lt O 9 gt lt Sample Interval Counter TC 3 GPCTRO OUT air ae Figure 3 12 CONVERT Signal Routing This figure shows that CONVERT can be generated from a number of sources including the external signals RTSI lt 0 6 gt and PFI lt 0 9 gt and the internal signals Sample Interval Counter TC and GPCTRO OUT Many of these timing signals are also available as outputs on the RTSI pins as described in the RTSI Triggers section and on the PFI pins as described in Chapter 4 Connecting Signals Programmable Function Inputs The 10 PFIs are connected to the signal routing multiplexer for each timing signal and software can select one of the PFIs as the external source for a given timing signal It is important to note that any of the PFIs can be used as an input by any of the timing signals and that multiple timing signals can use the same PFI simultaneously This flexible routing scheme reduces the need to change physical connections to the I O connector for different National Instruments Corporation 3 17 PCI E Series User Manual Chapter 3 Hardware Overview applications You also can individually enable each of the PFI pins to output a specific internal timing signal For example if you need the UPDATE signal as an output on the I O connector software can turn on the output driver for the PFIS UPDATE pin Device and RTSI Clocks RTSI Triggers PCI E Series User Man
12. to ground V us DACIOUT AO 0 1Q Short circuit 5at 10 5at 10 20 to ground V us EXTREF Al 10 KQ 25 15 AOGND AO DGND DO VCC DO 01 Q Short circuit 1A to ground DIO lt 0 7 gt DIO Vec 0 5 13 at 24at0 4 1 1 50 KQ pu Vcc 0 4 SCANCLK DO 3 5 at 5 at 0 4 1 5 50 kQ pu Vcc 0 4 EXTSTROBE DO 3 5 at 5 at 0 4 1 5 50 KQ pu Vcc 0 4 PFIO TRIGI AI 10kQ 35 3 5 at 5 at 0 4 1 5 9 KQ pu DIO Vec 0 5 Vcc 0 4 and 10 kQ pd PFII TRIG2 DIO Vec 40 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vec 0 4 PFI2 CONVERT DIO Vcc 40 5 3 5 at 5 at 0 4 1 5 50 KQ pu Vcc 0 4 PFI3 GPCTR1I SOURCE DIO Vec 40 5 3 5 at 5 at 0 4 1 5 50 KQ pu Vcc 0 4 O National Instruments Corporation 4 7 PCI E Series User Manual Chapter 4 Connecting Signals Signal Impedance Protection Sink Rise Type and Input Volts Source mA Time Signal Name Direction Output On Off mA at V at V ns Bias PFI4 GPCTR1_GATE DIO Vcc 40 5 3 5 at 5 at 0 4 1 5 50 KQ pu Vcc 0 4 GPCTR1_OUT DO 3 5at 5at 0 4 1 5 50 kQ pu Voc 0 4 PFIS UPDATE DIO Vcc 40 5 3 5at 5 at 0 4 1 5 50 kQ pu Vcc 0 4 PFI6 WFTRIG DIO Voc 40 5 3 5at 5 at 0 4 1 5 50 KQ pu Vcc 0 4 PFI7 STARTSCAN DIO Vcc 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vcc 0 4 PFIS GPCTRO SOURCE DIO Vcc 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vcc 0 4 PFI9 GPCTRO_GATE DIO Vcc 0 5 3 5 at 5 at 0 4 1 5 50 kQ pu Vcc 0 4
13. oooooooconnnonucucnnnnononnnnncnononanonccnnnnnnnncononnnnnnncnnnnananocnnns xi National Instruments Documentation ccccccccccesssscccesessseeeceeesssceececesseeeeeeeessseeeeees xii Related Documenta aia xiii Chapter 1 Introduction About the PCI E Series 0 ccccccccccssscccccesssssecceessssseeccescsseeeceesesseeececesesseeeceeessaeeeecesees 1 1 What You Need to Get Started anenun a n E eene E nenne 1 2 Software Programming Choices ooooooccnocconcnononnnonocononnnonncnnnonn cono cononn non conc cono nn nr eere 1 2 NEDA O void da io 1 3 National Instruments ADE Software essen 1 4 Register Level Programming esent enne nennen 1 4 Optional Equipment o tette o p e ence erp t 1 5 Custom Cabling aset et e bei ei ted diea cost pe eoe c 1 5 Unpacking iic eite eee UOI doeet ee Rie 1 5 Safety Information dte e e dd tei e pee 1 6 Chapter 2 Installing and Configuring the Device Installing the Software entente etd ei e o ere ei ien 2 1 Installing the Hard Ware ss ii rhet e tei Oe ondas eee ee aestu 2 1 Configuring the Device ze tie e cede eed aues 2 2 Chapter 3 Hardware Overview Analog Inp t ec eh eme e ehe deus deed e ta ey 3 4 Input Mode ecce e eae I Re Tett 3 4 Input Polarity and Input Range eee nemen 3 5 Considerations for Selecting Input Ranges eee cece eters 3 8 JD A 3 8 Multichannel Scanning Considerations
14. As an input this is one of the PFIs As an output this is the CONVERT signal A high to low edge on CONVERT indicates that an A D conversion is occurring PFIB GPCTR1_SOURCE DGND Input Output PFI3 Counter 1 Source As an input this is one of the PFIs As an output this is the GPCTRI SOURCE signal This signal reflects the actual source connected to the general purpose counter 1 PFI4 GPCTR1_GATE DGND Input Output PFI4 Counter 1 Gate As an input this is one of the PFIs As an output this is the GPCTR1_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 1 National Instruments Corporation 4 5 PCI E Series User Manual Chapter 4 Connecting Signals Signal Name Reference Direction Description GPCTRI OUT DGND Output Counter 1 Output This output is from the general purpose counter 1 output PFIS UPDATE DGND Input PFI5 Update As an input this is one of the PFIs Output As an output this is the UPDATE signal A high to low edge on UPDATE indicates that the AO primary group is being updated PFI6 WFTRIG DGND Input PFI6 Waveform Trigger As an input this is one of the PFIs As an output this is the WFTRIG signal In timed AO Output sequences a low to high transition indicates the initiation of the waveform generation PFI7 STARTSCAN DGND Input PFI7 Start of Scan As an input this is o
15. 0 4 PFI2 CONVERT DIO Vcc 0 5 3 5 at 5at0 4 1 5 50 kO pu Vcc 0 4 PFI3 GPCTR1 SOURCE DIO Vcc 0 5 3 5 at 5at0 4 1 5 50 KQ pu Vcc 0 4 PFI4 GPCTR1_GATE DIO Vcc 40 5 3 5 at 5at0 4 1 5 50 kO pu Vcc 0 4 GPCTRI OUT DO 3 5 at 5at0 4 1 5 50 KQ pu Vcc 0 4 PFIS UPDATE DIO Vcc 0 5 3 5 at 5at0 4 1 5 50 KQ pu Vcc 0 4 PFI6 WFTRIG DIO Vcc 40 5 3 5 at 5at0 4 1 5 50 kQ pu Vcc 0 4 PFI7 STARTSCAN DIO Vcc 40 5 3 5 at 5at0 4 1 5 50 kQ pu Vcc 0 4 PFIS GPCTRO SOURCE DIO Vcc 40 5 3 5 at 5at0 4 1 5 50 kQ pu Vcc 0 4 PFI9 GPCTRO_GATE DIO Vcc 40 5 3 5 at 5at0 4 1 5 50 KQ pu Vcc 0 4 GPCTRO_OUT DO 3 5 at 5at0 4 1 5 50 kQ pu Vcc 0 4 FREQ_OUT DO 3 5 at 5at0 4 1 5 50 kO pu Vcc 0 4 AI Analog Input DIO Digital Input Output pd pull down AO Analog Output DO Digital Output pu pull up O National Instruments Corporation 4 11 PCI E Series User Manual Chapter 4 Connecting Signals Analog Input Signal Connections PCI MIO 16E 1 PCI MIO 16E 4 PCI MIO 16XE 50 PCI MIO 16XE 10 and NI PCI 6032E The Al signals for the PCI E Series devices are ACH lt 0 15 gt AISENSE and AIGND The ACH lt 0 15 gt signals are tied to the 16 AI channels of the PCI E Series device In single ended mode signals connected to ACH lt 0 15 gt are routed to the positive input of the device PGIA In differential mode signals connected to ACH lt 0 7 gt
16. 0 5 13 at 24 at 0 4 1 1 50 KQ pu Vcc 0 4 SCANCLK DO 3 5 at 5at04 1 5 50 KQ pu Vcc 0 4 EXTSTROBE DO 3 5 at 5at04 1 5 50 KQ pu Voc 0 4 PFIO TRIGI AI 10 kQ 35 3 5 at 5at04 1 5 9 kQ pu and DIO Vcc 0 5 Vcc 0 4 10 KQ pd PFI1 TRIG2 DIO Vec 0 5 3 5 at 5at04 1 5 50 KQ pu Vcc 0 4 PFI2 CONVERT DIO Vec 40 5 3 5 at 5at04 1 5 50 KQ pu Vcc 0 4 PFI3 GPCTRI_SOURCE DIO Vec 40 5 3 5 at 5at0 4 1 5 50 KQ pu Voc 0 4 PFI4 GPCTR1_GATE DIO Vec 40 5 3 5 at 5at04 1 5 50 KQ pu Vcc 0 4 GPCTR1_OUT DO 3 5 at 5at04 1 5 50 KQ pu Vcc 0 4 PFI5 UPDATE DIO Vec 40 5 3 5 at 5at04 1 5 50 KQ pu Vcc 0 4 PFI6 WFTRIG DIO Vec 40 5 3 5 at 5at04 1 5 50 KQ pu Voc 0 4 PFI7 STARTSCAN DIO Vec 0 5 3 5 at 5at04 1 5 50 KQ pu Vcc 0 4 PFI8 GPCTRO_SOURCE DIO Vec 40 5 3 5 at 5at04 1 5 50 KQ pu Vcc 0 4 National Instruments Corporation 4 9 PCI E Series User Manual Chapter 4 Connecting Signals Signal Impedance Protection Sink Rise Type and Input Volts Source mA Time Signal Name Direction Output On Off mA at V at V ns Bias PFI9 GPCTRO GATE DIO Voc 40 5 3 5 at 5at0 4 1 5 50 kQ pu Vcc 0 4 GPCTRO_OUT DO 3 5 at 5at0 4 1 5 50 kQ pu Vcc 0 4 FREQ OUT DO 3 5 at 5at0 4 1 5 50 kQ pu Vcc 0 4 AI Analog Input AO Analog Output 100 KQ DIO Digital Input Output DO Digital Out
17. Figure 4 9 AO Connections The external reference signal can be either a DC or an AC signal The device multiplies this reference signal by the DAC code divided by the full scale DAC code to generate the output voltage Digital 1 0 Signal Connections The DIO signals are DIO lt 0 7 gt and DGND DIO lt 0 7 gt are the signals making up the DIO port and DGND is the ground reference signal for the DIO port You can program all lines individually to be inputs or outputs IN Caution Exceeding the maximum input voltage ratings which are listed in the I O signal summary tables in this chapter can damage the PCI E Series device and the computer NI is not liable for any damage resulting from such signal connections PCI E Series User Manual 4 24 ni com Chapter 4 Connecting Signals Figure 4 10 shows signal connections for three typical DIO applications 45V Sw LED uem DIO lt 4 7 gt ps rats TTL Signal o DIO lt 0 3 gt 5V VVV gt Switch p DGND 1 O Connector E Series Device Figure 4 10 DIO Connections Figure 4 10 shows DIO lt 0 3 gt configured for digital input and DIO lt 4 7 gt configured for digital output Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch shown in the figure Digital output applications include sending TTL signals a
18. For example if you are certain the input signal is not negative below 0 V unipolar input polarity is best However if the signal is negative or equal to zero you get inaccurate readings if you use unipolar input polarity When you enable dither you add approximately 0 5 LSB of white Gaussian noise to the signal to be converted by the ADC This addition is useful for applications involving averaging to increase the resolution of the PCI E Series device as in calibration or spectral analysis In such applications noise modulation is decreased and differential linearity is improved by the addition of the dither When taking DC measurements such as when checking the device calibration you should enable dither and average about 1 000 points to take a single reading This process removes the effects of quantization and reduces measurement noise resulting in improved resolution For high speed applications not involving averaging or spectral analysis you may want to disable the dither to reduce noise The software enables and disables the dither circuitry Figure 3 5 illustrates the effect of dither on signal acquisition Figure 3 5a shows a small 4 LSB sine wave acquired with dither disabled The ADC quantization is clearly visible Figure 3 5b shows what happens when 50 such acquisitions are averaged together quantization is still plainly visible In Figure 3 5c the sine wave is acquired with dither on There is a considerable amoun
19. T technical support D 1 telephone technical support D 1 theory of operation See hardware overview timebases 3 18 timing connections 4 26 DAQ timing connections 4 28 AIGATE signal 4 35 CONVERT signal 4 34 EXTSTROBE signal 4 37 SCANCLK signal 4 36 SISOURCE signal 4 35 STARTSCAN signal 4 32 TRIG1 signal 4 29 TRIG2 signal 4 30 typical posttriggered acquisition figure 4 28 typical pretriggered acquisition figure 4 29 exceeding maximum ratings caution 4 26 general purpose timing signal connections FREQ OUT signal 4 46 GPCTRO GATE signal 4 41 GPCTRO OUT signal 4 42 GPCTRO SOURCE signal 4 40 GPCTRO UP DOWN signal 4 42 GPCTR1_GATE signal 4 43 GPCTR1_SOURCE signal 4 43 programmable function input connections 4 27 PCI E Series User Manual Index questions about C 6 waveform generation timing connections UISOURCE signal 4 39 UPDATE signal 4 38 WFTRIG signal 4 37 timing I O specifications PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E A 9 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E A 20 PCI MIO 16XE 50 A 29 timing signal routing CONVERT signal routing figure 3 17 programmable function inputs 3 17 RTSI clocks 3 18 training customer D 1 transfer characteristic specifications analog input PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E A 3 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E A 15 PCI MIO 16XE 50 A 25 analog output PCI MIO 16E 1
20. o 44 o 43 42 41 40 39 38 37 36 m c A oroj o 35 Wa ACHO AIGND ACH9 ACH2 AIGND ACH11 AISENSE ACH12 ACH5 AIGND ACH14 ACH7 AIGND AOGND AOGND DGND DIOO DIO5 DGND DIO2 DIO7 DIO3 SCANCLK EXTSTROBE DGND PFI2 CONVERT PFIS GPCTR1_SOURCE PFI4 GPCTR1_GATE GPCTR1_OUT DGND PFI7 STARTSCAN PFIS GPCTRO SOURCE DGND DGND Not available on the NI PCI 6032E or NI PCI 6033E Not available on the PCI MIO 16XE 10 PCI MIO 16XE 50 NI PCI 6032E or NI PCI 6033E Figure B 1 68 Pin E Series Connector Pin Assignments B 2 ni com Appendix B Optional Cable Connector Descriptions Figure B 2 shows the pin assignments for the 68 pin extended AI connector This is the other 68 pin connector available when you use the SH1006868 cable assembly with the NI PCI 6031E NI PCI 6033E or NI PCI 6071E ACH24 ACH17 ACH18 ACH27 ACH20 ACH21 ACH30 ACH23 ACH32 ACH41 ACH34 ACH35 AIGND ACH44 ACH37 ACH38 ACH47 ACH48 ACH49 ACH58 ACH51 ACH52 ACH61 ACH54 ACH55 N C N C N C N C N C N C N C N C N C Me 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 c m co A5 jo0 o o Au ACH16 ACH25 ACH26 ACH19 ACH28 ACH29 ACH22
21. 1 400 LSB of the 4 V step It may take as long as 200 us for the circuitry to settle this much In general this extra settling time is not needed when the PGIA is switching to a lower gain Settling times can also increase when scanning high impedance signals due to a phenomenon called charge injection where the AI multiplexer injects a small amount of charge into each signal source when that source is selected If the impedance of the source is not low enough the effect of the charge a voltage error does not decay by the time the ADC samples the signal For this reason keep source impedances under 1 kQ to perform high speed scanning Due to the previously described limitations of settling times resulting from these conditions multichannel scanning is not recommended unless sampling rates are low enough or it is necessary to sample several signals as nearly simultaneously as possible The data is much more accurate and channel to channel independent if you acquire data from each channel independently for example 100 points from channel 0 then 100 points from channel 1 then 100 points from channel 2 and so on PCI E Series User Manual PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E These devices supply two channels of AO voltage at the I O connector The reference and range for the AO circuitry is software selectable The reference can be either internal or external whereas the range can be either bipolar or unipolar 3
22. 10 ni com Chapter 3 Hardware Overview PCI MIO 16XE 10 and NI PCI 6031E These devices supply two channels of AO voltage at the I O connector The range is software selectable between unipolar 0 to 10 V and bipolar 10 V PCI MIO 16XE 50 This device supplies two channels of AO voltage at the I O connector The range is fixed at bipolar 10 V Analog Output Reference Selection PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E You can connect each D A converter DAC to these PCI E Series devices internal reference of 10 V or to the external reference signal connected to the external reference EXTREF pin on the I O connector This signal applied to EXTREF should be within 11 V You do not need to configure both channels for the same mode Analog Output Polarity Selection PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E You can configure each AO channel for either unipolar or bipolar output A unipolar configuration has a range of 0 to Vep at the analog output A bipolar configuration has a range of V to V e at the analog output Vef 1S the voltage reference used by the DACs in the AO circuitry and can be either the 10 V onboard reference or an externally supplied reference within 11 V You do not need to configure both channels for the same range Selecting a bipolar range for a particular DAC means that any data written to that DAC is interpreted as two s complement format In two s complement mode data
23. 4 18 STARTSCAN Input Signal Timing 4 32 ni com Chapter 4 Connecting Signals ty 50 to 100 ns a Star of Scan Start Pulse __ i H CONVERT TE STARTSCAN tog 10 ns minimum i b Scan in Progress Two Conversions per Scan Figure 4 19 STARTSCAN Output Signal Timing The CONVERT pulses are masked off until the device generates the STARTSCAN signal If you are using internally generated conversions the first CONVERT appears when the onboard sample interval counter reaches zero If you select an external CONVERT the first external pulse after STARTSCAN generates a conversion The STARTSCAN pulses should be separated by at least one scan period A counter on the PCI E Series device internally generates the STARTSCAN signal unless you select some external source This counter is started by the TRIGI signal and is stopped either by software or by the sample counter Scans generated by either an internal or external STARTSCAN signal are inhibited unless they occur within a DAQ sequence Scans occurring within a DAQ sequence may be gated by either the hardware AIGATE signal or software command register gate National Instruments Corporation 4 33 PCI E Series User Manual Chapter 4 Connecting Signals PCI E Series User Manual CONVERT Signal Any PFI pin can externally input the CONVERT signal which is available as an output on the PFI
24. 4 43 GPCTR1_UP_DOWN signal 4 44 programmable function input connections 4 27 waveform generation timing connections UISOURCE signal 4 39 UPDATE signal 4 38 WFTRIG signal 4 37 types of signal sources floating 4 14 ground referenced 4 14 single ended connections description 4 20 floating signal sources RSE 4 21 grounded signal sources NRSE 4 21 when to use 4 20 SISOURCE signal 4 35 software drivers D 1 software installation 2 1 software programming choices 1 2 register level programming 1 4 specifications PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E analog input amplifier A 3 dynamic characteristics A 4 input characteristics A 1 stability A 6 transfer characteristics A 3 analog output dynamic characteristics A 8 output characteristics A 6 stability A 8 transfer characteristics A 6 voltage output A 7 analog trigger A 10 bus interface A 11 PCI E Series User Manual 1 12 calibration A 11 digital I O A 8 digital trigger A 10 electromagnetic compatibility A 12 environmental A 12 physical A 11 power requirements A 11 RTSI A 11 safety A 12 timing I O A 9 voltage A 12 PCI MIO 16XE 10 and NI PCI 6031E analog output dynamic characteristics A 19 output characteristics A 18 stability A 19 transfer characteristics A 18 voltage output A 18 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E analog input amplifier characteristics A 16 dynamic character
25. ACH31 ACH40 ACH33 ACH42 ACH43 AISENSE2 ACH36 ACH45 ACH46 ACH39 ACH56 ACH57 ACH50 ACH59 ACH60 ACH53 ACH62 ACH63 N C N C N C N C N C N C N C N C N C National Instruments Corporation Figure B 2 68 Pin Extended Al Connector Pin Assignments B 3 PCI E Series User Manual Appendix B PCI E Series User Manual Optional Cable Connector Descriptions Figure B 3 shows the pin assignments for the 50 pin E Series connector This connector is available when you use the SH6850 or R6850 cable assemblies with the PCI MIO 16E 1 PCI MIO 16E 4 PCI MIO 16XE 10 PCI MIO 16XE 50 or NI PCI 6032E It is also one of the two 50 pin connectors available when you use the RI005050 cable assembly with the NI PCI 6031E NI PCI 6033E or NI PCI 6071E AIGND ACHO ACH1 ACH2 ACH3 ACH4 ACH5 ACH6 ACH7 AISENSE DAC1OUT AOGND DIOO DIO1 DIO2 DIO3 DGND 45V EXTSTROBE PFH TRIG2 PFI3 GPCTR1 SOURCE GPCTR1 OUT PFIG WFTRIG PFIS GPCTRO SOURCE GPCTRO OUT Oo AI 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 AIGND ACH8 ACH9 ACH10 ACH11 ACH12 ACH13 ACH14 ACH15 DACOOUT EXTREF DGND DIO4 DIO5 DIO6 DIO7 45V SCANCLK PFIO TRIG1 PFI2 CONVERT PFI4 GPCTR1_GATE PFI5 UPDATE PFI7 STARTSCAN PFI9 GPCTRO_GATE FRE
26. Actual Range and Measurement Precision PCI MIO 16XE 10 PCI MIO 16XE 50 NI PCI 6031E NI PCI 6032E and NI PCI 6033E Range Configuration Gain Actual Input Range Precision 0 to 10 V 1 0 0 to 10 V 152 59 uV 2 0 0 to 5 V 76 29 uV 5 0 0to 2 V 30 52 uV 10 0 0Oto 1 V 15 26 uV 20 0 0 to 500 mV 7 63 uV 50 0 0 to 200 mV 3 05 uV 100 0 0 to 100 mV 1 53 uV 10 to 10 V 1 0 10 to 10 V 305 18 uV 2 0 5to 45 V 152 59 uV 5 0 2 to 2 V 61 04 uV 10 0 1to 1V 30 52 uV 20 0 500 to 500 mV 15 26 uV 50 0 200 to 200 mV 6 10 uV 100 0 100 to 100 mV 3 05 uV The value of 1 LSB of the 16 bit ADC that is the voltage increment corresponding to a change of one count in the ADC 16 bit count Not available on the PCI MIO 16XE 50 Note Refer to Appendix A Specifications for absolute maximum ratings National Instruments Corporation 3 7 PCI E Series User Manual Chapter 3 Hardware Overview Dither PCI E Series User Manual Considerations for Selecting Input Ranges Which input polarity and range you select depends on the expected range of the incoming signal A large input range can accommodate a large signal variation but reduces the voltage resolution Choosing a smaller input range improves the voltage resolution but may result in the input signal going out of range For best results match the input range as closely as possible to the expected range of the input signal
27. Basic is a development suite that allows you to use ANSI C Visual C and Visual Basic to design the test and measurement software For C developers Measurement Studio includes LabWindows CVI a fully integrated ANSI C application development environment that features interactive graphics and the LabWindows CVI Data Acquisition and Easy I O libraries For Visual Basic developers Measurement Studio features a set of ActiveX controls for using National Instruments DAQ hardware These ActiveX controls provide a high level programming interface for building virtual instruments For Visual C developers Measurement Studio offers a set of Visual C classes and tools to integrate those classes into Visual C applications The libraries ActiveX controls and classes are available with Measurement Studio and NI DAQ VI Logger is an easy to use yet flexible tool specifically designed for data logging applications Using dialog windows you can configure data logging tasks to easily acquire log view and share your data VI Logger does not require any programming it is a stand alone configuration based software Using LabVIEW Measurement Studio or VI Logger greatly reduces the development time for your data acquisition and control application Register Level Programming PCI E Series User Manual The final option for programming any National Instruments DAQ hardware is to write register level software Writing register level programming s
28. PCI 6071E A 3 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E A 16 PCI MIO 16XE 50 A 25 analog input dither 3 8 input mode 3 4 input polarity and range PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E 3 5 PCI MIO 16XE 10 PCI MIO 16XE 50 NI PCI 6031E NI PCI 6032E and NI PCI 6033E 3 6 multiple channel scanning considerations 3 9 questions about C 3 selection considerations 3 8 signal connections 4 12 exceeding maximum ratings caution 4 12 1 1 PCI E Series User Manual Index analog input specifications PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E amplifier characteristics A 3 dynamic characteristics A 4 input characteristics A 1 stability A 6 transfer characteristics A 3 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E amplifier characteristics A 16 dynamic characteristics A 16 input characteristics A 14 transfer characteristics A 15 PCI MIO 16XE 50 amplifier characteristics A 25 dynamic characteristics A 26 input characteristics A 24 stability A 27 transfer characteristics A 25 analog output PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E 3 10 PCI MIO 16XE 10 and NI PCI 6031E 3 11 PCI MIO 16XE 50 3 11 polarity selection PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E 3 11 PCI MIO 16XE 10 and NI PCI 6031E 3 11 questions about C 3 reference selection 3 11 reglitch selection 3 12 signal connections 4 23 analog output specifications PCI MIO 16E 1 PC
29. PCI MIO 16E 4 and NI PCI 6071E table 4 8 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E table 4 10 PCI MIO 16XE 50 table 4 11 GPCTRO SOURCE signal 4 40 GPCTRO UP DOWN signal 4 42 GPCTR1_GATE signal 4 43 GPCTR1_OUT signal 4 44 description table 4 6 general purpose timing considerations 4 44 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 8 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and N PCI 6033E table 4 9 PCI MIO 16XE 50 table 4 11 GPCTRI SOURCE signal 4 43 GPCTRI UP DOWN signal 4 44 ground referenced signal sources description 4 14 differential connections 4 17 recommended configuration figure 4 15 single ended connections NRSE configuration 4 21 H hardware installation 2 1 hardware overview analog input dither 3 8 input mode 3 4 input polarity and range 3 5 PCI E Series User Manual 1 6 multiple channel scanning considerations 3 9 selection considerations 3 8 analog trigger above high level triggering mode figure 3 14 below low level triggering mode figure 3 13 block diagram figure 3 13 high hysteresis triggering mode figure 3 15 inside region triggering mode figure 3 14 low hysteresis triggering mode figure 3 15 block diagrams NI PCI 6032E and NI PCI 6033E 3 3 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E 3 1 PCI MIO 16XE 10 and NI PCI 6031E 3 2 PCI MIO 16XE 50 3 4 digital I O 3 16 timing signal routing 3 16 progr
30. a specific sampling rate waveform generation trigger signal O National Instruments Corporation G 11 PCI E Series User Manual Index Symbols 5 V signal description table 4 5 power connections 4 26 protection provided by PCI E Series boards C 2 A ACH lt 0 15 gt signal analog input connections 4 12 description table 4 4 PCI MIO 16XE 50 table 4 10 ACH lt 0 63 gt signal analog input connections 4 12 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 7 PCI MIO 16XE 10 NI PCI 6031E and NI PCI 6033E table 4 8 ACH lt 16 63 gt signal description table 4 4 AIGATE signal 4 35 AIGND signal analog input connections 4 12 description table 4 4 differential connections for floating signal sources 4 18 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 7 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E table 4 8 PCI MIO 16XE 50 table 4 10 AISENSE signal analog input connections 4 12 description table 4 4 O National Instruments Corporation PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 7 PCI MIO 16XE 10 NI PCI 6031E and NI PCI 6033E table 4 8 PCI MIO 16XE 50 table 4 10 AISENSE2 signal analog input connections 4 12 description table 4 4 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 7 PCI MIO 16XE 10 NI PCI 6031E and NI PCI 6033E table 4 8 amplifier characteristic specifications PCI MIO 16E 1 PCI MIO 16E 4 and NI
31. an extensive library of functions that you can call from the ADE These functions allow you to use all the features of the device NI DAQ carries out many of the complex interactions such as programming interrupts between the computer and the DAQ hardware NI DAQ maintains a consistent software interface among its different versions so that you can change platforms with minimal modifications to the code Whether you are using LabVIEW Measurement Studio VI Logger or other ADEs your application uses NI DAQ as illustrated in Figure 1 1 Conventional Programming Environment LabVIEW Measurement Studio or VI Logger Driver Software Personal Computer or Workstation DAQ Hardware I 9 Figure 1 1 The Relationship Among the Programming Environment NI DAQ and the Hardware To download a free copy of the most recent version of NI DAQ click Download Software at ni com National Instruments Corporation 1 3 PCI E Series User Manual Chapter 1 Introduction National Instruments ADE Software LabVIEW features interactive graphics a state of the art interface and a powerful graphical programming language The LabVIEW Data Acquisition VI Library a series of virtual instruments for using LabVIEW with National Instruments DAQ hardware is included with LabVIEW Measurement Studio which includes LabWindows CVI tools for Visual C and tools for Visual
32. and could not find the answers you need contact your local office or NI corporate headquarters Phone numbers for our worldwide offices are listed at the front of this manual You also can visit the Worldwide Offices section of ni com niglobal to access the branch office Web sites which provide up to date contact information support phone numbers email addresses and current events National Instruments Corporation D 1 PCI E Series User Manual Glossary Prefix Meaning Value p pico 10 2 n nano 10 u micro 1075 m milli 103 k kilo 10 M mega 106 G giga 10 Numbers Symbols T degrees gt greater than 2 greater than or equal to lt less than lt less than or equal to per percent plus or minus positive of or plus negative of or minus Q ohms O National Instruments Corporation G 1 PCI E Series User Manual Glossary r 5 V A D AC ACH ADC AI AIGATE AIGND AISENSE ANSI AO AOGND ASIC BIOS bipolar PCI E Series User Manual square root of 5 VDC source signal amperes analog to digital alternating current analog input channel signal analog to digital converter an electronic device often an integrated circuit that converts an analog voltage to a digital number analog input analog input gate signal analog input ground signal analog input sense signal American National Standards Institute analo
33. are completely Plug and Play multifunction analog digital and timing I O devices for PCI bus computers This family of devices features 12 bit and 16 bit ADCs with 16 and 64 analog inputs 12 bit and 16 bit DACs with voltage outputs eight lines of TTL compatible DIO and two 24 bit counter timers for TIO Because the PCI E Series devices have no DIP switches jumpers or potentiometers they are easily software configured and calibrated The PCI E Series devices are completely switchless and jumperless data acquisition DAQ devices for the PCI bus This feature is made possible by the NI MITE bus interface chip that connects the device to the PCI I O bus The MITE implements the PCI Local Bus Specification so that the interrupts and base memory addresses are all software configured The PCI E Series devices use the National Instruments DAQ STC system timing controller for time related functions The DAQ STC consists of three timing groups that control AI AO and general purpose counter timer functions These groups include a total of seven 24 bit and three 16 bit counters and a maximum timing resolution of 50 ns The DAQ STC makes possible such applications as buffered pulse generation equivalent time sampling and seamlessly changing the sampling rate Often with DAQ devices you cannot easily synchronize several measurement functions to a common trigger or timing event The PCIE Series devices have the Real Time System Integration RTS
34. are routed to the positive input of the PGIA and signals connected to ACH lt 8 15 gt are routed to the negative input of the PGIA NI PCI 6031E NI PCI 6033E and NI PCI 6071E The AI signals are ACH lt 0 63 gt AISENSE AISENSE2 and AIGND The ACH lt 0 63 gt signals are tied to the 64 AI channels of the devices In single ended mode signals connected to ACH lt 0 63 gt are routed to the positive input of the PGIA In differential mode signals connected to ACH lt 0 7 16 23 32 39 48 55 gt are routed to the positive input of the PGIA and signals connected to ACH 8 15 24 31 40 47 56 63 are routed to the negative input of the PGIA UN Caution Exceeding the differential and common mode input ranges distorts the input signals Exceeding the maximum input voltage rating can damage the PCI E Series device and the computer NI is not liable for any damage resulting from such signal connections The maximum input voltage ratings are listed in the Protection column of the I O signal summary tables in this chapter PCI E Series User Manual In NRSE mode the AISENSE signal is connected internally to the negative input of the PCI E Series device PGIA when their corresponding channels are selected In DIFF and RSE modes this signal is left unconnected AIGND is a common AI signal that is routed directly to the ground tie point on the PCI E Series devices You can use this signal for a general analog ground tie point to the PC
35. attention to the settling times for each of the devices The settling time for most of the PCI E Series devices is independent of the selected gain even at the maximum sampling rate The settling time for the very high speed devices is gain dependent which can affect the useful sampling rate for a given gain No extra settling time is necessary between channels as long as the gain is constant and source impedances are low Refer to Appendix A National Instruments Corporation 3 9 PCI E Series User Manual Chapter 3 Hardware Overview Analog Output Specifications for a complete listing of settling times for each of the PCIE Series devices When scanning among channels at various gains the settling times may increase When the PGIA switches to a higher gain the signal on the previous channel may be well outside the new smaller range For example suppose a 4 V signal is connected to channel 0 and a 1 mV signal is connected to channel 1 and suppose the PGIA is programmed to apply a gain of one to channel 0 and a gain of 100 to channel 1 When the multiplexer switches to channel 1 and the PGIA switches to a gain of 100 the new full scale range is 100 mV if the ADC is in unipolar mode The approximately 4 V step from 4 V to 1 mV is 4 000 of the new full scale range For a 16 bit device to settle within 0 001596 15 ppm or 1 LSB of the 100 mV full scale range on channel 1 the input circuitry must settle within 0 00004 0 4 ppm or
36. dB 1 100 dB 95 dB 22 106 dB 100 dB Dynamic Characteristics Bandwidth Bandwidth PCI MIO 16E 1 Signal NI PCI 6071E PCI MIO 16E 4 Small 3 dB 1 6 MHz 600 kHz Large 196 THD 1 MHz 350 kHz Settling time to full scale step Accuracy 0 012 0 024 0 098 Device Gain 0 5 LSB 1 LSB 4 LSB PCI MIO 16E 1 0 5 2 uS typ 1 5 uS typ 1 5 uS typ 3 uS max 2 uS max 2 uS max 1 2 uS typ 1 5 uS typ 1 3 uS typ 3 uS max 2 uS max 1 5 uS max 2 to 50 2 uS typ 1 5 uS typ 0 9 uS typ 3 uS max 2 uS max 1 uS max 100 2 uS typ 1 5 uS typ 1 uS typ 3 uS max 2 uS max 1 5 uS max PCI MIO 16E 4 All 4 uS typ 4 uS max 4 uS max 8 uS max PCI E Series User Manual A 4 ni com Appendix A Specifications for PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E Accuracy 0 012 0 024 0 098 Device Gain 0 5 LSB 1 LSB 4 LSB NI PCI 6071E 0 5 3 uS typ 1 9 uS typ 1 9 uS typ 5 uS max 2 5 uS max 2 uS max 1 3 uS typ 1 9 uS typ 1 2 uS typ 5 uS max 2 5 uS max 1 4 uS max 2 to 50 3 uS typ 1 9 uS typ 1 2 uS typ 5 uS max 2 5 uS max 1 3 uS max 100 3 uS typ 1 9 uS typ 1 2 uS typ 5 uS max 2 5 uS max 1 4 uS max Accuracy values valid for source impedances 1 kQ Refer to the Multichannel Scanning Considerations section of Chapter 3 Hardware Overview for more information System noise LSB not including quantization Device Gain Dither Off
37. dither enabling 3 8 signal acquisition effects figure 3 9 nonreferenced or floating signal sources 4 18 questions about C 3 recommended configuration documentation figure 4 15 conventions used in manual xi single ended connections 4 20 National Instruments xii floating signal sources RSE 4 21 online library D 1 grounded signal sources related documentation xiii NRSE 4 21 drivers when to use 4 16 instrument D 1 digital I O software D 1 operation 3 16 dynamic characteristic specifications questions about C 7 analog input signal connections 4 24 PCI MIO 16E 1 PCI MIO 16E 4 exceeding maximum ratings and NI PCI 6071E A 4 caution 4 24 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E A 16 PCI E Series User Manual 1 4 ni com PCI MIO 16XE 50 A 26 analog output PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E A 8 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E A 19 PCI MIO 16XE 50 A 28 PCI MIO 16XE 50 A 26 E EEPROM storage of calibration constants 5 1 electromagnetic compatibility specifications PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E A 12 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E A 23 PCI MIO 16XE 50 A 32 environmental noise avoiding 4 46 environmental specifications PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E A 12 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E A 22 PCI MIO 16XE 50 A 31 equipment optio
38. is 100 kQ the resistors load down the source with 200 KQ and produce a 1 gain error Both inputs of the PGIA require a DC path to ground for the PGIA to work If the source is AC coupled capacitively coupled the PGIA needs a resistor between the positive input and AIGND If the source has low impedance choose a resistor that is large enough not to significantly load the source but small enough not to produce significant input offset voltage as a result of input bias current typically 100 kQ to 1 MQ In this case you can tie the negative input directly to AIGND If the source has high output impedance you should balance the signal path as previously described using the same value resistor on both the positive and negative inputs you should be aware that there is some gain error from loading down the source National Instruments Corporation 4 19 PCI E Series User Manual Chapter 4 Connecting Signals Single Ended Connection Considerations A single ended connection is one in which the PCI E Series device AI signal is referenced to a ground that can be shared with other input signals The input signal is tied to the positive input of the PGIA and the ground is tied to the negative input of the PGIA When every channel is configured for single ended input up to 16 AI channels are available up to 64 on the NI PCI 6031E NI PCI 6033E and NI PCI 6071E You can use single ended input connections for any input signal that meets
39. output specifications PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E A 7 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E A 18 PCI MIO 16XE 50 A 28 voltage specifications PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E A 12 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E A 22 PCI MIO 16XE 50 A 31 National Instruments Corporation 1 15 Index W waveform generation timing connections UISOURCE signal 4 39 UPDATE signal 4 38 WFTRIG signal 4 37 waveform generation questions about C 3 Web professional services D 1 technical support D 1 WFTRIG signal input signal timing figure 4 38 output signal timing figure 4 38 timing connections 4 37 wiring considerations 4 46 worldwide technical support D 1 PCI E Series User Manual
40. reserved Important Information Warranty The PCI E Series devices are warranted against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this document is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors ex
41. setting the device base memory address and interrupt channel Data acquisition related configuration includes such settings as AI polarity and range AI mode and others You can configure the default settings with Measurement amp Automation Explorer MAX or the NI DAQ Configuration Utility You can modify these settings through application level software such as NI DAQ LabVIEW Measurement Studio and VI Logger PCI E Series User Manual 2 2 ni com Hardware Overview This chapter presents an overview of the hardware functions on the PCIE Series device Figure 3 1 shows a block diagram for the PCI MIO 16E 1 the PCI MIO 16E 4 and the NI PCI 6071E Voltage Calibration REF Mux Mode 5 12 Bit Selection ii Sampling Switches AID Converter Address Data Calibration Mux Configuration Memory AT Control Data 16 Trigger Level m o DACs n o Trigger Circuitry Sk lt gt T DMAT E 2 Trigger i Analog Input i Interrupt b c PFI Trigger 1 Timing Control Request Analog EEPROM DMA e o TrT ll em aE Canto Control Interface O o Counter Bus lt ms O Timing Timing I O DAQ STC interface PAGS O MIO Oo Y A a Interface Interface jo a 1 Analog Output 1 RTSI Bus Analog Bus Digital VO Timing Co
42. values written to the AO channel can be either positive or negative If you select unipolar range data is interpreted in straight binary format In straight binary mode data values written to the AO channel range must be positive PCI MIO 16XE 10 and NI PCI 6031E You can configure each AO channel for either unipolar or bipolar output A unipolar configuration has a range of 0 to 10 V at the analog output A bipolar configuration has a range of 10 to 10 V at the analog output You do not need to configure both channels for the same range O National Instruments Corporation 3 11 PCI E Series User Manual Chapter 3 Hardware Overview Selecting a bipolar range for a particular DAC means that any data written to that DAC is interpreted as two s complement format In two s complement mode data values written to the AO channel can be either positive or negative If you select unipolar range data is interpreted in straight binary format In straight binary mode data values written to the AO channel range must be positive Analog Output Reglitch Selection Analog Trigger PCI MIO 16E 1 and NI PCI 6071E In normal operation a DAC output glitches whenever it is updated with a new value The glitch energy differs from code to code and appears as distortion in the frequency spectrum Each analog output contains a reglitch circuit that generates uniform glitch energy at every code rather than large glitches at the major code transitio
43. waveform generation even if the waveform generation is being externally triggered by another PFI The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to high impedance at startup National Instruments Corporation 4 37 PCI E Series User Manual Chapter 4 Connecting Signals PCI E Series User Manual Figures 4 25 and 4 26 show the input and output timing requirements for the WFTRIG signal Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 25 WFTRIG Input Signal Timing ty 50 to 100 ns Figure 4 26 WFTRIG Output Signal Timing UPDATE Signal Any PFI pin can externally input the UPDATE signal which is available as an output on the PFIS UPDATE pin As an input the UPDATE signal is configured in the edge detection mode You can select any PFI pin as the source for UPDATE and configure the polarity selection for either rising or falling edge The selected edge of the UPDATE signal updates the outputs of the DACs To use UPDATE you must set the DACs to posted update mode As an output the UPDATE signal reflects the actual update pulse that is connected to the DACs even if the updates are being externally generated by another PFI The output is an active low pulse with a pulse width of 300 to 350 ns This output is set to high impedance at startup 4 38 ni com Chapter 4 Connecting Signals Figures 4 27 an
44. 0196 10 ppm accurate 5 2 ni com Chapter 5 Calibration For a detailed calibration procedure for the PCI E Series devices refer to the E Series Calibration Procedure by clicking Manual Calibration Procedures at ni com calibration Other Considerations The CalDACs adjust the gain error of each AO channel by adjusting the value of the reference voltage supplied to that channel This calibration mechanism is designed to work only with the internal 10 V reference Thus in general it is not possible to calibrate the AO gain error when using an external reference In this case it is advisable to account for the nominal gain error of the AO channel either in software or with external hardware Refer to Appendix A Specifications for AO gain error information National Instruments Corporation 5 8 PCI E Series User Manual Specifications This appendix lists the specifications of each PCI E Series device These specifications are typical at 25 C unless otherwise noted PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E Analog Input Input Characteristics Number of channels PCI MIO 16E 1 PCI MIO 16E 4 sss 16 single ended or 8 differential software selectable per channel NIPCI 6071E ote 64 single ended or 32 differential software selectable per channel Type of ADC stes Successive approximation Resolution eese 12 bits 1 in 4 096 Max sampling rate single channel PCI MIO 16
45. 033E and NI PCI 6071E You should use differential input connections for any channel that meets any of the following conditions e The input signal is low level less than 1 V e The leads connecting the signal to the PCI MIO E Series device are greater than 3 m 10 ft e The input signal requires a separate ground reference point or return signal e The signal leads travel through noisy environments Differential signal connections reduce picked up noise and increase common mode noise rejection Differential signal connections also allow input signals to float within the common mode limits of the PGIA 4 16 ni com Chapter 4 Connecting Signals Differential Connections for Ground Referenced Signal Sources Figure 4 5 shows how to connect a ground referenced signal source to a channel on the PCI E Series device configured in DIFF input mode ACH oO 94 L oO Ground P ie o 2 Referenced V e Instrumentation Signal s e Amplifier Source ot o PGIA 9 ACH Measured Voltage Common Co Mode hd Noise and ven el so Ground z e y Potential pis gl PA Input Multiplexers AISENSE AIGND 1 0 Connector Selected Channel in DIFF Configuration Figure 4 5 Differential Input Connections for Ground Referenced Signals With this type of connection the PGIA rejects both the common mode noise in the signal and the g
46. 2 ACH60 ACH53 ACH61 ACH54 ACH62 ACH55 ACH63 O National Instruments Corporation Figure 4 2 1 0 Connector Pin Assignment for the NI PCI 6071E NI PCI 6031E and NI PCI 6033E 4 3 PCI E Series User Manual Chapter 4 Connecting Signals 1 0 Connector Signal Descriptions Signal Name Reference Direction Description AIGND Es AI Ground These pins are the reference point for single ended measurements in RSE configuration and the bias current return point for differential measurements All three ground references AIGND AOGND and DGND are connected together on the PCI E Series device ACH 0 15 AIGND Input ACH lt 16 63 gt AIGND Input AI Channels 0 through 15 Each channel pair ACH lt i i 8 gt i 2 0 7 can be configured as either one differential input or two single ended inputs AI Channels 16 through 63 NI PCI 6031E NI PCI 6033E NI PCI 6071E only Each channel pair ACH lt i i48 i 16 23 32 39 48 55 can be configured as either one differential input or two single ended inputs AISENSE AIGND Input AI Sense This pin serves as the reference node for any of channels ACH lt 0 15 gt in NRSE configuration AISENSE2 AIGND Input AI Sense NI PCI 6031E NI PCI 6033E and NI PCI 6071E only This pin serves as the reference node for any of channels ACH 16 63 in NRSE configuration DACOOUT AOGND Output Analog Channel 0 Output This pin suppli
47. 33E actual range and measurement precision table 3 7 unipolar and bipolar 3 6 selection considerations 3 8 installation hardware 2 1 questions about C 2 safety information 1 6 software 2 1 unpacking PCI E Series 1 5 instrument drivers D 1 K KnowledgeBase D 1 L LabVIEW definition 1 4 Measurement Studio definition 1 4 MITE interface bus chip 1 1 multiple channel scanning 3 9 National Instruments customer education D 1 documentation xii professional services D 1 system integration services D 1 technical support D 1 worldwide offices D 1 PCI E Series User Manual Index NI DAQ definition 1 3 noise avoiding 4 46 NRSE nonreferenced single ended input description table 3 5 differential connections 4 18 recommended configuration figure 4 15 single ended connections NRSE configuration 4 21 0 online technical support D 1 optional equipment 1 5 output characteristic specifications PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E A 6 PCI MIO 16XE 10 and NI PCI 6031E A 18 PCI MIO 16XE 50 A 27 P PCIE Series See also hardware overview custom cabling 1 5 features 1 1 optional equipment 1 5 questions about analog input and output C 3 general information C 1 installation and configuration C 2 timing and digital I O C 6 requirements for getting started 1 2 software programming choices 1 2 register level programming 1 4 unpacking 1 5 PCI E Series
48. 4 38 PFI7 STARTSCAN PFI9 GPCTRO_GATE 3 37 PFI8 GPCTRO_SOURCE GPCTRO OUT 2 36 DGND FREQ OUT 1 35 DGND 1 Not available on the PCI 6032bE Not available on the PCI MIO 16XE 10 PCI MIO 16XE 50 or PCI 6032bE Figure 4 1 1 0 Connector Pin Assignment for the PCI MIO 16E 1 PCI MIO 16E 4 PCI MIO 16XE 50 PCI MIO 16XE 10 and NI PCI 6032E PCI E Series User Manual 4 2 ni com Chapter 4 Connecting Signals AIGND AIGND ACHO ACH8 ACH1 ACH9 ACH2 ACH10 ACH3 ACH11 ACH4 ACH12 ACH5 ACH13 ACH6 ACH14 ACH7 ACH15 AISENSE DACOOUT DAC10UT EXTREF AOGND DGND DIOO DIO4 DIO1 DIO5 DIO2 DIO6 DIO3 DIO7 DGND 45V 45V SCANCLK EXTSTROBE PFIO TRIG1 PFH TRIG2 PFI2 CONVERT PFI3 GPCTR1_SOURCE PFI4 GPCTR1 GATE GPCTR1 OUT PFI5 UPDATE PFI6 WFTRIG PFI7 STARTSCAN PFIB GPCTRO SOURCE PFIS GPCTRO GATE GPCTRO_OUT FREQ_OUT jN Ioja A v N 1 Not available on the NI PCI 6033E 2 Not available on the NI PCI 6031E or NI PCI 6033E ACH16 ACH24 ACH17 ACH25 ACH18 ACH26 ACH19 ACH27 ACH20 ACH28 ACH21 ACH29 ACH22 ACH30 ACH23 ACH31 ACH32 ACH40 ACH33 ACH41 ACH34 ACH42 ACH35 ACH43 AISENSE2 AIGND ACH36 ACH44 ACH37 ACH45 ACH38 ACH46 ACH39 ACH47 ACH48 ACH56 ACH49 ACH57 ACH50 ACH58 ACH51 ACH59 ACH5
49. 6032E and NI PCI 6033E table 4 9 PCI MIO 16XE 50 table 4 10 DAQ timing connections AIGATE signal 4 35 CONVERT signal 4 34 EXTSTROBE signal 4 37 SCANCLK signal 4 36 SISOURCE signal 4 35 STARTSCAN signal 4 32 PCI E Series User Manual Index TRIGI signal 4 29 specifications TRIG2 signal 4 30 PCI MIO 16E 1 PCI MIO 16E 4 typical posttriggered acquisition and NI PCI 6071E A 8 figure 4 28 PCI MIO 16XE 10 NI PCI 6031E typical pretriggered acquisition 4 29 NI PCI 6032E and NI DAQ STC system timing controller C 1 C 6 PCI 6033E A 19 data acquisition timing connections See DAQ PCI MIO 16XE 50 A 29 timing connections digital trigger specifications DGND signal PCI MIO 16E 1 PCI MIO 16E 4 and description table 4 4 NI PCI 6071E A 10 digital I O connections 4 24 PCI MIO 16XE 10 NI PCI 6031E PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6032E and NI PCI 6071E table 4 7 NI PCI 6033E A 21 PCI MIO 16XE 10 NI PCI 6031E PCI MIO 16XE 50 A 30 N PCI 6032E and NI PCI 6033E DIO lt O0 7 gt signal table 4 9 description table 4 4 PCI MIO 16XE 50 table 4 10 digital I O connections 4 24 timing connections 4 27 PCI MIO 16E 1 PCI MIO 16E 4 and diagnostic resources D 1 NI PCI 6071E table 4 7 DIFF differential input mode PCI MIO 16XE 10 NI PCI 6031E definition table 3 5 NI PCI 6032E and N PCI 6033E description 4 16 table 4 9 PCI MIO 16XE 50 table 4 10 ground referenced signal sources 4 17
50. Bit ore Mux Mode Bil Interface Selection i Sampling A A D Switches ifi Converter Calibration Mux Trigger Level 2 DACs y rid lEEPROM DMA Control Control Interface Circuitry Trigger A i Analog Input Bus MIO lt PFI Trigger j Trigger Timing Control Interface Interface ie Analog ba 1 Output Interface Counter 4 Timing j Timing vo DAQ STC Control RTSI Bus m 1 Analog Output 1 Digital 1 O Timing Control Interface l O Connector Digital 1 0 8 32 for the PCI 6033E Figure 3 3 NI PCI 6032E and NI PCI 6033E Block Diagram National Instruments Corporation 3 3 PCI E Series User Manual Chapter 3 Hardware Overview Figure 3 4 shows a block diagram for the PCI MIO 16XE 50 Selection Switches Calibration Mux gt gt Mux Mode Calibration DACs 16 Bit Sampling A D Programmable Gain Amplifier Address Data Converter Configuration Memory Address 5 PFI Trigger A 1 0 Connector Timing yl T T Trigger 1 Analog Input nisap a Timing Control Request Analog IEEPROM DMA PIN A A Cohtro Cono Interface Oo Counter Bus piper mA Timing vo DAQ STC interface MIO a A C E Interface I
51. CI 6031E NI PCI 6032E and NI PCI 6033E table 4 9 PCI MIO 16XE 50 table 4 11 PFI7 STARTSCAN signal definition table 4 6 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 8 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E table 4 9 PCI MIO 16XE 50 table 4 11 PFI8 GPCTRO_SOURCE signal definition table 4 6 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 8 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E table 4 9 PCI MIO 16XE 50 table 4 11 PFI9 GPCTRO_GATE signal description table 4 6 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 8 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E table 4 10 PCI MIO 16XE 50 table 4 11 National Instruments Corporation Index PFIs programmable function inputs overview 4 27 signal routing 3 17 timing input connections 4 27 PGIA programmable gain instrumentation amplifier analog input connections 4 13 common mode signal rejection 4 22 differential connections floating signal sources 4 18 ground referenced signal sources 4 17 single ended connections floating signal sources figure 4 21 grounded signal sources figure 4 22 phone technical support D 1 physical specifications PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E A 11 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E A 22 PCI MIO 16XE 50 A 31 pin assignments 50 pin E Series connecto
52. DAQ PCI E Series User Manual Multifunction 1 0 Devices for PCI Bus Computers Wy NATIONAL July 2002 Edition P INSTRUMENTS Part Number 370509B 01 Worldwide Technical Support and Product Information ni com National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 512 683 0100 Worldwide Offices Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Brazil 55 11 3262 3599 Canada Calgary 403 274 9391 Canada Montreal 514 288 5722 Canada Ottawa 613 233 5949 Canada Qu bec 514 694 8521 Canada Toronto 905 785 0085 China 86 21 6555 7838 Czech Republic 02 2423 5774 Denmark 45 76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Greece 01 42 96 427 Hong Kong 2645 3186 India 91 80 4190000 Israel 03 6393737 Italy 02 413091 Japan 03 5472 2970 Korea 02 3451 3400 Malaysia 603 9596711 Mexico 001 800 010 0793 Netherlands 0348 433466 New Zealand 09 914 0488 Norway 32 27 73 00 Poland 22 3390 150 Portugal 210 311 210 Russia 095 238 7139 Singapore 65 6 226 5886 Slovenia 3 425 4200 South Africa 11 805 8197 Spain 91 640 0085 Sweden 08 587 895 00 Switzerland 056 200 51 51 Taiwan 02 2528 7227 United Kingdom 01635 523545 For further support information see the Technical Support and Professional Services appendix To comment on the documentation send email to techpubseni com O 2002 National Instruments Corporation All rights
53. Dither On PCI MIO 16E 1 0 5 to 10 0 25 0 5 NI PCI 6071E 20 04 0 6 50 0 5 0 7 100 0 8 0 9 PCI MIO 16E 4 0 5 to 5 0 15 0 5 10 to 20 0 2 0 5 50 0 35 0 6 100 0 6 0 8 Crosstalk DC to 100 kHz Adjacent channels 15 dB All other channels 90 dB National Instruments Corporation A 5 PCI E Series User Manual Appendix A Specifications for PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E Stability Offset temperature coefficient Pres Microcar 5 uV C Postgain iue 240 uV PC Gain temperature coefficient 20 ppm C Analog Output Output Characteristics Number of channels 2 voltage Resolution oooooocccnnnoonanccononananocononananoconnno 12 bits 1 in 4 096 Max update rate Waveform Generation FIFO Mode Non FIFO Mode Internally Externally Device Timed Timed 1 Channel 2 Channels NI PCI 6040E 1 MS s 950 kS s 800 kS s system 400 kS s system NI PCI 607XE dependent dependent Type ot DAC z 5 node Double buffered multiplying FIFO buffer size PCI MIO 16E 1 NI PCI 6071E 2 048 samples PCI MIO 16E 4 esses 512 samples Data transfers occccccccnnninnnnnanananannncnnnnnns DMA interrupts programmed I O DMA modes eee Scatter gather single transfer demand transfer Transfer Characteristics Relative accuracy INL After calibration
54. E 1 NI PCI 6071E 1 25 MS s PCI MIO 16E 4 500 kS s Refer to the settling time table in the Dynamic Characteristics section for multichannel rates National Instruments Corporation A 1 PCI E Series User Manual Appendix A Specifications for PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E PCI E Series User Manual Input signal ranges Device Range Channel Gain Software Selectable Software Selectable Bipolar Unipolar 0 5 10 V 1 5 V 0to 10 V 2 2 5 V 0to5 V 5 xl V 0to2V 10 500 mV 0to1V 20 250 mV 0 to 500 mV 50 100 mV 0 to 200 mV 100 50 mV 0 to 100 mV Input coupling eeeeees DC Max working voltage signal and common mode Overvoltage protection Inputs protected PCI MIO 16E 1 Each input should remain within 11 V of ground 25 V powered on x15 V powered off PCI MIO 16E 4 sees ACH lt 0 15 gt AISENSE NIPCI 6071E mm ACH lt 0 63 gt AISENSE AISENSE2 FIFO buffer size 512 samples Data transfers cccccccnnnnnnnnnnnnnannnnnnnnnnnos DMA modes cccccccccccncnnnnnononananananononcnnnnnos A 2 DMA interrupts programmed I O Scatter gather single transfer demand transfer 512 words ni com Appendix A Specifications for PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E Transfer Characteristics R
55. E SUITABILITY OF NATIONAL INSTRUMENTS PRODUCTS WHENEVER NATIONAL INSTRUMENTS PRODUCTS ARE INCORPORATED IN A SYSTEM OR APPLICATION INCLUDING WITHOUT LIMITATION THE APPROPRIATE DESIGN PROCESS AND SAFETY LEVEL OF SUCH SYSTEM OR APPLICATION Compliance FCC Canada Radio Frequency Interference Compliance Determining FCC Class The Federal Communications Commission FCC has rules to protect wireless communications from interference The FCC places digital electronics into two classes These classes are known as Class A for use in industrial commercial locations only or Class B for use in residential or commercial locations Depending on where it is operated this product could be subject to restrictions in the FCC rules In Canada the Department of Communications DOC of Industry Canada regulates wireless interference in much the same way Digital electronics emit weak signals during normal operation that can affect radio television or other wireless products By examining the product you purchased you can determine the FCC Class and therefore which of the two FCC DOC Warnings apply in the following sections Some products may not be labeled at all for FCC if so the reader should then assume these are Class A devices FCC Class A products only display a simple warning statement of one paragraph in length regarding interference and undesired operation Most of our products are FCC Class A The FCC rules have restrictions regarding
56. GPCTRO_OUT DO 3 5at 5at 0 4 1 5 50 kQ pu Vcc 0 4 FREQ_OUT DO 3 5 at 5at 0 4 1 5 50 KQ pu Vcc 0 4 AI Analog Input pu pull up 100 kO DIO Digital Input Output AO Analog Output DO Digital Output AI DIO Analog Digital Input Output pd pull down Note The tolerance on the 50 kQ pull up and pull down resistors is very large Actual value may range between 17 kQ and 1 0 Signal Summary PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E Signal Impedance Protection Sink Rise Type and Input Volts Source mA Time Signal Name Direction Output On Off mA at V at V ns Bias ACH lt 0 63 gt AI 100 GQ in 25 15 1 nA parallel with 100 pF AISENSE AISENSE2 AI 100 GQ in 25 15 1 nA parallel with 100 pF AIGND AO PCI E Series User Manual 4 8 ni com Chapter 4 Connecting Signals Signal Impedance Protection Sink Rise Type and Input Volts Source mA Time Signal Name Direction Output On Off mA at V at V ns Bias DACOOUT AO 0 1 Q Short circuit 5 at 10 Sat 10 5 V us to ground DACIOUT AO 0 1 Q Short circuit 5 at 10 Sat 10 5 V us to ground AOGND AO DGND DO VCC DO 0 1 Q Short circuit 1 A to ground DIO lt 0 7 gt DIO Vec
57. I bus to solve this problem The RTSI bus consists of our RTSI bus interface and a ribbon cable to route timing and trigger signals between several functions on as many as five DAQ devices in the computer National Instruments Corporation 1 1 PCI E Series User Manual Chapter 1 Introduction The PCI E Series devices can interface to an SCXI system so that you can acquire over 3 000 analog signals from thermocouples RTDs strain gauges voltage sources and current sources You also can acquire or generate digital signals for communication and control SCXI is the instrumentation front end for plug in DAQ devices Refer to Appendix A Specifications for detailed specifications of the PCIE Series devices What You Need to Get Started To set up and use the PCI E Series device you need the following LY A computer C One of the following devices NI PCI 6031E NI PCI 6032E NI PCI 6033E NI PCI 6071E PCI MIO 16E 1 PCI MIO 16E 4 PCI MIO 16XE 10 PCI MIO 16XE 50 Q PCIE Series User Manual C One of the following software packages and documentation LabVIEW Measurement Studio NI DAQ VI Logger Software Programming Choices When programming National Instruments DAQ hardware you can use an NI application development environment ADE or other ADEs In either case use NI DAQ PCI E Series User Manual 1 2 ni com NI DAQ Chapter 1 Introduction NI DAQ which ships with the PCI E Series device has
58. I 6033E and NI PCI 6071E support analog triggering on the PFIO TRIGI pin Refer to Chapter 3 Hardware Overview for more information on analog triggering As an output the TRIG1 signal reflects the action that initiates a DAQ sequence even if the acquisition is being externally triggered by another PFI The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to high impedance at startup National Instruments Corporation 4 29 PCI E Series User Manual Chapter 4 Connecting Signals PCI E Series User Manual Figures 4 14 and 4 15 show the input and output timing requirements for the TRIGI signal Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 14 TRIG1 Input Signal Timing ty 50 to 100 ns Figure 4 15 TRIG1 Output Signal Timing The device also uses the TRIGI signal to initiate pretriggered DAQ operations In most pretriggered applications the TRIG1 signal is generated by a software trigger Refer to the TRIG2 signal description for a complete description of the use of TRIGI and TRIG2 in a pretriggered DAQ operation TRIG2 Signal Any PFI pin can externally input the TRIG2 signal which is available as an output on the PFII TRIG2 pin Refer to Figure 4 13 for the relationship of TRIG2 to the DAQ sequence As an input the TRIG2 signal is configured in the edge detection mode You can select any PFI pin as the sour
59. I E Series device if necessary Connection of AI signals to the PCI E Series device depends on the configuration of the AI channels you are using and the type of input signal source With the different configurations you can use the PGIA in different ways Figure 4 3 shows a diagram of the PCI E Series device PGIA 4 12 ni com Chapter 4 Connecting Signals Instrumentation Vins O Amplifier Measured Voltage Vin O Vin Vins Vin x Gain Figure 4 3 PCI E Series PGIA The PGIA applies gain and common mode voltage rejection and presents high input impedance to the AI signals connected to the PCI E Series device Signals are routed to the positive and negative inputs of the PGIA through input multiplexers on the device The PGIA converts two input signals to a signal that is the difference between the two input signals multiplied by the gain setting of the amplifier The amplifier output voltage is referenced to the ground for the device The PCI E Series device A D converter ADC measures this output voltage when it performs A D conversions You must reference all signals to ground either at the source device or at the device If you have a floating source you should reference the signal to ground by using the RSE input mode or the DIFF input configuration with bias resistors Refer to the Differential Connections for Nonreferenced or Floating Signal Sources section for more information If you have a gro
60. I MIO 16E 4 and NI PCI 6071E dynamic characteristics A 8 output characteristics A 6 stability A 8 PCI E Series User Manual 1 2 transfer characteristics A 6 voltage output A 7 PCI MIO 16XE 10 and NI PCI 6031E dynamic characteristics A 19 output characteristics A 18 stability A 19 transfer characteristics A 18 voltage output A 18 PCI MIO 16XE 50 dynamic characteristics A 28 output characteristics A 27 stability A 29 transfer characteristics A 28 voltage output A 28 analog trigger 3 12 above high level triggering mode figure 3 14 below low level triggering mode figure 3 13 block diagram figure 3 13 high hysteresis triggering mode figure 3 15 inside region triggering mode figure 3 14 low hysteresis triggering mode figure 3 15 specifications PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E A 10 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E A 20 AOGND signal analog output signal connections 4 23 description table 4 4 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 7 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E table 4 9 PCI MIO 16XE 50 4 10 ni com bipolar input output See polarity selection block diagrams NI PCI 6032E and NI PCI 6033E 3 3 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E 3 1 PCI MIO 16XE 10 and NI PCI 6031E 3 2 PCI MIO 16XE 50 3 4 board configuration 2 2 bus interface specifications PCI MIO 16E 1 PCI MIO 16E 4 a
61. ISOURCE L p UISOURCE 4 GPCTR1_SOURCE sek M gt GPCTR1_GATE t l Switch e gt RTSI_OSC 20 MHz Ne Trigger gt gt 7 RTSI Bus Connector RTSI Switch Figure 3 13 RTSI Bus Signal Connection Refer to the Timing Connections section of Chapter 4 Connecting Signals for a description of the signals shown in Figure 3 13 National Instruments Corporation 3 19 PCI E Series User Manual Connecting Signals This chapter describes how to connect signals to the PCI E Series device using the device I O connector Table 4 1 1 0 Connector Details Cable for Cable for Cable for Connecting Connecting Connecting to Device with I O Number to 100 pinSignal to 68 pin Signal 50 pin Signal Connector of Pins Accessories Accessories Accessories PCI MIO 16E 1 68 N A SH68 68 EP SH6850 Shielded PCI MIO 16E 4 Shielded Cable Cable PCI MIO 16XE 10 SH68 68R1 EP R6850 Ribbon PCI MIO 16XE 50 Shielded Cable Cable and NI PCI 6032E R6868 Ribbon Cable NI PCI 6031E 100 SH100100 SH1006868 R1005050 Ribbon NI PCI 6033E Shielded Cable Shielded Cable Cable and NI PCI 6071E 1 0 Connector Figure 4 1 shows the pin assignments for the 68 pin I O connector on the PCI MIO 16XE 10 NI PCI 6032E PCI MIO 16E 1 PCI MIO 16E 4 and PCI MIO 16XE 50 Figure 4 2 shows the pin assignments for the 100 pin I O connector
62. ON OF THE SOFTWARE PRODUCTS CAN BE IMPAIRED BY ADVERSE FACTORS INCLUDING BUT NOT LIMITED TO FLUCTUATIONS IN ELECTRICAL POWER SUPPLY COMPUTER HARDWARE MALFUNCTIONS COMPUTER OPERATING SYSTEM SOFTWARE FITNESS FITNESS OF COMPILERS AND DEVELOPMENT SOFTWARE USED TO DEVELOP AN APPLICATION INSTALLATION ERRORS SOFTWARE AND HARDWARE COMPATIBILITY PROBLEMS MALFUNCTIONS OR FAILURES OF ELECTRONIC MONITORING OR CONTROL DEVICES TRANSIENT FAILURES OF ELECTRONIC SYSTEMS HARDWARE AND OR SOFTWARE UNANTICIPATED USES OR MISUSES OR ERRORS ON THE PART OF THE USER OR APPLICATIONS DESIGNER ADVERSE FACTORS SUCH AS THESE ARE HEREAFTER COLLECTIVELY TERMED SYSTEM FAILURES ANY APPLICATION WHERE A SYSTEM FAILURE WOULD CREATE A RISK OF HARM TO PROPERTY OR PERSONS INCLUDING THE RISK OF BODILY INJURY AND DEATH SHOULD NOT BE RELIANT SOLELY UPON ONE FORM OF ELECTRONIC SYSTEM DUE TO THE RISK OF SYSTEM FAILURE TO AVOID DAMAGE INJURY OR DEATH THE USER OR APPLICATION DESIGNER MUST TAKE REASONABLY PRUDENT STEPS TO PROTECT AGAINST SYSTEM FAILURES INCLUDING BUT NOT LIMITED TO BACK UP OR SHUT DOWN MECHANISMS BECAUSE EACH END USER SYSTEM IS CUSTOMIZED AND DIFFERS FROM NATIONAL INSTRUMENTS TESTING PLATFORMS AND BECAUSE A USER OR APPLICATION DESIGNER MAY USE NATIONAL INSTRUMENTS PRODUCTS IN COMBINATION WITH OTHER PRODUCTS IN A MANNER NOT EVALUATED OR CONTEMPLATED BY NATIONAL INSTRUMENTS THE USER OR APPLICATION DESIGNER IS ULTIMATELY RESPONSIBLE FOR VERIFYING AND VALIDATING TH
63. PCI 6033E These devices have two input polarities unipolar and bipolar Unipolar input means that the input voltage range is between 0 and V where Vef is a positive reference voltage Bipolar input means that the input voltage range is between V and V ef So these devices have a unipolar input range of 10 V 0 to 10 V and a bipolar input range of 20 V x10 V You can program polarity and range settings on a per channel basis so that you can configure each input channel uniquely 3 6 ni com Chapter 3 Hardware Overview lay Note You can calibrate the PCI MIO 16XE 10 PCI MIO 16XE 50 NI PCI 6031E NI PCI 6032E and NI PCI 6033E AI circuitry for either a unipolar or bipolar polarity If you mix unipolar and bipolar channels in the scan list and you are using NI DAQ NI DAQ loads the calibration constants appropriate to the polarity for which AI channel 0 is configured The software programmable gain on these devices increases their overall flexibility by matching the input signal ranges to those that the ADC can accommodate The PCI MIO 16XE 50 has gains of 1 2 10 and 100 and the other devices have gains of 1 2 5 10 20 50 and 100 These gains are suited for a wide variety of signal levels With the proper gain setting you can use the full resolution of the ADC to measure the input signal Table 3 3 shows the overall input range and precision according to the input range configuration and gain used Table 3 3
64. PCI MIO 16E 4 and NI PCI 6071E A 6 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E A 18 PCI MIO 16XE 50 A 28 TRIGI signal input timing figure 4 30 output timing figure 4 30 timing connections 4 29 TRIG2 signal input timing figure 4 31 output timing figure 4 31 timing connections 4 30 PCI E Series User Manual triggers analog 3 12 above high level triggering mode figure 3 14 below low level triggering mode figure 3 13 block diagram 3 13 high hysteresis triggering mode trigger 3 15 inside region triggering mode figure 3 14 low hysteresis triggering mode figure 3 15 analog trigger specifications PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E A 10 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E A 20 digital trigger specifications PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E A 10 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E A 21 PCI MIO 16XE 50 A 30 questions about C 6 RTSI triggers 3 18 troubleshooting resources D 1 U UISOURCE signal 4 39 unipolar input output See polarity selection unpacking PCI E Series 1 5 UPDATE signal input signal timing figure 4 39 output signal timing figure 4 39 timing connections 4 38 1 14 ni com V VCC signal PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 7 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E table 4 9 PCI MIO 16XE 50 table 4 10 voltage
65. Q_OUT 1 Not available on the NI PCI 6032E or NI PCI 6033E Not available on the PCI MIO 16XE 10 PCI MIO 16XE 50 NI PCI 6032E or NI PCI 6033E Figure B 3 50 Pin E Series Connector Pin Assignments B 4 ni com Appendix B Optional Cable Connector Descriptions Figure B 4 shows the pin assignments for the 50 pin extended AI connector This is the other 50 pin connector available when you use the R1005050 cable assembly with the NI PCI 6031E NI PCI 6033E and NI PCI 6071E ACH16 ACH17 ACH18 ACH19 ACH20 ACH21 ACH22 ACH23 ACH32 ACH33 ACH34 ACH35 AISENSE2 ACH36 ACH37 ACH38 ACH39 ACH48 ACH49 ACH50 ACH51 ACH52 ACH53 ACH54 ACH55 O a m 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 ACH24 ACH25 ACH26 ACH27 ACH28 ACH29 ACH30 ACH31 ACH40 ACH41 ACH42 ACH43 AIGND ACH44 ACH45 ACH46 ACH47 ACH56 ACH57 ACH58 ACH59 ACH60 ACH61 ACH62 ACH63 National Instruments Corporation Figure B 4 50 Pin Extended Al Connector Pin Assignments B 5 PCI E Series User Manual Common Questions This appendix contains a list of commonly asked questions and their answers relating to usage and special features of the PCI E Series device General Information What are the PCI E Series devices The PCI E Series devices are swi
66. R1_GATE Signal Timing in Edge Detection Mode GPCTR1_OUT Signal This signal is available only as an output on the GPCTR1_OUT pin The GPCTR1_OUT signal monitors the TC device general purpose counter 1 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to high impedance at startup Figure 4 35 shows the timing requirements for the GPCTR1_OUT signal GPCTR1_SOURCE GPCTR1_OUT Pulse on TC GPCTR1_OUT Toggle Output on TC i TC PCI E Series User Manual Figure 4 35 GPCTR1_OUT Signal Timing GPCTR1_UP_DOWN Signal This signal can be externally input on the DIO7 pin and is not available as an output on the I O connector General purpose counter 1 counts down when this pin is at a logic low and counts up at a logic high This input can be disabled so that software can control the up down functionality and 4 44 ni com Chapter 4 Connecting Signals leave the DIO7 pin free for general use Figure 4 36 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of the PCI E Series device Vin SOURCE IL GATE lt lt tsc p 4 tsp gt A p gt gt tu cce a to gt tout Source Clock Period tec 50 ns minimum Source Pulse Width tsp 23 ns minimum Gate Set
67. Signal TRIGI AI Start Trigger ND IN START TRIGGER TRIG2 AI Stop Trigger ND IN STOP TRIGGER STARTSCAN AI Scan Start ND IN SCAN START SISOURCE ND IN SCAN CLOCK TIMEBASE CONVERT AI Convert ND IN CONVERT AIGATE ND IN EXTERNAL GATE WFTRIG AO Start Trigger ND OUT START TRIGGER UPDATE AO Update ND OUT UPDATE UISOURCE ND OUT UPDATE CLOCK TIMEBASE AOGATE ND OUT EXTERNAL GATE UN Caution If you enable a PFI line for output do not connect any external signal source to it if you do you can damage the device the computer and the connected equipment PCI E Series User Manual What are the power on states of the PFI and DIO lines on the I O connector At system power on and reset both the PFI and DIO lines are set to high impedance by the hardware This means that the device circuitry is not actively driving the output either high or low However these lines may have pull up or pull down resistors connected to them as shown in I O signal summary tables in Chapter 4 Connecting Signals These resistors weakly pull the output to either a logic high or logic low state For example DIO O0 is in the high impedance state after power on and the table in the V O Signal Summary PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E section of Chapter 4 Connecting Signals shows that there is a 50 KQ pull up resistor This pull up resistor sets the DIO 0 pin to a logic high when the output is in a high impedance state C 8 ni com Techni
68. User Manual 1 8 PFIO TRIGI signal description table 4 5 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 7 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E table 4 9 PCI MIO 16XE 50 table 4 11 PFI1 TRIG2 signal description table 4 5 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 7 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E table 4 9 PCI MIO 16XE 50 table 4 11 PFI2 CONVERT signal definition table 4 5 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 7 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E table 4 9 PCI MIO 16XE 50 table 4 11 PFI2 GPCTR1 SOURCE signal PCI MIO 16XE 50 table 4 11 PFI3 GPCTRI1 SOURCE signal definition table 4 5 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 7 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E table 4 9 PFI4 GPCTR1_GATE signal definition table 4 5 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 8 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E table 4 9 PCI MIO 16XE 50 table 4 11 ni com PFIS UPDATE signal definition table 4 6 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 8 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E table 4 9 PCI MIO 16XE 50 table 4 11 PFI6 WFTRIG signal definition table 4 6 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 8 PCI MIO 16XE 10 NI P
69. Z CONVERT pin Refer to Figures 4 12 and 4 13 for the relationship of STARTSCAN to the DAQ sequence As an input the CONVERT signal is configured in the edge detection mode You can select any PFI pin as the source for CONVERT and configure the polarity selection for either rising or falling edge The selected edge of the CONVERT signal initiates an A D conversion As an output the CONVERT signal reflects the actual convert pulse that is connected to the ADC even if the conversions are being externally generated by another PFI The output is an active low pulse with a pulse width of 50 to 100 ns This output is set to high impedance at startup Figures 4 20 and 4 21 show the input and output timing requirements for the CONVERT signal Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 20 CONVERT Input Signal Timing ty 50 to 100 ns Figure 4 21 CONVERT Output Signal Timing 4 34 ni com Chapter 4 Connecting Signals The ADC switches to hold mode within 60 ns of the selected edge This hold mode delay time is a function of temperature and does not vary from one conversion to the next Separate the CONVERT pulses by at least one conversion period The sample interval counter on the PCI E Series device normally generates the CONVERT signal unless you select some external source The counter 1s started by the STARTSCAN signal and contin
70. al ni com Chapter 4 Connecting Signals Analog Output Signal Connections The AO signals are DACOOUT DACIOUT EXTREF and AOGND 3 Note DACOOUT and DACIOUT are not available on the NI PCI 6032E and NI PCI 6033E EXTREF is not available on the PCI MIO 16XE 10 PCI MIO 16XE 50 NI PCI 6031E NI PCI 6032E or the NI PCI 6033E DACOOUT is the voltage output signal for AO channel 0 DAC1OUT is the voltage output signal for AO channel 1 EXTREF is the external reference input for both AO channels You must configure each AO channel individually for external reference selection in order for the signal applied at the external reference input to be used by that channel If you do not specify an external reference the channel uses the internal reference AO configuration options are described in the Analog Output section of Chapter 3 Hardware Overview AOGND is the ground reference signal for both AO channels and the external reference signal National Instruments Corporation 4 23 PCI E Series User Manual Chapter 4 Connecting Signals Figure 4 9 shows how to make AO connections and the external reference input connection to the PCI E Series device EXTREF OT DACOOUT z 4 External T to Channel 0 Reference yy i Signal ref optional z VOUT 0 Load AOGND VOUT 1 Load DAC1OUT Channel 1 Analog Output Channels E Series Device
71. al Instruments Corporation C 1 PCI E Series User Manual Appendix C Common Questions What type of 5 V protection do the PCI E Series devices have The PCI E Series devices have 5 V lines equipped with a self resetting 1 A fuse How do I use a PCI E Series device with the NI DAQ C API The NI DAQ User Manual for PC Compatibles describes the general programming flow when using the NI DAQ C API as well as contains example code For a list of functions that support the PCI E Series devices refer to the NI DAO Help NI DAQ 6 7 or later or the NI DAQ Function Reference Manual NI DAQ 6 6 or earlier Which version of NI DAQ supports the PCI MIO 16E 4 revision E or later Revision E and later of the PCI MIO 16E 4 requires NI DAQ for Windows 5 1 or later Installing and Configuring the Device PCI E Series User Manual How do you set the base address for a PCI E Series device The base address of a PCI E Series device is assigned automatically through the PCI bus protocol This assignment is completely transparent to you What jumpers should I be aware of when configuring my PCI E Series device The PCI E Series devices are jumperless and switchless Which NI document should I read first to get started using DAQ software The DAQ Quick Start Guide and the NI DAQ or application software release notes are good places to start What is the best way to test my PCI E Series device without programming the device If you are
72. als depending on the hardware and software in the system Use the manuals you have as follows e Getting Started with SCXI 1f you are using SCXT this is the first manual you should read It gives an overview of the SCXI system and contains the most commonly needed information for the modules chassis and software e SCXI hardware user manuals If you are using SCXI read these manuals next for detailed information about signal connections and Xii ni com About This Manual module configuration They also explain in greater detail how the module works and contain application hints DAQ hardware documentation This documentation has detailed information about the DAQ hardware that plugs into or is connected to the computer Use this documentation for hardware installation and configuration instructions specification information about the DAQ hardware and application hints Software documentation You may have both application software and NI DAQ software documentation NI application software includes LabVIEW Measurement Studio and VI Logger After you set up the hardware system use either the application software documentation or the NI DAQ documentation to help you write your application If you have a large complicated system it is worthwhile to look through the software documentation before you configure the hardware Accessory installation guides or manuals If you are using accessory products read the terminal blo
73. ammable function inputs 3 17 RTSI clocks 3 18 help professional services D 1 technical support D 1 I O connectors exceeding maximum ratings caution 4 1 pin assignments figure 50 pin analog input connector B 5 50 pin E Series connector B 4 68 pin E Series connector B 3 ni com 68 pin extended analog input connector B 2 NI PCI 6071E NI PCI 6031E and NI PCI 6033E 4 3 PCI MIO 16E 1 PCI MIO 16E 4 PCI MIO 16XE 50 PCI MIO 16XE 10 and NI PCI 6032E 4 2 input characteristic specifications PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E A 1 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E A 14 PCI MIO 16XE 50 A 24 input configurations available input modes DIFF table 3 5 NRSE table 3 5 RSE table 3 5 common mode signal rejection 4 22 differential connections DIFF input configuration 4 16 floating signal sources 4 18 ground referenced signal sources 4 17 nonreferenced signal sources 4 18 recommended configuration figure 4 15 single ended connections 4 20 floating signal sources RSE configuration 4 21 grounded signal sources NRSE configuration 4 21 input polarity and range mixing bipolar and unipolar channels note 3 7 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E actual range and measurement precision table 3 6 unipolar and bipolar 3 5 O National Instruments Corporation 1 7 Index PCI MIO 16XE 10 PCI MIO 16XE 50 NI PCI 6031E NI PCI 6032E and NI PCI 60
74. an just 10 Am9513 style counters within one chip In fact the DAQ STC has the complexity of more than 24 chips The DAQ STC makes possible PFI lines analog triggering selectable logic level and frequency shift keying The DAQ STC also makes buffered operations possible such as direct up down control single or pulse train generation equivalent time sampling buffered period and buffered semiperiod measurement What is the difference in timebases between the Am9513 counter timer and the DAQ STC The DAQ STC based MIO devices have a 20 MHz timebase The Am9513 based MIO devices have a 1 MHz or 5 MHz timebase PCI E Series User Manual C 6 ni com Appendix C Common Questions Do the counter timer applications that I wrote previously work with the DAQ STC If you are using NI DAQ with LabVIEW some of your applications drawn using the CTR VIs do still run However there are many differences in the counters between the PCI E Series and other devices the counter numbers are different timebase selections are different and the DAQ STC counters are 24 bit counters unlike the 16 bit counters on devices without the DAQ STC If you are using NI DAQ the answer is no the counter timer applications that you wrote previously do not work with the DAQ STC You must use the GPCTR functions ICTR and CTR functions do not work with the DAQ STC The GPCTR functions have the same capabilities as the ICTR and CTR functions plus more but you must r
75. cal Support and Professional Services Visit the following sections of the National Instruments Web site at ni com for technical support and professional services e Support Online technical support resources include the following Self Help Resources For immediate answers and solutions visit our extensive library of technical support resources available in English Japanese and Spanish at ni com support These resources are available for most products at no cost to registered users and include software drivers and updates a KnowledgeBase product manuals step by step troubleshooting wizards hardware schematics and conformity documentation example code tutorials and application notes instrument drivers discussion forums a measurement glossary and so on Assisted Support Options Contact NI engineers and other measurement and automation professionals by visiting ni com ask Our online system helps you define your question and connects you to the experts by phone discussion forum or email Training Visitni com custed for self paced tutorials videos and interactive CDs You also can register for instructor led hands on courses at locations around the world e System Integration If you have time constraints limited in house technical resources or other project challenges NI Alliance Program members can help To learn more call your local NI office or visit ni com alliance If you searched ni com
76. ce for TRIG2 and configure the polarity selection for either rising or falling edge The selected edge of the TRIG2 signal initiates the posttriggered phase of a pretriggered acquisition sequence In pretriggered mode the TRIGI signal initiates the data acquisition The scan counter indicates the minimum number of scans before TRIG2 can be recognized After the scan counter decrements to Zero it is loaded with the number of posttrigger scans to acquire while the 4 30 ni com Chapter 4 Connecting Signals acquisition continues The device ignores the TRIG2 signal if it is asserted prior to the scan counter decrementing to zero After the selected edge of TRIG2 is received the device acquires a fixed number of scans and the acquisition stops This mode acquires data both before and after receiving TRIG2 As an output the TRIG2 signal reflects the posttrigger in a pretriggered acquisition sequence even if the acquisition is being externally triggered by another PFI The TRIG2 signal is not used in posttriggered data acquisition The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to high impedance at startup Figures 4 16 and 4 17 show the input and output timing requirements for the TRIG2 signal Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 16 TRIG2 Input Signal Timing ty 50 to 100 ns i Figure 4 17 TRIG2 O
77. ck and cable assembly installation guides They explain how to physically connect the relevant pieces of the system Consult these guides when you are making the connections SCXI Chassis Manual If you are using SCXI read this manual for maintenance information on the chassis and installation instructions Related Documentation The following documents contain information you may find helpful DAQ STC Technical Reference Manual at ni com manuals NI Developer Zone tutorial Field Wiring and Noise Considerations for Analog Signals at ni com zone PCI Local Bus Specification Revision 2 2 The following NI manual at ni com manuals contains detailed information for the register level programmer National Instruments Corporation PCI E Series Register Level Programmer Manual This manual is available from NI by request You should not need the register level programmer manual if you are using NI driver or application software Using NI DAQ LabVIEW Measurement Studio and VI Logger software is easier than the low level programming described in the register level programmer manual xiii PCI E Series User Manual Introduction This chapter describes the PCI E Series devices lists what you need to get started describes the optional software and optional equipment and explains how to unpack the PCI E Series device About the PCI E Series Thank you for buying an NI PCI E Series device The PCI E Series devices
78. configuration analog input 4 12 figure 4 15 analog output 4 23 single ended connections 4 20 digital I O 4 24 floating signal sources RSE field wiring considerations 4 46 configuration 4 21 I O connector grounded signal sources NRSE exceeding maximum ratings configuration 4 21 caution 4 1 power connections 4 26 I O signal summary table timing connections 4 26 PCI MIO 16E 1 DAQ timing connections 4 28 PCI MIO 16E 4 and AIGATE signal 4 35 NI PCI 6071E 4 7 CONVERT signal 4 34 PCI MIO 16XE 10 EXTSTROBE signal 4 37 NI PCI 6031E SCANCLK signal 4 36 NI PCI 6032E and SISOURCE signal 4 35 NI PCI 6033E 4 8 STARTSCAN signal 4 32 PCI MIO 16XE 50 4 10 TRIGI signal 4 29 pin assignments TRIG2 signal 4 30 50 pin E Series connector B 4 typical posttriggered acquisition 50 pin extended analog input figure 4 28 connector B 5 typical pretriggered acquisition 68 pin E Series connector B 2 figure 4 29 68 pin extended analog input general purpose timing signal connector B 3 connections NI PCI 6071E NI PCI 6031E FREQ_OUT signal 4 46 and NI PCI 6033E GPCTRO_GATE signal 4 41 figure 4 3 GPCTRO_OUT signal 4 42 PCI MIO 16E 1 PCI MIO 16E 4 PCI MIO 16XE 50 PCI MIO 16XE 10 and NI PCI 6032 figure 4 2 GPCTRO_SOURCE signal 4 40 GPCTRO_UP_DOWN signal 4 42 GPCTR1_GATE signal 4 43 National Instruments Corporation 1 11 PCI E Series User Manual Index GPCTR1_OUT signal 4 44 GPCTR1_SOURCE signal
79. corresponding analog voltage or current analog channel 0 output signal analog channel 1 output signal data acquisition a system that uses the computer to collect receive and generate electrical signals decibel the unit for expressing a logarithmic measure of the ratio of two signal levels dB 20log10 V1 V2 for signals in volts PCI E Series User Manual Glossary DC DGND DIFF DIO DIP dithering DMA DNL DO E EEPROM EXTREF EXTSTROBE PCI E Series User Manual direct current digital ground signal differential mode digital input output dual inline package the addition of Gaussian noise to an AI signal direct memory access a method by which data can be transferred to from computer memory from to a device or memory on the bus while the processor does something else is the fastest method of transferring data to from computer memory differential nonlinearity a measure in LSB of the worst case deviation of code widths from their ideal value of 1 LSB digital output electrically erasable programmable read only memory ROM that can be erased with an electrical signal and reprogrammed external reference signal external strobe signal G 4 ni com FIFO FREQ OUT ft G GATE GPCTR GPCTRO GATE GPCTRO OUT GPCTRO SOURCE GPCTRO UP DOWN GPCTRI GATE GPCTRI OUT GPCTRI SOURCE GPCTRI UP DOWN National Instruments Corporation 6 5 Glossary first in first out memory buf
80. ctable Output coupling oooonoconoccnnnnaniananancnncnnnnno DC Output impedance esee 0 1 Q max Current drive tete 5 mA A 18 ni com Appendix A Specifications for PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI G033E Protection 4e ete erede Short circuit to ground Power on state 0 V 220 mV Dynamic Characteristics Settling time for full scale step 10 us to x1 LSB accuracy Slew Tate visite casei easel nmm it 5 V us NOISE costaron 60 UV ins DC to 1 MHz Stability Offset temperature coefficient 50 uV C Gain temperature coefficient 7 5 ppm C Digital 1 0 Number of channels 8 input output Compatibility eee TTL CMOS Digital logic levels Level Min Max Input low voltage OV 0 8 V Input high voltage 2V 5V Input low current Vin 0 V 320 uA Input high current Vin 5 V 10 uA Output low voltage lour 24 mA 0 4 V Output high voltage lour 13 mA 4 35 V Power on state essent Input high impedance Data transfers esee Programmed I O Max transfer rate esses 50 kwords s system dependent Constant sustainable rate 1 to 10 kwords s typical National Instruments Corporation A 19 PCI E Series User Manual Appendix A Timing 1 0 Triggers PCI E Series User Manual Numbe
81. d 4 28 show the input and output timing requirements for the UPDATE signal Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 27 UPDATE Input Signal Timing ty 300 to 350 ns Figure 4 28 UPDATE Output Signal Timing The DACs are updated within 100 ns of the leading edge Separate the UPDATE pulses with enough time that new data can be written to the DAC latches The PCI E Series device UI counter normally generates the UPDATE signal unless you select some external source The UI counter is started by the WFTRIG signal and can be stopped by software or the internal Buffer Counter D A conversions generated by either an internal or external UPDATE signal do not occur when gated by the software command register gate UISOURCE Signal Any PFI pin can externally input the UISOURCE signal which is not available as an output on the I O connector The UI counter uses the UISOURCE signal as a clock to time the generation of the UPDATE signal You must configure the PFI pin you select as the source for the UISOURCE signal in the level detection mode You can configure the National Instruments Corporation 4 39 PCI E Series User Manual Chapter 4 Connecting Signals polarity selection for the PFI pin for either active high or active low Figure 4 29 shows the timing requirements for the UISOURCE signal ty ea e t
82. devices increases their overall flexibility by matching the input signal ranges to those that the ADC can accommodate They have gains of 0 5 1 2 5 10 20 50 and 100 and are National Instruments Corporation 3 5 PCI E Series User Manual Chapter 3 Hardware Overview suited for a wide variety of signal levels With the proper gain setting you can use the full resolution of the ADC to measure the input signal Table 3 2 shows the overall input range and precision according to the input range configuration and gain used Table 3 2 Actual Range and Measurement Precision PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E PCI E Series User Manual Range Configuration Gain Actual Input Range Precision 0 to 10 V 1 0 0 to 10 V 2 44 mV 2 0 0to 45 V 1 22 mV 5 0 0to 42 V 488 28 uV 10 0 Oto 1V 244 14 uV 20 0 0 to 500 mV 122 07 uV 50 0 0 to 200 mV 48 83 uV 100 0 0 to 100 mV 24 41 uV 5to 45V 0 5 10 to 10 V 4 88 mV 1 0 5 to 5 V 2 44 mV 2 0 2 5 to 42 5 V 1 22 mV 5 0 1to 1V 488 28 uV 10 0 500 to 500 mV 244 14 uV 20 0 250 to 250 mV 122 07 uV 50 0 100 to 100 mV 48 83 uV 100 0 50 to 50 mV 24 41 uV The value of 1 LSB of the 12 bit ADC that is the voltage increment corresponding to a change of one count in the ADC 12 bit count Note Refer to Appendix A Specifications for absolute maximum ratings PCI MIO 16XE 10 PCI MIO 16XE 50 NI PCI 6031E NI PCI 6032E and NI
83. dix A Specifications for PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E Dynamic Characteristics Settling time for full scale step 3 us to 0 5 LSB accuracy Slew tate erem 20 V us Nolan edad 200 uVrms DC to 1 MHz Glitch energy at midscale transition Magnitude Reglitching disabled 20 mV Reglitching enabled 4 mV A OS 1 5 us Stability Offset temperature coefficient 50 uV C Gain temperature coefficient Internal reference 25 ppm C External reference 25 ppm C Digital 1 0 Number of channels 8 input output Compatibility eee TTL CMOS Digital logic levels Level Min Max Input low voltage 0 0 V 0 8 V Input high voltage 2 0 V 5 0 V Input low current V 0 V 320 uA Input high current V 5 V 10 pA Output low voltage 1 24 mA 0 4 V Output high voltage 1 13 mA 4 35 V PCI E Series User Manual A 8 ni com Appendix A Power on state Data transfers Timing 1 0 Number of channels Resolution Counter timers Frequency scaler Compatibility Base clocks available Counter timers Frequency scaler Base clock accuracy Max source frequency Min source pulse duration Min gate pulse duration Data transfers DMA modes National Instruments Corporati
84. e Calibration interval External calibration reference Onboard calibration reference Level ee Temperature coefficient Long term stability O National Instruments Corporation Specifications for PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI G033E Programmable 255 kHz internal 4 MHz external 10 kQ DC 0 5 to Vcc 40 5 V when configured as a digital signal x35 V when configured as an analog signal or disabled x35 V powered off 1 of fullscale range Rising or falling edge 10 ns min 5 000 V 21 0 mV over full operating temperature actual value stored in EEPROM 0 6 ppm C max 6 ppm 1 000 h PCI E Series User Manual Appendix A Specifications for PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI G033E Bus Interface TS Dea oh diserte ta Master slave Power Requirement x25 VDC E5498 ih ihi eb ee 15A Power available at I O connector 4 65 to 5 25 VDC atl A Physical Dimensions not including connectors 33 8 by 9 9 cm 13 3 by 3 9 in I O connector PCI MIO 16XE 10 NIPCI 6032E teet 68 pin male SCSI II type NI PCI 6031E NI PCI 6033E 100 pin female 0 05 D type Maximum Working Voltage Maximum working voltage refers to the signal voltage plus the common mode voltage Channel to earth esee 42 V Installation Category II Channel to channel
85. e however the following guidelines may be useful Unpacking For the AI signals shielded twisted pair wires for each AI pair yield the best results assuming that you use differential inputs Tie the shield for each signal pair to the ground reference at the source You should route the analog lines separately from the digital lines When using a cable shield use separate shields for the analog and digital halves of the cable Failure to do so results in noise coupling into the analog signals from transient digital signals The PCI E Series device is shipped in an antistatic package to prevent electrostatic damage to the device Electrostatic discharge can damage several components on the device UN Caution Never touch the exposed pins of connectors National Instruments Corporation 1 5 PCI E Series User Manual Chapter 1 Introduction To avoid such damage in handling the device take the following precautions e Ground yourself using a grounding strap or by holding a grounded object e Touch the antistatic package to a metal part of the computer chassis before removing the device from the package Remove the device from the package and inspect the device for loose components or any sign of damage Notify NI if the device appears damaged in any way Do not install a damaged device into the computer Store the PCI E Series device in the antistatic envelope when not in use Safety Information PCI E Series Us
86. e see the Safety Information section of Chapter 1 Introduction for precautions to take Bold text denotes items that you must select or click in the software such as menu items and dialog box options Bold text also denotes parameter names and hardware labels Italic text denotes variables emphasis a cross reference or an introduction to a key concept This font also denotes text that is a placeholder for a word or value that you must supply Macintosh refers to all Macintosh computers with PCI bus unless otherwise noted Text in this font denotes text or characters that you should enter from the keyboard sections of code programming examples and syntax examples This font is also used for the proper names of disk drives paths directories programs subprograms subroutines device names functions operations variables filenames and extensions and code excerpts NI DAQ refers to the NI DAQ driver software for Macintosh or PC compatible computers unless otherwise noted Refers to all PC AT series computers with PCI bus unless otherwise noted SCXI stands for Signal Conditioning eXtensions for Instrumentation and is a National Instruments product line designed to perform front end signal conditioning for NI plug in DAQ devices National Instruments Documentation PCI E Series User Manual The PCI E Series User Manual is one piece of the documentation set for the DAQ system You could have any of several types of manu
87. e PCI E Series includes the following devices e PCI MIO 16E 1 e PCI MIO 16E 4 e PCI MIO 16XE 10 e PCI MIO 16XE 50 e NI PCI 6031E MIO 64XE 10 e NIPCI 6032E AI 16XE 10 e NIPCI 6033E AI 64XE 10 e NI PCI 6071E MIO 64E 1 The PCI E Series devices are high performance multifunction analog digital and timing I O devices for PCI bus computers Supported functions include analog input AD analog output AO digital I O DIO and timing I O TIO Conventions Used in This Manual lt gt 3 The following conventions are used in this manual Angle brackets that contain numbers separated by an ellipsis represent a range of values associated with a bit or signal name for example DBIO lt 3 0 gt The symbol leads you through nested menu items and dialog box options to a final action The sequence File Page Setup Options directs you to pull down the File menu select the Page Setup item and select Options from the last dialog box The symbol indicates that the text following it applies only to specific PCIE Series devices This icon denotes a note which alerts you to important information National Instruments Corporation Xi PCI E Series User Manual About This Manual bold italic Macintosh monospace NI DAQ PC SCXI This icon denotes a caution which advises you of precautions to take to avoid injury data loss or a system crash When this symbol is marked on the devic
88. e ard edes eund 4 37 UPDATES Signal xa desde 4 38 UISOURCE Sign l lni 3 5 mn labs 4 39 General Purpose Timing Signal Connections see 4 40 GPCTRO SOURCE Signal eset iecit ete cte titt ene 4 40 GPCTRO GATE Signal eei epiac teretes 4 41 GPETRO QUT Signal 2 m tet HL gem eee 4 42 GPCTRO UP DOWN Signal eene 4 42 GPCTR1 SOURCE Signal n a e ea is 4 43 GPCTRI GATE Signal icone eee eme 4 43 GPCTR1 OUT Signal iii me Ob Eee nee 4 44 GPCTRI UP DOWN Signal eee 4 44 FREQ OU L Siftial comi 4 46 Field Wiring Considerations sissies sirsiran i esesta rien iaee sasaaina ES 4 46 Chapter 5 Calibration Loading Calibration Constants esses nennen ren enne enne 5 1 Self Calibration a oi mee detur ed eet 5 2 External Calibracion 5 2 Other Considerations orientada 5 3 Appendix A Specifications Appendix B Optional Cable Connector Descriptions Appendix C Common Questions O National Instruments Corporation ix PCI E Series User Manual Contents Appendix D Technical Support and Professional Services Glossary Index PCI E Series User Manual X ni com About This Manual This manual describes the electrical and mechanical aspects of the devices in the PCI E Series product line and contains information concerning their operation and programming Unless otherwise noted text applies to all devices in the PCI E Series Th
89. ect the appropriate product family followed by the product and a link to the DoC appears in Adobe Acrobat format Click the Acrobat icon to download or read the DoC National Instruments Corporation A 23 PCI E Series User Manual Appendix A Specifications for PCI MIO 16XE 50 PCI MIO 16XE 50 Analog Input Input Characteristics Number of channels 16 single ended or 8 differential software selectable Type of ADC eene Successive approximation Resolution oooococccnnooonnnncononananocononananoconnno 16 bits 1 in 65 536 Max sampling rate esses 20 kS s guaranteed Input signal ranges Device Range Software Selectable Device Gain Software Selectable Bipolar Unipolar 1 10 V 0 to 10 V 2 5 V 0to5 V 10 xl V Otol V 100 0 1 V 0to0 1 V Input coupling eeeee DC Max working voltage signal common mode The common mode signal the average of two signals in a differential pair should remain within 8 V of ground and each input should remain within 11 V of ground Overvoltage protection 25 V powered on x15 V powered off Inputs protected sssss ACH lt 0 15 gt AISENSE FIFO buffer size eese 2 048 samples PCI E Series User Manual A 24 ni com Appendix A Data transfers cccccccccnnnnnnnnanananana
90. ect to unsynchronized gating sources The OUT output timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated clock signals on the PCI E Series devices Figure 4 36 shows the OUT signal referenced to the rising edge of a source signal Any OUT signal state changes occur within 80 ns after the rising or falling edge of the source signal FREQ OUT Signal This signal is available only as an output on the FREQ OUT pin The PCIE Series device frequency generator outputs the FREQ OUT pin The frequency generator is a 4 bit counter that can divide its input clock by the numbers 1 through 16 The input clock of the frequency generator is software selectable from the internal 10 MHz and 100 KHz timebases The output polarity is software selectable This output is set to high impedance at startup Field Wiring Considerations PCI E Series User Manual Environmental noise can seriously affect the accuracy of measurements made with the PCI E Series device if you do not take proper care when running signal wires between signal sources and the device The following recommendations apply mainly to AI signal routing to the device although they also apply to signal routing in general Minimize noise pickup and maximize measurement accuracy by taking the following precautions Use differential AI connections to reject common mode noise e Use individually shielded twisted pair wires to connect AI si
91. ed by the product and a link to the DoC appears in Adobe Acrobat format Click the Acrobat icon to download or read the DoC National Instruments Corporation A 13 PCI E Series User Manual Appendix A Specifications for PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI G033E PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E Analog Input Input Characteristics Number of channels PCI MIO 16XE 10 NI PCI 6032E sss NI PCI 6031E NI PCI 6033E Type of ADC eem Resolution sssrinin Max sampling rate single channel Input signal ranges 16 single ended or 8 differential software selectable 64 single ended or 32 differential software selectable Successive approximation 16 bits 1 in 65 536 100 kS s guaranteed Voltage Range Gain Software Selectable Software Selectable Bipolar Unipolar 1 10 V Oto 10 V 2 5 V 0to5V 5 2 V 0to2V 10 1 V 0to1V 20 0 5 V 0 to 0 5 V 50 0 2 V 0 to 0 2 V 100 0 1 V 0 to 0 1 V Refer to the settling time table in the Dynamic Characteristics section for multichannel rates A 14 ni com PCI E Series User Manual Appendix A Specifications for PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E Input coupling eese DC Max working voltage Each input should remain within x11 V of ground Overvoltage protection
92. elative accuracy eseeeee x 0 5 LSB typ dithered x1 5 LSB max undithered DNE e ttr exp 0 5 LSB typ 1 LSB max No missing codes ssesees 12 bits guaranteed Offset error PCI MIO 16E 1 State NI PCI 6071E PCI MIO 16E 4 Pregain error after calibration 12 uV max 16 uV max Pregain error before calibration 2 5 mV max 4 0 mV max Postgain error after calibration 0 5 mV max 0 8 mV max Postgain error before calibration 100 mV max 200 mV max Gain error relative to calibration reference After calibration gain 1 0 02 of reading max Before calibration 2 5 of reading max Gain with gain error adjusted to 0 at gain 1 0 02 of reading max Amplifier Characteristics Input impedance Normal powered on 100 GQ in parallel with 100 pF Powered off esses 820 Q min Overload 5 er tenen 820 Q min Input bias current sessses 200 pA Input offset current sss 100 pA National Instruments Corporation A 3 PCI E Series User Manual Appendix A Specifications for PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E CMRR all input ranges DC to 60 Hz CMRR PCI MIO 16E 1 Gain NI PCI 6071E PCI MIO 16E 4 0 5 95 dB 85
93. enced single ended input RSE See RSE referenced single ended input register level programming 1 4 reglitching questions about C 3 reglitch selection analog output 3 12 related documentation xiii requirements for getting started 1 2 RSE referenced single ended input description table 3 5 recommended configuration figure 4 15 single ended connections for floating signal sources 4 21 RTSI bus signal connection figure 3 19 RTSI clocks 3 18 RTSI trigger lines overview 3 18 signal connections figure 3 19 specifications PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E A 11 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E A 21 PCI MIO 16XE 50 A 30 S safety information 1 6 safety specifications PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E A 12 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E A 23 PCI MIO 16XE 50 A 31 sampling rate C 1 ni com Index SCANCLK signal signal descriptions table 4 4 description table 4 5 input configurations PCI MIO 16E 1 PCI MIO 16E 4 and common mode signal rejection 4 22 NI PCI 6071E table 4 7 differential connections PCI MIO 16XE 10 NI PCI 6031E DIFF input configuration 4 16 NI PCI 6032E and NI PCI 6033E floating signal sources 4 18 table 4 9 ground referenced signal PCI MIO 16XE 50 table 4 10 sources 4 17 timing connections 4 36 nonreferenced signal settling time 3 9 sources 4 18 signal connections recommended
94. er Manual The following section contains important safety information that you must follow during installation and use of the product Do not operate the product in a manner not specified in this document Misuse of the product can result in a hazard You can compromise the safety protection built into the product if the product is damaged in any way If the product is damaged return it to NI for repair If the product is rated for use with hazardous voltages 230 Vims 42 4 V y or 60 Vac you may need to connect a safety earth ground wire according to the installation instructions Refer to Appendix A Specifications for maximum voltage ratings Do not substitute parts or modify the product Use the product only with the chassis modules accessories and cables specified in the installation instructions You must have all covers and filler panels installed during operation of the product Do not operate the product in an explosive atmosphere or where there may be flammable gases or fumes Operate the product only at or below the pollution degree stated in Appendix A Specifications Pollution is foreign matter in a solid liquid or gaseous state that can produce a reduction of dielectric strength or surface resistivity The following is a description of pollution degrees e Pollution Degree 1 means no pollution or only dry nonconductive pollution occurs The pollution has no influence 1 6 ni com Chapter 1 Introduction e Poll
95. es User Manual Glossary TC t Lm gw out THD thermocouple TRIG tsc tsp TTL two s complement U UI UISOURCE unipolar UPDATE PCI E Series User Manual terminal count the ending value of a counter gate hold time gate setup time gate pulse width output delay time total harmonic distortion the ratio of the total rms signal due to harmonic distortion to the overall rms signal in dB or percent a temperature sensor created by joining two dissimilar metals The junction produces a small voltage as a function of the temperature trigger signal source clock period source pulse width transistor transistor logic given a number x expressed in base 2 with n digits to the left of the radix point the base 2 number 2n x update interval update interval counter clock signal a signal range that is always positive for example 0 to 10 V update signal G 10 ni com VDC VI waveform WFTRIG Glossary volts volts direct current virtual instrument 1 a combination of hardware and or software elements typically used with a PC that has the functionality of a classic stand alone instrument 2 a LabVIEW software module VI which consists of a front panel user interface and a block diagram program volts input high volts input low volts in measured voltage volts output high volts output low reference voltage volts root mean square multiple voltage readings taken at
96. es the voltage output of AO channel 0 This pin is not available on the NI PCI 6032E or NI PCI 6033E DACIOUT AOGND Output Analog Channel 1 Output This pin supplies the voltage output of AO channel 1 This pin is not available on the NI PCI 6032E or NI PCI 6033E EXTREF AOGND Input External Reference This is the external reference input for the AO circuitry This pin is not available on the PCI MIO 16XE 10 PCI MIO 16XE 50 NI PCI 6031E NI PCI 6032E or NI PCI 6033E AOGND AO Ground The AO voltages are referenced to this node All three ground references AIGND AOGND and DGND are connected together on the PCI E Series device DGND Digital Ground This pin supplies the reference for the digital signals at the I O connector as well as the 5 VDC supply All three ground references AIGND AOGND and DGND are connected together on the PCI E Series device DIO lt 0 7 gt DGND Input or Output DIO Signals DIO6 and 7 can control the up down signal of general purpose counters O and 1 respectively DIO7 is the MSB and DIOO is the LSB PCI E Series User Manual ni com Chapter 4 Connecting Signals Signal Name Reference Direction Description 5V DGND Output 5 VDC Source These pins are fused for up to 1 A of 5 V supply The fuse is self resetting SCANCLK DGND Output Scan Clock This pin pulses once for each A D conve
97. etect mode Min gate pulse duration 10 ns edge detect mode Data transfers DMA interrupts programmed I O DMA modes vectra Scatter gather Triggers Digital Trigger Compatibility eee TTL RESPONSE iio riales Rising or falling edge Pulse width asar tantra et 10 ns min RTSI Trigger ln cornisa an 7 Calibration Recommended warm up time 15 min Calibration interval year External calibration reference gt 6 and 9 999 V Onboard calibration reference leve l 5 000 V 3 0 mV over full operating temperature actual value stored in EEPROM Temperature coefficient 2 ppm C max Long term stability 15 ppm 1 000 h PCI E Series User Manual A 30 ni com Appendix A Specifications for PCI MIO 16XE 50 Bus Interface TPL t imet ARIS Master slave Power Requirement ES VDC 5590 ihid LIA Power available at I O connector 4 65 to 45 25 VDC at1 A Physical Dimensions not including connectors 17 5 by 9 9 cm 6 9 by 3 9 in VO connector eet tern 68 pin male SCSI II type Maximum Working Voltage Maximum working voltage refers to the signal voltage plus the common mode voltage Channel to earth esses 42 V Installation Category II Channel to channel 42 V Installation Category II Env
98. event is received A typical posttriggered DAQ sequence is shown in Figure 4 12 Pretriggered data acquisition allows you to view data that is acquired before the trigger of interest in addition to data acquired after the trigger Figure 4 13 shows a typical pretriggered DAQ sequence Each signal shown in these figures is described later in this chapter TRIG1 d 1 d STARTSCAN l l l CONVERT Ws Scan Counter 4 3 2 4 0 Figure 4 12 Typical Posttriggered Acquisition 4 28 ni com Chapter 4 Connecting Signals me SL me A STARTSCAN l l l l l cowea AE UE UU U UU UE QU UU Scan Counter 3 2 14 0 12 12 9 E 9 Figure 4 13 Typical Pretriggered Acquisition TRIG1 Signal Any PFI pin can externally input the TRIGI signal which is available as an output on the PFIO TRIGI pin Refer to Figures 4 12 and 4 13 for the relationship of TRIGI to the DAQ sequence As an input the TRIGI signal is configured in the edge detection mode You can select any PFI pin as the source for TRIGI and configure the polarity selection for either rising or falling edge The selected edge of the TRIGI signal starts the DAQ sequence for both posttriggered and pretriggered acquisitions The PCI MIO 16E 1 PCI MIO 16E 4 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E NI PC
99. ewrite the application with the GPCTR function calls I m using one of the general purpose counter timers on my PCI E Series device but I do not see the counter timer output on the I O connector What am I doing wrong If you are using NI DAQ you must configure the output line to output the signal to the I O connector Use the Select Signal call in NI DAQ to configure the output line By default all timing I O lines except EXTSTROBE are high impedance What are the PFIs and how do I configure these lines PFIs are Programmable Function Inputs These lines serve as connections to virtually all internal timing signals If you are using NI DAQ or LabWindows CVI use the Select_Signal function to route internal signals to the I O connector route external signals to internal timing sources or tie internal timing signals together If you are using NI DAQ with LabVIEW and you want to connect external signal sources to the PFI lines you can use AI Clock Config AI Trigger Config AO Clock Config AO Trigger and Gate Config and Counter Set Attribute advanced level VIs to indicate which function the connected signal serves Use the Route Signal VI to enable the PFI lines to output internal signals National Instruments Corporation C 7 PCI E Series User Manual Appendix C Common Questions Table C 1 Signal Name Equivalencies Hardware LabVIEW Signal Name Route Signal NI DAQ Select
100. fer FIFOs are often used on DAQ devices to temporarily store incoming or outgoing data until that data can be read or written For example an analog input FIFO stores the results of A D conversions until the data can be read into system memory Programming the DMA controller and servicing interrupts can take several milliseconds in some cases During this time data accumulates in the FIFO for future retrieval With a larger FIFO longer latencies can be tolerated In the case of analog output a FIFO permits faster update rates because the waveform data can be stored in the FIFO ahead of time This again reduces the effect of latencies associated with getting the data from system memory to the DAQ device frequency output signal feet gate signal general purpose counter general purpose counter 0 gate signal general purpose counter 0 output signal general purpose counter 0 clock source signal general purpose counter 0 up down general purpose counter 1 gate signal general purpose counter 1 output signal general purpose counter 1 clock source signal general purpose counter 1 up down PCI E Series User Manual Glossary INL interchannel delay LSB MB MIO MITE PCI E Series User Manual hour hexadecimal hertz input output the transfer of data to from a computer system involving communications channels operator interface devices and or data acquisition and control interfaces current output high current
101. format Click the Acrobat icon to download or read the DoC PCI E Series User Manual A 32 ni com Optional Cable Connector Descriptions This appendix describes the connectors on the optional cables for the PCIE Series devices Figure B 1 shows the pin assignments for the 68 pin E Series connector This connector is available when you use the SH6868 or R6868 cable assemblies with the PCI MIO 16E 1 PCI MIO 16E 4 PCI MIO 16XE 10 PCI MIO 16XE 50 and NI PCI 6032E It is also one of the two 68 pin connectors available when you use the SH1006868 cable assembly with the NI PCI 6031E NI PCI 6033E or NI PCI 6071E National Instruments Corporation B 1 PCI E Series User Manual Appendix B PCI E Series User Manual Optional Cable Connector Descriptions ACH8 ACH1 AIGND ACH10 ACH3 AIGND ACH4 AIGND ACH13 ACH6 AIGND ACH15 DACOOUT DAC1OUT EXTREF DIO4 DGND DIO1 DIO6 DGND 45V DGND DGND PFIO TRIG1 PFI1 TRIG2 DGND 5V DGND PFI5 UPDATE PFI6 WFTRIG DGND PRI9 GPCTRO_GATE GPCTRO_OUT FREQ_OUT 34 Ma 68 33 67 32 66 31 65 30 64 28 63 29 62 27 61 26 60 25 59 Nm AB 58 N wo 57 N N 56 N piri 55 N o 54 E c 53 A 00 52 mk N 51 A o 50 al 49 a A 48 A Co 47 A M 46 45 A
102. g the CalDACs with the values stored in the EEPROM NI DAQ software determines when this is necessary and does it automatically If you are not using NI DAQ you must load these values yourself In the EEPROM there is a user modifiable calibration area in addition to the permanent factory calibration area This means that you can load the CalDACs with values either from the original factory calibration or from a calibration that you subsequently performed National Instruments Corporation 5 1 PCI E Series User Manual Chapter 5 Calibration This method of calibration is not very accurate because it does not take into account the fact that the device measurement and output voltage errors can vary with time and temperature It is better to self calibrate when the device is installed in the environment in which it is used Self Calibration The PCI E Series device can measure and correct for almost all of its calibration related errors without any external signal connections The NI software provides a self calibration method This self calibration process which generally takes less than a minute is the preferred method of assuring accuracy in your application Initiate self calibration to minimize the effects of any offset gain and linearity drifts particularly those due to warmup Immediately after self calibration the only significant residual calibration error could be gain error due to time or temperature drift of the onboard
103. g output analog output ground signal Application Specific Integrated Circuit a proprietary semiconductor component designed and manufactured to perform a set of specific functions basic input output system BIOS functions are the fundamental level of any PC or compatible computer BIOS functions embody the basic operations needed for successful use of the computer s hardware resources a signal range that includes both positive and negative values for example 5 to 5 V G 2 ni com CalDAC CH channel rate cm CMOS CMRR CONVERT counter timer CTR D D A DAC DACOOUT DACIOUT DAQ dB National Instruments Corporation G 3 Glossary Celsius calibration DAC channel pin or wire lead to which you apply or from which you read the analog or digital signal Analog signals can be single ended or differential For digital signals you group channels to form ports Ports usually consist of either four or eight digital channels reciprocal of the interchannel delay centimeter complementary metal oxide semiconductor common mode rejection ratio a measure of an instrument s ability to reject interference from a common mode signal usually expressed in decibels dB convert signal a circuit that counts external pulses or clock pulses timing counter digital to analog digital to analog converter an electronic device often an integrated circuit that converts a digital number into a
104. generation starts 4 Initiate AO waveform generation Can I programmatically enable different channels on a PCI E Series device to acquire in different modes For example Channel 0 is differential and Channel 1 is RSE Different channels on a PCI E Series device can be enabled to acquire in different modes However different pairs of channels are used in different modes In the example configuration given above ACHO and ACH8 would be configured in differential mode and ACH1 and AIGND would be configured in RSE mode In this configuration ACH8 could not be used in a single ended configuration To enable multi mode scanning in LabVIEW you would use the coupling and input config cluster input of the AI Config VI This input has a 1 to 1 correspondence with the channels array input of the AI Config VI Therefore you must list all channels either individually or in groups of channels with the same input configuration For example if you want Channel 0 to be differential and Channels 1 and 2 to be RSE Figure C 1 demonstrates how to program this configuration in LabVIEW eno change T eno change 7 differential vilref single ended channels 0 Figure C 1 Configuring Channels for Different Acquisition Modes in LabVIEW To enable multi mode scanning in using NI DAQ functions call the AI Configure function for each channel C 4 ni com Appendix C Common Questions I am seeing crosstalk or
105. ghost voltages when sampling multiple channels What does this mean You may be experiencing a phenomenon called charge injection Charge injection occurs when you are sampling a series of high output impedance sources with a multiplexer Multiplexers contain switches usually made of switched capacitors When one of the channels for example Channel 0 is selected in a multiplexer those capacitors accumulate charge When the next channel for example Channel 1 is selected the accumulated charge that is current leaks backward through that channel If the output impedance of the source connected to Channel 1 is high enough the resulting reading can somewhat reflect the voltage trends in Channel 0 To circumvent this problem you must use a voltage follower op amp with unity gain for each of the high impedance sources before connecting up to the DAQ device or decrease the rate at which each channel is sampled Another common cause of channel crosstalk is due to sampling among multiple channels at various gains In this situation the settling times may increase For more information on charge injection and sampling channels at different gains refer to Chapter 3 Hardware Overview How are the AI channels of the NI PCI 6031E NI PCI 6033E and NI PCI 6071E addressed when they are used in differential mode The 32 differential channel pairs are addressed as follows Differential Channel Name I O Terminals lt 0 7 gt ACH
106. gnals to the device With this type of wire the signals attached to the CH and CH inputs are twisted together and then covered with a shield You then connect this shield only at one point to the signal source ground This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference e Route signals to the device carefully Keep cabling away from noise sources The most common noise source in a PCI DAQ system is the video monitor Separate the monitor from the analog signals as much as possible 4 46 ni com Chapter 4 Connecting Signals The following recommendations apply for all signal connections to the PCIE Series device e Separate PCI E Series device signal lines from high current or high voltage lines These lines can induce currents in or voltages on the PCI E Series device signal lines if they run in parallel paths at a close distance To reduce the magnetic coupling between lines separate them by a reasonable distance if they run in parallel or run the lines at right angles to each other e Do not run signal lines through conduits that also contain power lines e Protect signal lines from magnetic fields caused by electric motors welding equipment breakers or transformers by running them through special metal conduits For more information refer to the NI Developer Zone tutorial Field Wiring and Noise Consideration for Analog Signals at ni com z
107. h line for either input or output At system startup and reset the DIO ports are all high impedance The hardware up down control for general purpose counters 0 and 1 are connected onboard to DIO6 and DIO7 respectively Thus you can use DIO6 and DIO7 to control the general purpose counters The up down control signals are input only and do not affect the operation of the DIO lines Timing Signal Routing PCI E Series User Manual The DAQ STC provides a very flexible interface for connecting timing signals to other devices or external circuitry The PCI E Series device uses the RTSI bus to interconnect timing signals between devices and the Programmable Function Input PFI pins on the I O connector to connect the device to external circuitry These connections are designed to enable the PCI E Series device to both control and be controlled by other devices and circuits There are a total of 13 timing signals internal to the DAQ STC that can be controlled by an external source These timing signals can also be controlled by signals generated internally to the DAQ STC and these selections are fully software configurable For example the signal routing multiplexer for controlling the CONVERT signal is shown in Figure 3 12 3 16 ni com Chapter 3 Hardware Overview X gt gt RTSI Trigger lt 0 6 gt lt gt gt gt gt gt gt P
108. he measurement system ground output pin a counter output pin where the counter can generate various TTL pulse waveforms Peripheral Component Interconnect a high performance expansion bus architecture originally developed by Intel to replace ISA and EISA It is achieving widespread acceptance as a standard for PCs and work stations it offers a theoretical maximum transfer rate of 132 MB s Programmable Function Input PFIO trigger 1 PFI1 trigger 2 PFI2 convert O National Instruments Corporation G 7 PCI E Series User Manual Glossary PFI3 GPCTRI SOURCE PFI4 GPCTR1_GATE PFIS UPDATE PFI6 WFTRIG PFI7 STARTSCAN PFI8 GPCTRO_SOURCE PFI9 GPCTRO_GATE PGIA port ppm pu R RAM reglitch rms RSE RTD RTSIbus PCI E Series User Manual PFI3 general purpose counter 1 source PFI4 general purpose counter 1 gate PFI5 update PFI6 waveform trigger PFI7 start of scan PFI8 general purpose counter 0 source PFI9 general purpose counter 0 gate Programmable Gain Instrumentation Amplifier 1 a communications connection on a computer or a remote controller 2 a digital port consisting of four or eight lines of digital input and or output parts per million pull up random access memory to modify the glitches in a signal to make them less disruptive root mean square referenced single ended mode all measurements are made with respect to a common reference measurement system or a ground also ca
109. he receiver is connected Consult the dealer or an experienced radio TV technician for help Canadian Department of Communications This Class B digital apparatus meets all requirements of the Canadian Interference Causing Equipment Regulations Cet appareil num rique de la classe B respecte toutes les exigences du R glement sur le mat riel brouilleur du Canada Compliance to EU Directives Readers in the European Union EU must refer to the Manufacturer s Declaration of Conformity DoC for information pertaining to the CE Mark compliance scheme The Manufacturer includes a DoC for most every hardware product except for those bought for OEMs if also available from an original manufacturer that also markets in the EU or where compliance is not required as for electrically benign apparatus or cables To obtain the DoC for this product click Declaration of Conformity at ni com hardref nsf This Web site lists the DoCs by product family Select the appropriate product family followed by your product and a link to the DoC appears in Adobe Acrobat format Click the Acrobat icon to download or read the DoC Certain exemptions may apply in the USA see FCC Rules 15 103 Exempted devices and 15 105 c Also available in sections of CFR 47 The CE Mark Declaration of Conformity will contain important supplementary information and instructions for the user or installer Contents About This Manual Conventions Used in This Manual
110. her dedicated outputs for the remainder of the timing signals As inputs the PFI signals are programmable and can control any DAQ waveform generation and general purpose timing signals The DAQ signals are explained in the DAQ Timing Connections section The waveform generation signals are explained in the Waveform Generation Timing Connections section The general purpose timing signals are explained in the General Purpose Timing Signal Connections section PCI E Series User Manual 4 26 ni com Chapter 4 Connecting Signals All digital timing connections are referenced to DGND This reference is demonstrated in Figure 4 11 which shows how to connect an external TRIGI source and an external CONVERT source to two PCI E Series device PFI pins PFIO TRIG1 PFI2 CONVERT TRIG1 CONVERT Source Source DGND 1 0 Connector E Series Device Figure 4 11 TIO Connections Programmable Function Input Connections There are a total of 13 internal timing signals that you can externally control from the PFI pins The source for each of these signals is software selectable from any of the PFIs when you want external control This flexible routing scheme reduces the need to change the physical wiring to the device I O connector for different applications requiring alternative wiring You can individually enable each of the PFI pins t
111. ices that plug into the building power system fall into this category The difference in ground potential between two instruments connected to the same building power system is typically between 1 and 100 mV but can be much higher if power distribution circuits are not properly connected If a grounded signal source is improperly measured this difference may appear as an error in the measurement The connection instructions for grounded signal sources are designed to eliminate this ground potential difference from the measured signal Input Configurations PCI E Series User Manual You can configure the PCI E Series device for one of three input modes NRSE RSE or DIFF The following sections discuss the use of single ended and differential measurements and considerations for measuring both floating and ground referenced signal sources Figure 4 4 summarizes the recommended input configuration for both types of signal sources 4 14 ni com Chapter 4 Connecting Signals Input Signal Source Type Floating Signal Source Not Connected to Building Ground Grounded Signal Source Examples Ungrounded Thermocouples Signal Conditioning with Isolated Outputs Battery Devices Examples Plug in Instruments with Nonisolated Outputs ACH M ACH EJ Y EV
112. igure 4 8 shows how to connect a grounded signal source to a channel on the PCI E Series device configured for NRSE mode Ground Referenced Signal Source Common Mode Noise and Ground Potential 1 O Connector E wy ACH lt 0 15 gt O4 oo o 34 soe O4 o ud e i 0 O4 Z o Input Multiplexers O AISENSE e AIGND Instrumentation Amplifier Measured Voltage Selected Channel in NRSE Configuration Figure 4 8 Single Ended Input Connections for Ground Referenced Signals Common Mode Signal Rejection Considerations Figures 4 5 and 4 8 show connections for signal sources that are already referenced to some ground point with respect to the PCI E Series device In these cases the PGIA can reject any voltage caused by ground potential differences between the signal source and the device In addition with differential input connections the PGIA can reject common mode noise pickup in the leads connecting the signal sources to the device The PGIA can reject common mode signals as long as Vi and V input signals are both within x11 V of AIGND Sy Note The PCI MIO 16XE 50 has the additional restriction that V V added to the gain times Vi Vi must be within 26 V of AIGND At gains of 10 and 100 this is roughly equivalent to restricting the two input voltages to within 8 V of AIGND PCI E Series User Manu
113. ing on the frequency and nature of the output signal The PCI MIO 16E 1 and NI PCI 6071E devices have built in reglitchers which can be software enabled on its AO channels Refer to the Analog Output section of Chapter 3 Hardware Overview for more information about reglitching Can I synchronize a one channel AI data acquisition with a one channel AO waveform generation on my PCI E Series device Yes One way to accomplish this is to use the waveform generation timing pulses to control the AI data acquisition To do this follow steps 1 through 4 in addition to the usual steps for data acquisition and waveform generation configuration 1 Enable the PFI5 line for output as follows e If you are using NI DAQ call Select Signal deviceNumber ND PFI 5 ND OUT UPDATE ND HIGH TO LOW e Ifyou are using LabVIEW invoke Route Signal VI with signal name set to PFI5 and signal source set to AO Update National Instruments Corporation C 3 PCI E Series User Manual Appendix C PCI E Series User Manual Common Questions 2 Setup DAQ timing so that the timing signal for A D conversion comes from PFI5 as follows e If you are using NI DAQ call Select Signal deviceNumber ND IN CONVERT ND PFI 5 ND HIGH TO LOW e If you are using LabVIEW invoke AI Clock Config VI with clock source code set to PFI pin high to low and clock source string set to 5 3 Initiate AI data acquisition which starts only when the AO waveform
114. ing signal source to a channel on the PCI E Series device configured for RSE mode Floating Signal Source O ACH O4 oo O So ia co Instrumentation Amplifier O us so Input Multiplexers ii o AISENSE Measured Voltage m Ol 1 O Connector O4 AIGND Selected Channel in RSE Configuration Figure 4 7 Single Ended Input Connections for Nonreferenced or Floating Signals Single Ended Connections for Grounded Signal Sources NRSE Configuration To measure a grounded signal source with a single ended configuration you must configure the PCI E Series device in the NRSE input configuration The signal is then connected to the positive input of the PCIE Series PGIA and the signal local ground reference is connected to the negative input of the PGIA The ground point of the signal should therefore be connected to the AISENSE pin Any potential difference between the PCI E Series ground and the signal ground appears as a common mode signal at both the positive and negative inputs of the PGIA and this difference is rejected by the amplifier If the input circuitry of a PCIE Series device were referenced to ground in this situation as in the RSE input configuration this difference in ground potentials would appear as an error in the measured voltage National Instruments Corporation 4 21 PCI E Series User Manual Chapter 4 Connecting Signals F
115. ironmental Operating temperature ee 0 to 55 C Storage temperature sss 20 to 70 C H iidity tete 10 to 90 RH noncondensing Maximum altitude ss 2 000 meters Pollution degree indoor use only 2 Safety The PCIE Series devices meet the requirements of the following standards for safety and electrical equipment for measurement control and laboratory use e EN 61010 1 1993 A2 1995 IEC 61010 1 1990 A2 1995 e UL 3101 1 1993 UL 3111 1 1994 UL 3121 1998 e CAN CSA c22 2 no 1010 1 1992 A2 1997 National Instruments Corporation A 31 PCI E Series User Manual Appendix A Specifications for PCI MIO 16XE 50 Electromagnetic Compatibility CE C Tick and FCC Part 15 Class A Compliant Electrical emissions eene EN 55011 Class A at 10 m FCC Part 15A above 1 GHz Electrical immunity sse Evaluated to EN 61326 1998 Table 1 3 Note For full EMC compliance you must operate this device with shielded cabling In addition all covers and filler panels must be installed Refer to the Declaration of Conformity DoC for this product for any additional regulatory compliance information To obtain the DoC for this product click Declaration of Conformity at ni com hardref nsf This Web site lists the DoCs by product family Select the appropriate product family followed by the product and a link to the DoC appears in Adobe Acrobat
116. ist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instr
117. istics A 16 input characteristics A 14 stability A 17 transfer characteristics A 15 analog trigger A 20 bus interface A 22 calibration A 21 digital I O A 19 digital trigger A 21 electromagnetic compatibility A 23 environmental A 22 physical A 22 power requirements A 22 RTSI A 21 safety A 23 timing I O A 20 voltage A 22 ni com O National Instruments Corporation PCI MIO 16XE 50 analog input amplifier characteristics A 25 dynamic characteristics A 26 input characteristics A 24 stability A 27 transfer characteristics A 25 analog output dynamic characteristics A 28 output characteristics A 27 stability A 29 transfer characteristics A 28 voltage output A 28 bus interface A 31 calibration A 30 digital I O A 29 digital trigger A 30 electromagnetic compatibility A 32 environmental A 31 physical A 31 power requirement A 31 RTSL A 30 safety A 31 timing I O A 29 voltage A 31 stability specifications analog input PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E A 6 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E A 17 PCI MIO 16XE 50 A 27 analog output PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E A 8 PCI MIO 16XE 10 and NI PCI 6031E A 19 PCI MIO 16XE 50 A 29 l 13 Index STARTSCAN signal input timing figure 4 32 output timing figure 4 33 timing connections 4 32 support technical D 1 system integration services D 1
118. lar 20V 80 dB 10V 86 dB 80 dB 5V 86 dB 2V 100 dB 1V 100 dB 200 mV 120 dB 100 mV 120 dB Dynamic Characteristics Bandwidth Range Small Signal 3 dB 5to20V 63 kHz 1to2V 57 kHz 100 to 200 mV 33 kHz Settling time for full scale step Accuracy Range 0 0015 1 LSB 0 0061 4 LSB 1 to 20V 50 us max 50 us max 200 mV bipolar 75 us max 50 us max 100 mV unipolar 75 us max 50 us max Accuracy values are valid for source impedances lt 1 kQ Refer to the Multichannel Scanning Considerations section of Chapter 3 Hardware Overview for more information PCI E Series User Manual A 26 ni com Analog Output Appendix A Specifications for PCI MIO 16XE 50 System noise including quantization noise Range Bipolar Unipolar 1to20V 1 0 1 0 100 to 200 mV 1 2 1 6 Crosstalk DC to 100 kHz Adjacent channels 85 dB All other channels 100 dB Stability Offset temperature coefficient Pre ain cit ita 1 uV C Post ott 12 uV C Gain temperature coefficient 5 ppm C Output Characteristics Number of channels 2 Resolution cccccccnnnnnnnnnonccncncccnnnnnonononenes 12 bits 1 in 4 096 Max update rate esses 20 kS s Type ODA Cortada Double buffered FIFO buffer size
119. lled a grounded measurement system resistive temperature detector a metallic probe that measures temperature based upon its coefficient of resistivity real time system integration bus the NI timing bus that connects DAQ boards directly by means of connectors on top of the boards for precise synchronization of functions G 8 ni com S s SCANCLK scan interval scan rate SCXI SE settling time signal conditioning SISOURCE SOURCE STARTSCAN system noise O National Instruments Corporation Glossary seconds samples samples per second used to express the rate at which a DAQ board samples an analog signal scan clock signal controls how often a scan in initialized the scan interval is regulated by STARTSCAN reciprocal of the scan interval Signal Conditioning eXtensions for Instrumentation the NI product line for conditioning low level signals within an external chassis near sensors so only high level signals are sent to DAQ boards in the noisy computer environment single ended a term used to describe an analog input that is measured with respect to a common ground the amount of time required for a voltage to reach its final value within specified limits the manipulation of signals to prepare them for digitizing SI counter clock signal source signal start scan signal a measure of the amount of noise seen by an analog circuit or an ADC when the analog inputs are grounded G 9 PCI E Seri
120. log trigger Therefore it is susceptible to crosstalk from adjacent pins which can result in false triggering when the pin is left unconnected To avoid false triggering make sure this pin is connected to a low impedance signal source less than 1 k source impedance if you plan to enable this input using software Analog Input Channels PFIO TRIG1 PGIA ADC Mux Analog Trigger Circuit DAQ STC National Instruments Corporation Figure 3 6 Analog Trigger Block Diagram There are five analog triggering modes available as shown in Figures 3 7 through 3 11 You can set lowValue and high Value independently in software In below low level analog triggering mode the trigger is generated when the signal value is less than lowValue HighValue is unused lowValue Trigger Figure 3 7 Below Low Level Analog Triggering Mode PCI E Series User Manual Chapter 3 Hardware Overview In above high level analog triggering mode the trigger is generated when the signal value is greater than highValue LowValue is unused highValue Trigger Figure 3 8 Above High Level Analog Triggering Mode In inside region analog triggering mode the trigger is generated when the signal value is between the lowValue and the highValue highValue od ee es Lo melee lowValue ___
121. lt 0 8 7 15 gt lt 16 23 gt ACH lt 16 24 23 31 gt lt 32 39 gt ACH lt 32 40 39 47 gt lt 48 55 gt ACH lt 48 56 55 63 gt How can I use STARTSCAN and CONVERT on my PCI E Series device to sample AI channel s PCIE Series devices employ both the STARTSCAN and CONVERT signals to perform interval sampling The STARTSCAN signal of the DAQ STC controls the scan interval 1 scan interval scan rate shown in Figure C 2 The CONVERT signal controls the interchannel delay 1 interchannel delay sampling rate This method allows multiple channels to be sampled relatively quickly in relation to the overall scan rate providing a pseudo simultaneous effect with a fixed delay between channels National Instruments Corporation C 5 PCI E Series User Manual Appendix C Common Questions Channel 0 Channel 1 MP Interchannel Delay Scan Interval gt Figure C 2 Comparing Interchannel Delay and Scan Interval Timing and Digital 1 0 What types of triggering can be hardware implemented on my PCIE Series device Digital triggering is hardware supported on every PCI E Series device In addition the PCI MIO 16E 1 PCI MIO 16E 4 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E NI PCI 6033E and NI PCI 6071E support analog triggering in hardware What added functionality does the DAQ STC make possible in contrast to the Am9513 The DAQ STC incorporates much more th
122. n a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense FOR HOME OR OFFICE USE Canadian Department of Communications This Class A digital apparatus meets all requirements of the Canadian Interference Causing Equipment Regulations Cet appareil num rique de la classe A respecte toutes les exigences du R glement sur le mat riel brouilleur du Canada Class B Federal Communications Commission This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures Reorient or relocate the receiving antenna Increase the separation between the equipment and receiver Connect the equipment into an outlet on a circuit different from that to which t
123. n parallel with 100 pF Powered off ssssssssss 820 Q min Overload e eoe 820 Q min Input bias current sses nA Input offset current sesssss 2 nA CMRR DC to 60 Hz CMRR Device Range Bipolar Unipolar PCI MIO 16XE 10 20V 92 dB NI PCI 6031E 10 V 97 dB 92 dB NI PCI 6032E sv cm 97 dB NI PCI 6033E 4V 101 dB m 2V 104 dB 101 dB 1V 105 dB 104 dB 100 mV 105 dB 105 dB to 500 mV PCI E Series User Manual Dynamic Characteristics Bandwidth 3 dB All gains ies 255 kHz A 16 ni com Appendix A Specifications for PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI G033E Settling time for full scale step DC to all gains and ranges Accuracy 0 00076 0 0015 0 0061 Device 0 5 LSB 1 LSB 4 LSB PCI MIO 16XE 10 40 us max 20 us max 10 us max NI PCI 6032E NI PCI 6031E 50 us max 25 us max 10 us max NI PCI 6033E Accuracy values valid for source impedances 1 kQ Refer to the Multichannel Scanning Considerations section of Chapter 3 Hardware Overview for more information System noise including quantization noise Device Range Bipolar Unipolar PCI MIO 16XE 10 2 to 20 V 0 6 0 8 NI PCI 6031E 1V 0 7 0 8 NI PCI 6032E 400 to 500 mV 1 1 1 1 NI PCI 6033E 200 mV 2 0 2 0 100 mV 3 8 Crosstalk DC to 100 kHz Adjacent channels 75 dB All other channels
124. nal 1 5 example code D 1 EXTREF signal analog output signal connections 4 23 description table 4 4 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 7 EXTSTROBE signal description table 4 5 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 7 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E table 4 9 O National Instruments Corporation 1 5 Index PCI MIO 16XE 50 4 11 timing connections 4 37 F field wiring considerations 4 46 floating signal sources description 4 14 differential connections 4 18 recommended configuration figure 4 15 single ended connections RSE configuration 4 21 FREQ_OUT signal description table 4 6 general purpose timing considerations 4 46 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 8 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and N PCI 6033E table 4 10 PCI MIO 16XE 50 table 4 11 frequently asked questions D 1 See also questions and answers G general purpose timing signal connections FREQ OUT signal 4 46 GPCTRO GATE signal 4 41 GPCTRO OUT signal 4 42 GPCTRO SOURCE signal 4 40 GPCTRO UP DOWN signal 4 42 GPCTR1_GATE signal 4 43 GPCTRI OUT signal 4 44 GPCTRI SOURCE signal 4 43 GPCTRI UP DOWN signal 4 44 questions about C 7 glitches 3 12 C 3 GPCTRO GATE signal 4 41 PCI E Series User Manual Index GPCTRO OUT signal description table 4 6 general purpose timing connections 4 42 PCI MIO 16E 1
125. nd NI PCI 6071E A 11 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E A 22 PCI MIO 16XE 50 A 31 C cables See also I O connectors custom cabling 1 5 field wiring considerations 4 46 optional equipment 1 5 calibration adjusting for gain error 5 3 external calibration 5 2 loading calibration constants 5 1 mixing unipolar and bipolar channels note 3 7 self calibration 5 2 charge injection 3 10 commonly asked questions See questions and answers common mode signal rejection 4 22 configuration See also input configurations board configuration 2 2 questions about C 2 connectors See I O connectors O National Instruments Corporation 1 3 Index contacting National Instruments D 1 conventions used in the manual xi CONVERT signal input timing figure 4 34 multiplexer for controlling 3 17 output timing figure 4 34 signal routing 3 16 timing connections 4 34 counter timer applications C 7 customer education D 1 professional services D 1 technical support D 1 D DACOOUT signal analog output signal connections 4 23 description table 4 4 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 7 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E table 4 9 PCI MIO 16XE 50 table 4 10 DACIOUT signal analog output signal connections 4 23 description table 4 4 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E table 4 7 PCI MIO 16XE 10 NI PCI 6031E NI PCI
126. nd connect the negative side of the signal to AIGND as well as to the negative input of the PGIA without any resistors at all This connection works well for DC coupled sources with low source impedance less than 100 2 However for larger source impedances this connection leaves the differential signal path significantly out of balance Noise that couples electrostatically onto the positive line does not couple onto the negative line because it is connected to ground Hence this noise appears as a differential mode signal instead of a common mode signal and the PGIA does not reject it In this case instead of directly connecting the negative line to AIGND connect it to AIGND through a resistor that is about 100 times the equivalent source impedance The resistor puts the signal path nearly in balance so that about the same amount of noise couples onto both connections yielding better rejection of electrostatically coupled noise Also this configuration does not load down the source other than the very high input impedance of the PGIA You can fully balance the signal path by connecting another resistor of the same value between the positive input and AIGND as shown in Figure 4 6 This fully balanced configuration offers slightly better noise rejection but has the disadvantage of loading the source down with the series combination sum of the two resistors If for example the source impedance is 2 kQ and each of the two resistors
127. nd driving external devices such as the LED shown in Figure 4 10 National Instruments Corporation 4 25 PCI E Series User Manual Chapter 4 Connecting Signals Power Connections Two pins on the 1 0 connector supply 5 V from the computer power supply using a self resetting fuse The fuse resets automatically within a few seconds after the overcurrent condition is removed These pins are referenced to DGND and can be used to power external digital circuitry UN Caution Under no circumstances should you connect these 5 V power pins directly to analog or digital ground or to any other voltage source on the PCI E Series device or any other device Doing so can damage the PCI E Series device and the computer NI is not liable for damage resulting from such a connection Timing Connections J Caution Exceeding the maximum input voltage ratings which are listed in I O signal summary tables in this chapter can damage the PCI E Series device and the computer NI is not liable for any damage resulting from such signal connections All external control over the timing of the PCI E Series device is routed through the 10 programmable function inputs labeled PFIO through PFI9 These signals are explained in detail in the Programmable Function Input Connections section These PFIs are bidirectional as outputs they are not programmable and reflect the state of many DAQ waveform generation and general purpose timing signals There are five ot
128. ne of the PFIs Output As an output this is the STARTSCAN signal This pin pulses once at the start of each AI scan in the interval scan A low to high transition indicates the start of the scan PFIS GPCTRO SOURCE DGND Input PFI8 Counter 0 Source As an input this is one of the PFIs As an output this is the GPCTRO SOURCE signal Output This signal reflects the actual source connected to the general purpose counter 0 PFI9 GPCTRO GATE DGND Input PFI9 Counter 0 Gate As an input this is one of the PFIs Output As an output this is the GPCTRO_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 0 GPCTRO OUT DGND Output Counter 0 Output This output is from the general purpose counter 0 output FREQ_OUT DGND Output Frequency Output This output is from the frequency generator output PCI E Series User Manual 4 6 ni com Chapter 4 Connecting Signals 1 0 Signal Summary PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E Signal Impedance Protection Sink Rise Type and Input Volts Source mA Time Signal Name Direction Output On Off mA at V at V ns Bias ACH 0 63 AI 100 GQ 25 15 200 pA in parallel with 100 pF AISENSE AISENSE2 Al 100 GQ 25 15 200 pA in parallel with 100 pF AIGND AO DACOOUT AO 0 10 Short circuit 5at 10 5at 10 20
129. nononons DMA modes iii PME Specifications for PCI MIO 16XE 50 DMA interrupts programmed I O Scatter gather single transfer demand transfer Configuration memory size 512 words Transfer Characteristics Relative accuracy coocococcconnonncnnonnnonncnnninnos x 0 5 LSB typ 1 LSB max DNE ethernet 0 5 LSB typ 1 LSB max No missing codes seesees Offset error Pregain error after calibration Pregain error before calibration Postgain error after calibration Postgain error before calibration 16 bits guaranteed 3 uV max xl mV max 76 uV max 4 mV max Gain error relative to calibration reference After calibration gain 1 Before calibration With gain error adjusted to O at gain 1 Gam 2 gt 10 eet Gams 100 wise ee Amplifier Characteristics Input impedance Normal powered on Powered off Overlo d E Input bias current eese Input offset current sess National Instruments Corporation 30 5 ppm of reading max 2 250 ppm of reading max 100 ppm of reading 2 250 ppm of reading 7 GQ in parallel with 100 pF 820 Q min 820 Q min 10 nA 20 nA PCI E Series User Manual Specifications for PCI MIO 16XE 50 Appendix A CMRR DC to 60 Hz CMRR Range Bipolar Unipo
130. ns This uniform glitch energy appears as a multiple of the update rate in the frequency spectrum Notice that this reglitch circuit does not eliminate the glitches it only makes them more uniform in size Reglitching is normally disabled at startup and the software can independently enable each channel PCI E Series User Manual PCI MIO 16E 1 PCI MIO 16E 4 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E NI PCI 6033E and NI PCI 6071E In addition to supporting internal software triggering and external digital triggering to initiate a data acquisition sequence these devices also support analog triggering You can configure the analog trigger circuitry to accept either a direct analog input from the PFIO TRIGI pin on the I O connector or a postgain signal from the output of the PGIA as shown in Figure 3 6 The trigger level range for the direct analog channel is 10 V in 78 mV steps for the PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E and 10 V in 4 9 mV steps for the PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E The range for the post PGIA trigger selection is simply the full scale range of the selected channel and the resolution is that range divided by 256 for the PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E and divided by 4 096 for the PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E 3 12 ni com Chapter 3 Hardware Overview ER Note The PFIO TRIGI pin is an analog input when configured as an ana
131. nterface jo Bus Analog Output RTSI Bus Analog q Digital 1 O 8 utput Control Interface Digital d Timing Control Interface Analog Input Figure 3 4 PCI MIO 16XE 50 Block Diagram Input Mode PCI E Series User Manual The AI section of each PCI E Series device is software configurable You can select different AI configurations through application software designed to control the PCI E Series devices The following sections describe in detail each of the AI categories The PCI E Series devices have three different input modes nonreferenced single ended NRSE input referenced single ended RSE input and differential DIFF input The single ended input configurations provide up to 16 channels 64 channels on the NI PCI 6031E NI PCI 6033E and NI PCI 6071E The DIFF input configuration provides up to eight channels 32 channels on the NI PCI 6031E NI PCI 6033E and the NI PCI 6071E Input modes are programmed on a per channel basis for ni com Chapter 3 Hardware Overview multimode scanning For example you can configure the circuitry to scan 12 channels four differentially configured channels and eight single ended channels Table 3 1 describes the three input configurations Table 3 1 Available Input Configurations for the PCI E Series Configuration Description DIFF A channel configured in DIFF mode use
132. ntrol Interface Qum d Interface Digital 1 0 8 AO Control Data 16 Calibration DACs 32 for the PCI 6071E Figure 3 1 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E Block Diagram National Instruments Corporation 3 1 PCI E Series User Manual Chapter 3 Hardware Overview Figure 3 2 shows a block diagram for the PCI MIO 16XE 10 and the NI PCI 6031E 16 Bit Sampling AID Converter p Mux Mode Selection gt Switches Configuration Memory Trigger Level Analog Data 16 Address Data o6 DACs Trigger B gt Od O Trigger Circuitry T 2 o 2 Pi gt Tri 1 Analog Input E 5 lt PFVTrigger rigger riming Control Analog TEEPROM DMA e Gl l Tome o Counter Oo Timing Timing VO DAQ STC a R PY EE nm m 1 Analog Output RTSI Bus Digital VO 8 Digital VO Timing Control Interface AO Control ES Data 16 Cee ey oi 1 82 for the PCI 6031E Figure 3 2 PCI MIO 16XE 10 and NI PCI 6031E Block Diagram PCI E Series User Manual 3 2 ni com Chapter 3 Hardware Overview Figure 3 3 shows a block diagram for the NI PCI 6032E and the NI PCI 6033E Calibration Generic 16
133. o output a specific internal timing signal For example if you need the CONVERT signal as an output on the I O connector software can turn on the output driver for the PFI2 CONVERT pin Be careful not to drive a PFI signal externally when it is configured as an output National Instruments Corporation 4 27 PCI E Series User Manual Chapter 4 Connecting Signals DAQ Timing Conne PCI E Series User Manual As an input each PFI can be configured for edge or level detection and for polarity selection as well You can use the polarity selection for any of the 13 timing signals but the edge or level detection depends on the particular timing signal being controlled The detection requirements for each timing signal are listed within the section that discusses that individual signal In edge detection mode the minimum pulse width required is 10 ns This applies for both rising edge and falling edge polarity settings There is no maximum pulse width requirement in edge detect mode In level detection mode there are no minimum or maximum pulse width requirements imposed by the PFIs themselves but there may be limits imposed by the particular timing signal being controlled These requirements are listed later in this chapter ctions The DAQ timing signals are TRIG1 TRIG2 STARTSCAN CONVERT AIGATE SISOURCE SCANCLK and EXTSTROBE Posttriggered data acquisition allows you to view only data that is acquired after a trigger
134. oftware can be very time consuming and inefficient and it is not recommended for most users Even if you are an experienced register level programmer using NI DAQ or application software to program the National Instruments DAQ hardware is easier than and as flexible as register level programming and can save weeks of development time If you are doing register level programming refer to the PCI E Series Register Level Programmer Manual for detailed register information 1 4 ni com Chapter 1 Introduction Optional Equipment NI offers a variety of products to use with the PCI E Series device including cables connector blocks and other accessories as follows Cables and cable assemblies shielded and ribbon Connector blocks shielded and unshielded 50 and 68 pin screw terminals Real Time System Integration RTSI bus cables SCXI modules and accessories for isolating amplifying exciting and multiplexing signals for relays and analog output with SCXI you can condition and acquire up to 3 072 channels Low channel count signal conditioning modules devices and accessories including conditioning for strain gauges and RTDs simultaneous sample and hold and relays For more information about these products refer to ni com catalog Custom Cabling NI offers cables and accessories for you to prototype your application or to use if you frequently change device interconnections If you want to develop your own cabl
135. omputer National Instruments Corporation 2 1 PCI E Series User Manual Chapter 2 Installing and Configuring the Device 3 Remove the expansion slot cover on the back panel of the computer 4 Ground yourself using a grounding strap or by holding a grounded object Follow the ESD protection precautions described in the Unpacking section of Chapter 1 Introduction 5 Insert the PCI E Series device into a PCI slot Gently rock the device to ease it into place It may be a tight fit but do not force the device into place 6 Ifrequired screw the mounting bracket of the PCI E Series device to the back panel rail of the computer 7 Visually verify the installation Make sure the device is not touching other devices or components and is fully inserted in the slot Replace the cover 9 Plug in and power on the computer The PCI E Series device is now installed Configuring the Device Due to the NI standard architecture for data acquisition and the PCI bus specification the PCI E Series devices are completely software configurable You must perform two types of configuration on the PCIE Series devices bus related and data acquisition related configuration The PCI E Series devices are fully compatible with the industry standard PCI Local Bus Specification Revision 2 2 This allows the PCI system to automatically perform all bus related configurations and requires no user interaction Bus related configuration includes
136. on Such Windings of Distribution as Wall Sockets Isolation Panel Transformers Category III Category II Category I PCI E Series User Manual ni com Installing and Configuring the Device This chapter explains how to install and configure the PCI E Series device Installing the Software Complete the following steps to install the software before installing the PCIE Series device Install the application development environment ADE such as LabVIEW Measurement Studio or VI Logger according to the instructions on the CD and the release notes 2 Install NI DAQ according to the instructions on the CD and the DAQ Quick Start Guide included with the device 3 Note Itis important to install NI DAQ before installing the PCI E Series device to ensure that the device is properly detected Installing the Hardware You can install a PCI E Series device in any available expansion slot in the computer However to achieve best noise performance leave as much room as possible between the PCI E Series device and other devices and hardware The following are general installation instructions Refer to the computer or chassis user manual or technical reference manual for specific instructions and warnings about installing new devices hy Note Follow the guidelines in the computer documentation for installing plug in hardware 1 Power off and unplug the computer 2 Remove the top cover of the c
137. on A 9 Specifications for PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E Input high impedance Programmed I O 50 kwords s system dependent 1 to 10 kwords s typical 2 up down counter timers 1 frequency scaler 24 bits 4 bits TTL CMOS 20 MHz 100 kHz 10 MHz 100 kHz 0 01 20 MHz 10 ns edge detect mode 10 ns edge detect mode DMA interrupts programmed I O Scatter gather PCI E Series User Manual Appendix A Triggers PCI E Series User Manual Specifications for PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E Analog Trigger Source PCI MIO 16E 1 PCI MIO 16E 4 sess ACH lt 0 15 gt external trigger PFIO TRIG1 NI PELGOTLE ciertos ACH lt 0 63 gt external trigger PFIO TRIG1 Levels het bete o x full scale internal 10 V external Nn Positive or negative Resolutio insire nianag HN Stereo ete eee tete Bandwidth 3 dB PCI MIO 16E 1 NI PCI 6071E PCI MIO 16E 4 tes External input PFIO TRIGI Impedance esee Coupling tance retient Protection eee Digital Trigger Compatibility eese Responses ehe etes Pulse width iet ers software selectable 8 bits 1 in 256 Programmable 2 MHz internal 7 MHz external 650 kHz internal 3 0 MHz external 10 kQ DC 0 5 to Vcc 0 5 V when configured as a digital signal 35 V when configured as an analog trigger signal o
138. on the NI PCI 6031E NI PCI 6033E and NI PCI 6071E Refer to Appendix B Optional Cable Connector Descriptions for the pin assignments for the 50 pin connector A signal description follows the connector pinouts UN Caution Connections that exceed any of the maximum ratings of input or output signals on the PCI E Series devices can damage the PCI E Series device and the computer Maximum input ratings for each signal are given in the Protection column of the I O signal summary tables in this chapter NI is not liable for any damage resulting from such signal connections National Instruments Corporation 4 1 PCI E Series User Manual Chapter 4 Connecting Signals ACH8 34 68 ACHO ACH1 33 67 AIGND AIGND 32 66 ACH9 ACH10 31 65 ACH2 ACH3 30 64 AIGND AIGND 29 63 ACH11 ACH4 28 62 AISENSE AIGND 27 61 ACH12 ACH13 26 60 ACH5 ACH6 25 59 AIGND AIGND 24 58 ACH14 ACH15 23 57 ACH7 DACOOUT 22 56 AIGND DAC1OUT 21 55 AOGND EXTREF 20 54 AOGND DIO4 19 53 DGND DGND 18 52 DIOO DIO1 17 51 DIO5 DIO6 16 50 DGND DGND 15 49 DIO2 5V 14 48 DIO7 DGND 13 47 DIO3 DGND 12 46 SCANCLK PFIO TRIG1 11 45 EXTSTROBE PFH TRIG2 10 44 DGND DGND 9 43 PFI2 CONVERT 45V 8 42 PFIS GPCTR1 SOURCE DGND 7 41 PFI4 GPCTR1_GATE PFI5 UPDATE 6 40 GPCTR1 OUT PFI6 WFTRIG 5 39 DGND DGND
139. one National Instruments Corporation 4 47 PCI E Series User Manual Calibration This chapter discusses the calibration procedures for the PCI E Series device NI DAQ includes calibration functions for performing all of the steps in the calibration process Calibration refers to the process of minimizing measurement and output voltage errors by making small circuit adjustments On the PCI E Series devices these adjustments take the form of writing values to onboard calibration DACs CalDACs Some form of device calibration is required for all but the most forgiving applications If you do not calibrate the device the signals and measurements could have very large offset gain and linearity errors Three levels of calibration are available to you and described in this chapter The first level is the fastest easiest and least accurate whereas the last level is the slowest most difficult and most accurate Loading Calibration Constants The PCI E Series device is factory calibrated before shipment at approximately 25 C to the levels given in Appendix A Specifications The associated calibration constants the values that were written to the CalDACs to achieve calibration in the factory are stored in the onboard nonvolatile memory EEPROM Because the CalDACs have no memory capability they do not retain calibration information when the device is unpowered Loading calibration constants refers to the process of loadin
140. output low relative accuracy amount of time that passes between sampling consecutive channels the interchannel delay must be short enough to allow sampling of all the channels in the channel list within the scan interval The greater the interchannel delay the more time the PGIA is allowed to settle before the next channel is sampled The interchannel delay is regulated by CONVERT least significant bit meter megabytes of memory multifunction I O MXI Interfaces to Everything G 6 ni com MSB mux NC NI DAQ noise NRSE OUT PCI PFI PFIO TRIGI PFI1 TRIG2 PFI2 CONVERT Glossary most significant bit multiplexer a switching device with multiple inputs that sequentially connects each of its inputs to its output typically at high speeds in order to measure several signals with a single analog input channel normally closed or not connected NI driver software for DAQ hardware an undesirable electrical signal noise comes from external sources such as the AC power line motors generators transformers fluorescent lights CRT displays computers electrical storms welders radio transmitters and internal sources such as semiconductors resistors and capacitors Noise corrupts signals you are trying to send or receive nonreferenced single ended mode all measurements are made with respect to a common NRSE measurement system reference but the voltage at this reference can vary with respect to t
141. p 50 ns minimum ty 23 ns minimum Figure 4 29 UISOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 kHz internal timebase normally generates the UISOURCE signal unless you select some external source General Purpose Timing Signal Connections PCI E Series User Manual The general purpose timing signals are GPCTRO SOURCE GPCTRO GATE GPCTRO OUT GPCTRO UP DOWN GPCTRI SOURCE GPCTR1_GATE GPCTR1_OUT GPCTRI UP DOWN and FREQ OUT GPCTRO SOURCE Signal Any PFI pin can externally input the GPCTRO SOURCE signal which is available as an output on the PFIS GPCTRO SOURCE pin As an input the GPCTRO SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTRO SOURCE and configure the polarity selection for either rising or falling edge As an output the GPCTRO SOURCE signal reflects the actual clock connected to general purpose counter 0 even if another PFI is externally inputting the source clock This output is set to high impedance at startup 4 40 ni com Chapter 4 Connecting Signals Figure 4 30 shows the timing requirements for the GPCTRO SOURCE signal ly it ty e tp 50 ns minimum ty 23 ns minimum Figure 4 30 GPCTRO_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pul
142. put Not available on NI PCI 6032E and NI PCI 6033E pd pull down pu pull up Note The tolerance on the 50 kQ pull up and pull down resistors is very large Actual value may range between 17 kQ and 1 0 Signal Summary PCI MIO 16XE 50 Signal Impedance Protection Sink Rise Type and Input Volts Source mA Time Signal Name Direction Output On Off mA at V at V ns Bias ACH lt 0 15 gt Al 20 GQ in 25 15 3 nA parallel with 100 pF AISENSE Al 20 GQ in 25 15 3 nA parallel with 100 pF AIGND AO DACOOUT AO 0 1 Q Short circuit 5 at 10 5at 10 2 V us to ground DACIOUT AO 0 1 Q Short circuit 5 at 10 5at 10 2 V us to ground AOGND AO DGND DO VCC DO 0 1 Q Short circuit 1 A to ground DIO lt 0 7 gt DIO Voc 0 5 13 at 24 at 0 4 1 1 50 kQ pu Vcc 0 4 SCANCLK DO 3 5 at 5at0 4 1 5 50 kQ pu Vcc 0 4 PCI E Series User Manual 4 10 ni com Chapter 4 Connecting Signals Signal Impedance Protection Sink Rise Type and Input Volts Source mA Time Signal Name Direction Output On Off mA at V at V ns Bias EXTSTROBE DO 3 5 at 5at0 4 1 5 50 kQ pu Vcc 0 4 PFIO TRIGI 1 DIO Vcc 0 5 3 5 at 5at0 4 1 5 50 KQ pu Vcc 0 4 PFI1 TRIG2 DIO Vcc 0 5 3 5 at 5at0 4 1 5 50 KQ pu Vcc
143. r figure B 4 50 pin extended analog input connector figure B 5 68 pin E Series connector figure B 2 68 pin extended analog input connector figure B 3 NI PCI 6071E NI PCI 6031E and NI PCI 6033E figure 4 3 PCI MIO 16E 1 PCI MIO 16E 4 PCI MIO 16XE 50 PCI MIO 16XE 10 and NI PCI 6032E figure 4 2 PCI E Series User Manual Index polarity selection analog input mixing bipolar and unipolar channels note 3 7 PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E 3 5 PCI MIO 16XE 10 PCI MIO 16XE 50 NI PCI 6031E NI PCI 6032E and NI PCI 6033E 3 6 selection considerations 3 8 analog output PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E 3 11 PCI MIO 16XE 10 and NI PCI 6031E 3 11 posttriggered data acquisition 4 28 power connections 4 26 power requirement specifications PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E A 11 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E A 22 PCI MIO 16XE 50 A 31 pretriggered data acquisition 4 28 professional services D 1 programmable function inputs PFIs See PFIs programmable function inputs programmable gain instrumentation amplifier See PGIA programmable gain instrumentation amplifier programming examples D 1 Q questions and answers analog input and output C 3 general information C 1 installation and configuration C 2 timing and digital I O C 6 PCI E Series User Manual 1 10 R reference selection analog output 3 11 refer
144. r disabled 35 V powered off Rising or falling edge 10 ns min ni com Appendix A Specifications for PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E RTSI Trigger mess ret 7 Calibration Recommended warm up time 15 min Calibration interval 1 year External calibration reference gt 6 and 10 V Onboard calibration reference Levels vue 5 000 V x3 5 mV over full operating temperature actual value stored in EEPROM Temperature coefficient 5 ppm C max Long term stability 15 ppm 1 000 h Bus Interface TY PG uiii eee ete aes Master slave Power Requirement 5 VDC 45 PCI MIO 16E 1 NI PCI 6071E 1 1 A PCI MIO 16E A esee 1 0A Power available at I O connector 4 65 to 5 25 VDCat 1 A Physical Dimensions not including connectors 17 5 by 10 6 cm 6 9 by 4 2 in I O connector PCI MIO 16E 1 PCI MIO 16E 4 eese 68 pin male SCSI II type NIPGEO0TIE neus 100 pin female 0 05 D type National Instruments Corporation A 11 PCI E Series User Manual Appendix A Specifications for PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E Maximum Working Voltage Maximum working voltage refers to the signal voltage plus the common mode voltage Channel to earth eese 42 V Installation Category II Channel to channel
145. r of channels Resolution Counter timers eeeeeeee Frequency scaler Compatibility eese Base clocks available Counter timers eeeeee Frequency scaler Base clock accuracy Max source frequency Min source pulse duration Min gate pulse duration Data transfers ccccccccncninnnnnanananannnonos DMA modes cccccccccnccnonininanananananononononos Analog Trigger Source PCI MIO 16XE 10 NIPCI 6032E m NI PCI 6031E NI PCI 6033E PS oe A 20 Specifications for PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E and NI PCI 6033E 2 up down counter timers frequency scaler 24 bits 4 bits TTL CMOS 20 MEZ 100 kHz 10 MAz 100 kHz 0 01 20 MHz 10 ns edge detect mode 10 ns edge detect mode DMA interrupts programmed I O Scatter gather ACH lt 0 15 gt PFIO TRIG1 ACH lt 0 63 gt PFIO TRIGI fullscale internal 10 V external Positive or negative software selectable 12 bits 1 in 4 096 ni com Appendix A Hysteresis Bandwidth 3 dB External input PFIO TRIG1 Impedance Coupling Protec taa ACCUIACY ns geh p erige Digital Trigger Compatibility Response Pulse width RTSI Trigger lines Calibration Recommended warm up tim
146. rential Connection Considerations DIFF Input Configuration 4 16 Differential Connections for Ground Referenced Signal SOUECeS epo ED Ree e aen m iet erue 4 17 Differential Connections for Nonreferenced or Floating S1gnal SOUL Ces us rette ee ei ee te e 4 18 Single Ended Connection Considerations e 4 20 Single Ended Connections for Floating Signal Sources RSE Configuration erect eene ehe nnne thee nne tnnt nnn 4 21 Single Ended Connections for Grounded Signal Sources NRSE Configuration scenen ai nennen nnn 4 21 Common Mode Signal Rejection Considerations ees 4 22 Analog Output Signal Connections eese enne 4 23 Digital I O Signal Connections esent retener 4 24 Power Connections iste epe qu e EE HO en eats 4 26 Timing Connections 3 ob ter io 4 26 Programmable Function Input Connections oooconccocnnonconnnoncononancnnnonccnncnnnonnos 4 27 DAQ Timing Connections eer ont e et rp tente tese tdg 4 28 TRIGISiIgnal 522 4 29 TRIG2 SIgnal verter E rr EO Ure te tee 4 30 STARTSCAN Signal wastes tal ae a eese 4 32 CONVERT Signal rri he epe 4 34 AIGATE Signal etn one qa eee RE 4 35 PCI E Series User Manual viii ni com Contents SISOURCE Sigla aid 4 35 SCANGCLK Sipnal ihe gaidetu teles 4 36 EXTSTROBE Signal 2 a io iii 4 37 Waveform Generation Timing Connections eee 4 37 WETRIG Signal ie ee
147. round potential difference between the signal source and the PCI E Series device ground shown as Vem in Figure 4 5 National Instruments Corporation 4 17 PCI E Series User Manual Chapter 4 Connecting Signals Differential Connections for Nonreferenced or Floating Signal Sources Figure 4 6 shows how to connect a floating signal source to a channel on the PCI E Series device configured in DIFF input mode l O Connector Instrumentation Amplifier PGIA T Measured ACH oO Bias Resistors oe see text Ground P 6 o e m A e Source Z oo ACH O70 co Bias Current So Return o Paths E So Input Multiplexers AISENSE m Voltage Selected Channel in DIFF Configuration Figure 4 6 Differential Input Connections for Nonreferenced Signals Figure 4 6 shows two bias resistors connected in parallel with the signal leads of a floating signal source If you do not use the resistors and the source is truly floating the source is not likely to remain within the common mode signal range of the PGIA and the PGIA saturates causing erroneous readings You must reference the source to AIGND The easiest way is simply to connect the positive side of the signal to the positive input PCI E Series User Manual 4 18 ni com Chapter 4 Connecting Signals of the PGIA a
148. rsion in the scanning modes when enabled The low to high edge indicates when the input signal can be removed from the input or switched to another signal EXTSTROBE DGND Output External Strobe This output can be toggled under software control to latch signals or trigger events on external devices PFIO TRIGI DGND Input Output PFIO Trigger 1 As an input this is either one of the Programmable Function Inputs PFIs or the source for the hardware analog trigger PFI signals are explained in the Timing Connections section later in this chapter The hardware analog trigger is explained in the Analog Trigger section of Chapter 3 Hardware Overview Analog trigger is available only on the PCI MIO 16E 1 PCI MIO 16E 4 PCI MIO 16XE 10 NI PCI 6031E NI PCI 6032E NI PCI 6033E and the NI PCI 6071E As an output this is the TRIGI signal In posttrigger data acquisition sequences a low to high transition indicates the initiation of the acquisition sequence In pretrigger applications a low to high transition indicates the initiation of the pretrigger conversions PFI1 TRIG2 DGND Input Output PFI1 Trigger 2 As an input this is one of the PFIs As an output this is the TRIG2 signal In pretrigger applications a low to high transition indicates the initiation of the posttrigger conversions TRIG2 is not used in posttrigger applications PFI2 CONVERT DGND Input Output PFI2 Convert
149. s two analog channel input lines One line connects to the positive input of the device programmable gain instrumentation amplifier PGIA and the other connects to the negative input of the PGIA RSE A channel configured in RSE mode uses one analog channel input line which connects to the positive input of the PGIA The negative input of the PGIA is internally tied to AI ground AIGND NRSE A channel configured in NRSE mode uses one analog channel input line which connects to the positive input of the PGIA The negative input of the PGIA connects to the AI sense AISENSE input For more information about the three types of input configuration refer to the Analog Input Signal Connections section of Chapter 4 Connecting Signals which contains diagrams showing the signal paths for the three configurations Input Polarity and Input Range PCI MIO 16E 1 PCI MIO 16E 4 and NI PCI 6071E These devices have two input polarities unipolar and bipolar Unipolar input means that the input voltage range is between 0 and V where V ef IS a positive reference voltage Bipolar input means that the input voltage range is between V ef 2 and V ef 2 So these devices have a unipolar input range of 10 V 0 to 10 V and a bipolar input range of 10 V x5 V You can program polarity and range settings on a per channel basis so that you can configure each input channel uniquely The software programmable gain on these
150. se width of 23 ns high or low There is no minimum frequency limitation The 20 MHz or 100 KHz timebase normally generates the GPCTRO SOURCE signal unless you select some external source GPCTRO GATE Signal Any PFI pin can externally input the GPCTRO GATE signal which is available as an output on the PFIJ GPCTRO GATE pin As an input the GPCTRO GATE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTRO GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform actions such as starting and stopping the counter generating interrupts saving the counter contents and so on As an output the GPCTRO GATE signal reflects the actual gate signal connected to general purpose counter 0 even if the gate is being externally generated by another PFI This output is set to high impedance at startup National Instruments Corporation 4 41 PCI E Series User Manual Chapter 4 Connecting Signals Figure 4 31 shows the timing requirements for the GPCTRO GATE signal Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 31 GPCTRO_GATE Signal Timing in Edge Detection Mode GPCTRO_OUT Signal This signal is available only as an output on the GPCTRO_OUT pin The GPCTRO_OUT signal reflects the terminal count TC of general purpose counter 0 You have two
151. software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to high impedance at startup Figure 4 32 shows the timing of the GPCTRO_OUT signal GPCTRO_SOURCE GPCTRO_OUT Pulse on TC GPCTRO_OUT Toggle Output on TC PCI E Series User Manual Figure 4 32 GPCTRO OUT Signal Timing GPCTRO UP DOWN Signal This signal can be externally input on the DIO6 pin and is not available as an output on the I O connector The general purpose counter 0 counts down when this pin is at a logic low and counts up when it is at a logic high You can disable this input so that software can control the up down functionality and leave the DIO6 pin free for general use 4 42 ni com Chapter 4 Connecting Signals GPCTR1 SOURCE Signal Any PFI pin can externally input the GPCTR1 SOURCE signal which is available as an output on the PFI3 JGPCTR1 SOURCE pin As an input the GPCTR1 SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTRI SOURCE and configure the polarity selection for either rising or falling edge As an output the GPCTR1 SOURCE monitors the actual clock connected to general purpose counter 1 even if the source clock is being externally generated by another PFI This output is set to high impedance at startup Figure 4 33 shows the timing req
152. t of visible noise But averaging about 50 such acquisitions as shown in Figure 3 5d eliminates both the added noise and the effects of quantization Dither has the effect of forcing quantization noise to become a zero mean random variable rather than a deterministic function of the input signal 3 8 ni com Chapter 3 Hardware Overview LSBs LSBs 6 0 6 0 4 0 Ti 4 0 2 0 T 2 0 Py 0 0 4 0 0 2 0 r 2 0 e P ar p 6 0 6 0 0 100 200 300 400 500 0 100 200 300 400 500 a Dither Disabled No Averaging b Dither Disabled Average of 50 Acquisitions LSBs LSBs 6 0 6 0 4 0 4 0 2 0 2 0 v 0 0 0 0 2 0 2 0 ra 4 0 4 0 6 0 6 0 0 100 200 300 400 500 0 100 200 300 400 500 c Dither Enabled No Averaging d Dither Enabled Average of 50 Acquisitions Figure 3 5 Dither You cannot disable dither on the PCI MIO 16XE 10 PCI MIO 16XE 50 NI PCI 6031E NI PCI 6032E or NI PCI 6033E This is because the ADC resolution is so fine that the ADC and the PGIA inherently produce almost 0 5 LSB ms of noise This is equivalent to having a dither circuit that is always enabled Multichannel Scanning Considerations Most of the PCI E Series devices can scan multichannels at the same maximum rate as their single channel rate however pay careful
153. tallation Category II are measurements on household appliances portable tools and similar equipment MAINS is defined as the electricity supply system to which the equipment concerned is designed to be connected either for powering the equipment or for measurement purposes National Instruments Corporation 1 7 PCI E Series User Manual Chapter 1 Introduction e Installation Category II is for measurements performed in the building installation This category is a distribution level referring to hardwired equipment that does not rely on standard building insulation Examples of Installation Category III include measurements on distribution circuits and circuit breakers Other examples of Installation Category III are wiring including cables bus bars junction boxes switches socket outlets in the building fixed installation and equipment for industrial use such as stationary motors with a permanent connection to the building fixed installation e Installation Category IV is for measurements performed at the source of the low voltage 1 000 V installation Examples of Installation Category IV are electric meters and measurements on primary overcurrent protection devices and ripple control units Below is a diagram of a sample installation Category IV Electric Meter Source of Low Voltage 1000 V Installation Circuit Plug in Breaker Equipment Building Fixed Local Level Secondary Installation Distributi
154. tchless and jumperless enhanced MIO devices that use the DAQ STC for timing What is the DAQ STC The DAQ STC is the system timing control application specific integrated circuit ASIC designed by NI and is the backbone of the PCI E Series devices The DAQ STC contains seven 24 bit counters and three 16 bit counters The counters are divided into the following three groups Analog input two 24 bit two 16 bit counters e Analog output three 24 bit one 16 bit counters e General purpose counter timer functions two 24 bit counters The groups can be configured independently with timing resolutions of 50 ns or 10 us With the DAQ STC you can interconnect a wide variety of internal timing signals to other internal blocks The interconnection scheme is quite flexible and completely software configurable New capabilities such as buffered pulse generation equivalent time sampling and seamlessly changing the sampling rate are possible What does sampling rate mean to me It means that this is the fastest you can acquire data on the device and still achieve accurate results For example the PCI MIO 16XE 50 has a sampling rate of 20 kS s This sampling rate is aggregate one channel at 20 kS s or two channels at 10 kS s per channel illustrates the relationship Notice however that some PCI E Series devices have settling times that vary with gain and accuracy Refer to Appendix A Specifications for exact specifications Nation
155. the following conditions e The input signal is high level greater than 1 V e The leads connecting the signal to the PCI E Series device are less than 3 m 10 ft e The input signal can share a common reference point with other signals DIFF input connections are recommended for greater signal integrity for any input signal that does not meet the preceding conditions You can software configure the PCI E Series device channels for two different types of single ended connections RSE configuration and NRSE configuration The RSE configuration is used for floating signal sources in this case the PCI E Series device provides the reference ground point for the external signal The NRSE input configuration is used for ground referenced signal sources in this case the external signal supplies its own reference ground point and the PCI E Series device should not supply one In single ended configurations more electrostatic and magnetic noise couples into the signal connections than in differential configurations The coupling is the result of differences in the signal path Magnetic coupling is proportional to the area between the two signal conductors Electrical coupling is a function of how much the electric field differs between the two conductors PCI E Series User Manual 4 20 ni com Chapter 4 Connecting Signals Single Ended Connections for Floating Signal Sources RSE Configuration Figure 4 7 shows how to connect a float
156. the locations where FCC Class A products can be operated FCC Class B products display either a FCC ID code starting with the letters EXN Trade Name Model Number or the FCC Class B compliance mark that appears as shown here on the right FE Tested to Comply with FCC Standards Consult the FCC Web site at http www fcc gov for more information FCC DOC Warnings This equipment generates and uses radio frequency energy and if not installed and used in strict accordance with the instructions in this manual and the CE Mark Declaration of Conformity may cause interference to radio and television reception Classification requirements are the same for the Federal Communications Commission FCC and the Canadian Department of Communications DOC Changes or modifications not expressly approved by National Instruments could void the user s authority to operate the equipment under the FCC Rules Class A Federal Communications Commission This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment i
157. to 500 ns Figure 4 23 SCANCLK Signal Timing 4 36 ni com Chapter 4 Connecting Signals EXTSTROBE Signal EXTSTROBE is an output only signal that generates either a single pulse or a sequence of eight pulses in the hardware strobe mode An external device can use this signal to latch signals or to trigger events In the single pulse mode software controls the level of the EXTSTROBE signal A 10 us and a 1 2 us clock are available for generating a sequence of eight pulses in the hard ware strobe mode Figure 4 24 shows the timing for the hardware strobe mode EXTSTROBE signal hy Note EXTSTROBE cannot be enabled through NI DAQ VoL ty tw t 600 ns or 5 us Figure 4 24 EXTSTROBE Signal Timing Waveform Generation Timing Connections The analog group defined for the PCI E Series device is controlled by WFTRIG UPDATE and UISOURCE WFTRIG Signal Any PFI pin can externally input the WFTRIG signal which is available as an output on the PFI6 WFTRIG pin As an input the WFTRIG signal is configured in the edge detection mode You can select any PFI pin as the source for WFTRIG and configure the polarity selection for either rising or falling edge The selected edge of the WFTRIG signal starts the waveform generation for the DACs The update interval UI counter is started if you select internally generated UPDATE As an output the WFTRIG signal reflects the trigger that initiates
158. ual Many functions performed by the PCI E Series devices require a frequency timebase to generate the necessary timing signals for controlling A D conversions DAC updates or general purpose signals at the I O connector A PCI E Series device can use either its internal 20 MHz timebase or a timebase received over the RTSI bus In addition if you configure the device to use the internal timebase you can also program the device to drive its internal timebase over the RTSI bus to another device that is programmed to receive this timebase signal This clock source whether local or from the RTSI bus is used directly by the device as the primary frequency source The default configuration at startup is to use the internal timebase without driving the RTSI bus timebase signal This timebase is software selectable The seven RTSI trigger lines on the RTSI bus provide a very flexible interconnection scheme for any PCI E Series device sharing the RTSI bus These bidirectional lines can drive any of eight timing signals onto the RTSI bus and can receive any of these timing signals This signal connection scheme is shown in Figure 3 13 3 18 ni com Chapter 3 Hardware Overview DAQ STC lt gt TRIG1 gt TRIG2 4 h CONVERT M UPDATE K WFTRIG t gt GPCTRO SOURCE M gt GPCTRO_GATE t GPCTRO OUT e gt STARTSCAN p AGATE L S
159. uctions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation Trademarks CVI DAQ STC LabVIEW Measurement Studio MITE MXI National Instruments NI ni com NI DAQ NI PGIA RTSI and SCXI are trademarks of National Instruments Corporation Product and company names mentioned herein are trademarks or trade names of their respective companies Patents For patents covering National Instruments products refer to the appropriate location Help Patents in your software the patents txt file on your CD or ni com patents WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS 1 NATIONAL INSTRUMENTS PRODUCTS ARE NOT DESIGNED WITH COMPONENTS AND TESTING FOR A LEVEL OF RELIABILITY SUITABLE FOR USE IN OR IN CONNECTION WITH SURGICAL IMPLANTS OR AS CRITICAL COMPONENTS IN ANY LIFE SUPPORT SYSTEMS WHOSE FAILURE TO PERFORM CAN REASONABLY BE EXPECTED TO CAUSE SIGNIFICANT INJURY TO A HUMAN 2 IN ANY APPLICATION INCLUDING THE ABOVE RELIABILITY OF OPERATI
160. ues to count down and reload itself until the scan is finished It then reloads itself in preparation for the next STARTSCAN pulse A D conversions generated by either an internal or external CONVERT signal are inhibited unless they occur within a DAQ sequence Scans occurring within a DAQ sequence may be gated by either the hardware AIGATE signal or software command register gate AIGATE Signal Any PFI pin can externally input the AIGATE signal which is not available as an output on the 1 O connector The AIGATE signal can mask off scans in a DAQ sequence You can configure the PFI pin you select as the source for the AIGATE signal in level detection You can configure the polarity selection for the PFI pin for either active high or active low In the level detection mode if AIGATE is active the STARTSCAN signal is masked off and no scans can occur The AIGATE signal can neither stop a scan in progress nor continue a previously gated off scan In other words once a scan has started AIGATE does not gate off conversions until the beginning of the next scan conversely if conversions are being gated off AIGATE does not gate them back on until the beginning of the next scan SISOURCE Signal Any PFI pin can externally input the SISOURCE signal which is not available as an output on the I O connector The onboard scan interval counter uses the SISOURCE signal as a clock to time the generation of the STARTSCAN signal You must config
161. uirements for the GPCTRI SOURCE signal os y DA gt tp 50 ns minimum ty 23 ns minimum Figure 4 33 GPCTR1 SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation The 20 MHz or 100 KHz timebase normally generates the GPCTRI SOURCE unless you select some external source GPCTR1 GATE Signal Any PFI pin can externally input the GPCTR1 GATE signal which is available as an output on the PFI4 GPCTR1_GATE pin As an input the GPCTR1 GATE signal is configured in edge detection mode You can select any PFI pin as the source for GPCTR1 GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform such actions as starting and stopping the counter generating interrupts saving the counter contents and so on National Instruments Corporation 4 43 PCI E Series User Manual Chapter 4 Connecting Signals As an output the GPCTR1_GATE signal monitors the actual gate signal connected to general purpose counter 1 even if the gate is being externally generated by another PFI This output is set to high impedance at startup Figure 4 34 shows the timing requirements for the GPCTR1 GATE signal Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 34 GPCT
162. unded source you should not reference the signal to AIGND You can avoid this reference by using DIFF or NRSE input configurations Types of Signal Sources When configuring the input channels and making signal connections you must first determine whether the signal sources are floating or ground referenced The following sections describe these two types of signals National Instruments Corporation 4 13 PCI E Series User Manual Chapter 4 Connecting Signals Floating Signal Sources A floating signal source is not connected in any way to the building ground system but rather has an isolated ground reference point Some examples of floating signal sources are outputs of transformers thermocouples battery powered devices optical isolator outputs and isolation amplifiers An instrument or device that has an isolated output is a floating signal source You must tie the ground reference of a floating signal to the PCIE Series device AI ground to establish a local or onboard reference for the signal Otherwise the measured input signal varies as the source floats out of the common mode input range Ground Referenced Signal Sources A ground referenced signal source is connected in some way to the building system ground and is therefore already connected to a common ground point with respect to the PCI E Series device assuming that the computer is plugged into the same power system Nonisolated outputs of instruments and dev
163. up Time tysu 10 ns minimum Gate Hold Time toh 0 ns minimum Gate Pulse Width tgw 10 ns minimum Output Delay Time tout 80 ns maximum Figure 4 36 GPCTR Timing Summary The GATE and OUT signal transitions shown in Figure 4 36 are referenced to the rising edge of the SOURCE signal This timing diagram assumes that the counters are programmed to count rising edges The same timing diagram but with the source signal inverted and referenced to the falling edge of the source signal would apply when the counter is programmed to count falling edges The GATE input timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated signals on the PCIE Series device Figure 4 36 shows the GATE signal referenced to the rising edge of a source signal The gate must be valid either high or low for at least 10 ns before the rising or falling edge of a source signal for the gate to take effect at that source edge as shown by tesu and t in Figure 4 36 The gate signal is not required to be held after the active edge of the source signal If you use an internal timebase clock the gate signal cannot be synchronized with the clock In this case gates applied close to a source edge take effect either on that source edge or on the next one National Instruments Corporation 4 45 PCI E Series User Manual Chapter 4 Connecting Signals This arrangement results in an uncertainty of one source clock period with resp
164. ure the PFI pin you select as the source for the SISOURCE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low National Instruments Corporation 4 35 PCI E Series User Manual Chapter 4 Ej Connecting Signals The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 kHz internal timebase generates the SISOURCE signal unless you select some external source Figure 4 22 shows the timing requirements for the SISOURCE signal M te tw gt e tw gt tp 50 ns minimum ty 23 ns minimum Figure 4 22 SISOURCE Signal Timing SCANCLK Signal SCANCLK is an output only signal that generates a pulse with the leading edge occurring approximately 50 to 100 ns after an A D conversion begins The polarity of this output is software selectable but is typically configured so that a low to high leading edge can clock external AI multiplexers indicating when the input signal has been sampled and can be removed This signal has a 400 to 500 ns pulse width and is software enabled Figure 4 23 shows the timing for the SCANCLK signal Note When using NI DAQ SCANCLK polarity is low to high and cannot be changed programmatically PCI E Series User Manual CONVERT SCANCLK lt uj hi gt o ty 50 to 100 ns ty 400
165. using Windows Measurement amp Automation Explorer MAX has a Test Panel option available by selecting Devices and Interfaces and then selecting the device The test panels are excellent tools for performing simple functional tests of the device such as AI DIO and counter timer C 2 ni com Appendix C Common Questions tests If you are using Mac OS the NI DAQ Configuration Utility provides the same functionality Analog Input and Output I m using my device in DIFF AI mode and I have connected a differential input signal but my readings are random and drift rapidly What s wrong Check the ground reference connections The signal may be referenced to a level that is considered floating with reference to the device ground reference Even if you are in differential mode the signal must still be referenced to the same ground level as the device reference There are various methods of achieving this while maintaining a high common mode rejection ratio CMRR These methods are outlined in Chapter 4 Connecting Signals I m using the DACs to generate a waveform but I discovered with a digital oscilloscope that there are glitches on the output signal Is this normal When it switches from one voltage to another any DAC produces glitches due to released charges The largest glitches occur when the most significant bit MSB of the D A code switches You can build a lowpass deglitching filter to remove some of these glitches depend
166. ution Degree 2 means that only nonconductive pollution occurs in most cases Occasionally however a temporary conductivity caused by condensation must be expected e Pollution Degree 3 means that conductive pollution occurs or dry nonconductive pollution occurs which becomes conductive due to condensation Clean the product with a soft nonmetallic brush The product must be completely dry and free from contaminants before returning it to service You must insulate signal connections for the maximum voltage for which the product is rated Do not exceed the maximum ratings for the product Remove power from signal lines before connection to or disconnection from the product Operate this product only at or below the installation category stated in Appendix A Specifications The following is a description of installation categories e Installation Category I is for measurements performed on circuits not directly connected to MAINS This category is a signal level such as voltages on a printed wire board PWB on the secondary of an isolation transformer Examples of Installation Category I are measurements on circuits not derived from MAINS and specially protected internal MAINS derived circuits e Installation Category II is for measurements performed on circuits directly connected to the low voltage installation This category refers to local level distribution such as that provided by a standard wall outlet Examples of Ins
167. utput Signal Timing National Instruments Corporation 4 31 PCI E Series User Manual Chapter 4 Connecting Signals PCI E Series User Manual STARTSCAN Signal Any PFI pin can externally input the STARTSCAN signal which is available as an output on the PFI7 STARTSCAN pin Refer to Figures 4 12 and 4 13 for the relationship of STARTSCAN to the DAQ sequence As an input the STARTSCAN signal is configured in the edge detection mode You can select any PFI pin as the source for STARTSCAN and configure the polarity selection for either rising or falling edge The selected edge of the STARTSCAN signal initiates a scan The sample interval counter starts if you select internally triggered CONVERT As an output the STARTSCAN signal reflects the actual start pulse that initiates a scan even if the starts are being externally triggered by another PFI You have two output options The first is an active high pulse with a pulse width of 50 to 100 ns which indicates the start of the scan The second action is an active high pulse that terminates at the start of the last conversion in the scan which indicates a scan in progress STARTSCAN is deasserted t after the last conversion in the scan is initiated This output is set to high impedance at startup Figures 4 18 and 4 19 show the input and output timing requirements for the STARTSCAN signal Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure
168. voltage reference This error is addressed by external calibration which is discussed in the following section If you are interested primarily in relative measurements you can ignore a small amount of gain error and self calibration should be sufficient External Calibration PCI E Series User Manual The PCI E Series device has an onboard calibration reference to ensure the accuracy of self calibration Its specifications are given in Appendix A Specifications The reference voltage is measured at the factory and stored in the EEPROM for subsequent self calibrations This voltage is stable enough for most applications but if you are using the device at an extreme temperature or if the onboard reference has not been measured for a year or more you may wish to externally calibrate the device An external calibration refers to calibrating the device with a known external reference rather than relying on the onboard reference Redetermining the value of the onboard reference is part of this process and the results can be saved in the EEPROM so you should not have to perform an external calibration very often You can externally calibrate the device by calling the NI DAQ calibration function To externally calibrate the device be sure to use a very accurate external reference The reference should be several times more accurate than the device itself For example to calibrate a 16 bit device the external reference should be at least 0 0

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