Reference Manual
Contents
1. N HSMC 2 DATAOUTS N 68 HSMC2 DATANSN 14 Po 49 95 3 pATAOUTe P 150 3 P HSMC 2 P 152 3 HSMC 2 14 74 HSMC 2 N 153 154 76 155 HSMC 3 CLKOUT P 156 HSMC 3 CLKIN P HSMC 2 DATAOUTS P HSMC 2 5 P HSMC 3 CLKOUT N 158 HSMC 3 CLKIN N 2 DATAOUTS N 9 HSMC2DATANGN i15 5 5 Serial Port The Beryll Board has an asynchronous serial port An LTC2803 FPGA transceiver and a 9 pin D SUB connector from Linear Technology s LTC2803 are used for RS232C interface For pin information on the FPGA LTC2803 and D SUB connector see Figure 6 and the pin list shown below When purchasing a serial cable choose a straight type For details of Linear Technology s LTC28093 visit the following URL ja ur AX 2 79 SMC 3 DATAIN2 P 5 3 DATAIN2 x x 25 Ix http www linear com product LTC2803 Note The URL above is subject to change without notice UART_RXD R1IN JNO S RYAN Linear Technology Py EE LTC2803 yclone UART TXD T1OUT Figure 6 Connections of the FPGA LTC2803 and DB9 Connector Reference Manual Mpression Beryll Board Mpression by Macnica Group Mpression Beryll Board ESSION Solutions by Macnica Group Table 5 RS232C pin list UART TXD Transmitter Bank 8A K6 14 3 2 UA2. Mpression by Macnica Group Reference Manual Mpression Beryll Board pression Mpression Beryll Board 5 The Beryll Board Components This chapter describes the FPGA and various components installed on the periphery of the FPGA on the Beryll Board 5 1 Featured Device Cyclone V GX FPGA The Beryll Board carries 28 nm low cost FPGA Cyclone V GX manufactured by Altera Corporation Table 4 shows the specifications of the Cyclone V GX FPGA Table 4 Cyclone V GX FPGA Specifications Core Fabric Internal Connection Hardware IP i Device Number of Numberof Block Number of EAE of Number of Number of Number of LVDS PCIe memory Memory memory DSP gt 2 blocks Kb blocks PLL GrETO pius pairs blocks controllers LEs sok mo 2500 s m e w 2 2 5 2 FPGA and EPCS Configuration ROM Programming To carry out programming to the FPGA and EPCS ROM connect the Mini USB Cable that comes with the Beryll Board to USB Blaster U27 and write the program in the configuration file Therefore users do not need to prepare programming hardware such as a USB Blaster cable from Altera separately 5 2 1 Preface Use the Quartus II Programmer to perform programming writing the programming file into the configuration file for the device When being used for the first time it is necessary to install the drivers for each piece of programming hardware 5 2 2 Howto Perform Programming for t
3. 5 Jo o es 8 pDR2DQiO faca 8 Jo o 2 2 DDR3DQU aria 29 o jDDR3DQI2 fasie far 9 DDR3 Dan faaie 0 DDR3 AEM Aris 8 Signal Name DDR3 ADDRO DDR3 ADDR1 DDR3 ADDR2 DDR3 ADDR3 DDR3 ADDR4 DDR3 ADDR5 DDR3 ADDR6 DDR3 ADDR7 DDR3 ADDR8 DDR3 ADDR9 DDR3 DM3 DDR3 CS N DDR3 CAS N DDR3 RAS N 5 Table 6 Pin Information of the DDR3 Memory DDR 0 DDR 1 FPGA Signal Name iil DDR3 DQ DDR3 DQ 5 5 7 FLASH SRAM Beryll Board has JS28F256M29EWL 16 bit width 256 Mbits Flash ROM manufactured by Micron Technology Inc and IDT71V416S10PHGS8 16 bit width 4 Mbits SRAM manufactured by Integrated Device Technology IDT The address and data bus are shared by the Flash ROM and SRAM You can use the Flash ROM for booting the Nios II software and use the SRAM as a cache ROM for Nios II when you use a Nios II processor for Cyclone V GX FPGA These devices can also be used as general purpose Flash ROM and SRAM respectively For pin information of the Flash ROM and SRAM see Figure 8 The data sheet for the Flash ROM can be obtained from the following URL http www micron com parts nor flash parallel nor flash js28f256m29ewla pczi19A9BFAD5 DEEO 4 DDR 0 Mpression Beryll Board DDR 1 Pin Number Pi
4. RESSION Solutions by Macnica Group Reference Manual Mpression Beryll Board Revision 1 0 2014 2 Solutions by Macnica Group http www m pression com ESSION Mpression Beryll Board Solutions by Macnica Group Mpression Solutions by Macnica Group Disclaimer The information in this document hereinafter called Information is subject to change without notice Altima Corp makes no warranty of any kind regarding this document or of any liability arising out of the application or use of information in this document and assumes no responsibility for any errors that may appear in this document This document is distributed without any charge and reselling or copying without written authorization by Developer is restricted IN NO EVENT WILL DEVELOPER BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOST DATA AND LOST PROFITS ARISING FROM OR RELATING TO YOUR USE OF THE INFORMATION EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES THE TOTAL CUMULATIVE LIABILITY OF DEVELOPER IN CONNECTION WITH YOUR USE OF THE INFORMATION IN THIS DOCUMENT WHETHER IN CONTRACT OR TORT OR OTHERWISE WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO DEVELOPER HEREUNDER FOR USE OF THE INFORMATION YOU ACKNOWLEDGE THAT THE FEES IF ANY REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT DEVELOPER WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITH
5. Compiling the design creating a programming file Step 2 Creating a JIC file Step 3 Programming Step 1 Compiling the design Compile the design in order to create a configuration file sof which will be the basis for the JIC file Reference Manual Mpression Beryll Board Mpression by Macnica Group Mpression Beryll Board ESSION Solutions by Macnica Group Select the Processing menu and then Start Compilation or click the button Step 2 Creating a JIC file Create a jic file which will be the programming file for JIC from the SOF file which has been generated after compilation 1 Select the File menu and then Convert Programming Files 2 In Output Programming File set a file format to create configuration device and output file name Select JTAG Indirect Configuration File jic as a Programming file type n Configuration device set the type of the configuration device for which programming will be performed Select EPCS128 for the Beryll Board Specify a generation path of the output file and an output file name for File name 1 In Input files to convert select a type of FPGA for which the serial flash loader design is used Select the Flash Loader line and click the Add Device button nthe Select Device dialog box select Cyclone V GX for Device family and select Device name and click the OK button 2 Specify a configuration file sof that will be the basis for the J
6. Board Mpression by Macnica Group Mpression Beryll Board ESSION Solutions by Macnica Group 4 The Beryll Board Hardware Overview 4 1 Overview The Beryll Board is an FPGA development board that uses Cyclone V GX FPGA which is a low cost FPGA manufactured by Altera Corporation This development board has the following features Users can develop and test user logic flexibly using Cyclone V GX FPGA Users can expand their own system by preparing a daughter card connector HSMC manufactured by Altera Corporation With a built in On Board USB Blaster circuit users can download the FPGA configuration circuit by connecting a USB cable Users can use the hard memory controller HMO which has been installed in Cyclone V FPGA and later versions together with DDR3 memory from Micron Technology to carry out evaluations 4 2 Key Components Table 1 shows the product specifications of the Beryll Board Note Although the character LCD connector comes with the Beryll Board the LCD display is Table 1 Beryll Board Product Specifications FPGA Power Supply Dimensions HSMC Printed Circuit Board Configuration ROM SRAM DDR SDRAM Flash ROM USB 2 0 Mini B Audio Ethernet Clock for FPGA JTAG Connector Status LED FPGA Reconfiguration Push SW General purpose LED General purpose Push SW General purpose Dip SW General purpose 7 Segment LED Character LCD Connector Power SW RS 232C 5CGXFC
7. have now completed programming of the EPCS device by J TAG Indirect Configuration 5 4 Connector Pin Assignment Figure 5 shows the locations of connectors and the pin assignment of each connector 15 Gi 027 For USB Blaster FEL EL 035 a Pin Signal Name Pin Signal Name 3 Lip Uaec 03 U17 ENET CONN Pin Signal Name Pin Signal Name as 17 1 2 TDO 9 mP 4 TD1 N 09 5 war 6 mn o9 TD3 P 78 TD3 N 99 O Pe vec 0 GN 04 J3 Audio Line In 2 Pin Signal Name e ot 20 Reference Manual Mpression Beryll Board Mpression by Macnica Group Mpression Beryll Board pression Solutions by Macnica Group 05 J4 Audio Line Out Pin Signal Pin Signal Name Pin Signal Name O c Signal Name Pin Signal Name Lr 5 O Pin Signal Name Pin Signal Name C 1 MESE O Za Ue 9 J6 RS232C DSub9 Pin Female Connector Pin Signal Name Pin Signal Name 1 NC 2 URDDO ERE Rc D UR MNA 9 OOOOO 5 10 J5 Character LCD Pin Signal Name Pin Signal Name w f w 3 n 4 6555 7 5 ic RW e toe 7 10b DAT e 9 310 LCD DATAS Mpression by Macnica Group Reference Manual Mpression Beryll Board
8. ips to set the I O pin status in programming This option is supported only for MAX 7000B and 5 3 Programming to the EPCS Configuration device 5 3 1 Preface With the JTAG Indirect Configuration JIC file for the FPGA device you can perform programming of the EPCS device which does not support the JTAG interface through the JTAG chain 5 3 2 Outline of JIC When the EPCS device is used as a configuration device for the Cyclone V device the data transfer method supports the active serial configuration mode AS mode To perform configuration in AS mode a 10 pin header used to perform programming in AS mode is required in the EPCS device On the other hand to configure data for the FPGA through the JTAG port or to perform debugging using SignalTap II another 10 pin header for JTAG is also needed However the JIC function is used the serial flash loader design in the FPGA works as a bridge and so programming for the EPCS device can be performed through the JTAG port For this reason the 10 pin header for the AS mode is no longer needed which allows users to reduce both the board area and the cost 5 3 3 Programming method for EPCS configuration ROM Programming through the serial flash loader is performed using a JIC file instead of using a traditional SOF file or POF file To perform programming create a JIC file from the SOF file a configuration file for FPGA The flow of this operation is as follows Step 1
9. o ESSION Mpression Beryll Board by Macnica Group 11 J8 HSMC Connector Signal Name Pin Signal Name Signal Name Signal Name Pin in 2 81 82 85 HSMC 2 DATAOUT6_N 86 HSMC 2 DATAIN6 ener E y 0 9 10 89 HSMC 2 DATAOUT P 9 HSMC 2 7 P C O T S o 2 N 92 HSMC 2 N 141 125 8 7 96 HSMC_2_CLKINP oxposPe exmosP 97 HSMC_2 98 HSMC_2 N emn o 102 3 DATANO P 104 HSMC_3_DATAINO_N exmoip ef 108 3 DATA 110 HSMC 3 DATA a xeon Je 114 116 1 77 1 40 HSMC 1 CLKN 119 HSMC 3 DATAOUTS P 120 HSMC 3 122 HSMC 3 DATANS HSMCDATA2 44 HSMCDATAS 125 25 95 3 DATAOUTA P 126 3 P HSMC 2 DATAOUTO P 48 2 DATANNO P 128 3 DATAIN4 HSMC 2 DATANO N 20 130 PoC 5 3 DATAOUIS P 132 HSMC 3 DATAS P HSMC 2 DATANT P 134 HSMC 3 DATANNS N HSMC 2 N 139 95 3 PATAOUTe P 138 HSMC_3_DATAING HSMC 2 DATAOUTZ P 60 HSMC 2 DATAIN2 P 140 HSMC 3 6 HSMC 2 DATANZN ___ OO O ea 4 95 3 PATAOUTZ P 144 3 P HSMC 2 DATAOUTS P 66 HSMC 2 DATAINS P 146 HSMC 3
10. this device can be obtained from the following URL http www nxp com documents data_sheet UDA1345TS pdf Note The URL above is subject to change without notice SYS_CLK BCK WS lt DATAO DATAI UDA1345 V v MP5 Figure 11 Connection of the FPGA and UDA1345 Table 10 Pin assignment list of the FPGA and UDA1345 FPGA Pin Audio Pin Number Number Signal Name AUDIOMPI 74 9 5 11 User Interfaces The Beryll Board provides various input interfaces that can be set uniquely by the user Those user interfaces include eight LEDs two 7 SEGs four push buttons one DIP switch one character LCD and one UART For details of the specifications of each pin see the pin list shown below Reference Manual Mpression Beryll Board Mpression by Macnica Group Mpression Beryll Board pression Solutions by Macnica Group Table 11 Pin Assignment list of the Input Interfaces FPGA Pin FPGA Pin Signal Number Function Signal Name Number Function LED_NO DIPSWO LED N1 DIPSWI User DIP SW LED N2 DIPSW2 LED8 0 SEVEN_SEG1 AD6 Character LCD SEVEN SEG 0 W20 User Push Button eae m seven seven sron Rs seven Ps Mpression by Macnica Group Reference Manual Mpression Beryll Board pression Mpression Beryll Board Solutions b
11. 13 Y GF Bare Boord 14 USB Blaster ph oan 13 FPGA_Reconfig EE if 12 CPU_RESETn 72 28 45 11 SMA_CLKIN CLKO 9 PBO PB1 PB2 Figure 2 Beryll Switch Connector layout IND Reference Manual Mpression Beryll Board Mpression by Macnica Group ARAS Mpression Beryll Board 1 HSMC 2 DC Jack 10 3 Power supply switch 11 4 USB2 0 Mini B connector 12 5 Ethernet connector RJ45 13 6 Ethernet DIP switch 14 7 Audio line input output 15 8 Audio DIP switch 16 4 4 2 Beryll Component Layout pression Solutions by Macnica Group 9 General purpose push switches General purpose DIP switch SMA_CLKIN SMA_CLKOUT connectors Reset push switch FPGA reconfiguration push switch USB blaster switch JTAG connector for FPGA unimplemented RS232C connector Figure 3 shows the layout of major Beryll components 10 DDR3 SDRAM E 3 USB 2 0 Device PHY 724 amp Controller PEGN Atti A 1134 Figure 3 Beryll Component layout 1 Cyclone V GX FPGA 9 2 Power LED 10 3 USB2 0 Device PHY and controller 11 4 Ethernet PHY 12 5 Ethernet LED x 5 ACT LK10 LK100 LK1000 DUPLEX 13 6 Audio Codec 14 7 SRAM 15 8 FLASH Mpression by Macnica Group 7 Segment LED DDR3 SDRAM User LED FPGA status LED x 4 nSTATUS nCONFIG CONF DONE INIT DONE USB BLASTER LED Configuration ROM Character LCD Option Reference Manual Mpression Beryll Board pression Mpression Beryl Board Soluti
12. 48 MHz 3 3V K25 USB2 0 PHY amp controller 5 12 2 Off board Inputs Outputs The Beryll Board has input and output clocks which can be driven onto the board Table 13 lists the clock inputs for the Beryll Board Table 13 Off board Clock Inputs O ptio ana De HSMC HSMC_1_CLKIN 2 5V L8 Modius installed HSMC cable or board HSMC 2 CLKIN P LVDS 2 5V H12 LVDS input from the installed HSMC HSMC cable or board Can also support 2x HSMC 2 CLKIN ypg 2 5v G11 2 5V inputs HSMC 3 CLKIN P LVDS 2 5V G15 LVDS input from the installed HSMC HSMC so cable or board Can also support 2x rix S 2 5V G14 2 5V inputs SMA SMA_CLKIN 2 5V N9 User Mpression by Macnica Group Reference Manual Mpression Beryll Board eas pression Mission Belo Solutions by Macnica Group Table 14 lists the clock outputs for the Beryll Board Table 14 Off board Clock Outputs ource O Standard Descriptio anal Naame 5e HSMC HSMC 1 CLKOUT 2 5V AT FPGA 2 5V output or GPIO HSMC 2 CLKOUT LVDS 2 5V B15 LVDS output Can also support 2x HSMC 2 CLKOUT N LVDS 2 5V C15 2 5V outputs HSMC HSMC 3 CLKOUT P LVDS 2 5V A23 LVDS output Can also support 2x HSMC 3 CLKOUT N LVDS 2 5V A22 2 5V outputs SMA SMA CLKOUT 2 5V M9 User 5 13 Power Tree The Beryll Board uses a power supply device manufactured by Linear Technolog
13. 4C6F27C 40 00 mm x 155 00 mm ASP 122953 01 FR4 10 layer 51285116 IDT71V416S10PHG8 512 KByte DDR3 800 256 MBytes 128 MByte x 2 MT41J64MJT S28F256M29EWLA 32 MByte CY7C68013A 56LTXC UDA1345TS DP83865DVH 7 MHz x 1 33 MHz x 1 50 MHz x 1 125 MHz x 1 DIP 10 pin Header 2 54 mm pitch x 1 12 pcs 12V POWER HSMC PSNTn nSTATUS nCONFIG CONF DONE c g O lt e gt INIT DONE Blaster ACT LK10 LK100 LK 1000 DUPLEX 1 SYS RESET 1 SWO SW3 3 3 V A character LCD is optional DB9 Female Connector optional An LCD display should be prepared by the user Mpression by Macnica Group Reference Manual Mpression Beryll Board pression Mpression Beryl Board Solutions by Macnica Group 4 3 Block Diagram Figure 1 shows the block diagram of the Beryll Board Because the Beryll Board is an evaluation board using the properties of Cyclone V GX FPGA all of the functions are integrated in Cyclone V GX FPGA DP83865DVH USB Jack CY7C68013A 1285116 je Cyclone V GX Character LCD Dsub UDA1345TS Audio Jack Figure 1 Beryll Board Block Diagram 4 4 Board Specifications This section describes the layout of switches connectors and components on the Beryll Board 4 4 1 Beryll Switch Connector Layout Figure 2 shows the layout of switches and connectors used on the Beryll Board 16 RS232C_CONN 15 FPGA JTAG ALTIMA
14. IC file Select the SOF Data line and click the Add File button Select as SOF file to convert and click the Open button 3 To compress a programming file select an SOF to be compressed and click the Properties button In the SOF File Properties dialog box check the Compression option box and click the OK button 4 Click the Generate button A message reading Generated lt jic file name gt successfully is displayed and creation of the JIC file is complete Step3 Programming Programming of the JIC file you have created to the EPCS device is performed in mode 1 Start Programmer Select the Tools menu and then Programmer or click the V button 2 Select hardware download cable to be used and select JTAG for Mode 3 Click the AddFie button and select a JIC file 4 Check the Program Configure option box on the file line 5 Click the PH Stat button to start programming The serial flash loader in the FPGA device becomes enabled first and then EPCS programming is executed through the serial flash loader When the programming is completed successfully the Progress gauge in the upper right of the Programmer window reaches 100 Mpression by Macnica Group Reference Manual Mpression Beryll Board pression Solutions by Macnica Group and a message informing you of the successful completion of programming is shown in the Message dialog box You
15. ITEN m WEN FLASH ADDRESS ye _SRAMBEON vo BLEN FLASH ADDRESS24 Uie as mo smn 5 8 USB 2 0 The Beryll Board has EZ USB CY7C68013A 56LTXC manufactured by Cypress Semiconductor Corporation for USB2 0 interface This device works as a controller for USB2 0 interface in which a USB controller with a USB2 0 transceiver and 8051 microprocessor and 16 KB RAM are integrated The Cyclone V GX FPGA installed on the Beryll Board receives signals at the GPIF level from Mpression by Macnica Group Reference Manual Mpression Beryll Board ESSION Mpression Beryll Board Solutions by Macnica Group Cypress Semiconductor s EZ USB For pin information of the FPGA and CY7C68013 see Figure 9 and the pin assignment list shown below The data sheet for Cypress Semiconductor s EZ USB can be obtained from the following URL http www cypress com mpn CY7C68013A 56LTXC Note The URL above is subject to change without notice EZ EZ RESET N E EZ RDY 1 0 ANU S RYAN EZ CTL 2 0 Cypress EZ WAKEUP CY7C68013A USB EZ_VBUS_N js Cyclone V 7 0 USB2 0 Mini EZ PB 7 0 EZ PD 7 0 lt eT Figure 9 Connections of the FPGA and EZ USB Table 8 Pin Information of the FPGA and EZ USB FPGA Pin USB Pin Sional Name FPGA Pin USB Pin Number Number 9 Number Number Signal Name R
16. OUT THESE LIMITATIONS OF LIABILITY The Design is not designed or intended for use in the development of on line control equipment in hazardous environments requiring failsafe controls such as in the operation of nuclear facilities aircraft navigation or communications systems air traffic control life support or weapons systems High Risk Applications Developer specifically disclaims any express or implied warranties of fitness for such High Risk Applications You represent that use of the Design in such High Risk Applications is fully at your risk Reference Manual Mpression Beryll Board Mpression by Macnica Group Mpression Beryll Board ESSION Solutions by Macnica Group Index 1 For Ensuring Safe Use 4 T1 Legna 4 1 2 CAUTIONS ie 4 1 3 Developer Information nennen tnter tnnt nnns 6 7 2 Important Information 8 3 Unboxing 10 4 The Beryll Board Hardware Overview 11 A C TNT 11 4 2 Key Components iieri eniro aeo are tania REN av ba a ERE ER e ERR PORE EE ERR REPRE 11 4 3 Block DIagralm aiite are ti iei soi ed e aun 12 A A Board Specifications coo Renee A arva ia Rn RR 12 5 The Beryll Board Components 16 5 1 Featured Devi
17. RT RXD Receiver Bank 8A 17 16 1 3 5 6 DDR3 SDRAM The Beryll Board has two MT41J64M16JT 16 bits 128 MBytes manufactured by Micron Technology Inc and they are connected to the hard memory controller HMC of the FPGA Users can evaluate the hard memory controller of Cyclone V GX FPGA by using the attached reference design For pin information of the Cyclone V GX FPGA and DDR3 memory see Figure 7 The data sheet for Micron s MT41J64M16JT can be obtained from the following URL http www micron com parts dram ddr3 sdram mt41 64m16jt 15e Note The URL above 1s subject to change without notice Note The DDR3 memory installed on the Beryll Board may be replaced by an equivalent product that satisfies conditions for realizing DDR3 800 Mbps DDR3_ADDR 12 0 DDR3 ODT DDR3 CS E DDR3 CLK P DDR3 CLK N AND pYA DDR3 CKE DDR3 BA 2 0 DDR3 RAS DDR3 CAS Micron DDR3 WE MT41J64M V DDR3 DQ 15 0 DDR3 DQ 3 0 DDR3 DOS N 1 0 DDR3 DM 1 0 Micron DDR3_DQ 31 16 MT41J64M DDR3_DQS 3 0 DDR3_DQS_N 3 2 DDR3 DM 3 2 Figure 7 Connections of the FPGA and DDR3 Memory Mpression by Macnica Group Reference Manual Mpression Beryll Board ESSION Solutions by Macnica Group FPGA Pin Number Pin Number Pin Number AEG DRaDQS facis o jare 7 7
18. asynchro nous staticcram center pwr gnd pinout Note The URL above is subject to change without notice Reference Manual Mpression Beryll Board Mpression by Macnica Group Mpression Beryll Board ESSION Solutions by Macnica Group ADR 24 1 gt gt gt FLASH_CS_N f CEn ELASH READ N 11 gt ANU S RYAN ELASH WRITE N j WEn JS28F256 FLASH ADR 18 1 DATA 15 0 CEn OEn IDT ELM t WEn gt IDT71V416S LBn SRAM Figure 8 Pin Information of the FPGA and FLASH SRAM Table 7 Pin Information of the FPGA and FLASH SRAM FPGA FLASH SRAM FPGA FLASH SRAM Signal Name Signal Name Pin Number Pin Number Pin Number Pin Number Pin Number Pin Number FLASH ADDRESSI FLASH ADDRESS FLASH ADDRESS FLASH ADDRESS4 FLASH ADDRESSS FLASH ADDRESSG FLASH ADDRESST FLASH ADDRESSS FLASH ADDRESS FLASH ADDRESSIO FLASH ADDRESS FLASH ADDRESSI2 FLASH ADDRESSIS FLASH ADDRESSI4 FLASH ADDRESSIS FLASH ADDRESSIG FLASH_ADDRESSI7 ams n FLASH ADDRESSIS vis Am r FLasumREApN ve on FLASH ADDRESSIS wis as FLASH_WRITEN wi WEN FLASH ADDRESS20 vis aw vo SN FLASH ADDRESS21 A samorn os on FLASH ADDRESS22 Ur an SRAM_WR
19. ce Cyclone V GX FPGA 0 22 0 000 0000000000 010000000 16 5 2 FPGA and EPCS Configuration ROM Programming cccsssscceccecesssceseeceecsesseaeseeceeceessaeeeeees 16 5 3 Programming to the EPCS Configuration 18 5 4 Connector Pin 2 0 0 0 nennt tenia ases sisi sa sa sa sa sara sanas asa rasan 20 5 5 Seral dee 22 5 6 IDDRS SDRAM 23 BoD FLASH SRAM EE 24 NIA E 25 5 9 10 100 1000 Ethernet oie estre PE ob ete a 27 5 1024 bit Audio Codec oorr b HER RE XR PER ERR a na anias oeiia 28 54 10ser Interfaces 2 7 rtt het dioe ei 28 5 12 Clock RT 30 Dc USIPOWER rcc MR 32 6 Operating Precautions 33 6 1 Mode Selection for Unused Pins esee eene nnn nnne n 33 7 Document Revision History 34 Mpression by Macnica Group Reference Manual Mpression Beryll Board o ESSION Mpression Beryll Board Solutions by Macnica Group 1 For Ensuring Safe Use Be sure to follow the instructions given in this Manual which are intended to prevent harm to the user and others as well as material damage 1 1 Legend Indicates an imminent hazardous situation which if not avoided will result in Danger death or se
20. cumulated on the power plug and around the outlet socket Do not use a power plug with dust accumulated on it because doing so will lead to insulation failure due to moisture which may lead to fire Remove any dust on the power plug and around the outlet with dried cloth Do not place any containers such as cups or vases filled with water or other liquid on this Board If this Board is exposed to water or other liquids it may cause the Board to malfunction or lead to accidents involving electrical shock If you spilled water or other liquid on this Board immediately stop using the Board turn off the power and unplug the power plug If you have any requests for repairs or technical consultation please contact the local Macnica company or Mpression inquiry URL Do not place the kit on unstable places such as shaky stands or tilted locations Doing so may cause injuries or cause this Board to malfunction if the Board should fall Do not attempt to use or leave the kit in places subject to strong direct sunlight or other places subject to high temperatures such as in cars in hot weather Doing so might cause the kit to emit heat break ignite run out of control warp or malfunction Also some parts of the equipment might emit heat causing burn injuries fp Cauti Unplug the power supply cable when carrying out maintenance of devices in aution which the main unit is embedded Failure to do so may lead to accidents involvin
21. e SOF file sof Programming file for FPGA of Stratix FPGA Arria FPGA and Cyclone FPGA JIC file jic Programming file for configuration device Reference information Program Configure Writes programming data performs programming into the device Verify Compares the contents of the programming data registered in Programmer with the contents written in the device to verify the programming data Blank Check Confirms that the device is completely empty that the contents in the device have been completely deleted Examine Loads programming data which has been written in the MAX CPLD devices or configuration device The data which has been loaded can be saved as a programming file Data that has been written when the Security Bit option see the next item was enabled cannot be loaded correctly Executing Examine will not delete the data in the device Data that has been loaded cannot be restored to the design file Mpression by Macnica Group Reference Manual Mpression Beryll Board o ESSION Mpression Beryll Board Solutions by Macnica Group Security Bit Prevents the data that has been written into the device from being checked or the data which has been loaded by Examine from being copied when re programmed This option is supported only for MAX 7000 and MAX 3000 Erase Deletes data stored in the MAX CPLD device or configuration device ISP CLAMP Uses the IPS file
22. eference Manual Mpression Beryll Board Mpression by Macnica Group Mpression Beryll Board ESSION Solutions by Macnica Group 5 9 10 100 1000 Ethernet The Beryll Board has DP83865DVH manufactured by Texas Instruments Inc for Ethernet interface Texas Instruments DP83865DVH is an ultra low power consumption transceiver for Ethernet interface using a 1 8 V 0 18 p process For pin information of the FPGA and DP83865DVH see Figure 10 and the pin assignment list shown below The data sheet for this LSI can be obtained from the following URL http www ti com product dp83865 Note The URL above is subject to change without notice lt TSE MAC TSE GTX CLK E TSE TX D 3 0 TSE TX EN JNO RYA 2 TSE RX D 3 0 TSE_RX_DV lt TSE_RX_CLK TSE_INTERRUPT_N DP83865DVH 5 MDC TSE MDIO TSE RESET N Figure 10 Connection of the FPGA and DP83865DVH Table 9 Pin Assignment list of the FPGA and DP83865DVH FPGA Pin DP83865 Pin Number Number E 80 Signal Name Mpression by Macnica Group Reference Manual Mpression Beryll Board ESSION Mpression Beryll Board Solutions by Macnica Group 5 10 24 bit Audio Codec The Beryll Board has UDA1345TS manufactured by NXP Semiconductors N V for 24 bit CODEC for audio interface For pin information of the FPGA and UDA1845TS see Figure 11 and the pin assignment list shown below The data sheet for
23. g electrical shock Do not place this Board in locations where excessive force is applied to the Board Failure to do so may cause the PC board to warp leading to breakage of the PC board missing parts or malfunctioning parts Mpression by Macnica Group Reference Manual Mpression Beryll Board o ESSION Mpression Beryll Board Solutions by Macnica Group When using the kit together with expansion boards or other peripheral devices be sure to carefully read each of their manuals and to use them correctly Developer does not guarantee the operation of specific expansion boards or peripheral devices when used in conjunction with this Board unless they are specifically mentioned in this Manual or their successful operation with this Board has been confirmed in separate documents Be sure to turn off the power switch when moving this Board to connect to other Caution devices Failure to do so may cause this Board to fail or lead to accidents involving electrical shock Continued from Do not clean this Board by using a rag containing chemicals such as benzine or previous page x 4 thinner Failure to do so will likely to cause this Board to deteriorate When using a chemical cloth be sure to comply with any directions or warnings Do not immediately turn on the power if you find that water or moisture had condensed onto the main unit after removing the board from the package Condensati
24. gh the contact form in the following web site http www m pression com contact Macnica companies China amp HK Cytech Technology http www cytech com e ASEAN amp India Cytech Global http www cytechglobal com Taiwan Galaxy Far East Corp http www gfec com tw North America Maenica Americas http www macnica na com Brazil Macnica DHW http www macnicadhw com br en Japan Altima http www altima co jp Elsena http www elsena co jp Mpression by Macnica Group Reference Manual Mpression Beryll Board o ESSION Mpression Beryll Board Solutions by Macnica Group 2 Important Information READ FIRST e READ this Reference Manual before using this product KEEPthe Reference Manual handy for future reference Do not attemptto use the product until you fully understand its mechanism Purpose of the Product This product is the Beryll Board its purpose is to support the evaluation of a system that uses the Cyclone V GX FPGA manufactured by Altera Corporation It provides support for system development in both software and hardware For Users of This Product This product can only be used by operators who have carefully read the user s manual and understand how to use it Use of this product requires a basic knowledge of electric circuits logic circuits and FPGAs Precautions to be taken when using This Product This product is an evaluation supporting board fo
25. he FPGA This section introduces the basic operations for programming A Starting Programmer Connect the programming hardware and then select the Tools Menu in Quartus II and then Programmer or click the button B Selecting a programming mode From the Mode pull down list select a method for writing the programming file into the device Select J TAG for the Beryll Board C Setting the programming hardware a Click the Hardware Setup button b Select the Hardware Settings tab in the Hardware Setup window Reference Manual Mpression Beryll Board Mpression by Macnica Group Mpression Beryll Board ESSION Solutions by Macnica Group c From the Current selected hardware pull down list select the programming hardware to be used Move on to step If there is no programming hardware to use in the pull down list click the Add Hardware button d Select USB Blaster from Hardware type in the Add Hardware dialog box and click the OK button e Select USB Blaster from Currently selected hardware in the Hardware Setup window and click the Close button D Programming a Click the AddFie button to select a programming file SOF to write into the device b To write data into the device check the Program Configure box as a programming option c Click the Stat button to start programming Reference information POF file pof Programming file for the MAX CPLD series and configuration devic
26. lly or partially specifications design reference manual and other documentation at any time without notice Warranty Altima Corp offers exchange of this product free of charge only in a set range of cases of initial trouble for this product and within 30 days from when the customer received delivery of the Board Reference Manual Mpression Beryll Board Mpression by Macnica Group Mpression Beryll Board ESSION Solutions by Macnica Group Altima Corp cannot exchange products in cases where breakdown is caused for the following reasons 1 Misuse abuse of the product or use under abnormal conditions 2 Remodeling and repair 3 A fire earthquake fall or other accidents Figures Some figures in this reference manual may differ from your system as purchased Mpression by Macnica Group Reference Manual Mpression Beryll Board ESSION Solutions by Macnica Group 3 Unboxing Package Components Mpression Beryll Board This product consists of the Board and the parts listed in the table below Please make sure all components listed below are included as soon as you get the Board Customer letter The Beryll Board USB Standard A to Mini B plug cable AC adaptor Output 12 V 3 8 A Reference Manual Download these files from the web The Beryll Board circuit diagram site given in the customer letter FPGA sample design Reference Manual Mpression Beryll
27. n Number Pin Number R8 O _DQ15 _DQ16 DDR3ADDRIO aco y 7 facis 2 DDR3_ADDR11_ AC8 R7 R7 DDR3 DQ19 AF19 DDR3 ADDRI2 AB10o N7 5 DDR3 BAO V10 M2 M2 DDR3 DQ21 ABIT Oo H8 DDR3 BAI ans 8 486 DRA DQ2 farr 02 DDR3_BA2 ms Ms bpgRs Qe 7 DMO ari 7 DDR poa fars 3 farms DDR3 DM2 AE20 E7 JACO p fanai ui 2 farie Ja DDR3 DQ29 2 DDR3 Daso BS DDR3 WEN ro 8 8 pors pesi fars Aa O DDR3 RESETN Ar19 r 2 pors pasri 7 DDR3 JDDR3DQS NL DDR3 DQO 8 8 yu JppgpqsNo 3 Jani qv DQ3 ap2 1 DDR3 004 ys 8 s DDR3 DQ5 wi2n Ms RB DQSNO le DDR3 DQ6 0 2 h O pq ar 7 K KT ___ ___ DDR amp CKE KOK 9F7 ACE8 ED039D2582D6 Note The URL above is subject to change without notice The data sheet for the SRAM can be obtained from the following URL http ja 1dt com products memory logic srams asynchronous srams 71v416 33v 256k x 16
28. nd ordinances governing waste disposal Do not use the kit in places subject to extremely high or low temperatures or severe temperature changes Doing so may cause the kit to fail or to malfunction Always be sure to use the kit in a temperatures ranging from 5 C to 35 C and a humidity range of 0 to 8596 Reference Manual Mpression Beryll Board Mpression by Macnica Group Mpression Beryll Board ESSION Solutions by Macnica Group Do not pull the power supply cable with excessive force or place heavy items on it Do not damage break bundle or tamper with the power supply cable Damaged parts of the power supply cable might cause a short circuit resulting in fire or accidents involving electrical shock Do not unplug the power plug with wet or moist hands This might cause injuries or equipment malfunctions or failures due to electrical shock Plug the power plug securely into the outlet If the power plug is not securely plugged into the outlet it may cause accidents involving electrical shock or fire due to heat emitted Do not connect many electrical cords to a single socket or connect an AC adapter to an outlet that is not rated for the specified voltage Warning Failing to do so may cause the equipment to malfunction or fail or lead to Continued from x 7 4 accidents involving electrical shock or fire due to heat emitted previous page Periodically remove any dust ac
29. on might occur on this Board when taking it out of the box if the board is cool yet the room temperature is warm Do not apply power to the Board while water or moisture has condensed on it because the moisture may cause the Board to break or may shorten the service life of the parts When you first take this Board out of the box be sure to leave it at room temperature for a while before using it If condensation or moisture has occurred on this Board first wait for the moisture to fully evaporate before installing or connecting the Board to other devices Do not disassemble dismantle modify alter or recycle parts unless they are clearly described as customizable in this Manual Although this kit is customizable if parts not specified in this Manual as customizable are modified in any way then the overall product operation cannot be guaranteed Please consult with developer beforehand if you wish to customize or modify any parts that are not described in this Manual as customizable 1 3 Developer Information The Developer of this product is Altima Corp 1 5 5 Shin Yokohama Kouhoku ku Yokohama 222 8563 JAPAN http www altima co jp Reference Manual Mpression Beryll Board Mpression by Macnica Group Mpression Beryll Board ESSION Solutions by Macnica Group 1 4 Inquires In case you have any inquiries about the use this product please contact your local Macnica company or make inquiries throu
30. ons by Macnica Group 4 4 3 Beryll Switch LED Layout and Specifications Figure 4 shows the locations of switches and LEDs on the Beryll Board FPGA_Reconfig Dedicated Push SW D3 D22 D4 D5 D6 D7 Ethernet LEDs x5 ENET_DIPSW DIP SW x2 for Ethernet CPU_RESETn General Push SW AUDIO_DIPSW DIP SW x2 for Audio D1 D2 D3 D22 FPGA LEDs Figure 4 Positions of the Switches and LEDs Table 2 shows the functions of the LEDs Table 2 LED function specifications Function LED for checking FPGA CONF DONE LK100 LED for checking link in 100 Mbps communication LK1000 LED for checking link in 1 Gbps communication DUPLEX LED for checking full duplex communication Reference Manual Mpression Beryll Board Mpression by Macnica Group Mpression Beryll Board pression Solutions by Macnica Group Table 3 shows the functions of the switches Table 3 shows the functions of the switches Component Location Default Function POWER SW Slide Down i Sli Power CRS RGMITI_SELO Open RGMII 3COM Short RGMII HP ENET DIPSW Both OPEN COL CLK MAC FREQ Open 125MHz output Short 25MHz output AUDIO MP2 Open StaticPin Low or FPGA Control AUDIO DIPSW Both OPEN Short StaticPin and Mid Voltage AUDIO MP4 nen Pin High D A Qn Q DIP_SW Audio Setting DIP SWs x4 PU_RESETn PBO PB1 P General purpose Push SW FPGA Reconfig FPGA Reconfiguration Push SW
31. r use in your program development and evaluation stages When mass producing a program you have finished developing be sure to decide at your own responsibility whether it can be put to practical use by performing integration test evaluation or some other experiment nno event shall Altima Corp be liable for any consequence arising from the use of this product Altima Corp cannot anticipate every possible circumstance that might involve a potential hazard The warnings in this reference manual and on the product are therefore not all inclusive The user is therefore responsible for the safe use of the product at the user s own responsibility This product is to be used for evaluation of a program and the evaluation stage You cannot install the Beryll Board in your product and cannot use the Beryll Board for mass production The operation of any specific USB memories or SD cards cannot be guaranteed Connection with the apparatus of any specific LAN interfaces cannot be guaranteed This product does not guarantee device functionality Remodeling by the customer 1s not guaranteed This product is a lead free mounting product Generally the brand names carried in this reference manual each constitute a maker s trademark or registered trademark Improvement Policy Altima Corp pursues a policy of continuous improvement in design performance and safety of the product Altima Corp reserves the right to change who
32. rious injury Indicates potentially hazardous situation which if not avoided could result in A Warning death or serious injury Indicates a potentially hazardous situation which if not avoided may result in Caution minor or moderate injury or in property damage 1 2 Cautions Make sure to use the AC adapter included in package that is specified in this Manual Danger TM peace wile Using an AC adapter not meeting the specifications described in this Manual will cause the kit to emit heat explode or ignite Do not apply strong impacts or blows to the kit Doing so may cause the kit to emit heat explode or ignite or the equipment in the kit to fail or malfunction This may also cause fire Do not put the main unit or the AC adapter in cooking appliances such as microwave ovens or high pressure containers Doing so might cause the main unit or AC adapter to emit heat explode ignite or emit smoke or its parts to break or warp Do not wrap the main unit that is in use with cloth or other materials that are likely to allow heat to build up inside the wrapping This will cause heat to build up inside the wrapping which may cause the main unit to ignite or malfunction AN Wa rning When disposing of the main unit do not dispose of it along with general household waste Throwing the main unit into fire may cause it to explode Dispose of the main unit following the laws regulations a
33. ument Revision History Revision Changes February 2014 Document created Reference Manual Mpression Beryll Board Mpression by Macnica Group
34. y Figure 12 shows the tree diagram of the power supply for the Beryll Board LT3022 18 08A Osc Ether LTC3605 lt HSMC 12V DC CY t 12 1 0A 12V 0 2A HSMG 36W 14V 1 5A FPGA VINT wrC3633 3 3V 1 85 FPGA 1 0 1 0A LT3022 2 5V 1 0A 0 75A LT3022 1 5V 0 754 FPGA V 33V 1 2A 0 9A LTC3633 1 8A 7 2 5V 0 5 Ether RS232C LEVIA DDR3 1 3 763618 0 75V 0 5 DDR3 VTT Figure 12 Beryll Power Tree IN Reference Manual Mpression Beryll Board Mpression by Macnica Group Mpression Beryll Board ESSION Solutions by Macnica Group 6 Operating Precautions 6 1 Mode Selection for Unused Pins This section describes how to handle the pins which are not used on the hardware design unused pins When using the Beryll Board the unused pins must be set to the tri stated mode Follow the steps below to make the necessary setting for the unused pins in Quartus II 1 Select the Assignments menu and then Device 2 Click the Device amp Pin Options button The Device amp Pin Options window appears 3 Select the Unused Pins tab 4 From the Reserve all unused pins item select As input tri stated 5 Click the OK button 6 Click the OK button to close the Device amp Pin Options window Mpression by Macnica Group Reference Manual Mpression Beryll Board pression Mpression Beryll Board Solutions by Macnica Group 7 Doc
35. y Macnica Group 5 12 Clock Circuitry This section describes the board s clock inputs and outputs 5 12 1 On board clock source The Beryll Board includes clock sources for Cyclone V GX FPGA with a frequency of 27 MHz 33MHz 50 MHz and 125 MHz Figure 12 shows the default frequencies of all external clocks going to the Beryll Board HSMC From BANK 8A gt GAN From BANK 8A SMA CLK IN From BANK 7A CLKIN2 CLKOUT2 fe From BANK 7A Fiat s 5 From BANK 7A CLKIN3 CLKOUT3 From BANK 7A e NEA N Bank Bank 7A Cyclone V GX FPGA Fixed OSC 100M Bank Bank 38 Fixed OSC Fixed OSC gt gt Fixed OSC 33M 125M 50M Figure 12 Beryll Board Clocks Reference Manual Mpression Beryll Board Mpression by Macnica Group pression Beryll Board pression Solutions by Macnica Group Table 12 lists the clock sources the relevant I O standard and voltages required for the Beryll Board Table 12 On board clock sources Source Frequency V O Standard ra qund Description Signal Name Pin Number U7 CLK27M 27 MHz 3 3V T21 User us CLK33M 33 MHz 1 8V T13 User U10 CLK50M 50 MHz 1 8 U12 User U11 CLK125M 125 MHz 1 8V P11 User DIFFO P 100 MHz LVDS V6 Transceiver reference DIFFO N 100 MHz LVDS W6 Transceiver reference Uta TSE MAC CLK 25 MHz 3 3V N20 Ethernet PHY TSE RX CLK 25 MHz 3 3V R20 Ethernet PHY U22 EZ CLK
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