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Integrated Device Technology TSI578-10GIL Datasheet

1. T51578 reset value is 0x0000 A 2 3 9 I2C Boot and Diagnostic Timer The I2C Boot and Diagnostic Timer programs a timer used to timeout the boot load sequence and can be used after boot load as a general purpose timer COUNT Count for Timer Period The COUNT field defines the period for the timer The initial reset value is used for overall boot load timeout A value of 0 disables the timeout During normal operation this timer can be used for any general purpose timing AN The timer begins counting when this register is written If this register is written while the counter is running the timer is immediately restarted with the new COUNT and the DTIMER BLTO event is not generated When the timer expires either the BLTO or DTIMER event is generated depending on whether the boot load sequence is active If FREERUN is set to 1 when timer expires then the timer is restarted immediately the event is still generated providing a periodic interrupt capability Period DTIMER COUNT Period MSDIV Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 82 A 2 4 A 2 4 1 A Clocking MSDIV is the millisecond period define in I2C Time PeriodDivider Register The reset value for the boot load timeout is four seconds If the boot load completes before the timer expires the timer is set to zero disabled Tsi578 reset value is OXOFAO Other Performance Fact
2. Ensure that the wave front does not propagate along the trace and through the crosstalk path perpendicular to the parallel sections as shown in Figure 19 The arrival of a wave front at the receiver ahead of the wave front travelling along the serpentine route is caused by the self coupling between the parallel sections of the transmission line Lp Figure 19 Serpentine Signal Routing 3 3 2 A To maximize the signal integrity clock lines should not be serpentine Figure 22 describes the guidelines for length matching a differential pair If it is necessary to serpentine a trace follow these guidelines e Make the minimum spacing between parallel sections of the serpentine trace see S in Figure 19 at least 3 to 4 times the distance between the signal conductor and the reference ground plane e Minimize the total length see Lp in Figure 19 of the serpentine section in order to minimize the amount of coupling e Use an embedded microstrip or stripline layout instead of a microstrip layout 7 For a detailed discussion about serpentine layouts refer to Section 12 8 5 of ae High Speed Signal Propagation Advanced Black Magic by Howard Johnson and Martin Graham Crosstalk Considerations The Serial RapidIO signals easily capacitively couple to adjacent signals due to their high frequency It is therefore recommended that adequate space be used between different differential pairs and that channel transmit and
3. Reset time is 4 71 microseconds Tsi578 reset value is 0x01D7 A 2 3 7 I2C_SCLK Low and Arbitration Timeout Register The I2C_SCLK Low and Arbitration Timeout Register programs the I2C_SCLK low timeout and the Arbitration timeout The arbitration timer period is relative to the MSDIV period and the I2C_SCLK low timeout period is relative to the USDIV period SCL TO Count for I2C SCLK Low Timeout Period The SCL TO field defines the maximum amount of time for a slave device holding the I2C SCLK signal low This timeout covers the period from I2C SCLK falling edge to the next I2C_SCLK rising edge A value of 0 disables the timeout e Period SCL TO SCL TO Period USDIV USDIV is the microsecond time defined in the I2C Time Period Divider Register The reset value of this timeout is 26 milliseconds Tsi578 reset value is OX65BB ARB TO Count for Arbitration Timeout Period The ARB TO field defines the maximum amount of time for the master interface to arbitrate for the bus before aborting the transaction This timeout covers the period from master operation start see setting the START bit in the I2C Master Control Register until the ACK NACK is received from the external slave for the slave device address A value of 0 disables the timeout e Period ARB TO ARB_TO Period MSDIV MSDIV is the millisecond time defined in I2C Time Period Divider Register The reset value of this timeout i
4. SILENCE TIMER EN to be deasserted When the state machine is not in the SILENT state SILENCE TIMER DONE is deasserted Tundra Implementation The Ts1578 s silence timer does not have user programmable registers The silence timer is sourced from the P CLK and any changes to P CLK are directly reflected in the timer timeout period Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 72 A Clocking DISCOVERY_TIMER_DONE The RapidIO Interconnect Specification Revision 1 3 defines the DISCOVERY_TIMER_DONE as follows Asserted when DISCOVERY TIMER EN has been continuously asserted for 12 4msec and the state machine is in the DISCOVERY state The assertion of DISCOVERY TIMER DONE causes DISCOVERY TIMER EN to be deasserted When the state machine is not in the DISCOVERY state DISCOVERY TIMER DONE is deasserted Tundra Implementation The Ts1578 s discovery timer is programmed in the RIO Port x Discovery Timer on page 322 The DISCOVERY TIMER field is used by serial ports configured to operate in 4x mode The DISCOVERY TIMER allows time for the link partner to enter its discovery state and if the link partner supports 4x mode for all four lanes to be aligned The DISCOVERY TIMER field is a 4 bit field whose value is used as a pre scaler for a 17 bit counter clocked by P CLK The DISCOVERY TIMER has a default value of 9 decimal but can be programmed to various values The results of
5. 1 1 25 MHz 327 uS 8192 32767 1 25 MHz 10 74 seconds Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 76 A Clocking A 2 3 C interface and Timers The PC interface clock is derived from the P CLK Decreasing the frequency of P_CLK causes a proportional decrease in the PC serial clock and affects the I7C timers The timer values can be re programmed during boot loading but the changes does not take effect until after the boot load has completed As a result a decrease from 100 Mhz to 50 Mhz of P_CLK causes a doubling of the boot load time of the EEPROM Once boot loading has completed the new values take effect and the PC interface can operate at the optimum rate of the attached devices A 2 3 1 IC Time Period Divider Register The I2C Time Period Divider Register This register provides programmable extension of the reference clock period into longer periods used by the timeout and idle detect timers USDIV Period Divider for Micro Second Based Timers The USDIV field divides the reference clock down for use by the Idle Detect Timer the Byte Timeout Timer the I2C_SCLK Low Timeout Timer and the Milli Second Period Divider e Period USDIV Period P_CLK USDIV 1 e P CLKis 10 ns 751578 reset value is 0x0063 MSDIV Period Divider for Milli Second Based Timers The MSDIV field divides the USDIV period down further for use by the Arbitration Timeout Timer the Transaction Timeout Timer and
6. 1 3 3V supply for bias generator Refer to Decoupling circuitry This is required to be a low noise supply Requirements on page 57 REF_AVDD Refer to Decoupling Requirements on page 57 Common Supply Tsi578 Hardware Manual 80B803A MAO02 07 VDD IO Common 3 3V supply for CMOS I O Refer to Decoupling Requirements on page 57 VSS IO Common ground supply for I Os Refer to Decoupling Requirements on page 57 Tundra Semiconductor Corporation www tundra com 1 Signals and Package Table 2 Signal Descriptions and Recommended Termination 21 Recommended Pin Name Type Description Termination VSS Common ground supply for digital logic Refer to Decoupling Requirements on page 57 VDD E Common 1 2V supply for digital logic Refer to Decoupling Requirements on page 57 SP_VDD i 1 2V supply for CDR Tx Rx and digital logic for Refer to Decoupling all RapidlO ports Requirements on page 57 a Signals for unused serial ports do not require termination and can be left as N Cs Tundra Semiconductor Corporation www tundra com Tsi578 Hardware Manual 80B803A_MA002_07 22 1 Signals and Package 1 3 Package Characteristics The Tsi578 s package characteristics are summarized in the following table Figure 1 and Figure 2 illustrates the Top and Side views of the Tsi578 package Figure 3 represents the Bottom view of the d
7. 2 1 Absolute Maximum Ratings esee e eee nes 29 2 0 Recommended Operating Conditions l leere 30 2 3 JPOWOE v eoe ee Sue ewes a aa Gaede each obs owas edd ese CR HUP due 32 2 4 Electrical Characteristics setesi isoce Oe er RUE e eoe Res ab eee 35 4 Layout Guidellhes iius ca ea hax ees mda RR E RE E RO dues dao Ur RR ca 43 S OVERVIEW seirian ER DUCES eee ci be de n eene e eed ed d drea A ee ERR EA GER S 43 3 2 Impedance Requirements 0 0 0 0 cece ccc m 43 3 3 Tracking Fopologiesiu s Eam ae ee Rec n 8 RD Mec x had ec D und e Reto E A 44 3 4 Power Distribution llseeeeeeeeeee ehh hh 56 3 5 Decoupling Requirements 0 0 niies eti net I n 57 3 6 locking and Reset ee er Re c oe ve Pee Oe ace ted b ar 61 3 7 Modeling and Simulation 1 0 0 0 0 ehh 65 3 8 Testing and Debugging Considerations 0 00 0 eect teen eens 66 3 9 Reflow Profile 52e bc ok oa baw seats ea o e OOo ae gee a aed ane woes 68 A Clocking iai se backea e acido cease nerro Ra dO UU ot C QC waren ee 69 A l Lane Rate Support esee e ah eda ape cea d s dale Pea Su e e a e e E 69 A P CLK Programming sea eds et s hb ea ae Car OX EE eae DAR Cure ee ale 70 B Ordering Information iusaseesucscesukakua das aAA ReRadaa Kudai 83 B 1 Ordering Information lsseleleeeee I n 83 B 2 Part Numbering Information leleleeeeee s 83 Tundra Semiconductor Corporation www tundra com Tsi578 Hardware Manual 80B8
8. HyperLynx GHZ Ansoft SIwave and SiSoft SiAuditor This is by no means a complete list only a sample of known suppliers 3 7 1 IBIS The use of IBIS for signal integrity checking at the high frequencies of the Serial RapidIO link have been found to be too inaccurate to be useful Also we have found that most tools do not yet support the JBIS Specification Revision 3 2 for the support of multi staged slew rate controlled buffers Tundra is making available an IBIS file which supports the LVTTL pins on the device Please contact Tundra Applications Engineering to obtain the file 3 7 2 Encrypted HSPICE Please contact the Tundra Applications Engineering through the web based form at www tundra com support to request the necessary Model License Agreement form required to acquire the encrypted model Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 66 3 8 3 Layout Guidelines Testing and Debugging Considerations It is prudent to make provision for debugging and testing tools in order to speed board bring up This section provides information on the probing requirements for monitoring the serial RapidIO link between two devices At GHz frequencies standard probing techniques are intrusive and cause excessive signal degradation introducing additional errors in the link stream The recommended solution is an ultra low capacitance probe that operates in conjunction with a logic analyzer The
9. Tj is Junction Temperature P is the Power consumption Tamb is the Ambient Temperature Assuming a power consumption P of 3 5 W and an ambient temperature Tamb of 70 C the resulting junction temperature Tj would be 121 1 C Heatsink Requirement and Analysis The Tsi578 is packaged in a Flip Chip Ball Grid Array FCBGA With this package technology the silicon die is exposed and serves as the interface between package and heatsink Where a heatsink is required to maintain junction temperatures at or below specified maximum values it is important that attachment techniques and thermal requirements be critically analyzed to ensure reliability of this interface Factors to be considered include surface preparations selection of thermal interface materials curing process shock and vibration requirements and thermal expansion coefficients among others Each design should be individually analyzed to ensure that a reliable thermal solution is achieved Tundra makes no recommendations as to the reliability or effectiveness of either approach The designer must critically analyze heatsink requirements selection criteria and attachment techniques Both mechanical and adhesive techniques are available for heatsink attachment Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com 1 Signals and Package 27 1 4 2 1 Heatsink Attachment Both mechanical and adhesive techniques are available for heats
10. 100 MHZ S_CLK_p l Differential non inverting reference clock The AC coupling capacitor of CML clock is used for following purposes SERDES 0 1uF required Tsi578 Hardware Manual 80B803A_MA002_07 Tundra Semiconductor Corporation www tundra com 1 Signals and Package Table 2 Signal Descriptions and Recommended Termination 17 Recommended Pin Name Type Description Termination S_CLK_n l Differential inverting reference clock The clock is AC coupling capacitor of CML used for following purposes SerDes reference 0 1uF required clock serial port system clock ISF clock and test clock The clock frequency is defined in the Minimum Clock Frequency Requirements section The maximum frequency of this input clock is 156 25 MHZ HARD_RST_b l Schmidt triggered hard reset Asynchronous Connect to a power up LVTTL active low reset for the entire device reset source See Reset Hyst The Tsi578 does not contain a voltage detector to Requirements on page 64 PU generate internal reset for more detail INT_b SW_RST_b Miscellaneous O OD LVTTL 2mA O OD LVTTL 2mA Interrupt signal open drain output Software reset open drain output This signal is asserted when a RapidlO port receives a valid reset request on a RapidlO link If self reset is not selected this pin remains asserted until the reset request is cleared from the status registers If self reset is selected th
11. 3 3 12C Stop Idle Timing Register The I2C Stop Idle Timing Register programs the setup timing for the Stop condition when generated by the master control logic and the Idle Detect timer The START SETUP time doubles as the Stop Hold AN The Stop Idle register is broken down as follows e The timer period for the STOP SETUP is relative to the reference clock e The timer period for the Idle Detect is relative to the USDIV period e The STOP SETUP time is shadowed during boot loading and can be reprogrammed prior to a chain operation without affecting the bus timing for the current EEPROM STOP SETUP Count for STOP Condition Setup Period The STOP SETUP field defines the minimum setup time for the STOP condition that is both I2C SCLK seen high and I2C_SD seen low prior to I2C SD released high This is a master only timing parameter e PeriodSTOP SETUP STOP SETUP Period P CLK P CLK is 10ns Reset time is 4 01 microseconds Tsi578 reset value is 0x0191 Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 78 A 2 3 4 A Clocking IDLE DET Count for Idle Detect Period The IDLE DET field is used in two cases First it defines the period after reset during which the I2C SCLK signal must be seen high in order to call the bus idle This period is needed to avoid interfering with an ongoing transaction after reset Second it defines the period before a master transac
12. 38 Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com 3 Layout Guidelines 63 3 6 1 2 Stability Jitter and Noise Content The maximum input jitter on the S_CLK input is 3pS RMS from 1 5 to 10 Mhz to avoid passing through the PLL loop filter in the SerDes and affecting the transmit data streams The maximum input jitter allowable on the P_CLK input is 300 pSpp Jitter on this input would be reflected outside of the chip on the PC bus For more information refer to Figure 4 on page 38 Jitter Equation The following equation can be used to convert Phase Noise in dBc to RMS jitter RMSjitter pS rms Kao 10 1 2 2 2 pi frequency in hz Using this equation an example of 312 5 MHz and a phase noise of 63dBc would produce 0 72pS RMS jitter 3 6 2 Clock Domains Table 18 Tsi578 Clock Domains Internal Register Domain This clock domain includes all of the internal registers and their interconnect bus The domain uses the input P_CLK directly Internal Switching Fabric S CLK p n This clock domain includes the switching matrix of the ISF and Domain the portion of each RapidlO block that interfaces to the ISF IC Domain P CLK divided by 1000 This clock domain is responsible for driving the l2C output clock pin l2C SCLK This clock domain is generated by dividing the P CLK input by 1000 The majority of the I2C logic runs in the Internal Register Domain Serial Transmit D
13. 80B803A MAO002 07 30 2 Electrical Characteristics Table 6 Absolute Maximum Ratings Symbol Parameter pmax LVTTL Output or VO Voltage m V Vesp HBM Maximum ESD Voltage Discharge Tolerance 2000 for Human Body Model HBM Test Conditions per JEDEC standard JESD22 A114 B VEsD CDM Maximum ESD Voltage Discharge Tolerance 500 V for Charged Device Model CDM Test Conditions per JEDEC standard JESD22 C101 A 2 2 Recommended Operating Conditions Table 7 lists the recommended operating conditions the current values provided are maximum Continued exposure of Tundra s devices to the maximum limits of the specified N junction temperature could affect the device reliability Subjecting the devices to temperatures beyond the maximum minimum limits could result in a permanent failure of the device Table 7 Recommended Operating Conditions Vpp SP VDD REF AVDD Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com 2 Electrical Characteristics 31 Table 7 Recommended Operating Conditions Vripplet Power Supply ripple for Voltage Supplies SP_VDD VDD and VDD IO Vripple2 on Supply ripple for Voltage Supplies _AVDD REF_AVDD External reference resistor current a The current values provided are maximum values and dependent on device configuration such as port usage traffic etc Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 0
14. Lane C Differential Inverting Receive Data DC blocking capacitor of input 4x mode 0 1uF in series SP n RD p I SRIO Port n Lane D Differential Non inverting Receive DC blocking capacitor of Data input 4x mode 0 1uF in series SP n _ RD n I SRIO Port n Lane D Differential Inverting Receive Data DC blocking capacitor of input 4x mode 0 1uF in series Serial Port n n 1 Configuration n 0 2 4 6 8 10 12 14 SP n _ REXT Used to connect a 190Q 1 resistor to VSS to provide a reference current for the driver and equalization circuits Series resistor of 191 196 connected to VSS SP n MODESEL SP n _ PWRDN I O LVTTL PD I O LVTTL PU Selects the serial port operating mode for ports n and n 1 0 Port n operating in 4x mode Port n 1 not available 1 Ports n and n 1 operating in 1x mode Note Output capability of this pin is only used in test mode Must remain stable for 10 P_CLK cycles after HW_RST_B is de asserted in order to be sampled correctly Ignored after reset Port n Transmit and Receive Power Down control This signal controls the state of Port n and Port n 1 The PWRDN controls the state of all four lanes A B C D of SERDES Macro 0 Port n Powered Up Port n 1 controlled by SP n 1 _ PWRDN 1 Port n Powered Down Port n 1 Powered Down Override SP n _ PWRDN using PWDN x1 field in SRIO MAC x Clock Selection Register in the Tsi5
15. Notation Differential signals consist of pairs of complement positive and negative signals that are measured at the same time to determine a signal s active or inactive state they are denoted by _p and n respectively The following table illustrates the differential signal naming convention state Single line signal Multi line signal Inactive NAME_p 0 NAME p 3 0 NAME n 1 NAME n 3 71 Active NAME p 1 NAME pj3 is 1 NAME n 0 NAME n 3 is 0 Symbols 7 This symbol indicates a basic design concept or information considered helpful AR AN amp This symbol indicates important configuration information or suggestions This symbol indicates procedures or operating levels that may result in misuse or damage to the device Tsi578 Serial RapidlO Switch Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com Revision History 80B803A_MA002_07 Final November 2007 This is the production version of the 7si578 Serial RapidIO Switch Hardware Manual The key changes include clarification to the following areas e Information on P_CLK Programming on page 70 was added to Clocking on page 69 e General clarification in Signals and Package on page 11 including Any unused signal that is designated a No Connect N C must be left unconnected The DC SCLK signal description was updated The BCE signal description was updated 80B803A MAOO02 06 Final August 2007 T
16. Thks n L01 N oP eM alo Ua Olo Wla Oa O a Lo2 Lo3 L04 LoS Lo6 o o No N ARK N OO Lo Los Log L10 1 2 L11 0 6 L12 1 2 L13 0 6 L14 1 2 L15 1 2 L16 0 6 Total 88 Finish thickness over laminate 10 5 92 Finish thickness over plating 70 Tundra Semiconductor Corporation www tundra com Layer Definition PRI pwr gnd sig gnd sig gnd sig sig gnd sig gnd sig gnd pwr sec 50 0 2 50 0 2 50 0 22 50 0 2 50 0 2 50 0 2 4line6sp 100 0 2 4line6sp 100 0 2 eine 3535 with TETTI 20pad dovm traces ejje EFT ES 4orS 45 4line6sp 100 0 4line6sp 100 0 Q Tsi578 Hardware Manual 80B803A_MA002_07 56 3 4 3 Layout Guidelines Power Distribution The Tsi578 is a high speed device with both digital and analogue components in its design The core logic has a high threshold of noise sensitivity within its 1 2 V operating range However the analogue portion of the switch is considerably more sensitive The correct treatment of the power rails plane assignments and decoupling is important to maximize Tsi578 performance The largest indicator of poor performance on the Serial RapidIO interfaces is the presence of jitter The die I O and package designs have all been optimized to provide jitter performance well below the limits required by the Serial RapidIO specifications The guidelines provided below will assist the user in achieving a bo
17. as an I C slave Pull up to VDD IO through The values at these pins can be overridden by 10K resistor if external software after reset pull up is desired Pull down to VSS_IO to change the logic state I2C_SEL CMOS C Pin Select Together with the I2C SA 1 0 No termination required PU pins Tsi578 will determine the lower 2 bits of the Internal pull up may be 7 bit address of the EEPROM address it boots from When asserted the I2C_SA 1 0 values will also be used as the lower 2 bits of the EEPROM address When de asserted the I2C SA 1 0 pins will be ignored and the lower 2 bits of the EEPROM address are default to 00 The values of the lower 2 bits of the EEPROM address can be over ridden by software after reset JTAG TAP Controller used for logic 1 Pull up to VDD IO through 10K resistor if external pull up is desired Pull down to VSS IO to change the logic state TCK LVTTL IEEE 1149 1 Test Access Port Pull up to VDD IO through PD Clock input 10K if not used TDI LVTTL IEEE 1149 1 Test Access Port Pull up to VDD IO through PU Serial Data Input 10K if not used or if higher edge rate is required TDO O IEEE 1149 1 Test Access Port No connect if JTAG is not LVTTL Serial Data Output used Pull up to VDD IO 2mA through 10K if used TMS LVTTL IEEE 1149 1 Test Access Port Pull up to VDD IO through PU Test Mode Select 10K if not used Tundra Semiconductor
18. e Modeling and Simulation on page 65 e Testing and Debugging Considerations on page 66 e Reflow Profile on page 68 Overview The successful implementation of a Tsi578 in a board design is dependent on properly routing the Serial RapidIO signals and maintaining good signal integrity with a resultant low bit error rate The sections that follow contain information for the user on principals that will maximize the signal quality of the links Since every situation is different Tundra urges the designer to model and simulate their board layout and verify that the layout topologies chosen will provide the performance required of the product Impedance Requirements The impedance requirement of the Serial RapidIO interface is 100 ohms differential Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 44 3 Layout Guidelines 3 3 Tracking Topologies The tracking topologies required to maintain a consistent differential impedance of 100 ohms to the signal placed on the transmission line are limited to Stripline and Microstrip types The designer must decide whether the signalling must be moved to an outer layer of the board using a Microstrip topology or if the signalling may be placed on an inner layer as stripline where shielding by ground and power planes above and below is possible In order to prevent consuming received eye margin the track skew of a lane should be constrained to
19. operating frequency numbers M and G represent MHz and GHz For transfer rate numbers M and G represent Mbps and Gbps Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 84 B Ordering Information e E Operating environment in which the product is guaranteed This code may be one of the following characters C Commercial temperature range 0 to 70 C I Industrial temperature range 40 to 85 C E Extended temperature range 55 to 125 C e P The Package type of the product B Ceramic ball grid array CBGA E L J and K Plastic ball grid array PBGA G Ceramic pin grid array CPGA M Small outline integrated circuit SOIC Q Plastic quad flatpack e G Tundra products fit into three RoHS compliance categories Y RoHS Compliant 60f6 These products contain none of the six restricted substances above the limits set in the EU Directive 2002 95 EC Y RoHS Compliant Flip Chip These products contain only one of the six restricted substances Lead Pb These flip chip products are RoHS compliant through the Lead exemption for Flip Chip technology Commission Decision 2005 747 EC which allows Lead in solders to complete a viable electrical connection between semiconductor die and carrier within integrated circuit Flip Chip packages V RoHS Compliant Green These products follow the above definitions for RoHS Compliance
20. the SPn_AVDD signal Figure 26 Analog Resistor NOTE Place Discretes as close to Ul as possible POP RESERVED In this design Vtt can be controlled to be between 1 2 V and 3 3 V For the Tsi578 operation Vtt is set to be 3 3V which provides the required voltage for SPx_AVDD Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com 3 Layout Guidelines 59 Table 16 Decoupling Capacitor Quantities and Values Recommended for the Tsi578 Voltage Ecl MEI Component Requirements Logic Core VbD 20x0 1uF 20x 0 01uF 16x tnF 16x 22uF SerDes core VDD m E EIS NEN EI SerDes bias SerDes SPn AVDD 16 x0 1uF 16x0 01uF transceivers 3 3V Single ended I O VDD IO 12x0 1uF 12x 0 01uF ports 1 2V Clock distribution REF AVDD 2x 0 1uF 2 x 0 01uF 1 x ferrite bead 120 ohm circuit 1 5Amp 3 5 2 Effective Pad Design Breakout vias for the decoupling capacitors should be kept as close together as possible The trace connecting the pad to the via should also be kept as short as possible with a maximum length of 50mils The width of the breakout traces should be 20mils or the width of the pad A Via sharing should not be used in board design with the Tsi578 Figure 27 Recommended Decoupling Capacitor Pad Designs A B C B 3 5 3 Power Plane Impedance and Resonance The intent of adding decoupling to a board is to lower the impedance of the power supply to th
21. there is no resonance on the guard traces the stitching vias should be spaced at intervals that equal 20A of the 3 harmonic Figure 9 Equation Ac dex 9 3x10 m s mou Jao 20x f sa m In the case of the 3 125 Gb s data rate the rise and fall times must be less than 40 pS This relates to an upper frequency of 25Ghz and a corresponding wavelength of 25 mm based on a permittivity of 4 3 Therefore the stitching vias must not be further apart than 8 mm Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 48 3 Layout Guidelines 3 3 1 4 Via Construction Due to the high frequency content of the Serial RapidIO signals it is necessary to minimize the discontinuities imposed by crossing ground and power planes when it is necessary to transition to different signal layers The use of a controlled impedance via is recommended The construction of a differential via is shown in Figure 10 5 Detailed design information can be found in bibliography entry 15 Designing AN Controlled Impedance Vias by Thomas Neu EDN Magazine October 2 2003 Figure 10 Differential Controlled Impedance Via Signal Via Anti pad which Differential Signal 4 vias connected touches the ground vias to ground DN Reference ground plane Reference ground plane 3 3 1 5 Layer Transitioning with Vias The basic rule in high speed signal routing is to keep vias in the signal path down to a minimum Vi
22. 00000 OO0Oo0O0O0O00000000 0000000000000 0000000000000 o000000000000 ooo0oo0oo0000000000000000000000 0 o o o o o o o o o o ooooooooo o0oooooooooQ BOTTOM VIEW 25 c a B 70100 C 3z ra omo gt lt lt DUERI N OOO E 1 Signals and Package Tundra Semiconductor Corporation www tundra com 1 Signals and Package 25 1 4 Thermal Characteristics Heat generated by the packaged IC has to be removed from the package to ensure that the IC is maintained within its functional and maximum design temperature limits If heat buildup becomes excessive the IC temperature may exceed the temperature limits A consequence of this is that the IC may fail to meet the performance specifications and the reliability objectives may be affected Failure mechanisms and failure rate of a device have an exponential dependence of the IC operating temperatures Thus the control of the package temperature and by extension the Junction Temperature is essential to ensure product reliability The Tsi578 is specified safe for operation when the Junction Temperature is within the recommended limits Table 4 shows the simulated Theta jb and Theta jc thermal characteristics of the Tsi578 FCBGA package Table 4 Thermal Characteristics of Tsi578 Interface Result Theta jb junction to board 11 7 C watt Theta jc junction to case 0 08 C watt 1 4 1 Junction to Ambient Thermal Characteristics Theta ja Table 5 sh
23. 02 07 www tundra com 3 Layout Guidelines 47 Change from a VSS reference plane to another VSS reference plane and place a minimum of one via connecting the two planes as close as possible to the signal via This also applies when making a reference plane change from one VCC plane to another VCC plane For symmetric stripline provided return path vias for both VSS and VCC Do not switch the reference plane from VCC to VSS or vice versa 3 3 1 3 Guard Traces Guard traces are used to minimize crosstalk Guard traces are tracks that run parallel to a signal trace for the entire length and are connected to the reference plane to which the signal s are associated Guard traces can lower the radiated crosstalk by as much as 20dB The use of guard tracks requires some planning and foresight The guard tracks will consume board real estate but in a dense routing where the potential for crosstalk is present guard traces will save overall space that would have been consumed by separation space Simulation has shown that a 5 mil ground trace with 5 mil spaces between the aggressor and receptor traces offers as much isolation as a 20 mil space between aggressor and receptor traces The aggressor trace is the trace with a driven waveform on it The receptor trace is the trace onto which the crosstalk is coupled Guard tracks are required to be stitched or connected with vias to the reference plane associated with the signal To ensure that
24. 03A_MA002_07 4 Contents Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com D TNORA About this Document Scope This section discusses general document information about the 7si578 Serial RapidIO Switch Hardware Manual The following topics are described e Scope on page 5 Document Conventions on page 5 e Revision History on page 7 The 751578 Serial RapidIO Switch Hardware Manual discusses electrical physical and board layout information for the Tsi578 It is intended for hardware engineers who are designing system interconnect applications with these devices Document Conventions This document uses a variety of conventions to establish consistency and to help you quickly locate information of interest These conventions are briefly discussed in the following sections Non differential Signal Notation Non differential signals are either active low or active high An active low signal has an active state of logic 0 or the lower voltage level and is denoted by a lowercase b An active high signal has an active state of logic 1 or the higher voltage level and is not denoted by a special character The following table illustrates the non differential signal naming convention state Single line signal Multi line signal Active high NAME NAME 3 Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A_MA002_07 Differential Signal
25. 7 32 2 Electrical Characteristics 2 3 Power The following sections describe the Tsi578 s power dissipation and power sequencing 2 3 1 Power Dissipation The power dissipation values provided are dependent on device configuration The line rate port configuration traffic all impact the Tsi578 s power consumption The following table shows the power in both 1x and 4x modes Table 8 Measured Power 1x Mode 16 Links in Operation EL A NE NI HRN VDD VDD_CORE D 1 9 195 189 F Lm f e f e 8 woe cw em I RN Total Measured Power 3 23 4 09 4 84 1 6 7 8 Consumption W Power Reduction per 0 10 0 13 10 Unused Odd Port W Power Reduction per 0 32 0 37 0 43 11 Unused Even Port W Notes 1 Voltage temperature and process are all nominal VDD CORE supplies the ISF and other internal digital logic SP VDD supplies the digital portion of the SRIO SerDes 2 3 4 SPn AVDD supplies the analog portion of the SRIO SerDes 5 VDD IO supplies power for all non SRIO I O 6 Total power is independent of SRIO distance travelled due to Voltage Mode Driver technology used for SRIO I O et Slight power variations must expected across different applications 8 Power is provided for fully utilized SRIO lanes 9 Core power reduces by approximately 10 under light traffic conditions Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com 2 Electrical Characteris
26. 78 User Manual Output capability of this pin is only used in test mode Must remain stable for 10 P CLK cycles after HW RST Bis de asserted in order to be sampled correctly Ignored after reset Pin must be tied off according to the required configuration Either a 10K pull up to VDD IO ora 10K pull down to VSS IO Internal pull down may be used for logic 0 Pin must be tied off according to the required configuration Either a 10K pull up to VDD IO ora 10K pull down to VSS IO Internal pull up may be used for logic 1 Tsi578 Hardware Manual 80B803A MAOO2 07 Tundra Semiconductor Corporation www tundra com 1 Signals and Package Table 2 Signal Descriptions and Recommended Termination 15 Recommended Pin Name Type Description Termination SP n 1 _ PWRDN I O Port n 1 Transmit and Receive Power Down Pin must be tied off LVTTL control according to the required PU This signal controls the state of Port n 1 Note configuration Either a 10K SP IO SPEED 1 I O LVTTL PD Tundra Semiconductor Corporation www tundra com that Port n 1 is never used when 4x mode is selected for a Serial Rapid IO MAC and it must be powered down 0 Port n 1 Powered Up 1 Port n 1 Powered Down Override SP n 1 _ PWRDN using PWDN x4 field in SRIO MAC x Clock Selection Register in the Tsi578 User Manual Output capability of this pin is only used in test mode Must remain st
27. Corporation www tundra com Tsi578 Hardware Manual 80B803A_MA002_07 20 Table 2 Signal Descriptions and Recommended Termination 1 Signals and Package Recommended Pin Name Type Description Termination TRST_b LVTTL IEEE 1149 1 Test Access Port TAP Reset Input Tie to VSS IO through a PU This input must be asserted during the assertion 10K resistor if not used of HARD RST_b Afterwards it may be left in either state Combine the HARD_RST_b and TRST_b signals with an AND gate and use the output to drive the TRST_b pin BCE LVTTL Boundary Scan compatibility enabled pin This This signal should have PU input is used to aid 1149 6 testing the capability to be Port n n 1 n 0 2 4 6 8 10 12 14 This signal also enables system level diagnostic capability using features built into the SerDes For more information on this functionality refer to the Serial RapidlO Signal Analyzer documentation available on the Tundra extranet This signal must be tied to VDD IO during normal operation of the device and during JTAG accesses of the device registers pulled up or pulled low The default setting is to be pulled up Pulling the signal low enables the signal analyzer functionality on the SerDes A 10K resistor to VDD IO should be used Power Supplies Analog 1 2V for Reference Clock S CLK p n Clock distribution network power supply SP n AVDD Port n and n
28. G software to use to access the internal registers Please visit the Tundra web site to download the BSDL file for the Tsi578 Reflow Profile The Tsi578 adheres to JEDEC STD 020C for its reflow profile For the leaded version the peak reflow temperature is 225 C 0 5 C For the lead free version the peak reflow temperature is 260 C 0 5 C Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A_MA002_07 www tundra com D TU Dh s A A 1 Clocking This appendix describes device behaviour outside the specified or recommended operating line rates and clock frequencies The following topics are discussed e Line Rate Support on page 69 P CLK Programming on page 70 Line Rate Support The Tundra Tsi578 supports all of the RapidIO Interconnect Specification Revision 1 3 specified line rates of 1 25 2 50 and 3 125 Gbaud The device also supports line rates that are outside of the RapidIO specification The ability to support multiple line rates gives the Ts1578 flexibility in both application support and power consumption Table 20 shows the supported line rates for the Tsi578 The Serial Port Select pin SP IO SPEED I1 0 must be set to the values shown in Table 20 to achieve the documented line rates Table 20 Tsi578 Supported Line Rates SP IO SPEED 1 0 S CLK p n MHz Baud Rate Gbaud Bit Settings 1 This information assumes a 100 ppm clock tolerance that must be obeyed between l
29. Johnson Howard Martin Graham 1993 Prentice Hall inc ISBN 0 13 395724 1 Harper Charles A 1999 McGraw Hill ISBN 0 07 026713 8 Application Note 905 1996 National Semiconductor Corp Lit 100905 002 amp 633201 001 Ritchey Lee W James C Blankenhorn 1993 SMT Plus Inc and Ritch Tech The Institute for Interconnecting and Packaging Electronic Circuits 1999 IPC Document IPC D 317A Tsi578 Hardware Manual 80B803A_MA002_07 10 11 12 13 14 15 16 17 High Speed Signal Propagation High Speed Digital Design and PCB Layout 1 10 GBps Serial Interconnect Requirements 10GBps Serial Backplanes Using Virtex Il Pro X Designing Controlled impedance Vias Computer Circuits Electrical Design First Edition Tsi578 RapidlO Switch User Manual Tsi578 Serial RapidlO Switch Hardware Manual 80B803A MAO002 07 Johnson Howard Martin Graham 2003 Prentice Hall inc ISBN 0 13 084408 X Hanson Robert J AmeriCom Test amp SMT Technology Inc Solving High Speed Serial Design Challenges 2004Xilinx Solving High Speed Serial Design Challenges 2004Xilinx Thomas Neu EDN magazine October 2 2003 Ron K Poon Prentice Hall Inc 1995 Tundra Semiconductor document number 80B803A MAO01 Ox pdf Tundra Semiconductor Corporation www tundra com D TARA 1 1 1 1 2 Signals and Package This chapter describes the packaging mechanical features for the Ts1578 It includ
30. The actual observed period may be longer if other devices pull the clock low e Period SCL LOW SCL LOW Period P CLK P CLKis 10 ns Reset time is 5 00 microseconds 100 kHz Tsi578 reset value is 0x01F4 A 2 3 6 Il2C SCLK Minimum High and Low Timing Register The I2C_SCLK Minimum High and Low Timing Register programs the minimum high and low periods of the I2C SCLK signal when generated by the master interface It is shadowed during boot loading and can be reprogrammed prior to a chain operation without affecting the bus timing for the current EEPROM SCL MINH Count for I2C SCLK High Minimum Period The SCL MINH field defines the minimum high period of the clock from rising edge seen high to falling edge of I2C SCLK This is a master only parameter The actual observed period may be shorter if other devices pull the clock low e Period SCL MINH SCL MINH Period P_CLK P CLKis 10 ns Reset time is 4 01 microseconds Tsi578 reset value is 0x0191 Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 80 A Clocking SCL MINL Count for I2C SCLK Low Minimum Period The SCL_MINL defines the minimum low period of the clock from falling edge seen low to rising edge of I2C SCLK This is a master only parameter The actual observed period may be longer if other devices pull the clock low e Period SCL MINL SCL MINL Period P_CLK P CLKis 10 ns
31. Tsi578 Serial RapidlO Switch Hardware Manual Final November 2007 80B803A MAO02 07 Trademarks TUNDRA is a registered trademark of Tundra Semiconductor Corporation Canada U S and U K TUNDRA the Tundra logo Tsi578 and Silicon Behind the Network are trademarks of Tundra Semiconductor Corporation All other registered and unregistered marks including trademarks service marks and logos are the property of their respective owners The absence of a mark identifier is not a representation that a particular product name is not a mark Copyright Copyright November 2007 Tundra Semiconductor Corporation All rights reserved Published in Canada This document contains information that is proprietary to Tundra and may be used for non commercial purposes within your organization in support of Tundra products No other use or transmission of all or any part of this document is permitted without written permission from Tundra and must include all copyright and other proprietary notices Use or transmission of all or any part of this document in violation of any applicable Canadian or other legislation is hereby expressly prohibited User obtains no rights in the information or in any product process technology or trademark which it includes or describes and is expressly prohibited from modifying the information or creating derivative works without the express written consent of Tundra Disclaimer Tundra assumes no responsibility
32. a maximum of 15pS 3 3 1 Stripline The RapidIO buses should be routed in a symmetrical edge coupled stripline structure in order to ensure a constant impedance environment The symmetrical stripline construction is shown in Figure 6 This method also provides clean and equal return paths through VSS and VDD from the I O cell of the Ts1578 to the adjacent RapidIO device The use of broadside coupled stripline construction as shown in Figure 7 is discouraged because of its inability to maintain a constant impedance throughout the entire board signal layer The minimum recommended layer count of a board design consists of 12 layers The optimum design consists of 16 layers The designer should consider both of these designs and weigh their associated costs versus performance Figure 6 Recommended Edge Coupled Differential Stripline symmetric when h1 h2 Power Ground plane t hy LW bod e h2 S l Power Ground plane Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com 3 Layout Guidelines 45 Equations for Stripline and Differential Stripline Impedance in Ohms O i d Zo TAE 0 67 z 0 8w t 2 9 E Zdiff 220 10 d The broadside coupled stripline construction is not recommended for use with RapidIO because of the manufacturing variations in layer spacings These variations will cause impedance mismatch artifacts in the signal waveforms and will degrade the per
33. able for 10 P_CLK cycles after HW_RST_B is de asserted in order to be sampled correctly Ignored after reset Serial Port Speed Select Serial Port Transmit and Receive operating frequency select bit 1 When combined with SP IO SPEEDYJO this pin selects the default serial port frequency for all ports 00 1 25Gbit s 01 2 5Gbit s default 10 3 125Gbit s 11 illegal Selects the speed at which the ports operates when reset is removed This could be either due to HARD_RST_b being de asserted or by the completion of a self reset This signal must remain stable for 10 P_CLK cycles after HW_RST_B is de asserted in order to be sampled correctly The signal is ignored after reset The SP_IO_SPEED 1 0 setting is equal to the SCLK SEL field inSRIO MAC x Clock Selection Register in the Tsib78 User Manual Output capability of this pin is only used in test mode pull up to VDD IO ora 10K pull down to VSS IO Internal pull up may be used for logic 1 Pin must be tied off according to the required configuration Either a 10K pull up to VDD IO or a 10K pull down to VSS IO Internal pull down may be used for logic 0 Tsi578 Hardware Manual 80B803A MAOO02 07 16 Table 2 Signal Descriptions and Recommended Termination 1 Signals and Package Recommended Pin Name Type Description Termination SP IO SPEED O I O See SP IO SPEED 1 Pin must be tied off LVTTL according to the required PU confi
34. addition of the appropriate disassembler software to the analyzer makes it a very powerful tool for examining the traffic on a link and aiding in software debugging Please contact your local test equipment vendor for appropriate solutions for your requirements 3 8 1 Logic Analyzer Connection Pads The pinout for a recommended SRIO 8 channel probe is given in Table 19 This pin signal assignment has been adopted by several tool vendors including Tektronix but is not an established standard These notes are given here Footprint Channel vs Lane Link Designations e Channel either an upstream OR downstream differential pair for a given lane e Ccletter the designator for a channel which accepts a given differential pair of signals e Ccletter p or n the two signals of the differential pair The signals within a given pair may be assigned to either P or N regardless of polarity 3 8 1 1 General Rules for Signal Pair Assignment of Analyzer Probe The differential pairs that make up the SRIO links must be assigned to specific pins of the footprint in order to take advantage of the pre assigned channel assignments provided by Nexus when purchasing the SRIO pre processor Table 19 8 Channel Probe Pin Assignment Ls omm s L9 KENN wo om p omm Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com 3 Layout Guidelines 67 Table 19 8 Channel Probe Pin Assignment Pins Signal Name Pins Signa
35. al Port 0 rxclkc Serial Port 0 clk gen logic i Ed T SerDes Serial Port 1 logic S CLK p n rxclkb Serial Port 14 UR Le o clk gen ogic __rxcikd Serial Port 15 logic Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 62 3 Layout Guidelines The reference clocks are described in Table 17 For more information about special line rate support see Clocking on page 69 Table 17 Clock Input Sources Maximum Clock Input Pin Type Frequency Clock Domain S CLK p n Differential 156 25 MHz Serial Transmit Domain Nominally 156 25MHz Internal Switching Fabric ISF Domain P CLK Single Ended 100 MHz Internal Register Domain and IC Domain 3 6 1 1 Frequencies Required The clock signals should be shielded from neighboring signal lines using ground traces on either side This reduces jitter by minimizing crosstalk from the neighboring signal lines Since P CLK is single ended extra precaution should be taken so that noise does not get coupled onto it In order to preserve the quality of the low jitter 156 25 MHz clock the shielding requirement of the clock lines is critical It is possible that low frequency noise can interfere with the operation of PLLs which can cause the PLLs to modulate at the same frequency as the noise The high frequency noise is generally beyond the PLL bandwidth which is about 1 10th the S CLK frequency For more information refer to Figure 4 on page
36. and meet JIG Joint Industry Guide Level B requirements for Brominated Flame Retardants other than PBBs and PBDEs e Zit Prototype version status optional If a product is released as a prototype then a Z is added to the end of the part number Further revisions to the prototype prior to production release would add a sequential numeric digit For example the first prototype version of device would have a Z a second version would have Z1 and so on The prototype version code is dropped once the product reaches production status Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com
37. ard layout that will provide the best performance possible The required decoupling by each voltage rail can be found in Table 16 on page 59 The ripple specifications for each rail are maximums and every effort should be made to target the layout to achieve lower values in the design A solid low impedance plane must be provided for the VDD 1 2V core supply referenced to VSS It is strongly recommended that the VDD and VSS planes be constructed with the intent of creating a buried capacitance The connection to the power supply must also be low impedance in order to minimize noise conduction to the other supply planes A solid low impedance plane must be provided for the SP_VDD 1 2V SerDes supply referenced to the VSS plane This supply can be derived from the same power supply as VDD as long as a Kelvin connection is used The preference however is to use a separate power supply The term Kelvin connection is used to describe a single point of contact so that AR power from one power plane does not leak past the power supply pin into the other power plane The leadkage can be caused by the fact the output of a power supply is a very low impedance point in order to be able to supply a large amount of current Because it is such a low impedance point any noise presented to it by the power plane is sent to ground A kelvin connection enables two power planes to be connected together at a single point Using this technique the same power sup
38. as can represent a significant impedance discontinuity and should be minimized When routing vias try to ensure that signals travel through the via rather than across the via A via where the signal goes through the via has a much different effect than a via where the signal travels across the via These two cases are shown in Figure 13 and in Figure 14 The in and out nodes of the via model are shown on the their corresponding locations in the figures Transitioning across a via that is not blind or buried leaves a stub which appears as a capacitive impedance discontinuity The portion of the via that conducts current appears inductive while the stub that develops only an electric field will appear capacitive Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com 3 Layout Guidelines 49 In order to minimize the effects of a via on a signal the following equations may be used to approximate the capacitance and inductance of the via design It can be seen that the proximity of the pad and antipad have a direct relationship on the capacitance and that the length of the barrel h has a direct effect on the inductance Figure 11 Equation LAle TD L s 08h in 3 a 1 ee pons C is the capacitance in pF T is the thickness of the circuit board or thickness of pre preg D is the diameter of the via pad D is the diameter of the antipad is the dielectric constant of the circuit board materia
39. can operations are not affected by a chance in the P CLK frequency because these transactions use the JTAG TCK clock signal and do not access the internal register bus Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com D TAR as B B 1 B 2 Ordering Information This chapter discusses ordering information and describes the part numbering system for the Tsi578 Ordering Information When ordering the Tsi578 please refer to the device by its full part number as displayed in Table 25 Table 25 Tsi578 Ordering Information TSI578 10GCLY 1 25 3 125 Gbit s FCBGA RoHS TSI578 10GIL 1 25 3 125 Gbit s FCBGA TSI578 10GILY 1 25 3 125 Gbit s FCBGA RoHS Part Numbering Information The Tundra part numbering system is explained as follows Tsi NNN N SS S E P G Z l H D n S 3 gt ERL 8 uu am amp ong g Z g o0 ges amp 5 3 5 go c 5 f l o e on amp O D aoa g o _ Ad q Q d 2589 o o 3 caa D 5 3 2 d amp g gt S g Au Ss oQ Oo e D D o z A S B e amp e o0 3 02 S8 a oz A oO un d O amp F 8 l e fs a 3 A E c Indicates optional characters e Tsi Tundra system interconnect product identifier All Tundra semiconductor product numbers start with Tsi e NNNN Product number may be three or four digits e SS S Maximum operating frequency or data transfer rate of the fastest interface For
40. changing the DISCOVERY TIMER value and P CLK are shown in Table 22 Table 22 Timer Values with DISCOVERY TIMER and P CLK Variations DISCOVERY TIMER P CLK Setting Setting Timer Value Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com A Clocking A 2 1 3 73 RapidlO Part 8 RapidlO Error Management Extensions Specification Section 2 3 2 9 Packet Time to live CSR Block Offset 0x2C The RapidIO Interconnect Specification Revision 1 3 defines the Packet Time to live register as follows The Packet Time to live register specifies the length of time that a packet is allowed to exist within a switch device The maximum value of the Time to live variable OXFFFF shall correspond to 100 msec 34 The resolution minimum step size of the Time to live variable shall be maximum value of Time to live 2e16 1 The reset value is all logic Os which disables the Time to live function so that a packet never times out This register is not required for devices without switch functionality Tundra Implementation The Tsi578 s RIO Packet Time to Live CSR on page 303 specifies the length of time that a packet is allowed to exist within a switch device The maximum value of the Time to live variable OxFFFF corresponds to 100 msec 34 The resolution minimum step size of the Time to live variable is maximum value of Time to live 2e16 1 Due to the uncertainty of the arrival o
41. e devices on the board It is necessary to pay attention to the resonance of the combined bulk capacitance and to stagger the values in order to spread the impedance valleys broadly across the operating frequency range Figure 29 demonstrates the concept of staggered bands of decoupling Calculate the impedance of each of the capacitor values at the knee frequency to determine their impact on resonance Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 60 3 Layout Guidelines Figure 28 Equation RUE whereT time from 10 to 90 knee rise Ts Figure 29 Decoupling Bypass Frequency Bands log Z log F Power Bulk Supply Caps Low freq Mid freq High freq HH freq Band As the frequency changes each part of the power distribution system responds proportionally the low impedance power supply responds to slow events bulk capacitors to mid frequency events and so forth Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com 3 Layout Guidelines 61 3 6 Clocking and Reset This section discusses the requirements of the clock and reset inputs 3 6 1 Clock Overview The Tsi578 switch input reference clocks that are used to drive the switch s internal clock domains Figure 30 Tsi578 Clocking Architecture C SCLK P CLK Internal registers and bus Internal Switching Fabric F rxclkb Serial Port 0 Seri
42. e the capacitors along the signal trace at a A 4 increment from the driver in order to avoid possible standing wave effects Figure 20 Receiver Coupling Capacitor Positioning Recommendation Escape Routing All differential nets should maintain a uniform spacing throughout a route Separation of differential pairs to go around objects should not be allowed Figure 21 illustrates several options for breaking out a differential pair from the Tsi578 device The order of preference is from A to D Case D below has a small serpentine section used to match the inter pair skew of the differential pair In this case each serpentine section should be greater than 3 x W W width and the gap should not increase by more than 2x Figure 22 illustrates these requirements Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 54 3 Layout Guidelines Figure 21 Escape Routing for Differential Signal Pairs EROS One OVe re 71ers Be O 2e Figure 22 Differential Skew Matching Serpentine d 3 3 5 Board Stackup The recommended board stack up is shown in Figure 23 This design makes provision for four stripline layers and two outer microstrip layers Layers eight and nine are provisioned as orthogonal low speed signal routing layers Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com 3 Layout Guidelines Figure 23 Recommended Board Stackup 55 ayers
43. ectrical Characteristics This section describes the AC and DC signal characteristics for the Tsi578 2 4 1 SerDes Receiver SP n _RD_p n Table 10 lists the electrical characteristics for the SerDes Receiver in the Tsi578 Table 10 SerDes Receiver Electrical Characteristics Symbol Parameter RX Differential NN impedance VpiFFI RX Differential Input 1600 mV Voltage Lcn RX Common Mode Over a range 100MHz to 0 8 Baud Return Loss Frequency Lpn RX Differential Return 10 Over a range 100MHz to 0 8 Baud Loss Frequency Vios RX Loss of Input mV Port Receiver Input level below which Differential Level Low Signal input is detected TRX ch skew RX Channel to Between channels in a given x4 port Channel Skew 1 25 2 5Gb s Tolerance Between channels in a given x4 port 3 125Gb s RX Input Rise Fall BEER Between 20 and 80 levels times Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 36 2 Electrical Characteristics 2 4 2 SerDes Transmitter SP n TD p n Table lists the electrical characteristics for the SerDes transmitter in the Tsi578 Table 11 SerDes Transmitter Electrical Characteristics mo o9 9 DRIRD e ZsEO TX Single Ended 45 50 55 Ohm Output impedance Zpo TX Differential Output 100 110 Ohm Impedance Vsw TX Output Voltage 425 mVp Vsw in mV Zggo 2 x Inom x Swing Single ended p Rldr Inom where Ridr Inom is the Idr to Inom ratio VpiFFO TX Diffe
44. ended Termination Recommended Description Termination PORT n 1x 4x Mode Serial RapidlO PORT n 1 1x Mode Serial RapidlO n 0 2 4 6 8 10 12 14 SP n TA p O SRIO Port n Lane A Differential Non inverting Transmit No termination required Data output 4x mode Port n Differential Non inverting Transmit Data output 1x mode SP n TA n O SRIO Port n Lane A Differential Inverting Transmit Data No termination required output 4x mode Port n Differential Inverting Transmit Data output 1x mode Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com 1 Signals and Package Table 2 Signal Descriptions and Recommended Termination 13 Recommended Pin Name Type Description Termination SP n TB p O SRIO Port n Lane B Differential Non inverting Transmit No termination required Data output 4x mode Port n 1 Differential Non inverting Transmit Data output 1x mode SP n TB n O SRIO Port n Lane B Differential Inverting Transmit Data No termination required output 4x mode Port n 1 Differential Inverting Transmit Data output 1x mode SP n TC p O SRIO Port n Lane C Differential Non inverting Transmit No termination required Data output 4x mode SP n TC n O SRIO Port n Lane C Differential Inverting Transmit Data No termination required output 4x mode SP n TD p O SRIO Port n Lane D Differential Non inve
45. es the following information e Pinlist on page 11 e Signals on page 11 e Package Characteristics on page 22 e Thermal Characteristics on page 25 Pinlist Refer to the Tundra website at www tundra com for information on the Tsi578 package pinlist and ballmap Signals The following conventions are used in the signal description table e Signals with the suffix p are the positive half of a differential pair e Signals with the suffix n are the negative half of a differential pair e Signals with the suffix b are active low Signals are classified according to the types defined in Table 1 Table 1 Signal Types EE NN i Bm o mmm SRIO Differential driver receiver defined by RapidlO Interconnect Specification Revision 1 3 Pulled Up internal to the Tsi578 Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 12 1 Signals and Package Table 1 Signal Types Continued PD Pulled Down internal to the Tsi578 LVTTL CMOS 1 0 with LVTTL thresholds N C No connect These signals must be left unconnected 1 2 1 Endian Ordering This document follows the bit numbering convention adopted by RapidIO Interconnect Specification Revision 1 3 where 0 7 is used to represent an 8 bit bus with bit O as the most significant bit 1 2 2 Signal Grouping Table 2 lists the signals by group and their recommended termination Table 2 Signal Descriptions and Recomm
46. evice Table 3 Tsi578 Package Characteristics Se See I ON Package Type Flip Chip Ball Grid Array FCBGA Moisture Sensitivity Level Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com 1 Signals and Package 23 Figure 1 Tsib78 Package Diagram Top View PIN 1 CORNER TOP VIEW 848 REF 14 48 REF 14 48 REF 27 00 f The capacitors shown may or may not be present on the Tsi578 package Figure 2 Tsib78 Package Diagram Side View Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 24 Figure 3 Tsib78 Package Diagram Bottom View Tsi578 Hardware Manual 80B803A_MA002_07 0 60 675X 9 940 A 26 24 22 29 18 16 14 12 10 B 6 4 2 25 23 2V 19 1715 45 119 7 5 3 1 0000000000000 000000000000 0000000000000 0000000000000 0000000000000 0000000000000 0000000000000l0000000000000 OOOO0000000000j 0000000000000 0000000000000l0000000000000 0000000000000 0000000000000 0000000000000l0000000000000 0000000000000 0000000000000 0000000000000 0000000000000 0000000000000 0000000000000 0000000000000 0000000000000 0000000000000 o0000000000000 0000000000000l00000000000 0000000000000 0000000000 0000000000000l0000000000 0000000000009J 0000000000 0000000000000 0000000000 CEP ECC MEC apenas eh 0000000000000l0000000000 oo o OOoOo0O0000000000J o00000000 O000000000000j 000000000 0000000000000 00000
47. f a packet relative to clock edges a packet s time to live expiry time is not precise but falls within a range The range is as follows e Minimum time to live nS 1 P CLK x 132 x TTLVAL e Maximum time to live nS 1 P CLK x 198 x TTLVAL The TTL field in the RIO Packet Time to Live CSR on page 303 is a 16 bit counter with a maximum decimal value of 65535 The default value of TTL is 0 which disables the Time to live counter Table 23 shows the TTL counter values using different values for P CLK Table 23 TTL Values with P CLK Variations 25 MHz Minimum time to live nS 5 28 uS 1 25Mhz x 132 x 1 1 25Mhz x 198 x 15782 3DA6 124 9 mS Minimum time to live nS 519 mS 1 25Mhz x 198 x 65535 1 25Mhz x 132 x 15782 3DA6 83 3 mS Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 74 A Clocking Table 23 TTL Values with P_CLK Variations 50 MHz Minimum time to live nS 1 50Mhz x 132 x 1 Maximum time to live nS 259 5 mS 1 50Mhz x 198 x 65535 100 MHz Minimum time to live nS 132 nS 1 100Mhz x 132 x 1 1 100Mhz x 132 x 63132 F69C 83 3 mS 1 100Mhz x 198 x 63132 F69C 125 mS Maximum time to live nS 129 8 mS 1 100Mhz x 198 x 65535 Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com A Clocking 75 A 2 2 Tundra Specific Timers The following sections describe how changing the P_CLK frequency to bel
48. for the accuracy or completeness of the information presented which is subject to change without notice Tundra products may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request In no event will Tundra be liable for any direct indirect special incidental or consequential damages including lost profits lost business or lost data resulting from the use of or reliance upon the information whether or not Tundra has been advised of the possibility of such damages The information contained in this document does not affect or change Tundra s product warranties Mention of non Tundra products or services is for information purposes only and constitutes neither an endorsement nor a recommendation As this information will change over time please ensure you have the most recent version by contacting a member of the Tundra technical support team or by checking the Support section of www tundra com Contents 3 Contents 1 Signalsand Package iussa xa kn Ra RACER AC RUERUCH ACA Rm ewe aman 11 IMEMBLULP PE 11 12 Signals 2e bene betas e eta ed E EE A ps uera depu paci ehe died dle 11 1 3 Package Characteristics 0 0 cette ene I e enn ee 22 1 4 Thermal Characteristics ise seinenc seie De kates bebe ek aed pe E a ee 25 2 Electrical Characteristics ics csccce xao ack Rack RR ACROCRUCE C EORR aurea da 29
49. formance of the link Figure 7 Not Recommended Broadside Coupled or Dual Stripline Construction A uel k E Signal Layer c Dielectric esi Signal Layer 3 3 1 1 Microstrip When it is necessary to place the differential signal pairs on the outer surfaces of the board the differential microstrip construction is used Figure 8 shows the construction of the microstrip topology Below the figure are the design equations for calculating the impedance of the trace pair Figure 8 Differential Microstrip Construction Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 46 3 Layout Guidelines Equations for the Differential Microstrip construction 7 60 4h Z prms 0 0 475 0 67 0 67 0 8w t Ss 0 96 Zap 2Z 1 0 48e lohms 3 3 1 2 Signal Return Paths The return path is the route that current takes to return to its source It can take a path through ground planes power planes other signals or integrated circuits The return path is based on electro magnetic field effects The return path follows the path of least resistance nearest to the signal conductor Discontinuities in the return path often have signal integrity and timing effects that are similar to the discontinuities in the signal conductor Therefore the return paths need to be given similar consideration A simple way to evaluate return path parasitic inductance is to draw a loop
50. guration Either a 10K pull up to VDD IO or a 10K pull down to VSS IO Internal pull up may be used for logic 1 Serial Port Lane Ordering Select 0 A B C D 1 D C B A Must remain stable for 10 P_CLK cycles after HARD_RST_b is de asserted in order to be sampled correctly Ignored after reset SP_RX_SWAP LVTTL Configures the order of 4x receive lanes on serial No termination required PD ports 0 2 4 6 14 Internal pull down can be 0 A B C D used for logic 0 Pull up to l1zD 6B VDD_IO through 10K if pull up i ired Must remain stable for 10 P CLK cycles after SNR pulkupis desire HARD RST bis de asserted in order to be Pull down to VSS_IO sampled correctly Ignored after reset through 10K if external pull down is desired SP_TX_SWAP LVTTL Configures the order of 4x transmit lanes on serial No termination required PD ports 0 2 4 6 14 Internal pull down can be used for logic 0 Pull up to VDD O through 10K if external pull up is desired Pull down to VSS IO through 10K if external pull down is desired Clock and Reset reference clock serial port system clock ISF clock and test clock The clock frequency is defined in the Minimum Clock Frequency Requirements section The maximum frequency of this input clock is 156 25 MHz P CLK l This clock is used for the register bus clock No termination required CML The maximum frequency of this input clock is
51. h Output Tristate Current All PD inputs and I Os of LVTTL type 100 hi for voltages from 0 to Vpp jo on the pin 0 V loi 22mA for INT b SW RST b and TDO pins lg 8mA for I2C CLK and I2C SD pins LVTTL Output Low Vpp io V lon 2mMA for INT b SW RST b Voltage 0 5 and TDO pins 10 10 00 LVTTL Output Low E Voltage Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com 2 Electrical Characteristics 39 Table 13 LVTTL I O and Open Drain Electrical Characteristics Dynamic Overshoot Vuyst LVTTL Input Hysteresis Voltage Cpag LVTTL Pad Capacitance Totgps Configuration Pin Setup Time TetgpH Configuration Pin Hold Time LI ES A M SP n _ MODESEL Setup Time a E 0 9V Max with a maximum energy of 0 75 V ns All Hyst inputs and I Os of LVTTL type All pads of LVTTL type For all Configuration pins except SP n MODESEL with respect to HARD RST b rising edge For all Configuration pins except SP n _ MODESEL with respect to HARD RST b rising edge with respect to rising edge of P CLK SP n MODESEL pins are sampled on every rising edge of P CLK ns with respect to rising edge of P CLK SP n MODESEL pins are sampled on every rising edge of P CLK SP n MODESEL Hold Time Tisovi INT_b SW_RST_b Output Valid Delay from rising edge of P_CLK Tisor1 INT b SW RST b Output Float Delay from rising edge of P CLK Input Clock Frequency Fin STAB P_CLK Input C
52. his release of the 731578 Serial RapidIO Switch Hardware Manual had the following modifications e A footnote has been added to the recommended terminations in Signal Grouping on page 12 e Signals SP RX SWAP and SP TX SWAP were added to Table 2 on page 12 e The production versions of the part numbers are now listed in Ordering Information on page 83 80B803A MAO02 05 Final January 2007 This release of the 731578 Serial RapidIO Switch Hardware Manual had the following modifications e Corrected information in Power Dissipation on page 32 Updated information in Thermal Characteristics on page 25 80B803A MAO02 04 Final January 2007 This release of the 731578 Serial RapidIO Switch Hardware Manual had the following modifications e Added information to Power Sequencing on page 34 e The Tytorage Storage temperature was changed to a minimum value of 55 C and a maximum value of 125 C in Table 6 on page 29 Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A_MA002_07 80B803A_MA002_03 Final October 2006 This release of the 7si578 Serial RapidIO Switch Hardware Manual had a number of modifications A new Clocking on page 69 was been added as well as power information in Power on page 32 80B803A_MA002_02 Final September 2006 This release of the Tsi578 Serial RapidIO Switch Hardware Manual has had a number of modifications The electrical and packagi
53. i578 requires only one reset input HARD RST b The signal provided to the device must be a monotonic 3 3V swing that de asserts a minimum of ImS after supply rails are stable The signal de assertion is used to release synchronizers based on P CLK which control the release from reset of the internal logic P CLK must therefore be operating and stable before the 1mS HARD RST b countdown begins Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com 3 Layout Guidelines 65 TRST_b must be asserted while HARD_RST_b is asserted following a device power up to ensure the correct setup of the tap controller TRST_b is not required to be re asserted for non power cycle assertions of HARD_RST_b 4 The most versatile solution to this requirement is to AND the HARD_RST_b and A TRST b signals together to form an output with which to drive the TRST b pin on the switch Power up option pins are double sampled at the release of HARD RST b As such there is no set up time requirement but the signals must be stable at the release of HARD RST b There is a hold time requirement of 100nS or 10 P CLK cycles minimum 3 7 Modeling and Simulation The need for verifying the signal integrity of the board design is very important for designs using GHz signalling Tundra recommends that the designer invest in a simulation tool as an aid to a successful RapidIO design Tools are available from companies such as Mentor Graphics
54. ines the Port Link Time out CSR as follows The port link time out control register contains the time out timer value for all ports on a device This time out is for link events such as sending a packet to receiving the corresponding acknowledge and sending a link request to receiving the corresponding link response The reset value is the maximum time out interval and represents between three and six seconds Tundra Implementation The Tsi578 supports this timer in the RIO Switch Port Link Time Out Control CSR on page 280 Effects of changing the P CLK frequency are shown in the following formula Time out 32 F x TVAL Fis P CLK frequency in MHz TVAL is the 24 bit counter setting Maximum TVAL decimal value of 16 777 215 OXFFFFFF Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com A Clocking 71 Effects of changing the P_CLK frequency and TVAL setting can be seen in Table 21 Table 21 Timer Values with P_CLK and TVAL Variations ues mem m m9 A 2 1 2 RapidlO Part 6 1x 4x LP Serial Physical Layer Specification Revision 1 3 Section 4 7 3 2 State Machine Variables and Functions SILENCE TIMER DONE The RapidIO Interconnect Specification Revision 1 3 defines the SILENCE TIMER DONE as follows Asserted when the SILENCE TIMER EN has been continuously asserted for 120 40us and the state machine is in the SILENT state The assertion of SILENCE TIMER DONE causes
55. ink attachment Both mechanical and adhesive techniques are available for heatsink attachment Tundra makes no recommendations as to the reliability or effectiveness of either approach The designer must critically analyze heatsink requirements selection criteria and attachment techniques For heatsink attachment methods that induce a compressive load to the FCBGA package the maximum force that can be applied to the package should be limited to 5 gm BGA ball provided that the board is supported to prevent any flexing or bowing The maximum force for the Tsi578 package is 3 38 Kg Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 28 1 Signals and Package Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com y TOR 29 2 Electrical Characteristics This chapter provides the electrical characteristics for the Tsi578 It includes the following information e Absolute Maximum Ratings on page 29 e Recommended Operating Conditions on page 30 e Power on page 32 2 1 Absolute Maximum Ratings Operating the device beyond the operating conditions is not recommended Stressing the Tsi578 beyond the Absolute Maximum Rating can cause permanent damage Table 6 lists the absolute maximum ratings Table 6 Absolute Maximum Ratings Cea MESE EIN REF AVDD am rani Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com
56. ink partners All bit and register settings that are documented for operation with S CLK 156 25 Mhz also apply to the use of 153 6 Mhz and 125 Mhz Refer to Clocking and Reset on page 61 for more clocking information Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 70 A Clocking A 2 P_CLK Programming The Ts1578 recommends a P CLK operating frequency of 100 MHz However the device also supports P CLK frequencies less than the recommended 100 MHz The ability to support other P CLK frequencies gives the Tsi578 flexibility in both application support and design The minimum frequency supported by the P CLK input is 25 Mhz Operation above 100 Mhz or below 25 Mhz is not tested or guaranteed The following sections describe the effects on the Ts1578 when the input frequency of the P CLK source is decreased from the recommended 100 Mhz operating frequency A 2 1 RapidlO Specifications Directly Affected by Changes in the P CLK Frequency The following sections describe how changing the P CLK frequency to below the recommended 100 MHz operation affect the counters and state machines in the Ts1578 that are defined in the RapidIO Interconnect Specification Revision 1 3 A 2 1 1 Port Link Time out CSR RapidlO Part 6 1x 4x LP Serial Physical Layer Specification Revision 1 3 Section 6 6 2 2 Port Link Time out CSR Block Offset 0x20 The RapidIO Interconnect Specification Revision 1 3 def
57. is pin remains asserted until the self reset is complete If the Tsi578 is reset from the HARD_RST_b pin this pin is de asserted and remains de asserted after HARD_RST_bis released For more information refer to Resets in the Tsi578 User s Manual External pull up required Pull up to VDD IO through 10K External pull up required Pull up to VDD_IO through 10K Tundra Semiconductor Corporation www tundra com Tsi578 Hardware Manual 80B803A_MA002_07 18 Table 2 Signal Descriptions and Recommended Termination Description Multicast Event Symbol pin As an input an edge rising or falling will trigger a Multicast Event Control Symbol will be sent to all ports As an output this pin will toggle its value every time an Multicast Event Control Symbol is received by any port which is enabled for Multicast even control symbols Must remain stable for 10 P_CLK cycles before and after a transition 1 Signals and Package Recommended Termination No termination required This pin must not be driven by an external source until all power supply rails are stable Tsi578 Hardware Manual 80B803A_MA002_07 Il2C SCLK O OD c J a clock up to 100 kHz No termination required LVTTL This clock signal must be connected to the clock Internal pull up may be PU of the serial EEPROM on the 12C bus used for logic 1 Pull up to 8mA VDD_IO through a minimum 470
58. l L is the inductance in nH h is the overall length of the via barrel dis the diameter of the via barrel Figure 12 Via Construction Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 50 3 Layout Guidelines Figure 13 Signal Across a Via Signal Via Signal Pwr amp Gnd Planes Figure 14 Signal Through a Via Signal Via Pwr amp Gnd Planes x LLL LLL Because of the high frequencies present in the RapidIO signal vias become a significant contributor to signal degradation Most vias are formed by a cylinder going through the PCB board Because the via has some length there is an inductance associated with the via Parasitic capacitance comes from the power and ground planes through which the via passes From this structure we model the via in RLC lumps as shown in Figure 15 and Figure 16 Cvia is the total capacitance of the via to ground or power Rvia is the total resistance through the via and Lvia is the total inductance of the via These parameters may be extracted using 3D parasitic extraction tools By distributing the R L and C the model better represents the fact that the capacitance resistance and inductance are distributed across the length of the via For the Via model to be accurate in simulation the propagation delay of each LC section should be less than 1 10 of the signa
59. l Name CFp Rx2 CEn Tx2 Figure 33 Analyzer Probe Pad Tracking Recommendation Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 68 3 8 2 3 9 3 Layout Guidelines JTAG Connectivity The Joint Test Action Group JTAG created the boundary scan testing standard documented in the IEEE 1149 1 Standard for testing printed circuit boards PCBs The boundary scan approach involves designing boundary scan circuitry into the integrated circuit PCBs populated with 1149 1 compliant devices can be then tested for connectivity correct device orientation correct device location and device identification All the pins on compliant devices can be controlled and observed using typically five pins that are routed to the board edge connector Board designers can develop a standard test for all 1149 1 compliant devices regardless of device manufacturer package type technology or device speed In addition to the 1149 1 compliant boundary scan TAP controller the Ts1578 also contains an 1149 6 compliant TAP controller to aid in the production testing of the SERDES pins The Tsi578 also has the capability to read and write all internal registers through the JTAG interface Through this interface users may load and modify configuration registers and look up tables without the use of RapidIO maintenance transactions or an PC EEPROM Please visit the Tundra web site at www tundra com to download the JTA
60. l risetime This is to ensure the frequency response of the via is modeled correctly up to the frequencies of interest More information may be found in reference 16 Figure 15 Signal Transitioning Across a Via Simulation Model Out Rvia 3 Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com 3 Layout Guidelines 51 Figure 16 Signal Transitioning Through a Via Simulation Model Lvia 3 Lvia 3 Lvia 3 Rvia 3 Rvia 3 Rvia 3 it Cvia 4 T oT Cvia 4 T MRTT 3 3 1 6 Buried Vs Blind The use of buried and blind vias is recommended because in both cases the signal travels through the via and not across it Examples of these two types of structures are shown in Figure 17 and Figure 18 Figure 17 Buried Via Example Signal I Pwr amp Gnd Planes Figure 18 Blind Via Example Signal 3 3 1 7 Serpentine Traces During layout it is necessary to adjust the lengths of tracks in order to accommodate the requirements of equal track lengths for pairs of signals In the case of the differential signals this ensures that both the negative and positive halves of the signals arrive at the receiver simultaneously thus maximizing the data sampling window in the eye diagram Creating a serpentine track is a method of adjusting the track length Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 52 3 Layout Guidelines
61. lock 100 Frequency Stability Fin PCLK DC P CLK Input Clock Duty Cycle P CLK Input Rise Fall Time Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 Measured between 5096 points on both signals Output Valid delay is guaranteed by design A float condition occurs when the output current becomes less than lio where lio is2x loz Float delay guaranteed by design 10 15 15 00 2 5 40 2 Electrical Characteristics Table 13 LVTTL I O and Open Drain Electrical Characteristics mea D 9p 9Dm9IM 9 fucEs MCES pin frequency Rares MHz both as input and output R pull up Resistor pull up 82K NER 260K Vil 0 8V R pull down Resistor pull down 28K UR 54K Vih 2 0V Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A_MA002_07 www tundra com 2 Electrical Characteristics 41 2 4 5 I2C Interface Table 14 lists the AC specifications for Tsi578 s PC Interface The I2C interfaces includes balls I2C SCLK DC SD C DISABLE I2C MA I2C SEL I2C_SA 1 0 and I2C SEL Table 14 AC Specifications for I C Interface w 000 0999 0 T9 e e wa ee smee socere 8 e e TupsrA Hold Time repeated START condition a Tsp Rise Time for I2C xxx all 12C signals o 1000 ns Tsr Fall Time for I2C xxx all I2C signals Tsustop Setup Time for STOP Condition Notes 1 See Figure 5 PC Interface Signal Timings 2 After this period the first clock pu
62. lse is generated Figure 5 I2C Interface Signal Timings TupsrA l Tsusro gt gt Pe gt lt HIGH TsuDAT TsusrA Repeated tart Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 42 2 Electrical Characteristics 2 4 6 Boundary Scan Test Interface Timing Table 15 lists the test signal timings for Tsi578 Table 15 Boundary Scan Test Signal Timings TCK Frequency ns Measured at 1 5V Note test ns Measured at 1 5V Note test ns 0 8V to 2 0V Note test ns 2 0V to 0 8V Note test TRST b must become asserted while HARD RST bis asserted during device power up Input Hold from TCK Tgsovi TDO Output Valid Delay from falling edge of TCK 8 Tori TDO Output Float Delay from falling edge of TCK Tgsrnsri TRST_B release before HARD RST b release o Input Setup to TCK SE Tgstrst2 TRST_B release before TMS or TDI activity a Outputs precharged to VDD Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A_MA002_07 www tundra com 3 Layout Guidelines 43 3 3 1 Layout Guidelines This chapter describes the layout guidelines for the Tsi578 It includes the following information e Impedance Requirements on page 43 e Tracking Topologies on page 44 e Power Distribution on page 56 e Decoupling Requirements on page 57 e Clocking and Reset on page 61
63. ng sections have had extensive revisions and the layout chapter has been added Tsi578 Serial RapidlO Switch Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com Bibliography 10 RapidlO Interconnect Specification Revision 1 3 Enhancements to the RapidlO AC Specification ANSI TIA EIA 644 1995 Electrical Characteristics of Low Voltage Differential Signaling LVDS Interface Circuits March 1996 12C Specification High Speed Digital System Design High Speed Digital Design High Performance Printed Circuit Boards Transmission Line RAPIDESIGNER High Speed PCB Design Design Guidelines for Electronic Packaging Utilizing High Speed Techniques Tundra Semiconductor Corporation www tundra com This specification explains RapidlO s logical layer common transport layer and physical layer protocol and packet formats It also describes overall inter operability requirements for the RapidlO protocol For more information see www rapidio org This document contains the AC specifications for the RapidlO physical layer This documents the LVDS electrical characteristics This specification defines the standard I2C bus interface including specifications for all the enhancements For more information see www semiconductors philips com document number 9398 393 40011 Hall Stephen H Garret W Hall amp James A McCall 2000 John Wiley amp Sons inc ISBN 0 471 36090 2
64. ohms resistor if higher edge rate required l2C SD I O OD I C input and output data bus bidirectional open No termination required LVTTL drain Internal pull up may be PU used for logic 1 Pull up to 8mA VDD O through a minimum 470 ohms resistor if higher edge rate required Il2C DISABLE I LVTTL Disable 1 C register loading after reset When No termination PD asserted the Tsi578 will not attempt to load required Pull up to register values from C VDD_IO through 10K if if I2C loading is not required I2C MA I CMOS C Multibyte Address PU When driven high C module will expect No termination required multi byte peripheral addressing otherwise when Internal pull up may be driven low single byte peripheral address is used for logic 1 assumed Pull up to VDD IO through Must remain stable for 10 P CLK cycles after 10K resistor if external HW RST bis de asserted in order to be sampled pull up is desired Pull correctly Ignored after reset down to VSS IO to change the logic state Tundra Semiconductor Corporation www tundra com 1 Signals and Package Table 2 Signal Descriptions and Recommended Termination 19 Recommended Pin Name Type Description Termination I2C SA 1 0 CMOS I C Slave Address pins No termination required PU The values on these two pins represent the Internal pull up may be values for the lower 2 bits of the 7 bit address of USed for logic 1 Tsi578 when acting
65. omain S CLK p n This clock domain is used to clock all of the Serial RapidlO transmit ports 3 6 2 1 Interfacing to the S CLK x inputs The interface for a LVPECL clock source to the receiver input cell is shown in Figure 31 Note that an AC coupled interface is required so that only the AC information of the clock source is transmitted to the clock inputs of the Ts1578 Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 64 3 6 3 Clock Source LVPECL CML Clock Source 3 Layout Guidelines Figure 31 Tsi578 driven by LVPECL or CML clock source PCB Traces The interface for an LVDS clock source to the converter cell is shown in Figure 32 Since an LVDS driver requires a DC termination path a 2 K resistor should be inserted before the capacitors This resistor can be placed anywhere along the signal path between the clock source and the AC coupling capacitors although Tundra recommends placing it close to the clock source Note that the effective termination resistance seen by the clock source is about 95 due to the parallel combination of this external resistor and the integrated termination resistor of the converter cell Again an AC coupled interface is required so that only the AC information of the clock source is transmitted to the clock inputs of the Tsi578 Figure 32 Tsi578 driven by an LVDS clock source 2KO PCB Traces LVDS Reset Requirements The Ts
66. ors This section describes any other factors that may impact the performance of the Tsi578 if P CLK is programmed to operate lower than the recommended 100 MHz frequency Internal Register Bus Operation The internal register bus where all the internal registers reside is a synchronous bus clocked by the P CLK source A decrease in the P CLK frequency causes a proportional increase in register access time during RapidIO maintenance transactions JTAG registers accesses and PC register accesses RapidlO Maintenance Transaction Maintenance transactions use the internal register bus to read and write registers in the Tsi578 If the P CLK frequency is decreased it may be necessary to review the end point s response latency timer value to ensure that it does not expire before the response is returned Changing the frequency of the P CLK does not affect the operation or performance of the RapidIO portion of the switch in particular its ability to route or multicast packets between ports JTAG Register Interface Changing the P CLK frequency affects accesses to the internal registers through the JTAG register interface because the interface uses the internal register bus However since access to the registers using the JTAG interface is largely a manual command line terminal operation using the Tundra JTAG Register Interface Software see www tundra com for more information the decreased performance will not be perceivable Boundary s
67. ow the recommended 100 MHz operation affect the Tundra specific counters and state machines in the Tsi578 A 2 2 1 Dead Link Timer The Dead Link Timer period is controlled by the DLT_THRESH field in the SRIO MAC x Digital Loopback and Clock Selection Register on page 403 Each time a silence is detected on a link the counter is reloaded from this register and starts to count down When the count reaches 0 the link is declared dead which means that all packets are flushed from the transmit queue and no new packets are admitted to the queue until the link comes up The duration of the dead link timer is computed by the following formula e 24413 DLT THRESH P_CLK period P_CLK is 100Mhz which gives a P_CLK period of 10nS Default value of DLT_THRESH is 0x7FFF which corresponds to 32767 e Using these parameters the populated formula is 8192 32767 10e 9 2 68 seconds When enabled this timer is used to determine when a link is powered up and enabled but dead that is there is no link partner responding When a link is declared dead the transmitting port on the Ts1578 removes all packets from its transmit queue and ensure that all new packets sent to port are dropped rather than placed in the transmit queue The DLT_THRESH is a 15 bit counter with a maximum value of 32767 Table 24 shows equations using different values for DLT_THRESH and P_CLK Table 24 Timer Values with P_CLK and DLT_THRESH Variations 25 MHz 8192
68. ows the simulated Theta ja thermal characteristic of the Tsi578 FCBGA package The results in Table 5 are based on a JEDEC Thermal Test Board configuration JESD51 9 and do not factor in system level characteristics As such these values are for reference only The Theta ja thermal resistance characteristics of a package depend on multiple system level variables Table 5 Simulated Junction to Ambient Characteristics Theta ja at specified airflow no Heat Sink Tsib78 FCBGA 14 6 C watt 13 6 C watt 12 9 C watt Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 26 1 4 1 1 1 4 2 1 Signals and Package System level Characteristics In an application the following system level characteristics and environmental issues must be taken into account e Package mounting vertical horizontal e System airflow conditions laminar turbulent e Heat sink design and thermal characteristics see Heatsink Requirement and Analysis on page 26 e Heat sink attachment method see Heatsink Requirement and Analysis on page 26 e PWB size layer count and conductor thickness e Influence of the heat dissipating components assembled on the PWB neighboring effects Example on Thermal Data Usage Based on the Thetay data and specified conditions the following formula can be used to derive the junction temperature Tj of the Ts1578 with a Om s airflow Tj 074 P Tamb Where
69. ply module can be used to provide power to a noisy digital power plane VDD as well as a quiet analog power plane SP AVDD The SPn_AVDD 3 3V SerDes analogue supply also needs low impedance supply plane This supply voltage powers the RapidIO receivers and transmitters and their associated PLLs Connect all of the SPn_AVDD pins to this plane and decouple the plane directly to VSS The plane must be designed as a low impedance plane in order to minimize transmitter jitter and maximize receiver sensitivity Construction of this plane as a buried capacitance referenced to VSS is suggested Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com 3 Layout Guidelines 57 3 5 The REF_AVDD pins provide power to the S_CLK distribution circuits in the switch The voltage should be derived from the SPn_VDD plane One ferrite will suffice to isolate the SPn_VDD from the REF_AVDD Two decoupling capacitors should be assigned to each pin The VDD_IO supply powers the 3 3V I O cells on the switch This supply requires no special filtering other than the decoupling to the VSS_IO plane Connect the VSS_IO plane to the VSS plane using a Kelvin connection Decoupling Requirements This section deals with the subject of decoupling capacitors required by the Tsi578 To accomplish the goal of achieving maximum performance and reliability the power supply distribution system needs to be broken down into its individual piece
70. receive be routed on different layers Cross coupling of differential signals results in an effect called Inter Symbol Interference ISI This coupling causes pattern dependent errors on the receptor and can substantially increase the bit error rate of the channel Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A_MA002_07 www tundra com 3 Layout Guidelines 53 3 3 3 3 3 4 Receiver DC Blocking Capacitors The Serial RapidIO interface requires that the port inputs be capacitor coupled in order to isolate the receiver from any common mode offset that may be present in the transmitter outputs DC blocking capacitors should be selected such that they have low dissipation factor and low series inductance The recommended capacitor value is 0 1uF ceramic in an 0402 size Figure 20 shows the recommended tracking and capacitor pad placement required It will be necessary to model and simulate the effects of the changed track spacing on the channel quality and determine if any changes are required to the topology An often used method of correcting the decreased impedance caused by the larger capacitor mounting pads is to create a slot in the shield plane below the capacitor bodies and soldering pads Since the impedance change caused by the slot is dependent on the capacitor geometry core thickness core material characteristics and layer spacings the size and shape of the slot will have to be determined by simulation Do not plac
71. rential Output 2 Vsw mVp Voltage Amplitude p VoL TX Output Low level 1 2 V Voltage Vsw i a VoH TX Output High level 1 2 Voltage VTCM TX common mode V Voltage Lori TX Differential Return 10 For Baud Loss Frequency 10 Freq f 625MHz and Lpn2 TX Differential Return For 625MHz Freq f Baud Loss Frequency TTX_skew TX Differential signal ps Skew between _p and _n signals ona skew give Serial channel TX Output Rise Fall Between 20 and 80 levels times Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A_MA002_07 www tundra com 2 Electrical Characteristics 37 2 4 3 Reference Clock S CLK p n Table 12 lists the electrical characteristics for the differential SerDes Reference clock input S CLK pf n in the Tsi578 Table 12 Reference Clock S CLK p n Electrical Characteristics sme ee Vsw Input voltage 0 1 0 5 1 V swing VDIFF Differential input Voirr Vsw 2 voltage swing Differential Input 2000 The S_CLK_p n must be AC Common Mode coupled Range S_CLK_p S_CLK_n 2 Fin Input Clock 156 25 156 25 Hz Frequency Fs ckp Ref Clock 100 100 ppm PPM with respect to 156 25 MHz Frequency Stability Fin_DC Ref Clock Duty 40 50 Cycle TR SCLK S_CLK_p n Input 1 Tr SCLK Rise Fall Time rms a Total Permissible Phase Jitter on the Reference Clock is 3 ps rms This value is specified with assumption that the measurement is done with a 20 G Samples s scope with more than 1 million
72. rting Transmit No termination required Data output 4x mode SP n TD n O SRIO Port n Lane D Differential Inverting Transmit Data No termination required output 4x mode Serial Port n n 1 Receive n 0 2 4 6 8 10 12 14 SP n RA p I SRIO Port n Lane A Differential Non inverting Receive DC blocking capacitor of Data input 4x node 0 1uF in series Port n Differential Non inverting Receive Data input 1x mode SP n RA n I SRIO Port n Lane A Differential Inverting Receive Data DC blocking capacitor of input 4x mode 0 1uF in series Port n Differential Inverting Receive Data input 1x mode SP n RB p I SRIO Port n Lane B Differential Non inverting Receive DC blocking capacitor of Data input 4x mode 0 1uF in series Port n 1 Differential Non inverting Receive Data input 1x mode SP n RB n I SRIO Port n Lane B Differential Inverting Receive Data DC blocking capacitor of input 4x mode 0 1uF in series Port n 1 Differential Inverting Receive Data input 1x mode SP n RC p I SRIO Port n Lane C Differential Non inverting Receive DC blocking capacitor of Data input 4x mode 0 1uF in series Tundra Semiconductor Corporation www tundra com Tsi578 Hardware Manual 80B803A_MA002_07 14 Table 2 Signal Descriptions and Recommended Termination 1 Signals and Package Recommended Pin Name Type Description Termination SP n RC n I SRIO Port n
73. s and each designed carefully The standard model for representing the components of a typical system are shown in Figure 24 This figure graphically represents the parasitics present in a power distribution system Figure 24 System Power Supply Model Power Delivery System Vdd Power Decoupling Substrate Die Lpcb Rpcb 3 5 1 Component Selection The recommended decoupling capacitor usage for the Tsi578 is shown in Table 16 on page 59 The capacitors should be selected with the smallest surface mount body that the applied voltage permits in order to minimize the body inductance Ceramic X7R type are suggested for all of the values listed The larger value capacitors should be low ESR type The components should be distributed evenly around the device in order to provide filtering and bulk energy evenly to all of the ports Use the Tsi578 ball map available at www tundra com to aid in the distribution of the capacitors Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 58 3 Layout Guidelines 3 5 1 1 REF_AVDD The REF_AVDD pins require extra care in order to minimize jitter on the transmitted signals The circuit shown in Figure 25 is recommended for the REF_AVDD signal One filter is required for the two pins Figure 25 PLL Filter 120 2 1 5A SP_VDD 1 2V REF_AVDD pin C24 Mel ET REF_AVDD pin C26 3 5 1 2 SPn_AVDD The circuit shown in Figure 26 is recommended for
74. s 51 milliseconds This timeout is not active during the boot load sequence Tsi578 reset value is 0x0033 Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com A Clocking 81 A 2 3 8 I2C Byte Transaction Timeout Register The I2C Byte Transaction Timeout Register programs the Transaction and Byte time outs The timer periods are relative to the USDIV period for the byte timeout and relative to the MSDIV period for the transaction timeout BYTE TO Count for Byte Timeout Period The BYTE TO field defines the maximum amount of time for a byte to be transferred on the PC bus This covers the period from Start condition to next ACK NACK between two successive ACK NACK bits or from ACK NACK to Stop Restart condition A value of 0 disables the timeout e Period BYTE_TO BYTE TO Period USDIV USDIV is the microsecond time defined in I2C Time Period Divider Register This timeout is disabled on reset and is not used during boot load Tsi578 reset value is 0x0000 TRAN_TO Count for Transaction Timeout Period The TRAN TO field defines the maximum amount of time for a transaction on the I2C bus This covers the period from Start to Stop A value of 0 disables the timeout e Period TRAN TO TRAN TO Period MSDIV MSDIV is the millisecond time defined in I2C Time Period Divider Register This timeout is disabled on reset and is not used during boot load
75. samples taken The zero crossing times of each rising edges are recorded and an average Reference Clock is calculated This average period may be subtracted from each sequential instantaneous period to find the difference between each reference clock rising edge and the ideal placement to produce the Phase Jitter Sequence The PSD of the phase jitter is calculated and integrated after being weighted with the transfer function shown in Figure 4 The square root of the resulting integral is the rms Total Phase Jitter Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 38 2 Electrical Characteristics Figure 4 Weighing function for RMS Phase Jitter Calculation Magnitude OdBL SS 20 dB Decade 40 dB Decade A 1 5 MHz 10 MHz Frequency 2 4 4 LVTTL I O and Open Drain Signals Table 13 lists the electrical characteristics for the 3 3 V digital LVTTL Interface pins on the Tsi578 Table 13 LVTTL I O and Open Drain Electrical Characteristics Vit LVTTL Input Low Voltage Vin LVTTL Input High Voltage All inputs and I Os of LVTTL type All inputs and I Os of LVTTL type uA All non PU inputs and I Os of LVTTL type uA All non PD inputs and I Os of LVTTL type a te a LVTTL Input Low Current LVTTL Input High Current ae ae 1 All PU inputs and I Os of LVTTL type for voltages from 0 to Vpp jo on the pin lozL Pu lii PU LVTTL Input Low Output Tristate Current LVTTL Input Hig
76. seconds Tsi578 reset value is 0OxX007E SDA HOLD Count for I2C SD Hold Period The SDA HOLD field defines the minimum hold time for the I2C_SD signal that is I2C SD valid past the falling edge of I2C SCLK This applies to both slave and master interface e Period SDA HOLD SDA HOLD Period P CLK where P CLK is 10 ns Reset time is 310 nanoseconds Tsi578 reset value is OxOO1F Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com A Clocking 79 A 2 3 5 I2C_SCLK High and Low Timing Register The I2C_SCLK High and Low Timing Register programs the nominal high and low periods of the I2C SCLK signal when generated by the master interface It is shadowed during boot loading and can be reprogrammed prior to a chain operation without affecting the bus timing for the current EEPROM SCL HIGH Count for I2C SCLK High Period The SCL HIGH field defines the nominal high period of the clock from rising edge to falling edge of I2C SCLK This is a master only parameter The actual observed period may be shorter if other devices pull the clock low e Period SCL HIGH SCL HIGH Period P_CLK P CLKis 10 ns Reset time is 5 00 microseconds 100 kHz Tsi578 reset value is 0x01F4 SCL LOW Count for I2C SCLK Low Period The SCL LOW field defines the nominal low period of the clock from falling edge to rising edge of I2C SCLK This is a master only parameter
77. t e SP VDD 1 2 V and REF AVDD 1 2 V should power up at approximately the same time as VDD e Delays between the powering up of VDD SP VDD and REF AVDD are acceptable e No more than 50ms after VDD is at a valid level VDD IO 3 3 V should be powered up to a valid level e VDD IO 33V must not power up before VDD 1 2 V e SPn AVDD 3 3V should power up at approximately the same time as VDD IO e Delays between powering up VDD IO and SPn AVDD are acceptable e SPn AVDD must not power up before SP VDD It is recommended that there not be more than 50ms between ramping of the 1 2 V and 3 3 V supplies The power supply ramp rates must be kept between 10 V s and 1x10E6 V s to minimize power current spikes during power up If itis necessary to sequence the power supplies in a different order than that recommended above the following precautions must be taken e Any power up option pins must be current limited with 10 K ohms to VDD IO or VSS IO as required to set the desired logic level e Power up option pins that are controlled by a logic device must not be driven until all power supply rails to the Tsi578 are stable 2 3 2 1 Power down Power down is the reverse sequence of power up e VDD_IO 3 3V and SP n _AVDD e VDD 1 2V SP VDD and REF AVDD power down at the same time or all rails falling simultaneously Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com 2 Electrical Characteristics 35 2 4 El
78. that traces the current from the driver through the signal conductor to the receiver then back through the ground power plane to the driver again The smaller the area of the loop the lower the parasitic inductance If via densities are large and most of the signals switch at the same time as would be the case when a whole data group switches layers the layer to layer bypass capacitors may fail to provide an acceptably short signal return path to maintain timing and noise margins When the signals are routed using symmetric stripline return current is present on both the VDD and VSS planes If a layer change must occur then both VCC and VSS vias must be placed as close to the signal via as possible in order to provide the shortest possible path for the return current The following return path rules apply to all designs Always trace out the return current path and provide as much care to the return path as the path of the signal conductor Do not route impedance controlled signals over splits in the reference planes Do not route signals on the reference planes in the vicinity of system bus signals Do not make signal layer changes that force the return path to make a reference plane change Decoupling capacitors do not adequately compensate for a plane split Do not route over via anti pads or socket anti pads If reference plane changes must be made Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO0
79. the Boot Diagnostic Timeout Timer e Period MSDIV Period USDIV MSDIV 1 Tsi578 reset value is 0x03E7 A 2 3 2 I2C Start Condition Setup Hold Timing Register The I2C Start Condition Setup Hold Timing Register programs the setup and hold timing for the start condition when generated by the master control logic The timer periods are relative to the reference clock This register is shadowed during boot loading and can be reprogrammed prior to a chain operation without affecting the bus timing for the current EEPROM START SETUP Count for the START Condition Setup Period The START SETUP field defines the minimum setup time for the START condition that is both I2C SCLK and I2C SD seen high prior to I2C SD pulled low This is a master only timing parameter This value also doubles as the effective Stop Hold time AN e Period START SETUP START SETUP Period PCLK PCLK is 10ns Tsi578 Hardware Manual Tundra Semiconductor Corporation 80B803A MAO002 07 www tundra com A Clocking 77 Reset time is 4 71 microseconds Tsi578 reset value is 0x01D7 START HOLD Count for the START Condition Hold Period The START HOLD field defines the minimum hold time for the START condition that is from I2C SD seen low to I2C SCLK pulled low This is a master only timing parameter Period START HOLD START HOLD Period P_CLK e P CLK is 10ns e Reset time is 4 01 microseconds e TSsi578 reset value is 0x0191 A 2
80. tics 33 10 The corresponding even port is powered up and fully utilized 11 The corresponding odd port is already powered down This number represents additional power reduction which is gained by powering down the even port The following table represents the measured power in 4x mode Table 9 Measured Power 4x Mode Eight Links in Operation VDD VDDCORE Total Measured Power 3 32 4 34 5 11 1 6 7 8 Consumption W Power Reduction per 0 37 0 50 10 Unused Port W Notes 1 Voltage temperature and process are all nominal VDD CORE supplies the ISF and other internal digital logic SP VDD supplies the digital portion of the SRIO SerDes 2 3 4 SPn AVDD supplies the analog portion of the SRIO SerDes 5 VDD IO supplies power for all non SRIO I O 6 Total power is independent of SRIO distance travelled due to Voltage Mode Driver technology used for SRIO I O 7 Slight power variations must expected across different applications 8 Power is provided for fully utilized SRIO lanes 9 Core power reduces by approximately 1046 under light traffic conditions 10 Link pair refers to link groups 0 1 2 3 etc The odd numbered ports in the link pairs are powered down Tundra Semiconductor Corporation Tsi578 Hardware Manual www tundra com 80B803A MAO002 07 34 2 Electrical Characteristics 2 3 2 Power Sequencing The Tsi578 must have the supplies powered up in the following order e VDD 1 2 V must be powered up firs
81. tion during which the I2C SCLK and I2C SD signals must both be seen high in order to call the bus idle This period is a protection against external master devices not correctly idling the bus e Period IDLE DET IDLE DET Period USDIV where USDIV is the microsecond time defined in the I2C Time Period Divider Register A value of zero results in no idle detect period meaning the bus will be sensed as idle immediately Reset time is 51 microseconds Tsi578 reset value is 0x0033 Il2C SD Setup and Hold Timing Register The I2C SD Setup and Hold Timing Register programs the setup and hold times for the I2C SD signal when output by either the master or slave interface It is shadowed during boot loading and can be reprogrammed prior to a chain operation without affecting the bus timing for the current EEPROM SDA SETUP Count for the I2C SD Setup Period The SDA SETUP field defines the minimum setup time for the I2C SD signal that is I2C SD is set to a desired value prior to rising edge of I2C_SCLK This applies to both slave and master interface This value should be set to the sum of the I2C SD setup time and the maximum rise fall time of the I2C SD signal in order to ensure that the signal is valid on the output at the correct time This time is different than the raw I2C SD setup time in the PC Specification e Period SDA SETUP SDA_SETUP Period P_CLK where P_CLK is 10ns Reset time is 1260 nano

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