GPIO-MM User Manual - Diamond Systems Corporation
Contents
1. EICIST E2CIST EXIIST EXIST EXBST EXI4ST EXSST EXI6ST Write EICIST Encoder 1 Interrupt Status A 1 means this counter was a source of the current interrupt A 0 means it was not involved in the interrupt E2CIST Encoder 2 Interrupt Status A 1 means this counter was a source of the current interrupt A 0 means it was not involved in the interrupt EXI 1 6 ST External Interrupt 1 Interrupt Status A 1 means this counter was a source of the current interrupt A 0 means it was not involved in the interrupt EXT Interrupt 3 6 Control Register I Em ee EXI4EN EXIAPOL EXISEN EXISPOL EXIGEN EXI6POL EXI 3 6 EN External Interrupt 43 6 Enable A 1 turns on the interrupt generation whenever the External interrupt pin changes state in the direction set by the polarity bit below A 0 turns off the function EXI 3 6 POL External Interrupt 43 6 Polarity A 1 sets positive polarity pulses to generate the external interrupt A 0 sets negative polarity pulses Read EXT 7 14 Interrupt Status Register Indicates what is the source of the most current interrupt generating Interrupt A to the PC104 Bus If multiple interrupts occur simultaneously then all are indicated at the same time qose qp o qas px EXI7ST EXI8ST EXI9ST EXI108T EXILIST EXI12ST EXII3ST EXII4ST Bit No Name2. e Port direction and operation is selected through software programmable control registers All lines are buffered with transceivers Two Quadrature Position Encoders e Encoder inputs are rising falling edge selectable e Each encoder is individually enabled disabled e Each encoder is followed by 16 bit counter e Each 16 bit counter is presettable to any 16 bit value Interrupt Features e 16 multiplexed encoder interrupt sources 1 from each counter below and 14 External Interrupt lines multiplexed onto a single PC104 IRQ output line All interrupt sources are rising falling edge selectable e All interrupt sources are individually enabled disabled e All int sources Enhanced Features e On board EEPROM for user configuration data storage e AnLED display for easy identification of FPGA personality which can also be read in a register nterrupt source selection with counter timer DIO or external line options e A register accessible FPGA revision code for version control Software controlled board reset Diamond Systems Corporation GPIO MM User Manual Page 4 Board Layout Board Drawing Figure 1 GPIO MM Board Layout 3 775 Diamond Systems Corporation GPIO MM User Manual Page 5 I O Connector Pinout Digital I O Header Pinout Connector J4 is the 50 pin general purpose DIO interface The connector connects directly to the FPGA which implements the functionality of
3. Output Output Output 0 0 0 1 Output Output Output Input 0 0 1 0 Output Output Input Output 0 0 1 1 Output Output Input Input 0 1 0 0 Output Input Output Output 0 1 0 1 Output Input Output Input 0 1 1 0 Output Input Input Output 0 1 1 1 Output Input Input Input 1 0 0 0 Input Output Output Output 1 0 0 1 Input Output Output Input 1 0 1 0 Input Output Input Output 1 0 1 1 Input Output Input Input 1 1 0 0 Input Input Output Output 1 1 0 1 Input Input Output Input 1 1 1 0 Input Input Input Output 1 1 1 1 Input Input Input Input Diamond Systems Corporation GPIO MM User Manual Page 25 Programming Enhanced Features EEPROM Programming The EEPROM provides non volatile memory for storing application data Program the EEPROM using the following steps Repeat these steps for each data byte 1 Write the data byte to the EEPROM Data Register 08h 2 Specify the EEPROM address 0 256 where the data is to be written by writing the address to the EEPROM Address Register 09h 3 Set the data transfer direction to write by resetting the RW bit in the EEPROM Control and Status Register OAh 4 Set the EE EN bit in the EEPROM Control and Status Register 0Ah to initiate the write operation To read stored EEPROM data use the following steps Repeat these steps for each data byte 1 Specify the EEPROM address 0 256 where the data is to be read from b
4. when read 1 1 1 Quadrature Encoder Registers Base 0 Read Write Encoder 1 amp 2 Control Setting amp Readback Register pe Eee sess poeseos cq Name orror Jon oo QEIEN Quadrature Encoder 1 Enable A 1 turns on the Encoder Counter function for Encoder 1 A 0 turns off the function QE1POL Quadrature Encoder 1 Polarity determines under what conditions the counter increments up or down Every edge rising or falling on A or B causes a change in the count Not every quadrature encoder defines A leading B as Counter Clockwise rotation sometimes it s Clockwise So the polarity bit is typically used to define the relationship between A B counting up and the direction of the encoder shaft rotation We define the following Polarity bit 1 Input A edge leading input B edge counting up Input B edge leading input A edge counting down default Polarity bit 0 Input A edge leading B edge counting down Input B edge leading A edge counting up QE2EN Quadrature Encoder 2 Enable A 1 turns on the Encoder Counter function for Encoder 2 A 0 turns off the function QE2POL Quadrature Encoder 2 Polarity determines under what conditions the counter increments up or down Polarity bit 1 Input A edge leading input B edge counting up Input B edge leading input A edge counting down default Polarity bit 0 Input A edge leading B edge counting down Input B edge leading
5. Base 7 Bit No Name EXI 7 14 S T External Interrupt 7 14 Interrupt Status A 1 means this counter was a source of the current interrupt A 0 means it was not involved in the interrupt Write EXT Interrupt 7 10 Control Register SAP s eee ee EXI7EN EXI7POL EXISEN JEXI8POL EXI9EN EXI9POL EXI 7 10 EN External Interrupt 7 10 Enable A 1 turns on the interrupt generation whenever the External interrupt pin changes state in the direction set by the polarity bit below A 0 turns off the function Diamond Systems Corporation GPIO MM User Manual Page 16 EXI 7 10 POL External Interrupt 7 10 Polarity A 1 sets positive polarity pulses to generate the external interrupt A 0 sets negative polarity pulses Base 7 Read Unused Base 8 Write EXT Interrupt 11 14 Control Register a aee eae i 1 lExii 1POL EXI12EN EXI12POL EXII3EN EXI13POL EXI14EN EX114POL EXI 11 14 EN External Interrupt 11 14 Enable A 1 turns on the interrupt generation whenever the External interrupt pin changes state in the direction set by the polarity bit below A 0 turns off the function EXI 11 14 POL External Interrupt 11 14 Polarity A 1 sets positive polarity pulses to generate the external interrupt A 0 sets negative polarity pulses Base 8 Read Unused 1 1 2 E
6. NOTE AII positions are paralleled with zero ohm resistor locations for hard wire configuration line pull up pull down selection VO Line Pull up Pull down Selection Use jumper J8 to configure the pull up and pull down state of the counter timer header pins J3 Use jumper J11 to configure the pull up and pull down state of the DIO header pins J4 DIO pin pull up and pull down state is configured as shown in the following examples Jumper the position marked 5 to pull the J3 I O pins up to 5VDC Diamond Systems Corporation GPIO MM User Manual Page 11 Figure 6 Example Pull I O Pins Up to 5 VDC 455455485 OPOPOPOP 56G 2oOomxmonoxo DADADROR MESES E EET ES Jumper the position marked to pull the J3 I O pins down to ground Figure 7 Example Pull I O Pins Down to Ground omaltielelelelelelele e ie 5 6 Loud Loud LOY Loya e e Loud HOY NOTE Placing a jumper on both 5 and G simultaneously will short the 5VDC power plane to ground Diamond Systems Corporation GPIO MM User Manual Page 12 Map Overview The register base address is determined by setting jumper J10 as described in Section 4 Board Configuration Base Address Selection Jumper pins 2 5 set the DIO base address and pins 6 9 set the counter timer base address Counter Timer and Enhanced Feature Pro
7. to PC 104 IRQ5 1 91 1 1 91 345 6 7 101112156 Jumper blocks 7 J9 are also used to enable interrupt sharing for each IRQ signal enabling 1K Ohm pull down resistor When an I O module drives an IRQ line its output signal must either drive logic high or become a tri state input This allows more than one device to be on a single IRQ line To facilitate this a pull down resistor is used on the IRQ line to bring the logic low when no device is signaling an interrupt Shorting the R resistor jumper connects a 1K pull down resistor between the IRQ line and ground The following example shows IRQA connected to a pull down resistor and routed to IRQ5 which is shared Figure 5 Example Connect IRQA to Pull down Resistor and Route to Shared IRQ5 iroa 21 911 1 9 Lej o 345 6 7 10111215R NOTE There can only be one pull down resistor IRQ line If jumper blocks J7 and J9 both select IRQS only one jumper block should have the R jumper inserted Likewise there should only be one R jumper in a configuration of multiple GPIO MM boards NOTE All positions are paralleled with zero ohm resistor locations for hard wire configuration IRQA and IRQB interrupts sources are selected by configuring the enhanced feature register OCh as described in the Section 6 Register Bit Descriptions Interrupt Source Register
8. 2C0 Port 2C7 8255 2 Port C bits 0 7 5V 5 volt DC from the PC 104 bus Ground Digital ground from the PC 104 bus Diamond Systems Corporation GPIO MM User Manual Page 7 Counter timer Header Pinout Connector J3 is the 50 pin counter timer interface The connector connects directly to the FPGA which implements the functionality of two CTS9513 counter timer chips e input and ten output counter timer signals Eight input and eight output TTL level signals Ten gates e Power and ground The J3 pins may be configured to pull up to 5V or pull down to ground using jumper J8 as describe in Section 4 Board Configuration Line Pull up pull down Selection Q In 1A Unused Q In 2A Unused Ext 1 Ext IRQ 3 Ext IRQ 5 Ext IRQ 7 Ext IRQ 9 Ext IRQ 11 Ext IRQ 13 Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused 5V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Q In 1 B Unused Q In 2 B Unused Ext IRQ 2 Ext IRQ 4 Ext IRQ 6 Ext IRQ 8 Ext 10 Ext 12 Ext IRQ 14 Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Ground NOTE The co
9. A edge counting up Base 1 Read Write Encoder 1 Counter Preset Low Byte Register Access to this register allows a read or write to the low byte of the counter register of encoder 1 This register can be read at any time It is recommended that the user disable the quadrature encoder function while writing this register Diamond Systems Corporation GPIO MM User Manual Page 14 Base 2 Read Write Encoder 1 Counter Preset High Byte Register Access to this register allows a read or write to the high byte of the counter register of encoder 1 This register can be read at any time It is recommended that the user disable the quadrature encoder function while writing this register Base 3 Read Write Encoder 2 Counter Preset Low Byte Register Access to this register allows a read or write to the low byte of the counter register of encoder 2 This register can be read at any time It is recommended that the user disable the quadrature encoder function while writing this register Base 4 Read Write Encoder 2 Counter Preset High Byte Register Access to this register allows a read or write to the high byte of the counter register of encoder 2 This register can be read at any time It is recommended that the user disable the quadrature encoder function while writing this register Base 5 Write Encoder EXT 1 2 Interrupt Control Register PUN E pou Name EICIEN E2CIEN EXIIEN EXIIPOL EXDEN EXD
10. LEN i tnn A aae Dire Locus Doe d 27 Figures Figure 1 GPIO MM Board Layout icc sets erre eterne enne ne tenen 6 Figure 2 Example Set DIO Base Address to 11 Figure 3 Example Set Counter Timer Base Address to 1 11 Figure 4 Example Route IRQA to PC 104 12 Figure 5 Example Connect IRQA to Pull down Resistor and Route to Shared IRQ5 12 Figure 6 Example Pull I O Pins Up to 5 0 13 Figure 7 Example Pull I O Pins Down to Ground mme 13 Diamond Systems Corporation GPIO MM User Manual Page 3 General Description Overview The GPIO MM is a PC 104 board featuring 48 Digital I O DIO lines 2 dual input quadrature encoders 14 external interrupt lines and software controlled interrupt capability The DIO and quadrature encoders functions are implemented in FPGA cores emulating dual 82C55A PPI and dual Avago HCTL 2001 encoder chips A 50 pin I O header provides for external DIO connections Direction on all ports is selected by programming control registers in the FPGA All I O lines are buffered with transceivers whose directions are controlled by logic that responds to the direction control values written to the registers Each line is capable of sinking 64mA in a logic low stat
11. direction for each auxiliary line Writing a 1 sets input mode writing a 0 sets output mode All I O states are set to 1 input at power on or reset AUX 3 0 OUT Sets the output level for each line Writing a 1 sets output high writing a 0 sets output low These bits are valid even if the port is currently in input mode and will determine the output level if the port is set to output mode Base 0E Read Interrupt Status Register Diamond Systems Corporation GPIO MM User Manual Page 19 PENES especie gene peg AUX3DIR AUX2DIR AUXIDIR AUXODIR AUX3IN AUX2IN AUXIIN AUXOIN This register is used to read the state of the auxiliary DIO lines Name Base OF Bit No Name Base OF Bit No Name Write Board Reset Register AUX 3 0 DIR Reads back the direction for each auxiliary line A 1 indicates input mode a 0 indicates output mode AUX 3 0 IN Reads back the input level for each line A 1 indicates the input level is high a 0 indicates the input level is low If the port is currently in output mode the read back value corresponds to the current output level BRDRST ID7 Read ID Code Register BRDRST Writing a 1 to this register initiates a board reset performing the same initialization as an external reset pulse a a wc 2 qq e 1 4 ID3 ID2 ID1 IDO ID 7 0 Reads back the personal
12. two 82C55A PPI chips This gives a total of 48 bidirectional DIO lines The J4 pins can be configured to pull up to 5V or pull down to ground using jumper J11 as described in Section 4 Board Configuration Line Pull up pull down Selection Port 1A7 Port 1A6 Port 1A5 Port 1A4 Port 1A3 Port 1A2 Port 1A1 Port 1A0 Port 1B7 Port 1B6 Port 1B5 Port 1B4 Port 1B3 Port 1B2 Port 1B1 Port 1BO Port 1C7 Port 1C6 Port 1C5 Port 1C4 Port 1C3 Port 1C2 Port 1C1 Port 1CO 5V 4 5 6 yg 9 10 13 14 15 16 17 18 19 20 21 22 230024 25 26 27 28 29 30 y 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Port 2A7 Port 2A6 Port 2A5 Port 2A4 Port 2A3 Port 2A2 Port 2A1 Port 2A0 Port 2B7 Port 2B6 Port 2B5 Port 2B4 Port 2B3 Port 2B2 Port 2B1 Port 2 Port 2C7 Port 2C6 Port 2C5 Port 2C4 Port 2C3 Port 2C2 Port 2C1 Port 2CO Ground NOTE The connector is labeled Port 2 which should not be confused with DIO ports A B and C and the fixed direction TTL ports Diamond Systems Corporation GPIO MM User Manual Page 6 Signal Description Port 1A0 Port 1A7 8255 1 Port A bits 0 7 Port 1B0 Port 1B7 8255 1 Port B bits 0 7 Port 1C0 Port 1C7 8255 1 Port C bits 0 7 Port 2A0 Port 2A7 8255 2 Port A bits 0 7 Port 2B0 Port 2B7 8255 2 Port B bits 0 7 Port
13. 3 0 output 1 input Reset value Port B direction Sets the direction of the port B I O signals 0 output 1 input Reset value Group B mode selection Sets the mode of operation for the group B signals 0 mode 0 lt Reset value 1 mode 1 NOTE 1 Only mode 0 is currently implemented 2 All output registers are reset when the mode is changed Port C upper direction Sets the direction of the port C I O signals 4 7 0 output 1 input Reset value Port A direction Sets the direction of the port A I O signals 0 output 1 input Reset value Group A mode selection Sets the mode of operation for the group B signals 00h mode 0 lt Reset value 01h mode 1 Ixh mode NOTE 1 Only mode 0 is currently implemented 2 All output registers are reset when the mode is changed Mode set flag Selects the port configuration mode 0 Bit set reset control register mode Diamond Systems Corporation GPIO MM User Manual Page 21 DIO Base 03h 8255 1 DIO Base 07h 8255 2 When MSFLAG is reset this register is used to set reset individual Port C bits 1 Basic mode definition control register mode Reset value When MSFLAG 15 set this register is used for direction and mode selection NOTE When the control word is read the value of MSFLAG is always 1 implying basic control word information is being read Diamond Systems Corporation GPIO MM User Manual Page 22 8255 Control and Status
14. 4 DIAMOND SYSTEMS CORPORATION GPIO MM User Manual FPGA based PC 104 Counter Timer and Digital Module User Manual v1 0 Personality 0x22 Copyright 2006 1255 Terra Bella Ave Mountain View CA 94043 Tel 650 810 2500 Fax 650 810 2525 www diamondsystems com Diamond Systems Corporation GPIO MM User Manual Page 1 Table of Contents DESCripti ee A VS ES ccs 4 Digital l O Features 4 Counter Timer Features et REL o ie not en os etes de 4 Enhanced Featufes c Aceon ste gh etd Load tatu uides acento Ls adele 5 Board AY OU e e oiis 5 deg Greed p tue ib eb ice a eec pa ceder iL iiec 5 VO Connector PIDOUl nci epaiari edic eee elect ete ete 6 Digital O Header qa eq a aliaa etc 7 Counter timer Header oe op lei too bed e atre du UO eles 8 Auxiliary Header PINOUT dier border ades t eie oat Pera e 9 Board Configiralion eti HII cao ce cetera NE eect 10 Base Address Selector ete eo ua dete bg tle ed tabo dig asecotuet ius 11 Interrupt Level Selection eee nennen 11 I O Line Pull up Pull down 12 13 OV EIVIGW cec o
15. POL EICIEN Encoder 1 Counter Interrupt Enable A 1 turns on the interrupt generation whenever Encoder 1 Counter increments A 0 turns off the function E2CIEN Encoder 2 Counter Interrupt Enable A 1 turns on the interrupt generation whenever Encoder 2 Counter increments A 0 turns off the function EXIIEN External Interrupt 1 Enable A 1 turns on the interrupt generation whenever the External interrupt pin changes state in the direction set by the polarity bit below A 0 turns off the function EXIIPOL External Interrupt 1 Polarity A 1 sets positive polarity pulses to generate the external interrupt A 0 sets negative polarity pulses EXI2EN External Interrupt 2 Enable A 1 turns on the interrupt generation whenever the External interrupt pin changes state in the direction set by the polarity bit below A 0 turns off the function EXI2POL External Interrupt 2 Polarity A 1 sets positive polarity pulses to generate the external interrupt A 0 sets negative polarity pulses Base 5 Read Encoder EXT 1 6 Interrupt Status Register Indicates what is the source of the most current interrupt generating Interrupt A to the PC104 Bus If multiple interrupts occur simultaneously then all are indicated at the same time Diamond Systems Corporation GPIO MM User Manual Page 15 Bit No Name Base 6 Bit No Name Base 6 aa eee
16. Registers Bit SET RESET Mode MSFLAG 0 DIO Base 03h 8255 1 DIO Base 07h 8255 2 Bit 7 6 5 4 3 2 1 0 Name MSFLAG BSEL SET SET Bit set reset individual command 0 reset 1 set BSEL Port C bit select 0 bit 0 1 bit 1 2 bit 2 3 bit 3 4 bit 4 5 bit 5 6 bit 6 7 017 MSFLAG Mode set flag Selects the port configuration mode 0 Bit set reset control register mode When MSFLAG is reset this register is used to set reset individual Port C Bits 1 Basic mode definition control register mode When MSFLAG is set this register is used for direction and mode selection NOTE When the control word is read the value of MSFLAG is always 1 implying basic control word information is being read Diamond Systems Corporation GPIO MM User Manual Page 23 Quadrature Encoder and External Interrupts For more information on the Programming Quadrature Encoder and Programming External Interrupts refer to DSC Document 0700052 Application Programming Note GPIO MM FPGA for Position Encoder 48 I O Personality 0x22 Diamond Systems Corporation GPIO MM User Manual Page 24 Programming Digital I O 48 bit Programmable Direction 8255 GPIO MM provides 48 DIO lines using an FPGA core implementation of two 82C55A devices 82C55A 1 and 82C55A 2 The DIO functionality includes 48 programmable direction lines and 8 fixed inputs and 8 fixed outputs The 48 programmable I O lines are buf
17. TL 2001 Encoder datasheet 2 82C55A CMOS Programmable Peripheral Interface Harris Semiconductor March 1997 Diamond Systems Corporation GPIO MM User Manual Page 27
18. e or sourcing 15mA in a logic high state The board requires only 5V for operation DIO headers are organized to allow direct interfacing to OPTO 22s isolated I O racks including the G4 series the PB16 H J K L PB8H and the PB24HQ These racks and I O modules allow up to 3000 VRMS isolation between the computer and the user s signals All control signals power and ground on the DIO header match the corresponding signals on these I O racks so a single 50 pin ribbon cable such as Diamond Systems C50 18 is all that is needed to make the connection The GPIO MM provides access to interrupt levels 3 7 10 12 and 15 on the PC bus for real time background applications Interrupts provide a means for transferring data into or out of PC memory under external control Using interrupts allows background operation where I O can be performed while the PC is executing another task such as running an unrelated applications program This feature is useful for performing I O at a controlled rate since a counter output can be used to drive the interrupt request pin on the I O header at a periodic rate for a user supplied interrupt service routine that performs whatever function is necessary in response to the interrupt Digital I O Features e Dual 82C55A Parallel Peripheral Interfaces PPI logic implemented in FPGA cores e Each 82C55A has three 8 bit I O ports for a total of 48 DIO lines which connect to a 50 pin header for external connections
19. f I O address space as described in Section 5 Map Jumper the locations as shown to set the 8255 and 9513 base addresses VO 2 3 4 5 4 DIO Pins Address 6 7 8 9 lt Pins 0040h Out In In In 0080h In Out In In 00COh Out Out In In 0100h In In Out In 0140h Out In Out In 0180h In Out Out In 01COh Out Out Out In 0200h In In In Out 0240h Out In In Out 0280h In Out In Out 02COh Out Out In Out 0300h In In Out Out 0340h Out In Out Out 0380h In Out Out Out 03COh Out Out Out Out NOTE Different address must be selected for the DIO and counter timer functions The example below selects a DIO base address of 0040h Figure 2 Example Set DIO Base Address to 0040h crc 1 1 9876543210 The following example selects counter timer base address of 0100h Figure 3 Example Set Counter Timer Base Address to 0100h crc 91 901 1 1 le e efle e e e e e Diamond Systems Corporation GPIO MM User Manual Page 10 Interrupt Level Selection Jumper J7 is used to switch the IRQA interrupt and jumper J9 is used to switch the IRQB interrupt PC 104 lines that can be selected are IRQ3 to IRQ7 IRQIO to IRQ12 and IRQ15 The examples shown below also apply to the J9 jumper block for IRQB The example below shows J7 jumpered to route IRQA to PC 104 IRQS Figure 4 Example Route
20. fered for enhanced output current while the fixed I O and the counter timer signals feature ESD protective circuitry All I O lines contain jumper selectable 10Kohm pull up pull down resistors Operation of the 82C55A FPGA core should be as described in the 82C55A PPI datasheet Refer to the 82C55A datasheet Additional Information for detailed register and programming information The 82C55A has three parallel I O ports Ports A and B are 8 bit bi directional I O ports Port C is divided into two 4 bit bi directional I O ports For programming the ports are arranged into two groups as shown below Port Group Description A 8 bits of Port A and upper 4 bits 4 7 of port C B 8 bits of Port B and lower 4 bits 0 3 of port C NOTE The port groups can be separately configured for different operating modes However GPIO MM only implements operating mode 0 which provides simple bidirectional I O without handshaking Port C bits may be individually set and reset by setting the MSFLAG in the 8255 Control and Status Register and programming the remaining register bits for the desired bit state Setting the 8255 Control and Status Register to the following values gives 16 possible I O configurations Status and Control Register Bits Group A Group B PADIR PCUDIR PBDIR PCLDIR Port A PortC PortB Port C upper lower 0 0 0 0 Output
21. g Dade KO REIR 14 Counter Timer and Enhanced Feature 14 DOs PROGRAMING eee ec Tm 15 Register Bit Descriptions nieder n desit leder cedo et 16 9513 Command and Status Dad scoop eo 16 9513 Command and Status Data Pointer 16 9513 DIO Data Regis els cote er ette bebe tee shes es edepol etn 16 9513 Interrupt Control ISeglslels c ore ses oc ope ee Ceo il ee eese Come tote Phe 17 EEPROM D lta Reglsler cii teo sepu eet 17 EEPROM Address Register eese cesses tenen cuna n 17 EEPROM Control and Status 18 FPGA Revision Code Register ee 18 Interr pt SOURCE e bie reperto eee ee ese 19 Interrupt Control and Status 15 20 Auxiliary DIO Control and Status 20 Board Reset and ID eo bead oes een desee diee t epus dca o p 21 B255 Dala Registers iue o pee pte s IU ULIS UN icr 21 8255 Control and Status Registers Basic Mode Definition MSFLAG 1 22 8255 Control and Status Registers Bit SET RESET Mode MSFLAG2 0O 23 Quadrature Encode
22. gramming Sixteen registers are used for counter timer and enhanced feature programming Offset Write Function Read Function 00h Encoder 1 amp 2 Control Settings Encoder 1 amp 2 Control Readback Olh Encoder 1 Counter low byte Encoder 1 Counter low byte 02h Encoder 1 Counter high byte Encoder 1 Counter high byte 03h Encoder 2 Counter low byte Encoder 2 Counter low byte 04h Encoder 2 Counter high byte Encoder 2 Counter high byte 05h Encoder Ext interrupt control Encoder Ext interrupt status 06h Ext interrupt control Ext interrupt status 07h Ext interrupt control 08h Ext interrupt control 09h EEPROM Data EEPROM Data EEPROM Address EEPROM Address OBh EEPROM Control FPGA Revision OCh Master Interrupt Circuit Selection Master Interrupt Circuit Read back 0Dh Master Interrupt Control Master Interrupt amp EEPROM Status OEh Auxiliary DIO Control Auxiliary DIO Read back OFh Board Reset Board ID Read back Diamond Systems Corporation GPIO MM User Manual Page 13 1 1 Map Details Block 1 Quadrature Encoder Enhanced Features This section describes the location and general behavior of specific bits in each I O map register This does not go into specific signal behavior for which there are detailed descriptions in future sections In all register definitions below a bit named X or blank is not defined and serves no function Unused bits should return 0
23. ity ID code for this FPGA The value is hardcoded as 0x22 1 2 I O Map Details Block 2 1 2 1 GMM Registers These four registers map directly to the first 8255 core Base 4 Base 4 Base 4 Base 4 These Base 4 Base 4 Base 4 0 Read Write Read Write 2 Read Write F3 Read Write DIO Control Register four registers map directly to the second 8255 core 4 Read Write F5 Read Write 6 Read Write Base 4 7 Read Write DIO Control Register Diamond Systems Corporation GPIO MM User Manual Page 20 8255 Data Registers DIO Base 00h 8255 1 Port A DIO Base 04h 8255 2 Port A DIO Base 01h 8255 1 Port B DIO Base 05h 8255 2 Port B DIO Base 02h 8255 1 Port C DIO Base 06h 8255 2 Port C Bit 7 6 5 4 3 2 1 0 Name DATA DATA 8 bit parallel data On reset the port is set to input mode and the port is held at a logic level until the reset signal is removed The port remains in input mode until changed using the control register Following a reset all lines are set to input mode 8255 Control and Status Registers Basic Mode Definition MSFLAG 1 DIO Base 03h 8255 1 DIO Base 07h 8255 2 Bit 7 4 3 2 0 Name MSFLAG MSELA PADIR PCUDIR MSELB PBDIR PCLDIR PCLDIR PBDIR MSELB PCUDIR PADIR MSELA MSFLAG Port C lower direction Sets the direction of the port C I O signals 0
24. n or board reset are IRQA 0 IRQB 12 11 Unused GMM side 8255 2 Diamond Systems Corporation GPIO MM User Manual Page 18 Base OD Write Interrupt Control Register x E Ns IROBEN IRQBDIS IROBCLR IRQAEN IRQADIS IRQACLR This is a command register Commands are issued by writing a 1 to specific bits More than one bit can be written to at a time If both enable and disable are called simultaneously the IRQ will be disabled IRQ B A CLR Clears the interrupt flip flop for IRQ B A This must called each time IRQ B A occurs to reset the output state of the IRQ line IRQ B A DIS Disable IRQ B A IRQ B A EN Enable IRQ B A Base 0D Read Master Interrupt amp EEPROM Status Register Bue Name EEBUSY IRQBSTS IRQASTS EEBUSY EEPROM busy indicator 0 not busy 1 busy IRQ B A STS Reads back as a 1 if that IRQ has triggered This can only be cleared to 0 by issuing a IRQ B A RST command Base 0E Write Auxiliary DIO Control Register mue ae nod Name AUX3DIR_ AUX2DIR AUXIDIR JAUXODIR AUX3OUT AUX2OUT AUX1OUT AUX0OUT This register is used to change the input output state and the output levels of the auxiliary DIO lines All output levels are set to 0 low on power on or reset AUX 3 0 DIR Sets the
25. nhanced Feature Registers Base 9 Read Write EEPROM Data Register sip sse Name D7 D6 D5 D4 D3 D2 D1 DO D7 0 Data to be read or written to the EEPROM For EEPROM write operations the data written to this register will be written to the EEPROM For EEPROM read operations this register contains the data read from the EEPROM and is valid after EEBUSY 0 Base 0A Read Write EEPROM Address Register Bees Mep e Oe fl 7 5 4 A3 A2 Al AO A7 A0 EEPROM address Base 0B Write EEPROM Control Register Diamond Systems Corporation GPIO MM User Manual Page 17 Name EE EN EE RW EE EN EEPROM Enable Writing a to this bit will initiate a transfer to from the EEPROM as indicated by the EE_RW bit EE RW Selects read or write operation for the EEPROM 0 Write 1 Read Writing to this register initiates an EEPROM read Writing 0x80 initiates an EEPROM write Base 0B Read FPGA Revision Code This register returns the revision code of the FPGA This code starts at 0 10 1 0 Base 0C Read Write Interrupt Source Selection Register ve a a zeclp sm Name IRQB3 IRQB2 IRQBI IRQBO IRQA3 IRQA2 IRQAI IRQAO IRQ B A 3 0 Forms a 4 bit value from 0 to 15 that determines the interrupt source for IRQA and IRQB Defaults after power o
26. nnector is labeled Port 1 which should not be confused with DIO ports A B and C and the fixed direction TTL ports Diamond Systems Corporation GPIO MM User Manual Page 8 Signal Description In 1 lt A B gt the A and B inputs of Quadrature Encoder 1 and are standard TTL input lines In 2 lt A B gt the A and B inputs of Quadrature Encoder 2 and are the standard TTL input lines Ext IRQ 1 147 Are dedicated interrupt input lines and can be selected as a source for IRQ trigger 5V 5 volt DC from the PC 104 bus Ground Digital ground from the PC 104 bus Auxiliary Header Pinout The auxiliary I O header J5 is provided for bidirectional TTL level general purpose I O 1 AUXIO 0 2 AUXIO 1 3 AUXIO 2 4 AUXIO 3 5 GND Card Voltage Type Pin Configuration AUXIO 0 AUXIO 3 Four bidirectional TTL level general purpose I O signals GND Ground Diamond Systems Corporation GPIO MM User Manual Page 9 Board Configuration Base Address Selection Jumper J10 positions 2 5 is used to configure the base address of the DIO 8255 registers The 8255 register map occupies 8 bytes of I O address space as described in Section 5 I O Map Jumper positions 6 9 is used to configure the base address of the counter timer I O 9513 registers and the enhanced features registers The 9513 register map occupies 16 bytes o
27. r and External Interrupts csse 24 Diamond Systems Corporation GPIO MM User Manual Page 2 Programming the eene nnn nnn 24 M Dc MY 24 Accessing the Counter Timer Internal 24 Master Mode Reglsier 4 3 te eer piso c n RR e 24 Counter Mode Reglster cede Ue eat irent ene nl ER ta ese da 24 avidis Tr 24 FOUT Brequency 24 Counter 2 pua uoce etna st 24 Counter PROGRAMING adu in redd o veces Eee cte tnra o IR oe eee et 25 Programming Digital l Q rro Ro in p ical te Lade nn 25 48 bit Programmable Direction 8255 seen 25 16 bit Fixed Direction 9513 es cea arta eet eno eared tele cere 25 Programming Enhanced 26 EEPROM Programming eut eed otio Se diet Ma aea E Dd is uei 26 Specification S fmm erect 26 General SPSCHICATONS gt acces area bun eser Ee dea rk ete cpu oa id 26 Additional Information eroe iere Eee e coeur ec E oa ass seo eee 27 M T M IO 27 Technical SUDDOLH c coo oma e idis eate
28. y writing the address to the EEPROM Address Register 09h 2 Set the data transfer direction to read by setting the EE RW bit in the EEPROM Control and Status Register OAh 3 Reset the EE EN bit in the EEPROM Control and Status Register OAh to initiate the read operation 4 Test the EEPROM Control and Status Register OAh EEBUSY bit to determine that the data transfer has completed When EEBUSY is zero a valid data byte is available and the next byte may be read Specifications General Specifications Base FPGA Xilinx Spartan II 200 000 gates 40K RAM bits Input clock 40MHz e FPGA code storage Flash memory field upgradeable via JTAG ID indicator 8 bit LED display indicates FPGA code personality field upgradeable via JTAG e Counter timers 10 16 bits using 2 CTS9513 cores Maximum counting frequency 40MHz e Programmable 48 using 2 82C55A cores e Output current buffered I O Logic 0 64mA max per line buffered I O Logic 1 15mA max per line Output current fixed I O and counter timers 24mA max Dimensions 3 55 x 3 775 PC 104 form factor e PC 104 bus 16 bit stackthrough ISA bus e Power supply 5VDC 5 Operating temperature 40 to 85 C e Weight 2 20z Diamond Systems Corporation GPIO MM User Manual Page 26 Additional Information Datasheets Datasheets provide programming reference information for the counter timer and DIO functions 1 Avago Technologies HC
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