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(Exynos 4412) datasheet

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1. Number of VD Figure 16 19 32 BPP 8 8 8 8 Palette Data Format SAMSUNG ELECTRONICS 16 23 ex 4412 UM 16 Display Controller Figure 16 20 illustrates the 25 BPP A 8 8 8 palette data format INDEX Bit Pos Number of VD Figure 16 20 25 BPP A 8 8 8 Palette Data Format Figure 16 21 illustrates the 19 A 6 6 6 palette data format INDEX Bit Pos 00h Figure 16 21 19 BPP A 6 6 6 Palette Data Format SAMSUNG ELECTRONICS 16 24 27 4412 UM 16 Display Controller Figure 16 22 illustrates the 16 A 5 5 5 palette data format INDEX Bit Pos Figure 16 22 16 BPP 5 5 5 Palette Data Format SAMSUNG ELECTRONICS 16 25 ITT 4412 UM 16 Display Controller 16 3 4 2 Palette Read Write You should not access palette memory when the Vertical Status VSTATUS register has an ACTIVE status You should check the VSTATUS to do Read Write operation on the palette 16 3 5 Window Blending This section includes e O
2. lt e H lat e lt Pe PS Se Pc 0 P Pc C Pe S Px F lt x PX PX SC SC S lt S lt S lt S lt S lt x IN SPAN X 13 CAN X 13 gt SCAN Y 0 SCAN 0 IX P P P P ISSN lt Scan Procedure S W make one output LOW the others HIGH and Read KEYIN SCAN Y 7 SCAN 7 Figure 17 4 Keypad Scanning Procedure ll SAMSUNG ELECTRONICS 17 5 4412 UM 17 Keypad Interface Figure 17 5 illustrates the keypad scanning procedure gt gt write 11111101111111 know 7th row and 4th column ke MINN INE ORE resse When 2 key different rows Pressed case KEYIN 2bits are LOW But interrupt occuring timing is different z z z r x ms y y y y y y Y y gt gt 2 gt 2 x P S CAN X13 SCAN Y 0 X 13 SCAN Y 0 SCAN 7 Figure 17 5
3. 8 2 8 3 Register Description erret obiret tet EE 8 5 8 3 1 Register Map 8 5 saute suze 8 14 9 SROM CONTROLER ane E dava 9 1 9 1 9 1 UAM 9 1 9 3 Block DIA EEE EE 9 1 9 4 Functional Description S 9 2 9 4 1 AWAIT Pin Operation AA e 9 2 9 4 2 Programmable Access Cycle 9 3 9 5 1 0 Description E 9 4 9 6 Register Descriptio c 9 5 9 6 1 Register Map 9 5 SAMSUNG ELECTRONICS ex 10 NAND FLASH CONTROLLER 10 1 ngo 10 1 10 2 a ET een hee 10 1 10 3 Functional DE 10 2 10 31 Block Diagram 2 2 10 2 10 3 2 Flash Memory 0 10 3 10 4 Software a nr 10 4 10 4 1 Data Register Configuration n rra 10 4 10 4 2 1 4 8 12 T6 DIE EGG einer i einen Geen Eee aie 10 5 10 4 3 2048 Byte 1 bit ECC Code Assignment 10 6 10 4 4 32 Byte 1 bit ECC Code Assignment
4. 10 6 10 4 5 1 bit ECC Module Features 10 6 10 4 6 1 bit ECC Programming 10 7 10 4 7 4 bit ECC Programming Guide ENCODING 10 8 10 4 8 4 bit ECC Programming Guide 10 9 10 4 9 8 12 16 bit ECC Programming Guide 10 10 10 4 10 8 12 16 bit ECC Programming Guide 4 seen 10 11 10 4 11 ECC Parity Conversion Code Guide for 8 12 16 bit 10 12 10 4 12 Lock Scheme for Data Protection eene 10 13 10 5 Programming Constraints 10 14 10 6 Description x E a 10 14 10 7 Register DESCTIPlON T 10 15 10 7 1 Register Map 10 15 10 7 2 Flash Interface and 1 4 bit ECC 10 17 10 7 3 ECC Registers for 8 12 and 16 bit 10 29 11 PULSE WIDTH MODULATION TIMER 11 1 APP MA INA 11 1 Tl 2 proq oido 11 4 EP o aa 11 5 11 3 1 Prescaler and lt iia 11 5 11 3 2 Basic Timer Operation eee td id ii Eur pedes 11 6 11 3 3 Auto Reload and Double 11 8 11 3 4 Timer Operation Exam ple
5. 16 43 Timing Reference Code XY 16 46 I O Signals of Display 16 47 Keypad Interface I O 17 10 SAMSUNG ELECTRONICS ex List of Ekamples Example Title Page Number Number Example 16 1 Application I eddie 16 26 Example 16 2 Total Five WINO WI L uuu l wa 16 26 Example 16 3 Blending 16 27 Example 16 4 Default Blending Equation 16 28 Example 16 5 Window Blending Factor 3 3 16 30 Example 16 6 Hue Equation omic td ds ii ipod Dee EUR d 16 119 Example 16 7 Coefficient Decision SAMSUNG ELECTRONICS ex List of Conventions Register RW Access Type Conventions Type Definition Description R Read Only The application has permission to read the Register field Writes to read only fields have no effect W Write Only The application has permission to write in the Register field RW Read amp Write The application has permission to read and writes in the Register field The application sets this field by writing 1 b1 and clears it by writing 1 bO Register Value Conventions Expression Description x Undefined bit Undefined multiple bits 2 Undefined but depends on the device or pin status Device dependent The value depend
6. 13 0 18 3 UART ro 13 1 13 31 Data AA 13 2 1332 Data AAA Er ee 13 2 Q 13 3 13 3 4 Example of Non AFC Controlling nRTS nCTS by Software 13 4 13 3 5 Trigger Level of Tx Rx FIFO and DMA Burst Size in DMA Mode 13 4 13 3 6 2320 Interface rer eh east xin reno Raga gestu tit 13 4 13 3 7 Interrupt DMA Request Generation L nnne 13 5 13 3 8 UART Error Status FIFO iii ita 13 7 19 4 Input Glock Description cootra 13 10 13 5 00 Description a uu u un Pr tee 13 11 13 6 Register AERE n istad 13 12 13 6 1 Register Map 13 12 14 INTER INTEGRATED CIRCUIT 14 1 DEO e aia 14 1 14 2 II SAA AAA AA AA AA AA AWA AAA AAA 14 2 14 3 Functional Desoriplleh aaa 14 2 14 3 1 Block Diagram AA 14 2 14 4 12C Bus Interface Operation 14 3 14 4 1 Start and Stop eene ire 14 4 14 4 2 Data Transfer Format eiii 14 5 14 4 3 Signal Transmission
7. 11 9 11 3 5 Initialize Timer Setting Manual Up Data and 11 10 113 6 PWM m 11 10 11 3 7 During Current ISR Interrupt Service Routine Output Level Control 11 11 11 3 9 Dead Zone GEN AA KA dace 11 12 11 4 VO ia 11 13 11 5 Register DESCAPlION ibas 11 14 11 5 1 Register Map nensi nenas 11 14 12 WATCHDOG TIMER 12 1 12 1 12 1 122 Features Gene 12 1 12 3 Functional Description AA 12 2 12 3 1 W DT 12 2 12 3 2 WTDAT and WTON 12 3 12 30 WD Start a 12 3 12 3 4 Consideration of Debugging 2 1 1 12 3 12 4 Register BI ele 12 4 SAMSUNG ELECTRONICS ex 12 4 1 Register Map 5 12 4 13 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER 13 1 13 1 uu u u u ua 13 1 13 2 AAA
8. 0 0274 2 GPMO power down mode pull up pull down 0 0000 GPY6PUD 0x01E8 Port group GPY6 pull up pull down register 0x5555 ETCODRV 0 020 Port group ETCO drive strength control register 0x00_0000 SAMSUNG ELECTRONICS 4 12 4412 UM 4 General Purpose Input Output GPIO Control GPM1CONPDN 0x0290 Port group GPM1 power down mode configuration register 0x0000 GPM1PUDPDN 0 0294 en GPM1 power down mode pull up pull down 0 0000 GPM2PUDPDN 0x02B4 GPM2 power down mode pull up pull down 050000 GPM3CON 0x02C0 Port group GPM3 configuration register 0x0000_0000 GPM3DAT 0x02C4 Port group GPM3 data register 0 00 GPM3PUD 0x02C8 Port group GPM3 pull up pull down register 0x5555 0x0000 GPM3DRV 0x02CC Port group GPM3 drive strength control register 0x00_0000 GPM3CONPDN 0 0200 Port group GPM3 power down mode configuration register 0 0000 GPM3PUDPDN 0 0204 dl GPM3 power down mode pull up pull down 0 0000 GPM4CON 0x02E0 Port group configuration register 0x0000_0000 GPM4DAT 0x02E4 Port group GPM4 data register 0 00 GPM4DRV 0 02 Port group GPM4 drive strength control register 0x00_0000 GPM4PUD 0x02E8 Port group pull up pull down register 0x5555 GPM4CONPDN 0x02F0 Port group GPM4 power down mode configuration register 0 0000 GPM4PUDPDN 0 02 4 aS GPM4 power down mode pull up pull down 0x0000 EXT_INT23_CON 0x0708 External inter
9. 3 1 field indicates type or kind of the pad whether it is dedicated to signal or connected to multiplexed signals 2 VSYNCEN register controls VSYNC_LD signal 3 FIRMEN control register controls LCD FRM signal SAMSUNG ELECTRONICS 16 47 ex 4412 UM 16 Display Controller 16 5 Register Description Overview The registers you can use to configure display controller are 1 2 20 21 22 23 VIDCONO Configures video output format and displays enable disable VIDCON1 Specifies RGB I F control signal VIDCON2 Specifies output data format control VIDCONS Specifies image enhancement control I80IFCONx Specifies CPU interface control signal VIDTCONx Configures video output timing and determines the size of display WINCONx Specifies each window feature setting VIDOSDxA VIDOSDxB Specifies window position setting VIDOSDxC D Specifies On Screen Display OSD size setting VIDWxALPHAO0 1 Specifies alpha value setting BLENDEQx Specifies blending equation setting VIDWxxADDx Specifies source image address setting WXKEYCONXx Specifies color key setting register WxKEYALPHA Specifies color key alpha value setting WINxMAP Specifies window color control GAMMALUT_xx Specifies gamma value setting COLORGAINCON Specifies color gain value setting HUExxx Specifies Hue coefficient and offset value setting
10. 2 RSVD 1 Enables E RSVD 3 neve EN Clears the corresponding interrupt enable bit to oo CPU_nIRQOUT 0 13 you clear the interrupt enable bit interrupt combiner will RSVD 12 R mask the interrupt RSVD 1 Write 0 Does not change the current setting 1 Clears the interrupt enable bit to RSVD 10 Read The current interrupt enable bit 1 Enables RSVD 8 9 G2 Clears the corresponding interrupt enable bit to 0 If Gi you clear the interrupt enable bit interrupt combiner will 5 mask the interrupt MCT_GO RW Write 0 Does not change the current setting O RSVD 3 2 1 Clears the interrupt enable bit to 0 ___0 Read The current interrupt enable bit o 1_ 51 1 RW MPLHS m kaa fo NE TE a UART4 1 Enables aw SAMSUNG ELECTRONICS 7 23 4412 UM 7 Interrupt Combiner 7 6 2 15 ISTR3 Base Address 0x1044 0000 e Address Base Address 0x0038 Reset Value Undefined DEGERRINTR R MESSEN SLVERRINTR mo ERRRDINTR 29 EN Interrupt pending status ERRRTINTR 28 EN The corresponding interrupt enable bit does not affect this pending status mer 27 L4 0 The interrupt is not pending ERRWTINTR 26 1 The interrupt 5 pending EONTRINTR pec
11. 4412 UM 14 Inter Integrated Circuit Figure 14 8 illustrates the operations for Slave Transmitter mode START Slave mode has been configured 12C detects start signal and 12205 receives data 2 compares I2CADD and I2CDS the received slave address The 12C address match interrupt is generated Clear pending bit to resume N The data of the I2CDS is shifted to SDA Y Write data to 12CDS Y Interrupt is pending Figure 14 8 Operations for Slave Transmitter Mode SAMSUNG ELECTRONICS 14 10 II 4412 UM 14 Inter Integrated Circuit Figure 14 9 illustrates the operations for Slave Receiver Mode Slave Rx mode has been configured 12C detects start signal and 12CDS receives data 2 compares I2CADD and I2CDS the received slave address The 12C address match interrupt is generated Read data from I2CDS Clear pending bit to resume SDA is shifted to I2CDS Interrupt is pending Figure 14 9 Operations for Slave Receiver Mode SAMSUNG ELECTRONICS 14 11 ex 4412 UM 14 Inter Integrated Circuit 14 5 I O Description NOTE The 2 bus interface for the HDMI has no external I O SAMSUNG ELECTRONICS 14 12 ex 4412 UM 14 6 Register Description 14 6 1 Register Map Summary Base Address Base Address Base Address Base Address Base Address Base Address Base Address Base Address Base Address
12. Reset Value 0 0000 0400 GAMMALUT 64 SAMSUNG ELECTRONICS 16 131 ex Se I 4412 UM 16 Display Controller GM_LUT_x 26 18 Specifies Gamma LUT value register of index x Undefined GM_LUT_y 10 2 Specifies Gamma LUT value register of index y Undefined SAMSUNG ELECTRONICS 16 132 ex 4412 UM 16 Display Controller 16 5 4 2 Gamma LUT Data for 16 Step Mode Base Address 0x11C0_0000 e Address Base Address 0 037 Reset Value 0 0010 0000 GAMMALUT 1 0 e Address Base Address 0X0380 Reset Value 0X0030 0020 GAMMALUT 3 2 e Address Base Address 0X0384 Reset Value 0X0050 0040 GAMMALUT_R_5 4 e Address Base Address 0X0388 Reset Value 0 0070 0060 GAMMALUT R 7 6 e Address Base Address 0 038 Reset Value 0 0090 0080 GAMMALUT_R_9 8 e Address Base Address 0X0390 Reset Value 0 00 0 00A0 GAMMALUT_R_11_10 e Address Base Address 0X0394 Reset Value 0X00D0 00C0 GAMMALUT_R_13_12 e Address Base Address 0 0398 Reset Value 0 00 0 00 0 GAMMALUT R 15 14 e Address Base Address 0 039 Reset Value 0 0110 0100 GAMMALUT 16 e Address Base Address Reset Value 0X0130 0120 GAMMALUT_R_1_0 e Address Base Address 4 Reset Value 0X0150_0140 GAMMALUT 3 2 e Address Base Address 0X03A8 Reset Value 0 0170 0160 GAMMALUT_R_5 4 e Add
13. G LE 17 81 RW Species Green Alpha lower vale Gas 0 0 mw ra __ ALPHA BL F G0 RW Species Blue Apra lower vale ase AEN 0 0 NOTE ALPHAO R G B 7 4 ALPHA0_R G B _H 3 0 atVIDOSD2C ALPHA0_R G B 3 0 ALPHA0_R G B _L 3 0 at VIDW2ALPHA0 SAMSUNG ELECTRONICS 16 121 x 4412 UM 16 Display Controller 16 5 3 75 VIDW2ALPHA1 e Base Address 0x11C0_0000 e Address Base Address 0x0230 Reset Value 0x0000_0000 Nam Type Besciion Reset value Ro Remd 9 Reewd 19 16 Specifies Red Alpha lower value case AEN 1 msaa Reseved 11 8 Specifies Green Alpha lower value case 1 0 mo ma ee fo B L F 3 0 RW Specifies Blue Alpha lower value case AEN 1 NOTE ALPHA1_R 7 4 ALPHA1_R B _H 3 0 at VIDOSD2C ALPHA1_R 3 0 ALPHA1_R G L 3 0 at VIDW2ALPHA1 16 5 3 76 VIDW3ALPHAO e Base Address 0x11C0_0000 e Address Base Address 0x0234 Reset Value 0x0000_0000 Besciion Reset Value sw ea Rewa 9 _ Reserved 10 19 16 Specifies Red Alpha lower value case AEN 0 11 8 Specifies Green Alpha lower value case 0 revo Rea fo gt ALPHAD B L F 13 01 RW Species Blue Alpha lower val
14. R Rvo interrupt pending status fF Rvo ____ If the corresponding interrupt enable bit is 0 the IMSR 0 The interrupt is not pending Rvo H 1 The interrupt is pending Ce sw ____ NECH ms fa Svo 1544 9 CPU O R Masked interrupt pending status La If the corresponding interrupt enable bit is 0 the IMSR RD bitreadsas 0 AA Rvo 0 The interrupt is not pending 1 The interrupt is pending RsvO a RsvO E mores p Lu EE poe MTS MEG 27 If corresponding interrupt enable bit 15 0 the IMSR bit reads as 0 0 The interrupt is not pending R 1 The interrupt is pending aa n R SAMSUNG ELECTRONICS 7 25 4412 UM 7 Interrupt Combiner 7 6 2 17 IESR4 e Base Address 0x1044 0000 e Address Base Address 0x0040 Reset Value 0 0000 0000 Name Bit Type Description Reset Value m o CPU nIRQOUT 3 30 Sets the corresponding interrupt enable bit to 1 If you the interrupt enable bit interrupt o PARITYFAILS Us 29 combiner serves the interrupt request PARITYFAIL3 28 RW Write 0 Does not change the current setting o CPU_nCTIIRQ 3 27 1 Sets the interrupt enab
15. m aw 097 Erber mewn 0 0 Enables Interrupt EXT INT31 MASK 1 1 0 1 Masked 0 0 Enables Interrupt EXT INT31 MASK 0 Rw 0 1 Masked SAMSUNG ELECTRONICS 4 333 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 52 EXT_INT32_MASK Base Address Ox106E 0000 e Address Base Address 0x0908 Reset Value 0x0000_00FF a EXT INT32 MASK 6 6 er 4 EXT INT32 MASK 5 5 gt _ 4 EXT 32 MASK 4 4 m c das ec mee m nw 90 Esl merum EXT INT32 MASK 2 2 n 0 0 Enables Interrupt EXT INT32 MASK 1 1 0 1 Masked 0 0 Enables Interrupt SAMSUNG ELECTRONICS 4 334 en 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 53 EKT INT33 MASK Base Address 0x106E_0000 e Address Base Address 0 090 Reset Value 0x0000_00FF 0 0 Enables Interrupt 0 0 Enables Interrupt EXT INT33 MASK 6 Rw 0 1 Masked 0x0 Enables Interrupt EXT INT33 MASK 5 5 0 1 Masked EXT_INT33 MASKI4 4 INT33 3 Sn EXT INT33 MASK 2 2 e Med did 0 0 Enables Interrupt EXT INT33 MASK 1 1 0 1 Masked 0 0 Enables Interrupt EXT INT33 MASK 0 m Rw 0 1 Masked 4 3 5 54 EXT_INT34 MASK e Base Address 0x106E_ 0000 e Address Base Address 0x0910 Reset Value 0x0000_0003 0x0 Enables Interrupt 0x0
16. 4412 UM 5 Clock Management Unit 5 10 1 133 APLL_CON1 e Base Address 0x1004 0000 e Address Base Address 0x4104 Reset Value 0x0080_3800 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x3 0x8 0 0 0 0 RSVD 31 25 A 24 when it detects a low signal RESVO 23 eos VCO range boost up when the signal is If BYPASS 1 bypass mode is enabled Four BYPASS 22 RW Fin If BYPASS 0 PLL3500X operates normally Decides whether the DCC is enabled or not DCC_ENB 21 RW It is an active low signal Decides whether AFC is enabled or not When AFC is enabled it calibrates VCO automatically AFC_ENB 20 RWX 0 Enables AFC 1 Disables AFC It is an active low signal Specifies status of Linear Region Detector LDR 0 Enables 1 Disables SE mee ub j FEED EN 16 Enable signal for FEED OUT LOCK CON OUT 15 14 m Lock detector settings of the output LOCK_CON_IN 13 12 Specifies Lock detector settings of the input margin LOCK 11 8 detector settings of the detection SE ms fm 60 RWX AFO vale AFC automatically selects adaptive frequency curve of VCO using switched current bank for wide range high phase noise or Jitter and fast lock time Refer to the sectin 5 4 1 Recommended PLL PMS Value for APLL and MPLL for recommended AFC ENB and AFC valu
17. SCAN Y 7 Keypad Scanning Procedure Ill SAMSUNG ELECTRONICS 17 6 4412 UM 17 Keypad Interface Figure 17 6 illustrates the keypad scanning procedure when the two key pressed with different row Key Press Interrupt Occure Key Release Interrupt Occu S W ISR proceed scanni SAN ISR set flag option procedure Pressed Key 5 5 filtered view 1 1 Row Key interrupt 1st Row Ke st Row Key interrupt SER pressed set to Released key sta detected row column 1st Row Key 2nd Row Key 2nd Row Key interrupt 2 Row 2 Row Key Interr S W in ISR pressed key is detected pressed stat set to Released ke S W detect when the 1st Row Key pressed s Figure 17 6 Keypad Scanning Procedure when the Two key Pressed with Different Row SAMSUNG ELECTRONICS 475 ITT 4412 UM 17 Keypad Interface Figure 17 7 illustrates the keypad block diagram Debouncing Filte FLT CLK 2 filter clock KEYIFFC _ WAKEUP_INT_EN 10 bit Counter OSCIN clock 12MHz Or USB_XTI 48MHz KEY_WAKEUP_INT from ALIVE block SCAN_X 13 0 KEYFLTO Interrupt Positive KEYFLT1 One pulse keypress Keyrelease control signals KEYFLT 13 bus Interface SFR Write Read SCAN Y 7 0 Figure 17 7 Keypad I F Block D
18. 100 160 133 freq freq freq freq freq SCLK_ONENAND e MAUDIO clocks RP_CLK freq BUS of MAUDIO_BLK freq freq freq freq freq freq 2 5 Clock Management Unit MOUTCORE n where 1 16 ARMCLK n where 1 to 8 ARMCLK n where n 1 to 8 ARMCLK n where n 1 to 8 MOUTCORE n where n 1 to 8 ATCLK n where n 1 to 8 freq MOUTDMC BUS where 1 to 8 freq SCLK DMO n where n 1 to 8 freq ACLK where n 1 to 8 freq ACLK_ACP n where 1 to 8 freq MOUTC20 n where n 1 to 8 freq MOUTDMC BUS n where 1 to 8 freq SCLK_C2C n where n 1 to 8 freq MOUTGDL n where n 1 to 8 freq ACLK GDL n where n 1 to 8 freq MOUTGDR n where n 1 to 8 freq ACLK GDR n where n 1 to 8 freq freq freq freq freq freq MOUTACLK_400_mcuisp n where n 1 to 8 MOUTACLK_200 n where n 1 to 8 MOUTACLK_100 n where n 1 to 16 MOUTACLK_160 MOUTACLK_133 n where 1 to 8 MOUTONENAND n where n 1 to 8 where n 1 to 8 freq MOUTASS n where n 1 to 16 freq MOUTRP n where 1 to 16 NOTE Figure 5 3 of Chapter 39 Audio Subsystem illustrates the clock names including iROM IRAM and clock tree diagram Caution Ensure that the
19. SAMSUNG ELECTRONICS 16 50 4412 UM 16 Display Controller W2KEYALPHA 0x0164 0x0000 0000 WIN3MAP 0x018C 0x0000 0000 I80IFCONA1 0x01B4 Specifies i80 interface control 0 for sub LDI 0x0000 0000 HUECOEF 2 0x01F0 Specifies hue coefficient control register 0x0000 0000 HUECOEF 3 0x0204 Specifies hue coefficient control register 0x0000 0000 SAMSUNG ELECTRONICS 16 51 4412 UM 16 Display Controller SAMSUNG ELECTRONICS 16 52 4412 UM 16 Display Controller Gamma LUT Data for 16 Step Mode SAMSUNG ELECTRONICS 16 53 4412 UM 16 Display Controller 2 0 0390 Specifies gamma RED data of the index 10 11 0X00BO 00A0 0 0394 Specifies gamma RED data of the index 12 13 0 0000 00CO 0 0398 Specifies gamma RED data of the index 14 15 0 00 0 00 0 i 0X03B4 Specifies gamma GREEN data of the index 10 11 0X01D0_01C0 GAMMAL UT 0X03B8 Specifies gamma GREEN data of the index 12 13 0 01 0 01 0 _R 13 12 AMMALUT 15 14 0 Specifies gamma GREEN data of the index 14 15 0X0210_0200 2 0X03D8 Specifies gamma BLUE data of the index 10 11 0 02 0 02 0 0X03DC Specifies gamma BLUE data the index 12 13 0X0310_0300 Specifies gamma BLUE data of the index 14 15 0 0330 0320 Pod Specifies gamma BLUE data of the index 16 0X0350 0340 SAM
20. EXT 29 3 Sn EXT 29 MASK 2 2 e Med did 0 0 Enables Interrupt EXT INT29 MASK 1 1 0 1 Masked 0 0 Enables Interrupt EXT INT29 MASK 0 Rw 0 1 Masked SAMSUNG ELECTRONICS 4 233 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 162 EXT_INT8_MASK e Base Address 0x1100 0000 e Address Base Address 0x0924 Reset Value 0x0000_00FF EXT INT8 MASK 7 o idad Interrupt 0 0 Enables Interrupt 0x1 Masked pa mme ms m mw 007 Erbe mem EXT INT8 MASK 4 4 ska m nw 90 Eee merum EXT_INT8_MASK 6 0 0 Enables Interrupt EXT INT8 MASK 2 2 0x1 Masked 0 0 Enables Interrupt EXT INT8 MASK 1 0 1 Masked 0 0 Enables Interrupt EXT INT8 MASK 0 0 1 Masked SAMSUNG ELECTRONICS 4 234 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 163 EXT_INT9_MASK e Base Address 0x1100 0000 e Address Base Address 0x0928 Reset Value 0x0000_007F EXT INT9 MASK 6 o enel Interrupt Sa msa s aw nocte eun EXT 9 MASK 4 4 gt 2 EXT INT9 MASK 3 3 mr m nw 90 ee 0 0 Enables Interrupt EXT 9 MASK 1 1 0x1 Masked 0 0 Enables Interrupt EXT 9 MASK 0 0 1 Masked 4 3 3 164 EXT_INT10_MASK e Base Address 0x1100 0000 e Address Base Address 0x092C
21. SAMSUNG ELECTRONICS 0 0 Input 0 1 Output 0 2 125 1 SDO 0 3 PCM 1 SOUT 0 4 AC97SDO 0 5 to Reserved OxF EXT_INT4 4 0 0 Input 0 1 Output 0 2 12S 1 SDI 0x3 PCM_1_SIN 0 4 AC97SDI 0 5 to OxE Reserved OxF EXT INT4 3 0 0 Input 0 1 Output 0 2 125 1 LRCK 0x3 1 FSYNC 0 4 AC97SYNC 0 5 to Reserved OxF EXT_INT4 2 0 0 Input 0 1 Output 0 2 125 1 CDCLK 0 3 1 0 4 AC97RESETn 0 5 to Reserved OxF EXT_INT4 1 0 0 Input 0 1 Output 0 2 2128 1 SCLK 0 3 PCM 1 SCLK 0 4 AC97BITCLK 0 5 to Reserved OxF EXT INT4 0 4 General Purpose Input Output GPIO Control 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 20 GPCODAT e Base Address 0x1140_0000 e Address Base Address 0x0064 Reset Value 0x00 RWX When you configure as input port then corresponding bit is pin state When configuring as output port the GPCODAT 4 0 4 0 pin state should be same as the corresponding bit 0 00 When the port is configured as functional pin the undefined value will be read 4 3 2 21 GPCOPUD Base Address 0x1140_0000 e Address Base Address 0x0068 Reset Value 0x0155 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down GPCOPUD n 0104 RW 0x2 Reserved 0x0155 0x3 Enables Pull up 4 3 2 22 GPCODRV
22. 4412 UM 5 Clock Management Unit 5 10 1 7 CLKOUT CMU LEFTBUS e Base Address 0x1003 0000 e Address Base Address 0x4A00 Reset Value 0x0001 0000 RSVD Enable CLKOUT ENB_CLKOUT 16 0 Disables 1 Enables 85 0 1534 85 0 75 MUX selection 00000 SCLK MPLL 2 MUX SEL 4 0 00001 SCLK APLL 2 00010 ACLK GDL 00011 ACLK GPL 5 10 1 8 CLKOUT CMU LEFTBUS DIV STAT er e Base Address 0x1003 0000 e Address Base Address 0x4A04 Reset Value 0x0000 0000 RSV ar MEN DIVCLKOUT Status DIV_STAT 0 Stable 0 0 1 Status that the divider is changing SAMSUNG ELECTRONICS 5 39 ex 4412 UM 5 Clock Management Unit 5 10 1 9 CLK SRC RIGHTBUS e Base Address 0 1003 0000 e Address Base Address 08200 Reset Value 0x0000 0000 RSV aus 09 Controls MUXMPLL MPLL USER SEL 4 RW 0 FINPLL 1 FOUTMPLL RSVD Reseved Controls MUXGDR MUX_GDR_SEL RW 0 SCLKMPLL 1 SCLKAPLL 5 10 1 10 CLK MUK STAT RIGHTBUS Base Address 0x1003 0000 e Address Base Address 0x8400 Reset Value 0x0000 0011 RSV au Selection Signal Status of MUXMPLL MPLL_USER_SEL_R 6 4 oe A El 1xx Status that the mux is changing Selection Signal Status of MUXGDR 001 SCLKMPLL BOR SEL 2 0 010 SCLKAPLL 1 Status that the mux is changing SAMSUNG ELECTRONICS 5 40 ex 4412 UM 5 Clock
23. EXT_INT32 4 0 0 Input 0 1 Output GPV2CON 3 15 12 0 2 C2C_TXDI 3 0 00 0x3 to Reserved OxF EXT_INT32 3 0 0 Input 0 1 Output GPV2CON 2 11 8 0 2 2 TXD 2 0 00 0x3 to Reserved OxF EXT_INT32 2 0 0 Input 0 1 Output GPV2CON 1 7 4 0 2 2 TXD 1 0 00 0x3 to Reserved OxF EXT_INT32 1 0 0 Input 0 1 Output GPV2CON 0 3 0 0 2 2 TXD 0 0x3 to Reserved OxF EXT INT32 0 SAMSUNG ELECTRONICS 4 305 x 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 16 GPV2DAT Base Address Ox106E 0000 e Address Base Address 0x0064 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPV2DAT 7 0 7 0 output port then pin state should be same as 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 5 17 GPV2PUD Base Address Ox106E 0000 e Address Base Address 0x0068 Reset Value 0x5555 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down GPV2PUDIn n201o7 RW 0x2 Reserved 0x5555 0x3 Enables Pull up 4 3 5 18 GPV2DRV e Base Address 0x106E_ 0000 e Address Base Address 0x006C Reset Value 0 00 0000 23 16 Reserved Should be zero W GPV2DRVin Inj 2n 1 2 0x0000 0107 SAMSUNG ELECTRONICS 4 306 ex
24. at 4 5 4 31 Registers Summary en KAKAA a de ida 4 5 4 3 2 O AA AUNA 4 20 433 ria 4 124 4 3 4 Parts waned kl 4 289 4 3 5 4 298 5 CLOCK MANAGEMENT UNIT 5 1 MES ou 5 1 5 1 5 3 Clock Declaration A 5 3 5 38 1 Clocks from Clock Pads 5 3 5 3 2 Clocks Tom OG OE rie aa 5 4 muelle dis ros 5 5 5 4 1 Recommended PLL PMS Value for and 5 7 5 4 2 Recommended PLL PMS Value for 5 8 5 4 3 Recommended PLL PMS Value for 5 9 5 5 Clock Generation ias 5 10 5 6 Clock Configuration Procedure 5 15 SAMSUNG ELECTRONICS ex 5 61 Clock Gating E 5 16 5 6 2 Clock DIVING 5 16 5 7 Special Clock eaaa siada diaas 5 17 5 7 1 Special Glock Table a 5 17 5 8 CLKOUT 5 20 VO Description EE 5 23 5 10 Register Description y Ad ada 5
25. e Integral Nonlinearity Error 4 0 LSB Max Offset Error 0 to 55 LSB e Bottom Offset Error O to 55 LSB e Maximum Conversion Rate 1 MSPS e Low Power Consumption e Power Supply Voltage 1 8 V Typ 1 0 Typ Digital I O Interface e Analog Input Range 0 to 1 8 Result 4 8 Top Offset gt Bottom Offset AIN V Figure 18 1 ADC Top Bottom Offset Error Diagram SAMSUNG ELECTRONICS 18 1 18 ADC 4412 UM 18 ADC 18 3 Functional Description 18 3 1 Block Diagram Figure 18 2 is the functional block diagram of general A D converter AVDD10 5510 AVDD18A1 AVSS18A1 AVDD18A2 AVSS18A2 gt Level Shifte gt DO 11 0 gt EOC Figure 18 2 ADC Functional Block Diagram SAMSUNG ELECTRONICS 18 1 en 4412 UM 18 ADC 18 3 2 ADC Selection Exynos 4412 has two ADC blocks General ADC and MTCADC_ISP User can select one of ADC blocks by setting ADC_CFG 16 bit in System Register SFR ADC_CFG 16 in System Register Base address 0x1001_0118 0 General ADC 1 MTCADC ISP General ADC 0x126C 0000 ISP 0x1215 0000 Figure 18 3 ADC Selection 18 3 3 A D Conversion Time When the bus clock PCLK frequency is 66 2 and the prescaler value is 65 total 12 bit conversion time is as follows e A D converter freq 66 MHz 65 1 1 MHz e Conversion time 1 1 MHz 5 cycles 1 200 kHz
26. 16 4 16 31 Brief Description 16 4 SAMSUNG ELECTRONICS ex 16 32 FOM si 16 5 16 3 3 Overview of the Color Data L 16 8 16 3 4 Palette Usage AA aaa 16 23 16 3 5 Window 16 26 16 3 6 VTIME Controller Operation 16 35 16 3 7 Virtual DIS Yi acti dannii 16 39 16 3 8 RGB Interface Specification 16 40 16 3 9 LCD Indirect i80 System 16 43 16 4 DOSCHIPTON 16 47 16 5 Register D scriptiOh maven ees da Bea 16 48 16 5 1 Register Map crac 16 49 16 5 2 Palette uro wa 16 56 16 5 3 Control Register vga 16 57 16 5 4 Gamma Lookup a nnns intres 16 131 16 5 5 Shadow Windows Control 16 134 16 5 6 Falete RaM erno sss 16 136 17 KEYPAD INTERFACE d sas acu 17 1 AKSE EE EE 17 1 17 2
27. fo Sets signaling method of EXT INT33 4 0 0 Low level 0 1 High level EXT INT33 CON 4 18 16 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved 85 9 E mw Sets signaling method of EXT_INT33 3 0 0 Low level 0x1 High level EXT INT33 CON S 14 12 RW 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0x5 to 0 7 Reserved mw fm Jan SAMSUNG ELECTRONICS 4 320 ex 4412 UM 4 General Purpose Input Output GPIO Control Sets signaling method of EXT_INT33 2 0 0 Low level 0x1 High level EXT_INT33_CON 2 10 8 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT33 1 0 0 Low level 0x1 High level EXT_INT33_CON 1 6 4 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT33 0 0x0 Low level 0x1 High level EXT INT33 CON 0 2 0 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0 7 Reserved SAMSUNG ELECTRONICS 4 321 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 39 EXT_INT34CON Base Address Ox106E 0000 e Address Base Address 0x0710 Reset Value 0x0000 0000 signaling method of EXT INT34 1 0 0 Low level
28. 11 6 Figure 11 4 Example of Double Buffering 11 8 Figure 11 5 Example of a Timer 11 9 Figure 11 6 Example ot PWM 2266 aD awaanika awa 11 10 Figure 11 7 Inverter uu ka ee a ee eel dee 11 11 Figure 11 8 Waveform when a Dead Zone Feature is 11 12 Figure 12 1 Watchdog Timer Block Diagram 12 2 Figure 13 1 Block Diagram of ka ida cine 13 1 Figure 13 2 UART AFG Interface eec A OA 13 3 Figure 13 8 UART Receives the Five Characters Including Two Errors 2 13 7 Figure 13 4 IrDA Function Block 13 8 Figure 13 5 Serial Frame Timing Diagram Normal 13 8 Figure 13 6 Infra Red Transmit Mode Frame Timing 4 13 9 Figure 13 7 Infra Red Receive Mode Frame Timing 13 9 Figure 13 8 Input Clock Diagram for UART 13 10 Figure 13 9 nCTS and Delta CTS Timing Diagram eene nennen nns nennen 13 25 Figure 13 10 Block Diagram of UINTSP UINTP and 13 30 SAMSUNG ELECTRONICS II Figure 14 1 Figure 14 2 Figure 14 3 Figure 14 4 Figure 14 5 Figure 14 6 Figure 14 7 Figure 14 8 Figure 14 9 Figure 15 1
29. 4412 UM 10 NAND Flash Controller 10 7 3 6 NFECCERLn 0 to 7 e Base Address OXOCE2 0000 e Address Base Address 0 00 0 Reset Value 0x0000 0000 NFECCERLO e Address Base Address 0x00C4 Reset Value 0x0000 0000 NFECCERL1 e Address Base Address 0x00C8 Reset Value 0x0000 0000 NFECCERL2 e Address Base Address Reset Value 0x0000 0000 NFECCERL3 e Address Base Address 0 0000 Reset Value 0 0000 0000 NFECCERL4 e Address Base Address 0x00D4 Reset Value 0x0000 0000 NFECCERL5 e Address Base Address 0x00D8 Reset Value 0x0000 0000 NFECCERL6 e Address Base Address 0x00DC Reset Value 0x0000 0000 NFECCERL7 Bit Type Description Reset Value 926 Reseved R Efrorbytelocation of 2 biterror_ 000 Reserved ___ _ R Efrorbytelocation of 1 biterror_ 0000 Red ___ __ Efrorbytelocation of 4 bit error 0000 Reseved R Efrorbytelocation of 3 bit error 0000 Reseved Efrorbytelocation of 6 bit error 0000 RSVD sto Reserved 00 EmByteLoc5 9 0 EmorbytelocationofS bitemor 0000 RSVD 3126 Reseved E NX ME NN ENS CU EE O R RSVD ErrByteLoc2 RSVD ErrByteLoc1 RSVD ErrByteLoc4 RSVD ErrByteLoc3 RSVD 31 26 ErrByteLoc6 25 16 Error byte location of 14 bit error 0x000 ErrByteLoc10 RSVD Er
30. EXT_INT25 2 0 0 Input 0 1 Output GPK2CON 1 7 4 0 2 SD 2 CMD 0 00 0x3 to Reserved EXT INT25 1 0 0 Input 0 1 Output GPK2CON 0 3 0 0 2 SD 2 CLK 0 00 0x3 to Reserved OxF EXT_INT25 0 SAMSUNG ELECTRONICS 4 132 x 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 14 GPK2DAT Base Address 0x1100 0000 e Address Base Address 0x0084 Reset Value 0x00 When you configure port as input port then corresponding bit is pin state When configuring as GPK2DAT 6 0 RWX output port the pin state should be same as the 0x00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 3 15 GPK2PUD Base Address 0x1100 0000 e Address Base Address 0x0088 Reset Value 0x1555 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down GPK2PUDIn n 0to6 RW 0x2 Reserved 0x1555 0x3 Enables Pull up 4 3 3 16 GPK2DRV e Base Address 0x1100_0000 e Address Base Address 0x008C Reset Value 0x00_ 0000 23 16 Reserved Should be zero W GPK2DRVin n 2n 1 2n R 0x0000 0106 SAMSUNG ELECTRONICS 4 133 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 17 GPK2CONPDN e Base Address 0x1100 0000 e Address Base Address 0x0090 Reset Value 0x0000 0 0 Outputs 0 2n 1 21 0 1 Outputs 1 n 0t06 F
31. eati ER etna 17 3 173 Filter GIOCK 17 3 17 4 Wakeup SOURCE Micra ia 17 3 17 5 Keypad Scanning Procedure for Software 17 4 17 6 Keypad Scanning Procedure for Hardware 17 9 epe aaia 17 10 17 8 Register IA 17 12 17 8 1 Register Map Summary escindida e DEL Gate ore area t tn aia 17 12 p 10 o 18 1 AAPP n 18 1 18 2 ina 18 1 18 3 Functional Description Aa 18 1 18 3 1 Block atra 18 1 18 3 2 ADC Selec aida 18 2 18 3 3 A D Conversi n T ie het ie 18 2 18 3 4 Conversion uuu uu 18 2 18 3 5 Standby iii a tata 18 3 18 4 Input Glock ote ence utr Fea aee vec buen d xata c o neve exa 18 4 18 DESCIIPLIONS u uu Y 18 5 18 6 Register DescriptiOD u roce aa 18 6 18 6 1 Register Map 18 6 SAMSUNG ELECTRONICS ex List of Figures Figure Title Page Number Number Figure 4 1 GPIO Block 4 4 Figure 5 1 Exynos4412 Clock Generation Circuit
32. 2 10 VSYNG 11 FRONT Porch Specifies Video Frame Interrupt Enable Control Bit 0 Disables Video Frame Interrupt 1 Enables Video Frame Interrupt NOTE This bit is valid when INTEN 1 high Specifies FIFO Interrupt control bit Each bit has a special significance 11 Window 4 control 0 Disables 1 Enables 10 Window 3 control 0 Disables 1 Enables 9 Window 2 control 0 Disables FRAMESEL1 14 13 INTFRMEN 12 SAMSUNG ELECTRONICS 16 95 2 4412 UM 16 Display Controller 1 Enables 8 Reserved 7 Reserved 6 Window 1 control 0 Disables 1 Enables 5 Window 0 control 0 Disables 1 Enables NOTE This bit is valid if both INTEN and INTFIFOEN are high Specifies Video FIFO Interrupt Enable Control Bit 0 Disables video FIFO level interrupt DHEIEGEN 1 BW 1 Enables video FIFO level interrupt NOTE This bit is valid if INTEN is high Specifies Video Interrupt Enable Control Bit INTEN RW 0 Disables video interrupt 1 Enables video interrupt NOTE 1 If video frame interrupt occurs then you can select maximum two points by setting FRAMESELO FRAMESEL1 For example in case FRAMESELO 00 FRAMESEL1 11 it triggers video frame interrupt both at the start of back porch and front porch Selects Video FIFO Interrupt Level 000 0 25 96 001 0 50 96 FIFOLEVEL 4 2 RW 010 0 75 011 2 0 96 empty 100 1
33. 4412 UM 4 3 2 49 GPF1CON Base Address 0x1140_0000 e Address Base Address 0x01A0 Reset Value 0x0000 0000 GPF1CON 7 GPF1CON 6 GPF1CON 5 GPF1CON 4 31 28 SAMSUNG ELECTRONICS 0 0 Input 0 1 Output 0 2 LCD VD 11 0x3 to Reserved OxF EXT_INT14 7 0 0 Input 0 1 Output 0 2 LCD VD 10 0x3 to Reserved EXT_INT14 6 0 0 Input 0 1 Output 0 2 LCD VD 9 0x3 to Reserved EXT_INT14 5 0 0 Input 0 1 Output 0 2 LCD VD 8 0x3 to Reserved OxF EXT_INT14 4 0 0 Input 0 1 Output 0 2 LCD 0x3 to Reserved OxF EXT_INT14 3 0 0 Input 0 1 Output 0 2 LCD VD 6 0x3 to Reserved OxF EXT_INT14 2 0 0 Input 0 1 Output 0 2 LCD VD 5 0x3 to Reserved OxF EXT_INT14 1 0 0 Input 0 1 Output 0 2 LCD VD 4 0x3 to Reserved EXT INT14 0 4 46 4 General Purpose Input Output GPIO Control 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 50 GPF1DAT e Base Address 0x1140_0000 e Address Base Address 0x01A4 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPF1DAT 7 0 7 0 output port the pin state should be same as the 0 00 corresponding bit When the port is configured as functional pin the un
34. 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 19 GPV2CONPDN Base Address Ox106E 0000 e Address Base Address 0x0070 Reset Value 0x0000 0x0 Outputs 0 2n 1 2n 0 1 Outputs 1 0107 RW 0 2 Input 999 0 3 Previous state 4 3 5 20 GPV2PUDPDN Base Address 0x106E_0000 e Address Base Address 0x0074 Reset Value 0x0000 0 0 Disables Pull up Pull down 2n 1 20 0 1 Enables Pull down 0107 RW 0x2 Reserved Oxu 0x3 Enables Pull up SAMSUNG ELECTRONICS 4 307 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 21 GPV3CON Base Address Ox106E 0000 e Address Base Address 0x0080 Reset Value 0x0000 0000 0 0 Input 0 1 Output GPV3CON 7 31 28 RW 0 2 C2C_TXD 15 0 00 0x3 to Reserved EXT INT33 7 0 0 Input 0 1 Output GPV3CON 6 27 24 RW 0 2 C2C TXD 14 0 00 0x3 to Reserved OxF EXT INT33 6 0 0 Input 0 1 Output GPV3CON 5 23 20 0 2 C2C_TXD 13 0 00 0x3 to Reserved OxF EXT INT33 5 0 0 Input 0 1 Output GPV3CON 4 19 16 0 2 C2C_TXD 12 0 00 0x3 to Reserved EXT_INT33 4 0 0 Input 0 1 Output GPV3CON 3 15 12 0 2 C2C_TXD 11 0 00 0x3 to Reserved OxF EXT INT33 3 0 0 Input 0 1 Output GPV3CON 2 11 8 0 2 2 TXD 10 0 00 0x3 to Reserved OxF EXT INT33 2 0 0 I
35. 4412 UM 5 Clock Management Unit Register CLK DIV ISP 0xC538 Sets clock divider ratio for ISP BLK 0x0000_0000 CLK_DIV_MAUDIO 0xC53C Sets clock divider ratio for AUDIO BLK 0x0000_0000 0xC56C to RSVD OxC57C Reserved Undefined Sets PCLK divider ratio in FSYS CAM CLKDIV2 RATIO 0xC580 LCD TV and GPS block 0 0111 1111 0xC584 to RSVD OxC60F Reserved Undefined CLK DIV STAT TOP OxC610 Clock divider status for CMU TOP 0x0000 0000 0xC614 to SAMSUNG ELECTRONICS 5 29 4412 UM 5 Clock Management Unit CLK DIV STAT PERIL4 0xC660 Clock divider status for PERIL_BLK 0x0000_0000 CLK_DIV_STAT_PERIL5 0xC664 Clock divider status for PERIL_BLK 0x0000_0000 CLK_DIV_STAT_CAM1 0xC668 Clock divider status for CAM_BLK 0 66 to CLKDIV2 STAT OxC680 PCLK divider status for FSYS CAM LCD and TV block 0xC684 to Control gating of AXI AHB APB clock for 0 0744 FSyS BLK 0xC748 to 0xC920 Controls IP clock gating for CAM_BLK 0xC924 Controls IP clock gating for TV_BLK 0xC928 Controls IP clock gating for MFC_BLK RSVD GATE BUS FSYS1 RSVD CLK GATE IP CAM CLK GATE IP TV CLK GATE IP CLK GATE IP G3D OxC92C Controls IP clock gating for G3D BLK OxC944 to CLK GATE IP GPS 0xC94C Controls IP clock gating for GPS BLK CLK GATE IP PERIL 0xC950 Controls IP clock gating for PERIL_BLK 0xC954 to CLK GATE BLOCK 0xC970 Clock gating control block 0xC974 to CLKOUT CMU TOP CLKOUT con
36. Power down mode pad state enable register 0 PADs Controlled by normal mode 1 PADs Controlled by Power Down mode control registers PDNEN R This bit is set to 1 automaticially when system 0 0 enters into Power down mode and can be cleared by writing O to this bit or cold reset After wake up from Power down mode this bit maintains value 1 until writing O SAMSUNG ELECTRONICS 4 123 II 4412 UM 4 General Purpose Input Output Control 4 3 3 Part 2 For the following SFRs Sets the value does not take effect immediately lt takes at least 800 APB clocks for the value to take effect after the SFR is actually changed The SFRs GPKOPUD GPKODRV GPK1PUD GPK1DRV GPK2PUD GPK2DRV GPK3PUD GPK3DRV GPLOPUD GPLODRV GPL1PUD GPL1DRV GPL2PUD GPL2DRV GPYOPUD GPYODRV GPY1PUD GPY1DRV GPY2PUD GPY2DRV GPY3PUD GPY3DRV GPY4PUD GPY4DRV GPY5PUD GPY5DRV GPY6PUD GPY6DRV GPMOPUD GPMODRV GPM1PUD GPM1DRV GPM2PUD GPM2DRV GPM3PUD GPM3DRV GPM4PUD GPM4DRV SAMSUNG ELECTRONICS 4 124 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 1 GPKOCON e Base Address 0x1100 0000 e Address Base Address 0x0040 Reset Value 0 0000 0000 0 0 Input 0 1 Output 0 2 SD 0 DATA 3 GPKOCON 6 27 24 0x3 SD 4 DAT 1s 0x00 0 4 to OxE Reserved OxF EXT INT23 6 0 0 Input 0 1 Output 0 2 SD 0 DATA 2 GPKOCON 5 23 20 Ne 0 00 0 4 to
37. SAMSUNG ELECTRONICS 5 66 4412 UM 5 Clock Management Unit 0011 SCLK USBPHYO 0101 SCLK_HDMIPHY 0110 SCLKMPLL USER 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved 1 is the source clock of MMC1 Controls MUXMMCO 0000 XXTI 0001 XusbXTI 0010 SCLK HDMI24M 0011 SCLK USBPHYO MMCO SEL 3 0 RW 0101 SCLK_HDMIPHY 0110 SCLKMPLL USER 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved MUXMMCO is the source clock of MMCO SAMSUNG ELECTRONICS 5 67 ex 4412 UM 5 Clock Management Unit 5 10 1 35 CLK SRC PERILO e Base Address 0 1003 0000 e Address Base Address 0xC250 Reset Value 0x0001_1111 Reserved RSVD lt should be 1 b1 Controls MUXUART4 0000 XXTI 0001 XusbXTI 0010 SCLK HDMI24M 0011 SCLK_USBPHYO UART4 SEL 19 16 0101 SCLK_HDMIPHY 0110 SCLKMPLL USER 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved is the source clock of UART4 Controls MUXUART3 0000 0001 XusbXTI 0010 SCLK HDMI24M 0011 SCLK USBPHYO UART3_SEL 15 12 0101 SCLK_HDMIPHY 0110 SCLKMPLL_USER_T 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved MUXUARTS is the source clock of UART3 Controls MUXUART2 0000 0001 XusbXTI 0010 SCLK_HDMI24M 0011 SCLK USBPHYO UART2 SEL 11 8 0101 SCLK_HDMIPHY 0110 SCLKMPLL_USER_T 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved MUXUA
38. 0x1386 0000 0x1387 0000 0x1388 0000 0x1389 0000 0x138A 0000 0x138B 0000 0x138C 0000 0x138D 0000 0x138E 0000 14 Inter Integrated Circuit register onsa Description Peset Vale I2CDSn I2CLCn SAMSUNG ELECTRONICS 14 13 0x000C Specifies the I2C bus interfaceO transmit receive data shift register 0 0010 Specifies the I2C bus interfaceO multi master line 0 00 control register 4412 UM 14 6 1 1 2 n 0 to 7 Base Address Base Address Base Address Base Address Base Address Base Address Base Address Base Address Base Address 0 1386 0000 0x1387 0000 0x1388 0000 0x1389 0000 0x138A 0000 0x138B 0000 0x138C 0000 0x138D 0000 0x138E 0000 14 Inter Integrated Circuit Address Base Address 0x0000 Reset Value OxOX Acknowledge generation 1 Tx clock source selection Tx Rx Interrupt 5 Interrupt pending flag 2 8 Transmit clock value 4 NOTE While interfacing with EEPROM the ACK generation is disabled before Reading the last data to generate the STOP condition in Rx mode 1 SAMSUNG ELECTRONICS Reserved 12C bus acknowledge enable bit 0 Disables 1 Enables In Tx mode the I2CSDA is idle in the time In mode the I2CSDA is low in the time Source clock of I2C bus transmit clock prescaler selection bit 0 I2CCLK fPCLK 16 1 I2CCLK fPCLK 512 12C bus Tx Rx interrupt enable di
39. 22 16 Filtering width of EXT INT22 2 Filter Enable for EXT INT22 1 FLTEN18 1 15 RW 0x0 Disables filter 0 1 Enables filter FLTWIDTH18 1 14 8 Filtering width of EXT INT22 1 Filter Enable for EXT INT22 0 FLTEN18 0 7 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH18 0 6 0 RW Filtering width of EXT_INT22 0 4 3 2 119 EXT_INT22_FLTCON1 Base Address 0x1140_0000 e Address Base Address 0x088C Reset Value 0x0000_0000 Filter Enable for EXT_INT22 4 FLTEN18 4 7 RW Disables filter 0 1 Enables filter FLTWIDTH18 4 6 0 RW Filtering width of EXT_INT22 4 SAMSUNG ELECTRONICS 4 100 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 120 EXT_INT1_MASK e Base Address 0x1140_0000 e Address Base Address 0x0900 Reset Value 0x0000_00FF 0 0 Enables interrupt EXT MASK 7 7 0x1 Masked 0x0 Enables interrupt EXT INT1 MASK 6 KUET 0 1 Masked 0x0 Enables interrupt EXT_INT1_MASKT 5 5 0 1 Masked eq rasqa m nocere Soma 90 tetes ern m po negre 4 3 2 121 INT2 MASK Base Address 0x1140_0000 e Address Base Address 0x0904 Reset Value 0x0000_003F EXT INT2 MASK 5 i EXT INT2 MASK 4 d 4 STUE T eines 0 0 Enables interrupt EXT 2 MASK 0 EB RW oxi Masked SAM
40. Re gt es Rem gt s m eme gt 4 m Re gt Reserved dP Reserves 1 pe Reserved SAMSUNG ELECTRONICS 6 12 en 4412 UM 6 Interrupt Controller 6 4 Functional Overview Please refer to the GIC PL390 technical reference manual SAMSUNG ELECTRONICS 6 13 ex 4412 UM 6 Interrupt Controller 6 5 Register Description 6 5 1 Register Map Summary Base Address 0x1048 0000 ICCICR_CPUO 0x0000 0 0000 0000 INTERRUPT OUT_CPUO 0x0044 Interrupt output register 0x0000_0000 ICCIIDR OxOOFC CPU interface identification register 0x3901_043B ICCIAR_CPU1 0 400 Interrupt acknowledge register 0x0000_03FF CPU1 0x4010 End of interrupt register Undefined CPU1 0x4000 CPU interface control register 0x0000 0000 ICCRPR CPU1 0x4014 Running priority register 0x0000_00FF ICCPMR CPU1 0x4004 Interrupt priority mask register 0x0000 0000 CPU1 0x4008 Binary point register 0x0000 0000 CPU1 0x4018 Highest pending interrupt register 0x0000_03FF ICCABPR_CPU1 0 401 Aliased binary point register 0x0000_0000 INTEG EN CPU1 04040 Integration test enable register 0x0000_0000 INTERRUPT_ OUT CPU1 0x4044 Interrupt output register 0x0000 0000 INTERRUPT _ OUT CPU2 0x8044 Interrupt output register 0x0000 0000 SAMSUNG ELECTRONICS 6 14 4412 UM 6 Interru
41. Reserved OxF EXT_INT23 5 0 0 Input 0 1 Output 0 2 SD 0 DATA 1 GPKOCON 4 19 16 0x3 Sr 0 00 0 4 to Reserved OxF EXT_INT23 4 0 0 Input 0 1 Output 0 2 SD 0 DATA 0 GPKOCON S 15 12 0x3 BADAT 0x00 0x4 to Reserved OxF EXT_INT23 3 0 0 Input 0 1 Output 0 2 SD 0 CDn GPKOCON 2 11 8 0 3 SD 4 CDn 0 00 0 4 GNSS_GPIO 8 0 5 to Reserved OxF EXT_INT23 2 0 0 Input 0 1 Output 7 4 NA 0x00 0 4 to Reserved OxF EXT_INT23 1 0 0 Input 0 1 Output 0 2 SD 0 CLK GPKOCON O 3 0 0x3 SD 4 CLK 0 4 to OxE Reserved OxF EXT INT23 0 SAMSUNG ELECTRONICS 4 125 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 2 GPKODAT e Base Address 0x1100 0000 e Address Base Address 0x0044 Reset Value 0x00 When you configure port as input port then corresponding bit is pin state When configuring as GPKODAT 6 0 RWX output port the pin state should be same as the 0x00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 3 3 GPKOPUD Base Address 0x1100 0000 e Address Base Address 0x0048 Reset Value 0x1555 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down GPKOPUDIn n 0to6 RW 0x2 Reserved 0x1555 0x3 Enables Pull up 4 3 3 4 GPK0DRV e Base Address 0x1100_0000 e Addres
42. Set TCNTBn 3 and TCMPBn 1 Set auto reload 1 and manual update 1 If manual update bit is 1 then it loads TCNTBn and TCMPBn values to TCNTn and TCMPn Set TCNTBn 2 and 0 for the next operation Set auto reload 1 and manual update 0 If you set manual update 1 at this time it changes TCNTn to 2 and it changes TCMP to 0 Therefore it generates interrupt at interval two cycle instead of three cycle You should set auto reload 1 automatically for the next operation Set start 1 for starting the operation Then is down counting If TCNTn is 0 it generates interrupt and if auto reload is enable it loads 2 value and it loads 0 value is down counting before stops SAMSUNG ELECTRONICS 11 7 ex 4412 UM 11 Pulse Width Modulation Timer 11 3 3 Auto Reload and Double Buffering PWM Timers includes a double buffering feature which changes the reload value for the next timer operation without stopping the current timer operation The timer value is written into Timer Count Buffer register and the current counter value of the timer is read from TCNTOn Timer Count Observation register If is read the read value does not reflect the current state of the counter but the reload value for the next timer duration Auto reload is copy function that a value of the TCNTBn is copied to the TCNT
43. nD ne S Gating all clocks for CLK_SMMU_ISPCX CLK_SMMU_ISPCX 4 RW 0 Mask 1 Pass av fo Gating all clocks for CLK_ASYNCAXIM CLK_ASYNCAXIM RW 0 Mask 1 Pass 5 10 1 156 CLKOUT_CMU_ISP Base Address 0x1004 0000 e Address Base Address 8 00 Reset Value 0x0001 0000 RSVD 31 17 MN Reserved Enable CLKOUT ENB_CLKOUT 16 RW 0 Disables 1 Enables RSVD 15 14 DIV RATIO 13 8 Divide Ratio Divide ratio DIV RATIO 1 KN SVD MUX Selection 00000 ACLK MCUISP 00001 PCLKDBG_MCUISP 4 0 id 00010 ACLK DIVO 00011 ACLK DIV1 00100 2 SCLK MPWM ISP SAMSUNG ELECTRONICS 5 161 27 0 0 0 1 0 0 0 0 0 0 t 4412 UM 5 Clock Management Unit 5 10 1 157 CLKOUT CMU ISP DIV STAT e Base Address 0x1004 0000 e Address Base Address 0x8A04 Reset Value 0x0000 0000 DIVCLKOUT Status 0 Stable 1 Status that the divider is changing Base Address 0x1004 0000 Address Base Address 0x8B00 Reset Value 0 0000 0000 SPARE 31 0 CMU_ISP Spare Register 0 0 5 10 1 159 CMU ISP SPARE1 Base Address 0x1004 0000 Address Base Address 0x8B04 Reset Value 0x0000 0000 SPARE 31 0 ISP Spare Register 0 0 5 10 1 160 CMU_ISP_SPARE2 Base Address 0x1004 0000 Address Base Address 0x8B08 Reset Value 0x0000 0000 SPARE 31 0 CMU_ISP Spare Register 0 0 5
44. non palletized A 4 R 4 G 4 B 4 for per pixel blending 16 level blending SAMSUNG ELECTRONICS 16 76 4412 UM 16 Display Controller Selects Alpha value When Per plane blending case BLD_PIX 0 0 Uses ALPHAO R G B values 1 Uses ALPHA1_R G B values ALPHA_SEL_F 1 RW When Per pixel blending BLD_PIX 1 0 Selected by AEN A value 1 Uses DATA 31 24 data in word boundary only when BPPMODE_F 4 b1101 DATA 31 28 15 12 data in word boundary only when BPPMODE_F 4 b1110 Enables disables video output and logic immediately ENWIN_F RW 0 Disables the video output and video control signal 1 Enables the video output and video control signal SAMSUNG ELECTRONICS 16 77 IT 4412 UM 16 Display Controller 16 5 3 13 WINCON4 e Base Address 0x11C0_0000 e Address Base Address 0x0030 Reset Value 0x0000_0000 Specifies Buffer Status read only 00 Buffer is set to 0 BUFSTATUS_H 31 RW 01 Buffer is set to 1 10 Buffer is set to 2 NOTE BUFSTATUS BUFSTATUS_H BUFSTATUS 1 Selects Buffer set 00 Buffer is set to 0 01 Buffer is set to 1 BUPSEL H 80 10 Buffer is set to 2 only available where BUF MODE 1 61 NOTE BUFSEL BUFSEL_H BUFSEL_L Reserved 29 26 NOTE This bit should 0 Specifies Trigger Status read only TRIGSTATUS 25 RW 0 Does not issue trigger 1 Issues trigger Reserved Rev 24 20 NOTE This bit s
45. 13 0 EM This register values from input ports are not filtered data ports 17 8 1 5 KEYIFFC Base Address 0 100 _0000 e Address Base Address 0x0010 Reset Value 0 0000 0000 mw ema wee A KEYPAD interface debouncing filter clock division register You can set compare value for 10 bit up counter This register value means when FC EN bit is HIGH FOLK FLT_CLK KEYIFFC 9 0 1 FLT CLK 15 from OSC 17 8 1 6 KEYIFSCAN1 Base Address 0x100A 0000 e Address Base Address 0x0014 Reset Value 0x0000_0000 KEYPAD interface scan result of row only pressed row has 1 Clears value when first key is released KEYPAD interface scan result of column only pressed column has 1 Clears value when first key is released SAMSUNG ELECTRONICS 17 15 II 4412 UM 17 8 1 7 KEYIFSCAN2 e Base Address 0x100A_0000 e Address Base Address 00018 Reset Value 0x0000 0000 RSVD 31 22 17 8 1 8 Base Address 0 100 _0000 17 Keypad Interface KEYPAD interface scan result of row only pressed row has 1 Clears value when first key is released KEYPAD interface scan result of column only pressed column has 1 Clears value when first key is released e Address Base Address 0x001C Reset Value 0x0000 0000 SAMSUNG ELECTRONICS Reserved KEYPAD input release interrupt rising edge status read
46. 4 External interrupt EXT INT12 pending register 0 EM ANE x0B08 Current service register 0x0000 0000 EXT INT SERVICE _ _ OxOBOC Current service pending register 0x0000_0000 gt gt EXT_INT23_FIXPRI External interrupt 23 fixed priority control register 0x0000_0000 0x0000_0000 0 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 INT29 FIXPRI External interrupt 29 fixed priority control register 0x0000 0000 EXT INT8 FIXPRI 0x0B38 External interrupt 8 fixed priority control register 0x0000_0000 EXT_INT25_FIXPRI External interrupt 25 fixed priority control register EXT_INT26_FIXPRI External interrupt 26 fixed priority control register EXT_INT27_FIXPRI External interrupt 27 fixed priority control register EXT_INT28_FIXPRI External interrupt 28 fixed priority control register 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 EXT_INT9_FIXPRI External interrupt 9 fixed priority control register EXT_INT10_FIXPRI External interrupt 10 fixed priority control register EXT_INT11_FIXPRI External interrupt 11 fixed priority control register EXT_INT12_FIXPRI External interrupt 12 fixed priority control register GPXOCON Port group GPXO configuration register GPXODAT Port group GPXO data register 0 00 GPKOPUD Port group GPKO pull up pull down register 0 5555 GPX2DAT 0x0C44 Port group GPX2 data register 0 00 EXT_INT24_FIXPRI 0x0B20 External interrupt 24 fixed priority control regis
47. 4 3 2 153 5 Base Address 0x1140 0000 Address Base Address 0x0B24 Reset Value 0 0000 0000 Interrupt number the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group 4 EXT INT5 when fixed priority 0 0 mode 0 to 7 4 3 2 154 6 FIKPRI e Base Address 0x1140 0000 e Address Base Address 0x0B28 Reset Value 0x0000 0000 Interrupt number of the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group 5 EXT INT6 when fixed priority 0 0 mode 0 to 7 4 3 2 155 EXT_INT7_FIXPRI e Base Address 0x1140_0000 e Address Base Address 0x0B2C Reset Value 0 0000 0000 Reserved 0 00000000 Interrupt number of the highest priority in External Interrupt Group 6 EXT_INT7 when fixed priority 0 0 mode 0 to 7 SAMSUNG ELECTRONICS 4 120 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 156 EXT_INT13_FIXPRI e Base Address 0x1140_0000 e Address Base Address 0x0B44 Reset Value 0x0000 0000 Reserved 0x00000000 Interrupt number of the highest priority in External Interrupt Group 7 EXT_INT13 when fixed priority 0 0 mode 0 to 7 4 3 2 157 EKT INT14 FIKPRI Base Address 0x1140 0000 Address Base Address 0x0B48 Reset Value 0 0000 0000 Interrupt number the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group 8 EXT INT14 when fixed priority 0 0 mode 0
48. 4 3 2 6 GPAOPUDPDN Base Address 0x1140 0000 e Address Base Address 0x0014 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down 0107 RW 0x2 Reserved DE 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 23 II 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 7 GPA1CON e Base Address 0x1140_0000 e Address Base Address 0x0020 Reset Value 0 0000 0000 0 0 Input 0 1 Output 0 2 UART 3 TKD GPA1CON 5 23 20 0x3 Reserved 0 00 0 4 UART AUDIO TKD 0 5 to Reserved OxF EXT_INT2 5 0 0 Input 0 1 Output 0 2 UART_3_RXD GPA1CON 4 19 16 RW 0x3 Reserved 0 00 0 4 UART AUDIO RKD 0 5 to Reserved OxF EXT INT2 4 0 0 Input 0 1 Output 0 2 UART 2 RTSn GPA1CON 3 15 12 RW 0x3 120 3 SCL 0 00 0 4 to Reserved OxF EXT INT2 3 0 0 Input 0 1 Output q 0 2 UART 2 CTSn GPA1CON 2 11 8 RW 0x3 I2C 3 SDA 0 00 0 4 to Reserved OxF EXT_INT2 2 0 0 Input 0 1 Output 0 2 UART 2 TKD GPA1CON 1 7 4 RW 0x3 Reserved 0 00 0 4 UART AUDIO TKD 0 5 to Reserved OxF EXT_INT2 1 0 0 Input 0 1 Output 0 2 UART 2 RXD GPA1CON 0 3 0 RW 0x3 Reserved 0x4 UART_AUDIO_RXD 0 5 to Reserved OxF EXT_INT2 0 SAMSUNG ELECTRONICS 4 24 en 4412 UM 4 General Purpose Input Output GPIO Contr
49. 4 3 3 43 GPYOCON e Base Address 0x1100 0000 4 General Purpose Input Output GPIO Control e Address Base Address 0x0120 Reset Value 0x0000_0000 GPYOCON 5 23 20 RW SAMSUNG ELECTRONICS 0 0 Input 0 1 Output 0x2 WEn 0 4 to Reserved 0 0 Input 0 1 Output 0 2 OEn 0 4 to Reserved 0 0 Input 0 1 Output 0 2 SROM_CSn 3 0x3 NF_CSn 1 0x4 Reserved 0x5 OND_CSn 1 0 4 to Reserved 0 0 Input 0 1 Output 0 2 SROM CSn 2 0x3 NF_CSn 0 0x4 Reserved 0x5 OND_CSn 0 0 4 to Reserved 0 0 Input 0 1 Output 0 2 SROM CSn 1 0x3 CSn 3 0 4 to Reserved 0 0 Input 0 1 Output 0 2 SROM_CSn 0 0x3 NF CSn 2 0 4 to Reserved 4 147 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 44 GPYODAT Base Address 0x1100 0000 e Address Base Address 0x0124 Reset Value 0x00 RWX When you configure port as input port the corresponding bit is the pin state When configuring GPYODATI 5 0 5 0 as output port the pin state should be same as the 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 3 45 GPYOPUD Base Address 0x1100 0000 e Address Base Address 0x0128 Reset Value OxOFFF 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pul
50. 4412 UM 4 3 3 169 EKT INT25 PEND e Base Address 0x1100 0000 e Address Base Address 0x0A10 Reset Value 0x0000 0000 RSVD EXT INT25 PEND 6 EXT INT25 PEND 5 EXT INT25 PEND 4 EXT INT25 PEND 3 EXT INT25 PEND 2 EXT INT25 PEND 1 EXT INT25 PEND 0 e Base Address 0x1100 0000 6 5 4 3 2 1 RWX RWX RWX RWX 4 3 3 170 EXT_INT26_PEND 4 General Purpose Input Output GPIO Control 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs e Address Base Address 0x0A14 Reset Value 0x0000 0000 RSVD EXT 26 PEND 6 EXT INT26 PEND 5 EXT INT26 PEND 4 EXT INT26 PEND 3 EXT INT26 PEND 2 EXT INT26 PEND 1 EXT 26 PEND 0 6 5 4 S 2 1 RWX RWX RWX RWX SAMSUNG ELECTRONICS Reserved 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 4 239 0x0000000 7 4412 UM 4 General Purpose Inp
51. 4412 UM 13 Universal Asynchronous Receiver and Transmitter If AFC bit is enabled this value will be ignored In this case the Exynos 4412 controls nRTS signals automatically Request to RW If AFC bit is disabled the software must control nRTS Send signal 0 level inactivate nRTS 1 L level activate nRTS NOTE 1 UART 3 does not support AFC function because the Exynos 4412 has no nRTS3 and nCTS3 2 In AFC mode set the trigger level of Rx FIFO lower than the trigger level of RTS because transmitter stops data transfer when it deactivates the nRST signal SAMSUNG ELECTRONICS 13 20 ex 4412 UM 13 Universal Asynchronous Receiver and Transmitter 13 6 1 5 UTRSTATn 0 to 4 e Base Address 0x1380 0000 Base Address 0x1381_0000 Base Address 0x1382 0000 e Base Address 0x1383 0000 Base Address 0x1384 0000 Address Base Address 0x0010 Reset Value 0x0000_0000 mw noen _ 9 1 RA 23 16 Capture value of FIFO counter when Rx time out occurs 0 00 status Current State of Tx DMA FSM 0 0 IDLE 0 1 Burst Reguest 0 2 Burst Acknowledgement 0x3 Burst Next intermediate state for next request TX DMA 15 12 0x4 Single Request FSM State 0 5 Single Acknowledgement 0x6 Single Next intermediate state for next request 0x7 Last Burst Request 0x8 Last Burst Acknowledgement 0x9 Last Single Request 0 10 Last Single Acknow
52. 4412 UM 5 Clock Management Unit MUXFIMCO_LCLK is the source clock of FIMCO local MEN clock SAMSUNG ELECTRONICS 5 58 ex 4412 UM 5 Clock Management Unit 5 10 1 28 CLK SRC TV e Base Address 0 1003 0000 e Address Base Address 0xC224 Reset Value 0 0000 0000 RSV er Controls MUXHDMI 0 SCLK_PIXEL ADMI SEL RW 4 SCLK HDMIPHY 0x0 MUXHDMI is the source clock of HDMI link 5 10 1 29 CLK_SRC_MFC Base Address 0x1003_0000 e Address Base Address 0xC228 Reset Value 0x0000_0000 ASV oo Controls MUXMFC 0 MOUTMFC 0 SEL FW MOUTMFC 1 is the source clock of core SE FS AAN Controls MUXMFC 1 0 SCLKEPLL 1 SEL 4 RW 1 SCLKVPLL 1 is the source clock of MFC core SE Controls MUXMFC 0 0 SCLKMPLL D SEL RW 4 SCLKAPLL 0 15 the source clock of core SAMSUNG ELECTRONICS 5 59 ex 4412 UM 5 Clock Management Unit 5 10 1 30 CLK SRC G3D e Base Address 0x1003 0000 e Address Base Address 0xC22C Reset Value 0x0000 0000 RSV Controls MUXG3D 0 MOUTG3D_0 RW 1 MOUTG3D_1 MUXG3D is the source clock of G3D core SE A Controls MUXG3D 1 0 SCLKEPLL G3D 1 SEL 4 RW 1 SCLKVPLL MUXG3D_1 is the source clock G3D core 85 0 ey AAN C
53. 9 gt 0 Ree 10 19 16 Specifies Red Alpha lower value case AEN 0 amp Reewd 11 8 Specifies Green Alpha lower value case AEN 0 sv reserves fo gt ALPHAD B L F 13 01 RW Species Blue lower value case AEN 220 0 NOTE R 7 4 ALPHAO B _H 3 0 at VIDOSD1C ALPHAO R 3 0 3 0 ALPHAO_R B L 3 0 at VIDW1ALPHAO SAMSUNG ELECTRONICS 16 120 27 4412 UM 16 Display Controller 16 5 3 73 VIDW1ALPHA1 e Base Address 0x11C0_0000 e Address Base Address 0x0228 Reset Value 0x0000_0000 C neme AC Description Reset Value CC 19 16 RW Spocties Red ower vale case AEN o mevo ALPHA GLF 14 6 RW Species Green Aipha tower value case AEN 1 0 ra Reens AAPHALB LF 16 01 RW Species Blue Aipha lower vale case AEN 0 NOTE ALPHA1_R 7 4 ALPHA1_R 6 B _H 3 0 at VIDOSD1C ALPHA1_R 3 0 ALPHA1_R G L 3 0 at VIDW1ALPHA1 16 5 3 74 VIDW2ALPHAO e Base Address 0x11C0_0000 e Address Base Address 0x022C Reset Value 0x0000_0000 C neme rape Reset Value mv mene fo PD gs po R LF 1946 BW Species Red ower vao ase AEN cO o mv mesen 0
54. DIVCORE2_ DOWN_ENB 2 DIVCORE_DOWN _ENB USE_STANDBYWFE _ARM_CORE3 USE_STANDBYWFE _ARM_CORE2 2 USE STANDBYWFE _ARM_COREO USE STANDBYWFI ARM CORE3 USE STANDBYWFI ARM CORE2 USE STANDBYWFI R 7 USE_STANDBYWFE 5 ARM CORE1 4 3 2 R R R R R R W W W W W W W Ox1 Ox1 Ox1 Ox1 Ox1 Ox1 Ox1 1 SAMSUNG ELECTRONICS 5 152 4412 UM 5 Clock Management Unit ARM CORE1 frequency in ARM IDLE state USE STANDBYWFI RW Use ARM COREO STANDBYWFI to change 0 1 _ARM_COREO ARMCLK frequency in ARM IDLE state SAMSUNG ELECTRONICS 5 153 IT 4412 UM 5 Clock Management Unit 5 10 1 146 PWR_CTRL2 e Base Address 0x1004 0000 e Address Base Address 0x5024 Reset Value 0x0000_0000 RSVD 31 26 Reserved Enable ARMCLK Up feature when both ARM cores exit from IDLE mode for DIVCORE2 0 Disables 1 Enables Enable ARMCLK Up feature when both ARM it f IDLE mode for DIVCORE UP ne 0 Disables 1 Enables Sets duration to change to the normal divider value from the middle divider value 23 1 RW 23 16 This bit should be left shifted by 4 bit before comparing it to the counter value Sets duration to change to the middle divider value from the divider value in ARM idle state BY1 15 RW OUP STANG 15 8 This bit should be left shifted 4 bit before comparing it to
55. FTC3 0 004 Specifies the fault type for DMA channel 3 FTC4 0x0050 Specifies the fault type for DMA channel 4 m FS FS M C M FTC5 00054 Specifies the fault type for DMA channel 5 FTC6 00058 Specifies the fault type for DMA channel 6 FTC7 0 005 Specifies the fault type for DMA channel 7 0x0060 to 50 0 0100 Specifies the channel status for channel 0 S yA 52 ss 54 CS5 00128 Specifies the channel status for DMA channel 5 56 0 0130 Specifies the channel status for channel 6 CS7 00138 Specifies the channel status for DMA channel 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KO KO KO KO KO KO KO KO 0 0 0 0 0 0 0 0 SAMSUNG ELECTRONICS 8 9 4412 UM 8 Direct Memory Access Controller DMAC CPC6 00134 Specifies the channel PC for DMA channel 6 CPC7 0 013 Specifies the channel for DMA channel 7 0x0140 to i 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 KO KO KO KO KO KO KO KO KO KO KO KO KO KO KO KO KO KO KO KO KO KO KO KO KO KO KO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i SAMSUNG ELECTRONICS 8 10 4412 UM 8 Direct Memory Access Controller DMAC DBGSTATUS 0 0000 Specifies the debug status register 3 37 of 0 0 Specifies the debug command register Refer to 3 37 PREGE 00004 of
56. Gating all clocks for PPMUTV CLK_PPMUTV 5 0 Mask 1 Pass Gating all clocks for SMMUTV CLK SMMUTV 4 0 Mask 1 Pass vo ne Gating all clocks for MIXER CLK MIXER 1 RW 0 Mask 1 Pass Gating all clocks for CLK_VP RW 0 Mask 1 Pass Gating all clocks for HDMI link CLK HDMI 3 0 Mask 0 1 1 Pass SAMSUNG ELECTRONICS 5 110 IT 4412 UM 5 Clock Management Unit 5 10 1 94 CLK GATE e Base Address 0x1003 0000 e Address Base Address 0xC928 Reset Value OxFFFF_FFFF Gating all clocks for PPMUMFC R CLK_PPMUMFC_R 0 Mask 1 Pass Gating all clocks for L CLK_PPMUMFC_L 3 0 Mask 1 Pass Gating all clocks for SMMUMFC_L CLK_SMMUMFC_L 1 0 Mask 1 Pass Gating all clocks for RW Mask 1 Pass Gating all clocks for SMMUMFC_R CLK_SMMUMFC_R 2 0 Mask 0 1 1 Pass SAMSUNG ELECTRONICS 5 111 IT 4412 UM 5 Clock Management Unit 5 10 1 95 CLK GATE IP G3D e Base Address 0x1003 0000 e Address Base Address 0xC92C Reset Value OxFFFF_FFFF 1 Gating all clocks for PPMUG3D CLK PPMUG3D RW 0 Mask 0 1 1 Pass Gating all clocks for G3D CLK G3D RW 0 Mask 0 1 1 Pass 5 10 1 96 CLK GATE IP LCD e Base Address 0x1003 0000 e Address Base Address 0xC934 Reset Value OxFFFF_FFFF Gating all clocks for PPMULCDO CLK PPMULCDO 0 Mask 1 Pass Ga
57. RSV Sets signaling method of EXT_INT21 7 0 0 Low level 0x1 High level EXT_INT21_CON 7 30 28 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0x7 Reserved 85 2 mesen mo Sets signaling method of EXT_INT21 6 0 0 Low level 0x1 High level EXT INT21 CON 6 26 24 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved SVO ea Jo Sets signaling method of EXT_INT21 5 0 0 Low level 0x1 High level EXT_INT21_CON 5 22 20 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0x5 to 0x7 Reserved SVO nome Jo Sets signaling method of EXT INT21 4 0 0 Low level 0 1 High level EXT INT21 CON 4 18 16 RW 0 2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved 85 9 mp mw Sets signaling method of EXT_INT21 3 0 0 Low level 0x1 High level EXT INT21 CON 3 14 12 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved mw on SAMSUNG ELECTRONICS 4 79 ex 4412 UM 4 General Purpose Input Output GPIO Control Sets signaling method of EXT_INT21 2 0 0 Low level 0x1 High level EXT_INT21_CON 2 10 8 RW 0x2 Triggers falling edge 0x3 Triggers rising ed
58. S woot ne mo Controls MUXACLK 200 SUB MUX ACLK 2 gt Ec 200 20 RWX 0 FINPLL 1 DIVOUT ACLK 200 S sem neon mo ACLK 266 Controls MUXACLK 266 GPS SUB GPS SUB SEL RWX 0 FINPLL 1 DIVOUT ACLK 266 GPS S fm Controls MUXMPLL MUX MPLL USER SED 1 USER 12 RW 0 FINPLL 1 SCLKMPLLL S ma fm Controls MUXACLK 400 MCUISP MUX ACLK 400 _400 MCUISP SEL RW 0 SCLKMPLL_USER_T 1 SCLKAPLL 85 9 s fe Controls MUXACLK 266 GPS 2 dias 4 RW 0 SCLKMPLL_USER_T _ 1 SCLKAPLL SE Jf ov SAMSUNG ELECTRONICS 5 55 x 4412 UM 5 10 1 27 CLK SRC CAMO e Base Address 0x1003 0000 e Address Base Address 0xC220 Reset Value 1111 1111 CAM1_SEL 23 20 CAMO_SEL 19 16 SAMSUNG ELECTRONICS 5 Clock Management Unit Controls MUXCSIS1 0000 XXTI 0001 XusbXTI 0010 SCLK HDMI24M 0011 SCLK USBPHYO 0101 SCLK_HDMIPHY 0110 SCLKMPLL 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved MUXCSIS1 is the source clock of CSIS1 Controls MUXCSISO 0000 XXTI 0001 XusbXTI 0010 SCLK_HDMI24M 0011 SCLK_USBPHYO 0101 SCLK_HDMIPHY 0110 SCLKMPLL 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved MUXCSISO is the source clock of CSISO Controls MUXCAM1 0000 KITI 0001 XusbXTI 0010 SCLK HDMI24M 0011 SCLK USBPHYO 0101 SCLK_HDMIPHY 0110 SCL
59. SYSMMU FMC 21 combiner will mask the interrupt SYSMMU FIMC2 1 20 RW Write 0 Does not change the current setting __ SYSMMU_FIMC1 1 19 1 Clears the interrupt enable bit to Read The current interrupt enable bit 59000 SYSMMU_FIMCO 1 18 0 Masks SYSMMU 55501 17 1 Enables EE NE SYSMMU MOWAT 16 x o j RSV ml SYSMMU_MFC_M1 0 14 Clears the corresponding interrupt enable bit to 0 SYSMMU If you clear the interrupt enable bit interrupt 13 combiner will mask the interrupt SYSMMU TV 12 RW write 0 Does not change the current setting RSVD 11 MEN 1 Clears the interrupt enable bit to 0 Read The current interrupt enable bit 59000 SYSMMU LCDO MO 0 10 0 Masks SYSMMU GPSI0 09 RW 1 Enables EE SEMEN SYSMMU JPEG 0 Clears the corresponding interrupt enable bit to NN KENN If you clear the interrupt enable bit interrupt SYSMMU FIMC3 0 combiner will mask the interrupt SYSMMU FIMC2 0 RW Write 0 Does not change the current setting SYSMMU_FIMC1 0 1 Clears the interrupt enable bit to SYSMMU FIMCO 0 RW Read The current interrupt enable bit 0 Masks SYSMMU 55510 1 Enables SYSMMU NOMADI to Fe 227 SAMSUNG ELECTRONICS 7 15 4412 UM 7 6 2 7 ISTR1 e Base Address 0x1044 0000 e Address Base Address
60. 0 0 Input 0 1 Output 0 2 UART 0 TXD 0x3 to Reserved OxF EXT INT1 1 0 0 Input 0 1 Output 0 2 UART 0 0x3 to Reserved OxF EXT_INT1 0 4 General Purpose Input Output GPIO Control 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 2 GPAODAT Base Address 0x1140_0000 e Address Base Address 0 0004 Reset Value 0 00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPAODAT 7 0 7 0 output port the pin state should be same as the 0x00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 2 3 GPAOPUD Base Address 0x1140 0000 e Address Base Address 0x0008 Reset Value 0x5555 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down GPAOPUD n n 0io7 RW 0x2 Reserved 0x5555 0x3 Enables Pull up 4 3 2 4 GPA0DRV e Base Address 0x1140_0000 e Address Base Address 0x000C Reset Value 0 00 0000 23 16 Reserved Should be zero W GPA0DRV n n 2n 1 2n R 0x0000 0107 SAMSUNG ELECTRONICS 4 22 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 5 Base Address 0x1140_0000 e Address Base Address 0x0010 Reset Value 0x0000 0x0 Outputs O 2n 1 2n 0x1 Outputs 1 OPAO 0107 RW 0x2 Input n 0 3 Previous state
61. 0 1 Output 0 2 DATA 0 0x3 to Reserved OxF EXT INT21 3 0 0 Input 0 1 Output 0 2 CAM_A_HREF 0x3 to Reserved OxF EXT_INT21 2 0 0 Input 0 1 Output 0 2 VSYNC 0 3 to OxE Reserved OxF EXT INT21 1 0 0 Input 0 1 Output 0 2 PCLK 0x3 to Reserved OxF EXT_INT21 0 4 General Purpose Input Output GPIO Control 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 70 GPJODAT e Base Address 0x1140_0000 e Address Base Address 0x0244 Reset Value 0 00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPJODAT 7 0 7 0 output port the pin state should be same as the 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 2 71 GPJOPUD Base Address 0x1140_0000 e Address Base Address 0x0248 Reset Value 0x5555 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down GPJOPUD n n 0to 7 RW 0x2 Reserved 0x5555 0x3 Enables Pull up 4 3 2 72 GPJ0DRV e Base Address 0x1140_0000 e Address Base Address 0x024C Reset Value 0x00_ 0000 23 16 Reserved Should be zero W GPJODRV n n 2n 1 2n R 0x0000 n 0to7 SAMSUNG ELECTRONICS 4 56 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 73 GPJOCONPDN e Base
62. 00 Buffer is set to 0 BUFSTATUS_H 31 RW 01 Buffer is set to 1 10 Buffer is set to 2 NOTE BUFSTATUS BUFSTATUS_H BUFSTATUS 1 Selects Buffer set 00 Buffer is set to 0 01 Buffer is set to 1 PURSE 80 10 Buffer is set to 2 only available where BUF MODE 1 61 NOTE BUFSEL BUFSEL_H BUFSEL 1 Reserved PONE 129 281 NOTE This bit should be set to 0 Specifies Trigger Status read only TRIGSTATUS 25 RW 0 trigger is issued 1 Trigger is issued Reserved HSV EEE NOTE This bit should be set to 0 Specifies Buffer Status read only 21 NOTE BUFSTATUS BUFSTATUS H BUFSTATUS 1 Selects Buffer set sd sl 20 NOTE BUFSEL BUFSEL H BUFSEL L Specifies Double Buffer Auto control bit BUFAUTOEN 19 0 Fixed by BUFSEL 1 Auto changed by Trigger Input BITSWP F 18 BYTSWP F 17 HAWSWP F 16 0 Disables swap 1 Enables swap Specifies Word swap control bit WSWP 15 RW 0 Disables swap 1 Enables swap BUF MODE 14 RW Selects auto buffering mode 0 Double SAMSUNG ELECTRONICS 16 75 RW RW Specifies Bit swap control bit 0 Disables swap 1 Enables swap Specifies Byte swaps control bit 0 Disables swap 1 Enables swap Specifies Half Word swap control bit 4412 UM 16 Display Controller Name Bit Description Reset Value VEA Reserved RSVD 13 11 ES NOTE This bit should be set to 0 Selects DMA B
63. 0xC610 Reset Value 0x0000_0000 RSVD ere Ren DIVACLK 400 MCUISP Status DIV ACLK 400 MCUISP 24 0 Stable 1 Status that the divider is changing S om DIVACLK 266 GPS Status DIV ACLK 266 GPS 20 0 Stable 1 Status that the divider is changing SE 99 DIVONENAND Status DIV ONENAND 16 0 Stable 1 Status that the divider is changing Avo DIVACLK 133 Status DIV ACLK 133 12 0 Stable 1 Status that the divider is changing SE mal fremt om DIVACLK 160 Status DIV ACLK 160 0 Stable 1 Status that the divider is changing 85 9 eee fm DIVACLK 100 Status DIV ACLK 100 4 0 Stable 1 Status that the divider is changing 85 9 o 99 DIVACLK 200 Status DIV ACLK 200 0 0 Stable 1 Status that the divider is changing SAMSUNG ELECTRONICS 5 94 ex 4412 UM 5 Clock Management Unit 5 10 1 72 CLK DIV STAT CAMO e Base Address 0x1003 0000 e Address Base Address 0xC620 Reset Value 0 0000 0000 RSVD Gus DIVCSIS1 Status DIV_CSIS1 28 0 Stable 1 Status that the divider is changing SE gs 1 ov DIVCSISO Status DIV CSISO 24 0 Stable 1 Status that the divider is changing SE 1 ov DIVCAM1 Status DIV_CAM1 20 0 Stable 1 Status that the divider is changing SE vem __ ov
64. 1 Enables HUE_CSC _F Narrow HUE CSC FEQ709 1 HUE CSC Gamma mode selection 0 Applies 64 step identical value to all R G B data 1 Applies 16 step independent value to each B data Controls HUE CSC F Narrow Wide 0 Wide 1 Narrow Controls HUE_CSC_F parameter 0 Equation 601 1 Equation 709 Enables HUE CSC F 14 0 Disables 1 Enables when HUE ON 1 b1 Controls HUE CSC_B Narrow Wide 0 Wide 1 Narrow Controls HUE_CSC_B parameter 0 Equation 601 1 Equation 709 Enables HUE CSC 0 Disables 1 Enables when HUE ON 1 b1 Enables Control Hue 0 Disables bypass 1 Enables HUE_CSC _B Narrow HUE_CSC EQ709 HUE CSC BON SVD NOTE This bit should be set to 0 Ta SAMSUNG ELECTRONICS 16 62 ITT 10 Reserved w 4412 UM 16 Display Controller 0 0 5 positive 1 0 5 negative Enables Pixel Compensation 0 Disables _ 3 0 1 Enables 0x0 NOTE PC_ON 1 b1 compensates the TV output data SAMSUNG ELECTRONICS 16 63 ex 4412 UM 16 Display Controller 16 5 3 5 VIDTCONO e Base Address 0x11C0_0000 e Address Base Address 0x0010 Reset Value 0 0000 0000 Vertical back porch specifies the number of inactive lines at VBPDE 31 24 RW the start of a frame after vertical synchronization period only for even field of YVU interface VBPD 23 16 Vert
65. 1 Pass Gating all clocks for SYSREG 0 Mask 1 Pass Gating all clocks for CHIP ID 0 Mask 1 Pass 5 44 Reset Value x1 4412 UM 5 Clock Management Unit 5 10 1 15 CLKOUT CMU RIGHTBUS e Base Address 0x1003 0000 e Address Base Address 0x8A00 Reset Value 0x0001 0000 RSV Enable CLKOUT ENB_CLKOUT 16 0 Disables 1 Enables mw 184 ER RW RW 85 0 75 W MUX Selection 00000 SCLK MPLL 2 MUX SEL 4 0 R 00001 SCLK APLL 2 00010 ACLK GDR 00011 ACLK GPR 13 8 DIV RATIO 1 SAMSUNG ELECTRONICS 5 45 ex 4412 UM 5 Clock Management Unit 5 10 1 16 CLKOUT CMU RIGHTBUS DIV STAT e Base Address 0x1003 0000 e Address Base Address 0x8A04 Reset Value 0x0000 0000 RSVD 31 1 Reserved 1 __ DIVCLKOUT Status DIV STAT 0 0 Stable 0 0 1 Status that the divider is changing 5 10 1 17 EPLL_LOCK e Base Address 0x1003_0000 e Address Base Address 0xC010 Reset Value 0x0000 OFFF Required period to generate a stable clock output Set 3000 cycles x PDIV to PLL_LOCKTIME for the PLL maximum lock time PLL_LOCKTIME 15 0 1 cycle 1 FREF 1 FIN PDIV The maximum PLL lock time 1 250 usec where FIN is 24 MHz is 2 and PLL_LOCKTIME is 6000 The maximum lock time means the waiting time for locking in the worst case Therefore the user of this PLL must wait for more than the
66. 16 5 3 28 VIDOSD3B Base Address 0x11C0 0000 e Address Base Address 0x0074 Reset Value 0x0000 0000 OSD RightBotX F 21 11 Specifies Horizontal screen coordinate for right bottom pixel of OSD image 5 EN Specifies Vertical screen coordinate for right bottom pixel of OSD image OSD RightBotY F 10 0 RW For interlace TV output this value should be set to half of the original screen y coordinate The original screen y coordinate should be odd value NOTE Registers should have word boundary X position Therefore 24 BPP mode should have X position by 1 pixel For example X 0 1 2 3 16 BPP mode should have X position by 2 pixel For example X 0 2 4 6 8 BPP mode should have X position by 4 pixel For example X 0 4 8 12 SAMSUNG ELECTRONICS 16 89 ex 4412 UM 16 Display Controller 16 5 3 29 VIDOSD3C e Base Address 0x11C0_0000 e Address Base Address 0x0078 Reset Value 0x0000_0000 Name Rea O Specifies the Red Alpha upper value case 0 Specifies the Green Alpha upper value case AEN ALPHA RHF 11 8 Specifies the Red Alpha upper value case AEN 1 ALPHALG H F 74 Specifies the Green Alpha upper value case 1 ALPHA BH F 3 0 Specifies the Blue Alpha upper value case AEN 1 NOTE For more information Refer to 16 5 3 76 VIDWSALPHAO 16 5 3 77 VIDW3ALPHA1 register o
67. 4 3 5 63 EXT_INT30_FIXPRI Base Address Ox106E 0000 e Address Base Address 0x0B14 Reset Value 0x0000 0000 Interrupt number of the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group 0 EXT INT30 when fixed priority 0x0 mode 0 to 7 4 3 5 64 EXT INT31 FIXPRI Base Address Ox106E 0000 e Address Base Address 0x0B18 Reset Value 0x0000 0000 Interrupt number of the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group 1 EXT INT31 when fixed priority 0x0 mode 0 to 7 4 3 5 65 EXT INT32 FIXPRI Base Address Ox106E 0000 e Address Base Address 0x0B1C Reset Value 0x0000 0000 Interrupt number of the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group 2 EXT INT32 when fixed priority 0x0 mode 0 to 7 SAMSUNG ELECTRONICS 4 341 x 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 66 EXT_INT33_FIXPRI Base Address Ox106E 0000 e Address Base Address 0x0B20 Reset Value 0x0000 0000 Interrupt number of the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group EXT INT33 when fixed priority 0x0 mode 0 to 7 4 3 5 67 EXT INT34 FIXPR Base Address Ox106E 0000 e Address Base Address 0x0B24 Reset Value 0x0000 0000 Interrupt number of the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group 4 EXT INT34 when fixed priority 0x0 mode 0 to 7 SA
68. 440 MHz SCLKepi SCLKvpu SCLKapii SCLK_G2D G2D core operating clock 200 MHz 5 I SCL Kapu SCLK MFC core operating clock 200 MHz 8 Range varies in accordance to the All possible clock sources CAM specifications SCLK CSISO SCLK CSIS1 CSIS operating clock 160 MHz All possible clock sources SCLK FIMC LCLKO SCLK FIMC LCLK1 SCLK FIMC LCLK2 SCLK FIMC LCLK3 SCLK AUDIOO SCLK SPDIF SPDIF operating clock SCLK AUDIO1 SCLK AUDIO2 Reference clock for SEL AMD SO GANT external CAM device core operating clock 160 MHz All possible clock sources SCLK 0 5 SCLK MMC2 HSMMC operating clock All possible clock sources SCLK MMC3 SCLK MMC4 SAMSUNG ELECTRONICS IT 4412 UM 5 Clock Management Unit Wame 22772 mane Some SCLK AUDIOO SCLK_AUDIO1 SCLK_AUDIO2 AUDIO operating clock 100 MHz All possible clock sources 125 AUDIOCDCLKx SCLK_AUDIOO SCLK_PCMO AUDIO operating clock SCLK_AUDIO1 SCLK_PCM1 SCLK_PCM2 PCM SCLK AUDIO2 SCLK_PWI IEM APC operating clock 6 to 30 MHz All possible clock sources SCLK_KEY REY UF or TOADG XXTI XUSBXTI clock fixed clock SCLK SPIO SCLK SPI SCLK SPI2 operating clock 100 MHz All possible clock sources SCLK_UARTO SCLK UART1 SCLK UART2 UART operating clock 200 MHz All possible
69. 4412 UM 5 Clock Management Unit 5 5 Clock Generation Figure 5 1 and Figure 5 2 illustrates the block diagram of the clock generation logic The clock generator consists of an external crystal clock that is connected to the oscillation amplifier The PLL converts the incoming low frequency to a high frequency clock that is required by the Exynos 4412 The clock generator also includes a built in logic to stabilize the clock frequency for each system reset The clock requires a specified time for stabilization Figure 5 1 and Figure 5 2 illustrates the two types of clock Clock in grey color represents glitch free clock MUX that is free of glitches while changing the clock selection Clock MUX in white color represents non glitch free clock MUX that can suffer from glitches while changing the clock sources You have to be careful while using each clock MUX For glitch free MUX you should ensure that all clock sources are running while changing the clock selection If not it implies that the clock selection process is not complete and it results in clock output having unknown states The clock status registers are identified with keyword that starts with STAT For non glitch free clock glitches may occur while changing the clock selection To prevent glitch signals we recommend disabling the output of non glitch free before any change of clock selection After completing the clock change yo
70. 6 4 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT29 0 0 0 Low level 0x1 High level EXT INT29 CON 0 2 0 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 204 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 126 EXT_INT8CON e Base Address 0x1100 0000 e Address Base Address 0x0724 Reset Value 0x0000_0000 RSV Sets signaling method of EXT INT8 7 0x0 Low level 0x1 High level EXT 8 CON 7 30 28 RW 0 2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved 85 2 Reeves fo Sets signaling method of EXT INT8 6 0 0 Low level 0 1 High level EXT INT8 CON 6 26 24 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved ASVO gy Rese wp 0 Sets signaling method of EXT_INT8 5 0 0 Low level 0x1 High level EXT INT8 CON 5 22 20 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0x7 Reserved 85 0 mp eee wp 0 Sets signaling method of EXT_INT8 4 0 0 Low level 0x1 High level EXT INT8 CON 4 18 16 RW 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both
71. 85 9 mw Sets signaling method of EXT_INT15 3 0 0 Low level 0x1 High level EXT INT15 CON 3 14 12 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved mw on SAMSUNG ELECTRONICS 4 75 ex 4412 UM 4 General Purpose Input Output GPIO Control Sets signaling method of EXT_INT15 2 0 0 Low level 0x1 High level EXT_INT15_CON 2 10 8 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0 7 Reserved Sets signaling method of EXT_INT15 1 0x0 Low level 0x1 High level EXT_INT15_CON 1 6 4 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0 7 Reserved Sets signaling method of EXT INT15 0 0 0 Low level 0x1 High level EXT INT15 CON 0 2 0 RW 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved SAMSUNG ELECTRONICS 4 76 II 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 91 16 Base Address 0x1140 0000 e Address Base Address 0x073C Reset Value 0 0000 0000 m eee RSV o Sets signaling method of EXT INT16 5 0 0 Low level 0 1 High level EXT INT16 5 22 20 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0
72. Base Address 14 6 1 2 I2CSTATn n 0 to 7 0x1386 0000 0x1387 0000 0x1388 0000 0x1389 0000 0x138A 0000 0x138B 0000 0x138C 0000 0x138D 0000 0x138E 0000 14 Inter Integrated Circuit e Address Base Address 0x0004 Reset Value 0x00 Reserved 12C bus Master Slave Tx Rx mode select bits 00 Slave receive mode 01 Slave transmit mode 10 Master receive mode 11 Master transmit mode Mode selection 12C bus busy signal status bit 0 Read Not busy If Read write STOP signal generation 1 Read Busy If Read write START signal generation Transfers the data 12205 automatically just after the start signal 12C bus data output enable disable bit 0 Disables Rx Tx 1 Enables Rx Tx 12C bus arbitration procedure status flag bit 0 Bus arbitration successful 1 Bus arbitration fails during serial 1 0 Busy signal status START STOP condition Serial output Arbitration status flag 12C bus address as slave status flag bit 0 Clears when it detects START STOP condition 1 Receives slave address that matches the address value in the I2CADD 12C bus address zero status flag bit 0 Clears when it detects START STOP condition 1 Received slave address is 000000006 12C bus last received bit status flag bit 0 Last received bit is set to 0 receives 1 Last received bit is set to 1 does not receive ACK Address as slave status flag Address zero status flag
73. Base Address 0x0810 Reset Value 0x0000 0000 Filter Enable for EXT INT23 3 FLTEN3 3 31 RW 0 0 Disables Filter 0x1 Enabled Filter FLTWIDTH3 3 30 24 Filtering width of EXT INT23 3 Filter Enable for EXT INT23 2 FLTEN3 2 23 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH3 2 22 16 Filtering width of EXT INT23 2 Filter Enable for EXT_INT23 1 FLTEN3 1 15 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH3 1 14 8 Filtering width of EXT INT23 1 Filter Enable for EXT INT23 0 FLTEN3 0 7 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH3 0 6 0 RW Filtering width of EXT INT23 0 4 3 3 132 EXT INT23 1 e Base Address 0x1100 0000 e Address Base Address 0x0814 Reset Value 0x0000 0000 RSV area Rewwd om Filter Enable for EXT INT23 6 FLTEN3 6 23 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH3 6 22 16 Filtering width of EXT INT23 6 Filter Enable for EXT INT23 5 FLTEN3 5 15 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH3 5 14 8 Filtering width of EXT_INT23 5 Filter Enable for EXT_INT23 4 FLTEN3 4 7 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH3 4 6 0 RW Filtering width of EXT INT23 4 SAMSUNG ELECTRONICS 4 214 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 133 EXT_INT24_FLTCONO e Base Address 0x1100 0000 e Address
74. EXT_INT9 6 0 0 Input 0 1 Output 0 2 CAM BAY RGB 12 GPM1CONIE 23 20 WA er 0x00 0 5 TraceData 1 1 0x6 to Reserved OxF EXT_INT9 5 0 0 Input 0 1 Output 0 2 CAM BAY RGB 11 0x3 Reserved GPM1CON 4 19 16 0x4 XhsiCAREADY 0 00 0 5 TraceData 10 0 6 to Reserved OxF EXT_INT9 4 0 0 Input 0 1 Output 0 2 CAM BAY RGB 10 GPM1CON 3 15 12 a 1 WA 0x00 0 5 TraceData 9 0x6 to OxE Reserved OxF EXT_INT9 3 0 0 Input 0 1 Output 0 2 CAM_BAY_RGBJ9 1 2 0x3 Reserved 0 00 0 4 XhsiACDATA 0 5 TraceData 8 0x6 to OxE Reserved OxF EXT_INT9 2 0 0 Input 0 1 Output 7 4 iii GPM1CON 1 7 4 0 2 BAY RGB 8 0x3 CAM B FIELD SAMSUNG ELECTRONICS 4 177 ex 4412 UM 4 General Purpose Input Output GPIO Control 0x4 XhsiACWAKE 0 5 TraceCtl 0 6 to Reserved OxF EXT_INT9 1 0 0 Input 0 1 Output 0x2 Reserved 0x3 CAM DATA 7 0 4 XhsiACREADY 0 5 TraceData 7 0x6 to OxE Reserved SAMSUNG ELECTRONICS OxF EXT_INT9 0 4 178 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 96 GPM1DAT e Base Address 0x1100 0000 e Address Base Address 0x0284 Reset Value 0x00 When you configure port as input port then corresponding bit is pin state When configuring as GPM1DAT 6 0 RWX output port then pin state shou
75. Enables Interrupt SAMSUNG ELECTRONICS 4 335 x 4412 UM 4 3 5 55 EKT INT30 PEND Base Address Ox106E 0000 e Address Base Address 0x0AO00 Reset Value 0x0000 0000 RSVD EXT INT30 PEND 7 EXT INT30 PEND 6 EXT INT30 PEND 5 EXT INT30 PEND 4 EXT INT30 PEND 3 EXT INT30 PEND 2 EXT INT30 PEND 1 EXT 30 5 4 8 RWX 2 RWX 1 SAMSUNG ELECTRONICS 4 General Purpose Input Output GPIO Control 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 4 336 4412 UM 4 3 5 56 EXT_INT31_PEND Base Address 0x106E_0000 e Address Base Address 0x0A04 Reset Value 0x0000 0000 RSVD EXT INT31 PEND 7 EXT INT31 PEND 6 EXT INT31 PEND 5 EXT INT31 PEND 4 EXT INT31 PEND 3 EXT INT31 PEND 2 EXT INT31 PEND 1 EXT INT31 PEND 0 5 4 3 RWX 2 RWX 1 SAMSUNG ELECTRONICS 4 General Purpose Input Output GPIO Control 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interr
76. Enables Pull down GEVILD 0107 RW 0x2 Reserved Oxu 0x3 Enables Pull up SAMSUNG ELECTRONICS 4 303 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 13 ETC7PUD Base Address Ox106E 0000 e Address Base Address 0x0048 Reset Value 0x0005 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down ETC7PUD n 0101 RW 0x2 Reserved 0x0005 0x3 Enables Pull up ETC7PUD 1 0 controls Xc2cRXCLK O ETC7PUD 3 2 controls XC2cRXCLK 1 4 3 5 14 ETC7DRV Base Address Ox106E 0000 e Address Base Address 0x004C Reset Value 0 00 0000 23 16 Reserved Should be zero W ETC7DRV n n 2n 1 2 0x0000 0101 ETC7DRV 1 0 controls Xc2cRXCLK O ETC7DRV 3 2 controls XC2cRXCLK 1 SAMSUNG ELECTRONICS 4 304 en 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 15 GPV2CON Base Address Ox106E 0000 e Address Base Address 0x0060 Reset Value 0x0000 0000 0 0 Input 0 1 Output GPV2CON 7 31 28 RW 0 2 C2C TXD 7 0 00 0x3 to Reserved EXT_INT32 7 0 0 Input 0 1 Output GPV2CON 6 27 24 RW 0 2 C2C_TXDI 6 0 00 0x3 to Reserved OxF EXT INT32 6 0 0 Input 0 1 Output GPV2CON 5 23 20 0 2 C2C_TXDI 5 0 00 0x3 to Reserved EXT INT32 5 0 0 Input 0 1 Output GPV2CON 4 19 16 0 2 C2C_TXDI 4 0 00 0x3 to Reserved
77. Enables Pull down GPY4PUD n n 0to7 RW 0x2 Reserved 0x5555 0x3 Enables Pull up 4 3 3 70 GPY4DRV e Base Address 0x1100_0000 e Address Base Address 0x01AC Reset Value 0x00_AAAA 23 16 Reserved Should be zero W GPY4DRVIn n 2n 1 2n R ERA 0107 SAMSUNG ELECTRONICS 4 162 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 71 GPY4CONPDN Base Address 0x1100 0000 e Address Base Address 0x01B0 Reset Value 0x0000 0 0 Outputs 0 2n 1 21 0 1 Outputs 1 Sram 0107 FUN 0x2 Input 999 0 3 Previous state 4 3 3 72 GPY4PUDPDN e Base Address 0x1100 0000 e Address Base Address 0x01B4 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down a yani n 0to7 i 0x2 Reserved 990 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 163 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 73 GPY5CON Base Address 0x1100 0000 e Address Base Address 0x01C0 Reset Value 0 0000 0000 0 0 Input 0 1 Output GPYSCON 7 31 28 0x2 EBI DATA 7 0 00 0x3 to Reserved 0 0 Input 0 1 Output GPY5CON 6 27 24 RW 0 2 DATA 6 0 00 0x3 to Reserved 0 0 Input 0 1 Output GPY5CON 5 23 20 0 2 EBI DATA 5 0 00 0x3 to OxE Reserved OxF 0 0 Input 0 1 Output GPY5CON 4 19 16 0 2 EBI DATA 4 0 00
78. Enables interrupt EXT INT14 MASK 6 6 0 1 Masked 0 1 0 0 Enables interrupt EXT 14 MASK 5 5 0 1 Masked 0 1 EXT_INT14_MASK 4 4 a EXT INT14 MASK 3 3 EXT INT14 MASK 2 2 21 EXT INT14 MASK 1 EXT 14 HESS m SAMSUNG ELECTRONICS 4 106 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 129 EXT_INT15_MASK Base Address 0x1140_0000 e Address Base Address 0x0938 Reset Value 0x0000_00FF 0 0 Enables interrupt EXT INT15 7 0 1 Masked 0 0 Enables interrupt EXT INT15 MASK 6 6 0 1 Masked 0 0 Enables interrupt EXT INT15 MASK 5 5 Oxi Masked 0 0 Enables interrupt EXT INT15 MASK 4 4 0 1 Masked 0x0 Enables interrupt EXT INT15 MASK 3 3 0 1 Masked 0 0 Enables interrupt EXT INT15 MASK 2 2 0x1 Masked 0x0 Enables interrupt 0x0 Enables interrupt 4 3 2 130 EXT_INT16_MASK e Base Address 0x1140_0000 e Address Base Address 0x093C Reset Value 0x0000_003F EXT INT16 MASK 5 EXT INT16 MASK 4 EXT INT16 MASK 3 EXT INT16 MASK 2 EXT INT16 MASK 1 EXT INT16 MASK 0 5 Hon interrupt 4 interrupt 3 z Fe interrupt o DIE SAMSUNG ELECTRONICS 4 107 7 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 131 EXT_INT21_MASK Base Address 0x1140_0000 e Address Base Address 0x0940 Reset Value 0x
79. Enables swap NOTE It should be set to 0 when ENLOCAL is 1 Selects auto buffering mode BUF_MODE 14 RW 0 Double 1 Specifies input color space of source image InRGB RW Only for enable Reserved RA Hata NOTE This bit should be set to 0 Selects DMA Burst Maximum Length 00 16 word burst BURSTLEN 10 9 RW 10 4 word burst 18 7 BH EW This bit should be set to 0 Selects blending category In case of windowo this is required only for deciding window 0 s blending factor 0 Per plane blending 1 Per pixel blending BLD_PIX_F Selects Bits Per Pixel BPP mode for Window image 0000 1 BPP 0001 2BPP 0010 4BPP 0011 8 BPP palletized BPPMODE F 5 2 RW 0100 8 palletized 1 R 2 G 3 B 2 0101 16 non palletized R 5 G 6 B 5 0110 16 non palletized A 1 R 5 G 5 B 5 0111 16 BPP non palletized 1 R 5 G 5 B 5 1000 Unpacked 18 BPP non palletized R 6 G 6 B 6 10015 Unpacked 18 non palletized A 1 R 6 G 6 SAMSUNG ELECTRONICS 16 67 ma 000000000 am 4412 UM 16 Display Controller o SAMSUNG ELECTRONICS Selects Alpha value When per plane blending case BLD_PIX 0 0 Uses ALPHAO R G B values 1 Uses ALPHA1_R G B values When per pixel blending BLD_PIX 1 0 Selected by AEN A value 1 Using DATA 31 24 data in word boundary only when BPPMODE_F 4 b11
80. External interrupt EXT_INT24 filter configuration register 1 0 0000_0000 Register EXT_INT25_FLTCONO 0x0820 External interrupt EXT_INT25 filter configuration register 0 0x0000 0000 EXT INT25 FLTCON1 x0824 External interrupt EXT INT25 filter configuration register 1 0x0000 0000 EXT 26 FLTCONO 0x0828 External interrupt EXT 26 filter configuration register 0 0x0000 0000 EXT_INT26_FLTCON1 0x082C 0x0000 0000 27 FLTCONO 0 0000 0000 EXT_INT27_FLTCON1 0 0000 0000 28 FLTCONO 0 0000 0000 EXT 29 0x0840 External interrupt EXT_INT29 filter configuration register O 0x0000 0000 EXT_INT29_FLTCON1 0x0844 External interrupt EXT_int29 filter configuration register 1 0x0000_0000 EXT_INT8_FLTCONO 0 0848 External interrupt EKT INT8 filter configuration register 0 0x0000_0000 0x0000_0000 EXT INT8 FLTCON1 0 084 External interrupt EXT INTS8 filter configuration register 1 0x0000 0000 EXT INT9 FLTCONO 0x0850 External interrupt EXT INTO filter configuration register 0 0 EXT INT28 FLTCON1 0x083C External interrupt EXT_INT28 filter configuration register 1 0x0000 0000 0 EXT 9 FLTCON1 x0854 External interrupt EXT INTO filter configuration register 1 0x0000 0000 EXT INT10 FLTCONO 0x0858 External interrupt EXT INT10 filter configuration register 0 0x0000 0000 EXT INT10 FLTCON1 0x085C External interrupt INT10 filter configuration
81. High level EXT INT22 CON 1 6 4 W 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0x7 Reserved Sets signaling method of EXT INT22 0 0 0 Low level 0 1 High level EXT INT22 CON 0 2 0 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 81 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 94 EXT_INT1_FLTCONO e Base Address 0x1140_0000 e Address Base Address 0x0800 Reset Value 0 0000 0000 Filter Enable for EXT INT1 3 FLTEN1 3 31 RW 0 0 Disables filter 0 1 Enables filter FLTWIDTH1 3 30 24 Filtering width of EXT INT1 3 Filter Enable for EXT INT1 2 FLTEN1 2 23 RW 0x0 Disables filter 0 1 Enables filter FLTWIDTH1 2 22 16 Filtering width of EXT INT1 2 Filter Enable for EXT INT1 1 FLTEN1 1 15 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH1 1 14 8 Filtering width of EXT INT1 1 Filter Enable for EXT INT1 0 1 0 7 0 0 Disables filter 0 1 Enables filter FLTWIDTH1 0 6 0 Filtering width of EXT_INT1 0 SAMSUNG ELECTRONICS 4 82 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 95 EXT_INT1_FLTCON1 e Base Address 0x1140_0000 e Address Base Address 0x0804 Reset Value 0 0000 0000 Filter Enable for EXT_INT1 7 FLTEN1 7 31 RW 0 0 D
82. MOUTACLK 160 ACLK 160 RATIO 1 DIVACLK 100 Clock Divider Ratio ACLK 100 RATIO 7 4 RW ACLK 100 IMOUTACLK 100 ACLK 100 RATIO 1 B DIVACLK 200 Clock Divider Ratio ACLK 200 RATIO 2 0 RW ACLK 200 MOUTACLK_200 ACLK_200_RATIO 1 SAMSUNG ELECTRONICS 5 84 ex 4412 UM 5 Clock Management Unit 5 10 1 52 CLK DIV CAMO e Base Address 0x1003 0000 e Address Base Address 0xC520 Reset Value 0 0000 0000 DIVCSIS1 Clock Divider Rati CSIS1 RATIO 31 28 RW SCLK_CSIS1 MOUTCSIS1 CSIS1_RATIO 1 CSIS0_RATIO RW DIVCSISO Clock Divider Ratio CAM1_RATIO 23 20 RW W SCLK_CSISO MOUTCSISO CSISO RATIO 1 CAMO RATIO 19 16 R DIVCAM1 Clock Divider Ratio SCLK MOUTCAM1 CAM1 RATIO 1 DIVCAMO Clock Divider Ratio FIMC3 RATIO FIMC2 RATIO FIMC1 RATIO SCLK CAMO MOUTCAMO CAMO RATIO 1 FIMCO LCLK RATIO 3 0 DIVFIMC3 LCLK Clock Divider Ratio SCLKFIMC3 MOUTFIMC3 0 0 FIMC3 RATIO 1 DIVFIMC2 LCLK Clock Divider Ratio SCLKFIMC2_LCLK MOUTFIMC2_LCLK FIMC2 LCLK RATIO 1 DIVFIMC1 LCLK Clock Divider Ratio SCLKFIMC1 LCLK MOUTFIMC1 LCLK FIMC1 RATIO 1 DIVFIMCO LCLK Clock Divider Ratio SCLKFIMCO MOUTFIMCO KFIMCO RATIO 1 2 2 5 10 1 53 CLK DIV TV e Base Address 0x1003 0000 e Address Base A
83. Not occur EXT INT33 PEND 2 2 RWX 0 1 Interrupt Occurs 0 0 Not occur 0 1 Interrupt Occurs 0 0 Not occur EN INGEN EB PIS 0 1 Interrupt Occurs 4 3 5 59 EXT INT34 EXT INT33 PEND 1 1 Base Address Ox106E 0000 e Address Base Address 0x0A10 Reset Value 0x0000 0000 0 0 Not occur IM 0 1 Interrupt Occurs 0 0 Not occur UMS m 0 1 Interrupt Occurs SAMSUNG ELECTRONICS 4 339 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 60 EXT_INT_SERVICE_XC Base Address Ox106E 0000 e Address Base Address 0x0B08 Reset Value 0x0000 0000 EXT INT Service group number 0 1 EXT 0 0 2 EXT INT31 7 ava raup kum 7 3 0 3 EXT INT32 0 4 EXT INT33 0 5 EXT INT34 SVC Num 2 0 Interrupt number to be serviced 4 3 5 61 EXT INT SERVICE PEND XC Base Address Ox106E 0000 e Address Base Address Reset Value 0x0000 0000 0 0 Not occur 22 7 0 0x1 Interrupt Occurs 4 3 5 62 EXT_INT_GRPFIXPRI_XC e Base Address 0x106E_0000 e Address Base Address 0x0B10 Reset Value 0 0000_0000 Group number of the highest priority when fixed group priority mode 0 to 4 0x0 EXT_INT30 Highest GRP NUM 3 0 RW 0 1 EXT INT31 0 2 INT32 0x3 EXT_INT33 0x4 EXT_INT34 SAMSUNG ELECTRONICS 4 340 II 4412 UM 4 General Purpose Input Output GPIO Control
84. Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 4 241 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 174 EXT_INT8_PEND e Base Address 0x1100 0000 e Address Base Address 0x0A24 Reset Value 0x0000 0000 0x0 Not occur EN NIE PENDIZ Ox1 Interrupt occurs 0 0 Not occur EN MIE PENDIS Ox1 Interrupt occurs 0 0 Not occur EN INE Ox1 interrupt occurs EXT INT8 PEND 4 m hei 0x0 Not occur EXT INT8 PEND 3 RWX 0 1 Interrupt occurs 0 0 Not occur EXT INT8 PEND 2 RWX 0 1 Interrupt occurs 0 0 Not occur EATEN PENGIM 0 1 Interrupt occurs 0 0 Not occur EN SMIE FENDI Ox1 Interrupt occurs SAMSUNG ELECTRONICS 4 242 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 175 EXT_INT9_PEND e Base Address 0x1100 0000 e Address Base Address 0x0A28 Reset Value 0x0000 0000 0 0 Not occur EAT NIS PENDIS 0 1 Interrupt occurs 0 0 Not occur EM NIS PENDISI Ox1 Interrupt occurs EXT 9 PEND 4 4 RWX 0 0 Not occur 0 1 Interrupt occurs mareo m me poten EXT INT9 PEND 2 pp 00 0x1 Interrupt occurs EXT 9 PEND 1 1 RWX 0 0 Not occur 0x1 Interrupt occurs EXT INT9 PENDJ 0 R
85. Re data of li is the data of li is the data of li is the data of li ine 1 of virtual screen ine 2 of virtual screen ine 3 of virtual screen ine 4 of virtual screen ine 5 of virtual screen ine 9 of virtual screen This ine 10 of virtual screen This ine 11 of virtual screen This is of is the data of is the data of is the data of is the data of is the data of is the data o is the data of is the data of is the data of is the data of is the data of 5 the data of the data of isXhe data of is the data of is the data of is the data of is the data of is the data of is the data of is the data of 16 39 line 1 of virtual screen line 2 of virtual screen line 3 of virtual screen line 4 of virtual screen LINEVAL 1 line 5 of virtual screen line 6 of virtual screen of virtual screen line 8 of virtual screen View Port line 9 of virtual screen The same size of LCD panel line 10 of virtual screen line 11 of virtual screen Before Scrolling line 1 of virtual screen line 2 of virtual screen line 3 of virtual screen line 4 of virfual screen line 5 of virfual screen line 6 of virfual screen line 7 of virfual screen line 8 of virfual screen line 9 of virtual screen line 10 of virtual screen line 11 of virtual screen After Scrolling Example of Scrolling in Virtual Display 4412 UM 16 Display Controller 16 3 8 RGB Inter
86. is controlled byA_FUNC 9 BLENDEQ register or 1 by B_FUNC BLENDEQ register alphaA by P_FUNC BLENDEQ register or 1 alphaA q by Q FUNC BLENDEQ register or alphaB or 1 alphaB or A or 1 A or B or or Figure 16 23 Blending Equation Example 16 4 Default Blending Equation lt Data blending gt 1 alphaA A x alphaA Alpha value blending gt alphaB 0 alphaB x 0 alphaA x 0 SAMSUNG ELECTRONICS 16 28 II 4412 UM 16 Display Controller 16 3 5 2 Blending Diagram The display controller can blend five layers for one pixel the same time ALPHAO R ALPHAO ALPHAO ALPHA1_R ALPHA1_G and ALPHA1_B registers control the alpha value blending factor which you can implement for each window layer and color R G B The example below shows the R Red output using ALPHA_R value of each window All windows have two kinds of alpha blending value Alpha value that enables transparency AEN value 1 Alpha value that disables transparency AEN value 0 If you enable WINEN_F and BLD_PIX and disable ALPHA_SEL then it selects the AR The equation to select the AR is e AR Pixel R s AEN value 1 b1 2 Reg ALPHA1_R ALPHAO Pixel G s value 1 b1 2 Reg ALPHA1_G Reg ALPHAO Pixel B s AEN value 1 b1 2 Reg ALPHA1_B Reg ALPHAO_B where BLD PIX 1 ALPHA SEL 0 If you enable WINEN
87. 0 0 Low level 0x1 High level EXT INT24 CON 1 6 4 RW 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved mw m mess mw Sets signaling method of EXT INT24 0 0 0 Low level 0 1 High level EXT INT24 CON 0 2 0 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 195 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 121 EXT_INT25CON e Base Address 0x1100 0000 e Address Base Address 0x0710 Reset Value 0x0000 0000 rea o f 9 ms mp nes fo Sets signaling method of EXT INT25 6 0 0 Low level 0 1 High level EXT INT25 CON 6 26 24 RW 0 2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved 85 9 gp eee wp 0 Sets signaling method of EXT_INT25 5 0x0 Low level 0x1 High level EXT INT25 CON 5 22 20 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved ASV mp fe Sets signaling method of EXT INT25 4 0 0 Low level 0 1 High level EXT INT25 CON 4 18 16 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved 85 9 fe Sets signaling method of EXT INT25 3 0 0 Low level 0 1 High level EXT INT25 CON
88. 0 1 High level EXT INT34 CON 1 6 4 RW 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0x5 to 0 7 Reserved mo B ov Sets signaling method of EXT_INT34 0 0 0 Low level 0 1 High level EXT INT34 CON 0 2 0 RW 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0 7 Reserved SAMSUNG ELECTRONICS 4 322 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 40 EXT_INT30_FLTCONO Base Address Ox106E 0000 e Address Base Address 0x0800 Reset Value 0x0000 0000 Filter Enable for EXT INT30 3 FLTEN1 3 31 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH1 3 80 24 Filtering width of EXT INT30 3 Filter Enable for EXT INT30 2 FLTEN1 2 23 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH1 2 22 16 Filtering width of EXT_INT30 2 Filter Enable for EXT_INT30 1 FLTEN1 1 15 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH1 1 14 8 Filtering width of Filter Enable for EXT_INT30 0 FLTEN 1 0 7 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTHi 6 0 RW Filtering width of EXT INT3O 0 SAMSUNG ELECTRONICS 4 323 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 41 EXT_INT30_FLTCON1 Base Address 0x106E_0000 e Address Base Address 0x0804 Reset Value 0x0000_0000
89. 0x0000 0000 EXT_INT14_PEND 7 7 RWX 0 0 Not occur 0 1 Interrupt occurs EXT INT14 PEND 6 6 RWX 0x0 Not occur 0 1 Interrupt occurs EXT_INT14_PEND 5 5 RWY 0 0 Not occur PP 0x1 Interrupt occurs EXT INT14 PEND 4 4 RWX 0 0 Not occur 0 1 Interrupt occurs EXT INT14 PEND 3 3 RWX 0 0 Not occur 0 1 Interrupt occurs EXT INT14 PEND 2 2 RWX 0 0 Not occur 25 0 1 Interrupt occurs EXT INT14 PEND 1 1 RWX 0 0 Not occur 0 1 Interrupt occurs EKT 14 PEND 0 RWX 0 0 Not occur 0 1 Interrupt occurs SAMSUNG ELECTRONICS 4 114 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 142 EXT_INT15_PEND Base Address 0x1140_0000 e Address Base Address 0x0A38 Reset Value 0x0000 0000 0x0 Not occur EXT INT15 PEND 7 7 RWX 0 1 Interrupt occurs 0 0 Not occur EXT INT15 PEND 6 6 RWX 0 1 Interrupt occurs 0 0 Not occur EXT INT15 PEND 5 5 RWX 0 1 Interrupt occurs 0 0 Not occur Ox1 Interrupt occurs 0 0 Not occur EXT INT15 PEND 4 4 RWX EXT INT15 PEND 3 3 RWX 0x1 Interrupt occurs EXT_INT15_PEND 2 2 RWX 0 0 Not occur 0 1 Interrupt occurs EXT INT15 PEND 1 1 Rw x 0X0 Not occur Ox1 Interrupt occurs EXT INT15 RWX 0 0 Not occur 0 1 Interrupt occurs 4 3 2 143 EXT INT16 e Base Address 0x1140 0000 e Address Base Addre
90. 0x106E_0000 e Address Base Address 0x00C4 Reset Value 0x00 When you configure port as input port then corresponding bit is pin state When configuring as GPVADATT 1 0 1 0 RWX output port then pin state should be same as 0x00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 5 31 GPV4PUD Base Address Ox106E 0000 e Address Base Address 0x00C8 Reset Value 0x0005 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down n 0101 0 2 0 3 Enables Pull up GPV4PUDIn 0x0005 SAMSUNG ELECTRONICS 4 312 x 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 32 GPV4DRV Base Address Ox106E 0000 e Address Base Address 0x00CG Reset Value 0x00 0000 23 16 Reserved Should be zero W GPV4DRVIn n 2n 1 2 0x0000 0101 4 3 5 33 4 Base Address 0x106E_0000 e Address Base Address 0 0000 Reset Value 0x0000 0 0 Outputs O 2 1 21 0 1 Outputs 1 GRAN n 0t01 PY ox2 Input oe 0 3 Previous state 4 3 5 34 GPV4PUDPDN Base Address Ox106E 0000 e Address Base Address 0x00D4 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down EP n 0to 1 0 2 oe 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 313 ex 4412 UM 4 General Purpose Input
91. 0x3 to Reserved 0 0 Input 0 1 Output GPY5CON S 15 12 0 2 EBI_DATA S 0x00 0x3 to OxE Reserved OxF 0 0 Input 0 1 Output GPYSCON 2 11 8 0 2 DATA 2 0 00 0x3 to OxE Reserved OxF 0 0 Input 10 1 Output GPYSCON 1 7 4 0 2 EBI DATA 1 0 00 0x3 to Reserved OxF 0 0 Input 0x1 Output GPY5CON 0 3 0 0x2 EBI DATA 0 0x3 to Reserved SAMSUNG ELECTRONICS 4 164 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 74 GPY5DAT Base Address 0x1100 0000 e Address Base Address 0x01C4 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPY5DAT 7 0 7 0 output port then pin state should be same as 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 3 75 GPY5PUD e Base Address 0x1100 0000 e Address Base Address 0x01C8 Reset Value 0x5555 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down GPY5PUDIn n 0to7 RW 0x2 Reserved 0x5555 0x3 Disables Pull up 4 3 3 76 GPY5DRV e Base Address 0x1100_0000 e Address Base Address 0x01CC Reset Value 0x00 AAAA 23 16 Reserved Should be zero W GPY5DRVIn n 2n 1 2n R ERA 0107 SAMSUNG ELECTRONICS 4 165 ex 4412 UM 4 General Pur
92. 1 It completes ECC encoding When ECC decoding is finished this value set and issue interrupt if DecodeDone is enabled The DecodeDone 24 RWX NFMLCLO and NFMLCEL1 have valid values To clear this write 1 1 completes MLC ECC decoding RSVD 23 9 Reserved 0x0000 FreePageStat R indicates whether the sector is page or not RSVD Reewd 10 7 3 4 NFECCSECSTAT e Base Address OXOCE2 0000 e Address Base Address 0x0040 Reset Value 0x0000 0000 ValdErrorStat 31 8 Each bit indicates which ERL and ERP are valid 0x0000 00 decoding result when page read 00000 No error 00001 1 bit error 00010 2 bit error 00011 3 bit error 50 01110 14 bit error 01111 15 bit error 10000 16 bit error NOTE If it uses 8 bit ECC the valid number of error is until 8 If the number exceeds the supported error number it means that uncorrectable error occurs SAMSUNG ELECTRONICS 10 30 4412 UM 10 NAND Flash Controller 10 7 3 5 NFECCPRGECCn 0 to 6 Base Address 0 0 2 0000 e Address Base Address 0 0090 Reset Value 0x0000 0000 NFECCPRGECCO e Address Base Address 0x0094 Reset Value 0x0000 0000 NFECCPRGECC1 e Address Base Address 0x0098 Reset Value 0x0000 0000 2 e Address Base Address 0 009 Reset Value 000 0000 NFECCPRGECC3 e Address
93. 1 0 7 1 Combined interrupt pending status 0 The combined interrupt is not pending 8 5 1 The combined interrupt is pending This means the corresponding interrupt request to the GIC is asserted INTG24 INTG23 INTG22 INTG21 INTG20 INTG19 INTG18 INTG17 INTG16 INTG15 INTG14 INTG13 INTG12 INTG11 INTG10 INTG9 INTG8 INTG7 INTG6 INTG5 INTG4 INTG3 INTG2 INTG1 INTGO INTG25 Gls N Name Type INTGS1 KEW INTGS0 HEN INTG29 INTG28_ NN INTG27 ELE LINTG20 EN INTG25 INTG24 MESA INTGZS EM INTGZ2 um NG INTGZ0 OR INIGIS OR INTGA7 INIGIG n INIGIS EN INTGH4 OR INTGIS OR INTGIB NTA OR INTGIO MESA Duss OR NT __ OR INTG7 OR NT OR NIGS R NGA NG R NEAN INTGO EN SAMSUNG ELECTRONICS 7 30 en 4412 UM 8 Direct Memory Access Controller DMAC Direct Memory Access Controller DMAC This chapter includes e Overview DMA Controller Register description e Instruction 8 1 Overview The two Direct Memory Access DMA tops that Exynos 4412 supports Memory to Memory 2 transfer mem Peripheral to memory transfer and vice versa peri The consists of one PL330
94. 12 4 1 2 WTDAT e Base Address 0x1006 0000 e Address Base Address 0x0004 Reset Value 0 0000 8000 Reserved WDT count value reload 0 8000 WTDAT register specifies the time out duration You cannot load the content of WTDAT into the timer counter at initial WDT operation However by using 0x8000 initial value drives the WDT counter first time out In this case WDT counter logic reloads the value of WTDAT automatically into WTCNT 12 4 1 3 WTCNT Base Address 0x1006_0000 e Address Base Address 0x0008 Reset Value 0x0000_8000 85 0 Pesene _ 15 0 The current count value of the WDT 0x8000 The WTONT register contains the current count values for the WDT during normal operation WDT counter logic cannot automatically load the content of WTDAT register into the timer count register if it enables the WDT initially Therefore you should set the WTCNT register to an initial value before enabling it 12 4 1 4 WTCLRINT e Base Address 0x1006 0000 e Address Base Address 0x000C Reset Value Undefined Interrupt clear 31 0 Write any value to clear the interrupt ME You can use the WTCLRINT register to clear the interrupt Interrupt service routine is responsible to clear the relevant interrupt after the interrupt service is complete Writing any values on this register clears the interrupt Reading on this register is not allowed SAMSUNG ELECTRONICS 12 6 II
95. 2 CAM SPI 55 0 3 CAM_GPIO 15 0 4 to Reserved EXT INT12 5 0 0 Input 0 1 Output 0 2 CAM SPI CLK 0 3 CAM_GPIO 14 0 4 to Reserved OxF EXT_INT12 4 0 0 Input 0 1 Output 0 2 2 1 SDA 0x3 CAM_GPIO 13 0x4 CAM_SPI1_nSS 0 5 to OxE Reserved OxF EXT_INT12 3 0 0 Input 0 1 Output 0 2 1261 SCL 0x3 CAM_GPIO 12 0 4 CAM_SPI1_CLK 0 5 to OxE Reserved OxF EXT_INT12 2 0 0 Input 0 1 Output 0 2 2 0 SDA 0 3 CAM_GPIO 11 0 4 to Reserved OxF EXT_INT12 1 4 188 4412 UM 4 General Purpose Input Output GPIO Control 0x0 Input 0x1 Output 0 2 12 0 SCL GPMACON 0 3 0 RW 0x3 GPIO 10 0 4 to OxE Reserved EXT INT12 0 SAMSUNG ELECTRONICS 4 189 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 114 GPM4DAT Base Address 0x1100 0000 e Address Base Address 0 02 4 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPMADATT 7 0 7 0 output port then pin state should be same as 0x00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 3 115 GPM4PUD Base Address 0x1100_0000 e Address Base Address 0x02E8 Reset Value 0x5555 0x0 Disables Pull up Pull down
96. 4412 UM 11 Pulse Width Modulation Timer 11 5 1 12 2 e Base Address 0x139D_0000 PWM Base Address 0x1216 0000 PWM ISP e Address Base Address 0x002C Reset Value 0x0000 0000 Timer 2 count 31 0 Timer 2 Count Observation register 0x0000 0000 observation 11 5 1 13 TCNTB3 Base Address 0x139D 0000 PWM e Base Address 0x1216 0000 ISP e Address Base Address 0x0030 Reset Value 0x0000 0000 s 9 Count 31 0 Timer 3 Count Buffer register 0x0000 0000 11 5 1 14 TCMPB3 Base Address 0x139D 0000 PWM e Base Address 0x1216 0000 PWM ISP e Address Base Address 0x0034 Reset Value 0x0000 0000 p pampare 31 0 Timer 3 Compare Buffer register 0x0000 0000 11 5 1 15 TCNTO3 e Base Address 0x139D 0000 PWM e Base Address 0x1216 0000 ISP e Address Base Address 0x0038 Reset Value 0x0000 0000 Timer 3 count 31 0 Timer 3 Count Observation register 0 0000_0000 observation SAMSUNG ELECTRONICS 11 21 ex 4412 UM 11 Pulse Width Modulation Timer 11 5 1 16 TCNTB4 e Base Address 0x139D 0000 PWM Base Address 0x1216_0000 PWM ISP e Address Base Address 0x003C Reset Value 0x0000_0000 Timer oon 31 0 RW Timer 4 Count Buffer register 0x0000_0000 buffer 11 5 1 17 TCNTO4 e Base Address 0x139D_0000 PWM e Base Address 0x1216_0000 PWM_ISP e Address Base Address 0x0040 Reset Value 0x0000_ 0000 31
97. 5 INTG14 2 020000000 mm Interrupt Source Source Block PPMU LODO DMC1_PPC_PEREV_M DMC1 DMC1_PPC_PEREV_A DMCO_PPC_PEREV_M DMCO DMCO_PPC_PEREV_A L2CACHE L2 Cache GPIO AUDIO Audio SS G G G N Reserved SAMSUNG ELECTRONICS 7 5 4412 UM 7 Interrupt Combiner Combiner Group ID Combined Interrupt Source Source Block Source Name m scuevasom 6 Resewed O INTG16 ISP SYSMMU FIMO LEO 6 Reserved INTG17 ISP 10 SYSMMU FIMO Leo ceunraout PARITYFAIL2 T lt lt 6 GPU nIRGOUTI3 PARITYFAILSCU 3 PARITYFALS INTG19 a 4 PARITYFAIL3 2 PMUIRALS SAMSUNG ELECTRONICS 7 6 4412 UM 7 Interrupt Combiner Combiner Group ID Combined Interrupt Source Source Block Source Name SAMSUNG ELECTRONICS 7 7 ex 4412 UM 7 Interrupt Combiner 7 5 Functional Description An interrupt enable bit controls an interrupt source in an interrupt group IESRn and IECRn registers control the interrupt enable bits IESRn register can toggle an interrupt bit to 1 If you write 1 to a bit position on IESRn then it sets the corresponding bit on the interrupt enable bit to 1 However IECRn register can toggle an interrupt enable bit to O If you write 1 to a bit position on IECRn then it clears the corresponding bi
98. ASYNC C2C _XIUL es CLK SMMUG2D _ 27 24 Gating all clocks for ASYNC_GDL 0 Mask 1 Pass CLK_ASYNC_GDL 21 D CLK IEM IEC 18 CLK IEM APC 17 CLK PPMUACP 16 SAMSUNG ELECTRONICS 5 132 Gating all clocks for GIC 0 Mask 1 Pass Reserved Gating all clocks for IEM IEC 0 Mask 1 Pass Gating all clocks for IEM 0 Mask 1 Pass Gating all clocks for PPMUCPU 0 Mask 1 Pass Gating all clocks for ASYNC_GDR CLK_ASYNC_GDR 22 RW 0 Mask 1 Pass 4412 UM 5 Clock Management Unit ASV mq Rm 00000 Gating all clocks for ID REMAPPER SIP 13 RW Mask REMAPPER 13 0 Mas 1 Pass Gating all clocks for SMMUSSS CLK SMMUSSS 12 RW 0 Mask 1 Pass mv on Gating all clocks for PPMUCPU CLK PPMUCPU 10 0 Mask 0 1 1 Pass Gating all clocks for PPMUDMC 1 CLK PPMUDMC 1 0 Mask 0 1 1 Pass Gating all clocks for PPMUDMCO CLK PPMUDMCO 0 Mask 0 1 1 Pass Gating all clocks for FBMDMC1 FBMDMC1 0 Mask Ox1 1 Pass Gating all clocks for FBMDMCO CLK_FBMDMCO 5 0 Mask 0 1 1 Pass Gating all clocks for SSS CLK SSS 4 0 Mask 1 Pass m Gating all clocks for INT_COMB CLK_INT_COMB 2 RW 0 Mask 1 Pass mw fm few Gating all clocks for DREX2 CLK DREX2 RW 0 Mask 1 Pass SAMSUNG ELECTRONICS 5 133 en 4412 UM 5 Clock Management Unit 5 10 1 1
99. Base Address 0x0818 Reset Value 0x0000 0000 Filter Enable for EXT INT24 3 FLTEN4 3 31 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH4 3 30 24 Filtering width of EXT_INT24 3 Filter Enable for EXT_INT24 2 FLTEN4 2 23 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH4 2 22 16 Filtering width of EXT INT24 2 Filter Enable for EXT INT24 1 FLTENA 1 15 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH4 1 14 8 Filtering width of EXT INT24 1 Filter Enable for EXT INT24 0 FLTEN4 0 7 RW Disables Filter 0 1 Enables Filter FLTWIDTHA 0 6 0 RW Filtering width of EXT_INT24 0 4 3 3 134 INT24 1 e Base Address 0x1100 0000 e Address Base Address 0x081C Reset Value 0x0000 0000 RSV prea om Filter Enable for EXT_INT24 6 FLTEN4 6 23 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH4 6 22 16 Filtering width of EXT INT24 6 Filter Enable for EXT INT24 5 FLTEN4 5 15 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH4 5 14 8 Filtering width of EXT_INT24 5 Filter Enable for EXT_INT24 4 FLTEN4 4 7 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTHA 4 6 0 RW Filtering width of EXT INT24 4 SAMSUNG ELECTRONICS 4 215 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 135 EXT_INT25_FLTCONO Base Address 0x1100 0000 e
100. Base Address 0x0828 Reset Value 0x0000 0000 Filter Enable for EXT INT26 3 FLTEN6 3 31 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTHe 3 30 24 Filtering width of EXT INT26 3 Filter Enable for EXT INT26 2 FLTEN6 2 23 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH6 2 22 16 Filtering width of EXT_INT26 2 Filter Enable for EXT_INT26 1 FLTEN6 1 15 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH6 1 14 8 Filtering width of EXT INT26 1 Filter Enable for EXT INT26 0 FLTEN6 0 7 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTHe o 6 0 RW Filtering width of EXT INT26 0 4 3 3 138 EXT INT26 1 e Base Address 0x1100 0000 e Address Base Address 0x082C Reset Value 0x0000 0000 RSV prea nesen Filter Enable for EXT INT26 6 FLTEN6 6 23 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTHe 6 22 16 Filtering width of INT26 6 Filter Enable for EXT_INT26 5 FLTEN6 5 15 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH6 5 14 8 Filtering width of EXT_INT26 5 Filter Enable for EXT INT26 4 FLTEN6 4 7 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH6 4 6 0 Filtering width of INT26 4 SAMSUNG ELECTRONICS 4 217 en 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 139 EXT_INT27_FLTCONO e Base Address 0x1100 0000 e Address Base Ad
101. CPU BUS DRAM ISP 5 12 Figure 5 2 Exynos4412 Clock Generation Circuit Special 5 14 Figure 5 3 Exynos4412 CLKOUT Control 10 5 20 Figure 5 4 Exynos4412 Clock Controller Address Map 5 25 Figure 6 1 Interrupt Sources 6 4 Figure 7 1 Block Diagram of Interrupt Combiner 7 2 Figure 8 1 Two DMA ops aa a dai 8 1 Figure 9 1 Block Diagram of SROMC 9 1 Figure 9 2 SROMC nWAIT Timing Diagram U 9 2 Figure 9 3 SROMC Read Timing Diagram 2 2224 00 9 3 Figure 9 4 SROMC Write Timing Diagram 9 3 Figure 10 1 Flash Controller Block 10 2 Figure 10 2 CLE and ALE Timing TACLS 1 TWRPHO 0 TWRPH1 0 2000442 000 10 3 Figure 10 3 and nRE Timing TWRPHO 0 TWRPH1 0 10 3 Figure 10 4 Accessibility 10 13 Figure 11 1 Simple Example a PWM 11 2 Figure 11 2 TIMER Clock Tree 11 3 Figure 11 3 Timer Operations dieere Ree eter Lat cota rut E te ERE Ee
102. Da Pemu m n SAMSUNG ELECTRONICS 7 21 ex 4412 UM 7 Interrupt Combiner 7 6 2 13 IESR3 Base Address 0x1044 0000 e Address Base Address 0x0030 Reset Value 0x0000_0000 DECERRINTR 31 SLVERRINTR 30 Sets the corresponding interrupt enable bit to 1 If you ERRRDINTR set the interrupt enable bit interrupt combiner serves 29 the interrupt reguest ERRRTINTR 28 Write 0 Does not change the current setting ERRWDINTR 27 1 Sets the interrupt enable bit to 1 Read The current interrupt enable bit ERRWTINTR 2 RW ERRWTINTR 26 RW SCUEVABORT 0 RSVD CPU nIRQOUT 1 22 Sets the corresponding interrupt enable bit to 1 If you RSVD en set the interrupt enable bit interrupt combiner serves 21 the interrupt reguest RSVD 20 EN Write 0 Does not change the current setting O RSVD 19 1 Sets the interrupt enable bit to 1 cO Read The current interrupt enable bit RSVD 1 RD E RSVD 1 Enables EE RSVD EE HEVD ata MES Sets the corresponding interrupt enable bit to 1 If you __ CPU nIRQOUT 0 13 set the interrupt enable bit interrupt combiner serves RSVD 12 ow the interrupt request 05900 RSVD 11 Write 0 Does not change the current setting NE 1 Sets the interrupt enable bit to 1 RSVD 10 Read The current interrup
103. EXT 26 MASK 4 EXT INT26 MASK 3 EXT 26 MASK 2 EXT INT26 MASK 1 0 0 Enables Interrupt 0 1 Masked 5 pe x 4 Interrupt 4 e quond Interrupt 3 2 Interrupt 2 A Interrupt 1 a 2 Interrupt 0 0 Enables Interrupt EXT 26 MASK 0 0 1 Masked SAMSUNG ELECTRONICS 4 231 7 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 159 EXT_INT27_MASK e Base Address 0x1100 0000 e Address Base Address 0x0918 Reset Value 0x0000 007F 0 0 Enables Interrupt 0 0 Enables Interrupt EXT INT27 MASK 5 5 Oxi Masker 0 0 Enables Interrupt EXT INT27 MASK 4 4 0 1 Masked 0x0 Enables Interrupt EXT INT27 MASK 2 2 0x1 Masked 0 0 Enables Interrupt EXT INT27 MASK 1 1 0x1 Masked 0 0 Enables Interrupt EXT INT27 0 1 Masked 4 3 3 160 EXT_INT28_MASK EXT 27 MASK 3 3 D Fe e Base Address 0x1100_0000 e Address Base Address 0x091C Reset Value 0 0000 0003 0x0 Enables Interrupt 0x0 Enables Interrupt SAMSUNG ELECTRONICS 4 232 x 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 161 EXT_INT29_MASK e Base Address 0x1100 0000 e Address Base Address 0x0920 Reset Value 0x0000_00FF EXT 29 EXT INT29 MASK 6 Rw p suec EXT INT29 MASK 5 5 E 2 5 EXT INT29 5 4 4 m
104. Enables Interrupt 5 0 1 Masked 4 gt 4 Interrupt 3 Interrupt 2 m I 2 Interrupt 1 n 5 Interrupt 0 0 Enables Interrupt EXT 23 MASK 0 0 1 Masked 4 3 3 156 INT24 MASK Base Address 0x1100_0000 e Address Base Address 0x090C Reset Value 0x0000_007F EXT 24 MASK 6 EXT 24 MASK 5 EXT 24 MASK 4 EXT INT24 MASK 3 EXT INT24 MASK 2 EXT INT24 MASK 1 0 0 Enables Interrupt 0 1 Masked 5 pe x 4 Interrupt 4 e quond Interrupt 3 2 Interrupt 2 A Interrupt 1 a 2 Interrupt 0 0 Enables Interrupt EXT 24 MASKI 0 0 1 Masked SAMSUNG ELECTRONICS 4 230 7 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 157 EXT_INT25_MASK e Base Address 0x1100 0000 e Address Base Address 0x0910 Reset Value 0x0000 007F RSVD EXT 25 MASK 6 EXT INT25 MASK 5 EXT 25 MASK 4 EXT 25 MASK 3 EXT 25 MASK 2 EXT 25 MASK 1 0 0 Enables Interrupt 0 1 Masked 0 0 Enables Interrupt 5 0 1 Masked 4 gt 4 Interrupt 3 Interrupt 2 m I 2 Interrupt 1 n 5 Interrupt 0 0 Enables Interrupt EXT 25 MASK 0 0 1 Masked 4 3 3 158 EXT_INT26_MASK Base Address 0x1100 0000 e Address Base Address 0x0914 Reset Value 0x0000_007F EXT 26 MASK 6 EXT INT26 MASK 5
105. GPIO Control 4 3 3 38 GPL2DAT e Base Address 0x1100 0000 e Address Base Address 0x0104 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPL2DAT 7 0 7 0 output port the pin state should be same as the 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 3 39 GPL2PUD Base Address 0x1100 0000 e Address Base Address 0x0108 Reset Value 0x5555 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down GPL2PUD n n 0to7 RW 0x2 Reserved 0x5555 0x3 Disables Pull up 4 3 3 40 GPL2DRV e Base Address 0x1100 0000 e Address Base Address 0x010C Reset Value 0x00_0000 23 16 Reserved Should be zero W GPL2DRVIn n 2n 1 2n R 0x0000 0107 SAMSUNG ELECTRONICS 4 145 II 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 41 GPL2CONPDN Base Address 0x1100 0000 e Address Base Address 0x0110 Reset Value 0x0000 0 0 Outputs 0 2n 1 21 0 1 Outputs 1 GRAN 0107 FUN 0x2 Input 999 0 3 Previous state 4 3 3 42 GPL2PUDPDN Base Address 0x1100_0000 e Address Base Address 0x0114 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down 0107 i 0x2 Reserved 990 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 146 ex 4412 UM
106. Last received bit status flag SAMSUNG ELECTRONICS 14 16 4412 UM 14 6 1 3 I2CADDn n 0 to 7 RSVD Slave address 7 0 RWX Base Address Base Address Base Address Base Address Base Address Base Address Base Address Base Address Base Address 0x1386 0000 0x1387 0000 0x1388 0000 0x1389 0000 0x138A 0000 0x138B 0000 0x138C 0000 0x138D 0000 0x138E 0000 14 Inter Integrated Circuit Address Base Address 0x0008 Reset Value OxXX SAMSUNG ELECTRONICS pup ree 7 bit slave address latched from the I2C bus When serial output enable 0 in the I2CSTAT I2CADD is write enabled The I2CADD value is Read any time regardless of the current serial output enable bit I2CSTAT setting Slave address 7 1 Not mapped 0 14 17 4412 UM 14 6 1 4 I2CDSn n 0 to 7 RSVD Data shift 7 0 RWX Base Address Base Address Base Address Base Address Base Address Base Address Base Address Base Address Base Address 0x1386_0000 0 1387_0000 0 1388_0000 0 1389_0000 0x138A_0000 0x138B_0000 0x138C_0000 0x138D_0000 0x138E_0000 14 Inter Integrated Circuit Address Base Address 0x000G Reset Value SAMSUNG ELECTRONICS ere ree 8 bit data shift register for I2C bus Tx Rx operation When serial output enable 1 in the I2CSTAT 12CDS is write enabled The I2CDS value is Read any time regardless of the
107. Lm 4412 UM 16 Display Controller 101 RBG 110 where RGBSPSEL 1 b1 or RGBSPSEL 1 b0 and RGB SKIP EN 1 b1 000 R gt G gt B 001 G gt 010 B gt R gt G 100 B gt G gt R 101 R gt B gt G 110 G gt R gt B NOTE PNRO 0 at VIDCONO should be set to 0 when you use RGB_ORDER_E 2 0 at VIDCONS register Reserved RSVD 15 14 revo mp NOTE This bit should be set to 1 Specifies output format of YUV data 00 Reserved TVFORMATSEL 13 12 RW 01 YUV422 1 YUV444 Specifies order of YUV data OrgYCbCr RW 0 Y CbCr 1 CbCr Specifies order of Chroma data YUVOrd 7 RW 0 Cb Cr 1 Cb mew CN Controls WB frame skip rate The maximum rate is up to 1 30 only where VIDOUT 2 0 3 b001 or 3 b100 TV encoder interface INTERLACE_F 1 b0 and TV422 or TVRGB output WB_FRAME 00000 No skip 1 1 4 RW _SKIP 4 0 00001 Skip rate 1 2 00010 Skip rate 1 3 11101 Skip rate 1 0 1111x Reserved SAMSUNG ELECTRONICS 16 61 ex 4412 UM 16 Display Controller 16 5 3 4 VIDCON3 e Base Address 0x11C0_0000 e Address Base Address 0x000C Reset Value 0x0000_0000 Reserved 8121 NOTE This bit should be setto 0 RSVD 2019 18 Enables Control Color Gain CG_ON 0 Disables bypass 1 Enables Enables Control Gamma GM_ON 16 0 Disables bypass GM_MODE 15
108. M Command RS ovos AS J o AS F Fw m RW Contos Command HRS m RW Convots Command o SAMSUNG ELECTRONICS 16 115 IT 4412 UM 16 Display Controller 16 5 3 64 SIFCCONO e Base Address 0x11C0_0000 e Address Base Address 0 01 0 Reset Value 0x0000 0000 Reserved NOTE This bit should be set to 0 Controls LCD 80 System Interface ST Signal SYS_ST_CON 0 Low 1 High Controls LCD 80 System Interface RS Signal SYS_RS_CON 0 Low 1 High Controls LCD 180 System Interface 0 main Signal SYS nCS0 CON 0 Disables High 1 Enables Low Controls LCD i80 System Interface nOE Signal SYS nOE CON 0 Disables High 1 Enables Low Controls LCD i80 System Interface nWE Signal SYS nWE CON 0 Disables High 1 Enables Low Enables LCD i80 System Interface Command Mode SCOMEN 0 Disables Normal Mode 1 Enables Manual Command Mode 16 5 3 65 SIFCCON1 Controls LCD 180 System Interface nCS1 sub Signal SYS 51 CON 0 Disables High 1 Enables Low e Base Address 0x11C0 0000 e Address Base Address 0 01 4 Reset Value 0x0000 0000 SYS WDATA 23 0 Controls LCD i80 System Interface Write Data SAMSUNG ELECTRONICS 16 116 ex 4412 UM 16 Display Controller 16 5 3 66 SIFCCON2 e Base Address 0x11C0_0000 e Address
109. RSVD Reseed fo Sets signaling method of EXT INT5 4 0x0 Low level 0x1 High level EXT_INT5_CON 4 18 16 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0 7 Reserved RSV mp Rem ov Sets signaling method of EXT_INT5 3 0 0 Low level 0 1 High level EXT INT5 CON 3 14 12 RW 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved ASV n Sets signaling method of EXT_INT5 2 0x0 Low level 0x1 High level EXT INT5 CON 2 10 8 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved Sets signaling method of EXT_INT5 1 0 0 Low level 0x1 High level EXT INT5 CON 1 6 4 RW 0 2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0x7 Reserved Sets signaling method of EXT INT5 0 0 0 Low level 0 1 High level EXT INT5 CON 0 2 0 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 68 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 86 EXT_INT6CON Base Address 0x1140_0000 e Address Base Address 0x0714 Reset Value 0 0000 0000 RSVD mq fo Sets signaling method of EXT INT6 3 0x0 Low level 0x1 High level EXT INT6 CON 3 14 12 RW 0x2 Trig
110. RSVD eme mee fo Filter Enable for EXT INT34 1 FLTEN5 1 15 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH5 1 14 8 Filtering width of EXT INT34 1 Filter Enable for EXT INT34 0 FLTEN5 O 7 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH5 O 60 RW Filtering width of EXT_INT34 0 4 3 5 49 EXT_INT34_FLTCON1 Base Address 0x106E_0000 e Address Base Address 0x0824 Reset Value 0x0000_0000 SAMSUNG ELECTRONICS 4 331 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 50 EXT_INT30_MASK Base Address Ox106E 0000 e Address Base Address 0x0900 Reset Value 0x0000_00FF 0 0 Enables Interrupt 0 0 Enables Interrupt EXT INT30 MASK 6 Rw 0 1 Masked 0x0 Enables Interrupt EXT_INT30_MASKT 5 5 0 1 Masked 0x0 Enables Interrupt EXT INT30 MASK 3 3 0 1 Masked 0 0 Enables Interrupt EXT INT30 MASK 2 2 0x1 Masked 0 0 Enables Interrupt EXT INT30 MASK 1 1 0 1 Masked 0 0 Enables Interrupt 0 0 Enables Interrupt SAMSUNG ELECTRONICS 4 332 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 51 EXT_INT31_MASK Base Address 0x106E_0000 e Address Base Address 0x0904 Reset Value 0x0000_00FF o MASA E EXT_INT31_MASKT 5 5 ce _ 4 EXT INT31 MASK 4 4 od N Masked 90 Es ner
111. Reset Value 0x0000 0000 Filter Enable for EXT_INT2 5 FLTEN2 5 15 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH2 5 143 Filtering width of EXT INT2 5 Filter Enable for EXT INT2 4 FLTEN2 4 7 RW Disables filter 0 1 Enables filter FLTWIDTH2 4 6 0 Filtering width of EXT INT2 4 SAMSUNG ELECTRONICS 4 84 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 98 EXT_INT3_FLTCONO Base Address 0x1140_0000 e Address Base Address 0x0810 Reset Value 0x0000_0000 Filter Enable for EXT INT3 3 FLTENS S3 31 RW 0 0 Disables filter 0 1 Enables filter FLTWIDTH3 3 30 24 Filtering width of EXT INT3 3 Filter Enable for EXT INT3 2 FLTEN3 2 23 RW 0 0 Disables filter 0 1 Enables filter FLTWIDTH3 2 22 16 Filtering width of EXT_INT3 2 Filter Enable for EXT INT3 1 FLTENS 1 15 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH3 1 14 8 Filtering width of EXT_INT3 1 Filter Enable for EXT_INT3 0 FLTEN3 0 7 RW 0 0 Disables filter 0 1 Enables filter FLTWIDTH3 0 6 0 Filtering width of EXT INT3 0 SAMSUNG ELECTRONICS 4 85 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 99 EXT_INT3_FLTCON1 e Base Address 0x1140 0000 e Address Base Address 0x0814 Reset Value 0x0000 0000 Filter Enable for EXT INT3 7 FLTEN3 7 31 RW 0x0 Disables filter 0 1 Enable
112. Reset Value 0x0000 001F RSVD Reserved 0x0000000 EXT INT10 MASK 4 RW 0 0 Enables Interrupt 0 1 Masked 0 0 Enables Interrupt EXT INT10 MASK 3 3 0 1 Masked 0x0 Enables Interrupt EXT INT10 MASK 1 1 0 1 Masked 0x0 Enables Interrupt EXT INT10 MASK 0 0 1 Masked 0 0 Enables Interrupt SAMSUNG ELECTRONICS 4 235 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 165 EXT_INT11_MASK e Base Address 0x1100 0000 e Address Base Address 0x0930 Reset Value 0x0000_00FF MISH a on EXT_INT11_MASK 5 5 _ 4 EXT INT11 MASK 4 4 s _ DOE ec armas m 90 Esl merum Banm maske m aw DO Eras neu 0 0 Enables Interrupt EXT INT11 MASK 1 1 0 1 Masked 0 0 Enables Interrupt EXT INT11 Rw 0 1 Masked SAMSUNG ELECTRONICS 4 236 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 166 EXT_INT12_MASK e Base Address 0x1100 0000 e Address Base Address 0x0934 Reset Value 0x0000_00FF m one EXT_INT12_MASKT 5 5 ce _ 4 or maso aw 007 Ene ec mee m 90 Es merum vaske m aw nocere 0 0 Enables Interrupt EXT INT12 MASK 1 1 0 1 Masked 0 0 Enables Interrupt EXT INT12 MASK 0 Rw 0 1 Masked SAM
113. SAMSUNG ELECTRONICS 13 1 ex 4412 UM 13 Universal Asynchronous Receiver and Transmitter 13 3 1 Data Transmission The data frame for transmission is programmable lt consists of these bits that are specified by the line control register ULCONn e A Star bit e Five to eight data bits e optional parity bit e One to two stop bits The transmitter also produces a break condition that forces the serial output to logic 0 state for one frame transmission time This block transmits the break signals after it completely transmits the present transmission word After the break signal transmission the transmitter continuously transmits data to Tx FIFO Tx holding register in case of non FIFO mode 13 3 2 Data Reception The data frame for reception is also programmable It consists of a start bit five to eight data bits an optional parity bit and to two stop bits in the line control register ULCONn The receiver detects these errors and each of these errors sets an error flag e Overrun error This error indicates that new data has overwritten the old data before the old data was read e Parity error This error indicates that the receiver has detected an unexpected parity condition e Frame error This error indicates that the received data does not have a valid stop bit e Break condition This indicates that the RxDn input is held in the logic 0 state for more than one frame transmission time Receive time
114. This bit should be set to 0 Specifies Window Size DSIZE 23 pu ekample Height Width number of word MEN 16 5 3 23 VIDOSD2A e Base Address 0x11C0_0000 e Address Base Address 0x0060 Reset Value 0x0000_0000 OSD LeftTopX F 21 11 RW Specifies horizontal screen coordinate for left top pixel of OSD image Specifies vertical screen coordinate for left top pixel of OSD image OSD LeftTopY F 10 0 For interlace TV output this value should be set to half of the original screen y coordinate The original screen coordinate should be even value SAMSUNG ELECTRONICS 16 87 4412 UM 16 Display Controller 16 5 3 24 VIDOSD2B e Base Address 0x11C0_0000 e Address Base Address 0x0064 Reset Value 0x0000_0000 ENE ENE 21 11 Specifies horizontal screen coordinate for right bottom pixel of OSD image Specifies vertical screen coordinate for right bottom pixel of OSD image OSD_RightBotY_F 10 0 For interlace TV output this value should be set to half of the original screen y coordinate The original screen y coordinate should be odd value NOTE Registers should have word boundary X position Therefore 24 BPP mode should have X position by 1 pixel For example 0 1 2 3 16 BPP mode should have X position by 2 pixel For example X 0 2 4 6 8 BPP mode should have X position by 4 pixel For example 0 4 8 12 1
115. Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT32 1 0 0 Low level 0x1 High level EXT INT32 CON 1 6 4 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT32 0 0 0 Low level 0x1 High level EXT INT32 CON 0 2 0 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 319 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 38 EXT_INT33CON Base Address Ox106E 0000 e Address Base Address 0x070C Reset Value 0x0000 0000 RSV on eee To Sets signaling method of EXT INT33 7 0 0 Low level 0 1 High level EXT INT33 CON 7 30 28 RW 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0x5 to 0x7 Reserved 85 2 esee ooo Sets signaling method of EXT INT33 6 0x0 Low level 0 1 High level EXT INT33 CON 6 26 24 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0 7 Reserved SVO Jo Sets signaling method of EXT INT33 5 0 0 Low level 0 1 High level EXT INT33 CON 5 22 20 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0 5 to 0x7 Reserved 85 0
116. Underrun error Tx FIFO overrun error 0 No error 1 Overrun error Tx FIFO underrun error 0 No error 1 Underrun error NOTE Tx FIFO underrun error will occur if Tx FIFO is empty in slave mode 0 Data in FIFO less than trigger level 1 Data in FIFO more than trigger level 0 Data in FIFO more than trigger level 1 Data in FIFO less than trigger level 15 12 4412 UM 15 Serial Peripheral Interface 15 5 1 6 SPL TK DATAn n 0 to 2 Base Address 0x1392 0000 e Base Address 0x1393 0000 Base Address 0x1394_0000 Address Base Address 0x0018 Reset Value 0x0 TX_DATA 31 0 W This field contains the data to be transmitted over the SPI channel 15 5 1 7 SPI RX DATAn 0 to 2 Base Address 0x1392 0000 e Base Address 0x1393 0000 Base Address 0x1394 0000 e Address Base Address 0x001C Reset Value 0 0 This field contains the data to be received over the 15 5 1 8 PACKET CNT REGn n 0 to 2 e Base Address 0x1392 0000 e Base Address 0x1393 0000 Base Address 0x1394 0000 Address Base Address 0x0020 Reset Value 0x0 RSV eras bit for packet count PACKET CNT EN 16 RW 0 Disables 1 Enables COUNT VALUE 15 0 Packet count value SAMSUNG ELECTRONICS 15 13 ex 4412 UM 15 Serial Peripheral Interface 15 5 1 9 PENDING REGn n 0 to 2 Base Address 0x1392_0000 e Base Address 0x1393 00
117. Unpacked 18 BPP non palletized R 6 G 6 B 6 1001 Unpacked 18 BPP non palletized A 1 R 6 G 6 B 5 1010 Unpacked 19 BPP non palletized A 1 R 6 G 6 BPPMODE_F 5 2 RW B 6 1011 Unpacked 24 BPP non palletized R 8 G 8 B 8 1100 Unpacked 24 BPP non palletized A 1 R 8 G 8 B 7 1101 Unpacked 25 BPP non palletized A 1 R 8 G 8 B 8 1110 Unpacked 13 BPP non palletized A 1 R 4 G 4 B 4 1111 Unpacked 15 BPP non palletized R 5 G 5 B 5 NOTE 1 1101 Support unpacked 32 BPP non palletized A 8 R 8 G 8 B 8 for per pixel blending 2 1110 Support 16 BPP non palletized A 4 R 4 G 4 B 4 for per pixel blending 16 level blending SAMSUNG ELECTRONICS 16 79 Reserved NOTE This bit should be set to 0 Specifies Multiplied Alpha value mode 0 Disables multiplied mode 1 Enables multiplied mode When ALPHA_MUL is 1 set BLD PIX 1 ALPHA SEL 1 and BPPMODE _F 5 2 4 b1101 or 4 b1110 NOTE Alpha value alpha pixel from data x ALPHAO R G B 4412 UM 16 Display Controller Selects Alpha value When Per plane blending case BLD_PIX 0 0 Uses ALPHAO R G B values 1 Uses ALPHA1_R G B values ALPHA_SEL_F 1 RW When Per pixel blending BLD_PIX 1 0 Selected by AEN A value 1 Uses DATA 31 24 data word boundary only when BPPMODE_F 4 b1101 DATA 31 28 15 12 data in word boundary only when BPPMODE_F 4 b1110 Enables disables video output a
118. e MRR should fall in the range of 1 lt MRR lt 31 e OxMRRxMFR lt 512 e SEL PF 1 0 2000 x SEL PF lt 2 b10 SAMSUNG ELECTRONICS 5 52 ex 4412 UM 5 Clock Management Unit 5 10 1 24 VPLL CON2 e Base Address 0x1003 0000 e Address Base Address 0xC128 Reset Value 0x0000 0080 12 8 AFC value Decides whether DCC is enabled or not 0 Enables DCC PUU RW 1 disables It is an active low signal Decides whether AFC is enabled or not When enabled VCO is calibrated automatically AFC ENB RW 0 Enables AFC 1 Disables AFC It is an active low signal If BYPASS 1 then it enables bypass mode Four BYPASS 4 RW Fin IF BYPASS 0 then the PLL3600X operates normally FVCO EN Enable pin for our Specifies pin selection for monitoring purposes FSEL 2 RW if is set to 0 Fvco our FEED if FseL is set to 1 ICP_BOOST ICP_BOOST AFC_ENB is set to logic LOW then it enables the AFC If AFC_ENB is set to logic HIGH then EXTAFC 4 0 controls the VCO frequency tuning range Specifies if the dithered mode is enabled or not SSCG_EN 5 RW 0 Disables dithered mode 1 Enables dithered mode EXTAFC specifies the decimal value of EXTAFC 4 0 as EXTAFC EXTAFC 4 0 The hexadecimal values specified for EXTAFC 4 0 registers are e 560 0000 lt EXTAFC 4 0 lt 5 b1 1111 NOTE
119. is 0 1 Filter Enable for EXT_INT41 1 FLTEN16 1 0x0 Disables Filter 0x1 Enables Filter Filter Selection for EXT_INT41 1 FLTSEL16 1 0 0 Delays filter 0x1 Digital filter clock count Filtering width of EXT_INT41 1 FLTWIDTH16 1 This value is valid when FLTSEL16 of EKT INT41 is 0x1 Filter Enable for EXT INT41 0 FLTEN16 0 0x0 Disables Filter 0 1 Enables Filter Filter Selection for EXT_INT41 0 FLTSEL16 0 0 0 Delays filter Ox1 Digital filter clock count Filtering width of EXT INT41 0 FLTWIDTH16 0 This value is valid when FLTSEL16 of EXT 41 is Ox1 SAMSUNG ELECTRONICS 4 274 en 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 217 EXT_INT41_FLTCON1 e Base Address 0x1100 0000 e Address Base Address OxOE8C Reset Value 0x8080_8080 Filter Enable for EXT INT41 7 FLTEN16 7 0 0 Disables Filter 0x1 Enables Filter Filter Selection for EXT_INT41 7 FLTSEL16 7 0 0 Delays filter 0x1 Digital filter clock count Filtering width of EXT_INT41 7 FLTWIDTH16 7 This value is valid when FLTSEL16 of EKT INT41 is 0x1 Filter Enable for EXT_INT41 6 FLTEN16 6 0x0 Disables Filter 0x1 Enables Filter Filter Selection for EXT_INT41 6 FLTSEL16 6 0 0 Delays filter 0x1 Digital filter clock count Filtering width of EXT_INT41 6 FLTWIDTH16 6 This value is valid when FLTSEL16 of EKT INT41 is 0 1 Filter Enable for EXT_INT41 5 FLTEN16 5 0
120. such case both masters detect Low on the bus This is because the Low status is superior to the High status in power When this happens the Low as the first bit of address that generates master gets the mastership while the High as the first bit of address that generates master withdraws the mastership When both masters generate Low as the first bit of address there 15 arbitration for the second address bit again This arbitration continues till the end of last address bit 14 4 6 Abort Conditions When a Slave receiver cannot acknowledge the confirmation of the slave address it holds the level of the SDA line High In this case the master generates a Stop condition and cancels the transfer When a master receiver is involved in the aborted transfer it signals the end of Slave transmit operation by canceling the generation of an ACK This happens after the Master receives the last data byte from the Slave The Slave transmitter releases the SDA to enable a master to generate a Stop condition 14 4 7 Configuring I2C Bus To control the frequency of SCL you should write the 4 bit prescaler value in the I2CCON register The I2C bus interface address is stored in the I2C bus address I2CADD register By default the I2C bus interface address has an unknown value SAMSUNG ELECTRONICS 14 7 ex 4412 UM 14 Inter Integrated Circuit 14 4 8 Flowcharts of Operations in Each Mode Before you execute any 12C Tx Rx operations
121. 0 FLTEN 17 0 7 RW 0 0 Disables filter 0 1 Enables filter FLTWIDTH17 0 6 0 Filtering width of EXT INT21 0 SAMSUNG ELECTRONICS 4 98 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 117 EXT_INT21_FLTCON1 Base Address 0x1140_0000 e Address Base Address 0x0884 Reset Value 0 0000 0000 Filter Enable for EXT_INT21 7 FLTEN17 7 31 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH17 7 30 24 Filtering width of EXT_INT21 7 Filter Enable for EXT_INT21 6 FLTEN17 6 23 RW 0 0 Disables filter 0 1 Enables filter FLTWIDTH17 6 22 16 Filtering width of EXT_INT21 6 Filter Enable for EXT_INT21 5 FLTEN17 5 15 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH17 5 14 8 Filtering width of EXT INT21 5 Filter Enable for EXT INT21 4 FLTEN17 4 7 RW 0 0 Disables filter 0 1 Enables filter FLTWIDTH17 4 6 0 RW Filtering width of EXT INT21 4 SAMSUNG ELECTRONICS 4 99 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 118 EXT_INT22_FLTCONO Base Address 0x1140_0000 e Address Base Address 0x0888 Reset Value 0x0000_0000 Filter Enable for EXT_INT22 3 FLTEN18 3 31 RW 0 0 Disables filter 0 1 Enables filter FLTWIDTH18 3 30 24 Filtering width of EXT INT22 3 Filter Enable for EXT INT22 2 FLTEN18 2 23 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH18 2
122. 0 0000 0000 0 0 Input 0 1 Output 0 2 Reserved GPXOCON 7 31 28 us z e 0x00 0x5 ALV DBG 3 0x6 to Reserved OxF WAKEUP INTO 7 0 0 Input 0 1 Output 0 2 Reserved GPXOCONI6 27 24 o Leer 0 00 0 5 ALV DBG 2 0 6 to Reserved OxF WAKEUP_INTO 6 0 0 Input 0 1 Output 0 2 Reserved GPX0CON 5 23 20 Ne kwaa 0 00 0 5 ALV DBG 1 0 6 to Reserved OxF WAKEUP_INTO 5 0 0 Input 0 1 Output 0 2 Reserved GPXOCON 4 19 16 a 0 00 0 5 ALV DBG 0 0 6 to Reserved OxF WAKEUP_INTO 4 0 0 Input 0 1 Output 0 2 Reserved GPXOCON 3 15 12 M 22 0 00 0 5 ALV 0 6 to Reserved WAKEUP 0 0 Input GPXOCON 2 11 8 ae 0x00 0x3 AUD TDI SAMSUNG ELECTRONICS 4 252 ex 4412 UM 4 General Purpose Input Output GPIO Control 0x4 GNSS_TDI 0x5 ALV_TDI 0 6 to Reserved OxF WAKEUP INTO 2 0 0 Input 0 1 Output 0x2 Reserved 0x3 AUD_TMS GPXOCON 1 7 4 RW 0 4 GNSS TMS 0 5 ALV TMS 0x6 to OxE Reserved OxF WAKEUP INTO 1 0 0 Input 0 1 Output 0x2 Reserved 0x3 AUD_TCK GPXOCON O 3 0 RW 0 4 GNSS 0 5 ALV 0x6 to OxE Reserved WAKEUP_INTO 0 SAMSUNG ELECTRONICS 4 253 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 195 GPXODAT e Base A
123. 0 m Timer 4 Count Observation register 0x0000 0000 SAMSUNG ELECTRONICS 11 22 ex 4412 UM 11 Pulse Width Modulation Timer 11 5 1 18 TINT CSTAT e Base Address 0x139D_0000 PWM Base Address 0x1216 0000 ISP e Address Base Address 0x0044 Reset Value 0x0000 0000 Reserved Bits 0x00000 2 RSVD Timer 4 interrupt status Timer 4 interrupt status bit It clears by writing 1 on this bit y Timer 3 interrupt status Timer 3 interrupt status bit lt clears by writing 1 on this bit Timer 2 interrupt status Timer 2 interrupt status bit lt clears by writing 1 on this 7 bit Timer 1 interrupt status Timer 1 interrupt status bit lt clears by writing 1 on this bit Timer 0 interrupt status Timer 0 interrupt status bit lt clears by writing 1 on this bit Enables timer 4 interrupt 0 Disables Timer 4 interrupt 0x0 1 Enables Timer 4 interrupt 5 2 2 Timer 4 interrupt 4 enable Enables timer 3 interrupt 0 Disables Timer 3 interrupt 1 Enables Timer 3 interrupt Timer 3 interrupt enable 2 3 Enables timer 2 interrupt 0 Disables Timer 2 interrupt 1 Enables Timer 2 interrupt Timer 2 interrupt enable 2 2 Enables timer 1 interrupt 0 Disables 1 interrupt 1 Enables Timer 1 interrupt Timer 1 interrupt enable 2 Enables timer 0 interrupt
124. 0000 23 16 Reserved Should be zero W GPF2DRVIn n 2 1 2 0x0000 0107 SAMSUNG ELECTRONICS 4 50 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 59 GPF2CONPDN Base Address 0x1140_0000 e Address Base Address 0 0100 Reset Value 0x0000 0x0 Outputs O 2n 1 2n 0x1 Outputs 1 0107 RW 0x2 Input one 0 3 Previous state 4 3 2 60 GPF2PUDPDN Base Address 0x1140 0000 e Address Base Address 0x01D4 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down GPPAN 0107 RW 0x2 Reserved DE 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 51 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 61 GPF3CON e Base Address 0x1140_0000 e Address Base Address 0x01E0 Reset Value 0x0000 0000 0 0 Input 0 1 Output GPF3CON 5 23 20 RW 0x2 SYS_OE 0 00 0x3 to Reserved EXT_INT16 5 0 0 Input 0 1 Output GPF3CONJ 4 19 16 RW 0 2 VSYNC 0 00 0x3 to Reserved EXT INT16 4 0 0 Input 0 1 Output 15 12 RW 0 2 LCD VD 23 0 00 0x3 to Reserved EXT_INT16 3 0 0 Input 0 1 Output GPF3CON 2 11 8 RW 0 2 LCD VD 22 0 00 0x3 to Reserved EXT_INT16 2 0 0 Input 0 1 Output 7 4 RW 0 2 LCD VD 21 0 00 0x3 to
125. 0000 e Address Base Address 0xC920 Reset Value OxFFFF_FFFF Gating all clocks for PIXELASYNCM1 0 Mask 1 Pass Gating all clocks for PIXELASYNCMO 0 Mask 1 Pass Gating all clocks for PPMUCAMIF 0 Mask 1 Reserved Gating all clocks for SMMUJPEG 0 Mask 1 Pass B CLK PIKELASYN CMT 18 PIKELASYN CMO LER CLK PPMUCAMIF 16 CLK SMMUJPEG 11 O O B B Gating all clocks for SMMUFIMC1 0 Mask 1 Pass Gating all clocks for SMMUFIMCO 0 Mask 1 Pass Gating all clocks for JPEG 0 Mask 1 Pass Gating all clocks for CSIS1 0 Mask 1 Pass CLK_CSIS1 CSISO 1 Pass Gating all clocks for FIMC3 CLK_FIMC3 3 0 Mask 1 Pass SAMSUNG ELECTRONICS 5 108 Gating all clocks for CSISO 0 Mask Gating all clocks for SMMUFIMC3 CLK_SMMUFIMC3 10 0 Mask 1 Pass RW RW RW RW RW RW RW RW RW RW RW W 7 5 4 3 Gating all clocks for SMMUFIMC2 0 Mask Ox1 1 Pass a 4412 UM 5 Clock Management Unit Gating all clocks for FIMC2 CLK_FIMC2 0 Mask 1 Pass Gating all clocks for FIMCO CLK FIMCO 0 Mask 1 Pass Gating all clocks for FIMC1 FIMC1 0 Mask Ox1 1 Pass SAMSUNG ELECTRONICS 5 109 IT 4412 UM 5 Clock Management Unit 5 10 1 93 CLK GATE e Base Address 0x1003 0000 e Address Base Address 0xC924 Reset Value OxFFFF_FFFF
126. 0x0 Not occur EXT INT6 PEND 0 0 RWX Oxo 4 3 2 139 EXT_INT7_PEND Base Address 0x1140_0000 e Address Base Address 0x0A18 Reset Value 0x0000 0000 0 0 Not occur EXT INT7 3 RWX 0 1 Interrupt occurs 0 0 EXT INT7 PEND 2 2 RWX 0 0 Not occur 0 1 Interrupt occurs EXT INT7 PEND 1 1 RWX 0x0 Not occur 0 1 Interrupt occurs EXT INT7 PEND 0 RWX 0x0 Not occur 0 1 Interrupt occurs SAMSUNG ELECTRONICS 4 112 x 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 140 EXT_INT13_PEND e Base Address 0x1140_0000 e Address Base Address 0x0A30 Reset Value 0x0000 0000 EXT INT13 PEND 7 7 RWX 0 0 Not occur Ox1 Interrupt occurs EXT INT13 PEND 6 6 RWX 0 0 Not occur 0 1 Interrupt occurs EXT_INT13_PEND 5 5 RWY 0 0 Not occur PP 0x1 Interrupt occurs 0x0 Not occur EXT INT13 PEND 4 4 RWX Ore INT13 3 RWX 0 0 Not occur 0 1 Interrupt EXT INT13 PEND 2 2 RWX 0x0 Not occur 0x1 Interrupt occurs EXT INT13 PEND 1 1 RWX 0x0 Not occur 0 1 Interrupt occurs EXT INT13 PEND 0 RWX 0 0 Not occur 0 1 Interrupt occurs SAMSUNG ELECTRONICS 4 113 II 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 141 EXT_INT14_PEND Base Address 0x1140_0000 e Address Base Address 0x0A34 Reset Value
127. 0x0018 Reset Value Undefined 7 Interrupt Combiner av ______ MFG eo SYSMMU Mo 29 R Interrupt pending status mos MAUWA RD O 0 The interruptis not pending SYSMMU LCDO 26 1 The interruptis pending SYSMMU GPS 1 SYSMMU ROTATOR 1 SYSMMU_2D 1 SYSMMU JPEG 1 SYSMMU_FIMC3 1 21 Interrupt pending status EE Tr SYSMMU_FIMC1 1J I9 R 0 The interrupt is not pending SYSMMU_FIMCO 1 19 1 The interrupt is pending svsmmu sss ___ R SYSVMU fer R vo _______ SvsMMU tal R SYSMMU _ 13 Interrupt pending status RD mf 0 The interrupt is not pending 1 The interrupt is pending nr svewwu E R svsmmu 200 n svewwu JPEG l R SYSMMU FIMC3 0 ey R Interrupt pending status ESC C SYSMMU_FIMCt O 8 R 0 The interrupt is not pending SYSMMU_FIMCO O 21 1 The interrupt is pending svewwusssp mbwai SAMSUNG ELECTRONICS 7 16 Ea NEUEN HEC NR Mach NC HN WE HNE EE Ca EI MN MET KENN E 27 4412 UM 7 Interrupt
128. 0x002C Reset Value 0x0003_FFF2 When ECC Type is 1 bit ECC Indicates whether spare area bit fail error occurred 00 No Error 01 1 bit error correctable 10 Multiple error 11 ECC area error Indicates whether main data area bit fail error occurred 00 No Error 01 1 bit error Correctable 10 Multiple error 11 ECC area error NOTE The above values are valid only when both ECC register and ECC status register have valid value When ECC Type is 4 bit ECC Indicates the 4 bit ECC decoding engine is searching whether a error exists or not 0 Idle 1 Busy MLCECCReady 30 ECC Ready bit MLCFreePage 29 page data read from NAND flash has all 4 bit ECC decoding result 000 No error 001 1 bit error MLCECCError 28 26 de E a 100 4 bit error 101 Uncorrectable 11x Reserved MLCErrLocation2 25 16 Error byte location of 274 bit error SAMSUNG ELECTRONICS 10 25 27 4412 UM 10 NAND Flash Controller ASV sno _ MLCErrLocation1 9 0 Error byte location 1 bit error 0 000 NOTE These values are updated when ECCDecodeDone NFSTAT 6 is set 1 SAMSUNG ELECTRONICS 10 26 ex 4412 UM 10 NAND Flash Controller 10 7 2 13 NFECCERR1 e Base Address OXOCEO 0000 e Address Base Address 0x0030 Reset Value 0x0000 0000 When ECC Type is 4 bit ECC ASVD pag Reewd ow MLCErrLocation4 25 16 Error byt
129. 0x3 nRTS ee 0 00 0 4 to Reserved OxF EXT_INT11 4 0 0 Input 0 1 Output 0 2 CAM GPIO 5 GPM3CON 3 15 12 0x3 MPWM6_OUT_ISP 0 00 0 4 SPI1 MOSI 0 5 to Reserved OxF EXT INT11 3 0 0 Input 0 1 Output 0 2 GPIO 4 GPM3CON 2 11 8 0x3 MPWM5_OUT_ISP 0 00 0 4 CAM_SPI1_MISO 0 5 to Reserved OxF EXT_INT11 2 0 0 Input 0 1 Output 0 2 CAM GPIO 3 GEMSGONDI YA 0 3 MPWM4 OUT ISP 0 4 to Reserved OxF EXT INT11 1 SAMSUNG ELECTRONICS 4 184 27 4412 UM 4 General Purpose Input Output GPIO Control 0 0 Input 0 1 Output 0 2 CAM_GPIO 2 2 0 0 3 MPWM3_OUT_ISP 0 4 to Reserved OxF EXT_INT11 0 SAMSUNG ELECTRONICS 4 185 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 108 GPM3DAT e Base Address 0x1100 0000 e Address Base Address 0x02C4 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPM3DAT 7 0 7 0 output port then pin state should be same as 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 3 109 GPM3PUD Base Address 0x1100 0000 e Address Base Address 0x02C8 Reset Value 0x5555 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down GPM3PUD n 10407 RW 0x2 Re
130. 0x7 Reserved v n mee AT SAMSUNG ELECTRONICS 4 270 ex 4412 UM 4 General Purpose Input Output GPIO Control Sets signaling method of EXT_INT43 2 0 0 Low level 0x1 High level EXT_INT43_CON 2 10 8 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT43 1 0 0 Low level 0x1 High level EXT_INT43_CON 1 6 4 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT43 0 0 0 Low level 0x1 High level EXT INT43 CON 0 2 0 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0 5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 271 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 214 EXT_INT40_FLTCONO Base Address 0x1100 0000 e Address Base Address OxOE80 Reset Value 0x8080_ 8080 Filter Enable for EXT_INT40 3 FLTEN15 3 0 0 Disables Filter 0 1 Enables Filter Filter Selection for EXT INT40 3 FLTSEL15 3 0 0 Delays filter Ox1 Digital filter clock count Filtering width of EXT INT40 3 FLTWIDTH15 3 This value is valid when FLTSEL15 of EXT_INT40 is 0x1 Filter Enable for EXT_INT40 2 FLTEN15 2 0 0 Disables Filter 0x1 Enables Filter Filter Selection for EXT_INT40 2 FLTSEL15 2 0 0 Delays filter 0x1 Digital filte
131. 1 7 4 RW 0 2 2 RXD 1 0 00 0x3 to Reserved OxF EXT_INT30 1 0 0 Input 0 1 Output GPVOCON O 3 0 RW 0 2 C2C_RXDIO 0x3 to OxE Reserved OxF EXT INTSO 0 SAMSUNG ELECTRONICS 4 298 iD 0 0 Input 0 1 Output GPVOCON S 15 12 0 2 C2C_RXDI3 0x00 0x3 to OxE Reserved OxF EXT INTSO 3 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 2 GPVODAT Base Address Ox106E 0000 e Address Base Address 0x0004 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPVODAT 7 0 7 0 output port then pin state should be same as 0x00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 5 3 GPVOPUD Base Address Ox106E 0000 e Address Base Address 0x0008 Reset Value 0x5555 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down GPVOPUDIn n201o7 RW 0x2 Reserved 0x5555 0x3 Enables Pull up 4 3 5 4 GPVODRV Base Address 0x106E_0000 e Address Base Address 0 000 Reset Value 0x00_0000 23 16 Reserved Should be zero W GPVODRVIn n 2n 1 2 0x0000 0107 SAMSUNG ELECTRONICS 4 299 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 5 GPVOCONPDN Base Address Ox106E 0000 e Address Base Address 0x0010 Reset Value 0x0000 0x0 Ou
132. 1 KP_ROW 0 KP_COL 7 KP_COL 6 KP_COL 5 XEINT_13 XGNSS_GPIO_5 KEYPAD interface column 5 data GPX1 B GPL2 5 muxed KEINT 12 XGNSS_GPIO_4 KEYPAD interface column 4 data GPX1 4 GPL2 A muxed KEYPAD interface column 3 data KEINT 11 XGNSS GPIO 3 muxed KP COL 4 KP COL 3 SAMSUNG ELECTRONICS 17 10 4412 UM 17 Keypad Interface XEINT 10 XGNSS GPIO 2 KP COL 2 KEYPAD interface column 2 data GPX1 2 GPL2 2 XEINT 9 XGNSS GPIO 1 KP COL 1 m KEYPAD interface column 1 data GPX1 1 GPL2 1 KEYPAD INTERFACE XEINT 8 XGNSS GPIO 0 KP COL 0 ES COLUMN 0 data GPX1 0 GPL2 0 SAMSUNG ELECTRONICS 17 11 ex 4412 UM 17 Keypad Interface 17 8 Register Description 17 8 1 Register Map Summary Base Address 100 _0000 KEYIFCON 0 0000 Specifies KEYPAD interface control register 0x000F 0000 KEYIFSTSCLR 0 0004 Specifies KEYPAD interrupt for software scan status and 0 0000_0000 clear register KEYIFCOL 0 0008 Specifies interface column output register 0x0000 00 KEYIFROW 0 000 Specifies KEYPAD interface row data input register 0x0010 Specifies KEYPAD interface debouncing filter clock division 0x0000 0000 register KEYIFSCAN1 0 0014 Specifies KEYPAD interface output result of hardware scan 0 0000_0000 for first key register KEYIFSCAN2 0x0018 Specifies KEYPAD interface outpu
133. 1 If required Write own Slave address on I2CADD register 2 Set I2CCON register a Enable interrupt b Define SCL period 3 Set I2CSTAT to enable Serial Output Figure 14 6 illustrates the operations for Master Transmitter mode Master Tx mode has been configured Write slave address to 12CDS Write OxFO M T Start to I2CSTAT The data of the 12205 is transmitted interrupt is pending lt gt N After ACK period transmitted to 12205 to I2CSTAT RENE AM Clear pending bit The data of the 12CDS Wait until the stop is shifted to SDA condition takes effect Write new data Write Ok DO Stop Clear pending bit to resume END Figure 14 6 Operations for Master Transmitter Mode SAMSUNG ELECTRONICS 14 8 II 4412 UM 14 Inter Integrated Circuit Figure 14 7 illustrates the operations for Master Receiver Mode START Master Rx mode has been configured Write slave address to 12CDS Write 0 0 M R Start to I2CSTAT The data of the 12205 Slave address is transmitted After ACK period interrupt is pending Read new data Write 0 90 Stop 12CDS to I2CSTAT Clear pending bit to resume Clear pending bit Wait until the stop SDA is shifted to 12005 condition takes effect END Figure 14 7 Operations for Master Receiver Mode SAMSUNG ELECTRONICS 14 9 ex
134. 10 1 161 CMU_ISP_SPARE3 Base Address 0x1004_0000 Address Base Address 0 8 Reset Value 0x0000 0000 SPARE 31 0 CMU_ISP Spare Register x 1 SAMSUNG ELECTRONICS 5 162 4412 UM 6 Interrupt Controller Interrupt Controller 6 1 Overview Generic Interrupt Controller GIC is a centralized resource that supports and manages interrupts in a system GIC provides e Registers for managing interrupt sources interrupt behavior and interrupt routing to one or multiple processors e Support for The ARM architecture Security Extensions Enabling disabling and generating processor interrupts from hardware peripheral interrupt sources Generating software interrupts Interrupt masking and prioritization GIC takes the interrupts asserted at the system level and sends appropriate signals to each connected processor When GIC implements the Security Extensions it can implement two interrupt requests to a connected processor The architecture identifies these requests as IRQ and FIQ SAMSUNG ELECTRONICS 6 1 ex 4412 UM 6 2 Features The features of GIC are e Supports three interrupt types e Programmable interrupts that enable you to set the Software Generated Interrupt SGI Private Peripheral Interrupt PPI Shared Peripheral Interrupt Security state for an interrupt Priority level of an interrupt Enabling or disabling of an interrupt Processors that
135. 100 Reserved 101 Reserved 110 Reserved 111 Reserved Rx DMA Burst Size It is the data transfer size of one DMA transaction Rx DMA request triggers the DMA transaction You must program the DMA program to transfer the same data size as this is the value for a single Rx DMA request 000 1 byte Single Ax DMA Burst 48 16 RW 001 4 bytes 010 8 bytes 011 16 bytes 100 Reserved 101 Reserved 110 Reserved 111 Reserved Rx Timeout Interrupt Interval Rx Timeout Rx interrupt occurs if UART receives no data during 8 x N Interrupt 15 12 RW 1 frame time Interval The default value of this field is 3 It means that the timeout interval is 32 frame time Rx Time out Enables Rx time out feature when Rx FIFO counter is 0 with empty Rx 11 R W This bit is valid only when UCONn 7 is 1 FIFO 4 0 Disables Rx time out feature when Rx FIFO is empty SAMSUNG ELECTRONICS 13 14 4412 UM Time out DMA suspend 10 enable 9 8 7 6 5 4 Tx Interrupt Type Rx Time Out Enable Rx Error Status Interrupt Enable Loop back Mode Send Break Signal Transmit Mode 3 2 SAMSUNG ELECTRONICS Rx Interrupt Type AN RW RW RW RW RW WX RW RW 13 Universal Asynchronous Receiver and Transmitter 1 Enables Rx time out feature when Rx FIFO is empty Enables the suspension of FSM when Rx Time out occurs 0 Disables suspen
136. 104 GPM2DRV e Base Address 0x1100_0000 e Address Base Address 0x02AC Reset Value 0x00_0000 23 16 Reserved Should be zero W GPM2DRV n n 2n 1 21 0x0000 0104 SAMSUNG ELECTRONICS 4 182 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 105 GPM2CONPDN Base Address 0x1100 0000 e Address Base Address 0 02 0 Reset Value 0x0000 0 0 Outputs 0 2n 1 21 0 1 Outputs 1 n 0t04 FW o Input 999 0 3 Previous state 4 3 3 106 GPM2PUDPDN Base Address 0x1100_0000 e Address Base Address 0x02B4 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down 0104 zi 0x2 Reserved 990 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 183 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 107 GPM3CON e Base Address 0x1100 0000 e Address Base Address 0x02C0 Reset Value 0 0000 0000 0 0 Input 0 1 Output 0 2 CAM_GPIO 9 GPM3CON 7 31 28 0x3 1 0 00 0 4 to Reserved OxF EXT_INT11 7 0 0 Input 0 1 Output 0 2 CAM_GPIO 8 GPM3CON 6 27 24 0x3 nCTS je 0 00 0 4 to Reserved EXT INT11 6 0 0 Input 0 1 Output 0 2 CAM GPIO 7 GPM3CON 5 23 20 0x3 TXD een ls 0 00 0 4 to Reserved OxF EXT_INT11 5 0 0 Input 0 1 Output 0 2 CAM_GPIO 6 GPM3CON 4 19 16
137. 16 4 Memory Format of 25 BPP A888 Display NOTE 1 Specifies the transparency value selection bit AEN 0 Selects ALPHAO AEN 1 Selects ALPHA1 When it sets per pixel blending then this pixel blends with alpha value that AEN selects SFR selects the alpha value as ALPHAO_R ALPHAO_G ALPHAO_B ALPHA1_R ALPHA1_G and ALPHA1_B For more information refer to the section on SFR 2 D 23 16 Red data D 15 8 Green data and D 7 0 Blue data SAMSUNG ELECTRONICS 16 8 III 4412 UM 16 Display Controller 16 3 3 2 1 32BPP 8888 Mode Figure 16 5 illustrates the pixel data that contains alpha value BYSWP 0 HWSWP 0 WSWP 0 D 63 56 31 24 ALPHA value ALPHA value ALPHA value ALPHA value ALPHA value ALPHA value HWSWP 0 WSWP 1 D 63 56 D 55 32 D 31 24 D 23 0 ALPHA value P2 ALPHA value P1 ALPHA value P4 ALPHA value P3 ALPHA value P6 ALPHA value P5 Figure 16 5 Memory Format of 32 BPP 8888 Display SAMSUNG ELECTRONICS 16 9 ex 4412 UM 16 Display Controller 16 3 3 2 2 24 BPP Display A887 Figure 16 6 illustrates the 24 BPP display BSWP 0 HWSWP 0 WSWP 0 D 63 56 D 55 D 54 32 D 31 24 D 22 0 000H Dummy Bit AEN P1 Dummy Bit P2 008H Dummy Bit AEN P3 Dummy Bit P4 010H Dummy Bit AEN P5 Dummy Bit P6 BSWP 0 HWSWP 0 WSWP 1 D 63 56
138. 18 BPP non palletized R 6 G 6 B 6 1001 Unpacked 18 BPP non palletized A 1 R 6 G 6 B 5 1010 Unpacked 19 BPP non palletized A 1 R 6 G 6 BPPMODE_F 5 2 B 6 1011 Unpacked 24 non palletized R 8 G 8 B 8 1100 Unpacked 24 BPP non palletized A 1 R 8 G 8 B 7 1101 Unpacked 25 BPP non palletized A 1 R 8 G 8 B 8 1110 Unpacked 13 BPP non palletized A 1 R 4 G 4 B 4 1111 Unpacked 15 BPP non palletized R 5 G 5 B 5 NOTE 1 1101 Supports unpacked 32 BPP non palletized A 8 R 8 G 8 B 8 for per pixel blending 2 1110 Supports 16 non palletized A 4 R 4 G 4 B 4 for per pixel blending 16 level blending Selects Alpha value When per plane blending case BLD PIX 0 Using ALPHAO R G B values 1 Using ALPHA1 R G B values ALPHA SEL F When per pixel blending BLD PIX 1 0 Selected by AEN A value 1 Using DATA 31 24 data in word boundary only when BPPMODE F 4 b1101 DATA 31 28 15 12 data in word boundary only when BPPMODE F 461110 Enables disables video output and logic immediately ENWIN F 0 Disables the video output and video control signal 1 Enables the video output and video control signal SAMSUNG ELECTRONICS 16 71 4412 UM 16 Display Controller 16 5 3 11 WINCON2 e Base Address 0x11C0_0000 e Address Base Address 0x0028 Reset Value 0x0000 0000 Specifies Buffer Status Read only 00 Buffer to 0 BUFSTATUS_H 31
139. 2 Filter Enable for EXT INT10 1 FLTEN12 1 15 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH12 1 14 8 Filtering width of EXT INT10 1 Filter Enable for EXT INT10 0 FLTEN12 0 7 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH12 0 6 0 RW Filtering width of EXT_INT10 0 4 3 3 150 EXT_INT10_FLTCON1 Base Address 0x1100 0000 e Address Base Address 0x085C Reset Value 0x0000 0000 Filter Enable for EXT INT10 4 FLTEN12 4 7 RW Disables Filter 0x1 Enables Filter FLTWIDTH12 4 6 0 RW Filtering width of EXT_INT10 4 SAMSUNG ELECTRONICS 4 225 ITU 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 151 EXT_INT11_FLTCONO e Base Address 0x1100 0000 e Address Base Address 0x0860 Reset Value 0x0000_0000 Filter Enable for EXT_INT11 3 FLTEN13 3 31 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH13 3 30 24 Filtering width of EXT INT11 3 Filter Enable for EXT_INT11 2 FLTEN13 2 23 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH13 2 22 16 Filtering width of EXT INT11 2 Filter Enable for EXT INT11 1 FLTEN13 1 15 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH13 1 14 8 Filtering width of EXT INT11 1 Filter Enable for EXT INT11 0 FLTEN13 0 7 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH13 0 6 0 RW Filtering width of EXT INT11 0 SAMSUNG
140. 200 SEL 14 12 21 1 Status that the is changing RSV mi sone o Selection signal status of MUXVPLL 1 FINVPLL 6 FOUTVPLL 1 Status that the is changing Selection signal status of MUXEPLL 001 FINPLL EPLL_SEL 4 S 6 4 010 FOUTEPLL 1 Status that the mux is changing Selection signal status of MUKONENAND 1 ONENAND_1_SEL 2 0 001 MOUTONENAND 010 SCLKVPLL SAMSUNG ELECTRONICS 5 79 ex 4412 UM 5 Clock Management Unit Eee Status that the muxis changing 7 77 SAMSUNG ELECTRONICS 5 80 ex 4412 UM 5 Clock Management Unit 5 10 1 47 CLK_MUX_STAT_TOP1 e Base Address 0x1003 0000 e Address Base Address 0xC414 Reset Value 0 0111_1110 RSVD eee Selection signal status of MUKACLK 400 MCUISP ACLK 400 MCUISP 26 24 001 FINPLL _SUB_SEL 010 FOUTPOST_ACLK_400_MCUISP 1 Status that the is changing SE Gp ea MIN Selection signal status of 200 200 SUB 22 20 001 FINPLL SEL 010 FOUTPOST ACLK 200 1 Status that the is changing SE me 9 Selection signal status of MUXACLK 266 GPS ACLK 266 GPS 18 16 001 FINPLL _SUB_SEL 010 FOUTPOST ACLK 266 GPS 1 Status that the is changing SE eee 9 Selection signal status of MUXMPLL MPLL USER SEL T 14 12 M z Di 1 Status that the is changin
141. 24 5 10 1 Register Map SUMMA Y ion daa 5 26 6 INTERRUPT CONTROLLER 6 1 mST 6 1 WA ee Em 6 2 6 2 1 Security Extensions Support 6 2 6 2 2 Implementation Specific Configurable Features 6 3 6 3 Interrupt SOUICO ru ese be 6 4 6 3 1 Interrupt Sources 6 4 6 92 GIC Interrupt Tables 6 5 6 4 Functional Overview 6 13 6 5 Register Description m 6 14 6 5 1 Register Map 6 14 7 INTERRUPT COMBINER 7 1 ANO u m u uu 7 1 7 1 4 9 Functional a 7 2 FS 5 7 2 TA nterrupt SOUr6eSu uuu L 7 3 7 3 7 5 Functional Deserte E T 7 8 7 6 Register uuu u 7 9 7 6 1 Register Map 7 9 7 6 2 Interrupt COMDING aka 7 10 8 DIRECT MEMORY ACCESS CONTROLLER 8 1 O ER 8 1 8 2 POMO cia
142. 27 24 7 WxPAL 111 Ri DATA 31 24 Y Ap N 7 BLEN NEW ALPHA 0 BPPMODE Palette ALPHA 1 Ap BLEN_NEW 1 Ap 7 4 Ap 7 4 App Only valid BLD_PIX 1 amp amp ALPHA SEL 1 amp amp BPPMODE 11010r 1110 ALPHA MUL N Y App App ALPHAD LALPHAD T 4 ALPHAQ 7 4 Transparency factor Figure 16 28 SAMSUNG ELECTRONICS Stat Fr KEY EN Color match a A_FUNC ev BUEN ERE b B FUNC N a alpha b 1 alphaA Data Data Formatter Formatter Transparency Transparency Factor Factor Eguation Decision Decision Decision LLL IT alphaA Blending amp Chroma keying alphaB Blending Decision Diagram 16 34 4412 UM 16 Display Controller 16 3 6 VTIME Controller Operation VTIME comprises of two blocks namely e VTIME RGB TV for RGB timing control e VTIME 180 for indirect i80 interface timing control 16 3 6 1 RGB Interface Controller VTIME generates control signals such as RGB VSYNG RGB HSYNC RGB VDEN and RGB signal for the RGB interface You can use these control signals while configuring the VIDTCONO 1 2 registers in the VSFR register You can program configurations of display control registers in the VSFR
143. 2n 1 2n 0x1 Enables Pull down GPMA4PUD n 80407 RW 0x2 Reserved 0x5555 0x3 Enables Pull up 4 3 3 116 GPM4DRV e Base Address 0x1100_0000 e Address Base Address 0x02EC Reset Value 0x00_0000 23 16 Reserved Should be zero W GPM4DRV n n 2n 1 21 0x0000 0107 SAMSUNG ELECTRONICS 4 190 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 117 GPM4CONPDN Base Address 0x1100 0000 e Address Base Address 0 02 0 Reset Value 0x0000 0 0 Outputs 0 2n 1 21 0 1 Outputs 1 AMAIA 0107 0 2 Input 999 0 3 Previous state 4 3 3 118 GPM4PUDPDN e Base Address 0x1100_0000 e Address Base Address 0x02F4 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down 0107 zi 0x2 Reserved 990 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 191 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 119 EXT_INT23CON e Base Address 0x1100 0000 e Address Base Address 0x0708 Reset Value 0x0000 0000 Gus o ms nes fo Sets signaling method of EXT INT23 6 0 0 Low level 0 1 High level EXT INT23 CON 6 26 24 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved 85 9 gp eee pf 0 Sets signaling method of EXT_INT23 5 0 0 Low level 0x1 High level EXT_IN
144. 3 14 12 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved ASV mi Sets signaling method of EXT_INT25 2 0 0 Low level 0x1 High level EXT_INT25_CON 2 10 8 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 196 ex 4412 UM 4 General Purpose Input Output GPIO Control signaling method of EXT_INT25 1 0x0 Low level 0x1 High level EXT_INT25_CON 1 6 4 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0x5 to 0x7 Reserved CO pm Sets signaling method of EXT_INT25 0 0x0 Low level 0x1 High level EXT_INT25_CON 0 2 0 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0x5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 197 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 122 EXT_INT26CON e Base Address 0x1100 0000 e Address Base Address 0x0714 Reset Value 0x0000 0000 Gus ms Sets signaling method of EXT_INT26 6 0x0 Low level 0x1 High level EXT_INT26_CON 6 26 24 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0 7 Reserved 85 9 eee pf 0 Sets signaling method of EXT_INT26 5 0 0 Low level 0x1 High level E
145. 32 VIDOSD4C e Base Address 0x11C0_0000 e Address Base Address 0x0088 Reset Value 0x0000_0000 Twe Desoription Reset Value Re f lasema 23 20 Specifies the Red Alpha upper value case 0 19 16 Specifies the Green Alpha upper value case 0 15 12 Specifies the Blue Alpha upper value case 0 Specifies the Red Alpha upper value case 1 o _ Specifies the Green Alpha upper value case 1 p HE HE ALPHA 3 0 Specifies the Blue Alpha upper value case AEN 1 NOTE For more information Refer to 16 5 3 78 VIDW4ALPHAO 16 5 3 79 VIDWAALPHA 1 register SAMSUNG ELECTRONICS 16 91 ex 4412 UM 16 Display Controller 16 5 3 33 VIDWOn 00 to 04 ADDOBn n 0 to 2 Base Address 0x11C0_0000 e Address Base Address 0x00A0 Reset Value 0x0000_0000 VIDWOOADDOBO e Address Base Address 0x00A4 Reset Value 0x0000_0000 VIDWOOADDOB1 e Address Base Address 0x20A0 Reset Value 0x0000_0000 VIDWOOADDOB2 e Address Base Address 0x00A8 Reset Value 0x0000 0000 VIDW01ADDOBO e Address Base Address Reset Value 0x0000 0000 VIDWO1ADDOB1 e Address Base Address 0x20A8 Reset Value 0x0000 0000 VIDW01ADDOB2 e Address Base Address Reset Value 0x0000 0000 VIDWO2ADDOBO e Address Base Address 0x00B4 Reset Value 0x0000 0000 VIDWO2A
146. 4412 UM DMAO 8 Direct Memory Access Controller DMAC 12505 TK frem 3 3 facecm Am mm s Jsmsusem mm Jsmsso s Jsmsusom s sei s s sn s wis 4 wis mm SAMSUNG ELECTRONICS T IT 4412 UM 8 Direct Memory Access Controller DMAC Caution When you enable PDMA1 verify the CLKGATE status SAMSUNG ELECTRONICS 4412 UM 8 Direct Memory Access Controller DMAC 8 3 Register Description Most of the Special Function Registers SFRs are read only The role of SFR 1 to verify the PL330 status There are many SFRs for PL330 This section describes only the Exynos 4412 specific SFRs Refer to Chapter 3 PL330 TRM for more information 8 3 1 Register Map Summary Base Address 0x1284 0000 MDMA S 0 0000 Specifies the status register Refer to 3 11 of 0x200 PL330 for more information E e orm moa mama eT Specifies the interrupt status register Refer to page 3 16 of OS 06828 PL330 for more information Specifies the interrupt clear register Refer to page 3 17 of INTGER UKOO PL330 TRM for more information 0x9 Specifies the fault status DMA manager register Refer to 3 18 of PL330 for information 0x9 Specifies the
147. 5 10 1 40 CLK SRC MASK LCD e Base Address 0x1003 0000 e Address Base Address 0xC334 Reset Value 0x0000 1111 Mask output clock of MUKMIPIO MIPIO MASK 12 RW 0 Mask 0 1 1 Unmask SE ma fo PWMO M Mask output clock of MUXMDNIE_PWMO RW 0 Mask 1 Unmask SE mq ne fo Mask output clock of MUXMDNIEO MDNIEO MASK 4 RW 0 Mask 1 Unmask SE ne fo Mask output clock of MUXFIMDO FIMDO MASK RW 0 Mask 1 Unmask SAMSUNG ELECTRONICS 5 74 ex 4412 UM 5 Clock Management Unit 5 10 1 41 CLK SRC MASK ISP e Base Address 0x1003 0000 e Address Base Address 0xC338 Reset Value 0x0000_1111 RSV eee Mask output clock of MUXUART_ISP UART_ISP_MASK 12 RW 0 Mask 1 Unmask SE ma 99 Mask output clock of MUXSPI1 ISP SPI1 ISP MASK RW 0 Mask 1 Unmask SE mq ECT Mask output clock of MUXSPIO ISP SPIO ISP MASK 4 RW 0 Mask 1 Unmask SE AC Mask output clock of MUXPWM_ISP PWM_ISP_MASK RW 0 Mask 1 Unmask 5 10 1 42 CLK SRC MASK MAUDIO e Base Address 0 1003 0000 e Address Base Address 0xC33C Reset Value 0x0000 0001 RSVD 31 1 Reserved Mask output clock of MUXAUDIOO AUDIOO_MASK RW 0 Mask 0 1 1 Unmask SAMSUNG ELECTRONICS 5 75 ex 4412 UM 5 Clock Management Unit 5 10 1 43 CLK SRC MASK FSYS e Base Address 0x1003 0000
148. 5 us NOTE This A D converter was designed to operate at maximum 5MHz clock so the conversion rate can go up to 1MSPS 18 3 4 ADC Conversion Mode The operation of this mode is same as AINO to AIN3 s To initialize this mode set the ADCCON ADC control register The converted data can be read out from ADCDAT ADC conversion data register SAMSUNG ELECTRONICS 18 2 ex 4412 UM 18 ADC 18 3 5 Standby Mode Standby mode is activated when TSSEL bit is 0 and STANDBY bit is 1 in TSADCCONO register In this mode A D conversion operation is halted and TSDATXn registers hold their values 18 3 5 1 Programming Notes 1 The A D converted data can be accessed by means of interrupt or polling method With interrupt method the overall conversion time from A D converter start to converted data read may be delayed because of the return time of interrupt service routine and data access time With polling method to determine the read time for ADCDATXn register check the ADCCONn 15 end of conversion flag bit 2 A D conversion can be activated in different way After ADCCONn 1 A D conversion start by read mode is set to 1 A D conversion starts simultaneously when converted data is read SAMSUNG ELECTRONICS 18 3 ex 4412 UM 18 ADC 18 4 ADC Input Clock Diagram ADC 8 Touch Screen Interface gt FILCLK FILCLKsrc ADCCLK TSADCCONn 13 6 Figure 18 4 Input Clock Diagram for ADC amp Touch Screen
149. 6 5 Base Address 0x1140 0000 e Address Base Address 0x0914 Reset Value 0 0000 000F 0 0 Enables interrupt EXT INT6 MASK 3 3 0 1 Masked 0 1 0 0 Enables interrupt EKT 6 MASK 2 2 0 1 Masked 0 1 0 0 Enables interrupt 0 0 Enables interrupt 4 3 2 126 EXT_INT7_MASK e Base Address 0x1140_0000 e Address Base Address 0x0918 Reset Value 0x0000 000F 0 0 Enables interrupt EXT INT7 MASK 3 3 0 1 Masked 0x1 0x0 Enables interrupt EXT_INT7_MASK 2 2 0x1 Masked 0 1 0 0 Enables interrupt 0 0 Enables interrupt SAMSUNG ELECTRONICS 4 104 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 127 EXT_INT13_MASK e Base Address 0x1140_0000 e Address Base Address 0x0930 Reset Value 0x0000_00FF 0 0 Enables interrupt EXT INT13 MASK 7 7 0 1 Masked 0 1 0 0 Enables interrupt EXT INT13 MASK 6 6 0 1 Masked 0 1 0 0 Enables interrupt EXT INT13 MASK 5 5 0 1 Masked 0 1 EXT_INT13_MASK 4 4 EXT INT13 MASK 3 3 EXT INT13 2 2 EXT MASK 1 EXT_INT13_MASK 0 HESS SAMSUNG ELECTRONICS 4 105 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 128 EXT_INT14_MASK Base Address 0x1140_0000 e Address Base Address 0x0934 Reset Value 0x0000_00FF 0 0 Enables interrupt EXT INT14 MASK 7 7 0 1 Masked 0 1 0 0
150. 7 0 00 0x3 to Reserved 0 0 Input 0 1 Output GPYSCON 6 27 24 RW 0 2 ADDR 6 0 00 0x3 to Reserved 0 0 Input 0 1 Output GPY3CON 5 23 20 0 2 5 0 00 0x3 to OxE Reserved OxF 0 0 Input 0 1 Output GPY3CON 4 19 16 0 2 EBI ADDR 4 0x00 0x3 to OxE Reserved OxF 0 0 Input 0 1 Output GPYSCON S 15 12 0 2 ADDR 3 0x00 0x3 to OxE Reserved OxF 0 0 Input 0 1 Output GPY3CON 2 11 8 0 2 ADDR 2 0 00 0x3 to Reserved 0 0 Input 0 1 Output GPYSCON 1 7 4 0 2 ADDR 1 0x00 0x3 to OxE Reserved OxF 0 0 Input 0 1 Output GPY3CON 0 3 0 0 2 ADDR 0 0x3 to Reserved OxF SAMSUNG ELECTRONICS 4 157 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 62 GPY3DAT e Base Address 0x1100 0000 e Address Base Address 0x0184 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPY3DAT 7 0 7 0 output port the pin state should be same as the 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 3 63 GPY3PUD e Base Address 0x1100 0000 e Address Base Address 0x0188 Reset Value 0x5555 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pul
151. ALPHAO 15 12 Specifies the Blue Alpha upper value case 0 0 16 5 3 30 VIDOSD4A e Base Address 0x11C0_0000 e Address Base Address 0x0080 Reset Value 0x0000_0000 OSD LeftTopX F 21 11 RW Specifies the Horizontal screen coordinate for left top pixel of OSD image W Specifies the Vertical screen coordinate for left top pixel of OSD image OSD LeftTopY F 10 0 R For interlace TV output this value should be set to half of the original screen y coordinate The original screen y coordinate should be even value SAMSUNG ELECTRONICS 16 90 ex 4412 UM 16 Display Controller 16 5 3 31 VIDOSD4B e Base Address 0x11C0_0000 e Address Base Address 0x0084 Reset Value 0x0000_0000 OSD_RigntBoDX F F F 21 11 Specifies Horizontal screen coordinate for right bottom pixel of OSD image Specifies Vertical screen coordinate for right bottom pixel of OSD image OSD_RightBotY_F 10 0 For interlace TV output this value should be set to half of the original screen y coordinate The original screen coordinate should be odd value NOTE Registers should have word boundary X position Therefore 24 BPP mode should have X position by1 pixel For example 0 1 2 3 16 BPP mode should have X position by 2 pixel For example X 0 2 4 6 8 BPP mode should have X position by 4 pixel For example 0 4 8 12 16 5 3
152. Address 0x0708 Reset Value 0x0000 0000 RSV ey Sets signaling method of EXT_INT32 7 0 0 Low level 0x1 High level EXT INT32 CON 7 30 28 RW 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0x5 to 0x7 Reserved 85 2 ea o Sets signaling method of EXT_INT32 6 0 0 Low level 0x1 High level EXT INT32 CON 6 26 24 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved SVO fo Sets signaling method of EXT_INT32 5 0x0 Low level 0 1 High level EXT INT32 CON 5 22 20 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0 5 to 0x7 Reserved 85 0 AA Sets signaling method of EXT_INT32 4 0 0 Low level 0x1 High level EXT_INT32_CON 4 18 16 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved 85 9 mw Sets signaling method of EXT INT32 3 0 0 Low level 0 1 High level EXT INT32 CON 3 14 12 RW 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0 7 Reserved mw na SAMSUNG ELECTRONICS 4 318 ex 4412 UM 4 General Purpose Input Output GPIO Control Sets the signaling method of EXT_INT32 2 0 0 Low level 0x1 High level EXT_INT32_CON 2 10 8 RW 0x2
153. Address Base Address 0x0820 Reset Value 0x0000 0000 Filter Enable for EXT INT25 3 FLTEN5 3 31 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH5 3 30 24 Filtering width of EXT INT25 3 Filter Enable for EXT INT25 2 FLTEN5 2 23 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH5 2 22 16 Filtering width of EXT_INT25 2 Filter Enable for EXT_INT25 1 FLTEN5 1 15 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTHS 1 14 8 Filtering width of EXT INT25 1 Filter Enable for EXT INT25 0 FLTEN5 0 7 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH5 0 6 0 RW Filtering width of EXT INT25 0 4 3 3 136 EXT INT25 1 e Base Address 0x1100 0000 e Address Base Address 0x0824 Reset Value 0x0000 0000 RSV Filter Enable for EXT INT25 6 FLTEN5 6 23 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH5 6 22 16 Filtering width of EXT INT25 6 Filter Enable for EXT INT25 5 FLTEN5 5 15 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH5 5 14 8 Filtering width of EXT_INT25 5 Filter Enable for EXT INT25 4 FLTEN5 4 7 RW 0x0 Disables Filter 0x1 Enables Filter FLTWiDTHs 4 6 0 RW Filtering width of EXT_INT25 4 SAMSUNG ELECTRONICS 4 216 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 137 EXT_INT26_FLTCONO e Base Address 0x1100 0000 e Address
154. Address 0x1140_0000 e Address Base Address 0x0250 Reset Value 0x0000 0x0 Outputs O 2n 1 2n 0x1 Outputs 1 0107 RW 0x2 Input 0 3 Previous state 4 3 2 74 GPJOPUDPDN Base Address 0x1140_0000 e Address Base Address 0x0254 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down 0107 RW 0x2 Reserved DE 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 57 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 75 GPJ1CON e Base Address 0x1140_0000 e Address Base Address 0x0260 Reset Value 0x0000_0000 0 0 Input 0 1 Output GPJ1CON 4 19 16 0 2 CAM A FIELD 0x00 0x3 to OxE Reserved OxF EXT INT22 4 0x0 Input 0 1 Output GPJ1CON 3 15 12 0 2 CAM A CLKOUT 0x00 0x3 to OxE Reserved OxF EXT INT22 3 0 0 Input 0 1 Output GPJ1CON 2 11 8 0 2 CAM DATA 7 0 00 0x3 to Reserved OxF EXT_INT22 2 0 0 Input 0 1 Output GPJ1CON 1 7 4 0 2 DATA 6 0 00 0x3 to Reserved OxF EXT_INT22 1 0 0 Input 0 1 Output GPJ1CONI 0 3 0 0 2 DATA 5 0 00 0x3 to Reserved OxF EXT INT22 0 SAMSUNG ELECTRONICS 4 58 ITU 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 76 GPJ1DAT Base Address 0x1140_0000 e Address Base Address 0x0264 Reset Value 0 00 RWX When you config
155. D 55 D 54 32 D 31 24 D 22 0 000H Dummy Bit AEN P2 Dummy Bit P1 008H Dummy Bit AEN P4 Dummy Bit P3 010H Dummy Bit AEN P6 Dummy Bit P5 LCD Panel Figure 16 6 Memory Format of 24 BPP A887 Display NOTE 1 Specifies the transparency value selection bit 0 Selects ALPHAO 1 Selects ALPHA1 When it sets per pixel blending then this pixel blends with alpha value that selects SFR selects the alpha value as ALPHAO ALPHAO ALPHAO_B ALPHA1_R ALPHA1_G and ALPHA1 For more information refer to the section on SFR 2 D 22 15 Red data D 14 7 Green data and D 6 0 Blue data SAMSUNG ELECTRONICS 16 10 II 4412 UM 16 Display Controller 16 3 3 2 3 24 BPP Display 888 Figure 16 7 illustrates the 24 BPP display BSWP 0 HWSWP 0 WSWP 0 D 63 56 D 55 32 D 31 24 D 23 0 000H Dummy Bit P1 Dummy Bit P2 008H Dummy Bit P3 Dummy Bit P4 010H Dummy Bit P5 Dummy Bit P6 BSWP 0 HWSWP 0 WSWP 1 D 63 56 D 55 32 D 31 24 D 23 0 000H Dummy Bit P2 Dummy Bit P1 008H Dummy Bit P4 Dummy Bit P3 010H Dummy Bit P6 Dummy Bit P5 P1 P2 LCD Panel Figure 16 7 Memory Format of 24 888 Display NOTE D 23 16 Red data D 15 8 Green data and D 7 0 Blue data SAMSUNG ELECTRONICS 16 11 ex 4412 UM
156. D 63 50 D 49 32 D 31 18 D 17 0 000H Dummy Bit P2 Dummy Bit P1 008H Dummy Bit P4 Dummy Bit P3 010H Dummy Bit P6 Dummy Bit P5 LCD Panel Figure 16 9 Memory Format of 18 BPP 666 Display NOTE D 17 12 Red data D 11 6 Green data and D 5 0 Blue data SAMSUNG ELECTRONICS 16 13 ex 4412 UM 16 Display Controller 16 3 3 2 6 16 BPP Display A555 Figure 16 10 illustrates the 16 BPP display BSWP 0 HWSWP 0 WSWP 0 01631 D 62 48 D 46 32 D 30 16 D 14 0 000H AEN1 P1 P2 P3 P4 004H AEN5 P5 P6 P7 P8 008H AEN9 P9 BSWP 0 HWSWP 0 WSWP 1 D 63 D 62 48 D 46 32 D 30 16 D 14 0 000H 1 2 004H AEN7 7 P8 P5 P6 008H AEN11 P9 BSWP 0 HWSWP 1 WSWP 0 0163 D 62 48 D 46 32 D 30 16 D 14 0 000H AEN4 2 1 004H AEN8 P8 7 P6 P5 008H AEN12 P9 Figure 16 10 Memory Format of 16 BPP A555 Display NOTE 1 AEN Specifies the transparency value selection bit AEN 0 Selects ALPHAO AEN 1 Selects ALPHA When it sets per pixel blending then this pixel blends with alpha value that AEN selects SFR selects the alpha value as ALPHAO R ALPHAO G ALPHAO B ALPHA1 R ALPHA1 G and ALPHA1 B For more information refer to the section on SFR 2 D 14 10 Red data D 9 5 Green
157. DIVCAMO Status DIV_CAMO 16 0 Stable 1 Status that the divider is changing SE mes 9 DIVFIMC3 Status DIV FIMC3 LCLK 12 0 Stable 1 Status that the divider is changing E ma mew fe DIVFIMC2 LCLK Status DIV FIMC2 LCLK 0 Stable 1 Status that the divider is changing ASV ov DIVFIMC1_LCLK Status DIV_FIMC1_LCLK 4 0 Stable 1 Status that the divider is changing 85 0 E DIVFIMCO Status DIV FIMCO LCLK 0 Stable 1 Status that the divider is changing SAMSUNG ELECTRONICS 5 95 ex 4412 UM 5 Clock Management Unit 5 10 1 73 CLK DIV STAT TV e Base Address 0x1003 0000 e Address Base Address 0xC624 Reset Value 0 0000 0000 EN DIVTV BLK Status DIV TV BLK 0 Stable 0 0 1 Status that the divider is changing 5 10 1 74 CLK_DIV_STAT_MFC B Base Address 0x1003_0000 e Address Base Address 0xC628 Reset Value 0x0000_0000 RSV Ex DIVMFC Status DIV MFC 0 Stable 0 0 1 Status that the divider is changing 5 10 1 75 CLK_DIV_STAT_G3D Base Address 0x1003 0000 e Address Base Address 0xC62C Reset Value 0x0000_0000 RVD ar REM DIVG3D Status DIV G3D 0 Stable 0 0 1 Status that the divider is changing SAMSUNG ELECTRONICS 5 96 ex 4412 UM 5 Clock Management Unit 5 10 1 76 CLK DIV STAT LCD e Base Address 0 1003 0000 e Address Base Addre
158. DMA and some logics DMA_peri consists of two PL330s DMAO and DMA1 and dma_map Figure 8 1 illustrates the two DMA tops IRQ to IRQ to i ll i ll IRQ to er interrupt controller DMA_peri DMA_mem PL330 BREQQ 31 0 CLRO 31 0 BREQ 31 0 dma map only wires and OR gates 5 vv v REQ from IPs ACK to IPs Figure 8 1 Two Tops The attributes that the DMA_mem DMA Controllers have mem accesses memory through the AXI IMGX bus and is located in IMG block e mem supports only the secured AXI transaction SAMSUNG ELECTRONICS 8 1 ex 4412 UM 8 Direct Memory Access Controller DMAC 8 2 Features Table 8 1 describes the features of DMA Controller Refer to this table for DMA and for writing DMA assembly code Table 8 1 Features of DMA Controller Supports data size Up to double word 64 bit Up to word 32 bit Supports burst size Upto 16 burst Up to 16 burst Supports channel 8 channels at the same time 16 channels at the same time Each DMA module has 32 interrupt sources However you should send only one interrupt to Interrupt Controller Table 8 2 describes the DMA request mapping Table 8 2 Request Mapping Table Reserved Peri DMA1 9 ROR SAMSUNG ELECTRONICS g IU
159. ELECTRONICS 4 226 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 152 EXT_INT11_FLTCON1 Base Address 0x1100 0000 e Address Base Address 0x0864 Reset Value 0x0000_0000 Filter Enable For EXT_INT11 7 FLTEN13 7 31 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH13 7 30 24 Filtering width of EXT_INT11 7 Filter Enable for EXT_INT11 6 FLTEN13 6 23 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH13 6 22 16 Filtering width of EXT INT11 6 Filter Enable for EXT INT11 5 FLTEN13 5 15 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH13 5 14 8 Filtering width of EXT INT11 5 Filter Enable for EXT INT11 4 FLTEN13 4 7 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH13 4 6 0 RW Filtering width of EXT INT11 4 SAMSUNG ELECTRONICS 4 227 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 153 EXT_INT12_FLTCONO Base Address 0x1100 0000 e Address Base Address 0x0868 Reset Value 0x0000_0000 Filter Enable for EXT_INT12 3 FLTEN14 3 31 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH14 3 30 24 Filtering width of EXT_INT12 3 Filter Enable for EXT_INT12 2 FLTEN14 2 23 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH14 2 22 16 Filtering width of INT12 2 Filter Enable for EXT_INT12 1 FLTEN14 1 15 RW 0x0 Disables Filter 0x1 Enables
160. Enables when local SRC data has xvYCC color space InRGB 1 Controls CSC parameter 0 Equation 601 1 Equation 709 when local SRC data has HD 709 color gamut BUFSTATUS_H 31 BUFSEL_H LIMIT_ON EQ709 Chooses color space conversion equation from YCbCr to RGB according to input value range 2 00 for YCbCr wide range and 2 11 for YCbCr narrow range Wide Range Y Cb Cr 255 0 Narrow Range Y 235 16 Cb Cr 240 16 Specifies Trigger Status read only 0 Does not issue trigger 1 Issues trigger Reserved Selects Data access method 0 Dedicated DMA 1 Local Path Specifies Buffer Status read only NOTE BUFSTATUS BUFSTATUS_H BUFSTATUS L Selects Buffer set NOTE BUFSEL BUFSEL BUFSEL 1 nWide Narrow 27 26 TRGSTATUS 25 RSVD ENLOCAL_F 22 BUFSTATUS en BUFSEL_L Specifies Double Auto control bit BUFAUTOEN 19 RW 0 Fixed BUFSEL 1 Auto Changed by Trigger Input 0 Disables swap SAMSUNG ELECTRONICS 16 66 ITU 4412 UM 16 Display Controller Enables swap sk should be set to 0 when ENLOCAL is 1 Specifies Byte swaps control bit BYTSWP F 0 Disables swap 1 Enables swap NOTE It should be set to O when ENLOCAL is 1 Specifies Half Word swap control bit HAWSWP F RW 0 Disables swap 1 Enables swap NOTE It should be set to 0 when ENLOCAL is 1 Specifies Word swap control bit 0 Disables swap WSWP_F RW 1
161. F and disable BLD PIX then the ALPHA SEL ALPHAO controls the AR AEN bit information is not used anymore SAMSUNG ELECTRONICS 16 29 ex 4412 UM 16 Display Controller Figure 16 24 illustrates the blending diagram 4 4 haA A B Blending 1 d Blending 2 AR 2 Blending 3 AR3 Blending 4 OUTPUT 8 Figure 16 24 Blending Diagram Example 16 5 Window Blending Factor Decision Window n s blending factor decision 0 1 2 3 4 For more information refer to the section on SFR SAMSUNG ELECTRONICS 16 30 x 4412 UM 16 Display Controller Figure 16 25 illustrates the blending factor decision ALPHAO gt ALPHA1R gt DATA gt Palette gt AR decision Keying AEN BLD PIK ALPHA SEL ALPHA MUL Figure 16 25 Blending Factor Decision NOTE If you use DATA 15 12 BPPMODE b 1110 ARGB4444 format to blend then the alpha value is DATA 15 12 DATA 15 12 4 bit gt 8 bit expanding SAMSUNG ELECTRONICS 16 31 ex 4412 UM 16 Display Controller 16 3 5 3 Color Key Function The Color Key function in display controller supports various effects for image mapping For special functionality the Color
162. FREQ DPM 23 0 Maximum Frequency of DPM 0 0 5 10 1 126 DVSEMCLK EN Base Address 0x1004 0000 e Address Base Address 0x1080 Reset Value 0x0000 0000 Avo er DVSEMCLK EN 0 DVS Emulation Clock Enable 0 0 SAMSUNG ELECTRONICS 5 137 en 4412 UM 5 Clock Management Unit 5 10 1 127 MAKPERF e Base Address 0x1004 0000 e Address Base Address 01084 Reset Value 0x0000 0000 ASV er me Maximum Performance Enable MAXPERF_EN RW 0 Disables 0 0 1 Enables 5 10 1 128 DMC PAUSE CTRL e Base Address 0x1004 0000 e Address Base Address 0x1094 Reset Value 0x0000_0000 ICE mee OOO STATE Species status for debugging mw Enable pause function for DREX2 DVFS DMC PAUSE RW PREX2 pause function works when RATIO or 0 0 _ENABLE DMCD_RATIO in CLK DIV DMCO register is changed SAMSUNG ELECTRONICS 5 138 IT 4412 UM 5 Clock Management Unit 5 10 1 129 DDRPHY LOCK CTRL e Base Address 0x1004 0000 e Address Base Address 0x1098 Reset Value 0x0000 0000 Use ctrl_locked signal coming from LPDDR_PHY to check DLL lock time duration 2 31 RW 0 Uses internal counter to measure DLL lock duration 1 Uses ctrl_locked signal 30 Enable Clearing of start signal CTRL RESYNC ENABLE 29 Enable ctrl resync pulse generation CTRL RESYNC Mask ctr
163. Figure 15 2 Figure 15 3 Figure 16 1 Figure 16 2 Figure 16 3 Figure 16 4 Figure 16 5 Figure 16 6 Figure 16 7 Figure 16 8 Figure 16 9 Figure 16 10 Figure 16 11 Figure 16 12 Figure 16 13 Figure 16 14 Figure 16 15 Figure 16 16 Figure 16 17 Figure 16 18 Figure 16 19 Figure 16 20 Figure 16 21 Figure 16 22 Figure 16 23 Figure 16 24 Figure 16 25 Figure 16 26 Figure 16 27 Figure 16 28 Figure 16 29 Figure 16 30 Figure 16 31 Figure 17 1 Figure 17 2 Figure 17 3 Figure 17 4 Figure 17 5 Figure 17 6 Figure 17 7 SAMSUNG ELECTRONICS I2 G Bus Block DiagraM AAA 14 2 Start and Stop CONGO MAA AA 14 4 12C Bus Interface Data 14 5 Data Transfer on the 2 14 5 Acknowledgement on the I2C Bus 14 6 Operations for Master Transmitter 14 8 Operations for Master Receiver 14 9 Operations for Slave Transmitter 14 10 Operations for Slave Receiver 14 11 SPI Transfer Format e Ue 15 4 Input Clock Diagram for u Ati ee beeen ieee 15 5 Auto Chip Select Mode Waveform CPOL 0 0 CH WIDTH Byte 15 10 Block Diagram of Display 16 1 Block Diagram of the Data EEE 16 6 Bl
164. Filter FLTWIDTH14 1 14 8 Filtering width of EXT INT12 1 Filter Enable for EXT INT12 0 FLTEN14 0 7 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH14 0 6 0 RW Filtering width of EXT_INT12 0 SAMSUNG ELECTRONICS 4 228 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 154 EXT_INT12_FLTCON1 e Base Address 0x1100 0000 e Address Base Address 0x086C Reset Value 0x0000_0000 Filter Enable for EXT_INT12 7 FLTEN14 7 31 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH14 7 30 24 Filtering width of EXT_INT12 7 Filter Enable for EXT INT12 6 FLTEN14 6 23 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH14 6 22 16 Filtering width of EXT INT12 6 Filter Enable for EXT INT12 5 FLTEN14 5 15 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH14 5 14 8 Filtering width of EXT INT12 5 Filter Enable for EXT INT12 4 FLTEN14 4 7 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH14 4 60 RW Filtering width of EXT_INT12 4 SAMSUNG ELECTRONICS 4 229 II 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 155 EXT_INT23_MASK e Base Address 0x1100 0000 e Address Base Address 0x0908 Reset Value 0x0000_007F RSVD EXT INT23 MASK 6 EXT INT23 MASK 5 EXT INT23 MASK 4 EXT INT23 MASK 3 EXT INT23 MASK 2 EXT INT23 MASK 1 0 0 Enables Interrupt 0 1 Masked 0 0
165. Filter 0x1 Enables Filter FLTWIDTH10 0 6 0 RW Filtering width of EXT_INT8 0 SAMSUNG ELECTRONICS 4 222 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 146 EXT_INT8_FLTCON1 Base Address 0x1100 0000 e Address Base Address 0x084C Reset Value 0x0000_0000 Filter Enable for EXT INT8 7 FLTEN10 7 31 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH10 7 30 24 Filtering width of EXT_INT8 7 Filter Enable for EXT INT8 6 FLTEN10 6 23 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH10 6 22 16 Filtering width of EXT_INT8 6 Filter Enable for EXT INT8 5 FLTEN10 5 15 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH10 5 14 8 Filtering width of EXT INT8 5 Filter Enable for EXT INT8 4 FLTEN10 4 7 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH10 4 6 0 RW Filtering width of EXT_INT8 4 SAMSUNG ELECTRONICS 4 223 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 147 EXT_INT9_FLTCONO e Base Address 0x1100 0000 e Address Base Address 0x0850 Reset Value 0x0000_0000 Filter Enable for EXT_INT9 3 FLTEN11 3 31 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH11 3 30 24 Filtering width of EXT_INT9 3 Filter Enable for EXT INT9 2 FLTEN11 2 23 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH11 2 22 16 Filtering width of EXT INT9 2 F
166. Format of 13 BPP A444 Display 1 Specifies the transparency value selection bit 0 Selects ALPHAO AEN 1 Selects ALPHA1 When it sets per pixel blending then this pixel blends with alpha value that AEN selects 2 D 11 8 Red data D 7 4 Green data and D 3 0 Blue data 3 16 BPP 4444 mode For more information refer to the section on SFR Data has Alpha value BYSWP 0 HWSWP 0 WSWP 0 D 63 60 D 59 48 0 47 44 04332 031 28 D 27 16 D 1512 D 11 0 000H ALPHA P1 ALPHA P2 ALPHAS P3 ALPHA P4 004H ALPHA P5 ALPHA P6 ALPHA7 P7 ALPHA8 P8 008H ALPHA P9 ALPHA10 P10 ALPHA11 P11 2 12 SAMSUNG ELECTRONICS 16 18 4412 UM 16 Display Controller 16 3 3 2 10 8 BPP Display A232 Figure 16 15 illustrates the 8 BPP display BYSWP 1 HWSWP 0 WSWRO 0169 D 62 56 0155 D 46 40 D 31 9 30 24 D 2218 005 D 148 OOH AN P8 P6 P4 P3 P2 AEN P16 AEN P14 AEN P12 11 Pio P24 AEN P22 AEN P20 P19 P18 P2 P3 Ps Pe P7 Ps P1o P11 P12 LCD Panel Figure 16 15 Memory Format of 8 BPP A232 Display NOTE 1 Specifies the transparency value selection bit AEN 0 Selecis ALPHAO 1
167. Graphic Accelerator G3D Multi Format Codec MFC Universal Asynchronous Receiver UART Inter Integrated CircuitO 120 Serial Peripheral InterfaceO SPI SAMSUNG ELECTRONICS ae x Exynos 4412 UM 3 Chip ID Chip ID 3 1 Overview The Exynos 4412 includes Chip ID block for the Software SW that sends and receives Advanced Peripheral Bus APB interface signals to the bus system SAMSUNG ELECTRONICS 3 1 IT Exynos 4412 UM 3 Chip ID 3 2 Register Description 3 2 1 Register Map Summary e Base Address 0x1000 0000 PRO ID 0 0000 Product information ID package and revision 0xE441_2XXX PACKAGE_ID 0x0004 Package information POP type and package OxXXXX_XXXX 3 2 1 1 PRO_ID e Base Address 0x1000_0000 e Address Base Address 0x0000 Reset Value 0xE441_2XXX Description Reset Value Product ID 0x4412 Reserved 0 0 Exynos 4412 Package Information 0x2 Main Revision Number 0x1 Sub Revision Number 0x1 NOTE PRO ID register 31 0 depends on the e fuse ROM value As power on sequence is progressing it loads the e fuse ROM values to the registers can read the loaded current e fuse ROM values An e fuse ROM has main and sub revision numbers 3 2 1 2 PACKAGE_ID Base Address 0x1000_0000 e Address Base Address 0x0004 Reset Value Package ID 31 0 oR Package information POP type and package OXXXXX_XXXX NOTE PACKAGE ID
168. INT40 PEND 2 EXT INT40 PEND 1 EXT INT40 PEND 0 5 4 8 RWX 2 RWX 1 SAMSUNG ELECTRONICS 4 General Purpose Input Output GPIO Control 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 4 284 4412 UM 4 3 3 227 EKT INT41 PEND e Base Address 0x1100 0000 e Address Base Address 0x0F44 Reset Value 0x0000 0000 RSVD EXT INT41 PEND 7 EXT INT41 PEND 6 EXT INT41 PEND 5 EXT 41 PEND 4 EXT INT41 PEND 3 EXT INT41 PEND 2 EXT INT41 PEND 1 EXT INT41 PEND 0 5 4 3 RWX 2 RWX 1 SAMSUNG ELECTRONICS 4 General Purpose Input Output GPIO Control 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 4 285 4412 UM 4 3 3 228 EXT_INT42_PEND Base Address 0x1100_0000 e Address Base Address 0x0F48 Reset Value 0 0000 0000 RSVD EXT INT42 PEND
169. Input Output GPIO Control 4 3 2 44 GPFODAT Base Address 0x1140_0000 e Address Base Address 0x0184 Reset Value 0 00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPFODAT 7 0 7 0 output port the pin state should be same as the 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 2 45 GPFOPUD Base Address 0x1140_0000 e Address Base Address 0x0188 Reset Value 0x5555 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down GPFOPUD n a 0t0 7 RW x Reserved 0 5555 0x3 Enables Pull up 4 3 2 46 GPFODRV Base Address 0x1140_0000 e Address Base Address 0x018C Reset Value 0x00_0000 23 16 Reserved Should be zero W GPFODRVIn n 2n 1 2 0x0000 0107 SAMSUNG ELECTRONICS 4 44 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 47 GPFOCONPDN Base Address 0x1140_0000 e Address Base Address 0x0190 Reset Value 0x0000 0x0 Outputs O 2n 1 2n 0x1 Outputs 1 0107 RW 0x2 Input 0 3 Previous state 4 3 2 48 GPFOPUDPDN e Base Address 0x1140_0000 e Address Base Address 0x0194 Reset Value 0x0000 0 0 Disables Pull up Pull down 2n 1 20 0 1 Enables Pull down 0107 RW 0x2 Reserved DE 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 45 II
170. JPEG 0 SEL 0 RW 1 SCLKAPLL MUXJPEG 0 is the source clock of JPEG core SAMSUNG ELECTRONICS 5 72 ex 4412 UM 5 Clock Management Unit 5 10 1 38 CLK SRC MASK CAMO Base Address 0x1003 0000 e Address Base Address 0xC320 Reset Value 0 1111_1111 RSVD eee ___ _ _ 99 Mask output clock of MUXCSIS1 CSIS1_MASK 28 RW 0 Mask 1 Unmask SE eras Rmwa 99 Mask output clock of MUXCSISO CSISO MASK 24 RW 0 Mask 1 Unmask SE A Mask output clock of MUXCAM 1 1 5 20 RW 0 Mask 1 Unmask SE vem fo Mask output clock of MASK 16 RW 0 Mask 1 Unmask SE Rmwa 99 Mask output clock of MUXFIMC3_LCLK FIMC3_LCLK_MASK 12 RW 0 Mask 1 Unmask SE ma AA Mask output clock of MUXFIMC2_LCLK FIMC2 LCLK MASK RW 0 Mask 1 Unmask SE as mo Mask output clock of MUXFIMC1_LCLK MASK 4 RW 0 Mask 1 Unmask SE mo Mask output clock of MUXFIMCO_LCLK MASK RW 0 Mask 1 Unmask SAMSUNG ELECTRONICS 5 73 ex 4412 UM 5 Clock Management Unit 5 10 1 39 CLK SRC MASK TV Base Address 0x1003 0000 e Address Base Address 0xC324 Reset Value 0x0000_0111 RSV au ne Mask output clock of MUXHDMI HDMI_MASK 0 RW 0 Mask 0 1 1 Unmask
171. MCT LO 24 RSVD 23 CPU nIRQOUT 2 22 PARITYFAILSCU2 21 Masked interrupt pending status PARITYFAL2 If the corresponding interrupt enable bit is 0 PARITYFAIL2 20 the IMSR bit reads as 0 19 R 0 The interrupt is not pending E __ _ _ _ __ _ _ __ o CPU_PMUIRQ_2 18 1 The interrupt is pending RSVD 17 11 16 mew SYSMMU ISP CXM 3 Masked interrupt pending status Lm roo rue roli Da ne conspondng nu eanet __ SYSMMU_FIMC_DRCI 11 R 0 The interrupt is not pending o SYSMMU FIMC ISP 1 10 1 The interrupt is pending IEEE SYSMMU LITEO SYSMMU_FIMC_LITEO 1 o _ _ __ _ __ o gt tU R 19 SYSMMU ISP CXD B Masked interrupt pending status rog ta R somosponding enable SYSMMU_FIMC_DRC O 3 R 0 The interrupt is not pending SYSMMU_FIMC_ISP O 2 1 The interrupt is pending SYSMWU FIMG LITEOOL m R svewwu FIMO R _ SAMSUNG ELECTRONICS 7 29 4412 UM 7 Interrupt Combiner 7 6 2 21 CIPSRO Base Address 0x1044 0000 e Address Base Address 0x0100 Reset Value Undefined Reserved
172. Masked SAMSUNG ELECTRONICS 4 281 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 224 EXT_INT42_MASK e Base Address 0x1100 0000 e Address Base Address 0x0F08 Reset Value 0x0000_00FF ex ac norem ene EXT_INT42_MASKT 5 5 ce _ 4 Somme aw 007 Ene tr re masa m 90 Esl ner m nw nri 0 0 Enables Interrupt EXT INT42 MASK 1 1 0 1 Masked 0 0 Enables Interrupt EXT INT42 Rw 0 1 Masked SAMSUNG ELECTRONICS 4 282 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 225 EKT INT43 MASK e Base Address 0x1100 0000 e Address Base Address OxOFOC Reset Value 000 Ox MASA om m ww ae ene EXT INT43 MASK 5 5 gt _ 4 oo maoga pw 90 Eels merum as m nw 207 Erebos merum m aw norint 0 0 Enables Interrupt EXT INT43 MASK 1 1 0 1 Masked 0 0 Enables Interrupt EXT INT43 MASK 0 Rw 0 1 Masked SAMSUNG ELECTRONICS 4 283 IT 4412 UM 4 3 3 226 EKT INT40 PEND Base Address 0x1100 0000 e Address Base Address 40 Reset Value 0x0000 0000 RSVD EXT 40 PEND 7 EXT 40 PEND 6 EXT 40 PEND 5 EXT INT40 PEND 4 EXT 40 EXT
173. MsgLenght NFECCCONF 25 16 to the size that you want NOTE You should set the ECC parity conversion codes to check free page error Refer to 10 4 11 ECC Parity Conversion Code Guide for 8 12 16 bit ECC for more information SAMSUNG ELECTRONICS 10 11 IT 4412 UM 10 NAND Flash Controller 10 4 11 ECC Parity Conversion Code Guide for 8 12 16 bit ECC The ECC parity conversion codes are there to fix errors which occur when reading a free page Free page means the erased page The 8 12 16 bit ECC modules support variable message size for meta data stored in spare area Generally the size of main data sector is 512 byte and user should set the corresponding ECC parity conversion codes as the Table describes ECC Type ECC Parity Conversion Codes 8 bit ECC Here 13 byte ECC parity conversion codes 12 bit ECC Here 20 byte ECC parity conversion codes 16 bit ECC Here 26 byte ECC parity conversion codes Depending on the requirements of users the message size for meta data stored spare area might differ Therefore you can change the size of meta data by changing MsgLength NFECCCONF 25 16 and change ECC parity conversion codes Steps to determine ECC parity conversion codes according to the size of message length are 1 Clear all ECC parity conversion registers NFECCCONECCO to 6 as all zero 2 Set all registers for page program 3 Reset InitMECC NFECCCONT 2 bit as 1 4 Write Oxff
174. Output GPIO Control 4 3 5 35 Base Address 0x106E 0000 e Address Base Address 0x0700 Reset Value 0x0000 0000 RSV ey o Sets signaling method of EXT INT30 7 0 0 Low level 0 1 High level EXT 0 CON 7 30 28 RW 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0 7 Reserved 85 2 eee Sets signaling method of EXT INT30 6 0x0 Low level 0 1 High level EXT INT30 CON 6 26 24 RW 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0x5 to 0 7 Reserved ASVO mee Jo Sets signaling method of EXT_INT30 5 0x0 Low level 0x1 High level EXT INT30 CON 5 22 20 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0 5 to 0x7 Reserved 85 0 mee fo Sets signaling method of EXT_INT30 4 0 0 Low level 0x1 High level EXT_INT30_CON 4 18 16 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0 7 Reserved 85 9 AN Sets signaling method of EXT_INT30 3 0 0 Low level 0x1 High level EXT 0 CON 3 14 12 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0 7 Reserved mo lii seemed oc SAMSUNG ELECTRONICS 4 314 27 4412 UM 4 General Purpose Input Output GPIO Control Se
175. Outputs 1 net 0104 RW 0x2 Input me 0 3 Previous state 4 3 2 30 GPC1PUDPDN Base Address 0x1140 0000 e Address Base Address 0x0094 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down 0104 RW 0x2 Reserved DE 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 36 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 31 GPDOCON Base Address 0x1140_0000 e Address Base Address 0x00AO0 Reset Value 0x0000 0000 0 0 Input 0 1 Output GPDOCON 3 15 12 e 0 00 0 4 to Reserved OxF EXT_INT6 3 0 0 Input 0 1 Output GPDOCON 2 11 8 e 0x00 0 4 to OxE Reserved EXT INT6 2 0 0 Input 0 1 Output GPDOCON 1 7 4 e I P BUM 0x00 0x4 to OxE Reserved OxF EXT INT6 1 0 0 Input 0 1 Output GPDOCON O 3 0 vim 5 0 00 0 4 to Reserved OxF INT6 0 SAMSUNG ELECTRONICS 4 37 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 32 GPDODAT Base Address 0x1140_0000 e Address Base Address 0x00A4 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPDODAT 3 0 3 0 output port then pin state should be same as 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 2 33 GPDOPUD B
176. RIGHT 0 Mask 1 Pass SAMSUNG ELECTRONICS 5 42 ex 4412 UM 5 Clock Management Unit 5 10 1 14 CLK GATE IP PERIR e Base Address 0 1003 0000 e Address Base Address 08960 Reset Value OxFFFF_FFFF Gating all clocks for CMU_ISPPART CLK_CMU_ISPPART 18 RW 0 Mask 1 Pass Gating all clocks for TMU_APBIF CLK_TMU_APBIF 17 0 Mask 1 Pass Gating all clocks for KEYIF CLK KEYIF 16 0 Mask CLK RTC 15 14 CLK MCT 13 1 Pass Gating all clocks for RTC 0 Mask 1 Pass Gating all clocks for WDT 0 Mask 1 Pass Gating all clocks for System Timer 0 Mask 1 Gating all clocks for HDMI 0 Mask 1 Pass CLK_TZPC2 7 1 Pass TZPC1 Gating all clocks TZPC1 0 Mask SAMSUNG ELECTRONICS 5 43 en Gating all clocks for TZPC5 0 Mask 1 Pass Gating all clocks for TZPC4 0 Mask 1 Pass Gating all clocks for TZPC3 0 Mask 1 Pass Gating all clocks for TZPC2 0 Mask Gating all clocks for SECKEY CLK_SECKEY 12 RW 0 Mask 0 1 1 Pass 4412 UM CLK TZPCO CLK CMU COREPART CLK CMU TOPPART CLK PMU APBIF CLK SYSREG CLK CHIP ID SAMSUNG ELECTRONICS 5 Clock Management Unit Gating all clocks for TZPCO 0 Mask 1 Pass Gating all clocks for CMU_COREPART 0 Mask 1 Pass Gating all clocks for CMU_TOPPART 0 Mask 1 Pass Gating all clocks for PMU APBIF 0 Mask
177. RWX When you configure port as input port then corresponding bit is pin state When configuring as GPBDAT 7 0 7 0 output port the pin state should be same as 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 2 15 GPBPUD Base Address 0x1140 0000 e Address Base Address 0x0048 Reset Value 0x5555 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down SPBPUBIN n 0to7 RW 0x2 Reserved 05955 0x3 Enables Pull up 4 3 2 16 GPBDRV e Base Address 0x1140_0000 e Address Base Address 0x004C Reset Value 0 00 0000 23 16 Reserved Should be zero W GPBDRVIn n 2n 1 21 0x0000 0107 SAMSUNG ELECTRONICS 4 29 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 17 GPBCONPDN e Base Address 0x1140_0000 e Address Base Address 0x0050 Reset Value 0x0000 0x0 Outputs O 2n 1 2n 0x1 Outputs 1 GREIN 0107 RW 0x2 Input 999 0 3 Previous state 4 3 2 18 GPBPUDPDN Base Address 0x1140_0000 e Address Base Address 0x0054 Reset Value 0x0000 0 0 Disables Pull up Pull down 2n 1 20 0 1 Enables Pull down GPB n 0107 BW 0 2 Reserved oe 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 30 ex 4412 UM 4 3 2 19 GPCOCON e Base Address 0x1140 0000 e Address Base Address 00060 Reset Value 0 0000 0000 GPCOCON 4 19 16
178. Reserved OxF EXT_INT16 1 0 0 Input 0 1 Output GPF3CONJ 0 3 0 RW 0 2 LCD VD 20 0 00 0x3 10 Reserved OxF EXT_INT16 0 SAMSUNG ELECTRONICS 4 52 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 62 GPF3DAT e Base Address 0x1140_0000 e Address Base Address 1 4 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPF3DAT 5 0 5 0 output port the pin state should be same as the 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 2 63 GPF3PUD Base Address 0x1140 0000 e Address Base Address 0x01E8 Reset Value 0x0555 0 0 Disables Pull up Pull down 2 1 2n 0 1 Enables Pull down GPF3PUDI n 0105 RW x Reserved 0 0555 0x3 Enables Pull up 4 3 2 64 GPF3DRV e Base Address 0x1140_0000 e Address Base Address 0x01EC Reset Value 0x00_0000 23 16 Reserved Should be zero W GPF3DRV n n 2n 1 21 0x0000 0105 4 3 2 65 GPF3CONPDN Base Address 0 1140_0000 e Address Base Address 0x01F0 Reset Value 0x0000 0 0 Outputs 0 2n 1 21 0 1 Outputs 1 0105 Y 0 2 Input oe 0 3 Previous state SAMSUNG ELECTRONICS 4 53 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 66 GPF3PUDPDN e Base Address 0x1140
179. RnB interrupt SAMSUNG ELECTRONICS 10 18 27 4412 UM 10 NAND Flash Controller Enables RnB interrupt RnB transition detection configuration R 0 Detects rising edge 1 Detects falling edge RnB TransMode Bit Lock area generation 0 Unlocks Main area 1 Locks Main area Main area ECC status register is NFMECCO NFMECC1 0 0 0 0034 0xBOEO 0038 Lock Spare area ECC generation 0 Unlocks Spare ECC 1 Locks Spare ECC Spare area ECC status register is NFSECC 0 0 0 003C m Bn 1 Initializes main area ECC decoder encoder Write IntMECC IntSECC 2 1 Initializes spare area decoder encoder Write only Reserved HW_nCE NAND flash memory nRCS 1 signal control flash memory nRCS 0 signal control 0 Force nRCS 0 to low enables chip select 1 Force nRCS 0 to high disables chip select Reg nCEO 1 H NOTE The setting all nCE 3 0 zero cannot be allowed Only one nCE can be asserted to enable external NAND flash memory The lower bit has more priority when user set all nCE 3 0 zeros NAND flash controller operating mode RW 0 Disables flash controller 1 Enables NAND flash controller SAMSUNG ELECTRONICS 10 19 II 4412 UM 10 NAND Flash Controller 10 7 2 3 NFCMMD e Base Address OXOCEO 0000 e Address Base Address 0x0008 Reset Value 0x0000 0000 REG C
180. S PDIF interface support for digital audio Eight 12C interface support Three SPI support Four UART supports three Mbps ports for Bluetooth 2 0 On chip USB 2 0 Device supports high speed 480 Mbps on chip transceiver On chip USB 2 0 Host support Two on chip USB HSIC Four SD SDIO HS MMC interface support SAMSUNG ELECTRONICS 1 2 ex 4412 UM 1 Product Overview e 24 channel DMA controller 8 channels for Memory to memory 16 channels for Peripheral DMA Supports 14 x 8 key matrix e Configurable GPIOs e Real time clock PLL timer with PWM and watch dog timer e Multi core timer support for accurate tick time in power down mode except sleep mode e Memory Subsystem Asynchronous SRAM ROM NOR interface with x8 or x16 data bus NAND interface with x8 data bus LPDDR2interface 800 Mbps pin DDR SAMSUNG ELECTRONICS 1 3 IT 4412 UM 1 Product Overview 1 2 1 Multi Core Processing Unit The features of main microprocessors are The ARM Cortex A9 MPCore quad core processor integrates the proven and highly successful ARM MPCore technology along with further enhancements to simplify and broaden the adoption of multi core solutions e With the ability to scale in speed from 200 MHz to 1 4 GHz the ARM Cortex A9 MPCore quad processor meets the requirements of power optimized mobile devices which require operation in low power and performance optimized consumer applications
181. Then the VTIME module generates programmable control signals that support different types of display devices RGB VSYNC signal causes the LCD line pointer to begin at the top of display The configuration of both HOZVAL field and LINEVAL registers control pulse generation of RGB VSYNC and RGB HSYNC Based on these equations the size of the LCD panel determines HOZVAL and LINEVAL e HOZVAL Horizontal display size 1 LINEVAL Vertical display size 1 The CLKVAL field in VIDCONO register controls the rate of signal RGB_VCLK Hz SCLK_FIMDx CLKVAL 1 where CLKVAL gt 1 where SCLK_FIMDx x 0 1 Table 16 1 describes the relationship of CLKVAL The minimum value of CLKVAL is 1 e Hz SCLK_FIMDx CLKVAL 1 where CLKVAL gt 1 where SCLK_FIMDx x 0 1 Table 16 1 Relation 16 BPP between VCLK and CLKVAL TFT Frequency of Video Clock Source 60 MHz CLKVAL 60 MHz X VCLK VSYNC VBPD VFPD HSYNG HOZVAL and LINEVAL configure RGB HSYNC RGB VSYNC signal For more information refer to RGB Hz SCLK_FIMDx CLKVAL 1 where CLKVAL gt 1 where SCLK_FIMDx x 0 1 The frame rate is RGB_VSYNC signal frequency The frame rate associates with the field of VSYNC VBPD VFPD LINEVAL HSYNC HBPD HFPD HOZVAL and CLKVAL registers Most LCD drivers require their own adequate frame rate SAMSUNG ELECTRONICS 16 35
182. They require over 2000 Dhrystone MIPS e Other features ARM 9 MPCore quad core processor are Thumb 2 technology for greater performance energy efficiency and code density signal processing extensions Jazelle RCT Java acceleration technology TrustZone technology for secure transactions and DRM Floating Point unit for significant acceleration for both single and double precision scalar Floating Point operations Optimized L1 caches for performance and power Integrated 1 MB L2 Cache using standard compiled RAMs Program Trace Macrocell and CoreSight e Generic Interrupt Controller Supports three interrupt types o Software Generated Interrupt SGl o Private Peripheral Interrupt PPI Shared Peripheral Interrupt SPI Programmable interrupts that enable to set the o Security state for an interrupt o Priority level of an interrupt o Enabling or disabling of an interrupt Processors that receive an interrupt Enhanced security features SAMSUNG ELECTRONICS 1 4 ex 4412 UM 1 Product Overview 1 2 2 Memory Subsystem The features of memory subsystem are e High bandwidth Memory Matrix subsystem e Two independent external memory ports o 1x16 Static Hybrid Memory port 2x32 DRAM port e Matrix architecture increases the overall bandwidth with simultaneous access capability SRAM ROM NOR Interface o X80rx16 data bus o Addresses range support 23 bit o Supports asynchronous
183. VDEN VEN VSYNC VEN HSYNG VEN FIELD VEN HREF SYS 50 SYS CS1 SYS WE and so on Using the display controller data you can select one of the above data paths by setting LCDBLK CFG Register 0x1001 0210 For more information refer to the System Others manual SAMSUNG ELECTRONICS 16 4 ex 4412 UM 16 Display Controller 16 3 2 Data Flow FIFO 15 in the VDMA FIFO is empty or partially empty VDMA requests data fetching from frame memory based on burst memory transfer mode The data transfer rate determines the size of FIFO The display controller contains five FIFOs Three local FIFOs and two DMA FIFOs since it needs to support the overlay window display mode Use one FIFO for one screen display mode VPRCS fetches data from FIFO It contains the following functions for final image data blending image enhancing and scheduling It also supports the overlay function This can overlay any image up to five window images whose smaller or same size can be blended with the main window image having programmable alpha blending or color chroma key function Figure 16 2 shows the data flow from system bus to output buffer VDMA has five channels 0 4 and three local input interfaces CAMIFO CAMIF1 and CAMIF2 or CAMIF3 The Color Space Conversion CSC block changes Hue YCbCr local input only data to RGB data for blending operation Also the alpha values written in SFR determine the level of
184. Value 0x0000_00C2 Revo 122 Specifies constant that it uses in alphaB alpha value of background 1 0000 0 zero 0001 1 maximum 0010 alphaA 2 alpha value of foreground 1 0011 1 alphaA 0100 alphaB 0101 1 alphaB FUNC 21 18 RW 0110 ALPHAO 0111 Reserved 100x Reserved 1010 A foreground color data 1011 1 1100 background color data 1101 1 111 RSVD 716 Specifies constant that it uses in alpha P_FUNC_F 15 12 RW Same as above see COEF 9 RD Specifies constant that it uses B_FUNC_F RW Same as above see COEF_Q RD 54 Specifies constant that it uses in A FUNC F RW Same as above see COEF Q NOTE For more information Refer to Figure 16 23 Blending equation 1 Background Window 0123 foreground Window 4 in Blend Equation 4 2 BPPMODE F BLD PIX ALPHA SEL 9 WINCONx WxPAL WPALCON decides alphaA and alphaB SAMSUNG ELECTRONICS 16 128 227 4412 UM 16 Display Controller 16 5 3 84 BLENDCON e Base Address 0x11C0_0000 e Address Base Address 0x0260 Reset Value 0x0000_0000 Specifies alpha value width BLEND_NEW RW 0 4 bit alpha value 0x0 1 8 bit alpha value 16 5 3 85 WnRTQOSCON n 0 to 4 e Base Address 0x11C0_0000 e Address Base Address 0x0264 Reset Value 0x0000 0000 WORTQOSCON e Address B
185. WARNING No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung This publication is intended for use by designated recipients only This publication contains confidential information including trade secrets of Samsung protected by Competition Law Trade Secrets Protection Act and other related laws and therefore may not be in part or in whole directly or indirectly publicized distributed photocopied or used including in a posting on the Internet where unspecified access is possible by any unauthorized third party Samsung reserves its right to take any and all measures both in equity and law available to it and claim full damages against any party that misappropriates Samsung s trade secrets and or confidential information SE FE labas DP HRA B TRAE ES MENS FET BEA RANGE FER SERT EE RA 5 REEK EAA EA TI GZR LADE TR FINSE IE HE BJ TRA SUR AED DIER TE ENGER k Trademarks All brand names trademarks and registered trademar
186. XrnWBE 1 0 is dedicated nBE 1 0 Wait enable control for memory bank 0 0 Disables WAIT 1 Enables WAIT Select SROM ADDR base for memory bank 0 0 SROM_ADDR is half word base address SROM ADDR 22 0 lt HADDR 23 1 1 SROM ADDR is byte base address SROM ADDR 22 0 HADDR 22 0 NOTE When DataWidthO is 0 SROM ADDR is byte base address It ignores this bit Data bus width control for memory bank 0 0 8 bit 1 1 16 bit 4412 UM 9 SROM Controller 9 6 1 2 SROM BCn n 0 to 3 e Base Address 0x1257 0000 e Address Base Address 0x0004 Reset Value 0x000F 0000 SROM BCO e Address Base Address 0x0008 Reset Value 0x000F 0000 SROM BC1 e Address Base Address 0x000C Reset Value 0x000F 0000 SROM BC2 Address Base Address 0x0010 Reset Value 0x000F 0000 SROM BC3 Address set up before nGCS 0000 0 Clock 0001 1 Clocks 0010 2 Clocks 0011 3 Clocks Tacs 31 28 RW 1100 12 Clocks 1101 13 Clocks 1110 14 Clocks 1111 2 15 Clocks NOTE More 1 2 cycles according to bus i f status Chip selection set up before nOE 0000 0 Clock 0001 1 Clocks 0010 2 Clocks Tcos 27 24 Rw 0011 Clocks 1100 12 Clocks 1101 13 Clocks 1110 14 Clocks 1111 15 Clocks A 9 Access cycle 00000 1 Clock 00001 2 Clocks 00001 3 Clocks Tacc 20 16 RW 00010 4 Clocks 11100 29 Clocks 11101 30 Clocks 11110 31 Clocks 11111 32 Clocks Chip
187. active low signal Decides whether Adaptive Frequency Calibrator AFC is enabled or not When AFC is enabled it AFC RW calibrates VCO automatically e B 0 Enables AFC 1 Disables AFC It is an active low signal Specifies if the dithered mode is enabled or not SSCG EN 5 RW Disables dithered mode 1 Enables dithered mode If BYPASS 1 then it enables bypass mode Four BYPASS 4 RW Fin If BYPASS 0 then PLL3600X operates normally FVCO EN Enable pin for our Pin selection for monitoring purposes FSEL 2 RW FVco if FSEL is set to 0 Fvco ouT FSEL is set to 1 ICP_BOOST ICP_BOOST If AFC_ENB is set to logic LOW then it enables the AFC If AFC_ENB is set to logic HIGH then EXTAFC 4 0 controls the VCO frequency tuning range EXTAFC specifies the decimal value of EXTAFC 4 0 as EXTAFC EXTAFC 4 0 The hexadecimal values specified for EXTAFC 4 0 registers are e 5 b0 0000 lt EXTAFC 4 0 lt 5 b1 1111 NOTE The other PLL control inputs should be set as DCC_ENB 1 ICP_BOOST 0 SSCG_EN 0 Disable dithered mode 0 EXTAFC 0 SAMSUNG ELECTRONICS 5 50 ex 4412 UM 5 Clock Management Unit 5 10 1 22 VPLL CONO Base Address 0x1003 0000 e Address Base Address 0xC120 Reset Value 0x006F 0302 PLL Enable Control ENABLE 31 RW 0 Disables 1 Enables SE ne fo PLL Locking Indication LO
188. and clear write for hardware scan of second Key Read 0 Does not occur 1 Released interrupt occurs Write Clears released interrupt when write 1 KEYPAD input press interrupt falling edge status read and clear write for HW scan of second Key Read 0 Does not occur 1 Pressed interrupt occurs Write Clear pressed interrupt when write 1 KEYPAD input release interrupt rising edge status read and clear write for HW scan of first Key Read 0 Does not occur 1 Released interrupt occurs Write Clears released interrupt when write 1 KEYPAD input press interrupt falling edge status read and clear write for hardware scan of first Key Read 0 Does not occur 1 Pressed interrupt occurs Write Clears pressed interrupt when write 1 17 16 4412 UM 18 ADC ADC This chapter describes the functions and usage of general ADC 18 1 Overview The 10 bit or 12 bit CMOS Analog to Digital Converter ADC comprises of 4 channel analog inputs lt converts the analog input signal into 10 bit 12 bit binary digital codes at maximum conversion rate of 1MSPS with 5MHz A D converter clock A D converter operates with on chip sample and hold function ADC supports low power mode SAMSUNG ELECTRONICS 18 1 ex 4412 UM 18 2 Features The ADC includes the following features Resolution 10 bit 12 bit optional e Differential Nonlinearity Error 2 0 LSB
189. bit When the port is configured as functional pin the undefined value will be read 4 3 3 91 GPMOPUD Base Address 0x1100 0000 e Address Base Address 0x0268 Reset Value 0x5555 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down GPMOPUD n nieto 7 RW 0x2 Reserved 0x5555 0x3 Enables Pull up 4 3 3 92 GPMODRV Base Address 0x1100 0000 e Address Base Address 0x026C Reset Value 0 00 0000 23 16 Reserved Should be zero W GPMODRVIn n 2n 1 21 0x0000 0107 SAMSUNG ELECTRONICS 4 175 II 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 93 GPMOCONPDN e Base Address 0x1100 0000 e Address Base Address 0x0270 Reset Value 0x0000 0 0 Outputs 0 2n 1 21 0 1 Outputs 1 0107 0 2 Input 2599 0 3 Previous state 4 3 3 94 GPMOPUDPDN Base Address 0x1100_0000 e Address Base Address 0x0274 Reset Value 0 0000 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down GEMA 0107 zi 0x2 Reserved 990 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 176 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 95 GPM1CON Base Address 0x1100 0000 e Address Base Address 0 0280 Reset Value 0x0000_0000 0 0 Input 0 1 Output 0 2 CAM BAY RGB 13 GPM1CONI6 27 24 s der 0x00 0 5 TraceData 12 0 6 to Reserved OxF
190. both edge 0x5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 208 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 128 EXT INT10CON e Base Address 0x1100 0000 e Address Base Address 0x072C Reset Value 0x0000 0000 I 9 Sets signaling method of EXT INT10 4 0 0 Low level 0 1 High level EXT INT10 CON 4 18 16 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved 85 9 fm Sets signaling method of EXT INT10 3 0 0 Low level 0 1 High level EXT 10 CON 3 14 12 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved 85 0 mp 1 4 Sets signaling method of EXT_INT10 2 0x0 Low level 0x1 High level EXT_INT10_CON 2 10 8 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0 7 Reserved Sets signaling method of EXT_INT10 1 0 0 Low level 0x1 High level EXT INT10 CON 1 6 4 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved Sets signaling method of EXT_INT10 0 0 0 Low level 0x1 High level EXT INT10 CON O 2 0 RW 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 209 ex 4412 UM 4 General Purp
191. byte 6 Parity 15 8 6 parity generated from main area 512 byte 5 Parity 7 0 EN 5 Check parity generated from main area 512 byte NOTE The NAND flash controller generates these ECC parity codes when write main area data while the MainECCLock NFCON 7 bit is 0 unlock 10 7 2 16 NFSECC e Base Address OXOCEO 0000 e Address Base Address 0x003C Reset Value OxFFFF_FFFF BH fe ____________ Reset Vale _____ 5 R Spare area EGO Sas sco mo Spare area Ses NOTE The flash controller generates when Read or Write spare area data while the SpareECCLock NFCONT 6 bit is unlock 10 7 2 17 NFMLCBITPT e Base Address OXOCEO 0000 e Address Base Address 0x0040 Reset Value 0x0000 0000 4 Error bit pattern 31 24 4 Error bit pattern 0 00 2 Error bit pattern 15 8 2 Error bit pattern 0x00 1 Error bit pattern 7 0 1 Error bit pattern 0 00 3 Error bit pattern 23 16 3 Error bit pattern SAMSUNG ELECTRONICS 10 28 II 4412 UM 10 NAND Flash Controller 10 7 3 ECC Registers for 8 12 and 16 bit ECC 10 7 3 1 NFECCCONF e Base Address OXOCE2 0000 e Address Base Address 0x0000 Reset Value 0x0000_0000 RSVD 31 RSVD 28 message size MsgLength 25 16 For 512 byte message you should set to 511 W Re
192. clock for the Audio Sub system It divides EPLL output to generate 24 MHz SLIMbus clock e VPLL uses FINPLL or SCLK_HDMI24M as input to generate frequencies from 22 to 1400 MHz This PLL generates 54 MHz video clock or G3D clock e USB Device PHY uses XUSBXTI to generate frequencies of 30 and 48 MHz e HDMI PHY uses XUSBXTI to generate 54 MHz In typical Exynos 4412 applications e Cortex A9 MPCore CoreSight and HPM use e DRAM system bus clocks and other peripheral clocks like audio IPs and SPI use MPLL and EPLL e Video clock uses VPLL e G3D uses MPLL or VPLL as input clock source Clock controllers allow bypassing of PLLs for low frequency clock They also provide clock gating to each block thereby reducing power consumption SAMSUNG ELECTRONICS 5 4 ex 4412 UM 5 4 Clock Relationship The clock relationship between various clocks are e CPU BLK clocks freq ARMCLK freq ACLK_COREMO freq ACLK COREM1 freq PERIPHCLK ATCLK freq PCLK_DBG e clocks SCLK_DMC ACLK_DMCD freq ACLK_DMCP freq ACLK ACP lm SCLK C2C 2 e LEFTBUS clocks GDL ACLK GPL e HIGHTBUS clocks GPR e clocks ACLK 400 MCUISP 200
193. code 0x00 2 23 Conversion Code 23 16 x 25 Conversion Code 7 0 RW 25 ECC Parity conversion code 0x00 0 15 Conversion Code 23 16 1 3 th 0 SAMSUNG ELECTRONICS 10 36 4412 UM 10 NAND Flash Controller NOTE For more information about ECC parity conversion codes refer to 10 4 11 ECC Parity Conversion Code Guide for 8 12 16 bit ECC SAMSUNG ELECTRONICS 10 37 ex 4412 UM 11 Pulse Width Modulation Timer Pulse Width Modulation Timer 11 1 Overview Exynos 4412 has five 32 bit Pulse Width Modulation PWM timers These timers generate internal interrupts for the ARM subsystem Additionally timers 0 1 2 and include a PWM function that drives an external I O signal The PWM in timer 0 has an optional dead zone generator capability to support a large current device Timer 4 1 an internal timer without output pins The Timers use the APB PCLK as source clock Timers O and 1 share a programmable 8 bit prescaler that provides the first level of division for the PCLK Timers 2 3 and 4 share a different 8 bit prescaler Each timer has its own private clock divider that provides a second level of clock division prescaler divided by 2 4 8 or 16 Each timer has its 32 bit down counter the timer clock drives this counter The Timer Count Buffer registers loads initial value of the down counter If the down counter reaches zero it generates the timer interru
194. components Various low power modes are available such as Idle Stop Deep Stop Deep Idle and Sleep modes Wake up sources in sleep mode are o External interrupts o alarm o Tick timer o Keyinterface Wake up sources of Stop and Deep Stop mode are o MMC o Touch screen interface o System timer o Entire wake up sources of Sleep mode Wake up sources of Deep Idle mode are o 5 1 channel 125 o Wake up source of Stop mode SAMSUNG ELECTRONICS 1 12 ex 4412 UM 1 Product Overview 1 3 Conventions 1 3 1 Register RW Conventions The application has permission to read the register field Writes to read only Head Only fields have no effect Write Only The application has permission to write in the Register field Read and Write The application has permission to read and writes in the Register field The application sets this field by writing 1 b1 and clears it by writing 170 application clears this field by writing 1 b1 A register write of 1 b0 has no aca effect on this field The application has permission to read and write in the register field The Read and Write to set application sets this field by writing 1701 A register write of 1 bO has effect on this field Read and Write to The application has permission to read and write in the register field The R WC 1 3 2 Register Value Conventions 7 Undefined but depends on the device or pin status Device dependent
195. counter value Specifies DIVCORE2 clock divider ratio when UP_CORE2_RATIO 6 4 RW ARMO or ARM1 cores are not in wait state for an interrupt or event to occur mw fm CN Specifies DIVCORE clock divider ratio when UP_CORE_RATIO 2 0 RW ARMO ARM1 cores are not in a wait state for an interrupt or event to occur SAMSUNG ELECTRONICS 5 154 ex 4412 UM 5 Clock Management Unit 5 10 1 147 L2 STATUS e Base Address 0x1004 0000 e Address Base Address 0x5400 Reset Value 0x0000_0000 Indicates L2 cache controller is in idle state 28 99 B mew vw ere GLKSTOPPED 4 mdicates 12 cache contolerisn standby mode mw tx nene ENN Read access Latency or Tag ram om rs Fena AT TAGWAITELAT R access Latency orTagRaM om Aa TE DATASETUPLAT R Sewo tatone ior baara 100 mw m E DATAREADLAT Read access Latency or Dala RAM om m ea DATAWRITELAT eo 8 write access Latency or Daanan oo 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 TAGSETUPLAT 22 20 Setup Latency for Tag RAM TAGREADLAT 18 16 SAMSUNG ELECTRONICS 5 155 en 4412 UM 5 Clock Management Unit 5 10 1 148 CPU STATUS e Base Address 0 1004 0000 e Address Base Address 0x5410 Reset Value 0x0000_0000 Returns status of the Cor
196. data as much as the size of meta data 5 After you write data as MsgLength NFECCCONF 25 16 the EncodeDone NFECCSTAT 25 is set to 1 generates the corresponding ECC codes 6 Set ECC conversion registers as inverted values of ECC codes generated To ensure ECC conversion codes work properly repeat step 3 5 After you set ECC parity conversion codes if the generated ECC parity codes are all Oxff then it is working correctly Constraints to support free page function are 1 Free page check is for only data area 512 byte 2 If there is an error during reading a page erased free page then free page engine indicates that the page is not free page 3 To detect errors on free page you should set corresponding conversion codes SAMSUNG ELECTRONICS 10 12 ex 4412 UM 10 NAND Flash Controller 10 4 12 Lock Scheme for Data Protection NFCON provides a lock scheme to protect data stored in external NAND flash memories from malicious program For this scheme the NFSBLK and NFEBLK registers are used to provide access control methods Only the memory area between NFSBLK and NFEBLK is erasable and programmable However the read access is available to entire memory area This lock scheme is only available when you enable LockTight NFCONT 17 and LOCK NFCONT 16 1 Unlock Mode In unlock mode user can access entire NAND flash memory there are no constraints to access memor
197. data in all BPP modes At 24 BPP Mode 24 bit color value 1 valid e A COLVAL Red COLVAL 23 17 Green COLVAL 15 8 Blue COLVAL 7 0 B COMPKEY Red COMPKEY 23 17 Green COMPKEY 15 8 COMPKEY 7 0 At 16 BPP 5 6 5 mode 16 bit color value is valid e A COLVAL Red COLVAL 23 19 Green COLVAL 15 10 Blue COLVAL 7 3 B COMPKEY Red COMPKEY 23 19 Green COMPKEY 15 10 COMPKEY 7 3 COMPKEY 18 16 should be 0x7 9 8 should be 0x3 COMPKEY 2 0 should be 0x7 NOTE COMPKEY register should be set properly for each BPP mode SAMSUNG ELECTRONICS 16 101 ex 4412 UM 16 Display Controller 16 5 3 46 W1KEYALPHA e Base Address 0x11C0_0000 e Address Base Address 0x0160 Reset Value 0x0000_0000 RSVD pud KEYALPHA 23 0 Specifies Key alpha value __ KEYALPHA G F 15 8 Specifies Key alpha G value KEYALPHA B F 7 0 Specifies Key alpha B value 16 5 3 47 W2KEYALPHA e Base Address 0x11C0_0000 e Address Base Address 0x0164 Reset Value 0x0000_0000 C name Jie Besriplon Reset vawe anta mesones KEYALPHA R F 1230 RW Species o KEVALPHA G F 158 RW Species G value o KEVALPHAB F 70 Species Key Bva o 16 5 3 48 W3KEYALPHA e Base Address 0x11C0_0
198. dedicated ByteEnable2 VIGEN nWBE 1 0 1 Uses UB LB XrnWBE 1 0 is dedicated nBE 1 0 Wait enable control for memory bank 2 WaitEnable2 0 Disables WAIT 1 Enables WAIT Select SROM ADDR Base for memory bank 2 0 SROM ADDR is half word base address SROM ADDR 22 0 HADDR 23 1 AddrMode2 1 SROM_ADDR is byte base address SROM ADDR 22 0 HADDR 22 0 NOTE When DataWidth2 is 0 SROM ADDR is byte base address It ignores this bit Data bus width control for memory bank 2 DataWidth2 0 8 bit 1 16 bit nWBE nBE for UB LB control for memory bank 1 0 Does not use UB LB XrnWBE 1 0 is dedicated nWBE 1 0 1 Uses UB LB XrnWBE 1 0 is dedicated nBE 1 0 WaitEnable1 Wait enable control for memory bank 1 SAMSUNG ELECTRONICS 9 6 ex ByteEnable1 4412 UM 1 DataWidthi ByteEnableO WaitEnableO AddrModeO DataWidthO SAMSUNG ELECTRONICS 9 SROM Controller 0 Disables WAIT 1 Enables WAIT Select SROM ADDR base for memory bank 1 0 SROM is half word base address SROM ADDR 22 0 HADDR 23 1 1 SROM ADDR is byte base address SROM ADDR 22 0 lt HADDR 22 0 NOTE When DataWidth1 is 0 SROM ADDR is byte base address It ignores this bit Data bus width control for memory bank 1 0 8 bit 1 16 bit nWBE nBE for UB LB control for memory bank 0 0 Does not use UB LB XrnWBE 1 0 is dedicated 1 nWBE 1 0 1 Uses UB LB
199. down mode pull up pull down 0 0000 GPD1PUDPDN 0 0004 GPD1 power down mode pull up pull down 0 0000 GPFOPUDPDN 0x0194 4 GPFO power down mode pull up pull down 0 0000 GPF1PUDPDN 0x01B4 2 GPF1 power down mode pull up pull down 0 0000 GPF2PUDPDN 0x01D4 2 GPF2 power down mode pull up pull down 0 0000 GPF3CON 0 01 0 Port group configuration register 0x0000_0000 GPF3DAT 0x01E4 Port group data register SAMSUNG ELECTRONICS 4 6 en 4412 UM 4 General Purpose Input Output GPIO Control GPF3PUD 0x01E8 Port group pull up pull down register 0 0555 GPF3DRV Ox01EC Port group drive strength control register 0x00_0000 GPF3CONPDN 0 01 0 Port group power down mode configuration register 0 0000 0x01F4 power down mode pull up pull down 050000 ETC1PUD 0x0228 Port group ETC1 pull up pull down register 0x0005 ETC1DRV 0 022 Port group ETC1 drive strength control register 0x00 0000 GPJOCON 0x0240 Port group GPJO configuration register 0x0000 0000 GPJODAT 0x0244 Port group GPJO data register 0 00 GPJOPUD 00248 Port group GPJO pull up pull down register 0x5555 GPJODRV 0x024C Port group GPJO drive strength control register 0x00_0000 GPJOCONPDN 0x0250 Port group GPJO power down mode configuration register 0x0000 GPJOPUDPDN 0x0254 2 GPJO power down mode pull up pull down 0 0000 Por group GR power dow
200. e Address Base Address 0 00 Reset Value 0x0000_0000 VIDWO3ADD1B1 e Address Base Address 0x20E8 Reset Value 0x0000 0000 VIDWO3ADD1B2 e Address Base Address Ox00FO Reset Value 0x0000 0000 VIDWO4ADD1B0 VIDWO0ADD1B0 VIDWOOADD1B1 VIDWO0ADD1B2 VIDW01ADD1B0 VIDWO1ADD1B1 VIDW01ADD1B2 VIDWO2ADD1B0 VIDWO2ADD1B1 2 a e Address Base Address 0x00F4 Reset Value 0x0000 0000 VIDWO4ADD1B1 Address Base Address 0x20F0 Reset Value 0x0000 0000 VIDWO4ADD1B2 Specifies A 31 0 of the end address for video frame buffer VBASEL F 31 0 RW VBASEL VBASEU PAGEWIDTH OFFSIZE x LINEVAL 1 SAMSUNG ELECTRONICS 16 93 IT 4412 UM 16 Display Controller 16 5 3 35 VIDWOnADD 0 to 4 Base Address 0x11C0_0000 e Address Base Address 0x0100 Reset Value 0x0000 0000 VIDWOOADD2 e Address Base Address 0x0104 Reset Value 0x0000 0000 VIDW01ADD2 e Address Base Address 0x0108 Reset Value 0x0000 0000 VIDWO2ADD2 e Address Base Address 0x010C Reset Value 0 0000 0000 VIDWOSADD2 Address Base Address 0x0110 Reset Value 0x0000_0000 VIDWO4ADD2 Specifies virtual screen offset size number of byte This value defines the difference between address of last byte which displays on the previous video line and OFFSIZE_F 25 13 RW address of first byte which will display in the new vid
201. e Base Address 0x1140_0000 e Address Base Address 0 006 Reset Value 0 00_0000 23 16 Reserved Should be zero W GPCODRV n n 2n 1 21 R 0x0000 0104 SAMSUNG ELECTRONICS 4 32 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 23 GPCOCONPDN Base Address 0x1140_0000 e Address Base Address 0x0070 Reset Value 0x0000 0x0 Outputs O 2n 1 2n 0x1 Outputs 1 GPOUIn 0104 RW 0x2 Input me 0 3 Previous state 4 3 2 24 GPCOPUDPDN Base Address 0x1140 0000 e Address Base Address 0x0074 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down 0104 RW 0x2 Reserved DE 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 33 ex 4412 UM 4 3 2 25 GPC1CON e Base Address 0x1140 0000 e Address Base Address 00080 Reset Value 0 0000 0000 GPC1CON 4 GPC1CON 3 GPC1CON 2 GPC1CON 1 GPC1CON 0 19 16 SAMSUNG ELECTRONICS 0 0 Input 0 1 Output 0 2 125 2 00 0 3 PCM 2 SOUT 0 4 126 6 SCL 0 5 SPI 2 MOSI 0x6 to OxE Reserved OxF EXT_INT5 4 0 0 Input 0 1 Output 0x2 125 2 SDI 0x3 PCM 2 SIN 0 4 2 6 SDA 0 5 SPI 2 MISO 0x6 to OxE Reserved OxF EXT_INT5 3 0 0 Input 0 1 Output 0 2 125 2 LRCK 0x3 PCM_2 FSYNC 0 4 Reserved 0 5 SPI 2 55 0x6 to OxE Reserved OxF EXT_INT5 2 0 0
202. edge 0x5 to 0 7 Reserved 85 9 fe Sets signaling method of EXT_INT8 3 0 0 Low level 0x1 High level EXT INT8 CON 3 14 12 RW 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved mw n new mw SAMSUNG ELECTRONICS 4 205 eL 4412 UM 4 General Purpose Input Output GPIO Control Sets signaling method of EXT INT8 2 0 0 Low level 0x1 High level EXT INT8 CON 2 10 8 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0x7 Reserved Sets signaling method of INT8 1 0 0 Low level 0 1 High level EXT INT8 CON 1 6 4 RW 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0x7 Reserved Sets signaling method of EXT INTS 0 0 0 Low level 0 1 High level EXT INT8 CON 0 2 0 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 206 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 127 EXT INT9CON e Base Address 0x1100 0000 e Address Base Address 0x0728 Reset Value 0x0000 0000 prea nes fo Sets signaling method of EXT_INT9 6 0x0 Low level 0x1 High level EXT INT9 CON 6 26 24 RW 0 2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both
203. edge 0x5 to 0 7 Reserved 85 9 gy eee AN Sets signaling method of EXT_INT9 5 0 0 Low level 0x1 High level EXT INT9 CON 5 22 20 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0x7 Reserved 85 0 mp fe Sets signaling method of EXT_INT9 4 0 0 Low level 0x1 High level EXT 9 CON 4 18 16 RW 0 2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved 85 0 mq Jane fe Sets signaling method of EXT INT9 3 0 0 Low level 0 1 High level EXT 9 CON 3 14 12 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0x7 Reserved 85 0 mi fasen fe Sets signaling method of EXT INT9 2 0 0 Low level 0 1 High level EXT INT9 CON 2 10 8 W 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved SAMSUNG ELECTRONICS 4 207 ex 4412 UM 4 General Purpose Input Output GPIO Control Be signaling method of EXT_INT9 1 0 0 Low level 0x1 High level EXT INT9 CON 1 6 4 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0x7 Reserved mw me mee Sets signaling method of EXT INT9 0 0 0 Low level 0x1 High level EXT INT9 CON 0 2 0 RW 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers
204. ex 4412 UM 16 Display Controller The eguation to calculate frame rate is Frame Rate 1 VSPW 1 VBPD 1 LIINEVAL 1 VFPD 1 HSPW 1 HBPD 1 HFPD 1 HOZVAL 1 x CLKVAL 1 Frequency of Clock source SAMSUNG ELECTRONICS 16 36 ex 4412 UM 16 Display Controller 16 3 6 2 180 Interface Controller VTIME 180 controls display controller for CPU style LCD Driver LDI The functions of interface controller are e Generates 180 Interface Control Signals e CPU style LDI Command Control e Timing Control for VDMA and VDPRCS 16 3 6 3 Output Control Signal Generation VTIME 180 generates SYS CS0 SYS_CS1 SYS WE and 5 5 RS control signals for Timing Diagram refer to RGB_VCLK Hz SCLK_FIMDx CLKVAL 1 where CLKVAL gt 1 where SCLK_FIMDx x 0 1 SYS 50 SYS_CS1 SYS WE and SYS RS timing parameters LCD CS SETUP LCD WR SETUP LCD WR and LCD WR HOLD are set through I80IFCONAO and I80IFCONA1 SFRs 16 3 6 4 Partial Display Control Although partial display is the main feature of CPU style LDI VTIME 180 does not support this function in hardware logic SFR setting LINEVAL HOZVAL OSD LeftTopX F OSD LeftTopY F OSD RightBotX F OSD RightBotY F PAGEWIDTH and OFFSIZE implements partial display function 16 3 6 5 LDI Command Control LDI receives both command and data Command specifies an index for selecting the SFR in LDI In control
205. fault status DMA channel register Refer to 00034 3 19 of PL330 for more information 0x9 Specifies the fault type DMA manager register Refer to 00086 page 3 20 PL330 for more information og FTCO 0x0040 Specifies the fault type for DMA channel 0 FTC1 0x0044 Specifies the fault type for DMA channel 1 FTC2 0x0048 Specifies the fault type for DMA channel 2 m FS S C M FTC3 0 004 Specifies the fault type for DMA channel 3 FTC4 0 0050 Specifies the fault type for DMA channel 4 FTC5 0x0054 Specifies the fault type for DMA channel 5 FTC7 0 005 Specifies the fault type for DMA channel 7 FTC6 0x0058 Specifies the fault type for DMA channel 6 0x0060 to 50 0 0100 Specifies the channel status for channel 0 CS1 0x0108 Specifies the channel status for DMA channel 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KO KO 0 0 SAMSUNG ELECTRONICS 8 5 4412 UM 8 Direct Memory Access Controller DMAC 5 s Register 5 5 ii S 2 3 54 5 6 7 CPC6 0x0134 Specifies the channel PC for DMA channel 6 7 0 013 Specifies the channel for channel 7 0x0140 to SA 6 0x04C0 Specifies the source address for DMA channel 6 SA_7 0x04E0 Specifies the source address for DMA channel 7 DA 0 0x0404 Specifies the destination address for DMA channel 0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0
206. format of ECC read from memory is important to compare the ECC parity code that the hardware modules generate NOTE 4 bit 8 bit 12 bit 16 bit ECC decoding scheme is different compared to 1 bit ECC NAND Flash Memory Interface saa asa 07 SAMSUNG ELECTRONICS 10 6 27 4412 UM 10 NAND Flash Controller 10 4 6 1 bit ECC Programming Guide 1 To use SLC ECC in software mode reset the ECCType to 0 enable SLC ECC ECC module generates ECC code for all Read Write data when MainECCLock NFCON 7 and SpareECCLock NFCON 6 are unlocked 0 You should reset ECC value To reset ECC value write the NFCONT 5 and InitSECC NFCON 4 bit as 1 and clear the MainECCLock NFCONTT 7 bit to 0 Unlock before Reading or Writing data MainECCLock NFCONT 7 and SpareECCLock NFCONT 6 bits control whether it generates ECC parity code or not The ECC module generates ECC parity code on register NFMECCO 1 whenever it Reads or Writes data After you complete Reading or Writing one page excluding spare area data set the MainECCLock bit to 1 Lock It locks ECC parity code and the value of the ECC status register does not change To generate spare area ECC parity code clear SpareECCLock NFCONTT 6 bit as 0 Unlock The spare area ECC module generates ECC parity code on register NFSECC whenever it Reads or Writes data After you complete Reading or Writing
207. horizontal size of display o NOTE HOZVAL Horizontal display size 1 and LINEVAL Vertical display size 1 16 5 3 8 VIDTCON3 e Base Address 0x11C0_0000 e Address Base Address 0x001C Reset Value 0x0000_0000 Enables VSYNC Signal Output 0 Disables VSYNCEN 31 RW 1 Enables VBPD VFPD VSPW 1 lt LINEVAL when VSYNCEN 1 Reserved RVD 80 ES NOTE This bit should be set to 0 EN Enables FRM signal output FRMEN 29 RW 0 Disables 1 Enables Controls polarity of FRM pulse INVFRM 28 RW 0 Active HIGH 1 Active LOW FRMVRATE 27 24 Controls FRM issue rate maximum rate up to 1 16 Rv FRMVFPD 15 8 Specifies number of line between data active and FRM signal Specifies number of line of FRM signal width FRMVSPW 7 RW 0 00 ese ew FRMVEPD 1 FRMVSPW 1 lt LINEVAL 1 in RGB SAMSUNG ELECTRONICS 16 65 ex 4412 UM 16 Display Controller 16 5 3 9 WINCONO e Base Address 0x11C0_0000 e Address Base Address 0x0020 Reset Value 0x0000_0000 Specifies Buffer Status read only NOTE BUFSTATUS BUFSTATUS H BUFSTATUS L 00 Buffer set to 0 01 Buffer set to 1 10 Buffer set to 2 Selects Buffer set NOTE BUFSEL BUFSEL H BUFSEL L 00 Buffer set to 0 01 Buffer set to 1 10 Buffer set to 2 only available where BUF MODE 1 b1 Enables CSC source limiter for clamping xvYCC source 0 Disables 1
208. indicating signal The LCD driver using 180 Interface contains a frame buffer and can self refresh so the display controller updates one still image by writing only one time to the LCD e The third type is FIFO interface with CAMIFx selected FIMDxWB DEST Bit Field on CAMERA CONTROL Register in System Register for writeback RGBe RGBb RGB 888 RGB888 YUV RGB 888 888 RGB I F i 801 F YUV4 4 4 30 bit RGB 180 Inerface Inerface 24 8 bit 8 9 16 118 24 bit WriteBack to Figure 16 3 Block Diagram of the Interface SAMSUNG ELECTRONICS 16 7 x 4412 UM 16 Display Controller 16 3 3 Overview of the Color Data The overview of the color data section describes the RGB data format and 25 BPP display of display controller 16 3 3 1 RGB Data Format The display controller requests the specified memory format of frame buffer Figure 16 4 illustrates some examples of each display mode 16 3 3 2 25 BPP Display A888 Figure 16 4 illustrates the examples of each display mode BSAP 0 HWSWP 0 WEWP 0 32 DOOH Dummy Bi Dummy Bt AEN P2 008 Dummy Bt AEN Dummy Bt AEN Dummy Bt Dummy Bt BSAP 20 HWSWP 0 WEWP 0 D B3 57 D 56 D 55 32 DE1 25 D 24 D 23 0 000H Dummy Bt AEN P1 Dummy Bt AEN P2 008H Dummy Bt AEN Dummy Bt AEN P4 ERRATA LCD Panel Figure
209. interrupt Time tick interrupt Four on chip PLLs and APLL MPLL EPLL VPLL generates ARM core and MSYS clocks generates a system bus clock and special clocks EPLL generates special clocks VPLL generates clocks for video interface Keypad 14 8 Key Matrix support Provides internal de bounce filter Timer with Pulse Width Modulation Five channel 32 bit internal timer with interrupt based operation Three channel 32 bit Timer with PWM Programmable duty cycle frequency and polarity Dead zone generation Supports external clock source Multi Core timer 64 bit global timer with four independent count comparators Two 31 bit local timers It can change interrupt interval without stopping reference tick timer DMA Micro code programming based DMA The specific instruction set provides flexibility to program DMA transfers Supports linked list DMA function Supports three enhanced built in DMA with eight channels per DMA so the total number of channels it supports are 32 Supports one Memory to memory type optimized DMA and two Peripheral to memory type optimized DMA 2 DMA supports up to 16 burst and P2M DMA supports up to 8 burst Watch Dog Timer 16 bit watch dog timer SAMSUNG ELECTRONICS 1 11 ex 4412 UM 1 Product Overview e Thermal Management Unit TMU e Power Management Clock gating control for
210. maximum lock time unconditionally before the PLL 1 locked Waiting time before locking gt the maximum locktime SAMSUNG ELECTRONICS 5 46 ex 4412 UM 5 Clock Management Unit 5 10 1 18 VPLL LOCK e Base Address 0 1003 0000 e Address Base Address 0xC020 Reset Value 000 OFFF RSVD e eee 00 Required period to generate stable clock output Set 3000 cycles x to PLL_LOCKTIME for the PLL maximum lock time PLL_LOCKTIME 15 0 RW 1 cycle 1 FREF 1 FIN PDIV The maximum PLL lock time is 250 usec where FIN 15 24 MHz 15 2 and PLL_LOCKTIME is 6000 The maximum lock time means the waiting time for locking in the worst case Therefore the user of this PLL must wait for more than the maximum lock time unconditionally before the PLL is locked Waiting time before locking gt the maximum locktime SAMSUNG ELECTRONICS 5 47 ex 4412 UM 5 Clock Management Unit 5 10 1 19 EPLL CONO e Base Address 0 1003 0000 e Address Base Address 0xC110 Reset Value 0 0060 0302 PLL Enable Control ENABLE 31 0 Disables 1 Enables Avo 99 PLL Locking Indication 0 Unlocks LOCKED 29 Ut This field is set after the locking time EPLL LOCK SFR register sets the locking time It is a Read Only register vo eee fo CTI O mw vus __ The reset value of EPLL CONO generates a 192 MHz output clo
211. mene om DIVUART2 Status DIV_UART2 0 Stable 1 Status that the divider is changing SE neem fm DIVUART1 Status DIV UART1 4 0 Stable 1 Status that the divider is changing SE Reena om DIVUARTO Status DIV UARTO 0 Stable 1 Status that the divider is changing SAMSUNG ELECTRONICS 5 102 IT 4412 UM 5 Clock Management Unit 5 10 1 84 CLK DIV STAT PERILI e Base Address 0x1003 0000 e Address Base Address 0xC654 Reset Value 0 0000 0000 RSV DIVSPI1_PRE Status DIV_SPI1_PRE 24 0 Stable 1 Status that the divider is changing Avo wei 0 DIVSPI1 Status DIV_SPI1 16 0 Stable 1 Status that the divider is changing Avo DIVSPIO PRE Status DIV SPIO PRE 8 0 Stable 1 Status that the divider is changing SE mp mw DIVSPIO Status DIV SPIO 0 Stable 1 Status that the divider is changing 5 10 1 85 CLK DIV STAT PERIL2 e Base Address 0x1003 0000 e Address Base Address 0xC658 Reset Value 0x0000 0000 RSV DIVSPI2_PRE Status DIV_SPI2_PRE 8 0 Stable 1 Status that the divider is changing ST my nese AE DIVSPI2 Status DIV SPI2 0 Stable 1 Status that the divider is changing SAMSUNG ELECTRONICS 5 103 27 4412 UM 5 Clock Management Unit 5 10 1 86 CLK_DIV_STAT_PERIL3 e Base Address 0x1003 0000 e Address Base Add
212. method of EXT_INT27 1 0x0 Low level 0x1 High level EXT_INT27_CON 1 6 4 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0 7 Reserved mw B ne 99 Sets signaling method of EXT INT27 0 0 0 Low level 0 1 High level EXT 27 CON 0 2 0 RW 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 201 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 124 EXT_INT28CON e Base Address 0x1100 0000 e Address Base Address 0x071C Reset Value 0x0000 0000 signaling method of EXT INT28 1 0x0 Low level 0 1 High level EXT INT28 CON 1 6 4 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved mw m mesen mw Sets signaling method of EXT INT28 0 0 0 Low level 0 1 High level EXT 28 CON 0 2 0 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved SAMSUNG ELECTRONICS 4 202 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 125 EXT_INT29CON e Base Address 0x1100 0000 e Address Base Address 0x0720 Reset Value 0x0000 0000 RSV Sets signaling method of EXT_INT29 7 0x0 Low level 0x1 High level EXT 29 CON 7 30 28 RW 0 2 Triggers fal
213. out condition occurs when the Rx FIFO is not empty in the FIFO mode and does not receive any data during the frame time specified in UCON SAMSUNG ELECTRONICS 13 2 ex 4412 UM 13 Universal Asynchronous Receiver and Transmitter 13 3 3 AFC UARTO and Exynos 4412 support AFC by using nRTS nCTS signals To connect UART to a Modem disable the AFC bit in UMCONn register and control the signal of nRTS by using software The UART4 supports AFC but it is dedicated for communication with GPS In AFC the nRTS signal depends on the condition of the receiver whereas the nCTS signals control the operation of transmitter The transmitter of UART transfers the data to FIFO when nCTS signals are activated In AFC nCTS signals means that other FIFO of UART 1 ready to receive data Before the UART receives data nRTS has to be activated when Rx FIFO has a spare more than 2 byte and has to be inactivated when its receive FIFO has a spare under 1 byte In AFC the nRTS signals means that its RX FIFO 1 ready to receive data Figure 13 2 illustrates the UART AFC interface Transmission case in Reception case in UART A UART A Figure 13 2 UART AFC Interface SAMSUNG ELECTRONICS 13 3 ex 4412 UM 13 Universal Asynchronous Receiver and Transmitter 13 3 4 Example of Non AFC Controlling nRTS and nCTS by Software This section includes e Rx operation with FIFO e operation with FIFO 13 3 4
214. ratio between the SCLK DMC and ACLK DMCD frequency should be 2 1 or 1 1 always Do not change this ratio during the running state of DMC You should also ensure that the ratio between the SCLK C2C and ACLK C2C frequency should be 2 1 You should not change this ratio during the running state of C2C SAMSUNG ELECTRONICS 227 4412 UM 5 Clock Management Unit The values for high performance operation are freg ARMCLK 1400 MHz at 1 3 freq ACLK_COREMO 350 MHz at 1 3 V freq ACLK_COREM1 188 MHz at 1 3 V freq PERIPHCLK 1400 MHz at 1 3 freq ATCLK 214 MHz at 1 3 V freq PCLK_DBG 107 MHz at 1 3 V freq SCLK_DMC 400 MHz at 1 0 V freq ACLK_DMCD 200 MHz at 1 0 V freq ACLK_DMCP 100 MHz at 1 0 V freq ACLK_ACP 200 MHz at 1 0 V freq PCLK_ACP 100 MHz at 1 0 V freq SCLK_C2C 400 MHz at 1 0 V freq ACLK_GDL 200 MHz at 1 0 V freq ACLK_C2C 200 MHz at 1 0 V freq ACLK_GPL 100 MHz at 1 0 V freq ACLK_GDR 200 MHz at 1 0 V freq ACLK_GPR 100 MHz at 1 0 V freq ACLK_400_MCUISP 400 MHz at 1 0 V freq ACLK_200 160 MHz at 1 0 V freq ACLK_100 100 MHz at 1 0 V freq ACLK_160 160 MHz at 1 0 V freq ACLK_133 133 MHz at 1 0 V freq SCLK_ONENAND 160 MHz at 1 0 V The PLL operations are APLL mainly drives the CPU_BLK clocks lt generates frequencies up to 1 4 GHz with a duty ratio o
215. receive an interrupt 6 2 1 Security Extensions Support 6 Interrupt Controller The ARM GIC architecture Security Extensions support e Configuring each interrupt as either Secure or Non secure e Signaling Secure interrupts to the target processor by using either the IRQ or FIQ exception request e Handling priority of secure and Non secure interrupts which is a unified scheme e Optional lockdown of the configuration of some Secure interrupts In an implementation that includes the Security Extensions e System software individually defines each implemented interrupt as either Secure or Non secure e The behavior of processor accesses to registers in the GIC depends on whether the access is Secure or Non secure When accessing GIC registers Non secure read of a register field that holds state information for a Secure interrupt returns zero GIC ignores any Non secure write to a register field that holds state information for a secure interrupt Non secure accesses can only read or set information corresponding to Non secure interrupts Secure accesses can read or set information corresponding to both Non secure and Secure interrupts e ANon secure interrupt signals an IRQ interrupt request to a target processor e Secure interrupt can signal either an IRQ or interrupt request to a target processor SAMSUNG ELECTRONICS 227 6 2 4412 UM 6 Interrupt Controller 6 2 2 Implementation Specific Co
216. register not reach the trigger level of Rx FIFO and does not whenever receive buffer becomes full receive any data during the specified time receive time out in Generated when Tx FIFO count is less than or Generated by transmit holding register Tx interrupt equal to the trigger level of transmit FIFO trigger whenever transmit buffer becomes level of Tx FIFO empty Rx interrupt Generated if frame error parity error or break Error signal are detected interrupt Generated if UART receives new data when Rx FIFO is full overrun error Generated by all errors However when another error occurs same time only one interrupt is generated SAMSUNG ELECTRONICS 13 6 ex 4412 UM 13 Universal Asynchronous Receiver and Transmitter 13 3 8 UART Error Status FIFO UART contains the error status FIFO besides the Rx FIFO register The error status FIFO indicates which data among FIFO registers receives an error An error interrupt is issued only when the data that contains an error is ready to read out To clear the error status FIFO you must read out URXHn with an error and UERSTATn For example assume that the UART Rx FIFO receives and E characters sequentially and the frame error occurs while receiving B and the parity error occurs while receiving D The actual UART receive error does not generate any error interrupt since it does not read out the character received with an erro
217. register 31 0 depends on the e fuse ROM value SAMSUNG ELECTRONICS 3 2 x 4412 UM 4 General Purpose Input Output GPIO Control General Purpose Input Output GPIO Control This chapter describes the General Purpose Input Output GPIO 4 1 Overview Exynos 4412 contains 304 multi functional input output port pins and 164 memory port pins There are 37 general port groups and two memory port groups They are GPA1 14 in out ports 3xUART with flow control UART without flow control and or 2x12C 8 in out ports 2xSPI and or 2x12C and or GPCO GPC1 10 in out ports 2xl2S and or 2xPCM and or AC97 SPDIF 2 and or SPI GPD1 8 in out ports PWM 2xl2C and or LCD GPMO GPM1 GPM2 GPM3 GPM4 35 in out ports CAM I F and or TS I F HSI and or Trace GPFO GPF1 GPF2 30 in out ports LCD GPJ1 13 in out ports CAM GPK1 GPK2 GPK3 28 in out ports 4xMMC 4 bit MMC and or 2xMMC 8 bit MMC and or GPS debugging GPLO GPL1 11 in out ports GPS GPL2 8 in out ports GPS debugging I F or Key pad GPX0 GPX1 GPX2 GPX3 32 in out ports External wake up and or Key pad NOTE These are in ALIVE region SAMSUNG ELECTRONICS 4 1 ex 4412 UM 4 General Purpose Input Output GPIO Control e GPZ 7 in out ports low Power 125 and or PCM e GPYO GPY1 GPY2 16 in out ports Control signals of EB
218. select slave indicates that the data is valid when XspiCS is set to low level KspiCS must be set low before packets are transmitted or received 15 2 1 2 FIFO Access The SPI supports CPU access and DMA access to FIFOs Data size of CPU access and DMA access to FIFOs are selected either from 8 bit 16 bit 32 bit data When it selects 8 bit data size then valid bits are from 0 to 7 bit User can define the trigger threshold to raise interrupt to CPU The trigger level of each FIFO in port 0 is set by 4 bytes step from 0 to 252 bytes and that of each FIFO in port 1 is set by 1 byte step from 0 to 63 bytes TxDMAOn or RxDMAOn bit of SPI MODE CFG register must set to use DMA access DMA access supports only single transfer and 4 burst transfer In Tx FIFO DMA request signal is high until Tx FIFO is full In Rx FIFO DMA request signal is high if FIFO is not empty 15 2 1 3 Trailing Bytes in the Rx FIFO When the number of samples in Rx FIFO is less than the threshold value in INT mode or DMA 4 burst mode and it does not receive any additional data then the remaining bytes are called trailing bytes To remove these bytes in Rx FIFO it uses internal timer and interrupt signal The value of internal timer is set up to 1024 clocks based on APB BUS clock When timer value is zero interrupt signal occurs and CPU can remove trailing bytes in FIFO 15 2 1 4 Packet Number Control SPI controls the number of packets to be received in master m
219. signal for command and data only SYS RS signal has a special function Usually SYS RS has a polarity of 1 for issuing command and vice versa Display controller has two kinds of command control e Auto command e Normal command Auto command is issued automatically that is without software control and at a pre defined rate rate 2 4 6 30 If the rate is equal to 4 then it implies that auto commands are sent to LDI at the end of every four image frames Normal command The software control issues Normal command SAMSUNG ELECTRONICS 16 37 ex 4412 UM 16 Display Controller 16 3 6 6 Interrupt Completion of one frame generates Frame Done Interrupt SAMSUNG ELECTRONICS 16 38 ex 4412 UM 16 3 7 Virtual Display 16 Display Controller Display controller supports hardware horizontal or vertical scrolling If the screen scrolls then it changes the fields of LCDBASEU and LCDBASEL Refer to Figure 16 29 but not the values of PAGEWIDTH and OFFSIZE The size of video buffer in which you store the image should be larger than the LCD panel screen size Figure 16 29 illustrates the example of scrolling in virtual display OFFSIZE PAGEWIDTH OFFSIZE is the data of li LCDBASEU LCDBASEL is the data of is the data o is the data of is the data of is the data of Figure 16 29 SAMSUNG ELECTRONICS ine 1 of virtual screen is the data of li is the data of li
220. slave Tx signal can lag if slave device 1 very far There are four types of feedback clocks which experience different path delays This register selects the feedback clock that you can use FB_CLK_SEL 1 0 RW Note that this register value is invalid when SPI operates in 0 0 slave mode 00 SPICLK bypass do not use feedback clock 01 A feedback clock with 90 degree phase lagging 10 A feedback clock with 180 degree phase lagging 11 A feedback clock with 270 degree phase lagging 90 degree phase lagging means 5 ns delay in 50 MHz operating frequency PAD Driving Strength PAD driving strength of SPI is controlled by setting drive strength control register GPIO SPI related SFR is GPBDRV for SPI port 0 and 1 and GPCDRV for SPI port 2 SAMSUNG ELECTRONICS 15 16 II 4412 UM 16 Display Controller Display Controller 16 1 Overview Display controller consists of logic for transferring image data from local bus of the camera interface controller a video buffer located in system memory to an external LCD driver interface The LCD driver interface supports three kinds of interfaces They RGB interface indirect i80 interface and YUV interface for write back display controller uses up to five overlay image windows that support various color formats 256 level alpha blending color key x y position control soft scrolling and variable window size among others Display controller suppor
221. slave devices The master Exynos 4412 initiates and terminates a data transfer over the I2C bus The 12C bus in the Exynos4412 uses a standard 2 bus arbitration procedure to realize multi master and multi slave transfer To control multi master 12C bus operations you must write values to these registers Multi master I2C bus control register I2CCON e Multi master I2C bus control status register I2CSTAT e Multi master I2C bus Tx Rx data shift register I2CDS e Multi master I2C bus address register I2CADD If the 12C bus is idle both SDA and SCL lines should be at High level A High to Low transition of SDA initiates a Start condition A Low to High transition of SDA initiates a Stop condition while SCL remains steady at High level The master device always generates Start and Stop conditions Front 7 bits address value in the data byte is transferred through SDA line after the start condition has been initiated This address value determines the slave device which the bus master device has selected The 8th bit determines the direction of the transfer Read or Write Every data byte put on the SDA line should be 8 bits in total There is no limit either to send or receive bytes during the bus transfer operation 2 master and slave devices always send the data from the Most Significant Bit MSB first and then acknowledge ACK bit immediately follows every byte SAMSUNG ELECTRONICS 14 1 ex 4412 UM 14 Inte
222. spare area set the SpareECCLock bit to 1 Lock It locks ECC parity code and it does not change the value of the ECC status register From now on you can use these values to record to the spare area or verify the bit error For example to verify the bit error of main data area on page Read operation you should move the ECC parity codes stored in spare area to NFMECCDO after it generates ECC codes for main data area From this point the NFECCERRO and NFECCERR1 have the valid error status values NOTE NFSECCD is for ECC in the spare area The main data area generates the spare area Usually the user writes the ECC value generated from main data area to spare area The value is similar to NFMECCO 1 SAMSUNG ELECTRONICS 10 7 ex 4412 UM 10 NAND Flash Controller 10 4 7 4 bit ECC Programming Guide ENCODING 1 To use 4 bit ECC in software mode set the MsgLength to 0 512 byte message length and the to 1 enable 4 bit ECC ECC module generates parity code for 512 byte read data Therefore to reset ECC value write the NFCONT 5 bit as 1 and clear the MainECCLock 7 bit to 0 Unlock before reading data MainECCLock 7 bit controls whether ECC code is generated or not Whenever it writes data the 4 bit ECC module generates ECC parity code internally After you complete writing 512 byte data excluding s
223. that it uses in B_FUNC_F RW Same as above see COEF_Q IC 154 Specifies the constant that it uses A_FUNC_F RW 9 0 Same as above see COEF Q NOTE For more information refer to Figure 16 23 Blending equation 1 Background Window 0 foreground Window 1 in Blend Equation 1 2 BPPMODE F BLD PIX ALPHA SEL at WINCONx and WxPAL at WPALCON decides the alphaA and alphaB SAMSUNG ELECTRONICS 16 125 x 4412 UM 16 Display Controller 16 5 3 81 BLENDEQ2 e Base Address 0x11C0_0000 e Address Base Address 0x0248 Reset Value 0x0000_00C2 Revo Bt22 Specifies constant that it uses in alphaB alpha value of background 1 0000 0 zero 0001 1 maximum 0010 alphaA 2 alpha value of foreground 1 0011 1 alphaA 0100 alphaB 0101 1 alphaB Q FUNC F 21 18 RW 0110 ALPHAO 0111 Reserved 100x Reserved 1010 A foreground color data 1011 1 A 1100 B background color data 1101 1 B 111x Reserved RSVD 1716 Specifies constant that it uses in alpha P_FUNC_F 15 12 RW Same as above see _ RD mo Specifies constant that it uses in B_FUNC_F RW Same as above see COEF_Q RD 164 Specifies constant that it uses in A FUNG F RW 2 0 Same as above see COEF_Q NOTE For more information Refer to Figure 16 23 Blending equation 1 Background Window 01 foreground Window 2
224. the LCD i80 interface I80IFEN 0 RW 0 Disables 1 Enables SAMSUNG ELECTRONICS 16 110 ex 4412 UM 16 Display Controller 16 5 3 60 I80IFCONBn 0 to 1 Base Address 0x11C0_0000 e Address Base Address 0x01B8 Reset Value 0x0000 0000 I80IFCONBO e Address Base Address 0x01BC Reset Value 0 0000 0000 I80IFCONB1 RSVD mal 1 Normal Command Start NORMAL CMD ST RW NOTE Auto clears after sending out one set of commands CT ee Specifies i80 Interface Output Frame Decimation Factor FRAME_SKIP 6 5 RW 00 1 Does not Skip 01 2 10 3 ew 0000 Disables auto command if you do not use any auto command then you should set AUTO CMD RATE as 0000 0001 2 AUT MD RATE RW 20 0010 per 4 Frames 0011 per 6 Frames 1111 per 30 Frames SAMSUNG ELECTRONICS 16 111 ex 4412 UM 16 Display Controller 16 5 3 61 COLORGAINCON e Base Address 0x11C0_0000 e Address Base Address 0x01C0 Reset Value 0x1004 0100 SETE METI Specifies color gain value of R data maximum 4 8 bit resolution 0h000 0 0h001 0 00390625 1 256 CG_RGAIN 29 20 RW 01002 0 0078125 2 256 OhOFF 0 99609375 255 256 0h100 1 0 Ox3FF 3 99609375 maximum Specifies color gain value of G data maximum 4 8 bit resolution 00000 0 0h001 0 00390625 1 256 CG_GGAIN 1
225. to 0 512 byte message length and the ECCType to 1 enable 4 bit ECC ECC module generates ECC parity code for 512 byte read data Therefore to reset ECC value write the NFCONT 5 bit as 1 and clear MainECCLock NFCONT 7 bit to 0 Unlock before reading data MainECCLock NFCONT 7 bit controls whether ECC code is generated or not Whenever data is read the 4 bit ECC module generates ECC parity code internally After you complete reading 512 byte excluding spare area data you should read parity codes MLC ECC module needs parity codes to detect whether error bits have occurred or not Therefore you should read ECC parity code immediately after reading 512 byte After reading ECC parity code 4 bit ECC engine starts searching for error internally 4 bit ECC error searching engine requires minimum of 155 cycles to find any error During this time you can continue reading main data from external NAND flash memory Use ECCDecDone 6 to verify whether ECC decoding is completed or not When ECCDecDone is set to 1 NFECCERRO indicates whether error bit exists or not If any error exists refer NFECCERRO 1 and NFMLCBITPT registers to fix If you have more main data to Read repeat step 1 To verify meta data error set the MsgLength to 1 24 byte message length and the ECCType to 1 Enable 4 bit ECC ECC module generates ECC parity code for 24 byte read data Th
226. to on and off then is Read and enables the video controller until the end of current frame NOTE NOTE Display On ENVID and ENVID_F are set to 1 Direct Off ENVID and ENVID_F are set to 0 simultaneously Per Frame Off ENVID_F is to 0 and ENVID is set to 1 Caution 1 If VIDCONO is set for Per Frame Off in interlace mode then the value of INTERLACE F should be set to 0 in the same time 2 f display controller is off using direct off then it is impossible to turn on the display controller without reset SAMSUNG ELECTRONICS 16 58 ex 4412 UM 16 Display Controller 16 5 3 2 VIDCON1 e Base Address 0x11C0_0000 e Address Base Address 0x0004 Reset Value 0x0000_0000 LINECNT 26 16 RW Provides status of the line counter Read only Up count from O read only to LINEVAL Specifies Field Status Read only FSTATUS 15 RW 0 Field 1 EVEN Field Specifies Vertical Status Read only 00 VSYNC VSTATUS 14 13 RW 01 BACK Porch 10 ACTIVE 11 FRONT Porch COMICO mesen oOo Specifies VCLK hold scheme at data under flow 00 VCLK hold 10 RW dais pe 01 VCLK running 11 VCLK running and disables VDEN vo W mesen 0 Controls polarity of the VCLK active edge IVCLK 7 0 Fetches video data at VCLK falling edge 1 Fetches video data at VCLK rising edge Specifies HSYNC pulse polarity IHSYNG 0 Normal 1 Inverted Specifies VSYN
227. to 7 4 3 2 158 EKT INT15 FIKPRI Base Address 0x1140 0000 e Address Base Address 0x0B4C Reset Value 0 0000 0000 Reserved 0 00000000 Interrupt number the highest priority in External Interrupt Group 9 EXT_INT15 when fixed priority 0 0 mode 0 to 7 4 3 2 159 EXT_INT16_FIXPRI e Base Address 0x1140_0000 e Address Base Address 0x0B50 Reset Value 0x0000 0000 Reserved 0x00000000 Interrupt number of the highest priority in External Interrupt Group 10 EXT_INT16 when fixed 0 0 priority mode 0 to 7 SAMSUNG ELECTRONICS 4 121 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 160 EXT_INT21_FIXPRI Base Address 0x1140_0000 e Address Base Address 0x0B54 Reset Value 0x0000 0000 Interrupt number of the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group 11 INT21 when fixed 0 0 priority mode 0 to 7 4 3 2 161 EXT_INT22_FIXPRI Base Address 0x1140_0000 e Address Base Address 0x0B58 Reset Value 0x0000 0000 Interrupt number of the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group 12 INT22 when fixed 0 0 priority mode 0 to 7 SAMSUNG ELECTRONICS 4 122 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 162 PDNEN Base Address 0x1140_0000 e Address Base Address OxOF80 Reset Value 0x00 RSV 72 0 Automatically by power down mode
228. xvYCC color space InRGB 1 Controls CSC parameter 0 Equation 601 1 Equation 709 when local SRC data has HD 709 color gamut Chooses color space conversion equation from YCbCr to RGB based on input value range 2 00 for YCbCr wide range and 2 11 for YCbCr narrow range Wide Range Y Cb Cr 255 0 Narrow Range Y 235 16 Cb Cr 240 16 Specifies Window 0 Software Trigger Update Status read only 0 Updates 1 Does not update If the Software Trigger in window 1 occurs then this bit is automatically set to 1 clears this value only after updating the shadow register sets Reserved NOTE This bit should be set to 0 Selects Data access method RW 0 Dedicated DMA 1 Local Path Specifies Buffer Status Read only NOTE BUFSTATUS BUFSTATUS H BUFSTATUS 1 Selects Buffer set nWide Narrow TRGSTATUS RSVD 24 23 ENLOCAL 22 BUFSTATUS L 21 za SAMSUNG ELECTRONICS 16 69 en 2 RW W R 4412 UM 16 Display Controller x f NOTE BUFSEL BUFSEL H BUFSEL T BUFAUTOEN 19 BITSWP_F 18 Specifies Double Buffer Auto control bit 0 Fixed by BUFSEL 1 Auto changed by Trigger Input Specifies Bit swap control bit 0 Disables swap 1 Enables swap NOTE Set it to 0 when ENLOCAL is 1 HAWSWP F 16 WSWP F 15 BUF MODE 14 0 Double 1 Indicates input color space of source image Only for EnLcal en
229. 0 Disables Timer 0 interrupt 1 Enables Timer 0 interrupt Timer 0 interrupt enable SAMSUNG ELECTRONICS 11 23 ex 4412 UM 12 Watchdog Timer Watchdog Timer 12 1 Overview Watchdog Timer WDT in Exynos 4412 15 a timing device You can use this device to resume the controller operation after malfunctioning due to noise and system errors You can use WDT as a normal 16 bit interval timer to request interrupt service WDT generates the reset signal 12 2 Features The features of WDT are e Supports normal interval timer mode with interrupt request Activates internal reset signal if the timer count value reaches 0 time out e Supports level triggered interrupt mechanism SAMSUNG ELECTRONICS 12 1 IT 4412 UM 12 Watchdog Timer 12 3 Functional Description This section includes WDT operation e WTDAT WTCNT e WDT Start e Consideration of debugging environment 12 3 1 WDT Operation WDT uses PCLK as its source clock The 8 bit Prescaler prescales the PCLK frequency to generate the corresponding WDT and it divides the resulting frequency again Interrupt gt gt gt 8 bit Prescaler WIENT Reset Signal Generator RESET gt Down Counter gt WTCON 15 8 WTCON 4 3 WTCON 2 WTCON 0 Figure 12 1 Watchdog Timer Block Diagram Figure 12 1 illustrates the functional block diagram of WDT The Watchdog Timer Control WTCON specifies the pr
230. 0 0 Input 0 1 Output GPL1CON 0 3 0 RW 0 2 GNSS SCL 0 00 0x3 to Reserved OxF EXT INT28 0 4 3 3 32 GPL1DAT Base Address 0x1100 0000 e Address Base Address 0x00E4 Reset Value 0x00 When you configure port as input port then corresponding bit is pin state When configuring as GPL1DAT 1 0 1 0 RWX output port the pin state should be same as the 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 3 33 GPL1PUD e Base Address 0x1100 0000 e Address Base Address 0x00E8 Reset Value 0x0005 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down n 0to 1 0x2 Reserved 0 3 Enables Pull up GPL1PUDIn 0x0005 SAMSUNG ELECTRONICS 4 141 x 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 34 GPL1DRV e Base Address 0x1100 0000 e Address Base Address OxOOEC Reset Value 0x00 0000 23 16 Reserved Should be zero W GPL1DRVIn 2 1 2 R 0x0000 0101 4 3 3 35 GPL1CONPDN Base Address 0x1100_0000 e Address Base Address 0x00FO0 Reset Value 0x0000 0x0 Outputs O 2n 1 2n 0x1 Outputs 1 GREIA n 0t01 FW oxo Input oe 0 3 Previous state 4 3 3 36 GPL1PUDPDN e Base Address 0x1100 0000 e Address Base Address 0x00F4 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down n 0
231. 0 0 Low level 0x1 High level EXT INT7 CON 1 6 4 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved Sets signaling method of EXT_INT7 0 0 0 Low level 0x1 High level EXT INT7 CON 0 2 0 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 70 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 88 EXT_INT13CON e Base Address 0x1140 0000 e Address Base Address 0x0730 Reset Value 0 0000 0000 RSV en Sets signaling method of EXT_INT13 7 0 0 Low level 0x1 High level EXT_INT13_CON 7 30 28 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0x7 Reserved 85 2 ns mo Sets signaling method of EXT INT13 6 0 0 Low level 0 1 High level EXT INT13 CON 6 26 24 RW 0 2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved ASVO ey Rewd Jo Sets signaling method of EXT_INT13 5 0 0 Low level 0x1 High level EXT_INT13_CON 5 22 20 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0 7 Reserved SVO nome Jo Sets signaling method of EXT INT13 4 0 0 Low level 0 1 High level EXT INT13 CON 4 18 16 RW 0 2 Triggers falling edge 0 3 Trig
232. 0 0_3400 Specifies Window 4 Palette entry 0 address Undefined 0 0_3404 Specifies Window 4 Palette entry 1 address Undefined 0x0_37FC Specifies Window 4 Palette entry 255 address Undefined SAMSUNG ELECTRONICS 16 137 ex 4412 UM 17 Keypad Interface Keypad Interface 17 1 Overview The Keypad Interface block in Exynos 4412 facilitates communication with external keypad devices The ports multiplexed with GPIO ports provide up to 14 rows and eight columns You can use keypad interface on port O or port 1 Port O and port 1 has the same function You can use any port for the GPIO connection Port O column is using alive power therefore it can use wakeup source without any setting But port 1 column is using normal power therefore it can use wakeup source with GPIO setting for retention Interrupt delivers the events of key press or key release to the CPU There are two types of scans in Keypad Interface They are Software Scan and Hardware Scan In software scan mode if one of the interrupt occurs from row lines then the software should scan the column lines using the proper procedure to detect one or multiple key press or release In hardware scan mode if you press any one of the keys then the hardware reports the row and column number of the pressed key after it scans the column line automatically Multiple key press support in hardware scan mode is limited to dual key with other row It provides interrupt statu
233. 0 4 XhsiCAWAKE 0 00 0 5 TraceData 4 0 6 to Reserved OxF EXT_INT8 5 GPMOCON 4 0 0 Input 0 1 Output 0 2 Reserved GPMOCON 3 15 12 2 _ zA PEN 0x00 0 5 TraceData 2 0 6 to Reserved OxF EXT_INT8 3 0 0 Input 0 1 Output NI2 11 8 RW GPMOCON 2 11 8 0x2 Reserved 0 3 B DATA 1 SAMSUNG ELECTRONICS 4 173 ex 0 0 Input 0 1 Output Ox2 Reserved 0x3 DATA 3 19 16 RW 0 4 TS ERROR 0 00 0x5 TraceData 3 0x6 to OxE Reserved OxF EXT INT8 4 4412 UM 4 General Purpose Input Output GPIO Control 0 4 TS_VAL 0x5 TraceData 1 0x6 to OxE Reserved OxF EXT_INT8 2 0 0 Input 0 1 Output 0x2 Reserved 0x3 CAM B DATA 0 GPMOCON 1 7 4 RW 0 4 TS SYNC 0x5 TraceData 0 0x6 to OxE Reserved OxF EXT INT8 1 0 0 Input 0 1 Output 0 2 Reserved 0 3 GPMOCON 0 3 0 RW 0 4 TS 0 5 TraceClk 0 6 to Reserved OxF EXT INT8 0 SAMSUNG ELECTRONICS 4 174 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 90 GPMODAT Base Address 0x1100 0000 e Address Base Address 0x0264 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPMODAT 7 0 7 0 output port then pin state should be same as 0 00 corresponding
234. 00 Base Address 0x1394 0000 e Address Base Address 0x0024 Reset Value 0 0 Tx underrun pending clear bit TX_UNDERRUN_CLR 0 Non Clear 1 Clears Tx overrun pending clear bit TX_OVERRUN_CLR 0 Non Clear 1 Clears Rx overrun pending clear bit RX_OVERRUN_CLR 0 Non Clear 1 Clears Trailing pending clear bit TRAILING CLR 0 Non Clear 1 Clears NOTE After error interrupt pending clear 5 controller should be reset Error interrupt list Tx underrun Tx overrun Rx underrun and Rx overrun Rx underrun pending clear bit RX_UNDERRUN_CLR 0 Non clear 1 Clears SAMSUNG ELECTRONICS 15 14 IT 4412 UM 15 Serial Peripheral Interface 15 5 1 10 SWAP_CFGn n 0 to 2 Base Address 392 0000 e Base Address 0x1393 0000 Base Address 0x1394 0000 Address Base Address 0x0028 Reset Value 0x0 1 Swap 1 Swap Swap Enable RX_SWAP_EN 0 Normal TX_HWORD_SWAP 7 EN Swap Enable 0 Normal 1 Swap NOTE Data size must be larger than swap size SAMSUNG ELECTRONICS 15 15 ex 4412 UM 15 Serial Peripheral Interface 15 5 1 11 SELn n 0 to 2 e Base Address 0x1392_0000 e Base Address 0x1393_0000 e Base Address 0x1394_0000 e Address Base Address 0x002C Reset Value 0x0 mv ea In master mode SPI uses clock which is feedback from the SPICLK The feedback clock is intended to capture safely the slave Tx signal The
235. 00 full 2 Interrupt controller has three interrupt sources related to display controller namely LCD 0 LCD 1 and LCD 2 For more information refer to Chapter 9 interrupt controller LCD 0 specifies FIFO Level interrupt LCD 1 specifies video frame synchronization interrupt and LCD 2 specifies i80 done interface interrupt SAMSUNG ELECTRONICS 16 96 ex 4412 UM 16 Display Controller 16 5 3 37 VIDINTCON1 e Base Address 0x11C0_0000 e Address Base Address 0x0134 Reset Value 0x0000_0000 Reserved REVD NOTE This bit should be set to 0 Specifies 180 done interrupt Writes 1 to clear this bit INTISOPEND 0 Does not request interrupt 1 180 done status asserts the interrupt request 1 Frame synchronization status asserts the interrupt request Specifies FIFO Level interrupt Writes 1 to clear this bit 0 Does not request interrupt 1 FIFO empty status asserts the interrupt request Specifies frame synchronization interrupt Writes 1 to clear this bit 0 Does not request interrupt 16 5 3 38 W1KEYCONO e Base Address 0x11C0_0000 e Address Base Address 0x0140 Reset Value 0x0000_0000 Description Reset Value Enables blending 0 Disables blending 1 Enables blending using original alpha for non key area and KEY_ALPHA for key area Enables Disables Color Key Chroma key 0 Disables color key 1 Enables color key COLVAL then it displays the pixel fro
236. 00 DIV STAT 0x8A08 to RSVD OxCOOF Reserved Undefined EPLL LOCK 0xC010 Controls PLL locking period for EPLL 0x0000 OFFF 0xC014 to VPLL LOCK 0xC020 Controls PLL locking period for VPLL 0x0000 OFFF 0xC024 to 0xC12C to CLK_SRC_TOP0 0xC210 Selects clock source for CMU_TOP0 0 0000_0000 CLK SRC 1 0xC214 Selects clock source for CMU TOP1 0x0000_0000 0xC218 to CLK SRC MAUDIO 0 0000 0005 0xC244 to SAMSUNG ELECTRONICS 5 27 4412 UM 5 Clock Management Unit CLK SRC PERILO 0x0001 1111 SRC PERIL1 00111 0055 0xC25C to CLK_SRC_MASK_CAMO 0xC320 Clock source mask for CAM_BLK 0x1111_1111 CLK_SRC_MASK_TV 0xC324 Clock source mask for TV_BLK 0x0000_0111 0xC328 to SRC MASK LCD 0x0000 1111 SRC MASK ISP 0x0000 1111 SRC MASK MAUDIO 0x0000 0001 SRC MASK FSYS 0x0101 1111 CLK SRC MASK PERILO 0x0001 1111 SRC MASK PERIL1 0x0111 0111 0xC358 to CLK_MUX_STAT_TOPO 0xC410 Clock MUX status for CMU_TOP Ox1111 1111 CLK_MUX_STAT_TOP1 0xC414 Clock MUX status for CMU_TOP 0x0111 1110 0xC418 to CLK_MUX_STAT_MFC 0xC428 Clock status for 0x0000_0111 CLK_MUX_STAT_G3D 0xC42C Clock MUX status for G3D_BLK 0x0000_0111 0xC430 to CLK MUX STAT CAM1 0xC458 Clock MUX status for CAM_BLK 0x0000_0111 0xC45C to CLK DIV TOP 0xC510 Sets clock divider ratio for CMU_TOP 0x0000_0000 0xC514 to SAMSUNG ELECTRONICS 5 28
237. 000 e Address Base Address 0x0168 Reset Value 0x0000_0000 RSVD fo KEYALPHA R F 23 0 Specifies Key alpha value KEYALPHA G F 15 8 Specifies Key alpha G value EE NN KEYALPHA B F 7 0 Specifies Key alpha B value 0 SAMSUNG ELECTRONICS 16 102 27 4412 UM 16 Display Controller 16 5 3 49 WAKEYALPHA e Base Address 0x11C0_0000 e Address Base Address 0x016C Reset Value 0x0000_0000 RSVD 31 14 KEYALPHA R F 23 0 Specifies Key alpha value __ KEYALPHA G F 15 8 Specifies Key alpha G value w x KEYALPHA_B_F 7 0 Specifies Key alpha value 16 5 3 50 DITHMODE e Base Address 0x11C0_0000 e Address Base Address 0x0170 Reset Value 0x0000_0000 RSVD 7 BW Does not use for normal access writing not zero values to these registers results in abnormal behavior Controls Red Dither bit 00 8 bit RDithPos 6 5 01 6 bit 10 5 bit Controls Green Dither bit 00 8 bit GDithPos 4 3 01 6 bit 10 5 bit Controls Blue Dither bit 00 8 bit BDithPos 2 1 RW 01 6 bit 10 5 bit Enables Dithering bit DITHEN F RW 0 Disables dithering 1 Enables dithering SAMSUNG ELECTRONICS 16 103 x 4412 UM 16 Display Controller 16 5 3 51 WINOMAP e Base Address 0x11C0_0000 e Address Base Address 0x0180 Reset Value 0x0000_0000 Specifies color mapping of w
238. 0000 Filter Enable for EXT INT4 4 FLTEN4 4 7 RW Disables filter 0 1 Enables filter FLTWIDTH4 4 6 0 RW Filtering width of EXT_INT4 4 SAMSUNG ELECTRONICS 4 87 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 102 EXT_INT5_FLTCONO e Base Address 0x1140_0000 e Address Base Address 0x0820 Reset Value 0x0000_0000 Filter Enable for EXT INT5 3 FLTEN5 S 31 RW 0 0 Disables filter 0x1 Enables filter FLTWIDTH5 3 30 24 Filtering width of EXT_INT5 3 Filter Enable for EXT_INT5 2 FLTEN5 2 23 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH5 2 22 16 Filtering width of EXT_INT5 2 Filter Enable for EXT INT5 1 FLTEN5 1 15 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH5 1 14 8 Filtering width of EXT_INT5 1 Filter Enable for EXT INT5 0 FLTEN5 O 7 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH5 0 6 0 RW Filtering width of EXT 5 0 4 3 2 103 EXT_INT5_FLTCON1 Base Address 0x1140_0000 e Address Base Address 0x0824 Reset Value 0x0000_0000 Filter Enable for EXT_INT5 4 FLTEN5 4 7 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH5 4 60 RW Filtering width of EXT_INT5 4 SAMSUNG ELECTRONICS 4 88 en 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 104 6 0 e Base Address 0x1140 0000 e Address Base Addr
239. 0000_00FF 0 0 Enables interrupt EXT 21 MASK 7 7 Ox1 Masked 0 1 0 0 Enables interrupt EXT INT21 MASK 6 6 0 1 Masked 0 1 0 0 Enables interrupt EXT 21 MASK 5 5 0 1 Masked 0 1 EXT_INT21_MASK 4 4 a EXT INT21 MASK 3 3 EXT INT21 MASK 2 2 21 EXT INT21 MASK 1 EXT INT21 Lo s m 4 3 2 132 EXT 22 MASK e Base Address 0x1140 0000 e Address Base Address 0x0944 Reset Value 0x0000 001F 0 0 Enables interrupt EXT INT22 MASK 4 4 0 1 Masked 0 1 0 0 Enables interrupt EXT INT22 MASK 3 3 0 1 Masked 0 1 0 0 Enables interrupt EXT INT22 MASK 2 2 0 1 Masked 0 1 0 0 Enables interrupt 0 0 Enables interrupt SAMSUNG ELECTRONICS 4 108 en 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 133 EXT_INT1_PEND e Base Address 0x1140_0000 e Address Base Address 0x0A00 Reset Value 0x0000 0000 EXT INT1 PEND 7 7 RWX 0 0 Not occur 0 1 Interrupt occurs EXT INT1 PEND 6 6 RWX 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs EXT INT1 PEND 4 4 RWX 0x0 Not occur Ox1 Interrupt occurs 0 0 0 0 0 0 EXT INT1 0 0 0 0 0 0 0 EXT INT1 PEND 5 5 0 1 Interrupt occurs EXT INT1 PEND 2 2 0X0 Not occur Ox1 Interrupt occurs EXT INT1 PEND 1 1 RWX 0 0 Not occu
240. 001 FINPLL MPLL SEL 14 12 5 l 010 MOUTMPLLFOUT 1xx Status that the mux is changing Selection signal status of MUXDMCO 001 SCLKMPLL DPHY_SEL 10 S nee 010 SCLKAPLL 1xx Status that the mux is changing Selection signal status of MUXDMC_BUS DMC_BUS_SEL 6 4 _ dr 1xx Status that the mux is changing Selection signal status of MUXC2C 001 SCLKMPLL 2 SEL 2 0 E 2 0 010 SCLKAPLL 1 Status that the is changing SAMSUNG ELECTRONICS 5 127 x 4412 UM 5 Clock Management Unit 5 10 1 110 CLK DIV DMCO e Base Address 0 1004 0000 e Address Base Address 0 0500 Reset Value 0x0000_0000 are reer DIVCK133 Clock Divider Ratio 220 ACLK DMCP ACLK DMCD DMCP RATIO 1 99 DIVDMCD Clock Divider Ratio 18 16 ACLK_DMCD DOUTDMC DMCD_ RATIO 1 SE mew fo DIVDMC Clock Divider Ratio 14 12 DOUTDMC MOUTDMC_BUS DMC_RATIO 1 Avo DIVDPHY Clock Divider Ratio ud 12 SCLK_DPHY MOUTDPHY DPHY_RATIO 1 DIVACP Clock Divider Ratio PCLK ACLK_ACP ACP_PCLK_RATIO 1 RSVD O Reseved me Clock Divider Ratio AGP RATIO ACLK_ACP MOUTDMC_BUS ACP_RATIO 1 SAMSUNG ELECTRONICS 5 128 IT 4412 UM 5 Clock Management Unit 5 10 1 111 CLK_DIV_DMC1 e Base Address 0x1004 0000 e Address Base Address 0x0504 Reset Va
241. 01 DATA 31 28 15 12 data in word boundary only when BPPMODE_F 4 b1110 Enables disables video output and logic immediately 0 Disables the video output and video control signal 1 Enables the video output and video control signal 1010 Unpacked 19 BPP non palletized A 1 R 6 G 6 B 6 1011 Unpacked 24 BPP non palletized R 8 G 8 B 8 1100 Unpacked 24 BPP non palletized A 1 R 8 G 8 B 7 1101 Unpacked 25 BPP non palletized A 1 R 8 G 8 B 8 1110 Unpacked 13 BPP non palletized A 1 R 4 G 4 B 4 1111 Unpacked 15 BPP non palletized R 5 G 5 B 5 NOTE 1 1101 Supports unpacked 32 BPP non palletized A 8 R 8 G 8 B 8 for per pixel blending 2 1110 Supports 16 BPP non palletized A 4 R 4 G 4 B 4 for per pixel blending 16 level blending t 16 68 ex 4412 UM 16 Display Controller 16 5 3 10 WINCON1 e Base Address 0x11C0_0000 e Address Base Address 0x0024 Reset Value 0 0000 0000 Specifies Buffer Status read only 00 Buffer set to 0 BUFSTATUS_H 31 RW 01 Buffer set to 1 10 Buffer set to 2 BUFSEL_H 30 NOTE BUFSTATUS BUFSTATUS BUFSTATUS L Select Buffer set LIMIT ON EQ709 00 Buffer set to 0 01 Buffer set to 1 10 Buffer set to 2 only available when BUF MODE 1 b1 NOTE BUFSEL BUFSEL BUFSEL_L Enables Control CSC source limiter for clamping xvYCG source 0 Disables 1 Enables when local SRC data has
242. 01002 2 OFFSET OUT RW OhOFF 255 01100 256 Ox1FF 1 NOTE Generally HUE OFFSET IN 128 and HUE OFFSET OUT 128 Example 16 6 Hue Equation Cb hue CBGO Cb OFFSET IN CBG1 Cr OFFSET IN OFFSET OUT Cr lt hue gt CRGO Cb OFFSET IN CRGl Cr OFFSET IN OFFSET OUT Example 16 7 Coefficient Decision CBGO P CBGO_N CBG1 P CBG1_N CRGO P CRGO CRG1 P CRG1_N gt gt gt gt SAMSUNG ELECTRONICS 16 119 x 4412 UM 16 Display Controller 16 5 3 70 VIDWOALPHAO e Base Address 0x11C0_0000 e Address Base Address 0x021C Reset Value 0x0000_0000 RSV o o ALPHAO F 23 16 Specifies Red Alpha value case AEN 0 ALPHAO G F 15 8 Specifies Green Alpha value case 0 ALPHAO_B_F 7 0 Specifies Blue Alpha value case 0 16 5 3 71 VIDWOALPHA1 e Base Address 0x11C0_0000 e Address Base Address 0x0220 Reset Value 0x0000_0000 BR Twe Description Reset Value mo 23 10 RW Species Red Apna valu caso AEN 0 GF H58 RW Species Green Alpha vale case 1 o BF 170 RW Species Bue Aipha vale ase AEN c 0 16 5 3 72 VIDW1ALPHAO e Base Address 0x11C0_0000 e Address Base Address 0x0224 Reset Value 0x0000_0000 B amp Twe Besciion Reset Value Sv ft Reema
243. 0B14 External interrupt 30 fixed priority control register 0x0000 0000 SAMSUNG ELECTRONICS 4 19 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 Part 1 For the following SFRs Sets the value does not take effect immediately lt takes at least 800 APB clocks for the value to take effect after the SFR is actually changed The SFRs are GPAOPUD GPAODRV GPA1PUD GPA1DRV GPBPUD GPBDRV GPCOPUD GPCODRV GPC1PUD GPC1DRV GPDOPUD GPDODRV GPD1PUD GPD1DRV GPFOPUD GPFODRV GPF1PUD GPF1DRV GPF2PUD GPF2DRV GPF3PUD GPF3DRV GPJOPUD GPJODRV GPJ1PUD GPJ1DRV SAMSUNG ELECTRONICS 4 20 ex 4412 UM 4 3 2 1 GPAOCON e Base Address 0x1140 0000 e Address Base Address 00000 Reset Value 0 0000 0000 GPAOCON 7 GPAOCON 6 5 GPAOCON 4 B SAMSUNG ELECTRONICS 0 0 Input 0 1 Output 0 2 UART 1 RTSn 0x3 126 2 SCL 0 4 to Reserved OxF EXT_INT1 7 0 0 Input 0 1 Output 0 2 UART_1_CTSn 0x3 126 2 SDA 0 4 to Reserved OxF EXT_INT1 6 0 0 Input 0 1 Output 0 2 UART_1_TXD 0x3 to Reserved OxF EXT_INT1 5 0 0 Input 0 1 Output 0 2 UART_1_RXD 0x3 to Reserved OxF EXT_INT1 4 0 0 Input 0 1 Output 0 2 UART 0 RTSn 0x3 to Reserved OxF EXT_INT1 3 0 0 Input 0 1 Output 0 2 UART 0 CTSn 0x3 to Reserved OxF EXT_INT1 2
244. 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down GPX1PUDIn 0107 RW 0x2 Reserved 0x5555 0x3 Enables Pull up 4 3 3 201 GPX1DRV e Base Address 0x1100_0000 e Address Base Address 0x0C2C Reset Value 0x00_0000 23 16 Reserved Should be zero W GPX1DRVIn 2n 1 2n N oto7 P 0 0000 SAMSUNG ELECTRONICS 4 257 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 202 GPX2CON Base Address 0x1100 0000 e Address Base Address 0x0C40 Reset Value 0x0000 0000 0 0 Input 0 1 Output 0 2 Reserved GPX2CON 7 31 28 Mis z 0x00 0 5 ALV DBG 19 0x6 to OxE Reserved WAKEUP INT2 7 0 0 Input 0 1 Output 0 2 Reserved 2 27 24 ee 0 00 0 5 ALV DBG 18 0 6 to Reserved OxF WAKEUP_INT2 6 0 0 Input 0 1 Output 0 2 Reserved GPX2CON 5 23 20 Ne 0 00 0 5 ALV DBG 17 0 6 to Reserved OxF WAKEUP_INT2 5 0 0 Input 0 1 Output 0 2 Reserved GPX2CONI4 19 16 ke 0 00 0 5 ALV DBG 16 0x6 to Reserved OxF WAKEUP_INT2 4 0 0 Input 0 1 Output 0 2 Reserved GPX2CON 3 15 12 E 0x00 0 5 ALV DBG 15 0x6 to OxE Reserved WAKEUP_INT2 3 0x0 Input GPX2CON 2 11 8 ud 0x00 0x3 ROW 2 SAMSUNG ELECTRONICS 4 258 ex 4412 UM 4 General Purpose Input Output GPIO Control
245. 0x0000 0000 0x0000 0000 EXT INT33 CON 0 070 External interrupt EXT INT33 configuration register 0x0000 0000 EXT INT34 CON 0x0710 External interrupt EXT INT34 configuration register EXT INT31 FLTCONO 0x0808 External interrupt EXT INT31 filter configuration register 0 0x0000 0000 EXT INT31 FLTCON 1 0x080C External interrupt EXT INT31 filter configuration register 1 0x0000 0000 EXT INT32 FLTCONO 0x0810 External interrupt EXT INT32 filter configuration register 0 0x0000 0000 EXT INT32 FLTCON 1 0x0814 External interrupt EXT INT32 filter configuration register 1 0x0000 0000 EXT 0 FLTCONO 0x0800 External interrupt EXT INT30 filter configuration register O 0x0000 0000 EXT INT33 FLTCONO 0x0818 External interrupt EXT INT33 filter configuration register O 0x0000 0000 EXT 0 FLTCON1 0x0804 External interrupt EXT INT30 filter configuration register 1 0x0000 0000 SAMSUNG ELECTRONICS 4 18 4412 UM 4 General Purpose Input Output GPIO Control 0x0000_0000 0x0000_0000 0x0000_0000 EXT_INT34_PEND Ox0A10 External interrupt EXT_INT34 pending register 0 0000_0000 0x0B08 Current service register EXT_INT_SERVICE _ _ OxOBOC Current service pending register P 0x0B10 External interrupt group fixed priority control register 0x0000 0000 EXT INT33 PEND OxOAOC External interrupt EXT INT33 pending register 0x0000 0000 EXT INT30 FIXPRI 0x
246. 0x0000 0000 KEYPAD input release interrupt rising edge status read and clear write Read 0 Does not occur PONT 29 16 RW 1 Released interrupt occurs 1450 Write Clears released interrupt when write 1 The R_INT 13 0 indicates that each key pressed from 0 to 13 has a dedicated interrupt from R_INT 16 to R_INT 29 KEYPAD input press interrupt falling edge status read and clear write Read D n r P_INT 13 0 RW 2 occurs 14 b0 Write Clears pressed interrupt when write 1 The P_INT 13 0 indicate that each key released from 0 to 13 has a dedicated interrupt from P INT 0 to P INT 13 NOTE Clears keypad wakeup interrupt when the write access to the KEYIFSTSCLR 17 8 1 3 KEYIFCOL e Base Address 0x100A 0000 e Address Base Address 0x0008 Reset Value 0x0000_FFOO KEYPAD interface column data output tri state enable register Each bit is for each KEYIFCOL bit KEYIFCOLEN 15 8 0 Enables output pad tri state buffer Normal output KEY 801111 1111 enable 1 Disables output pad Tri state buffer High Z output KEY disable KEYIFCOL 7 0 KEYPAD interface column data output register 800 SAMSUNG ELECTRONICS 17 14 ex 4412 UM 17 Keypad Interface 17 8 1 4 KEYIFROW Base Address 0x100A 0000 e Address Base Address 0x000C Reset Value Reflects input ports RSVD 31 14 _ Reserved 4 KEYPAD interface row data input register read only Reflects input
247. 0x0A34 Reset Value 0x0000 0000 RSVD EXT INT12 PEND 7 EXT INT12 PEND 6 EXT INT12 PEND 5 EXT INT12 PEND 4 EXT INT12 PEND 3 EXT INT12 PEND 2 EXT INT12 PEND 1 EXT INT12 PEND 0 5 4 3 RWX 2 RWX 1 SAMSUNG ELECTRONICS 4 General Purpose Input Output GPIO Control 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 4 245 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 179 EXT_INT_SERVICE_XA e Base Address 0x1100 0000 e Address Base Address 0x0B08 Reset Value 0x0000 0000 EXT INT Service group number 0 1 EXT INT23 0 2 EXT INT24 0x3 EXT INT25 0 4 EXT INT26 0 5 EXT INT27 SVC Group Num 7 3 RW 0x6 EXT INT28 0 00 0 7 INT29 0 8 EXT_INT8 0 9 INT9 EXT_INT10 OxB EXT INT11 0 EXT INT12 SVC Num 2 0 Interrupt number to be serviced 4 3 3 180 EXT INT SERVICE PEND XA e Base Address 0x1100 0000 e Address Base Address Reset Value 0x0000 0000 SVC 7 0 R 0 0 Not occur 0 00 0 1 Interrupt occurs SAMSUNG ELECTRONICS 4 246 II 4412 U
248. 0x11C0_0000 e Address Base Address 0x0154 Reset Value 0 0000 0000 COLVAL_F 23 0 Specifies color key value for transparent pixel effect SAMSUNG ELECTRONICS 16 99 x 4412 UM 16 Display Controller 16 5 3 44 W4KEYCONO e Base Address 0x11C0_0000 e Address Base Address 0x0158 Reset Value 0x0000_0000 Enables blending 0 Disables blending KEYBLEN_F 2 RW 26 1 Enables blending using original alpha for non key area and KEY_ALPHA for key area Enables color Key Chroma key KEYEN_F 25 RW 0 Disables color key 1 Enables color key Controls color key Chroma key direction 0 If the pixel value matches foreground image with COLVAL then it displays the pixel from background image DIRCON_F 24 RW only in OSD area 1 If the pixel value matches background image with COLVAL then it displays the pixel from foreground image only in OSD area Each bit corresponds to COLVAL 23 0 If some position bit is set then it disables the COLVAL position bit NOTE Set BLD PIX 1 ALPHA SEL 0 A FUNC 0x2 and B FUNC 0x3 to enable alpha blending using color key SAMSUNG ELECTRONICS 16 100 IT 4412 UM 16 Display Controller 16 5 3 45 W4KEYCON1 e Base Address 0x11C0_0000 e Address Base Address 0x015C Reset Value 0 0000 0000 COLVAL_F 23 0 Specifies color key value for transparent pixel effect 8 NOTE Both COLVAL and COMPKEY use 24 bit color
249. 0x4 Reserved 0x5 ALV_DBG 14 0 6 to Reserved WAKEUP_INT2 2 0 0 Input 0 1 Output 0x2 Reserved 0x3 KP ROW 1 GPX2CON 1 7 4 RW 0 4 Reserved 0 5 ALV DBG 13 0x6 to OxE Reserved OxF WAKEUP_INT2 1 0 0 Input 0 1 Output 0x2 Reserved 0x3 KP ROW 0 GPX2CON 0 3 0 RW 0 4 Reserved 0 5 ALV_DBG 12 0x6 to 0xE Reserved WAKEUP_INT2 0 SAMSUNG ELECTRONICS 4 259 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 203 GPX2DAT e Base Address 0x1100 0000 e Address Base Address 0x0C44 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPX2DAT 7 0 7 0 output port then pin state should be same as 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 3 204 GPX2PUD Base Address 0x1100 0000 e Address Base Address 0x0C48 Reset Value 0x5555 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down GPX2PUDIn 0107 RW 0x2 Reserved 0x5555 0x3 Enables Pull up 4 3 3 205 GPX2DRV e Base Address 0x1100_0000 e Address Base Address 0x0C4C Reset Value 0x00_0000 23 16 Reserved Should be zero W GPX2DRV n 2n 1 2n 0107 0x0000 SAMSUNG ELECTRONICS 4 260 ex 4412 UM 4 General Purpose Input Output GPIO Control 4
250. 0x4100 Reset Value 0x0064_0300 PLL Enable Control ENABLE 31 RW 0 Disables 1 Enables S mw PLL Locking Indication 0 Unlocks 1 Locks If ENABLE LOCK DET 0 then this field is set to 1 after the locking time The lock time is set using LOCKED E the APLL LOCK SFR register If ENABLE LOCK DET 1 then this field is set when the hardware lock detector meets the PLL locking condition This bit is Read only Sw mp ena _ 99 Monitors Frequency Select Pin FSEL 27 RWX 0 Frer 1 Fvco our Fvco vw pa fo a Jf o mw ma new ov The reset value of APLL_CONO generates an 800 MHz output clock for an input clock frequency of 24 MHz The equation to calculate the output frequency is FOUT x FIN PDIV x 2597 FOUT should fall in the range of 21 9 MHz lt FOUT lt 1400 MHz The conditions MDIV PDIV SDIV for APLL and MPLL should meet are e 1 lt lt 63 e 64 lt lt 1023 e SDIV 0 lt SDIV lt 5 e Fref FIN PDIV Fref should fall in the range of 2 MHz lt Fref lt 12 MHz e x FEn PDIV Fyco should fall in the range 700 MHz lt Fyco lt 1400 MHz SAMSUNG ELECTRONICS 5 141 ex 4412 UM 5 Clock Management Unit Refer to the section 5 4 1 Recommended PLL PMS Value for APLL and MPLL for recommended PMS values SAMSUNG ELECTRONICS 5 142 IT
251. 1 Enables Normal Command 10 Enables Auto Command 11 Enables Normal and Auto Command Controls command 11 00 Disables 01 Enables Normal Command 10 Enables Auto Command 11 Enables Normal and Auto Command 16 113 7 4412 UM CMD3 EN CMD2 CMD1_EN CMDO_EN SAMSUNG ELECTRONICS 16 Display Controller Controls command 11 00 Disables 01 Enables Normal Command 10 Enables Auto Command 11 Enables Normal and Auto Command Controls command 11 00 Disables 01 Enables Normal Command 10 Enables Auto Command 11 Normal and Auto Command Enable Controls command 11 00 Disables 01 Enables Normal Command 10 Enables Auto Command 11 Enables Normal and Auto Command Controls command 11 00 Disables 01 Enables Normal Command 10 Enables Auto Command 11 Enables Normal and Auto Command 16 114 4412 UM 16 Display Controller 16 5 3 63 LDI CMDCON1 e Base Address 0x11C0_0000 e Address Base Address 0x01D4 Reset Value 0x0000 0000 ame Bk Tve Description Reset Vate ou Rea _ ovon as RW Contos Command o 9 AS Command 10 J o 4 RW Command ovos AS RW Command m Fw owe 16 OmmCommdeRS o ovos AS RW Command SAS omoa AS
252. 1 Status that the divider is changing RSV eq fm DIVGDL Status DIV GDL 0 0 Stable 1 Status that the divider is changing SAMSUNG ELECTRONICS 5 36 ex 4412 UM 5 Clock Management Unit 5 10 1 5 CLK GATE LEFTBUS e Base Address 0x1003 0000 e Address Base Address 0x4800 Reset Value 0xFFFF_FFFF Gating all clocks for ASYNC_G3D CLK_ASYNC_G3D 6 RW 0 Mask 1 Pass sv B feme SSCS Gating all clocks for ASYNC_MFCL CLK_ASYNC_MFCL 4 RW 0 Mask 1 Pass mv a feme _ Gating all clocks for PPMULEFT CLK PPMULEFT 1 RW 0 Mask 1 Pass Gating all clocks for GPIO LEFT CLK GPIO LEFT 0 RW 0 Mask 1 Pass Gating all clocks for ASYNC_TVX CLK_ASYNC_TVX 3 RW 0 Mask 0 1 1 Pass SAMSUNG ELECTRONICS 5 37 ex 4412 UM 5 Clock Management Unit 5 10 1 6 CLK GATE IP IMAGE e Base Address 0x1003 0000 e Address Base Address 04930 Reset Value OxFFFF_FFFF Gating all clocks for PPMUIMAGE CLK PPMUIMAGE RW 0 Mask 1 Pass RSVD m ne Gating all clocks for SMMUMDMA CLK_SMMUMDMA 5 RW 0 Mask 1 Pass mw ____ Gating all clocks for CLK MDMA 2 RW 0 Mask 1 Pass Gating all clocks for ROTATOR CLK_ROTATOR 1 RW 0 Mask 1 Pass m eee SSS Gating all clocks for SMMUROTATOR CLK_SMMUROTATOR 4 RW 0 Mask 0 1 1 Pass SAMSUNG ELECTRONICS 5 38 ex
253. 1 30 V The Cortex A9 MPCore operates at 200 MHz to 1 4 GHz and CoreSight Clock is up to 200 MHz The CMU in CPU block CMU CPU generates all the necessary clocks for IPs CPU block It also generates certain control signals for Cortex A9 MPCore e DMC block consists of the DRAM memory controller DMC Security sub system SSS and Generic Interrupt Controller GIC CMU in DMC block CMU_DMC generates 400 MHz DRAM clock 200 MHz AXI bus clock which is synchronized with the DRAM clock and 100 MHz clock for register accesses It also generates 200 MHz clock for Accelerator Coherency Port ACP bus which is used for memory coherency checking and connects CPU and SSS bus masters e The LEFTBUS and RIGHTBUS blocks contain the global data buses that are clocked at 200 MHz The global data buses transfer data between the DRAM and various sub blocks It also contains global peripheral buses that are clocked at 100 MHz You can use 100 MHz clock for register accesses e CMU_TOP generates clocks for all the remaining function blocks which include G3D MFC LCDO ISP CAM TV FSYS MFC GPS MAUDIO PERIL and PERIR It generates bus clocks that operate at 400 200 160 133 100 MHz It also generates various special clocks to operate IPs in Exynos 4412 e Additionally asynchronous bus bridges are inserted between two different function blocks SAMSUNG ELECTRONICS 5 1 ex 4412 UM 5 Clock Management Unit Table 5 1 describes the typi
254. 1 Rx Operation with FIFO 1 Select the transmit mode either interrupt or DMA mode 2 Verify the value of Rx FIFO count in the register When the value is less than 16 set the value of UMCONn 0 to 1 activate nRTS However when the value equal to or larger than 16 set the value to 0 inactivate nRTS 3 Repeat the Step 2 to receive next data 13 3 4 2 Tx Operation with FIFO 1 Select the transmit mode either interrupt or DMA mode 2 Verify the value of UMSTATn 0 When the value is 1 activate NCTS Write data to Tx FIFO register 3 Repeat the Step 2 to send next data 13 3 5 Trigger Level of Tx Rx FIFO and DMA Burst Size in DMA Mode DMA transaction starts when Tx Rx data reaches the trigger level of Tx Rx FIFO of UFCONn register mode single transaction transfers data whose size is specified as the burst size of UCONn register The DMA transactions are repeated until Tx Rx FIFO count is less than the DMA burst size Thus DMA burst size should be less than or equal to the trigger level of Tx Rx FIFO In general ensure that the trigger level of Tx Rx FIFO and DMA burst size matches 13 3 6 RS 232C Interface To connect UART to the modem interface instead of null modem nRTS nCTS nDSR nDTR DCD and nRI signals are required You can control these signals with general I O ports by using software as the AFC does support the RS 232C interface SAMSUNG ELECTRONICS 13 4
255. 13 5 illustrates the serial frame timing diagram Normal UART 4 amp SIO Frame Start Data Bits Figure 13 5 Serial Frame Timing Diagram Normal UART SAMSUNG ELECTRONICS 13 8 ex 4412 UM 13 Universal Asynchronous Receiver and Transmitter Figure 13 6 illustrates the infra red transmit mode frame timing diagram IR Trans mit Frame gt Start Data Bits gt Stop t Bit Bit lt Pulse Width 3 16 Bit Frame Figure 13 6 Infra Red Transmit Mode Frame Timing Diagram Figure 13 7 illustrates the infra red receive mode frame timing diagram lt gt Start Data Bits h Stop 4 Figure 13 7 Infra Red Receive Mode Frame Timing Diagram SAMSUNG ELECTRONICS 13 9 ex 4412 UM 13 Universal Asynchronous Receiver and Transmitter 13 4 UART Input Clock Description Figure 13 8 illustrates the input clock diagram for UART System Controller XusbXTI gt MUXuarTo 4 SCLK_HDMI27M __ gt SCLK_USBPHYO _ gt SCLK_USBPHY1 ___ gt SCLK UART SCLK HDMIPHY gt MOUTUARTo 3 SCLKv 5 gt UBRDIVn Figure 13 8 Input Clock Diagram for UART Exynos 4412 provides UART with a variety of clocks Figure 13 8 illustrates that UART uses SCLK_UART clock whi
256. 1393 0000 Base Address 0x1394_0000 Address Base Address 0x0008 Reset Value 0x0 RSVD ey 00 Byte 01 Halfword CH WIDTH 30 29 RW 10 Word 11 Reserved Count value from writing the last data in Rx FIFO to TRANG GNT Ge flush trailing bytes in FIFO 00 01 Halfword BUS WIDTH 18 17 RW 10 Word 11 Reserved Rx FIFO trigger level in INT mode Port 0 Trigger level bytes 4 RX_RDY_LVL 16 11 RW Port 1 2 Trigger level bytes value of RX_RDY_LVL field Tx FIFO trigger level in INT mode Port 0 Trigger level bytes 4 TX_RDY_LVL 10 5 RW B m Port 1 2 Trigger level bytes value of TK LVL field mode enable disable SW 2 RW 0 Disables DMA Mode 1 Enables DMA Mode Tx DMA mode enable disable TX_DMA_SW 1 RW 0 Disables DMA Mode 1 Enables DMA Mode DMA transfer type single or 4 bursts 0 Single _ 1 4 burst transfer size must be set as the same size in SPI DMA NOTE 1 CH WIDTH is shift register width 2 BUS WIDTH is SPI FIFO width transfer data size should be aligned with BUS WIDTH For example Tx Rx data size must be aligned with 4 bytes if BUS WIDTH is word 3 CH WIDTH must be smaller than BUS WIDTH or similar to BUS WIDTH SAMSUNG ELECTRONICS 15 9 ex 4412 UM 15 Serial Peripheral Interface
257. 15 5 1 3 CS REGn n 0 to 2 Base Address 0x1392 0000 e Base Address 0x1393 0000 Base Address 0x1394 0000 e Address Base Address 0 000 Reset Value 0 1 RSVD NSSOUT inactive time NES TIME COUNT 2 nCS time count 3 2 SPICLKout RSVD RW RW Mee MESA Chip select toggle manual or auto selection AUTO_N_MANUAL 1 0 Manual 1 Auto Slave selection signal manual only NSSOUT RW 0 Active 1 1 Inactive When AUTO MANUAL is set then SPI controller controls NSSOUT and does not perform data transfer continuously Unit data size depends on CH_WIDTH Figure 15 3 illustrates auto chip select mode waveform SPICLK MOS MSB 6 5 4 2 1 LSB MSB 6 5 4 2 Its mso MSB 6 5 2 LB MB 6 5 2 1 LSB MSB NSSOUT lt 5 TIME COUNT Figure 15 3 Auto Chip Select Mode Waveform CPOL 0 0 CH_WIDTH Byte SAMSUNG ELECTRONICS 15 10 ex 4412 UM 15 Serial Peripheral Interface 15 5 1 4 SPI ENn n 0 to 2 Base Address 0x1392_0000 e Base Address 0x1393 0000 Base Address 0x1394 0000 e Address Base Address 0 0010 Reset Value 0 0 RSVD sur Interrupt Enable for trailing count to be 0 0 Disables 1 Enables INT EN TRAILING
258. 15 CLK GATE DMC1 e Base Address 0x1004 0000 e Address Base Address 0x0904 Reset Value OxFFFF_FFFF Gating all clocks for TZASC_LR CLK_TZASC_LR 0 Mask 1 Pass Gating all clocks for TZASC_LW CLK_TZASC_LW 0 Mask 1 Pass Gating all clocks for TZASC_RR CLK_TZASC_RR 0 Mask 0 1 1 Pass Gating all clocks for 7 5 RW CLK TZASC RW 0 Mask 0 1 1 Pass SAMSUNG ELECTRONICS 5 134 IT 4412 UM 5 Clock Management Unit 5 10 1 116 CLKOUT CMU DMC e Base Address 0x1004 0000 e Address Base Address 0x0A00 Reset Value 0x0001_0000 RSVD oven meme Enable CLKOUT ENB_CLKOUT 16 0 Disables 1 Enables RSVD 15 14 Reewed Divide Ratio DIV_RATIO 13 8 _ Divide ratio DIV_RATIO 1 MUX 00000 DMCD 00001 ACLK_DMCP 00010 ACLK ACP 00011 PCLK ACP 00100 SCLK_DMC X_SEL 4 0 0 MIKS 4 0 00101 SCLK DPHY 00110 MPLL FOUT 2 00111 SCLK PWI 01000 Reserved 01001 SCLK C2C 01010 ACLK C2C 5 10 1 117 CLKOUT CMU DMC DIV STAT e Base Address 0x1004 0000 e Address Base Address 0x0A04 Reset Value 0x0000 0000 ASV Exe DIVCLKOUT Status DIV STAT 0 Stable 0 0 1 Status that the divider is changing SAMSUNG ELECTRONICS 5 135 ex 4412 UM 5 Clock Management Unit 5 10 1 118 DCGIDK MAPO Base Address 0 1 DCGIDK MAPO 004 0000 Address Base Address 0x1000 Res
259. 16 Display Controller 16 3 3 2 4 19 BPP Display A666 Figure 16 8 illustrates the 19 BPP display BSWP 0 HWSWP 0 WSWP 0 D 63 51 D 50 D 49 32 D 31 19 D 17 0 000H Dummy Bit AEN 1 Dummy Bit P2 008H Dummy Bit AEN P3 Dummy Bit P4 010H Dummy Bit AEN P5 Dummy Bit P6 BSWP 0 HWSWP 0 WSWP 1 D 63 51 D 50 D 49 32 D 31 19 D 17 0 000H Dummy Bit AEN P2 Dummy Bit 1 008H Dummy Bit AEN P4 Dummy Bit P3 010H Dummy Bit AEN P6 Dummy Bit P5 Pa P LCD Panel Figure 16 8 Memory Format of 19 BPP A666 Display NOTE 1 Specifies the transparency value selection bit 0 Selects ALPHAO 1 Selects ALPHA1 When it sets per pixel blending then this pixel blends with alpha value that selects SFR selects the alpha value as ALPHAO_R ALPHAO_G ALPHA1_R ALPHA1_G and ALPHA1_B For more information refer to the section on SFR 2 D 17 12 Red data D 11 6 Green data and 0 5 0 Blue data SAMSUNG ELECTRONICS 16 12 x 4412 UM 16 Display Controller 16 3 3 2 5 18 BPP Display 666 Figure 16 9 illustrates the 18 BPP display BSWP 0 HWSWP 0 WSWP 0 D 63 50 D 49 32 D 31 18 D 17 0 000H Dummy Bit P1 Dummy Bit P2 008H Dummy Bit P3 Dummy Bit P4 010H Dummy Bit P5 Dummy Bit P6 BSWP 0 HWSWP 0 WSWP 1
260. 2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 292 ex 4412 UM 4 General Purpose Input Output GPIO Control MES signaling method of EXT_INT50 1 0 0 Low level 0x1 High level EXT INT50 CON 1 6 4 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0x5 to 0 7 Reserved B new vo Sets signaling method of EXT INT50 0 0x0 Low level 0 1 High level EXT INT50 CON 0 2 0 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0x5 to 0 7 Reserved SAMSUNG ELECTRONICS 4 293 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 4 8 EXT_INT50_FLTCONO e Base Address 0 0386 0000 e Address Base Address 0x0800 Reset Value 0x0000_0000 Filter Enable for EXT INT50 3 FLTEN1 3 31 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH1 3 30 24 Filtering width of EXT INT50 3 Filter Enable for EXT INT50 2 FLTEN1 2 23 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH1 2 22 16 Filtering width of 50121 Filter Enable for EXT INT50 1 FLTEN1 1 15 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH1 1 14 8 Filtering width of EXT INT50 1 Filter Enable for EXT INT50 0 1 0 7 RW Disables Filter 0 1 Enables Filter FLTWIDTH1 0 6 0
261. 2C Reset Value Undefined Dosoripion Reset value Svo _______ 27 Masked interrupt pending status EE If the corresponding interrupt enable bit is 0 the _ IA A 0 The interrupt is not pending OR 1 The interrupt is pending _ PEREV 4 R DMCO PEREV 2 Masked interrupt pending status PEREV A 20 2 enable bit is 0 the HEDER ADC 0 The interrupt is pending s 2CACHE 1 The interrupt is pending AUDIO 0 sv Bena Pemu d MEN PPMU MFC Mo iS R Masked interrupt pending status A PPMUSD If the corresponding interrupt enable bit is 0 the PPMU TV f IMSR bit reads as o De FILE D Mo 0 The interrupt is not pending ee i 1 The interrupt is pending PPU sem B 8 Pwuicp a PPMUMAGEMO m P PPMU CAMF MO D RIGHT Mo 5 Masked interrupt pending status E ow 4 D LEFT 4 n enable bit is 0 the PPMU ACPO MO B R 0 The interrupt is nel pending CE St 2 1 The interrupt is pending R A
262. 3 111 2 Channel 4 SAMSUNG ELECTRONICS 16 83 Selects Channel 1 s channel 001 Window 0 CH1FISEL 21 19 i 010 110 Window 3 111 Window 4 ex 4412 UM 16 Display Controller Selects Window 2 s channel 001 Channel 0 010 Channel 1 W2FISEL 8 6 RW 101 Channel 110 Channel 3 111 Channel 4 Selects Window 1 5 channel 001 Channel 0 010 Channel 1 W1FISEL 5 3 RW 101 Channel 010 110 Channel 3 111 Channel 4 Selects Window 0 s channel 001 Channel 0 010 Channel 1 WOFISEL 2 0 ee 001 110 Channel 3 111 Channel 4 SAMSUNG ELECTRONICS 16 84 IT 4412 UM 16 Display Controller 16 5 3 16 VIDOSDOA e Base Address 0x11C0_0000 e Address Base Address 0x0040 Reset Value 0 0000 0000 OSD LeftTopX F 21 11 RW Specifies the horizontal screen coordinate for left top pixel of OSD image Specifies the vertical screen coordinate for left top pixel of OSD image OSD LeftTopY F 10 0 interlace TV output this value should be set to half of the original screen y coordinate The original screen y coordinate should be even 16 5 3 17 VIDOSDOB e Base Address 0x11C0_0000 e Address Base Address 0x0044 Reset Value 0x0000_0000 OSD RightBotX F 21 11 Specifies horizontal screen coordinate for right bottom pixel of OSD image Specifies vertical screen coordinate for right bottom pixel of OSD image
263. 3 0000 Base Address 0x1384 0000 e Address Base Address 0x0030 Reset 0x0000 0000 Reeva po MODEM Generates modem interrupt TKD Generates transmit interrupt ERROR Generates error interrupt fo s Generates receive interrupt Interrupt pending contains the information of the generated interrupts If one of the 4 bits is logical high 1 each UART channel generates interrupt NOTE You must clear this in the interrupt service routine after clearing interrupt pending in Interrupt Controller INTC Clear specific bits of UINTP by writing 1 s to the bits that you want to clear 13 6 1 14 UINTSPn 0 to 4 e Base Address 0x1380 0000 Base Address 0x1381 0000 Base Address 0x1382 0000 e Base Address 0x1383 0000 Base Address 0x1384 0000 e Address Base Address 0x0034 Reset 0x0000 0000 mp Reeva MODEM Generates modem interrupt TKD Generates transmit interrupt ERROR Generates error interrupt fo s Generates receive interrupt o NOTE Interrupt Source Pending contains the information of the generated interrupt regardless of the value of Interrupt Mask SAMSUNG ELECTRONICS 13 29 ex 4412 UM 13 Universal Asynchronous Receiver and Transmitter 13 6 1 15 UINTMn 0 to 4 e Base Address 0x1380 0000 Base Address 0x1381 0000 e Base Addres
264. 3 3 206 GPX3CON Base Address 0x1100_0000 e Address Base Address 0 0 60 Reset Value 0 0000 0000 0 0 Input 0 1 Output 0 2 Reserved GPX3CON 7 31 28 5 5 Ajer 0x00 0 5 ALV_DBG 27 0x6 to OxE Reserved OxF WAKEUP_INT3 7 0 0 Input 0 1 Output 0 2 Reserved GPX3CON 6 27 24 ot 0x00 0 5 ALV DBG 26 0x6 to OxE Reserved WAKEUP INT3 6 0 0 Input 0 1 Output 0 2 Reserved GPX3CONIE 23 20 MES 3 0x00 0 5 ALV DBG 25 0x6 to OxE Reserved OxF WAKEUP_INT3 5 0 0 Input 0 1 Output 0 2 Reserved GPX3CON 4 19 16 _ 2 0 00 0 5 ALV DBG 24 0 6 to Reserved OxF WAKEUP_INT3 4 0 0 Input 0 1 Output 0 2 Reserved GPX3CON 3 15 12 0 00 0 5 ALV_DBG 23 0 6 to Reserved WAKEUP_INT3 3 0x0 Input GPX3CON 2 11 8 d E 0x00 0x3 KP ROW 10 SAMSUNG ELECTRONICS 4 261 ex 4412 UM 4 General Purpose Input Output GPIO Control 0x4 Reserved 0x5 ALV_DBG 22 0 6 to Reserved OxF WAKEUP_INT3 2 0 0 Input 0 1 Output 0x2 Reserved 0x3 KP ROW 9 GPXSCON 1 7 4 RW 0 4 Reserved 0 5 ALV DBG 21 0x6 to OxE Reserved OxF WAKEUP INT3 1 0 0 Input 0 1 Output 0x2 Reserved 0x3 KP ROW 8 GPX3CON 0 3 0 RW 0 4 Reserved 0 5 ALV_DBG 20 0x6 to OxE Reserved OxF WAKEUP_INT3 0 SAMSUNG EL
265. 4 XhsiACDATA 0 5 to Reserved OxF 0 0 Input 0 1 Output 0 2 EBI_ADDR 12 0 3 Reserved 0 4 XhsiACWAKE 0 5 to Reserved 0 0 Input 0 1 Output 0 2 EBI_ADDR 11 0 3 Reserved 0 4 XhsiACREADY 0 5 to Reserved 0 0 Input 0 1 Output 0 2 EBI ADDR 10 0 3 Reserved 0 4 KhsiCAFLAG 0 5 to Reserved OxF 0 0 Input 0 1 Ouiput 4 160 4 General Purpose Input Output GPIO Control 4412 UM 4 General Purpose Input Output GPIO Control 0 2 EBI_ADDR 9 0 3 Reserved 0 4 XhsiCADATA 0 5 to Reserved 0 0 Input 0 1 Output 0 2 EBI_ADDR 8 0x3 Reserved 0 4 XhsiCAWAKE 0 5 to Reserved SAMSUNG ELECTRONICS 4 161 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 68 GPY4DAT e Base Address 0x1100 0000 e Address Base Address 0x01A4 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPY4DAT 7 0 7 0 output port then pin state should be same as 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 3 69 GPY4PUD e Base Address 0x1100 0000 e Address Base Address 0x01A8 Reset Value 0x5555 0x0 Disables Pull up Pull down 2n 1 2n 0 1
266. 4 325 II 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 43 EXT_INT31_FLTCON1 Base Address Ox106E 0000 e Address Base Address 0x080C Reset Value 0x0000 0000 Filter Enable for EXT INT31 7 FLTEN2 7 31 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH2 7 30 24 Filtering width of EXT_INT31 7 Filter Enable for EXT_INT31 6 FLTEN2 6 23 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH2 6 22 16 Filtering width of EXT_INT31 6 Filter Enable for EXT_INT31 5 FLTEN2 5 15 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH2 5 14 8 Filtering width of EXT INT31 5 Filter Enable for EXT INT31 4 FLTEN2 4 7 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH2 4J 1601 RW Filtering width of EXT INT31 4 SAMSUNG ELECTRONICS 4 326 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 44 EXT_INT32_FLTCONO Base Address Ox106E 0000 e Address Base Address 0x0810 Reset Value 0x0000 0000 Filter Enable for EXT INT32 3 FLTENS S 31 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH3 3 30 24 Filtering width of EXT INT32 3 Filter Enable for EXT INT32 2 FLTEN3 2 23 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH3 2 22 16 Filtering width of EXT_INT32 2 Filter Enable for EXT_INT32 1 FLTENS 1 15 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH3 1 14 8 Filterin
267. 4 General Purpose Input Output GPIO Control 4 3 3 55 GPY2CON e Base Address 0x1100 0000 e Address Base Address 0x0160 Reset Value 0x0000 0000 0 0 Input 0 1 Output GPY2CON 5 23 20 RW 0 2 RnB 3 0 00 0x3 to Reserved 0 0 Input 0 1 Output 0 2 NF RnB 2 0x3 Reserved GPY2CON 4 19 16 RW Reserved 0x00 0x5 OND_RPn 0x6 to 0xE Reserved 0 0 Input 0 1 Output 0 2 NF RnB 1 0x3 Reserved GPY2CON S 15 12 RW Gude Reserved 0x00 0 5 OND INT 1 0x6 to OxE Reserved OxF 0 0 Input 0 1 Output 0 2 RnB 0 0 3 Reserved GPY2CON 2 11 8 RW Ox4 Reserved 0x00 0x5 INT 0 0x6 to OxE Reserved 0 0 Input 0 1 Output 0 2 ALE 0x3 Reserved GPY2CON 1 7 4 RW 0 4 Reserved 0x00 0x5 OND_SMCLK 0x6 to 0xE Reserved OxF 0x0 Input 0x1 Output 0 2 NF_CLE GPY2CON 0 3 0 RW 0x3 Reserved 0 4 Reserved 0x5 OND ADDRVALID 0x6 to OxE Reserved SAMSUNG ELECTRONICS 4 153 ex 4412 UM 4 General Purpose Input Output GPIO Control SAMSUNG ELECTRONICS 4 154 en 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 56 GPY2DAT e Base Address 0x1100 0000 e Address Base Address 0x0164 Reset Value 0x00 RWX When you configure port as input port the corresponding bit is the pin state When configuring GPY2DA
268. 4412 UM 13 Universal Asynchronous Receiver and Transmitter Universal Asynchronous Receiver and Transmitter 13 1 Overview A Universal Asynchronous Receiver and Transmitter UART in Exynos 4412 provide four independent channels with asynchronous and serial input output I O ports for general purpose to 3 It also provides a dedicated channel for communication with Global Positioning System GPS Ch4 All the ports operate either in an interrupt based or a DMA based mode UART generates either an interrupt or a DMA request to transfer data to and from CPU and UART UART supports bit rates up to 4 Mbps Each UART channel contains two First In First Outs FIFOs to receive and transmit data as in 256 bytes in e 64 bytes in Ch1 and Ch4 16 bytes in Ch2 and Ch3 UART includes e Programmable Baud rates e Infrared IR transmitter receiver e One or two stop bit insertion e 5 bit 6 bit 7 bit or 8 bit data width and parity checking As shown in Figure 13 1 each UART contains e Baud rate generator e Transmitter e Receiver e Control unit The Baud rate generator uses SCLK_UART The transmitter and the receiver contain FIFOs and data shifters The data to be transmitted 1 written to Tx FIFO and copied to the transmit shifter The data is then shifted out by the transmit data pin TxDn The received data is shifted from the receive data pin RxDn and copied to Rx FIFO from the shifter SAMSUNG ELECTRON
269. 5 Shadow Windows Control 16 5 5 1 SHD VIDWOnADDO n 0 to 4 Base Address 0x11C0_0000 e Address Base Address 0x40A0 Reset Value 0x0000 0000 SHD_VIDWOO0ADDO e Address Base Address 0x40A8 Reset Value 0x0000 0000 SHD_VIDW01ADD0 e Address Base Address 0x40B0 Reset Value 0x0000_0000 SHD_VIDWO2ADDO e Address Base Address 0x40B8 Reset Value 0x0000 0000 SHD_VIDWO3ADDO e Address Base Address 0 40 0 Reset Value 0x0000 0000 SHD_VIDWO4ADDO VBASEU F 31 0 Specifies A 31 0 of the start address for video frame buffer shadow 16 5 5 2 SHD_VIDWOnADD1 n 0 to 4 e Base Address 0x11C0_0000 e Address Base Address 0x40D0 Reset Value 0x0000 0000 SHD VIDWOOADD1 e Address Base Address 0x40D8 Reset Value 0x0000 0000 SHD VIDWO1ADD1 e Address Base Address 0x40E0 Reset Value 0x0000 0000 SHD VIDWO2ADD 1 e Address Base Address 0x40E8 Reset Value 0x0000 0000 SHD_VIDWO3ADD1 e Address Base Address 0x40F0 Reset Value 0x0000 0000 SHD VIDWO4ADD1 VBASEL F 31 0 EM uds A 31 0 of the end address for video buffer 0 0 SAMSUNG ELECTRONICS 16 134 ex 4412 UM 16 Display Controller 16 5 5 3 SHD_VIDWOnADD2 n 0 to 4 Base Address 0x11C0_0000 e Address Base Address 0x4100 Reset Value 0x0000_0000 SHD_VIDWOOADD2 e Address Base Address 0x4104 Reset Value 0x0000 0000 SHD_VIDW01ADD2 e Address Base Address 0x4108 Reset Val
270. 6 5 3 25 VIDOSD2C e Base Address 0x11C0_0000 e Address Base Address 0x0068 Reset Value 0x0000_0000 __ Tyre Desoiption Reset Value Sv ft 23 20 Specifies the Red Alpha upper value case AEN 0 NE NN 19 16 Specifies the Green Alpha upper value case AEN 0 15 12 Specifies the Blue Alpha upper value case 0 Specifies the Red Alpha upper value case 1 Specifies the Green Alpha upper value case 1 __ __ ALPHA B H F 3 0 Specifies the Blue Alpha upper value case AEN 1 NOTE For more information refer to VIDW2ALPHAQ 1 register SAMSUNG ELECTRONICS 16 88 ex 4412 UM 16 Display Controller 16 5 3 26 VIDOSD2D e Base Address 0x11C0_0000 e Address Base Address 0x006C Reset Value 0x0000 0000 RW Reserved SEYA NOTE This bit should 0 EN Specifies Window Size DSIZE 23 EVI For example Height x Width Number of Word 16 5 3 27 VIDOSD3A e Base Address 0x11C0_0000 e Address Base Address 0x0070 Reset Value 0x0000_0000 RW RW OSD LeftTopX F 21 11 screen coordinate for left top pixel Specifies Vertical screen coordinate for left top pixel of 050 image OSD LeftTopY F 10 0 For interlace TV output this value should be set to half of the original screen y coordinate The original screen y coordinate should be even value
271. 7 EXT 42 PEND 6 EXT 42 PEND 5 EXT INT42 PEND 4 EXT INT42 EXT_INT42_PEND 2 EXT INT42 PEND 1 EXT INT42 PEND 0 5 4 8 RWX 2 RWX 1 SAMSUNG ELECTRONICS 4 General Purpose Input Output GPIO Control 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 4 286 4412 UM 4 3 3 229 EKT INT43 PEND e Base Address 0x1100 0000 e Address Base Address 0x0F4G Reset Value 0x0000 0000 RSVD EXT INT43 PEND 7 EXT PEND 6 EXT PEND 5 EXT INT43 PEND 4 EXT INT43 EXT INT43 PEND 2 EXT INT43 PEND 1 EXT INT43 PEND 0 5 4 3 RWX 2 RWX 1 SAMSUNG ELECTRONICS 4 General Purpose Input Output GPIO Control 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 4 287 4412 UM 4 General Purpose Input Outpu
272. 7 Reserved 85 9 nome AI Sets signaling method of INT16 4 0x0 Low level 0x1 High level EXT_INT16_CON 4 18 16 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0 7 Reserved 85 0 mw Sets signaling method of EXT INT16 3 0 0 Low level 0 1 High level EXT INT16 CON 3 14 12 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved 85 0 mi mw Sets signaling method of EXT INT16 2 0 0 Low level 0 1 High level EXT INT16 CON 2 10 8 RW 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0x7 Reserved Sets signaling method of EXT INT16 1 0 0 Low level 0 1 High level EXT INT16 CON 1 6 4 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 77 ex 4412 UM 4 General Purpose Input Output GPIO Control Sets signaling method of EXT INT16 0 0 0 Low level 0x1 High level EXT INT16 CON 0 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0 7 Reserved SAMSUNG ELECTRONICS 4 78 II 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 92 EXT_INT21CON e Base Address 0x1140_0000 e Address Base Address 0x0740 Reset Value 0 0000 0000
273. 8 0x3 to Reserved OxF EXT_INT31 0 SAMSUNG ELECTRONICS 4 301 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 8 GPV1DAT Base Address Ox106E 0000 e Address Base Address 0x0024 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPV1DAT 7 0 7 0 output port then pin state should be same as 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 5 9 GPV1PUD Base Address 0x106E_0000 e Address Base Address 0x0028 Reset Value 0x5555 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down GPV1PUDIn n201o7 RW 0x2 Reserved 0x5555 0x3 Enables Pull up 4 3 5 10 GPV1DRV e Base Address 0x106E_0000 e Address Base Address 0x002C Reset Value 0x00_ 0000 23 16 Reserved Should be zero W GPV1DRVin n 2n 1 2 0x0000 0107 SAMSUNG ELECTRONICS 4 302 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 11 GPV1CONPDN Base Address Ox106E 0000 e Address Base Address 0x0030 Reset 0x0000 0x0 Outputs 0 2n 1 2n 0 1 Outputs 1 0107 RW 0 2 Input 999 0 3 Previous state 4 3 5 12 GPV1PUDPDN Base Address 0x106E_0000 e Address Base Address 0x0034 Reset Value 0x0000 0 0 Disables Pull up Pull down 2n 1 20 0 1
274. 8 A 27 A 26 A 25 A 24 A 23 22 A 21 A 20 A 19 A 18 17 16 fr re m os Jo fo re es o er 1 A 15 A 14 A 13 12 A 11 A 10 9 8 A 7 A 6 A 5 A S A 2 A O LCD Panel 16BPP 5 5 5 1 Format Non Palette 31 30 29 A 28 A 27 A 26 A 25 A 24 A 23 A 22 A 21 A 20 A 19 A 18 17 16 m m m To To es To er To s e e e To A 15 14 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 4 A S A 2 Ali A 0 LCD Panel 16BPP 5 6 5 Format Non Palette Figure 16 13 16 5 6 5 Display Types SAMSUNG ELECTRONICS 16 17 ex 4412 UM 16 3 3 2 9 13 BPP Display A444 Figure 16 14 illustrates the13 BPP display BYSWP 0 HWSWP 0 WSWP 0 16 Display Controller D 63 61 D 60 D 59 48 D 43 32 D 27 16 01513 000H Dummy AEN1 P1 P2 P3 Dummy 004H Dummy AEN5 5 P6 P7 Dummy 008H Dummy AEN9 P9 Dummy BYSWP 0 HWSWP 1 WSWP 0 D 63 61 D 60 D 59 48 D 43 32 D 27 16 D 1513 D 11 0 000H Dummy AEN4 P4 P3 P2 Dummy P1 004H Dummy AEN8 P8 P7 P6 Dummy P5 008H Dummy AEN12 12 Dummy P9 NOTE Figure 16 14 LCD Panel Memory
275. 8 ex 4412 UM 16 Display Controller trigger 0 Does not reguest 1 Reguests 1 Clear Condition Read or New Frame Start 2 Only when TRGMODE is to 1 Enables 80 start trigger 2 1 RW 1 Software Triggering Command write only B NOTE Only when TRGMODE is set to 1 Enables i80 start trigger TRGMODE 180 RW 0 Disables i80 Software Trigger 1 Enables i80 Software Trigger NOTE Generates two continuous software trigger inputs in some video clocks VCLK recognizes as one SAMSUNG ELECTRONICS 16 109 IT 4412 UM 16 Display Controller 16 5 3 59 I80IFCONAn 0 to 1 Base Address 0x11C0_0000 e Address Base Address 0 0180 Reset Value 0x0000 0000 I80IFCONAO e Address Base Address 0x01B4 Reset Value 0x0000 0000 I80IFCONA1 RSVD mosen 00000001090 LCD_CS_SETUP 19 16 RW Specifies number of clock cycles for the active period of address signal enable to chip select enable LCD_WR_SETUP 15 12 RW Specifies number of clock cycles for the active period of CS signal enable to write signal enable LCD WR ACT 11 8 RW Specifies number of clock cycles for the active period of chip select enable LCD WR HOLD 7 4 Specifies number of clock cycles for the active period of chip select disable to write signal disable RSVD PM Reserved Specifies polarity of RS Signal RSPOL 2 RW 0 Low 1 High vo fm meme Controls
276. 9 1 Address 0x1100 0000 e Address Base Address 0x0844 Reset Value 0x0000 0000 Filter Enable for EXT_INT29 7 FLTEN9 7 31 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH9 7 30 24 Filtering width of EXT_INT29 7 Filter Enable for EXT_INT29 6 FLTEN9 6 23 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH9 6 22 16 Filtering width of EXT INT29 6 Filter Enable for EXT INT29 5 FLTEN9 5 15 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH9 5 14 8 Filtering width of EXT_INT29 5 Filter Enable for EXT_INT29 4 FLTEN9 4 7 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH9 4 6 0 Filtering width of EXT INT29 4 SAMSUNG ELECTRONICS 4 221 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 145 EXT INT8 FLTCONO Base Address 0x1100 0000 e Address Base Address 0x0848 Reset Value 0x0000 0000 Filter Enable for EXT INT8 3 FLTEN10 3 31 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH10 3 30 24 Filtering width of EXT INT8 3 Filter Enable for EXT INT8 2 FLTEN10 2 23 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH10 2 22 16 Filtering width of EXT INT8 2 Filter Enable for EXT INT8 1 FLTEN10 1 15 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH10 1 14 8 Filtering width of EXT INT8 1 Filter Enable for EXT INT8 0 FLTEN10 0 7 RW 0x0 Disables
277. 9 10 0h002 0 0078125 2 256 0x100 OhOFF 0 99609375 255 256 0h100 1 0 Ox3FF 3 99609375 maximum Specifies color gain value of B data maximum 4 8 bit resolution 00000 0 0h001 0 00390625 1 256 CG_BGAIN 0h002 0 0078125 2 256 0x100 OhOFF 0 99609375 255 256 0h100 1 0 Ox3FF 3 99609375 maximum SAMSUNG ELECTRONICS 16 112 x 4412 UM 16 5 3 62 LDI CMDCONO e Base Address 0x11C0 0000 e Address Base Address 0x01D0 Reset Value 0x0000 0000 RSVD 31 24 an SAMSUNG ELECTRONICS RW RW RW RW RW RW RW W 16 Display Controller Reserved __ Controls command 11 00 Disables 01 Enables Normal Command 10 Enables Auto Command 11 Enables Normal and Auto Command Controls command 11 00 Disables 01 Enables Normal Command 10 Enables Auto Command 11 Enables Normal and Auto Command Controls command 11 00 Disables 01 Enables Normal Command 10 Enables Auto Command 11 Enables Normal and Auto Command Controls command 11 00 Disables 01 Enables Normal Command 10 Enables Auto Command 11 Enables Normal and Auto Command Controls command 11 00 Disables 01 Enables Normal Command 10 Enables Auto Command 11 Enables Normal and Auto Command Controls command 11 00 Disables 01 Enables Normal Command 10 Enables Auto Command 11 Enables Normal and Auto Command Controls command 11 00 Disables 0
278. Base Address 0x00A0 Reset Value 0x0000 0000 NFECCPRGECC4 e Address Base Address 0x00A4 Reset Value 0x0000 0000 NFECCPRGECC5 e Address Base Address 0x00A8 Reset Value 0x0000 0000 NFECCPRGECC6 th h h lt Bit 4 3 274 1 Parity 8 Parity 7 Parity 8 check parity generated from main area 0x00 6 Parity 15 8 5 Parity i 10 15 8 7 0 16 31 24 R p EN EN O R EM 10 check parity generated from main area 0x00 OR 15 2316 R LR R NNI EN R Er R MN NN 13 Parity i i 19 Parity 18 17 24 Parity i 23 Parity i i RSVD 26 Parity i 25 Parity 26 check parity generated from main area 0 00 5 check parity generated from main area 0 00 th th th 13 check parity generated from main area 0 00 20 parity generated from main area 0 00 th th rd NIN N 25 check parity generated from main area 0 00 SAMSUNG ELECTRONICS 10 31 4412 UM 10 NAND Flash Controller NOTE The NAND flash controller generates these ECC parity codes when write main area data while the MainECCLock NFCON 7 bit is 0 unlock SAMSUNG ELECTRONICS 10 32 ex
279. Base Address 0x01E8 Reset Value 0 2222 SYS_RDATA 23 0 Controls 180 System Interface Read Data 16 5 3 67 HUECOEF_CR_n n 1 to 4 Base Address 0x11C0_0000 e Address Base Address 0x01EC Reset Value 0100 0100 HUECOEF_CR_1 e Address Base Address 0x01F0 Reset Value 0x0000 0000 HUECOEF_CR_2 e Address Base Address 0x01F4 Reset Value 0x0000_0000 HUECOEF_CR_3 e Address Base Address 0x01F8 Reset Value 0x0100_0100 HUECOEF_CR_4 mw Specifies Hue matrix coefficient 00 when cb In_offset is positive Signed 00000 0 01001 0 00390625 1 256 01002 0 0078125 2 256 CRGO x 25 16 RW OhOFF 0 99609375 255 256 0h100 1 0 256 256 0h300 1 0 256 256 0h301 0 99609375 255 256 Oh3FF 0 00390625 1 256 0h101 to 2FF Reserved do not use Svo mem po Specifies Hue matrix coefficient 00 when cb In offset is negative Signed 00000 0 01001 0 00390625 1 256 01002 0 0078125 2 256 CRG1_x RW OhOFF 0 99609375 255 256 0h100 1 0 256 256 0h300 1 0 256 256 01301 0 99609375 255 256 Oh3FF 0 00390625 1 256 01101 to 2FF Reserved do not use SAMSUNG ELECTRONICS 16 117 x 4412 UM 16 Display Controller 16 5 3 68 HUECOEF_CB_n n 1 to 4 Base Address 0x11C0_0000 e Address Base Address 0x01FC Reset Value 0x0100 0100 HUE
280. Bn to value in the TCMPBn register 109 the output changes from low to high If the down counter reaches 0 then it generates an interrupt request 10 The down counter automatically reloads This restarts the cycle SAMSUNG ELECTRONICS 11 2 ex 4412 UM 11 Pulse Width Modulation Timer Figure 11 2 illustrates the clock generation scheme for individual PWM channels Y XpwmTOUTO gt DeadZone Generator Control Logic 0 DeadZone 8BIT PRESCALER 0 TCMPB1 TCNTB1 N N gt TOUTI Control pwmTOU Logic 1 gt DeadZone TCMPB2 2 y y N Nr Control 0 XpwmTOUT2 Logic 2 gt gt y Y 8BIT Control XpwmTOUT3 PRESCALER Logic 3 gt 1 4 Y Control Logic 4 Figure 11 2 PWM TIMER Clock Tree Diagram Each timer can generate level interrupts SAMSUNG ELECTRONICS 11 3 II 4412 UM 11 Pulse Width Modulation Timer 11 2 Features The features of PWM are Five 32 bit timers Two 8 bit Clock Prescalers providing first level of division for the PCLK Five Clock Dividers and Multiplexers providing second level of division for the Prescal
281. C pulse polarity IVSYNC 5 0 Normal 1 Inverted Specifies VDEN signal polarity IVDEN 4 0 Normal 1 Inverted SAMSUNG ELECTRONICS 16 59 ex 4412 UM 16 Display Controller 16 5 3 3 VIDCON2 Base Address 0x11C0_0000 e Address Base Address 0x0008 Reset Value 0x0000_0000 RSV II ACT Enables RGB skip mode RGB SKIP EN 27 RW Ca where RGBSPSEL 1 b0 0 Disables 1 Enables RD Rem Controls RGB dummy insertion location Only where RGB DUMMY 25 RW RGBSPSEL 1 b1 and RGB DUMMY EN 1 b1 LOG 0 Last fourth position 1 First position Enables RGB dummy insertion mode RGB DUMMY 24 RW Only where RGBSPSEL 1 b1 EN 0 Disables 1 Enables Reserved RSVD 23 22 eso eal NOTE This bit should be set to 0 Controls RGB interface output order Odd Line line number 1 3 5 7 where RGBSPSEL 1 b0 RGB ORDER O 18 16 RW 000 001 GBR 010 BRG 100 BGR SAMSUNG ELECTRONICS 16 60 Controls RGB interface output order Even line line number 2 4 6 8 where RGBSPSEL 1 b0 000 RGB 001 GBR 010 BRG 100 BGR 101 RBG 110 GRB RGB ORDER 21 19 RW where RGBSPSEL 1 b1 RGBSPSEL 1 b0 and RGB_SKIP_EN 1 b1 000 R gt G gt B 001 G gt B gt R 010 B gt R gt G 100 B gt G gt R 101 R gt B gt G 110 G gt R gt B NOTE PNRO 0 atVIDCONO should be set to 0 when you use RGB ORDER OJ 2 0 at VIDCONS register
282. CKED 29 0 Unlocks 1 Locks RD ma ov The reset value of VPLL_CONO generates a 222 75 MHz output clock for an input clock frequency of 24 MHz Equation to calculate the output frequency is Four K 65535 x F PDIV x 2597 Where MDIV PDIV SDIV and K should meet the following conditions e 1 lt PDIV lt 63 e MDIV 16 lt lt 511 e SDIV 0 lt SDIV lt 5 e K 0 lt K lt 65535 e Fref Fpy PDIV Fref should fall in the range of 4 MHz lt Fref lt 30 MHz e K v x Fin PDIV e FOUT 22 MHz lt Four lt 1400 MHz Do not set the value PDIV or MDIV to all zeros Refer to the section 5 4 3 Recommended PLL PMS Value for VPLL for the recommended PMS values SAMSUNG ELECTRONICS 5 51 ex 4412 UM 5 Clock Management Unit 5 10 1 23 VPLL_CON1 e Base Address 0x1003 0000 e Address Base Address 0xC124 Reset Value 0x6601 6000 Modulation Method Control 00 Down spread 30 29 01 spread 1 Center spread 28 24 Modulation Rate Control MFR 23 16 Modulation Frequency Control PLL DSM The equation to calculate the Modulation Frequency is MF FFIN PDIV MFR 32 Hz The equation to calculate the Modulation Rate MR is e MR MFR x MRR MDIV 64 x 100 The conditions that MFR and MRR should meet are e should fall in the range of 0 lt lt 255
283. CMU CPU CMU DMC CMU RIGHTBUS CMU LEFTBUS RX HALF BYTE _ SAMSUNG ELECTRONICS 5 22 27 4412 UM 5 Clock Management Unit 5 9 1 0 Description Table 5 8 describes the 1 0 Table 5 8 IO Description EPLLFILTER Input Output Pad for EPLL loop filter capacitance XEPLLFILTER Dedicated VPLLFILTER Input Output Pad for VPLL loop filter capacitance XVPLLFILTER Dedicated XCLKOUT Output Clock out pad XCLKOUT Dedicated SAMSUNG ELECTRONICS 5 23 ex 4412 UM 5 Clock Management Unit 5 10 Register Description The clock controller controls PLLs and clock generation units This section describes the usage of Special Functional Registers SFRs in the clock controller Do not change any reserved area Any change in the reserved area leads to an unexpected behavior The address map of Exynos 4412 clock controller consists of six CMUs They are CMU_LEFTBUS CMU_RIGHTBUS CMU_TOP CMU_DMC CMU_CPU and CMU_ISP Each CMU uses an address space of 16 KB for SFRs The internal structure of address space for each CMU is similar for all CMUs The six categories into which the address space is divided are e Use 0x000 to Ox1FF for PLL control PLL lock time and control Use 0x200 to 0x4FF for MUX control MUX selection output masking and status e Use 0x500 to 0x6FF for clock division Divider ratio and status e 0x700 to Ox8FF is reserved and you are not allowed to access the region e Use 0x900 to
284. COEF_CB_1 e Address Base Address 0x0200 Reset Value 0x0000 0000 HUECOEF_CB_2 e Address Base Address 0x0204 Reset Value 0x0000 0000 HUECOEF_CB_3 Address Base Address 0x0208 Reset Value 0x0100_0100 HUECOEF_CB_4 Specifies Hue matrix coefficient 00 when cb In_offset is positive Signed 00000 0 01001 0 00390625 1 256 01002 0 0078125 2 256 CBGO 25 16 E OhOFF 0 99609375 255 256 0h100 1 0 256 256 0h300 1 0 256 256 0h301 0 99609375 255 256 Oh3FF 0 00390625 1 256 0h101 to 2FF Reserved do not use RSVb __ Reserved Specifies Hue matrix coefficient 00 when cb In_offset is negative Signed 00000 0 01001 0 00390625 1 256 01002 0 0078125 2 256 CBG1_x RW OhOFF 0 99609375 255 256 0100 1 0 256 256 01300 1 0 256 256 01301 0 99609375 255 256 Oh3FF 0 00390625 1 256 01101 to 2FF Reserved do not use SAMSUNG ELECTRONICS 16 118 x 4412 UM 16 Display Controller 16 5 3 69 HUEOFFSET e Base Address 0x11C0_0000 e Address Base Address 0x020C Reset Value 0x0108_0080 Sv freer AT Specifies Hue matrix input offset signed 0h000 0 0h001 1 0h002 2 OFFSET_IN 24 16 RW OhOFF 255 01100 256 Ox1FF 1 mo ms Specifies Hue matrix output offset signed 0h000 0 01001 1
285. Clock Management Unit MFC_BLK MAUDIO_BLK gt tbo lt SCLK_HDMI27M SCLK_USBPHYO SCLK MFC 0 MUXaupioo SCLK_AUDIOO DIVaupioo pS LS XusbXTI s MouTaool 1716 DIVpcmo SCLK_PCMO 1 256 L SCLK_G3D Sex HDMIZ7M 9 SCLK USBPHYO SCLK S SCLK_HDMIPHY gt MOUTasp 1 SCLKwpu usen gt SCLK HDMI27M SCLK USBPHYO SCLK MMC4 PRE 1 256 SCLKmpu usen SCLK HDMI SCLK_HDMIPHY SCLKupu user gt DIV SCLK_PIXEL_GATED 1 D MIPIHSI gt 1 16 MOUTmipinst SCLK_MIPIHSI clock frequency is fixed at 200MHz So the glitch free mux is not used SCLK_MIPIHSI Figure 5 2 4412 Clock Generation Circuit Special Clocks NOTE The SCLKuser_mpll In Figure 5 2 means SCLKuser_mpll_T Caution In Figure 5 1 and Figure 5 2 MUX s with grey color are glitch free For glitch free clock ensure that all clock sources are running while changing the clock selection For clock dividers ensure that input clock is running while changing the divider value SAMSUNG ELECTRONICS 5 14 ex 4412 UM 5 Clock Management Unit 5 6 Clock Configuration Procedure The rules for changing the clock configuration are e All inputs of a glitch free MUX should run e When PLL is turned OFF you should not select the output of PLL The
286. Combiner 7 6 2 8 IMSR1 e Base Address 0x1044 0000 e Address Base Address 0x001C Reset Value Undefined Name Tyre Desorption Roset Value Rv ______ SYSMMU MI EE SYSMMU Mo 29 interrupt pending status ECKEN SYSMMU TV Mor 28 enable bit is 0 the Bn 0 The interrupt is not pendiid E SYSMMU LCDO 26 1 The interrupt is pending svsmmu 28 R svewwu ROTATOR 24 R 201 R r SYSMMU tea R SYSMMU_FIMC3 1 21 Masked interrupt pending status ___ SYSMMU FIMC2 1 20 enable bit is 0 the HE SYSMMU FIMC1H 091 0 The interrupt is not sending SYSMMU_FIMCO 1 18 R 1 The interrupt is pending svwwusss n SvsMMU __ A m svewwu MO R SYSMMU MO 13 interrupt pending status If the LE ww SYSMMU TV 12 enable bit is 0 the IMSR 0 The interrupt pending E GEN SYSMMU LCDO 10 1 The interrupt is pending SYSMMU_GPSIO 9 Ss SYSMMU ROTATOR O 8 SYSMMU 2D m SYSMMU JPEG el SYSMMU FIMC3 0 51 Masked i
287. Control 4 3 3 120 EXT_INT24CON e Base Address 0x1100 0000 e Address Base Address 0x070C Reset Value 0x0000 0000 Gus ms ne oo Sets signaling method of EXT INT24 6 0 0 Low level 0 1 High level EXT INT24 CON 6 26 24 RW 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved 85 9 gp eee pf 0 Sets signaling method of EXT INT24 5 0 0 Low level 0x1 High level EXT 24 22 20 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0x7 Reserved 85 0 mp fe Sets signaling method of EXT INT24 4 0 0 Low level 0 1 High level EXT INT24 CON 4 18 16 RW 0 2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved 85 0 mp Jane fe Sets signaling method of EXT INT24 3 0 0 Low level 0 1 High level EXT INT24 CON 3 14 12 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0x7 Reserved 85 0 mi fasen fe Sets signaling method of EXT INT24 2 0x0 Low level 0 1 High level EXT INT24 CON 2 10 8 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 194 27 4412 UM 4 General Purpose Input Output GPIO Control Bee signaling method of EXT INT24 1
288. Cycle 9 4 1 nWAIT Pin Operation When it enables NWAIT signal corresponding to each memory bank the external NWAIT pin should prolong the duration of nOE while the memory bank is active It verifies the nWAIT from tacc 1 and deasserts the nOE at the next clock after sampling NWAIT is high The nWE signal has the similar relation with signal Figure 9 2 illustrates the SROMC nWAIT timing diagram Delayed gt gt Sampling nWAIT Figure 9 2 SROMC nWAIT Timing Diagram SAMSUNG ELECTRONICS 9 2 ex 4412 UM 9 SROM Controller 9 4 2 Programmable Access Cycle Figure 9 3 illustrates the SROMC read timing diagram ADDRESS 1 gt lt DATAO y Tacs 2 cycle 2 cycle Tcos 2 cycle Tcoh 2 cycle Tacc 3 cycle Tcah 2 cycle Figure 9 3 SROMC Read Timing Diagram Figure 9 4 illustrates the SROMC write timing diagram ADDRESS DATA W Tacs 2 cycle Tacp dont care Tcos 2 cycle 2 3 2 Figure 9 4 5 Write Timing Diagram SAMSUNG ELECTRONICS 9 3 x 4412 UM 9 SROM Controller 9 5 I O Description This section describes the I O d
289. DATA 0 GPK1CON 3 15 12 0 3 SD 0 DATA 4 0 00 0 4 SD 4 DATA 4 0 5 to Reserved EXT INT24 3 0 0 Input 0 1 Output 0 2 SD 1 CDn GPK1CON 2 11 8 0x3 GNSS GPIO 9 0 00 0 4 SD 4 nRESET OUT 0 5 to Reserved OxF EXT_INT24 2 0x0 Input 0x1 Output GPK1CON 1 7 4 0 2 SD 1 CMD 0 00 0 3 to Reserved OxF EXT_INT24 1 0x0 Input 0x1 Output GPK1CONI 0 3 0 0 2 SD 1 CLK 0 00 0 3 to Reserved SAMSUNG ELECTRONICS 4 128 IT 4412 UM 4 General Purpose Input Output GPIO Control O GEO E SAMSUNG ELECTRONICS 4 129 II 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 8 GPK1DAT Base Address 0x1100 0000 e Address Base Address 0x0064 Reset Value 0 00 When you configure port as input port the corresponding bit is the pin state When configuring GPK1DAT 6 0 RWX as output port the pin state should be same as the 0x00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 3 9 GPK1PUD Base Address 0x1100 0000 e Address Base Address 0x0068 Reset Value 0 1555 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down GPK1PUDIn n 0to6 RW 0x2 Reserved 0x1555 0x3 Enables Pull up 4 3 3 10 GPK1DRV e Base Address 0x1100_0000 e Address Base Address 0x006C Reset Value 0 00 0000 23 16 Reserve
290. DDOB 1 e Address Base Address 0 20 0 Reset Value 0x0000_0000 VIDWO2ADDOB2 e Address Base Address 0x00B8 Reset Value 0x0000 0000 VIDWOSADDOBO e Address Base Address Reset Value 0x0000 0000 VIDWO3ADDOB1 e Address Base Address 0x20B8 Reset Value 0x0000_0000 VIDWO3ADD0B2 e Address Base Address 0 00 0 Reset Value 000 0000 VIDWO4ADDOBO e Address Base Address 0x00C4 Reset Value 0x0000 0000 VIDWO4ADDO0B1 e Address Base Address 0 20 0 Reset Value 0x0000_0000 VIDWO4ADDOB2 VBASEU F 31 0 A 31 0 of the start address for video frame SAMSUNG ELECTRONICS 16 92 IT 4412 UM 16 Display Controller 16 5 3 34 VIDWOn 00 to 04 ADD1Bn n 0 to 2 Base Address 0x11C0_0000 e Address Base Address 0 0000 Reset Value 0x0000 0000 e Address Base Address 0x00D4 Reset Value 0x0000 0000 e Address Base Address 0 2000 Reset Value 0x0000_0000 e Address Base Address 0x00D8 Reset Value 0x0000 0000 e Address Base Address 0x00DC Reset Value 0 0000 0000 e Address Base Address 0x20D8 Reset Value 0x0000_ 0000 e Address Base Address Reset Value 0x0000 0000 e Address Base Address 0x00E4 Reset Value 0x0000 0000 e Address Base Address 0 20 0 Reset Value 0x0000 0000 VIDWO2ADD1B2 e Address Base Address 0x00E8 Reset Value 0x0000 0000 VIDWO3ADD1B0
291. DIO2 I282 RATIO 1 RSVD 7 6 Reserved w 0x0 DIVI2S1 Clock Divider Ratio FE 5 0 SCLK 1251 SCLK AUDIO1 I281 RATIO 1 EN 5 10 1 69 CLK DIV CAM1 e Base Address 0x1003 0000 e Address Base Address 0xC568 Reset Value 0x0000 0000 RSVD ove DIVJPEG Clock Divider Ratio 8 01 PW ACLK JPEG MOUTJPEG JPEG RATIO 1 SAMSUNG ELECTRONICS 5 92 27 4412 UM 5 Clock Management Unit 5 10 1 70 CLKDIV2 RATIO e Base Address 0x1003 0000 e Address Base Address 0xC580 Reset Value 0 0110 1011 RSV one noen 99 PCLK Divider Ratio in GPS BLK 0 Reserved GPS BLK 25 24 RW 1 Divides by 2 2 Divides by 3 3 Divides by 4 SE Red mw PCLK Divider Ratio in TV BLK 0 Reserved TV BLK 21 20 RW 1 Divides by 2 2 Divides by 3 3 Divides by 4 SE muq mee fm PCLK Divider Ratio in LCD BLK for 160 MHz domain 0 Reserved LCD BLK 13 12 RW 1 Divides by 2 2 Divides by 3 3 Divides by 4 SE me AN PCLK Divider Ratio in CAM 0 Reserved CAM BLK 5 4 RW 1 Divides by 2 2 Divides by 3 Divides by 4 SE Gg mw PCLK Divider Ratio in FSYS BLK 0 Reserved FSYS BLK 1 0 RW 1 Divides by 2 2 Divides by 3 3 Divides by 4 SAMSUNG ELECTRONICS 5 93 ex 4412 UM 5 Clock Management Unit 5 10 1 71 CLK DIV STAT TOP e Base Address 0x1003 0000 e Address Base Address
292. DIOO_SEL 3 0 RW SAMSUNG ELECTRONICS Controls MUXAUDIOO 0000 AUDIOCDCLKO 0001 Reserved 0010 SCLK HDMI24M 0011 SCLK_USBPHYO 0100 XXTI 0101 XusbXTI 0110 SCLKMPLL USER 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved MUXAUDIOO is the source clock of AUDIOO 5 Clock Management Unit 4412 UM 5 Clock Management Unit 5 10 1 34 CLK SRC FSYS e Base Address 0x1003 0000 e Address Base Address 0xC240 Reset Value 0x0001_1111 ra Control MUXMIPIHSI which is the source clock of MIPIHSI MIPIHSI SEL 24 RW 24 0 SCLKMPLL USER 1 SCLKAPLL wo 20 Controls MUXMMC4 MMC4_SEL 19 16 0000 XXTI 0001 XusbXTI 0010 SCLK_HDMI24M 0011 SCLK_USBPHYO 0101 SCLK_HDMIPHY 0110 SCLKMPLL_USER_T 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved MUKMMG is the source clock of MMC4 Controls MUKMMC3 0000 XXTI 0001 XusbXTI 0010 SCLK_HDMI24M 0011 SCLK_USBPHYO 0101 SCLK_HDMIPHY 0110 SCLKMPLL USER 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved MUKMMG3 is the source clock of MMC3_SEL 15 12 MMC2_SEL Controls MUXMMC2 0000 XXTI 0001 XusbXTI 0010 SCLK HDMI24M 0011 SCLK_USBPHYO 0101 SCLK_HDMIPHY 0110 SCLKMPLL USER 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved MUXMMC2 is the source clock of 2 Controls MUXMMC 1 0000 XXTI 0001 XusbXTI 0010 SCLK_HDMI24M MMC1 SEL
293. DIV SPIO ISP 4 0 Stable 1 Status that the divider is changing RSV oe DIVPWM ISP Status DIV PWM ISP 0 Stable 1 Status that the divider is changing SAMSUNG ELECTRONICS 5 98 ex 4412 UM 5 Clock Management Unit 5 10 1 78 CLK DIV STAT MAUDIO e Base Address 0 1003 0000 e Address Base Address 0xC63C Reset Value 0x0000 0000 RSV ers DIVPCMO Status DIV 4 0 Stable 1 Status that the divider is changing Avo 0 DIVAUDIOO Status DIV AUDIOO 0 Stable 1 Status that the divider is changing 5 10 1 79 CLK_DIV_STAT_FSYSO e Base Address 0x1003_0000 e Address Base Address 0xC640 Reset Value 0x0000_0000 RSV eran DIVMIPIHSI Status DIV MIPIHSI 20 0 Stable 1 Status that the divider is changing SE fom SAMSUNG ELECTRONICS 5 99 ex 4412 UM 5 Clock Management Unit 5 10 1 80 CLK_DIV_STAT_FSYS1 e Base Address 0x1003 0000 e Address Base Address 0xC644 Reset Value 0x0000_0000 RSV eras mesones DIVMMC1_ PRE Status DIV_MMC1_PRE 24 0 Stable 1 Status that the divider is changing Avo DIVMMC1 Status DIV MMC1 16 0 Stable 1 Status that the divider is changing DIVMMCO Status DIV MMCO PRE 8 0 Stable 1 Status that the divider is changing SE my nene DIVMMCO Status DIV MMCO 0 Stable 1 Statu
294. DIV1_CLK m MPWMDIV RATIO 1 SAMSUNG ELECTRONICS 5 157 x 4412 UM 5 Clock Management Unit 5 10 1 152 CLK_DIV_STAT_ISPO e Base Address 0x1004 0000 e Address Base Address 0x8400 Reset Value 0x0000_0000 RSV ers ISPDIV1 Status DIV_ISPDIV1 4 0 Stable 1 Status that the divider is changing moser AIN ISPDIVO Status DIV ISPDIVO 0 Stable 1 Status that the divider is changing 5 10 1 153 CLK DIV STAT ISP1 e Base Address 0x1004 0000 e Address Base Address 0x8404 Reset Value 0x0000 0000 RSV mu DIVMCUISP1 Status DIV MCUISPDIV1 0 Stable 1 Status that the divider is changing SE FS mo DIVMCUISPO Status DIV_MCUISPDIVO 4 0 Stable 1 Status that the divider is changing SE Gq ne mo DIVMPWM Status DIV MPWMDIV 0 Stable 1 Status that the divider is changing SAMSUNG ELECTRONICS 5 158 ex 4412 UM 5 Clock Management Unit 5 10 1 154 CLK_GATE_IP_ISPO e Base Address 0x1004 0000 e Address Base Address 0x8800 Reset Value OxFFFF_FFFF Gating all clocks for UART_ISP except SCLK CLK_UART_ISP 31 RW 0 Mask 1 Pass Gating all clocks for WDT_ISP CLK_WDT_ISP 30 RW 0 Mask 0 1 1 ASVO E Reewd fo Gating all clocks for PWM ISP except SCLK CLK PWM ISP 28 0 Mask 0 1 1 Pass Gating all clocks for MTCADC_ISP CLK_MTCADC_ISP 27 0 Mask 1 Pass Gat
295. DIVO 1 8 gt ACLK DIV1 ACLK DIV2 Figure 5 1 Exynos 4412 Clock Generation Circuit CPU BUS DRAM ISP Clocks SAMSUNG ELECTRONICS 5 12 227 4412 UM 5 Clock Management Unit CAM BLK LCDO BLK SCLK FIMCO 3 LCLK SCLKupuL user MUXrea o 5 ACLK JPEG wA m MUX pec 1 1 16 XusbXTI MUXrimpo MOUT pes SCLK HDMI24M SCLK FIMDO gt SCLK_USBPHYO DIVrimpo 1 16 gt SCLK HDMIPHY user SCLKveu XusbXTI MUXcsiso 1 SCLK_HDMI24M ess SCLK_USBPHYO DIVesi o X 0719 MT MPLL USER SCLK USBPHYO DiVmonizo SCLK_MDNIEO gt SCLK HDMIPHY SCLK weit usen XusbXTI MUXcamo 1 SCLKes SCLK HDMI24M SCLK yeu SCLK USBPHYO GATED PAD gt XXTI SCIK HDMIPHY XusbXTI SCLKupu user SCLK_HDMI24M DIV SCL Kem SCLK USBPHYO SCLK MDNIE PWMO SCLKypu WMO PRE SCLK_HDMIPHY 1 16 XXTI user XusbXTI MUXrimco 3 SCLKepu 5 SCLK HDMI24M SCLK_USBPHYO SCLK FIMCO 3 SCLK MIPIDPHY4L GATED DIVFimco 3 XXTI MUX SCLK_HDMIPHY 1 16 EP SCLK_USBPHYO DIV MIPIO SCLK PRE SCLK_HDMIPHY 1 16 1 16 SCLKueu user SCLKepu 5 PERIL_BLK XXT
296. DRESS Figure 10 2 CLE and ALE Timing 1 TWRPHO 0 TWRPH1 0 Figure 10 3 illustrates the nWE nRE timing TWRPHO 0 TWRPH1 0 TWRPHO TWRPH gt gt HCLK nWE nRE Figure 10 5 nWE and nRE Timing TWRPHO 0 TWRPH1 0 SAMSUNG ELECTRONICS 10 3 ex 4412 UM 10 NAND Flash Controller 10 4 Software Mode Exynos 4412 supports only software mode access Use this mode to access NAND flash memory The NAND flash controller supports direct access to interface with the NAND flash memory e Writing to the command register specifies the flash memory command cycle e Writing to the address register NFADDR specifies the flash memory address cycle e Writing to the data register NFDATA specifies write data to the flash memory Write cycle e Reading from the data register NFDATA specifies read data from the flash memory Read cycle e Reading ECC registers NFMECCDO NFMECCD1 and Spare registers NFSECCD specifies read data from the NAND flash memory NOTE In the software mode use polling or interrupt to the RnB status input pin 10 4 1 Data Register Configuration 10 4 1 1 8 bit NAND Flash Memory Interface 1 Word Access Register Endan esse ens NFDATA 4 1 0 7 0 3 1 0 7 0 2 1 0 7 0 14 1 0 7 0 2 Access NFDATA L
297. DTH15 6 This value is valid when FLTSEL15 of EXT_INT40 is 0 1 Filter Enable for EXT_INT40 5 FLTEN15 5 0 0 Disables Filter 0x1 Enables Filter Filter Selection for EXT_INT40 5 FLTSEL15 5 0 0 Delays filter 0x1 Digital filter clock count Filtering width of EXT_INT40 5 FLTWIDTH15 5 This value is valid when FLTSEL15 of EXT_INT40 is Ox1 Filter Enable for EXT INT40 4 FLTEN15 4 0 0 Disables Filter 0x1 Enables Filter Filter Selection for EXT_INT40 4 FLTSEL 15 4 0 0 Delays filter 0x1 Digital filter clock count Filtering width of EXT_INT40 4 FLTWIDTH15 4 This value is valid when FLTSEL15 of EXT INT40 is Ox1 SAMSUNG ELECTRONICS 4 273 II 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 216 EXT_INT41_FLTCONO Base Address 0x1100 0000 e Address Base Address OxOE88 Reset Value 0x8080_ 8080 Filter Enable for EXT_INT41 3 FLTEN16 3 0 0 Disables Filter 0x1 Enables Filter Filter Selection for EXT INT41 3 FLTSEL16 3 0 0 Delays filter 0 1 Digital filter clock count Filtering width of EXT_INT41 3 FLTWIDTH16 3 This value is valid when FLTSEL16 of EKT INT41 is 0x1 Filter Enable for EXT_INT41 2 FLTEN16 2 0x0 Disables Filter 0x1 Enables Filter Selection for EXT_INT41 2 FLTSEL16 2 0 0 Delays filter 0 1 Digital filter clock count Filtering width of EXT_INT41 2 FLTWIDTH16 2 This value is valid when FLTSEL16 of EXT_INT41
298. Delays filter 0x1 Digital filter clock count Filtering width of EXT_INT42 5 FLTWIDTH17 5 This value is valid when FLTSEL17 of EXT_INT42 is 0x1 Filter Enable for EXT_INT42 4 FLTEN17 4 0x0 Disables Filter 0 1 Enables Filter Filter Selection for EXT_INT42 4 FLTSEL17 4 0 0 Delays filter Ox1 Digital filter clock count Filtering width of EXT INT42 4 FLTWIDTH17 4 This value is valid when FLTSEL17 of EXT INT42 is Ox1 SAMSUNG ELECTRONICS 4 277 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 220 EXT_INT43_FLTCONO Base Address 0x1100 0000 e Address Base Address OxOE98 Reset Value 0x8080_ 8080 Filter Enable for EXT_INT43 3 FLTEN18 3 0 0 Disables Filter 0 1 Enables Filter Filter Selection for EXT INT43 3 FLTSEL18 3 0 0 Delays filter 0 1 Digital filter clock count Filtering width of EXT_INT43 3 FLTWIDTH1 8 3 This value is valid when FLTSEL18 of EXT_INT43 is 0x1 Filter Enable for EXT_INT43 2 1 8 2 0 0 Disables Filter 0 1 Enables Filter Filter Selection for EXT_INT43 2 FLTSEL18 2 0 0 Delays filter Ox1 Digital filter clock count Filtering width of EXT INT43 2 FLTWIDTH18 2 This value is valid when FLTSEL18 of EXT_INT43 is 0 1 Filter Enable for EXT_INT43 1 FLTEN18 1 0x0 Disables Filter 0x1 Enables Filter Filter Selection for EXT_INT43 1 FLTSEL18 1 0 0 Delays filter Ox1 Digital filter clock c
299. ECTRONICS 4 262 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 207 GPX3DAT e Base Address 0x1100 0000 e Address Base Address 0x0C64 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPX3DAT 7 0 7 0 output port then pin state should be same as 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 3 208 GPX3PUD Base Address 0x1100 0000 e Address Base Address 0x0C68 Reset Value 0x5555 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down GPX3PUDIn n201o7 RW 0x2 Reserved 0x5555 0x3 Enables Pull up 4 3 3 209 GPX3DRV e Base Address 0x1100_0000 e Address Base Address 0x0C6C Reset Value 0x00_0000 23 16 Reserved Should be zero W GPX3DRV n n 2n 1 2 0x0000 0107 SAMSUNG ELECTRONICS 4 263 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 210 EKT INT40CON e Base Address 0x1100 0000 e Address Base Address 0 Reset Value 0x0000 0000 RSV Sets signaling method of EXT_INT40 7 0 0 Low level 0x1 High level EXT 40 CON 7 30 28 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0 7 Reserved 85 2 mee ov Sets signaling method of EXT INT40 6 0 0 Low le
300. ELECTRONICS 4 135 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 20 GPK3DAT Base Address 0x1100 0000 e Address Base Address 0x00A4 Reset Value 0x00 When you configure port as input port then corresponding bit is pin state When configuring as GPKS3DAT 6 0 RWX output port the pin state should be same as the 0x00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 3 21 GPK3PUD Base Address 0x1100 0000 e Address Base Address 0x00A8 Reset Value 0x1555 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down GPK3PUDIn A 0t06 RW 0x2 Reserved 0x1555 0x3 Enables Pull up 4 3 3 22 GPK3DRV e Base Address 0x1100_0000 e Address Base Address Reset Value 0 00 0000 23 16 Reserved Should be zero W GPK3DRVIn Inj 2n 1 2n R 0x0000 0106 SAMSUNG ELECTRONICS 4 136 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 23 GPK3CONPDN e Base Address 0x1100 0000 e Address Base Address Reset Value 0x0000 0 0 Outputs 0 2n 1 21 0 1 Outputs 1 ala 0106 FW oxo lt input 552 0 3 Previous state 4 3 3 24 GPK3PUDPDN Base Address 0x1100_0000 e Address Base Address 0x00B4 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down 0106 0 2
301. EN Specifies the transparency value selection bit with WPALCON Palette output format AEN 0 Selects ALPHAO AEN 1 Selects ALPHA1 When it sets per pixel blending then this pixel blends with alpha value that AEN selects SFR selects the alpha value as ALPHAO_R ALPHAO_G ALPHAO_B ALPHA1_R ALPHA1_G and ALPHA1_B For more information refer to the section on SFR SAMSUNG ELECTRONICS 16 22 x 4412 UM 16 Display Controller 16 3 4 Palette Usage The Palette Usage section includes e Palette Configuration and Format Control e Palette Read Write 16 3 4 1 Palette Configuration and Format Control The display controller supports 256 color palette to select color mapping You can select up to 256 colors from 32 bit colors using these formats 256 color palette consists of 256 depth x 32 bit SPSRAM Palette supports 8 8 8 6 6 6 5 6 5 R G B and other formats For Example See A 5 5 5 format write palette as illustrated in Figure 16 20 1 Connect VD pin to TFT LCD panel 5 VD 23 19 5 VD 15 11 and 5 VD 7 3 2 AEN bit controls the blending function enable or disable 3 Set WPALCON W1PAL case window0 register to 0 b101 The 32 bit 8 8 8 8 format has an alpha value directly without using alpha value register ALPHA 0 1 Figure 16 19 illustrates the 32 BPP 8 8 8 8 palette data format INDEX Bit Pos
302. EXT INT7 0 FLTEN7 O 7 RW Disables filter 0 1 Enables filter FLTWIDTH7 0 1601 RW Filtering width of EXT INT7 0 4 3 2 107 EXT INT7 FLTCON1 Base Address 0x1140 0000 e Address Base Address 0x0834 Reset Value 0x0000 0000 SAMSUNG ELECTRONICS 4 90 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 108 EXT_INT13_FLTCONO e Base Address 0x1140 0000 e Address Base Address 0x0860 Reset Value 0x0000 0000 Filter Enable for EXT INT13 3 FLTEN13 3 31 RW 0 0 Disables filter 0 1 Enables filter FLTWIDTH13 3 30 24 Filtering width of EXT INT13 3 Filter Enable for EXT INT13 2 FLTEN13 2 23 RW 0 0 Disables filter 0x1 Enables filter FLTWIDTH13 2 22 16 Filtering width of EXT INT13 2 Filter Enable for EXT INT13 1 FLTEN13 1 15 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH13 1 14 8 Filtering width of EXT INT13 1 Filter Enable for EXT INT13 0 FLTEN13 0 7 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH13 0 6 0 Filtering width of EXT INT13 0 SAMSUNG ELECTRONICS 4 91 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 109 EXT_INT13_FLTCON1 e Base Address 0x1140_0000 e Address Base Address 0x0864 Reset Value 0x0000_0000 Filter Enable for EXT_INT13 7 FLTEN13 7 31 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH13 7 30 24 Filtering width o
303. FC It is an active low signal oxo 90 og Decides whether DCC is enabled not 0 Enables DCC im 0 sad LOCK DLY 11 8 detector settings of the detection 85 9 75 op RW aro value owo Refer to the section 5 4 1 Recommended PLL PMS Value for APLL and MPLL for recommended AFC_ENB and AFC values 0x0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x3 0x8 0 0 0 0 NOTE The other PLL control inputs should be set as RESV1 0 RESV0 0 DCC_ENB 1 EXTAFC 0 LOCK CON IN 3 LOCK CON OUT 0 LOCK_CON_DLY 8 _ 0 SAMSUNG ELECTRONICS 5 123 ex 4412 UM 5 Clock Management Unit 5 10 1 107 CLK SRC DMC e Base Address 0x1004 0000 e Address Base Address 0x0200 Reset Value 0x0001 0000 RSV 61291 eee om Control MUXG2D ACP which is the source clock G2D ACP 5 28 RW of G2D ACP core EL 0 MOUTG2D ACP 0 1 MOUTG2D ACP 1 D ma Control MUKG2D ACP 1 which is the source G2D ACP 1 24 RW clock of G2D ACP core _SEL 0 SCLKEPLL 1 SCLKVPLL ASV A Control MUXG2D ACP 0 which is the source MUX_G2D_ACP_0 20 RW clock of G2D ACP core _SEL 0 SCLKMPLL 1 SCLKAPLL Controls MUKPWI 0000 0001 XusbXTI 0010 SCLK_HDMI24M 0011 SCLK USBPHYO 0100 SCLK_USBPHY1 MUX_PWI_SEL 19 16 RW 0101 SCLK HDMIPHY 0110 SCLKMPLL 0111 SCLKEPLL 1000 SCLK
304. Filter Enable for EXT_INT30 7 FLTEN1 7 31 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH1 7 30 24 Filtering width of EXT_INT30 7 Filter Enable for EXT_INT30 6 FLTEN 1 6 23 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH1 6 22 16 Filtering width of EXT INT3O 6 Filter Enable for EXT INT30 5 FLTEN1 5 15 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH1 5 14 8 Filtering width of EXT_INT30 5 Filter Enable for EXT_INT30 4 FLTEN1 4 7 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH1 4J 1601 RW Filtering width of EXT_INT30 4 SAMSUNG ELECTRONICS 4 324 en 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 42 EXT_INT31_FLTCONO Base Address Ox106E 0000 e Address Base Address 0x0808 Reset Value 0x0000 0000 Filter Enable for EXT INT31 S3 FLTEN2 3 31 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH2 3 30 24 Filtering width of EXT INT31 3 Filter Enable for EXT_INT31 2 FLTEN2 2 23 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH2 2 22 16 Filtering width of EXT_INT31 2 Filter Enable for EXT_INT31 1 FLTEN2 1 15 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH2 1 14 8 Filtering width of EXT INT31 1 Filter Enable for EXT INT31 0 FLTEN2 0 7 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH2 0 RW Filtering width of EXT_INT31 0 SAMSUNG ELECTRONICS
305. General Purpose Input Output GPIO Control 4 3 2 136 EXT_INT4_PEND Base Address 0x1140_0000 e Address Base Address Reset Value 0x0000 0000 EXT INT4 PEND 4 4 RWX 0 0 Not occur Ox1 Interrupt occurs EXT PEND 3 3 RWX 0 0 Not occur 44 0 1 Interrupt occurs EXT INT4 PEND 2 2 RWX Ox0 Not occur m 0 1 Interrupt occurs EXT INT4 PEND 1 1 RWX Ox0 Not occur 0 1 Interrupt occurs EXT INT4 PEND 0 RWX 0 0 Not occur 0 1 Interrupt occurs 4 3 2 137 EXT 5 Base Address 0x1140 0000 e Address Base Address 0x0A10 Reset Value 0x0000 0000 EXT 5 PEND 4 4 RWX 0 0 Not occur WA 0 1 Interrupt occurs EXT 5 3 RWY 0 0 Not Ox1 Interrupt occurs 5 PEND 2 Pr 90 Not oceur 0 1 Interrupt occurs EXT_INT5_PEND 1 mi Bwoc 0021916655 0 1 Interrupt occurs 0 0 Not occur EXT PEND 0 EB BUDE T oiner o SAMSUNG ELECTRONICS 4 111 en 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 138 EXT_INT6_PEND Base Address 0x1140_0000 e Address Base Address 0x0A14 Reset Value 0x0000 0000 EXT INT6 PEND S3 3 RWX 0x0 Not occur 0 1 Interrupt occurs EXT INT6 PEND 2 2 Rw x 0x0 Not occur 0 1 Interrupt occurs EXT 6 PEND 1 1 RWX 0 0 Not occur 0 1 Interrupt occurs
306. Guide DECODING 1 To use 8 12 16 bit ECC in software mode set MsgLength NFECCCONF 25 16 to 511 512 byte message length and the ECCType to 001 100 101 enable 8 12 16 bit ECC respectively ECC module generates ECC parity code for 512 byte read data Therefore you should reset ECC value by writing the NFECCCONT 2 bit as 1 and clear the MainECCLock NFCONT 7 bit to 0 unlock before read data Whenever data is read the 8 12 16 bit ECC module generates ECC parity code internally After you complete reading 512 byte excluding spare area data ensure to read the corresponding parity codes ECC module requires parity codes to detect whether error bits have occurred or not Therefore you should read ECC parity code immediately after reading 512 byte After reading the ECC parity code the 8 12 16 bit ECC engine searches for error internally 8 12 16 bit ECC search engine requires minimum of 155 cycles to find any errors DecodeDone NFECCSTAT 24 can be used to check whether ECC decoding is completed or not When DecodeDone NFECCSTAT 24 is set 1 ECCError NFECCSECSTAT 4 0 indicates whether error bit exists or not If any error exists you can fix it by referencing NFECCERLO to 7 and NFECCERPO to NFECCERP3 registers If you have additional main data to Read repeat the steps 1 4 To verify spare area data meta data error the sequences are similar steps 1 4 except setting the
307. H18 5 This value is valid when FLTSEL18 of EXT_INT43 is 0 1 Filter Enable for EXT INT43 4 FLTEN18 4 0 0 Disables Filter 0 1 Enables Filter Filter Selection for EXT INT43 4 FLTSEL18 4 0 0 Delays filter Ox1 Digital filter clock count Filtering width of EXT INT43 4 FLTWIDTH18 4 This value is valid when FLTSEL18 of EXT INT43 is Ox1 SAMSUNG ELECTRONICS 4 279 II 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 222 EXT_INT40_MASK e Base Address 0x1100 0000 e Address Base Address 0x0F00 Reset Value 0x0000_00FF ox vao MASA E EXT_INT40_MASKT 5 5 ce _ 4 Da masa pw 90 Eels merum masa 90 Enes ner m aw nocens 0 0 Enables Interrupt EXT INT40 MASK 1 1 0 1 Masked 0 0 Enables Interrupt EXT INT40 Rw 0 1 Masked SAMSUNG ELECTRONICS 4 280 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 223 41 5 e Base Address 0x1100 0000 e Address Base Address 0x0F04 Reset Value 0x0000_00FF ex acu norem oe m one EXT_INT41_MASKT 5 5 ce _ 4 EXT INT41 MASK 4 4 s 4 A ocr ra assqa m 90 Esl ner EXT 41 MASK 2 2 Fe 0 0 Enables Interrupt EXT INT41 MASK 1 1 0 1 Masked 0 0 Enables Interrupt EXT INT41 Rw 0 1
308. I SROM NF e GPY3 GPY4 GPY5 GPY6 32 in out memory ports EBI For more information about EBI configuration refer to Chapter 5 and 6 e MP1 0 1 9 78 ports NOTE registers does not control these ports e 2 0 MP2 9 78 DRAM2 ports NOTE registers does not control these ports ETCO ETC1 ETC6 18 in out ETC ports JTAG SLIMBUS RESET CLOCK ETC7 ETC8 4 clock port for C2C Warning When you do not use or connect port to an input pin without Pull up Pull down then do not leave a port Input Pull up Pull down disable state It may cause unexpected state and leakage current Disable Pull up Pull down when you use port as output function SAMSUNG ELECTRONICS 4 2 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 2 Features The features of GPIO include e Controls 172 External Interrupts e Controls 32 External Wake up Interrupts e 252 multi functional input output ports e Controls pin states in Sleep Mode except GPX0 GPX1 GPX2 GPX3 GPX pins are alive pads 4 2 1 Input Output Description This section includes e General Purpose Input Output Block Diagram e Register Description SAMSUNG ELECTRONICS 4 3 ex 4412 UM 4 2 1 1 General Purpose Input Output Block Diagram GPIO consists of two parts e alive part e off part 4 General Purpose Input Output GPIO Control In Alive part you should supply power
309. I XusbXTI MUXspio 2 SCLK_HDMI24M ISP BLK SCEKLUSBFHYD DIVspio 2 DIVspio 2 PRE gt SCLK HDMIPHY 1716 1 256 SCLKupuL usen SCLKepu MOUTspio 2 SCLK ypu XXTI XusbXTI xxm SCLK HDMI24M XusbXTI MUXUART0 4 SCLK USBPHY0 SCLK_PWM_ISP SCLK_HDMI24M SCLK USBPHYO 4 SCLK HDMIPHY 1 16 SCLKmpu_usen r SCLK_HDMIPHY 5 Kuru usen SCLKyeu SCLKepu SCLKvpu XXTI XusbXTI MUX pio 2 SCLK SLIMBUS SCLK HDMI24M Vsumbus gt 5 USBPHYO DlVspio ise SCLK SPIO ISP 1 16 isP PRE SCLK HDMIPHY 1 16 1 256 MOUTspio 2 MUXaupio1 SCLK HDMI24M SCLK USBPHYO DIVAubio XXTI XusbXTI MOUTA 1716 XXTI 5 user MUXsen_isP SCLK SCLK USBPHYO SCLK AUDIO1 isp pre 19 SCLK HDMIPHY 17256 SCLK HDMI24M 5 MOUT spis is SCLK_USBPHYO DIVaupioe SCLK_AUDIO2 SCLK veut XXTI 1 XusbXTI 1 16 SCLKmpu_usen_T SCLKepu SCLKveu XXTI XusbXTI MUXuart isP SCLK HDMI24M SCLK USBPHYO SCLK UART ISP SCLK AUDIO1 2 SCLK PCM1 2 SCLK HDMIPHY MOUT uar isP SCLK AUDIO1 2 SCLK 1251 2 DIVi2s1 2 1 64 ALIVE_WRAP OSCCLK OSCCLK_MTCADG SCLK_AUDIOO S D CRYCLK_MTCADC_ISP SCLK AUDIO RTC CLK RTC OUT MTCADC SCLK AUDIO gt D gt RTCCLK MTCADC ISP SPDIF SAMSUNG ELECTRONICS 5 13 4412 UM 5
310. ICS 13 1 x 4412 UM 13 Universal Asynchronous Receiver and Transmitter 13 2 Features Features of UART are e 00 TxDO RxD1 TxD1 RxD2 TxD2 RxD3 and TxD3 with either DMA based or interrupt based operation e UART Ch 0 1 2 and 3 with IrDA 1 0 e UART Ch 0 with 256 byte FIFO Ch 1 and 4 with 64 byte FIFO Ch 2 and with 16 byte FIFO e UART Ch 0 1 2 with nRTSO nCTSO nRTS1 nCTS1 52 and nRTS2 for Auto Flow Control AFC e UART Ch 4 communicates with GPS and it supports AFC e supports handshakes transmit receive SAMSUNG ELECTRONICS 13 0 ex 4412 UM 13 Universal Asynchronous Receiver and Transmitter 13 3 UART Description This section includes UART operations such as e Data transmission e Data reception e Interrupt generation e Baud rate generation e Loop back mode e Infrared modes AFC Figure 13 1 illustrates the block diagram of UART Peripheral BUS Transmitter S555 Transmit FIFO Register FIFO mode Transmit Buffer Register Transmit Holding Register Non FIFO mode Transmit Shifter Control acy Buad rate Unit Generator Receiver Receive Shifter Receive Holding Register Non FIFO mode only Receive FIFO Register FIFO mode In FIFO mode all bytes of Buffer Register are used as FIFO register In non FIFO mode only 1 byte of Buffer Register is used as Holding register Figure 13 1 Block Diagram of UART
311. INT3 5 0 0 Low level 0 1 High level EXT INT3 CON 5 22 20 RW 0 2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved 85 0 na esea Sets signaling method of EXT_INT3 4 0x0 Low level 0x1 High level EXT_INT3_CON 4 18 16 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0 7 Reserved 85 9 Resened Sets signaling method of EXT INT3 3 0 0 Low level 0x1 High level EXT INT3 CON 3 14 12 RW 0 2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved mw n ee mw SAMSUNG ELECTRONICS 4 65 en 4412 UM 4 General Purpose Input Output GPIO Control Sets signaling method of EXT_INT3 2 0 0 Low level 0x1 High level EXT INT3 CON 2 10 8 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0x7 Reserved Sets signaling method of EXT INT3 1 0 0 Low level 0 1 High level EXT INT3 CON 1 6 4 RW 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0x7 Reserved Sets signaling method of EXT INT3 0 0 0 Low level 0 1 High level EXT INT3 CON 0 2 0 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved SAMSUNG ELECTRONICS 4 66 IT 4412 UM 4 General Purpose
312. IR 1 26 RW Read The current interrupt enable bit PARITYFAILSC 1 25 0 Masks PARITYFAIL1 24 ee ar ASVD ea Reema FARBINTE 221 Sets the corresponding interrupt enable bit to 1 If PARRDINTR 21 you set the interrupt enable bit interrupt combiner TMU ______ 20 serves the interrupt reguest Write 0 Does not change the current setting NE TRAU 19 1 Sets the interrupt enable bit to 1 PMUIRQ O 18 RW Read The current interrupt enable bit PARITYFAILSCU O 17 0 Masks PARITYFAILO 16 EN RSVD Reewd 271 TZASC1 1 11 Sets the corresponding interrupt enable bit to 1 EC 0 a you interrupt enable bit interrupt combiner TZASCOM RW Write 0 Does not change the current setting 1 Sets the interrupt enable bit to 1 TZASCO 0 Read interrupt enable bit 1 Enables ASVD ma Reewd 2 27 RSVD B RW Sets the corresponding interrupt enable bit to 1 If RSVD 2 Rw you set the interrupt enable bit interrupt combiner RSVD RW Write 0 Does not change the current setting 1 Sets the interrupt enable bit to 1 RSVD 0 mw Read The current interrupt enable bit 0 Masks 1 Enables SAMSUNG ELECTRONICS 7 10 4412 UM 7 Interrupt Combiner 7 6 2 2 IECRO e Base Address 0x1044 0000 e Address Base Address 0x0004 Reset Value 0 0000 0000 ASVD reserved 00 gt 80 RW C
313. IVCOPY Clock Divider Ratio d TO DOUTCOPY MOUTHPM COPY RATIO 1 oxo SAMSUNG ELECTRONICS 5 147 IT 4412 UM 5 Clock Management Unit 5 10 1 138 CLK_DIV_STAT_CPUO e Base Address 0x1004 0000 e Address Base Address 04600 Reset Value 000 0000 RSV Gus mee To DIVCORE2 Status DIV CORE2 28 0 Stable 1 Status that the divider is changing S res DIVAPLL Status DIV 24 0 Stable 1 Status that the divider is changing DIVPCLK_DBG Status DIV PCLK DBG 20 0 Stable 1 Status that the is changing Avo mose DIVATB Status DIV ATB 16 0 Stable 1 Status that the divider is changing S _____ mo DIVPERIPH Status DIV PERIPH 12 0 Stable 1 Status that the divider is changing SD ma mew 99 DIVCOREM Status DIV COREM1 0 Stable 1 Status that the divider is changing 85 0 Jan mw DIVCOREMO Status DIV COREMO 4 0 Stable 1 Status that the divider is changing 85 0 Jan AN DIVCORE Status DIV CORE 0 Stable 1 Status that the divider is changing SAMSUNG ELECTRONICS 5 148 27 4412 UM 5 Clock Management Unit 5 10 1 139 CLK DIV STAT CPU1 e Base Address 0x1004 0000 e Address Base Address 0x4604 Reset Value 000 0000 RSVD ne _ DIVCORES Status DIV CORES 8 0 Stable 1 Status that the
314. Input 0 1 Output 0 2 125 2 CDCLK 0 3 PCM 2 EXTCLK 0x4 SPDIF_EXTCLK 0x5 SPI_2 CLK 0x6 to OxE Reserved OxF EXT_INT5 1 0 0 Input 0 1 Output 0 2 125 2 SCLK 0x3 PCM 2 SCLK 0 4 SPDIF 0 OUT 0 5 to OxE Reserved OxF EXT_INT5 0 4 General Purpose Input Output GPIO Conirol 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 26 GPC1DAT e Base Address 0x1140_0000 e Address Base Address 0x0084 Reset Value 0 00 RWX When you configure port as input port corresponding bit is pin state When configuring as output port pin GPC1DAT 4 0 4 0 state should be same as the corresponding bit When 0 00 the port is configured as functional pin the undefined value will be read 4 3 2 27 GPC1PUD Base Address 0x1140_0000 e Address Base Address 0x0088 Reset Value 0x0155 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down GPC1PUDIn 0104 RW 0x2 Reserved 0x0155 0x3 Enables Pull up 4 3 2 28 GPC1DRV e Base Address 0x1140_0000 e Address Base Address 0x008C Reset Value 0x00_0000 23 16 Reserved Should be zero W GPC1DRV n n 2n 1 2n R 0x0000 n 0to 4 SAMSUNG ELECTRONICS 4 35 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 29 GPC1CONPDN Base Address 0x1140_0000 e Address Base Address 0x0090 Reset Value 0x0000 0x0 Outputs O 2n 1 2n 0x1
315. Input Output GPIO Control 4 3 2 84 EXT_INT4CON Base Address 0x1140_0000 e Address Base Address 0x070C Reset Value 0x0000_0000 RSVD Sets signaling method of EXT_INT4 4 0x0 Low level 0x1 High level EXT_INT4_CON 4 18 16 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0 7 Reserved 85 9 nome MI Sets signaling method of EXT_INT4 3 0x0 Low level 0x1 High level EXT INT4 CON 3 14 12 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0x5 to 0x7 Reserved 85 0 n Sets signaling method of EXT_INT4 2 0x0 Low level 0x1 High level EXT INT4 CON 2 10 8 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved Sets signaling method of EXT_INT4 1 0 0 Low level 0x1 High level EXT INT4 CON 1 6 4 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved Sets signaling method of EXT_INT4 0 0 0 Low level 0x1 High level EXT INT4 CON 0 2 0 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 67 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 85 EXT_INT5CON e Base Address 0x1140_0000 e Address Base Address 0x0710 Reset Value 0 0000 0000
316. Interface SAMSUNG ELECTRONICS 18 4 27 4412 UM 18 ADC 18 5 I O Descriptions AN3 Input ADC Channel 3 Analog input Xadc1AIN 3 AIN 2 ADC Channel 2 Analog input Xadc1AIN 2 AIN 1 ADC Channel 1 Analog input Xadc1AIN_1 AIN 0 ADC Channel 0 Analog input Xadc1AIN 0 SAMSUNG ELECTRONICS 18 5 ex 4412 UM 18 ADC 18 6 Register Description 18 6 1 Register Map Summary e Base Address 0x126C_0000 ADCCON 0x0000 ADC Control Register 0x0000_3FC4 ADCDLY 0x0008 ADC Start or Interval Delay Register 0x0000_00FF ADCDAT 0 000 ADC Conversion Data Register Undefined CLRINTADC 0x0018 Clear ADC Interrupt Undefined ADCMUX 0x001C Specifies the Analog input channel selection 0x0000_0000 SAMSUNG ELECTRONICS 18 6 ex 4412 UM 18 ADC 18 6 1 1 ADCCON e Base Address 0x126C_0000 e Address Base Address 0x0000 Reset Value 0x0000_3FC4 ADC output resolution selection RES 16 RW 0 10 bit A D conversion 1 12 bit A D conversion End of conversion flag Read only ECFLG 15 RW 0 conversion in process 1 End of A D conversion A D converter prescaler enable PRSCEN 14 RW 0 Disable 1 Enable A D converter prescaler value Data value 19 to 255 The division factor is N 1 when the prescaler value is N For example ADC frequency is 5 MHz if bus clock is 100 PRSCVL 13 6 RW MHz and the prescaler value is 19 NOTE This A D convert
317. Interrupt Enable for RxOverrun 0 Disables 1 Enables Interrupt Enable for RxUnderrun 0 Disables 1 Enables INT_EN_RX_ OVERRUN INT_EN_RX_ 4 UNDERRUN INT_EN_TX_ 3 OVERRUN Interrupt Enable for TkUnderrun In slave mode this le bit must be clear first after turning on slave path 0 Disables 1 Enables INT_EN_TX_ UNDERRUN INT EN RX FIFO literrupt Enable for RxFifoRdy INT mode 0 Disables RE 1 Enables INT EN TX FIFO Enable for TxFifoRdy INT mode RDY R 0 Disables 1 Enables RW RW RW RW RW RW W Interrupt Enable for TxOverrun 0 Disables 1 Enables SAMSUNG ELECTRONICS 15 11 ex 4412 UM 15 Serial Peripheral Interface 15 5 1 5 SPI STATUSn 0 to 2 Base Address 0x1392 0000 e Base Address 0x1393 0000 Base Address 0x1394 0000 e Address Base Address 0x0014 Reset Value 0 0 RSVD pre TRAILING_BYTE 24 RX_FIFO_RDY TX_FIFO_RDY SAMSUNG ELECTRONICS Indication that trailing count is 0 Indication of transfer done in Shift register master mode only 0 All case except below case 1 If Tx FIFO and shift register are empty after transmission start Data level in Rx FIFO O to 256 bytes in port 0 O to 64 bytes in port 1 2 Data level in Tx FIFO O to 256 bytes in port 0 0 to 64 bytes in port 1 2 Rx FIFO overrun error 0 No error 1 Overrun error Rx FIFO underrun error 0 No error 1
318. KMPLL 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved is the source clock of CLKOUT Controls MUKCAMO 0000 XXTI 0001 XusbXTI 0010 SCLK HDMI24M 0011 SCLK USBPHYO 0101 SCLK HDMIPHY 0110 SCLKMPLL 0111 SCLKEPLL 1000 SCLKVPLL 0 amm 4412 UM FIMC3 LCLK SEL 15 12 FIMC2 LCLK SEL FIMC1_LCLK_SEL FIMCO_LCLK_SEL SAMSUNG ELECTRONICS 5 Clock Management Unit RW Others Reserved MUXCAMO is the source clock of CAM A CLKOUT Controls MUXFIMC3_LCLK 0000 0001 XusbXTI 0010 SCLK HDMI24M 0011 SCLK USBPHYO 0101 SCLK_HDMIPHY 0110 SCLKMPLL 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved MUXFIMC3_LCLK is the source clock of FIMC3 local clock Controls MUXFIMC2_LCLK 0000 XXTI 0001 XusbXTI 0010 SCLK_HDMI24M 0011 SCLK_USBPHYO 0101 SCLK_HDMIPHY 0110 SCLKMPLL 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved MUXFIMC2_LCLK is the source clock of 2 local clock Controls MUXFIMC1_LCLK 0000 XXTI 0001 XusbXTI 0010 SCLK_HDMI24M 0011 SCLK_USBPHYO 0101 SCLK_HDMIPHY 0110 SCLKMPLL 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved MUXFIMC1_LCLK is the source clock of FIMC1 local clock Controls MUXFIMCO_LCLK 0000 XXTI 0001 XusbXTI 0010 SCLK_HDMI24M 0011 SCLK_USBPHYO 0101 SCLK_HDMIPHY 0110 SCLKMPLL 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved
319. K_HDMIPHY 0110 SCLKMPLL USER 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved MUXSPIO is the source clock of SPIO np nen Controls MUXSPDIF 00 SCLK_AUDIOO 01 SCLK AUDIO1 SPDIF SEL 9 8 10 SCLK AUDIO 11 SPDIF_EXTCLK MUXSPDIF is the source clock of SPDIF AUDIO2 Controls MUXAUDIO2 SAMSUNG ELECTRONICS 5 70 4412 UM 5 Clock Management Unit _SEL 0000 AUDIOCDCLK2 0001 Reserved 0010 SCLK HDMI24M 0011 SCLK_USBPHYO 0100 XXTI 0101 XusbXTI 0110 SCLKMPLL USER 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved MUXAUDIOZ2 is the source clock of AUDIO2 Controls MUXAUDIO1 0000 AUDIOCDCLK1 0001 Reserved 0010 SCLK HDMI24M 0011 SCLK USBPHYO AUDIO1 0100 XXTI SEL 3 0 RW 0101 XusbXTI 0110 SCLKMPLL USER T 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved MUXAUDIO1 is the source clock of AUDIO1 SAMSUNG ELECTRONICS 5 71 IT 4412 UM 5 Clock Management Unit 5 10 1 37 SRC 1 e Base Address 0x1003 0000 e Address Base Address 0xC258 Reset Value 0 0000 0000 RSVD nesen Tw Controls MUXJPEG 0 MOUTJPEG 0 JPEG SEL RW 4 MOUTJPEG 1 MUXJPEG is the source clock of JPEG core RSV GS Controls MUKJPEG 1 0 SCLKEPLL JPEG 1 SEL 4 RW 1 SCLKVPLL MUXJPEG_1 is the source clock of JPEG core 85 0 Controls MUKJPEG 0 0 SCLKMPLL_USER_T
320. Key register that specifies the color image of OSD layer is substituted by the background image either as cursor image or preview image of the camera Figure 16 26 illustrates the Color Key function configurations OSD image180 x 100 BLEND ALPHA Chroma Key KEY BLEN KEY ALPHA OxFF SAMSUNG ELECTRONICS Figure 16 26 Chroma Key KEY BLEN KEY ALPHA Ox7F BLEND ALPHA 0x00 Chroma Key KEY BLEN KEY ALPHA 0x 00 Color Key Function Configurations Chroma Key not KEY BLEN 4412 UM 16 Display Controller 16 3 5 4 Blending and Color Key Function The display controller supports simultaneous blending function with two transparency factors and Color Key function in the same window Figure 16 27 illustrates the blending and Color Key function Window 0 Window 1 Sub menu Alpha 1 100 Chroma key Alpha 0 50 Figure 16 27 Blending and Color Key Function SAMSUNG ELECTRONICS 16 33 III 4412 UM Figure 16 28 illustrates the blending decision diagram lt Transparency factor Decision gt 16 Display Controller lt Blending Equation Decision gt Stat KEY_EN N Color match KEY BLEN p KEY ALPHA T BLD PIX 1 Ap 0 y Ap ALPHA SEL ALPHA SEL 571 i 3 2 00 Y DATA 31 24 DATA 27 24 Ap DATA
321. LDI CMD9 e Address Base Address 0x02A8 Reset Value 0x0000_0000 LDI CMD10 e Address Base Address 0 02 Reset Value 0x0000 0000 LDI CMD11 LDI_CMD 23 0 Specifies LDI command SAMSUNG ELECTRONICS 16 130 IT 4412 UM 16 Display Controller 16 5 4 Gamma Lookup Table 16 5 4 1 Gamma LUT Data for 64 Step Mode e Base Address 0x11C0_0000 e Address Base Address 0x037C Reset Value 0x0010 0000 GAMMALUT 01 00 e Address Base Address 0x0380 Reset Value 0x0030 0020 GAMMALUT 03 02 e Address Base Address 0x0384 Reset Value 0x0050_0040 GAMMALUT 05 04 e Address Base Address 0x0388 Reset Value 0x0070_0060 GAMMALUT_07_06 e Address Base Address 0x038C Reset Value 0x0090_0080 GAMMALUT 09 08 e Address Base Address 0x0390 Reset Value 0 00 0 00A0 GAMMALUT 11 10 e Address Base Address 0x0394 Reset Value 0 0000 00 0 GAMMALUT_13_12 e Address Base Address 0x0398 Reset Value 0 00 0 00 0 GAMMALUT 15 14 e Address Base Address 0 039 Reset Value 0x0110_0100 GAMMALUT_17_16 e Address Base Address 0x03A0 Reset Value 0x0130 0120 GAMMALUT 19 18 e Address Base Address 0x03A4 Reset Value 0 0150 0140 GAMMALUT 21 20 e Address Base Address 0x03A8 Reset Value 0x0170 0160 GAMMALUT 23 22 e Address Base Address Reset Value 0x0190_0180 GAMMALUT 25 24 e Address Base Address 0x03B0 Reset Value 0x01B0_01A0 GAMMA
322. LUT 27 26 e Address Base Address 0x03B4 Reset Value 0x01F0 01 0 GAMMALUT 29 28 e Address Base Address 0x03B8 Reset Value 0x01F0 01E0 GAMMALUT_31_30 e Address Base Address Reset Value 0x0210 0200 GAMMALUT 33 32 e Address Base Address 0 03 0 Reset Value 0x0230_0220 GAMMALUT 35 34 e Address Base Address 0x03C4 Reset Value 0 0250 0240 GAMMALUT_37_36 e Address Base Address 0x03C8 Reset Value 0x0270_0260 GAMMALUT 39 38 e Address Base Address Reset Value 0 0290 0280 GAMMALUT 41 40 e Address Base Address 0x03D0 Reset Value 0x02B0_02A0 GAMMALUT 43 42 e Address Base Address 0x03D4 Reset Value 0200 02 0 GAMMALUT 45 44 e Address Base Address 0x03D8 Reset Value 0x02F0_02E0 GAMMALUT_47_46 e Address Base Address Reset Value 0x0310 0300 GAMMALUT_49 48 e Address Base Address 0x03E0 Reset Value 0x0330_0320 GAMMALUT_51_50 e Address Base Address 0 03 4 Reset Value 0x0350_0340 GAMMALUT 53 52 e Address Base Address 8 Reset Value 0x0370 0360 GAMMALUT 55 54 e Address Base Address Reset Value 0x0390_0380 GAMMALUT 57 56 e Address Base Address 0x03F0 Reset Value 03A0 GAMMALUT 59 58 e Address Base Address 0x03F4 Reset Value 0x03D0 03C0 GAMMALUT 61 60 e Address Base Address 0x03F8 Reset Value 0x03F0_03E0 GAMMALUT 63 62 e Address Base Address
323. M 4 General Purpose Input Output GPIO Control 4 3 3 181 EXT_INT_GRPFIXPRI_XA e Base Address 0x1100 0000 e Address Base Address 0x0B10 Reset Value 0x0000 0000 When fixed group priority mode 0 to 11 then group number should be of the highest priority 0x0 EXT_INT23 0x1 EXT_INT24 0x2 EXT_INT25 0x3 EXT_INT26 0 4 27 Highest GRP NUM 3 0 RW 0 5 EXT INT28 0 00 0x6 EXT_INT29 0x7 EXT_INT8 0x8 EXT_INT9 0x9 EXT_INT10 EXT_INT11 OxB EXT_INT12 SAMSUNG ELECTRONICS 4 247 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 182 EXT_INT23_FIXPRI e Base Address 0x1100 0000 e Address Base Address 0x0B1C Reset Value 0x0000 0000 Interrupt number of the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group 0 EXT INT23 when fixed priority 0x0 mode 0 to 7 4 3 3 183 EXT INT24 FIXPRI Base Address 0x1100 0000 e Address Base Address 0x0B20 Reset Value 0x0000 0000 Interrupt number of the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group 1 EXT INT24 when fixed priority 0x0 mode 0 to 7 4 3 3 184 EXT INT25 FIXPRI Base Address 0x1100 0000 e Address Base Address 0x0B24 Reset Value 0x0000 0000 Interrupt number of the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group 2 EXT INT25 when fixed priority 0x0 mode 0 to 7 SAMSUNG ELECTRONICS 4 248 e
324. M 5 Clock Management Unit 5 10 1 32 CLK SRC ISP e Base Address 0x1003 0000 e Address Base Address 0xC238 Reset Value 0 0000_1111 RSVD 31 16 UART ISP SPI ISP Reserved Controls MUXUART_ISP 0000 XXTI 0001 XusbXTI 0010 SCLK_HDMI24M 0011 SCLK_USBPHYO 0101 SCLK_HDMIPHY 0110 SCLKMPLL USER T 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved MUXUART_ISP is the source clock of DSIM1 Controls MUXSPI1 ISP 0000 XXTI 0001 XusbXTI 0010 SCLK HDMI24M 0011 SCLK USBPHYO 0101 SCLK HDMIPHY 0110 2 SCLKMPLL USER T 0111 2 SCLKEPLL 1000 SCLKVPLL Others Reserved MUXSPI1 ISP is the source clock SPI1 ISP Controls MUXSPIO ISP 0000 XXTI 0001 XusbXTI 0010 2 SCLK HDMI24M 0011 SCLK USBPHYO 0101 2 SCLK HDMIPHY 0110 2 SCLKMPLL USER T 0111 2 SCLKEPLL 1000 SCLKVPLL Others Reserved MUXSPIO ISP is the source clock of SPIO ISP Controls MUXPWM ISP 0000 XXTI 0001 XusbXTI 0010 2 SCLK HDMI24M 0011 2 SCLK USBPHYO 0101 2 SCLK HDMIPHY 0110 2 SCLKMPLL USER T 0111 2 SCLKEPLL 1000 SCLKVPLL SPIO ISP PWM ISP SAMSUNG ELECTRONICS 5 63 4412 UM 5 Clock Management Unit Others Reserved MUXPWM_ISP is the source clock of PWM ISP SAMSUNG ELECTRONICS 5 64 ex 4412 UM 5 10 1 33 CLK SRC MAUDIO e Base Address 0x1003 0000 Address Base Address 0xC23C Reset Value 0x0000 0005 ame mw ma AU
325. MMD 7 0 NAND flash memory command value 10 7 2 4 NFADDR e Base Address OXOCEO 0000 e Address Base Address 0x000C Reset Value 0x0000 0000 REG ADDR 7 0 NAND flash memory address value 10 7 2 5 NFDATA e Base Address OXOCEO 0000 e Address Base Address 0x0010 Reset Value 0x0000 0000 flash Read program data value for I O NFDATA 31 0 RW NOTE Refer to 10 4 1 Data Register Configuration for more 0x00000000 information 10 7 2 6 NFMECCD e Base Address OXOCEO 0000 e Address Base Address 0x0014 Reset Value 0x0000 0000 avo eza aa os 2 ECCDatat 1 23 16 RW NOTE In software mode read this register when you need to read 27 ECC value from NAND flash memory ma o 1 ECC ECCData0 7 0 RW NOTE In software mode read this register when you need to ECCO read 1 ECC value flash memory This register has the similar Read function as NFDATA NOTE It allows only word access SAMSUNG ELECTRONICS 10 20 27 4412 UM 10 NAND Flash Controller 10 7 2 7 NFMECCD1 e Base Address OXOCEO 0000 e Address Base Address 0x0018 Reset Value 0x0000 0000 Ro ma eee om 4 ECC ECCData3 ECC3 23 16 RW NOTE In software mode read this register when you need to 0x00 read 4 ECC value from NAND flash memory RSVD 15 8 Reserved 3 ECCData2 7 0 RW NOTE In s
326. MSUNG ELECTRONICS 14 5 II 4412 UM 14 Inter Integrated Circuit 14 4 3 ACK Signal Transmission To complete a 1 byte transfer operation the receiver sends bit to the transmitter The pulse appears at the ninth clock of the SCL line The 12C master device generates eight clock cycles to transmit or receive 1 byte data The master generates clock pulse that is required to transmit the ACK bit When the transmitter receives ACK clock pulse it sets the SDA line to High to release the SDA line The receiver drives the SDA line Low during the ACK clock pulse to keep the SDA Low This happens during the High period of the ninth SCL pulse The software I2CSTAT enables or disables ACK bit transmit function However the pulse on the ninth clock of SCL should complete the 1 byte data transfer operation Figure 14 5 illustrates the acknowledgement on the I2C bus Data Output by Transmitter Data Output by Receiver SCL from Master Condition Clock Pulse for Acknowledgment Figure 14 5 Acknowledgement on the I2C Bus SAMSUNG ELECTRONICS 14 6 II 4412 UM 14 Inter Integrated Circuit 14 4 4 Read Write Operation When the 2 controller transmits data in transmitter mode the I2C bus interface waits until I2C bus Data Shift I2CDS register receives the new data Before you write new data to the register the SCL line is held Low 12C controller releases the SCL line after you w
327. MSUNG ELECTRONICS 4 342 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 68 PDNEN Base Address Ox106E 0000 e Address Base Address OxOF80 Reset Value 0x00 Nae 0 Automatically by power down mode Am I By PONEN BI W Power down mode pad state enable register 0 PADs Controlled by normal mode 1 PADs Controlled by Power Down mode control registers PDNEN R This bit is set to 1 automatically when system enters into Power down mode and clears by writing 0 to this bit or cold reset After wake up from Power down mode this bit maintains value 1 until writing O SAMSUNG ELECTRONICS 4 343 4412 UM 5 Clock Management Unit Clock Management Unit 5 1 Overview This chapter describes the Clock Management Units 5 of Exynos 4412 CMUs control Phase Locked Loops PLLs and generate system clocks for CPU buses and function clocks for individual IPs in Exynos 4412 They also communicate with the power management unit PMU in order to stop clocks before entering certain low power mode to reduce power consumption by minimizing clock toggling 5 2 Clock Domains In Exynos 4412 it clocks the function blocks asynchronously with each other to provide a wider choice of operating frequencies It also eases physical implementation e CPU block consists of the Cortex A9 MPCore processor 12 cache controller and CoreSight operates at voltage levels of 0 875 V to
328. Management Unit 5 10 1 11 CLK DIV RIGHTBUS e Base Address 0x1003 0000 e Address Base Address 0x8500 Reset Value 0x0000 0000 RSV 99 DIVGPR Clock Ratio PRORA ACLK_GPR MOUTGPR GPR_RATIO 1 Lomo DIVGDR Clock Divider Ratio GOR RATIO ACLK_GDR MOUTGDR GDR_RATIO 1 5 10 1 12 CLK DIV STAT RIGHTBUS e Base Address 0x1003 0000 e Address Base Address 08600 Reset Value 00000 0000 ASV up DIVGPR Status DIV_GPR 4 0 Stable 1 Status that the divider is changing 86 0 Rem fo DIVGDR Status DIV GDR 0 0 Stable 1 Status that the divider is changing SAMSUNG ELECTRONICS 5 41 ex 4412 UM 5 Clock Management Unit 5 10 1 13 CLK GATE IP RIGHTBUS e Base Address 0x1003 0000 e Address Base Address 08800 Reset Value OxFFFF_FFFF Gating all clocks for ASYNC_ISPMX CLK_ASYNC_ISPMX RW 0 Mask 1 Pass mv fm eea Gating all clocks for ASYNC_MAUDIOX CLK_ASYNC_MAUDIOX 7 0 Mask 1 Pass Gating all clocks for ASYNC_MFCR CLK_ASYNC_MFCR 0 Mask 1 Pass Gating all clocks for ASYNC_FSYSD CLK_ASYNC_FSYSD 5 0 Mask 1 Pass CLK_ASYNC_LCDOX E a Gating all clocks for ASYNC LCDOX 3 RW 0 Mask 0 1 1 Pass Gating all clocks for _ CLK_ASYNC_CAMX 2 RW 0 Mask 0 1 1 Pass Gating all clocks for PPMURIGHT CLK_PPMURIGHT 1 RW 0x1 0 Mask 1 Pass Gating all clocks for GPIO
329. Masks 1 Enables SAMSUNG ELECTRONICS 7 11 4412 UM 7 Interrupt Combiner 7 6 2 3 ISTRO Base Address 0x1044 0000 e Address Base Address 0x0008 Reset Value Undefined ASVD mesen ISP R PMUIRQ_ISP 29 Ce 5 PMUIROISP 129 pending status 28 EE The corresponding interrupt enable bit does not __ nCTIIRQ 1 27 affect this pending status ER PMUIR 1 26 0 The interrupt is pending ___ 1 The interrupt is pending PARITYFAILSC 1 25 Ce RSVD py Reed fom PARRINTR R A PARRDINTR 21 Interrupt pending status 20 E The corresponding interrupt enable bit does not ___ nCTIIRQ 0 19 affect this pending status PMUIRQ 0 18 0 The interrupt is not pending 1 The interrupt is pending PARITYFAILSCU O 17 RSVD psum Reewd fom TZASC1 1 11 Interrupt pending status TZASCH 0 10 The corresponding interrupt enable bit does not MI affect this pending status TAS o R 0 The interrupt is not pending TZASCO 0 dB R 1 Theinterruptis pending ASV een RSVD 4 Interrupt pending status RSVD J R The corresponding interrupt enable bit does not RSVD m affect this pending status 0 The interrupt is not pending RSVD n 1 The interrupt is pending SAMSUNG ELECTRONICS 7 12 en 4412
330. N 1 0x0874 External interrupt EXT INT15 filter configuration register 1 0x0000 0000 EXT INT16 FLTCONO 0x0878 External interrupt EXT INT16 filter configuration register 0 0x0000 0000 EXT INT16 FLTCON1 0x0000 0000 EXT INT21 FLTCONO 0x0000 0000 EXT 21 FLTCON1 0x0000 0000 EXT INT22 FLTCONO 0 0000 0000 EXT INT22 0x0000 0000 EXT INT1 MASK 0x0900 External interrupt EXT mask register 0x0000_00FF 6 5 0 0914 External interrupt EKT 6 mask register 0 0000 000 INT7 5 0 0918 External interrupt EXT_INT7 mask register 0x0000_000F EXT_INT13_MASK 0x0930 External interrupt EXT_INT13 mask register 0x0000_00FF EXT_INT14_MASK 0x0934 External interrupt EXT_INT14 mask register 0x0000_00FF EXT_INT15_MASK 0x0938 External interrupt EXT_INT15 mask register 0x0000_00FF SAMSUNG ELECTRONICS 4 8 4412 UM 4 General Purpose Input Output GPIO Control Rase CS 2 0x0B08 Current service register 0x0000_0000 EXT_INT_SERVICE _ _ OxOBOC Current service pending register 0x0000_0000 0x0B10 External interrupt group fixed priority control register 0x0000_0000 SAMSUNG ELECTRONICS 4 9 en 4412 UM 4 General Purpose Input Output GPIO Control e Base Address 0x1100 0000 Por group GPKO power down mode configuration regster GPKOCONPDN 0x0050 Port group power down mode configuration regist
331. OSD_RightBotY_F 10 0 RW For interlace TV output this value should be set to half of the original screen y coordinate The original screen y coordinate should be odd value NOTE Registers should have word boundary X position Therefore 24 BPP mode should have X position by 1 pixel For example 0 1 2 3 16 BPP mode should have X position by 2 pixel For example X 0 2 4 6 8 BPP mode should have X position by 4 pixel For example X 0 4 8 12 16 5 3 18 VIDOSDOC e Base Address 0x11C0_0000 e Address Base Address 0x0048 Reset Value 0x0000_0000 Reserved RSVD 25 84 ES NOTE This bit should be set to 0 91 Specifies the Window Size EVI For example Height x Width number of word SAMSUNG ELECTRONICS 16 85 ex 4412 UM 16 Display Controller 16 5 3 19 VIDOSDOC e Base Address 0x11C0_0000 e Address Base Address 0x0050 Reset Value 0x0000_0000 OSD LeftTopX F 21 11 RW Specifies Horizontal screen coordinate for left top pixel of OSD image Specifies Vertical screen coordinate for left top pixel of OSD image OSD LeftTopY F 10 0 interlace TV output this value should be set to half of the original screen y coordinate The original screen y coordinate should be even 16 5 3 20 VIDOSD1B e Base Address 0x11C0_0000 e Address Base Address 0x0054 Reset Value 0x0000_0000 OSD RightBotX F 21 11 Specifies
332. Ox9FF for clock gating control Clock gating of IPs and function blocks e Use 0xA00 to OxAFF for CLKOUT CLKOUT input clock selection and divider ratio NOTE The CLK GATE IP XXX registers in the CMU LEFTBUS and CMU RIGHTBUS are located at 0x800 Additionally some CMUS use addresses beyond OxAFF for other functions such as CPU control functions in CMU CPU Refer to register description for more information SAMSUNG ELECTRONICS 5 24 ex 4412 UM 5 Clock Management Unit In Figure 5 4 XXX in the register name shall be replaced with the function block name e LEFTBUS RIGHTBUS TOP CAM TV MFC G3D IMAGE LCDO LCD1 MAUDIO FSYS PERIL and PERIR Figure 5 4 illustrates the Exynos 4412 clock controller address 0x1003_4000 xPLL_LOCK PLL lock time xPLL_CON PLL control 0x1003_8000 CLK SRC KKK selection CLK SRC MASK KKK output masking 0x1003_C000 CLK_MUX_STAT_XXX Mux status CLK_DIV_XXX Divider ratio 0x1004_0000 CLK_DIV_STAT_XXX Divider status Reserved 0 1004_4000 Reserved CLK GATE IP clock gating 0x1004 8000 CLKOUT CMU XXX CLKOUT control CMU ISP XXX function block name Figure 5 4 Exynos 4412 Clock Controller Address SAMSUNG ELECTRONICS 5 25 IT 4412 UM 5 Clock Management Unit 5 10 1 Register Map Summary e Base Address 0x1003 0000 Register SRC LEFTBUS 04200 Selects clock source for CMU
333. P e Base Address 0x11C0_0000 e Address Base Address 0x0190 Reset Value 0x0000_ 0000 Specifies color mapping of window control bit If it enables this bit then Video DMA stops and MAPCOLEN F 24 RW MAPCOLOR appears on background image instead of original image 0 Disables 1 Enables MAPCOLOR 23 0 Specifies color value 16 5 3 56 WPALCON H e Base Address 0x11C0_0000 e Address Base Address 0x019C Reset Value 0x0000_0000 Mame te nD Jema A vo Reseved AN CAI CO aw WPA wpaq AN np SAMSUNG ELECTRONICS 16 105 27 4412 UM 16 Display Controller 16 5 3 57 WPALCON L e Base Address 0x11C0_0000 e Address Base Address 0x01A0 Reset Value 0x0000 0000 RSVD 31 23 PALUPDATEEN L Reserved 0 Normal Mode 1 Enables Palette Update EN CA wean A weno 00 wer 9 weni a ew wenen 9 or 9 NOTE 1 WPALCON WPALCON H WPALCON Lj 0 Normal Mode FALUEDATEEN 1 Enables Palette Update Specifies size of palette data format of Window 4 000 16 bit 5 6 5 001 16 bit 5 5 5 010 18 bit 6 6 6 WAPAL 3 0 011 18 bit A 6 6 5 100 19 bit A 6 6 6 101 24 bit 8 8 8 110 25 bit A 8 8 8 111 32 bit 8 8 8 8 A 8 bit Specif
334. P block They control clock source selection clock divider ratio and clock gating SAMSUNG ELECTRONICS 5 34 ex 4412 UM 5 Clock Management Unit 5 10 1 1 CLK SRC LEFTBUS e Base Address 0x1003 0000 e Address Base Address 04200 Reset Value 0x0000 0000 RSV erst nesen 0 Controls MUXMPLL MPLL USER SEL L 4 RW 0 FINPLL 1 FOUTMPLL RSVD Reseved iL Controls MUXGDL GDL SEL RW 0 SCLKMPLL 1 SCLKAPLL 5 10 1 2 CLK_MUX_STAT_LEFTBUS Base Address 0x1003_0000 e Address Base Address 0x4400 Reset Value 0x0000_0011 RSVD an 9 Selection Signal Status of MUXMPLL MPLL USER SEL 6 4 en 1xx Status that the mux is changing SE most om Selection Signal Status of MUXGDL A 001 SCLKMPLL GDE SEL 2 0 010 SCLKAPLL 1xx Status that the mux is changing SAMSUNG ELECTRONICS 5 35 ex 4412 UM 5 Clock Management Unit 5 10 1 3 CLK DIV LEFTBUS e Base Address 0x1003 0000 e Address Base Address 04500 Reset Value 0x0000 0000 RSV au o DIVGPL Clock Divider Ratio SPL RATIO ACLK GPL MOUTGPL GPL_RATIO 1 DIVGDL Clock Divider Ratio ACLK_GDL MOUTGDL GDL RATIO 1 5 10 1 4 CLK_DIV_STAT_LEFTBUS Base Address 0 1003 0000 e Address Base Address 04600 Reset Value 000 0000 RSV reme DIVGPL Status DIV GPL 4 0 Stable
335. PHAO SAMSUNG ELECTRONICS 16 123 ex 4412 UM 16 Display Controller 16 5 3 79 VIDW4ALPHA1 e Base Address 0x11C0_0000 e Address Base Address 0x0240 Reset Value 0x0000_0000 Nam Type Description Reset Value ts Ree 9 19 16 Specifies Red Alpha lower value case AEN 1 o Reseved fo 11 8 Specifies Green Alpha lower value case 1 fiaj ALPHAT B L F 3 0 Specifies Blue Alpha lower value case AEN 1 0 7 4 ALPHA1_R B _H 3 0 at VIDOSD4C NOTE ALPHA1_R G B B 3 0 ALPHA1_R G L 3 0 at VIDW4ALPHA1 ALPHA1_R G SAMSUNG ELECTRONICS 16 124 IT 4412 UM 16 Display Controller 16 5 3 80 BLENDEQ1 e Base Address 0x11C0_0000 e Address Base Address 0x0244 Reset Value 0x0000_00C2 Specifies constant that it uses in alphaB alpha value of background 1 0000 0 zero 0001 1 maximum 0010 alphaA 2 alpha value of foreground 1 0011 1 alphaA 0100 alphaB 0101 1 alphaB Q FUNC F 21 18 RW 0110 ALPHAO 0111 Reserved 100x Reserved 1010 A foreground color data 1011 1 1100 background color data 1101 1 111 RSVD 17 16 Specifies the constant that it uses in alpha P 15 12 RW li Same as above see COEF_Q mo tio Specifies the constant
336. PL330 TRM for more information Specifies the debug instruction 0 register Refer page 3 BEGINS TO 0 8 38 of PL330 for information Specifies the debug instruction 1 register Refer to page 3 KODO 39 of 30 for more information Undetined Specifies the configuration register 0 Refer to page 3 40 of n PL330 more information Specifies the configuration register 1 Refer to page 3 42 of PL330 for more information O O SAMSUNG ELECTRONICS 8 11 4412 UM 8 Direct Memory Access Controller DMAC Specifies the configuration register 2 Refer to page 3 43 of PL330 TRM for more information Specifies the configuration register 3 Refer to 3 44 of 0 0 PL330 for more information Specifies the configuration register 4 Refer to page 3 45 of PL330 TRM for more information Specifies the configuration register Refer to 3 46 of PL330 TRM for more information eriph id n OxOFEO to Specifies the peripheral identification registers 0 3 Refer to Configuration _10_ OxOFEC page 3 48 of PL330 for more information dependent cell id n OxOFFO to Specifies the primecell identification registers 0 3 Refer to Configuration poet 10 OxOFFC page 3 50 of PL330 for more information dependent NOTE The SFR description shows on
337. RT 2 is the source clock of UART2 Controls MUXUART1 0000 0001 XusbXTI UART1 SEL 7 4 Rw 0010 SCLK HDMI24M 0011 SCLK USBPHYO 0101 SCLK_HDMIPHY 0110 SCLKMPLL_USER_T 0111 SCLKEPLL SAMSUNG ELECTRONICS 5 68 4412 UM 5 Clock Management Unit 1000 SCLKVPLL Others Reserved MUXUART 1 is the source clock of UART1 Controls MUXUARTO 0000 XXTI 0001 XusbXTI 0010 SCLK HDMI24M 0011 SCLK USBPHYO UARTO SEL 3 0 RW 0101 SCLK HDMIPHY 0110 SCLKMPLL USER T 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved MUXUARTO is the source clock of UARTO SAMSUNG ELECTRONICS 5 69 IT 4412 UM 5 Clock Management Unit 5 10 1 36 CLK SRC PERILI Base Address 0x1003 0000 e Address Base Address 0xC254 Reset Value 0x0111 0055 av Controls MUXSPI2 0000 XXTI 0001 XusbXTI 0010 SCLK HDMI24M 0011 SCLK USBPHYO SPI2 SEL 27 24 RW 0101 SCLK HDMIPHY 0110 2 SCLKMPLL USER T 0111 2 SCLKEPLL 1000 SCLKVPLL Others Reserved MUXSPI2 is the source clock SPI2 Controls MUXSPI1 0000 XXTI 0001 XusbXTI 0010 SCLK_HDMI24M 0011 SCLK_USBPHYO SPI1_SEL 23 20 RW 0101 SCLK_HDMIPHY 0110 SCLKMPLL_USER_T 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved MUXSPI1 is the source clock of SPI Controls MUXSPIO 0000 XXTI 0001 XusbXTI 0010 SCLK_HDMI24M 0011 SCLK USBPHYO SPIO SEL 19 16 RW 0101 SCL
338. RW 01 Buffer set to 1 10 Buffer set to 2 NOTE BUFSTATUS BUFSTATUS H BUFSTATUS L Selects Buffer set 00 Buffer set to 0 01 Buffer set to 1 PUES 30 10 Buffer set to 2 only available when BUF MODE 1 b1 NOTE BUFSEL BUFSEL H BUFSEL 1 Enables CSC source limiter for clamping xvYCC source 0 Disables 29 1 Enables when local SRC data has xvYCC color space InRGB 1 Controls CSC parameter 0 Equation 601 EQ7 2 om 28 1 Equation 709 when local SRC data has HD 709 color gamut Chooses color space conversion equation from YCbCr to RGB based on the input value range 2 00 for YCbCr wide nWide Narrow 27 26 range and 2 11 for YCbCr narrow range Wide Range Y Cb Cr 255 0 Narrow Range Y 235 16 Cb Cr 240 16 85 0 Selects local path source LOCALSEL F 23 RW 0 CAMIF2 1 CAMIF3 Selects Data access method ENLOCAL_F 22 RW 0 Dedicated DMA 1 Local Path Specifies Buffer Status read only 21 NOTE BUFSTATUS BUFSTATUS_H BUFSTATUS_L Selects Buffer set 20 NOTE BUFSEL BUFSEL H BUFSEL L Specifies Double Buffer Auto control bit BUFAUTOEN 19 RW 0 Fixed by BUFSEL 1 Auto changed by Trigger Input BITSWP F 18 RW Species the Bit swap control bit 0 Disables swap iL SAMSUNG ELECTRONICS 16 72 4412 UM 16 Display Controller 1 Enables swap NOTE Setitto 0 when ENLOCAL is 1 Specifies Byte swaps c
339. RW Filtering width of EXT INT50 0 4 3 4 9 50 1 e Base Address 0x0386 0000 e Address Base Address 0 0804 Reset Value 0 0000 0000 RSV eee Filter Enable for EXT_INT50 6 FLTEN 1 6 23 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH1 6 22 16 Filtering width of EXT INT50 6 Filter Enable for EXT INT50 5 FLTEN1 5 15 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH1 5 14 8 Filtering width of EXT_INT50 5 Filter Enable for EXT INT50 4 FLTEN1 4 7 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH1 4 6 01 RW Filtering width of 1 5014 SAMSUNG ELECTRONICS 4 294 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 4 10 EXT_INT50_MASK e Base Address 0x0386 0000 e Address Base Address 0x0900 Reset Value 0x0000 007F EXT INT50 o 2 interrupt EXT INT50 MASK 5 5 2 Fleten EXT 50 MASK 4 4 E 2 5 Sas m pw Este non EXT 50 MASK 2 2 Sn 0 0 Enables Interrupt EXT INT50 MASK 1 1 0x1 Masked 0 0 Enables Interrupt EXT INT50 MASK 0 0 1 Masked 4 3 4 11 EXT_INT50_PEND Base Address 0x0386 0000 e Address Base Address 0x0AO00 Reset Value 0x0000 0000 RSVD Reserved 0x0000000 0 0 Not occur A 0x1 Interrupt Occurs 0x0 Not occur rl Nad PENDS 5 0 1 Inter
340. Reserved 990 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 137 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 25 GPLOCON Base Address 0x1100 0000 e Address Base Address 0 00 0 Reset Value 0x0000 0000 0 0 Input 0 1 Output GPLOCON 6 27 24 RW 0x2 GNSS RF RSTN 0 00 0 3 to Reserved OxF EXT_INT27 6 0 0 Input 0 1 Output GPLOCON 5 23 20 RW 0x2 to Reserved 0x00 OxF EXT_INT27 5 0x0 Input 0x1 Output GPLOCON 4 19 16 RW 0x2 GNSS_QMAG 0 00 0 3 to Reserved OxF EXT INT27 4 0 0 Input 0 1 Output GPLOCON 3 15 12 RW 0 2 GNSS QSIGN 0 00 0x3 to Reserved EXT INT27 3 0 0 Input 0 1 Output GPLOCON 2 11 8 RW 0x2 GNSS_IMAG 0 00 0x3 to Reserved OxF EXT_INT27 2 0 0 Input 0 1 Output GPLOCON 1 7 4 RW 0 2 GNSS ISIGN 0x00 0x3 to OxE Reserved OxF EXT INT27 1 0 0 Input 0 1 Output GPLOCON 0 3 0 RW 0 2 GNSS SYNC 0 00 0x3 to Reserved OxF EXT_INT27 0 SAMSUNG ELECTRONICS 4 138 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 26 GPLODAT Base Address 0x1100 0000 e Address Base Address 0x00C4 Reset Value 0 00 When you configure port as input port then corresponding bit is pin state When configuring as GPLODATT 6 0 RWX output port the pin state should be same as the 0 00 corresponding
341. S 16 41 ex 4412 UM 16 Display Controller 16 3 8 2 LCD RGB Interface Timing Figure 16 30 illustrates the LCD RGB interface timing INT_FrSyn VSYNC HSYNC VDEN LINEVAL 1 HII X X XX XX ri E gt gt lt lt HSPW 1 HBPD 1 HOZVAL 1 Figure 16 30 LCD RGB Interface Timing SAMSUNG ELECTRONICS 16 42 ex 4412 UM 16 Display Controller 16 3 9 LCD Indirect i80 System Interface LCD Indirect 180 System Interface includes e Signals e Indirect i80 System Interface Write Cycle Timing 16 3 9 1 Signals Table 16 3 describes the signals Table 16 3 LCD Indirect i80 System Interface Signals of Display Controller Display Controller In Out Description GPIO Control FAddress oupa emal Connection Data bit 12 2 0 o0 o NEAN SAMSUNG ELECTRONICS 16 43 IT 4412 UM 16 Display Controller NOTE 1 SYS ST SYS ADD 1 is valid DSI Mode VIDCONO 30 1 SYS ADD 1 SYS ST 0 when VDOUT is from Frame SYS_ADD 1 SYS_ST 1 when VDOUT is from Command 2 While using RGB interface set the LBLKx bit fields in LCDBLKC_CFG 0x1001_0210 register to i80 interface out 2 b01 even though you use 051 Command Mode SAMSUNG ELECTRONICS 16 44 IT 4412 UM 16 Display Controller 16 3 9 2 Indirect i80 Syst
342. SBXTO pins XXTI Specifies the clock from external oscillator with pins The input frequency ranges from 12 to 50 MHz When is not used it should be pulled down XUSBXTI Specifies the clock from crystal pad with XUSBXTI and XUSBXTO pins XUSBXTI and XUSBXTO use wide range OSC pads This clock is supplied to the USB PHY and the phase locked loops namely APLL MPLL VPLL and EPLL Refer to Chapter 36 USB HOST and Chapter 37 USB DEVICE for more information We recommend using 24 MHz crystal as the ROM design is based on the 24 MHz input clock lt requires parallel resistance of 5 between the XUSBXTI and XUSBXTO pins SAMSUNG ELECTRONICS 5 3 ex 4412 UM 5 Clock Management Unit 5 3 2 Clocks from CMU CMUs generate internal clocks with intermediate freguencies using from clocks from the clock pads They are e Clock pads namely XRTCXTI and XUSBXTI e Four PLLs namely APLL EPLL and e USB PHY and HDMI PHY Some of these clocks are selected pre scaled and provided to the corresponding modules We recommend using 24 MHz input clock source for APLL MPLL EPLL and VPLL The components to generate internal clocks are e APLL uses FINPLL as input to generate frequencies from 22 to 1400 MHz e MPLL uses FINPLL as input to generate frequencies from 22 to 1400 MHz e EPLL uses FINPLL as input to generate frequencies from 22 to 1400 MHz This PLL generates 192 MHz
343. SCUEVABORT 1241 R RSVD EX 0 RSVD 21 Interrupt pending status RSVD 20 The corresponding interrupt enable bit does not affect EBEN 0 sd a 19 0 The interrupt is not pending RSVD 18 NN 1 The interrupt is pending LE RSVD e RSVD He RSVD nIRQOUT 13 P ow I CPU nIRQOUT O 13 pending status RSVD 12 EN The corresponding interrupt enable bit does not affect RSVD 11 EN this pending status RSVD 10 0 The interrupt is pending 1 The interrupt is pending RSVD gg RSVD MEMES IKUY The corresponding interrupt enable bit does not affect this pending status 0 The interrupt is not pending n 1 The interrupt is pending I R SAMSUNG ELECTRONICS 7 24 4412 UM 7 Interrupt Combiner 7 6 2 16 IMSR3 e Base Address 0x1044 0000 e Address Base Address 0x003G Reset Value Undefined Nae Bit Twe Desorption Reset Value DEGERRINTR a SLVERRINTR Bo R SN lt i ERRRDNTR 29 R Masked interrupt pending status Dhe FERRRTINTR 28 E interrupt enable bit is 0 the IMSR ERRWDINTR 27 0 The is not pending ERRWTINTR 29 R 1 The interrupt is pending EGNTRINTR ES R ES a R F j Rv Eo CPU
344. SUNG ELECTRONICS 16 54 4412 UM 16 Display Controller VIDWOOADDO Ox40A0 o window 0 5 buffer start address register 0x0000 0000 SHD_VIDWO1ADDO 0x40A8 window 1 s buffer start address register 0 0000_0000 VIDWO2ADDO 0 40 0 4 window 2 s buffer start address register 0x0000 0000 VIDWO3ADDO 0x40B8 window 3 s buffer start address register 0 0000_0000 SHD_VIDWO4ADDO 0 40 0 ba window 4 s buffer start address register 0x0000 0000 SHD_VIDWOOADD1 0 4000 Specifies window 0 s buffer end address register shadow 0 0000_0000 SHD_VIDWO1ADD1 0 4008 Specifies window 1 s buffer end address register shadow 0 0000_0000 VIDWO2ADD1 Ox40E0 window 2 s buffer end address register 0x0000 0000 VIDWO3ADD1 0x40E8 SEN window 3 s buffer end address register 0x0000 0000 VIDWO4ADD1 SE window 4 s buffer end address register 0x0000 0000 SAMSUNG ELECTRONICS 16 55 IT 4412 UM 16 Display Controller 16 5 2 Palette Memory e Base Address 0x11C0_0000 0 2400 0 27 Win0 PalRam 0x0400 0x07FC Specifies 0 to 255 entry palette data Undefined 0x2800 Ox2BFC Win1 PalRam 0x0800 Specifies O to 255 entry palette data Undefined Win2 PalRam 0 2 00 Ox2FFC Specifies 0 to 255 entry palette data Undefined Win3 PalRam 0x3000 0x33FC Specifies O to 255 entry palette data Undefined Win4 PalRam 0x3400 0 37 Specifies 0 to 255 e
345. SUNG ELECTRONICS 4 101 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 122 EXT_INT3_MASK e Base Address 0x1140_0000 e Address Base Address 0x0908 Reset Value 0x0000_00FF 0 0 Enables interrupt EXT MASK 7 7 0 1 Masked 0 1 0 0 Enables interrupt 0 0 Enables interrupt EXT_INT3_MASKT 5 5 0x1 Masked 0x1 EXT INT3 MASK 3 3 EXT INT3 MASK 2 2 EXT INT3 MASK 1 EXT INT3 MASK 0 MUS SAMSUNG ELECTRONICS 4 102 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 123 EXT_INT4_MASK e Base Address 0x1140_0000 e Address Base Address 0 090 Reset Value 0x0000_001F 0 0 Enables interrupt EXT INT4 MASK 4 4 0 1 Masked 0 1 0 0 Enables interrupt EXT INT4 MASK 3 3 0 1 Masked 0 1 0 0 Enables interrupt EXT INT4 MASK 2 2 0 1 Masked 0 1 0 0 Enables interrupt 0 0 Enables interrupt 4 3 2 124 EXT_INT5_MASK Base Address 0x1140_0000 e Address Base Address 0x0910 Reset Value 0x0000_001F 0 0 Enables interrupt EXT_INT5_MASK 4 4 0 1 Masked 0 1 0 0 Enables interrupt EXT INT5 MASK 3 3 0 1 Masked 0 1 0 0 Enables interrupt EXT INT5 MASK 2 2 0 1 Masked 0 1 0 0 Enables interrupt 0 0 Enables interrupt SAMSUNG ELECTRONICS 4 103 x 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 125
346. SUNG ELECTRONICS 4 17 en 4412 UM 4 General Purpose Input Output GPIO Control Por group GPV pullupiput GPV2PUD 0x0068 Port group GPV2 pull up pull down register 0x5555 GPV2DRV 0 006 Port group GPV2 drive strength control register 0x00_0000 GPV2CONPDN 0x0070 Port group GPV2 power down mode configuration register 0 0000 GPV2PUDPDN 0x0074 2 GPV2 power down mode pull up pull down 0 0000 Por group power down mode configuration register GPV3CONPDN 0x0090 Port group GPV3 power down mode configuration register 0 0000 GPV3PUDPDN 0x0094 power down mode pull up pull down 050000 ETC8PUD 0x00A8 Port group ETC8 pull up pull down register 0 0005 ETC8DRV 0x00AC Port group ETC8 drive strength control register 0x00_0000 GPV4CON 0x00CO Port group GPV4 configuration register 0x0000_0000 GPV4DAT 0x00C4 Port group GPV4 data register 0 00 GPV4PUD 0x00C8 Port group GPV4 pull up pull down register 0x0005 GPV4DRV Ox00CC Port group GPV4 drive strength control register 0x00_0000 GPV4CONPDN 0 0000 Port group GPV4 power down mode configuration register 0 0000 GPV4PUDPDN 0 0004 s GPV4 power down mode pull up pull down 0x0000 EXT INT30 CON 0x0700 External interrupt INT30 configuration register 0x0000 0000 EXT INT31 CON 0x0704 External interrupt EXT INT31 configuration register 0x0000 0000 EXT INT32 CON 0x0708 External interrupt INT32 configuration register
347. SUNG ELECTRONICS 4 237 ex 4412 UM 4 3 3 167 EKT INT23 PEND e Base Address 0x1100 0000 e Address Base Address 0x0A08 Reset Value 0x0000 0000 RSVD EXT 23 PEND 6 EXT INT23 PEND 5 EXT INT23 PEND 4 EXT INT23 PEND 3 EXT INT23 PEND 2 EXT INT23 PEND 1 EXT 23 PEND 0 Base Address 0x1100 0000 e Address Base Address Reset Value 0x0000 0000 RSVD EXT 24 PEND 6 EXT 24 PEND 5 EXT INT24 EXT INT24 PEND 3 EXT INT24 PEND 2 EXT INT24 PEND 1 EXT INT24 PEND 0 5 4 3 2 1 RWX RWX RWX RWX 4 3 3 168 EXT_INT24_PEND 5 4 3 2 1 RWX RWX RWX SAMSUNG ELECTRONICS 4 General Purpose Input Output GPIO Control 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs Reserved 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 4 238 0x0000000 7
348. Samsung 4 Guad Exynos 4412 RISC Microprocessor Revision 1 00 October 2012 User s Manual SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS INFORMATION AND SPECIFICATIONS WITHOUT NOTICE Products and specifications discussed herein are for reference purposes only All Informa tion discussed herein is provided on an AS IS basis without warranties of any kind This document and all Infogpat roperty of Samsung ms t 2012 Samsung Electronics Co Ltd All rights reserved SAMSUNG ELECTRONICS ITU Important Notice Samsung Electronics Co Ltd Samsung reserves the right to make changes to the information in this publication at any time without prior notice All information provided is for reference purpose only Samsung assumes no responsibility for possible errors omissions Or for any conseguences resulting from the use of the information contained herein This publication on its own does not convey any license either express or implied relating to any Samsung and or third party products under the intellectual property rights of Samsung and or any third parties Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitatio
349. Selects ALPHA1 When it sets per pixel blending then this pixel blends with alpha value that selects SFR selects the alpha value as ALPHAO ALPHAO ALPHAO_B ALPHA1_R ALPHA1_G and ALPHA1 For more information refer to the section on SFR 2 D 6 5 Red data D 4 2 Green data and D 1 0 Blue data SAMSUNG ELECTRONICS 16 19 II 4412 UM 16 Display Controller 16 3 3 2 11 8 BPP Display Palette Figure 16 16 illustrates the 8 BPP display BYSWP 0 HWSWP 0 WSWP 0 D 63 56 D 55 48 0 47 40 3934 31 24 D 23 16 D 15 8 000H P1 P2 P3 P4 P5 P6 P7 008H P9 P10 P11 P12 P13 P14 P15 010H P 18 P22 BYSWP 1 HWSWP 0 WSWP 0 0 63 56 L 55 48 D 47 40 32 D 31 24 000H P8 P7 P6 P4 008H 16 15 P14 12 010H P24 22 20 P Pe P7 Ps Po P1o P11 Pr2 LCD Panel Figure 16 16 Memory Format of 8 BPP Display NOTE AEN Specifies the transparency value selection bit with WPALCON Palette output format AEN 0 Selects ALPHAO AEN 1 Selects ALPHA1 When it sets per pixel blending then this pixel blends with alpha value that AEN selects SFR selects the alpha value as ALPHAO_R ALPHAO_G ALPHAO_B ALPHA1_R ALPHA1_G and ALPHA1_B For more information refer to the section on SFR SAMSUNG ELECTRONICS 16 20 II 4412 UM 16 Display Co
350. T ETC6PUD 3 2 controls XCLKOUT ETC6PUD 5 4 controls XnRSTOUT ETC6PUD 9 8 controls XRTCCLKO ETC6PUD 1 1 10 controls XuotgDRVVBUS ETC6PUD 13 12 controls XuhostPWREN ETC6PUD 15 14 controls XuhostOVERCUR SAMSUNG ELECTRONICS 4 171 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 88 ETC6DRV Base Address 0x1100 0000 e Address Base Address 0x022C Reset Value 0x00 0000 23 16 Reserved Should be zero W ETC6DRV n I n 2n 1 2n R 0x0000 0107 ETC6DRV 1 0 controls XnRESET ETC6DRV 3 2 controls XCLKOUT ETC6DRV 5 4 controls XnRSTOUT ETC6DRV 7 6 controls XnWRESET ETC6DRV 9 8 controls XRTCCLKO ETC6DRV 11 10 controls XuotgjDRVVBUS ETC6DRV 13 12 controls XuhostPWREN ETC6DRV 15 14 controls XuhostOVERCUR SAMSUNG ELECTRONICS 4 172 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 89 GPMOCON e Base Address 0x1100 0000 e Address Base Address 0x0260 Reset Value 0x0000 0000 0 0 Input 0 1 Output 0 2 Reserved 0x3 DATA 6 GPMOCON 7 31 28 0 4 XhsiCAFLAG 0 00 0 5 TraceData 6 0 6 to Reserved OxF EXT_INT8 7 0 0 Input 0 1 Output 0 2 Reserved 0x3 CAM DATA 5 GPMOCON 6 27 24 RW 0 4 XhsiCADATA 0 00 0 5 TraceData 5 0 6 to Reserved OxF EXT INT8 6 0 0 Input 0 1 Output 0 2 Reserved 0 3 CAM_B_DATA A GPMOCON 5 23 20 RW
351. T 5 0 5 0 as output port the pin state should be same as the 0x00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 3 57 GPY2PUD Base Address 0x1100 0000 e Address Base Address 0x0168 Reset Value OxOFFF 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down 0 0 0105 ix 0x2 Reserved FFF 0 3 Enables Pull up 4 3 3 58 GPY2DRV Base Address Ox1100 0000 e Address Base Address 0x016C Reset Value 0x00 0AAA 23 16 Reserved Should be zero W GPY2DRV n n 2n 1 2n R DOARA 0105 SAMSUNG ELECTRONICS 4 155 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 59 GPY2CONPDN Base Address 0x1100 0000 e Address Base Address 0x0170 Reset Value 0x0000 0 0 Outputs 0 2n 1 21 0 1 Outputs 1 eran n 0t05 FW Input 999 0 3 Previous state 4 3 3 60 GPY2PUDPDN e Base Address 0x1100 0000 e Address Base Address 0x0174 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down ar yeni n 0to5 0 2 Reserved 990 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 156 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 61 GPY3CON e Base Address 0x1100 0000 e Address Base Address 0x0180 Reset Value 0x0000_0000 0 0 Input 0 1 Output GPY3CON 7 31 28 0x2 EBI ADDR
352. T NUM 2 0 RW Interrupt Group 0 EXT INT50 when fixed priority 0x0 mode 0 to 7 4 3 4 16 PDNEN e Base Address 0x0386 0000 e Address Base Address OxOF80 Reset Value 0x00 RSV a 0 Automatically by power down mode EGNE W Power down mode pad state enable register 0 PADs Controlled by normal mode This bit is set to 1 automatically when system enters into Power down mode and clears by writing PDNEN R 0 to this bit or cold reset After wake up from 0 0 Power down mode this bit maintains value 1 until writing O 1 PADs Controlled by Power Down mode control registers SAMSUNG ELECTRONICS 4 297 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 Part 4 4 3 5 1 GPVOCON Base Address Ox106E 0000 e Address Base Address 0x0000 Reset Value 0x0000 0000 0 0 Input 0 1 Output GPVOCON 7 31 28 0 2 2 RXD 7 0 00 0x3 to Reserved OxF EXT_INT30 7 0 0 Input 0 1 Output GPVOCON 6 27 24 0 2 C2C RXD 6 0 00 0x3 to Reserved EXT_INT30 6 0 0 Input 0 1 Output GPVOCON 5 23 20 0 2 C2C RXD 5 0 00 0x3 to Reserved OxF EXT_INT30 5 0 0 Input 0 1 Output GPVOCON 4 19 16 0 2 C2C RXD 4 0 00 0x3 to Reserved OxF EXT_INT30 4 0 0 Input 0 1 Output GPVOCON 2 11 8 RW 0 2 C2C_RXD 2 0 00 0x3 to Reserved OxF EXT_INT30 2 0 0 Input 0 1 Output GPVOCON
353. T23_CON 5 22 20 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0x7 Reserved 85 0 mp 1 7 Sets signaling method of EXT_INT23 4 0 0 Low level 0x1 High level EXT_INT23_CON 4 18 16 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0x7 Reserved 85 0 Jane fe Sets signaling method of EXT INT23 3 0 0 Low level 0 1 High level EXT INT23 CON S 14 12 RW 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0x7 Reserved 85 0 mp fasen fe Sets signaling method of EXT INT23 2 0 0 Low level 0 1 High level EXT INT23 CON 2 10 8 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 192 ex 4412 UM 4 General Purpose Input Output GPIO Control Be signaling method of EXT_INT23 1 0 0 Low level 0x1 High level EXT_INT23_CON 1 6 4 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0x7 Reserved mw me mee pm Sets signaling method of EXT INT23 0 0 0 Low level 0 1 High level EXT INT23 CON 0 2 0 RW 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved SAMSUNG ELECTRONICS 4 193 IT 4412 UM 4 General Purpose Input Output GPIO
354. T50 1 0 0 Input 0 1 Output 0 2 125 0 SCLK GPZCON 0 3 0 0x3 PCM 0 SCLK 0 4 to Reserved EXT INT50 0 SAMSUNG ELECTRONICS 4 289 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 4 2 GPZDAT e Base Address 0x0386 0000 e Address Base Address 0x0004 Reset Value 0x00 When you configure port as input port then corresponding bit is pin state While configuring as GPZDAT 6 0 RWX output port then pin state should be same as 0x00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 4 3 GPZPUD Base Address 0x0386_0000 e Address Base Address 0x0008 Reset Value 0x1555 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down 0106 SUM 0x2 Reserved Son 0 3 Enables Pull up 4 3 4 4 GPZDRV e Base Address 0x0386 0000 e Address Base Address 0x000C Reset Value 0x00_0000 23 16 Reserved Should be zero W GPZDRVIn n 2n 1 21 0x0000 0106 SAMSUNG ELECTRONICS 4 290 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 4 5 GPZCONPDN e Base Address 0x0386 0000 e Address Base Address 0x0010 Reset Value 0x0000 0 0 Outputs 0 2n 1 21 0 1 Outputs 1 eran n 0t06 Y ox2 Input 999 0 3 Previous state 4 3 4 6 GPZPUDPDN Base Address 0 0386 0000 e Address Base Address 0x0014 Reset Va
355. TE Do not use zero value 0x0000 Before ADC conversion Touch screen uses X tal clock During ADC conversion PCLK Max 66 MHz is used SAMSUNG ELECTRONICS 18 8 ex 4412 UM 18 ADC 18 6 1 3 ADCDAT Base Address 0x126C_0000 e Address Base Address 0x000C Reset Value Undefined ADC conversion data value Data value 0x0 to OxFFF 18 6 1 4 CLRINTADC e Base Address 0x126C_0000 e Address Base Address 0x0018 Reset Value Undefined w INT ADOn interrupt clear Cleared if any value is written These registers are used to clear the interrupts Interrupt service routine is responsible to clear interrupts after the interrupt service is completed Writing any values on this register will clear up the relevant interrupts asserted When it is read undefined value will be returned INTADCCLR 18 6 1 5 ADCMUX e Base Address 0x126C_0000 e Address Base Address 0x001C Reset Value 0x0000_0000 Analog input channel select 0000 AIN O SEL_MUX 3 0 RW 0001 1 0010 AIN 2 0011 AIN 3 SAMSUNG ELECTRONICS 18 9 x
356. Table 8 2 Table 11 1 Table 13 1 Table 16 1 Table 16 2 Table 16 3 Table 16 4 Table 16 5 Table 17 1 List of Tables Title Page Number Operating Frequencies 4412 waziwazi 5 2 APLL and MPEE PMS 5 7 EPUL PMS Value rn rece ett easi ertt das 5 8 LIBRAIRES 5 9 Special Clocks in 4412 5 17 I O Clocks in Exynos44 12 a 5 19 CLKOUT Input Clock Selection Information 5 21 VO Description M 5 23 GIC Configuration Values UL dd 6 3 GIC Interrupt Table SPI 127 0 6 5 GIC Interrupt Table 5 01 6 12 Interrupt Groups of Interrupt 7 3 Features of DMA Controller ini cion Eel tent eei tt En e Lade Re d Te vend 8 2 DMA Request Mapping Table seen nennen nnne nennen aaa 8 2 Minimum and Maximum Resolution Based on Prescaler and Clock Divider Values 11 5 Interrupts in Connection with FIFO 13 6 Relation 16 BPP between and CLKVAL TFT Frequency of Video Clock Source 60 MHz H 16 35 RGB Interface Signals of Display 16 40 LCD Indirect i80 System Interface Signals of Display
357. The other PLL control inputs should be set as DCC_ENB 1 ICP BOOST 0 0 EXTAFC 0 SAMSUNG ELECTRONICS 5 53 ex 4412 UM 5 Clock Management Unit 5 10 1 25 CLK SRC TOPO e Base Address 0x1003 0000 e Address Base Address 0xC210 Reset Value 0x0000_0000 RSV era Controls MUXONENAND MUX ONENAND SEL 28 RW 0 133 1 160 SE gr eee fo Controls MUXACLK 133 MUX 133 SEL 24 RW 0 SCLKMPLL 1 SCLKAPLL SE woot fo Controls MUXACLK 160 MUX 160 SEL 20 RW 0 SCLKMPLL 1 SCLKAPLL SE sem eee fo Controls MUXACLK 100 MUX 100 SEL 16 RW 0 SCLKMPLL 1 SCLKAPLL SE eee fo Controls MUXACLK 200 MUX ACLK 200 SEL 12 RW 0 SCLKMPLL 1 SCLKAPLL D ma mews eo Controls MUXVPLL MUX VPLL SEL RW 0 FINPLL 1 FOUTVPLL ASV eo Controls MUKEPLL EPLL SEL 4 RW 0 FINPLL 1 FOUTEPLL ASV eee 1 99 Controls MUXONENAND 1 MUX ONENAND 1 SEL RW 0 MOUTONENAND 1 SCLKVPLL SAMSUNG ELECTRONICS 5 54 27 4412 UM 5 Clock Management Unit 5 10 1 26 CLK_SRC_TOP1 e Base Address 0x1003 0000 e Address Base Address 0xC214 Reset Value 0 0000 0000 RSV eras mesen _ _ ACLK 400 Controls MUXACLK 400 MCUISP SUB MCUISP SUB SEL 24 RWX 0 FINPLL n 1 DIVOUT ACLK 400 MCUISP
358. The value depends on the device The value depends on the pin status SAMSUNG ELECTRONICS 1 13 ex 4412 UM 2 Memory Map Memory Map 2 1 Overview This section describes the base address of region BE a ROM mirror of 0x0 to 0 10000 0x0300 0000 0x0302 0000 128 KB Data memory or general purpose of Samsung Reconfigurable Processor SRP 0x0302_0000 0x0303_0000 64 KB or general purpose of SRP 0x0303_0000 0x0303_9000 36 KB Configuration memory write only of SRP 0x0381 0000 0x0383 0000 AudioSS s SFR region 0x0400 0000 0x0500 0000 16 MB eden 2 Read Only Memory Controller SMC 0000 00 0000 0x0D00 0000 SFR region of Flash Controller 04000 0000 Sdn SCS Memory of Dynamic Memory Controller DMC 0 SAMSUNG ELECTRONICS 2 1 27 4412 UM 2 Memory Map 2 2 SFR Base Address This section describes the base address of SFR BaseAddress PB 4 Power Management Unit PMU Thermal Management Unit TMU _ 2 Modem side SAMSUNG ELECTRONICS x 4412 UM 2 Memory Map Base Address BR Security Sub System SSS SAMSUNG ELECTRONICS T x 4412 UM 2 Memory Map ase Address Transport Stream Interface TSI Video Processor VP SAMSUNG ELECTRONICS 24 x 4412 UM 2 Memory Map em 3D
359. Triggers rising edge 0 4 Triggers both edge 0 5 to 0x7 Reserved Sets signaling method of EXT INT1 1 0 0 Low level 0 1 High level EXT INT1 CON 1 6 4 RW 0 2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0x7 Reserved Sets signaling method of INT1 0 0 0 Low level 0 1 High level EXT INT1 CON 0 2 0 RW 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 62 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 82 EXT_INT2CON Base Address 0x1140_0000 e Address Base Address 0x0704 Reset Value 0x0000_0000 RSV prea eee RSV mp fo Sets signaling method of EXT INT2 5 0 0 Low level 0 1 High level EXT 2 CON 5 22 20 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved 85 9 A Sets signaling method of EXT_INT2 4 0x0 Low level 0x1 High level EXT_INT2_CON 4 18 16 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0 7 Reserved 85 0 mp Sets signaling method of EXT_INT2 3 0x0 Low level 0x1 High level EXT INT2 CON 3 14 12 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved 85 9 Resene
360. UM 5 Clock Management Unit 5 10 1 65 CLK_DIV_PERIL2 e Base Address 0x1003 0000 e Address Base Address 0xC558 Reset Value 0 0000 0000 DIVSPI2 PRE Clock Divider Ratio RENO isl SCLK SPI2 DOUTSPI2 SPI2 PRE RATIO 1 on SE vay DIVSPI2 Clock Divider Ratio SPRANG 3 0 DOUTSPI2 MOUTSPI2 SPI2_RATIO 1 me 5 10 1 66 CLK_DIV_PERIL3 e Base Address 0 1003_0000 e Address Base Address 0xC55C Reset Value 0x0000 0000 RSV noen oo DIVSLIMBUS Clock Divider Ratio BS ID SCLK_SLIMBUS SCLKEPLL SLIMBUS RATIO 1 SE Gq eens SAMSUNG ELECTRONICS 5 91 ex 4412 UM 5 Clock Management Unit 5 10 1 67 CLK_DIV_PERIL4 e Base Address 0x1003_0000 e Address Base Address 0xC560 Reset Value 0x0000_0000 DIVPCM2 Clock Divider Ratio SCLK_PCM2 SCLK AUDIO2 PCM2 RATIO 1 oxo DIVAUDIO2 Clock Divider Ratio AUDIO2_RATIO 19 16 RW SCLK_AUDIO2 MOUTAUDIO2 AUDIO2 RATIO 0 0 RSVD 15 12 NE Reserved DIVPCM1 Clock Divider Ratio SCLK_PCM1 SCLK_AUDIO1 PCM1_RATIO 1 DIVAUDIO1 Clock Divider Ratio AUDIO1_RATIO 3 0 RW SCLK AUDIO1 MOUTAUDIO1 AUDIO1 RATIO 1 5 10 1 68 CLK_DIV_PERIL5 0 0 Base Address 0x1003_0000 e Address Base Address 0xC564 Reset Value 0x0000_0000 RSVD 81 14 Reserved e 0 0 DIVI2S2 Clock Divider Ratio IPS 13 8 SCLK 1252 SCLK AU
361. UM 7 Interrupt Combiner 7 6 2 4 IMSRO e Base Address 0x1044 0000 e Address Base Address 0x000C Reset Value Undefined ASVD 99 NCTIIRQ ISP R GE p EE PE 28 EX If the corresponding interrupt enable bit is 0 the __ nCTIIRQ 1 27 IMSR bitreads as 0 ETE O 2 ptis pending PARITYFAILSC 1 25 LM RSVD Reed fom gt PARRINTR R PARRDINTR 21 Masked interrupt pending status 20 R If the corresponding interrupt enable bit is 0 the ___ nCTIIRQ O 19 IMSR bit reads as 0 18 0 interrupt 5 not pending Et 1 The interrupt is pending PARITYFAILSCU O 17 RSVD ps Reewd fom TZASC1 1 11 Masked interrupt pending status TZASCH 0 10 NN If the corresponding interrupt enable bit is the EEE IMSR bit reads as 0 TSN 0 The interrupt is not pending TZASCOJO B R 1 The interrupt is pending RSVD 74 Reseved RSVD B Masked interrupt pending status RSVD 2 If the corresponding interrupt enable bit is 0 the RSVD IMSR bit reads as 0 0 The interrupt 15 not pending RSVD n 1 The interrupt is pending SAMSUNG ELECTRONICS 7 13 27 4412 UM 7 Interrupt Combiner 7 6 2 5 IESR1 e Base Address 0x1044 0000 e Address Base Address 0x0010 Reset Value 0 0000 0000 Nam
362. VPLL Others Reserved MUXPWI is the clock source of PWI SE era mose mw Controls MUXMPLL MPLL SEL 12 RW 0 FINPLL 1 MOUTMPLLFOUT SE ma meme mw Controls MUXDPHY MUX DPHY SEL RW 0 SCLKMPLL 1 SCLKAPLL SE ms ea mw Controls MUXDMC BUS 4 RW 0 SCLKMPLL T 1 SCLKAPLL CO SAMSUNG ELECTRONICS 5 124 IT 4412 UM 5 Clock Management Unit Controls MUXC2C MUX_C2C_SEL RW 0 SCLKMPLL 1 SCLKAPLL SAMSUNG ELECTRONICS 5 125 IT 4412 UM 5 Clock Management Unit 5 10 1 108 CLK SRC MASK DMC e Base Address 0 1004 0000 e Address Base Address 0x0300 Reset Value 0x0001 0000 RSVD er _ Mask output clock of MUXPWI PWI_MASK 16 RW 0 Mask 1 Unmask SE os SAMSUNG ELECTRONICS 5 126 IT 4412 UM 5 Clock Management Unit 5 10 1 109 CLK_MUX_STAT_DMC e Base Address 0x1004 0000 e Address Base Address 0x0400 Reset Value 0x1110 1111 RSVD on ne gt Selection signal status of MUXG2D ACP 001 MOUTG2D ACP 0 AGP SEL 0558 010 MOUTG2D ACP 1 1xx On changing i 85 0 ay mesen mw Selection signal status of MUXG2D_ACP_1 G2D ACP 1 SEL 26 24 pe 111 1 changing 85 0 gy mesen ANT Selection signal status of MUXG2D ACP 0 G2D ACP 0 SEL 22 20 d E TTN 1xx On changing ASV meus eem Selection signal status of MUXMPLL
363. Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down ere 0107 i 0x2 Reserved 990 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 169 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 85 ETCOPUD e Base Address 0x1100 0000 e Address Base Address 0x0208 Reset Value 0x0400 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down 0105 0 2 Reserved 0 3 Enables Pull up ETCOPUD n 0x0400 ETCOPUD 1 0 controls X TRSTn ETCOPUD 3 2 controls XjTMS ETCOPUDI 5 4 controls XjTCK ETCOPUD 7 6 controls XjTDI ETCOPUD 9 8 controls XjTDO ETCOPUD 11 10 controls XjDBGSEL 4 3 3 86 ETCODRV e Base Address 0 1100_0000 e Address Base Address 0x020C Reset Value 0x00_0000 23 16 Reserved Should be zero W ETCODRV n n 2n 1 2n R 0x0000 0105 ETCODRV 1 0 controls X TRSTn ETCODRV 3 2 controls XjTMS ETCODRV 5 4 controls XjTCK ETCODRV 7 6 controls XjTDI ETCODRV 9 8 controls XjTDO ETCODRV 11 10 controls X iDBBGSEL SAMSUNG ELECTRONICS 4 170 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 87 ETC6PUD e Base Address 0x1100 0000 e Address Base Address 0x0228 Reset Value 0xC000 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down 0107 0 2 Reserved 0 3 Enables Pull up ETC6PUD n 0xC000 ETC6PUD 1 0 controls XnRESE
364. Vn UFRACVALn 16 or DIV VAL SCLK UART bps x 16 1 Where the divisor should be from 1 to 216 1 By using UFRACVALn you can generate the Baud rate more accurately For example if the Baud rate is 115200 bps and SCLK_UART is 40 MHz UBRDIVn and UFRACVALn are DIV_VAL 40000000 115200 x 16 1 21 7 1 20 7 UBRDIVn 20 integer of DIV VAL UFRACVALn 16 0 7 Therefore UFRACVALn 11 2 Baud Rate Error Tolerance UART Frame error should be less than 1 87 3 160 tUPCLK UBRDIVn 1 UFRACVAL 16 x 16 x 1Frame SCLK_UART tUPCLK Real UART Clock tEXTUARTCLK 1Frame baud rate tEXTUARTCLK Ideal UART Clock UART error tUPCLK tEXTUARTCLK AEXTUARTCLK x 100 96 1Frame start bit data bit parity bit stop bit 3 UART Clock and PCLK Relation There is a constraint on the ratio of clock frequencies for PCLK to UARTCLK The frequency of UARTCLK must be no more than 5 5 3 times faster than the frequency of PCLK FUARTCLK lt 5 5 3 x FPCLK SAMSUNG ELECTRONICS 13 27 ex 4412 UM 13 Universal Asynchronous Receiver and Transmitter FUARTCLK baudrate 16 This allows sufficient time to Write the received data to the receive FIFO SAMSUNG ELECTRONICS 13 28 ex 4412 UM 13 Universal Asynchronous Receiver and Transmitter 13 6 1 13 UINTPn 0 to 4 e Base Address 0x1380 0000 Base Address 0x1381_0000 Base Address 0x1382 0000 e Base Address 0x138
365. W ox2 Input 98 0 3 Previous state 4 3 3 18 GPK2PUDPDN Base Address 0 1100 0000 e Address Base Address 0x0094 Reset Value 0x0000 0 0 Disables Pull up Pull down 2n 1 21 0 1 Enables Pull down 0106 0 2 Enables Reserved 0x3 Pull up SAMSUNG ELECTRONICS 4 134 en 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 19 GPK3CON e Base Address 0x1100 0000 e Address Base Address 0x00AO0 Reset Value 0x0000 0000 0 0 Input 0 1 Output 0 2 SD 3 DATA 3 GPK3CON 6 27 24 0x3 SD 2 DATA 7 0 00 0 4 to Reserved EXT INT26 6 0 0 Input 0 1 Output 0 2 SD 3 DATA 2 GPK3CON 5 23 20 RW 0 3 SD 2 DATAS 0 00 0 4 to Reserved EXT_INT26 5 0 0 Input 0 1 Output 0 2 SD 3 DATA 1 GPK3CON 4 19 16 RW 0x3 SD 2 DATA 0 00 0 4 to Reserved EXT_INT26 4 0 0 Input 0 1 Output 0 2 SD 3 DATA 0 GPK3CON 3 15 12 RW 0x3 SD 2 4 0 00 0 4 to Reserved EXT_INT26 3 0 0 Input 0 1 Output 0 2 SD 3 CDn GPK3CON 2 11 8 RW 0x3 GNSS GPIO 11 0 00 0 4 to Reserved OxF EXT_INT26 2 0 0 Input 0 1 Output GPK3CON 1 7 4 RW 0 2 SD 3 CMD 0 00 0 3 to Reserved OxF EXT_INT26 1 0x0 Input 0x1 Output GPK3CON 0 3 0 RW 0 2 SD 3 0x3 to Reserved OxF EXT INT26 0 SAMSUNG
366. W Interrupt Group 7 EXT INT8 when fixed priority 0 0 mode 0 to 7 4 3 3 190 EKT INT9 FIKPRI Base Address 0x1100_0000 e Address Base Address 0x0B3C Reset Value 0x0000 0000 Interrupt number of the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group 8 INT9 when fixed priority 0 0 mode 0 to 7 4 3 3 191 EKT INT10 FIKPRI Base Address 0x1100_0000 e Address Base Address 0x0B40 Reset Value 0x0000 0000 Interrupt number of the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group 9 EXT INT10 when fixed priority 0x0 mode 0 to 7 SAMSUNG ELECTRONICS 4 250 x 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 192 EXT_INT11_FIXPRI e Base Address 0x1100 0000 e Address Base Address 0x0B44 Reset Value 0x0000_0000 Interrupt number of the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group 10 EXT_INT11 when fixed priority 0 0 mode 0 to 7 4 3 3 193 EXT_INT12_FIXPRI Base Address 0x1100_0000 e Address Base Address 0x0B48 Reset Value 0x0000 0000 Interrupt number of the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group 11 INT12 when fixed priority 0 0 mode 0 to 7 SAMSUNG ELECTRONICS 4 251 ex 4412 UM 4 General Purpose Input Output Control 4 3 3 194 GPKOCON Base Address 0x1100 0000 e Address Base Address 0 0 00 Reset Value
367. W Read The current interrupt enable bit 0 Masks SYSMMU GPS 0 9 RW 1 Enables E SYSMMU 2DI0 NE SYSMMU JPEG 0 Sets the corresponding interrupt enable bit to 1 If E KEEN SYSMMU FIMC3 0 you set the interrupt enable bit interrupt combiner serves the interrupt reguest SYSMMU_FIMC2 0 RW Write 0 Does not change the current setting SYSMMU FIMC1 0 1 Sets the interrupt enable bit to 1 SYSMMU FIMCO 0 RW Read The current interrupt enable bit 0 Masks SYSMMU SSS 0 1 Enables SYSMMU_MOMAJO 10 iL SAMSUNG ELECTRONICS 7 14 4412 UM 7 Interrupt Combiner 7 6 2 6 IECR1 e Base Address 0x1044 0000 e Address Base Address 0x0014 Reset Value 0x0000 0000 o SYSMMU_MFC_M1 1 30 Clears the corresponding interrupt enable bit to 0 If you clear the interrupt enable bit interrupt MPG MoN 29 combiner will mask the interrupt SYSMMU_TV_MO 1 28 RW write 0 Does not change the current setting NE RSVD 27 e 1 Clears the interrupt enable bit to EI SYSMMU LCDO 26 RW Read The current interrupt enable bit 0 Masks SYSMMU_GPS 1 25 1 Enables 9 SYSMMU_ROTATOR 1 24 0000 Svsmmu n te AA SYSMMU JPEG 1 22 Clears the corresponding interrupt enable bit to If you clear the interrupt enable bit interrupt
368. WPALCON Specifies palette control register WxRTQOSCON Specifies RTQoS control register WxPDATAxx Specifies window palette data of each index SHDOWCON Specifies shadow control register WxRTQOSCON Specifies QoS control register SAMSUNG ELECTRONICS 16 48 ex 4412 UM 16 Display Controller 16 5 1 Register Map Summary e Base Address 0x11C0_0000 register onse beseripilon Reset Value VIDTCON2 0x0018 Specifies video time control 2 register 0x0000_0000 VIDTCON3 0x001C Specifies video time control 3 register 0x0000_0000 WINCONO 0x0020 Specifies window control O register 0x0000_0000 WINCON 1 0x0024 Specifies window control 1 register 0x0000 0000 WINCON2 0x0028 Specifies window control 2 register 0x0000 0000 WINCON3 0 002 Specifies window control 3 register 0x0000 0000 WINCON4 Specifies window control 4 register 0x0000_0000 VIDOSD2C 0x0068 Specifies video window 2 s alpha control register 0x0000_0000 VIDOSD4C 0x0088 Specifies video window 4 s alpha control register 0x0000_0000 VIDWOOADDOBO Ox00A0 Specifies window 0 s buffer start address register buffer 0 0 0000 0000 SAMSUNG ELECTRONICS 16 49 4412 UM 16 Display Controller VIDWO1ADDOB1 0x00AC 0x0000_0000 VIDW03ADD0B1 0x00BC 0x0000_0000 VIDWOOADD1B1 0 0004 0x0000 0000 VIDWO2ADD1B1 0 00 4 Specifies window 2 s buffer end address register buffer 1 0x0000 0000 VIDWO4ADD1B1 0x00F4 0 0000 0000
369. WX 0 0 Not occur 0 1 Interrupt occurs 4 3 3 176 EXT INT10 PEND Base Address 0x1100 0000 e Address Base Address 0x0A2C Reset Value 0x0000 0000 RSVD Reserved 0x0000000 0 0 Not occur EN NHO RENDE 4 Ox1 Interrupt occurs 0 0 Not occur EAT PENDDI 3 0 1 Interrupt occurs 0 0 Not EXT INT10 PEND 1 1 RWX 0 1 Interrupt occurs 0 0 Not occur EXT INT10 PEND 0 RWX 0 1 Interrupt occurs EXT INT10 PEND 2 2 RWX 0 0 Not occur 0 1 Interrupt SAMSUNG ELECTRONICS 4 243 27 4412 UM 4 3 3 177 EXT_INT11_PEND e Base Address 0x1100 0000 e Address Base Address 0x0A30 Reset Value 0x0000 0000 RSVD EXT INT11 PEND 7 EXT INT11 PEND 6 EXT INT11 PEND 5 EXT INT11 PEND 4 EXT INT11 PEND 3 EXT INT11 PEND 2 EXT INT11 PEND 1 EXT INT11 PEND 0 5 4 3 RWX 2 RWX 1 SAMSUNG ELECTRONICS 4 General Purpose Input Output GPIO Control 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 4 244 4412 UM 4 3 3 178 EKT INT12 PEND Base Address 0x1100 0000 e Address Base Address
370. XT_INT26_CON 5 22 20 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0x7 Reserved 85 0 mp o Sets signaling method of EXT INT26 4 0 0 Low level 0x1 High level EXT_INT26_CON 4 18 16 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0 7 Reserved 85 0 fe Sets signaling method of EXT INT26 3 0 0 Low level 0 1 High level EXT 26 CON 3 14 12 W 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved 85 0 mi fasen fe Sets signaling method of EXT INT26 2 0 0 Low level 0 1 High level EXT INT26 CON 2 10 8 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved SAMSUNG ELECTRONICS 4 198 ex 4412 UM 4 General Purpose Input Output GPIO Control Be signaling method of EXT_INT26 1 0 0 Low level 0x1 High level EXT_INT26_CON 1 6 4 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0x7 Reserved mw me Resend pm Sets signaling method of EXT INT26 0 0 0 Low level 0x1 High level EXT_INT26_CON 0 2 0 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 199 IT 4412 UM 4 General Purpose Input Outpu
371. _0000 e Address Base Address 0x01F4 Reset Value 0x0000 0 0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down 0105 RW 0x2 Reserved 999 0 3 Enables Pull up 4 3 2 67 ETC1PUD Base Address 0x1140_0000 e Address Base Address 0x0228 Reset Value 0x0005 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down ETC1PUD n A 0t08 RW 0 2 Reserved 0 0005 0 3 Enables Pull up ETC1PUD 1 0 controls KsbusDATA ETC1PUD 3 2 controls XsbusCLK 4 3 2 68 ETC1DRV e Base Address 0x1140 0000 e Address Base Address 0x022C Reset Value 0x00 0000 23 16 Reserved Should be zero W ETC1DRV n n 2n 1 2 0x0000 0105 ETC1PUD 1 0 controls XsbusDATA ETC1PUD 3 2 controls XsbusCLK SAMSUNG ELECTRONICS 4 54 27 4412 UM 4 3 2 69 GPJOCON e Base Address 0x1140 0000 e Address Base Address 00240 Reset Value 0 0000 0000 GPJOCON 7 GPJOCON 6 GPJOCON 5 GPJOCON 4 31 28 SAMSUNG ELECTRONICS 0 0 Input 0 1 Output 0 2 DATA 4 0x3 to Reserved OxF EXT INT21 7 0 0 Input 0 1 Output 0 2 DATA 3 0x3 to Reserved OxF EXT_INT21 6 0 0 Input 0 1 Output 0 2 DATA 2 0 3 to OxE Reserved OxF EXT INT21 5 0 0 Input 0 1 Output 0 2 DATA 1 0 3 to OxE Reserved OxF EXT INT21 4 0 0 Input
372. _INT5 Highest GRP NUM 3 0 RW 0 5 EXT 6 0x00 0x6 EXT INT7 0 7 EXT INT13 0 8 EXT INT14 0 9 EXT INT15 OxA EXT INT16 OxB EXT INT21 OxC EXT INT22 SAMSUNG ELECTRONICS 4 118 II 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 149 EXT_INT1_FIXPRI Base Address 0x1140_0000 e Address Base Address 0x0B14 Reset Value 0x0000 0000 Interrupt number of the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group 0 EXT_INT1 when fixed priority 0 0 mode 0 to 7 4 3 2 150 EXT_INT2_FIXPRI Base Address 0x1140_0000 e Address Base Address 0x0B18 Reset Value 0x0000 0000 Interrupt number the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group 1 EXT_INT2 when fixed priority 0 0 mode 0 to 7 4 3 2 151 EXT_INT3_FIXPRI Base Address 0x1140_0000 e Address Base Address 0x0B1C Reset Value 0x0000_0000 Reserved 0x00000000 Interrupt number of the highest priority in External Interrupt Group 2 EXT_INT3 when fixed priority 0 0 mode 0 to 7 4 3 2 152 EXT_INT4_FIXPRI Base Address 0x1140_0000 e Address Base Address 0x0B20 Reset Value 0x0000 0000 Reserved 0x00000000 Interrupt number of the highest priority in External Interrupt Group 3 EXT_INT4 when fixed priority 0 0 mode 0 to 7 SAMSUNG ELECTRONICS 4 119 27 4412 UM 4 General Purpose Input Output GPIO Control
373. _LEFTBUS 0x0000_0000 0x4204 to CLK_MUX_STAT_LEFTBUS 0x4400 Clock MUX status for CMU_LEFTBUS 0x0000_0011 0x4404 to CLK_DIV_LEFTBUS 0x4500 Sets clock divider ratio for CMU LEFTBUS 0x0000_0000 CLKOUT_CMU_LEFTBUS 0 4 00 CLKOUT control register 0x0001_0000 GLKOUT_OMU_LEFTBUS 0x4A04 Clock divider status for CLKOUT 0x0000_0000 DIV_STAT 0x4A08 to RSVD 0x81FF Reserved Undefined CLK_SRC_RIGHTBUS 0x8200 Selects clock source for CMU_RIGHTBUS 0x0000_0000 0x8204 to CLK_MUX_STAT_RIGHTBUS 0x8400 Clock MUX status for CMU_RIGHTBUS 0x0000_0011 0x8404 to RSVD 0x84FF Reserved Undefined Sets clock divider ratio for CLK_DIV_RIGHTBUS 0x8500 CMU_RIGHTBUS 0x0000_0000 0x8504 to RSVD Reserved Undefined CLK DIV STAT RIGHTBUS 08600 Clock divider status for CMU_RIGHTBUS 0x0000_0000 0x8604 to CLK GATE IP RIGHTBUS 0 8800 Control IP clock gating for RIGHTBUS OxFFFF FFFF CLK_DIV_STAT_LEFTBUS 0x4600 Clock divider status for CMU_LEFTBUS 0x0000_0000 CLK_GATE_IP_IMAGE 0x4930 Control IP clock gating for IMAGE_SS OxFFFF FFFF CLK GATE IP LEFTBUS 0x4800 Control IP clock gating for LEFTBUS BLK OxFFFF FFFF SAMSUNG ELECTRONICS 5 26 4412 UM 5 Clock Management Unit messe CLK GATE 08960 Controls IP clock gating for PERIR S OxFFFF FFFF 0x8964 to CLKOUT CMU RIGHTBUS 0x8A00 CLKOUT control register 0x0001 0000 GDSQUT CMBSFUGHTEDS 0x8A04 Clock divider status for CLKOUT 0x0000 00
374. aa 16 30 Blending Factor Decision a aaa 16 31 Color Key Function 16 32 Blending and Color Key Function sess 16 33 Blending Decision Diagram 16 34 Example of Scrolling in Virtual Display 16 39 LGD RGB Interface Timing ce tote kuwa Entre doors 16 42 Indirect 180 System Interface Write Cycle Timing sse 16 45 Key Matrix Interface External Connection 17 2 Internal Debouncing Filter 17 3 Keypad Scanning 17 4 Keypad Scanning Procedure ll U nnns nennen ns 17 5 Keypad Scanning nnnr nnns 17 6 Keypad Scanning Procedure when the Two key Pressed with Different 17 7 Keypad I F Block 17 8 Figure 18 1 Figure 18 2 Figure 18 3 Figure 18 4 ADC Top Bottom Offset Error Diagram ADC Functional Block 18 1 ADC Selection Input Clock Diagram for ADC amp Touch Screen Interface SAMSUNG ELECTRONICS I Table Number Table 5 1 Table 5 2 Table 5 3 Table 5 4 Table 5 5 Table 5 6 Table 5 7 Table 5 8 Table 6 1 Table 6 2 Table 6 3 Table 7 1 Table 8 1
375. able InRGB 1 R ne 13 0 RGB 1 YCbCr Reserved RSVD 12 11 mw men NOTE This bit should be set to 0 Specifies DMA s Burst Maximum Length selection 00 16word burst BURSTLEN 10 9 RW 01 woFd 10 4word burst Reserved RSVD NOTE This bit should be set to 0 Specifies Multiplied Alpha value mode 0 Disables multiplied mode 1 Enables multiplied mode When ALPHA_MUL is 1 set BLD PIX 1 7 ALPHA SEL 1 and BPPMODE F 5 2 401101 or 401110 NOTE Alpha value alpha_pixel from data ALPHAO R G B SAMSUNG ELECTRONICS 16 70 ex Specifies Word swap control bit 0 Disables swap 1 Enables swap NOTE Set it to 0 when ENLOCAL is 1 Selects auto buffering mode Specifies Byte swaps control bit 0 Disables swap i ds D 1 Enables swap NOTE Set it to 0 when ENLOCAL is 1 RW RW RW RW RW RW W Specifies Half Word swap control bit 0 Disables swap 1 Enables swap NOTE Set it to 0 when ENLOCAL is 1 4412 UM 16 Display Controller Selects blending category BLD_PIX_F 0 Per plane blending 1 Per pixel blending Selects Bits Per Pixel BPP mode in Window image 0000 1 BPP 0001 2BPP 0010 4BPP 0011 8 BPP palletized 0100 8 BPP non palletized A 1 R 2 G 3 B 2 0101 16 BPP non palletized R 5 G 6 B 5 0110 16 BPP non palletized A 1 R 5 G 5 B 5 0111 16 BPP non palletized 1 R 5 G 5 B 5 1000 Unpacked
376. ad zone enable disable Enables Disables Dead zone generator 4 Timer 0 auto 3 2 R 0 One shot reload on off 1 Interval mode auto reload R 0 output 2 RW 0 Inverter Timer 2 auto reload on off 1 1 0 operation 1 Updates 2 2 1 1 1 2 output inverter on off W RW RW RW RW RW RW Timer 2 manual RW RW RW RW RW RW W W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMSUNG ELECTRONICS 11 17 4412 UM 11 Pulse Width Modulation Timer inverter on off 1 TOUT_ 0inverter on Timer 0 manual 0 No operation update 1 1 Updates TCNTBO andTCMPBO om 0 Stops Timer 0 Timer 0 start stop 4 Starts Timer 0 0 0 SAMSUNG ELECTRONICS 11 18 ex 4412 UM 11 Pulse Width Modulation Timer 11 5 1 4 TCNTBO e Base Address 0x139D_0000 PWM Base Address 0x1216 0000 PWM ISP e Address Base Address 0x000C Reset Value 0x0000 0000 31 0 Timer 0 Count Buffer register 0x0000_0000 11 5 1 5 TCMPBO e Base Address 0x139D_0000 PWM Base Address 0x1216 0000 ISP e Address Base Address 0x0010 Reset Value 0x0000_0000 a DOOR 31 0 Timer 0 Compare Buffer register 0x0000 0000 11 5 1 6 TCNTOO Base Address 0x139D 0000 PWM B
377. alii ea Era e 14 6 14 4 4 Read Write Operation 14 7 14 4 5 Bus Arbitration Procedures e ta 14 7 14 4 6 Abort Conditions ie oi 14 7 14 47 Configuring 12 O 14 7 14 4 8 Flowcharts of Operations in Each Mode 14 8 14 5 1 WA 14 12 14 6 Register Deseripiipohuu u uu u u 14 13 14 6 1 Register Map Summary ascii caia a tua ee eat v eua YER RE REL Ya ex 14 13 15 SERIAL PERIPHERAL INTERFACE 15 1 AENA A 15 1 15 2 Features M 15 1 15 271 Operation of SPU ius iere tee reete sapra tac 15 2 15 3 SPI Input Clock Description nu EHE Ee LL 15 5 15 410 Descriptie m 15 6 15 5 Register Description io 15 7 15 5 1 Register Map Summasry 15 7 16 DISPLAY CONTROLLER 16 1 KONE ERE N 16 1 16 2 Features o 16 2 16 3 Functional Description uuu aaa ete et eade E RR
378. alletized 1 R 5 G 5 B 5 1000 Unpacked 18 non palletized R 6 G 6 B 6 1001 Unpacked 18 BPP non palletized A 1 R 6 G 6 B 5 1010 Unpacked 19 BPP non palletized A 1 R 6 G 6 B 6 1011 Unpacked 24 BPP non palletized R 8 G 8 B 8 1100 Unpacked 24 BPP non palletized A 1 R 8 G 8 B 7 1101 Unpacked 25 BPP non palletized A 1 R 8 G 8 B 8 1110 Unpacked 13 BPP non palletized A 1 R 4 G 4 B 4 1111 Unpacked 15 BPP non palletized R 5 G 5 B 5 NOTE 1 1101 Supports unpacked 32 BPP non palletized A 8 R 8 G 8 B 8 for per pixel blending 2 1110 Supports 16 BPP non palletized A 4 R 4 G 4 B 4 for per pixel blending 16 level blending Selects Alpha value When Per plane blending case BLD_PIX 0 0 Using ALPHAO R G B values 1 Using ALPHA1_R G B values ALPHA_SEL_F 1 RW When Per pixel blending BLD_PIX 1 0 Selected by AEN A value 1 Using DATA 31 24 data in word boundary only when BPPMODE_F 4 b1101 DATA 31 28 15 12 data in word boundary only when BPPMODE_F 4 b1110 Enables disables the video output and logic immediately ENWIN_F RW Disables the video output and video control signal 1 Enables the video output and video control signal SAMSUNG ELECTRONICS 16 74 x 4412 UM 16 Display Controller 16 5 3 12 WINCON3 e Base Address 0x11C0_0000 e Address Base Address 0x002C Reset Value 0x0000_0000 Specifies Buffer Status read only
379. alue 0x0000_0000 DIVMMC4_PRE Clock Divider Ratio MMC4_PRE_RATIO 15 8 RW SCLK 4 DOUTMMC4 MMC4_PRE_RATIO 1 W DIVMMC4 Clock Divider Ratio I 3 0 p DOUTMMC4 MOUTMMC4 MMC4_ RATIO 1 SAMSUNG ELECTRONICS 5 89 ex 4412 UM 5 Clock Management Unit 5 10 1 63 CLK DIV PERILO e Base Address 0 1003 0000 e Address Base Address 0xC550 Reset Value 0 0000 0000 DIVUART4 Clock Divider Ratio BANG SCLK_UART4 MOUTUART4 UART4 RATIO 1 DIVUART3 Clock Divider UART3_RATIO 15 12 22 22 0 0 SCLK_UART3 RATIO 1 DIVUART2 Clock Divider Ratio SCLK_UART2 MOUTUART2 UART2 RATIO 1 ae DIVUART1 Clock Divider Ratio FA SCLK_UART1 MOUTUART1 UART1 RATIO 1 ae DIVUARTO Clock Divider Ratio SARTO RATE E SCLK UARTO MOUTUARTO UARTO RATIO 1 dE 5 10 1 64 CLK DIV PERIL1 e Base Address 0x1003 0000 e Address Base Address 0xC554 Reset Value 0x0000 0000 DIVSPI1 PRE Clock Divider Ratio RATO pron SCLK_SPI1 DOUTSPIH SPI1 PRE RATIO 1 oxo DIVSPI1 Clock Divider Ratio SPA RANG 1316 DOUTSPI1 MOUTSPI1 SPI1_RATIO 1 exe DIVSPIO_PRE Clock Divider Ratio PPP BATO 195 SCLK_SPIO DOUTSPIO SPIO PRE RATIO 1 oxo S 5 DIVSPIO Clock Divider Ratio PPO RANG 3 0 DOUTSPI0 MOUTSPIO SPIO RATIO 1 is SAMSUNG ELECTRONICS 5 90 x 4412
380. ase Address 0x0268 Reset Value 0x0000_0000 W1RTQOSCON e Address Base Address 0x026C Reset Value 0x0000_0000 W2RTQOSCON e Address Base Address 0x0270 Reset Value 0x0000_0000 W3RTQOSCON e Address Base Address 0x0274 Reset Value 0x0000_0000 W4RTQOSCON Reserved RSVD 1 12 Specifies real time QoS FIFO level FIFOLEVEL 11 4 RW If FIFO depth is less than FIFOLEVEL 7 0 then RTQoS output is 1 Reserved RSVD 2 mo NOTE This bit should be set to 0 Disables 5 output signal gate QOS_GATE_DIS 1 RW 0 Gates 1 Does not gate Reserved RSVD SAMSUNG ELECTRONICS 16 129 ex 4412 UM 16 Display Controller 16 5 3 86 LDI CMDn n 0 to 11 Base Address 0x11C0_0000 e Address Base Address 0x0280 Reset Value 0x0000_0000 LDI_CMDO e Address Base Address 0x0284 Reset Value 0x0000_0000 LDI_CMD1 e Address Base Address 0x0288 Reset Value 0x0000 0000 LDI_CMD2 e Address Base Address 0x028C Reset Value 0x0000 0000 LDI CMD3 e Address Base Address 0x0290 Reset Value 0x0000 0000 LDI CMD4 e Address Base Address 0x0294 Reset Value 0x0000 0000 LDI_CMD5 e Address Base Address 0x0298 Reset Value 0x0000 0000 LDI_CMD6 e Address Base Address 0x029C Reset Value 0x0000 0000 LDI_CMD7 e Address Base Address 0x02A0 Reset Value 0x0000_0000 LDI_CMD8 e Address Base Address 0x02A4 Reset Value 0x0000 0000
381. ase Address 0x0838 Reset Value 0x0000_0000 RSV Filter Enable for EXT_INT28 1 FLTENS 1 15 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH8 1 14 8 Filtering width of EXT INT28 1 Filter Enable for EXT INT28 0 FLTENS 0 7 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTHe o 60 RW Filtering width of EXT INT28 0 4 3 3 142 EXT 28 1 e Base Address 0x1100 0000 e Address Base Address 0x083C Reset Value 0x0000 0000 SAMSUNG ELECTRONICS 4 219 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 143 EXT_INT29_FLTCONO e Base Address 0x1100 0000 e Address Base Address 0x0840 Reset Value 0 0000 0000 Filter Enable for EXT_INT29 3 FLTEN9 S 31 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH9 3 30 24 Filtering width of EXT_INT29 3 Filter Enable for EXT_INT29 2 FLTEN9 2 23 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTHe 2 22 16 Filtering width of EXT INT29 2 Filter Enable for EXT INT29 1 FLTEN9 1 15 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH9 1 14 8 Filtering width of EXT INT29 1 Filter Enable for EXT INT29 0 FLTEN9 0 7 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTHe 0 6 0 Filtering width of EXT INT29 0 SAMSUNG ELECTRONICS 4 220 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 144 2
382. ase Address 0x1140_0000 e Address Base Address 0x00A8 Reset Value 0x0055 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down GPDOPUD n RW 0x2 Reserved 0 0055 0 3 Enables Pull up 4 3 2 34 GPDODRV e Base Address 0x1140_0000 e Address Base Address Ox00AC Reset Value 0x00 0000 23 1 6 Reserved Should zero W GPDODRVIn n 2n 1 2n R 0x0000 0103 SAMSUNG ELECTRONICS 4 38 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 35 GPDOCONPDN e Base Address 0x1140 0000 e Address Base Address Reset Value 0x0000 0 0 Outputs 0 2n 1 21 0 1 Outputs 1 SRA 0103 Input 5 0 3 Previous state 4 3 2 36 GPDOPUDPDN e Base Address 0x1140_0000 e Address Base Address 0x00B4 Reset Value 0 0000 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down 0103 di 0x2 Reserved 990 0x3 Enables Pull up SAMSUNG ELECTRONICS 4 39 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 37 GPD1CON e Base Address 0x1140_0000 e Address Base Address 0 00 0 Reset Value 0 0000 0000 0 0 Input 0 1 Output 0 2 12C_1_SCL GPD1CON 3 15 12 0x3 ESC CLK 0x00 0x4 to OxE Reserved OxF EXT_INT7 3 0 0 Input 0 1 Output 0 2 126 1 SDA GPD1CON 2 11 8 0x3 BYTE 0 00 0 4 to Re
383. ase Address 0x1216 0000 PWM ISP e Address Base Address 0x0014 Reset Value 0x0000 0000 Timer 0 count 31 0 Timer 0 Count Observation register 0 0000 0000 observation 11 5 1 7 TCNTB1 e Base Address 0x139D 0000 PWM Base Address 0x1216 0000 PWM ISP e Address Base Address 0x0018 Reset Value 0x0000 0000 21 count 31 0 Timer 1 Count Buffer register 0 0000_0000 SAMSUNG ELECTRONICS 11 19 II 4412 UM 11 Pulse Width Modulation Timer 11 5 1 8 TCMPB1 e Base Address 0x139D_0000 PWM Base Address 0x1216 0000 ISP e Address Base Address 0x001C Reset Value 0x0000 0000 1 compare 31 0 Timer 1 Compare Buffer register 0x0000 0000 11 5 1 9 TCNTO1 e Base Address 0x139D 0000 PWM Base Address 0x1216 0000 PWM ISP e Address Base Address 0x0020 Reset Value 0x0000 0000 Timer 1 count 31 0 1 Count Observation register 0 0000 0000 observation 11 5 1 10 TCNTB2 Base Address 0x139D_0000 PWM Base Address 0x1216 0000 ISP e Address Base Address 0x0024 Reset Value 0x0000 0000 IRSE OH 31 0 RW Timer 2 Count Buffer register 0x0000 0000 buffer 11 5 1 11 TCMPB2 e Base Address 0x139D 0000 PWM Base Address 0x1216 0000 ISP e Address Base Address 0x0028 Reset Value 0x0000 0000 compare 31 0 Timer 2 Compare Buffer register 0x0000 0000 SAMSUNG ELECTRONICS 11 20 II
384. ate 4 3 5 26 GPV3PUDPDN Base Address Ox106E 0000 e Address Base Address 0x0094 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down 0107 RW 0x2 Reserved Oxu 0x3 Enables Pull up SAMSUNG ELECTRONICS 4 310 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 27 ETC8PUD Base Address Ox106E 0000 e Address Base Address 0x00A8 Reset Value 0x0005 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down ETC8PUD n 0101 RW 0x2 Reserved 0x0005 0x3 Enables Pull up ETC8PUD 1 0 controls Xc2cTXCLK 0 ETC8PUDJ 3 2 controls Xc2cTXCLK 1 4 3 5 28 ETC8DRV e Base Address 0x106E 0000 e Address Base Address Reset Value 0x00 0000 23 16 Reserved Should be zero W ETC8DRV n n 2 1 2 0x0000 0101 ETC8DRV 1 0 controls Xc2cTXCLKJ 0 ETC8DRV 3 2 controls Xc2cTXCLK 1 SAMSUNG ELECTRONICS 4 311 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 29 GPV4CON Base Address Ox106E 0000 e Address Base Address 0 00 0 Reset Value 0x0000 0000 0 0 Input 0 1 Output GPV4CON 1 7 4 RW 0 2 2 WKREQOUT 0 00 0x3 to Reserved EXT INT34 1 0 0 Input 0 1 Output GPV4CON 0 3 0 RW 0 2 2 WKREQIN 0 00 0x3 to Reserved OxF EXT INT34 0 4 3 5 30 GPV4DAT Base Address
385. ature Humidity Semiconductor devices are sensitive to e Environment e Temperature e Humidity High temperature or humidity deteriorates the characteristics of semiconductor devices Therefore do not store or use semiconductor devices in such conditions Mechanical Shock Do not to apply excessive mechanical shock or force on semiconductor devices Chemical Do not expose semiconductor devices to chemicals because exposure to chemicals leads to reactions that deteriorate the characteristics of the devices Light Protection In non Epoxy Molding Compound EMC package do not expose semiconductor IC to bright light Exposure to bright light causes malfunctioning of the devices However a few special products that utilize light or with security functions are exempted from this guide Radioactive Cosmic and X ray Radioactive substances cosmic ray or X ray may influence semiconductor devices These substances or rays may cause a soft error during a device operation Therefore ensure to shield the semiconductor devices under environment that may be exposed to radioactive substances cosmic ray or X ray EMS Electromagnetic Susceptibility Strong electromagnetic wave or magnetic field may affect the characteristic of semiconductor devices during the operation under insufficient PCB circuit design for Electromagnetic Susceptibility EMS SAMSUNG ELECTRONICS I Revision History Revision No Date Desc
386. atus that the is changing SAMSUNG ELECTRONICS 5 145 IT 4412 UM 5 Clock Management Unit 5 10 1 136 CLK DIV CPUO Base Address 0x1004 0000 e Address Base Address 04500 Reset Value 000 0000 RSV on DIVCORE2 Clock Divider Ratio CORES ARMCLK DOUTCORE CORE2 RATIO 1 SE em ea fo DIVAPLL Clock Divider Ratio pere SCLKAPLL MOUTAPLL APLL RATIO 1 SE a __ fo DIVPCLK_DBG Clock Divider Ratio j 22720 PCLK DBG ATCLK PCLK DBG RATIO 1 SE fo DIVATB Clock Divider Ratio ATE PATIO pel ATCLK MOUTCORE ATB_RATIO 1 SE ea o DIVPERIPH Clock Divider Ratio 14 12 PERIPHCLK DOUTCORE PERIPH_RATIO 1 ASV Jo DIVCOREM1 Clock Divider Ratio 10 8 ACLK_COREM1 ARMCLK COREM1_RATIO 1 DIVCOREMO Clock Divider Ratio SAREMBAG ACLK COREMO ARMCLK COREMO RATIO 1 DIVCORE Clock Divider Ratio CORE RATIO 2 0 RWX DIVCORE_OUT MOUTCORE CORE RATIO 1 SAMSUNG ELECTRONICS 5 146 ex 4412 UM 5 Clock Management Unit 5 10 1 137 DIV CPU1 e Base Address 0x1004 0000 e Address Base Address 0x4504 Reset Value 0x0000_0000 DIVCORES Clock Divider Ratio 198 ACLK_CORES ARMCLK CORES_RATIO 1 ig Sw m DIVHPM Clock Divider Ratio 6 4 SCLK_HPM DOUTCOPY HPM RATIO 1 S Gg fo D
387. aus cunmoum F mcus Bena gt Bena A mas Bena gt mau fasea Jj Rea mors moa E gt COCO Rem A Imo gt mos Resev A meier Je mee fe us mers mee fo mos mena A more mwena mm gt mors umm _ mons emm meno L nes e ee SAMSUNG ELECTRONICS ar IU 4412 UM 6 Interrupt Controller SPI Port No wo O ua Sauce ek moms CTN E mewo feom CO A mers mor rcm ENER m SAMSUNG ELECTRONICS 6 10 27 4412 UM 6 Interrupt Controller SPI Port No Ce maa mea 2 s EIS Mr ET r p 0000 27 IntGO 0 MDNIE LCDO 0 SAMSUNG ELECTRONICS 6 11 4412 UM 6 Interrupt Controller Table 6 3 describes the GIC interrupt PPI 15 0 Table 6 3 GIC Interrupt Table PPI 15 0 reparo a L3_IRQ for CPU3 or 12 28 L2_IRQ for 2 or L1 IRQ for CPU1 or LO IRQ for CPUO G3 IRQ for CPU3 or G2 IRQ for CPU2 or G1 IRQ for CPU1 o GO IRQ for CPUO s es ew gt 3
388. basic SFR configuration requires change in system clock divider values that are e DIV CPUO 31 0 target valueO e DIV 31 0 target value1 e DIV 31 0 target value2 e CLK DIV LEFTBUS 31 0 target value3 e DIV RIGHTBUS 31 0 target value4 Change the divider values for special clocks by setting CLK DIV XXX SFRs in CMU TOP e DIV XXX 31 0 target value The following sequence shows turn on PLL procedure Change PLL PMS values Set PMS values Set PDIV MDIV and SDIV values Refer to A M E V PLL CONO SFRs Change other PLL control values A M E V PLL CON1 31 0 target value Set AFC MRR MFR values if necessary Refer to M E V PLL 1 SFRs Turn on a PLL A M E V PLL CONO 31 1 Turn PLL Refer to V PLL SFRs wait lock time Wait until the PLL is locked MUK A M E V PLL SEL 1 Select the PLL output clock instead of input reference clock after PLL output clock is stabilized Refer to CLK_SRC_CPU SFR for APLL and MPLL CLK SRC for EPLL and VPLL Once a PLL is turned on do not turn it off SAMSUNG ELECTRONICS 5 15 x 4412 UM 5 Clock Management Unit 5 6 1 Clock Gating Exynos 4412 can disable the clock operation of each IP if it does not require This reduces the dynamic power consumption The two types of clock gating control register to disable or enable c
389. bit When the port is configured as functional pin the undefined value will be read 4 3 3 27 GPLOPUD e Base Address 0x1100 0000 e Address Base Address 0x00C8 Reset Value 0x1555 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down GPLOPUD n n 0to6 RW 0x2 Reserved 0x1555 0x3 Enables Pull up 4 3 3 28 GPLODRV e Base Address 0x1100_0000 e Address Base Address 0x00CC Reset Value 0x00_0000 23 16 Reserved Should be zero W GPL0DRV n n 2n 1 2n R 0x0000 0106 SAMSUNG ELECTRONICS 4 139 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 29 GPLOCONPDN e Base Address 0x1100 0000 e Address Base Address 0 0000 Reset Value 0x0000 0 0 Outputs 0 2n 1 21 0 1 Outputs 1 0106 FW oxo lt input 552 0 3 Previous state 4 3 3 30 GPLOPUDPDN e Base Address 0x1100 0000 e Address Base Address 0x00D4 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down 0106 0 2 Reserved 990 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 140 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 31 GPL1CON Base Address 0x1100 0000 e Address Base Address Reset Value 0x0000 0000 0 0 Input 0 1 Output GPL1CON 1 7 4 RW 0 2 GNSS SDA 0 00 0x3 to Reserved EXT_INT28 1
390. blending Data from output buffer appears in the Video Data Port NOTE The performance of the all these local input interfaces is limited by the scale ratio of the input and output image resolution TBD SAMSUNG ELECTRONICS 16 5 ex 4412 UM 16 Display Controller CAMIF2 CHO CAMIF1 CH1 CAMIF3 CH2 CH3 CH4 YUV RGB RGB YUV RGB YUV RGB RGB RGB RGB RWB888 LA LIMITER LIMITER LIMITER WIN1 R WIN2 RGB WIN3 R WIN4 RGB888 RGB888 RGB888 RGB888 Blending RGB888 Blending Color Keying RGB888 Blending Color Keying RGB888 Blending mma RGB RGB888 Color Gai RGB888 CSC las RGB888 RGB888 RGBe RGBb Figure 16 2 Block Diagram of the Data Flow SAMSUNG ELECTRONICS 16 6 I 4412 UM 16 Display Controller 16 3 2 1 Interface The display controller supports three types of interfaces e first type is the conventional RGB interface which uses RGB data vertical horizontal sync data valid signal and data sync clock e The second type is the indirect i80 Interface which uses address data chip select read write control and register status
391. cal operating frequencies for each function block in Exynos 4412 Table 5 1 Operating Frequencies Exynos 4412 2 200 MHz to 1 4 GHz CPU It is a Quad Core processor emenn CTN 2 2 MAUDIO AudioSS ROM RAM 192 MHz UART 12C SPI 2 PCM SPDIF PWM I2CHDMI 400 MHz Slimbus CHIPID SYSREG PMU CMU TMU Bus I F MCTimer WDT RTC KEYIF SECKEY TZPC NOTE Refer to Audio SubsystemChapter for more details MAUDIO block clocks SAMSUNG ELECTRONICS 5 2 x 4412 UM 5 Clock Management Unit 5 3 Clock Declaration The top level clocks in Exynos 4412 are Clocks from clock pads namely XRTCXTI and XUSBXTI Clocks from CMUs For instance ARMCLK ACLK HCLK and SCLK ARMCLK specifies clock for 9 MPCore up to 800 MHz 1 0 1 GHz 1 1 ACLK HCLK PCLK specify bus clocks SCLK Special clock specifies all clocks except bus clocks and processor core clock Clocks from USB PHY Clocks from HDMI_PHY Clocks from GPIO pads 5 3 1 Clocks from Clock Pads The clock pads derive the clocks They are XRTCXTI Specifies the clock generated from the crystal pad of 32 768 KHz with and XRTCXTO pins and XRTCXTO are the two pins of crystal pad uses this clock as a source to the real time clock requires a parallel resistance of 10 between the XUSBXTI and XU
392. ch is from clock controller You can also select SCLK_UART from various clock sources Refer to Chapter 7 Clock Controller for more information SAMSUNG ELECTRONICS 13 10 ex 4412 UM 13 Universal Asynchronous Receiver and Transmitter 13 5 Description Clears to send active low for UARTO Reguests to send active low for UARTO Clears to send active low for UART1 Requests to send active low for UART1 Clears to send active low for UART2 Requests to send active low for UART2 NOTE 1 Type filed indicates whether the signal connects to the dedicated pad or muliplexed signal pad s UART shares external pads with IrDA To use these pads set GPIO before the start of UART Refer to Chapter 6 GPIO for more information 2 UART4 has no ports It communicates with the internal GPS module SAMSUNG ELECTRONICS 13 11 ex 4412 UM 13 6 Register Description 13 6 1 Register Map Summary e Base Address 0x1380 0000 Base Address 0x1381_0000 e Base Address 0x1382_0000 e Base Address 0x1383 0000 Base Address 0x1384 0000 13 Universal Asynchronous Receiver and Transmitter Register Offset beserlon Reset Vate SAMSUNG ELECTRONICS 13 12 4412 UM 13 Universal Asynchronous Receiver and Transmitter 13 6 1 1 ULCONn 0 to 4 e Base Address 0x1380_0000 Base Address 0x1381_0000 Base Address 0x1382 0000 e Base Address 0x1383 0000 e Base Addres
393. ck for the input clock frequency of 24 MHz The equation to calculate the output frequency is Four K 65536 x Fin PDIV 2597 The conditions MDIV PDIV SDIV and K should meet are e PDIV 1x lt 63 e 16 lt lt 511 e SDIV 0 lt SDIV lt 5 e K 0 lt K lt 65535 e Fref Fpy PDIV where 4 MHz x Fref lt 30 MHz e Fvco K 65536 x FIN PDIV e Four should fall in the range of 22 MHz lt Four lt 1400 MHz Do not set the value or MDIV to all zeros Refer to the section 5 4 2 Recommended PLL PMS Value for EPLL for recommended PMS values SAMSUNG ELECTRONICS 5 48 ex 4412 UM 5 Clock Management Unit 5 10 1 20 EPLL_CON1 e Base Address 0 1003 0000 e Address Base Address 0xC114 Reset Value 0x6601 0000 28 24 Modulation Rate Control 23 16 Modulation Frequency Control 15 0 PLL 16 bit DSM Delta Sigma Modulator Refer to the section 5 4 2 Recommended PLL PMS Value for EPLL for the recommended value of K NN Modulation Method Control 1 Center spread SAMSUNG ELECTRONICS 5 49 ex 4412 UM 5 Clock Management Unit 5 10 1 21 EPLL CON2 e Base Address 0x1003 0000 e Address Base Address 0xC118 Reset Value 0 0000 0080 RSV 12 8 W AFC value Decides whether Duty Cycle Corrector DCC is enabled or not DCC_ENB 7 RW 0 Enables DCC 0x1 1 Disables DCC It is an
394. clear this write 1 1 Completes 4 bit ECC decoding Once Soft Lock or Lock tight is enabled and any illegal RW access program erase to the memory takes place then this bit is set 0 It does not detect illegal access 1 It detects illegal access To clear this value write 1 to this bit Transition configuration is set in RnB 5 IllegalAccess RnB TransDetect 4 Flash_nCE 1 3 The status of nCE 3 0 output pin OxF Read only When it completes 4 bit ECC encoding this bit is set and Flash nCE 0 it issues an interrupt if it enables MLCEncodeDone The NFMLCECCO and have valid values To Read only When RnB 0 low to high transition occurs this bit is set and an interrupt is issued if RnB TransDetect is enabled To clear this write 1 0 It does not detect RnB transition 1 It detects RnB transition Transition configuration is set in RnB 5 The status of nCE 1 output pin 1 The status of nCE 0 output pin 1 Reserved SAMSUNG ELECTRONICS 10 23 4412 UM 10 NAND Flash Controller f RnB 0 i i Flash RnB The status of RnB 0 input pin Read only RW 0 flash memory busy 1 NAND flash memory ready to operate SAMSUNG ELECTRONICS 10 24 ex 4412 UM 10 NAND Flash Controller 10 7 2 12 NFECCERRO Base Address 0xOCEO 0000 e Address Base Address
395. clock sources SCLK UARTS SCLK_UART4 SCLK SLIMBUS SLIMBUS clock SCI Keen see SCLK_MIPIHSI er core operating 200 MHz SCLKapu SAMSUNG ELECTRONICS 5 18 ex 4412 UM 5 Clock Management Unit e All possible clock sources include XUSBXTI SCLK HDMI24M SCLK_USBPHY SCLK_HDMIPHY SCLKzepu and SCLKvpu e XXTI and XUSBXTI refer to external crystal e SCLK USBPHY refers to USB PHY 48 MHz output clock e SCLK HDMI24M refers to HDMI PHY 24 MHz reference clock for XUSBXTI output e SCLK HDMIPHY refers to HDMI PHY PIXEL_CLKO output clock e SCLKep and SCLKvyp refer to the output clock EPLL VPLL respectively Table 5 6 describes the I O clocks in Exynos 4412 Table5 6 Clocks in Exynos 4412 IOCLK AC97 Xi2s1SCLK Func2 AC97BITCLK 12 288 MHz 97 Bit Clock _ 1250 Xi2s0CDCLK Funco 125 0 CDCLK IOCLK 1251 Input Xi2s1CDCLK Funco 125 1 CDCLK 83 4 MHz 125 CODEC Clock IOCLK 1252 Xpcm2EXTCLK Func2 128 2 CDCLK IOCLK_PCMO Xi2s0CDCLK Funct PCM 0 EXTCLK IOCLK PCM1 Input Xi2s1CDCLK Funct PCM 1 EXTCLK 83 4 MHz CODEC Clock PCM2 Xpcm2EXTCLK Func0 PCM 2 EXTCLK SPDIF Xpcm2EXTCLK Func1 SPDIF EXTCLK 36 864 MHz SPDIF Input Clock SAMSUNG ELECTRONICS 5 19 ex 4412 UM 5 Clock Management Unit 5 8 CLKOUT You can use the XCLKOUT port to monitor certain clocks Exyn
396. contrary if FC_EN is LOW then the filter clock divider does not divide FLT_CLK 17 4 Wakeup Source It uses KEYPAD inputs as wakeup source When it uses Key input for wakeup source from Audio playback STOP DSTOP or SLEEP mode it does not require KEYPAD interface register setting However GPIO register GPX1CON GPX2CON GPX3CON or GPL2CON should be set for KEYPAD interface and SYSCON register should be set for masking SAMSUNG ELECTRONICS 17 3 II 4412 UM 17 Keypad Interface 17 5 Keypad Scanning Procedure for Software Scan At initial state all column lines outputs are low level But column data output tri state enable bits are all high Therefore when it does not use the tri state enable mode these bits should be written to zeros When the status of the key is not pressed then all row lines inputs are high used pull up pads When you press any key then the corresponding row and column lines are shortened together and a low level is driven on the corresponding row line This generates a keypad interrupt The CPU software outputs a LOW on one column line and Hi Z on the others by setting KEYIFCOLEN and KEYIFCOL fields in KEYIFCOL register Each time when it writes the CPU reads the value of the KEYIFROW register and detects if one key of the corresponding column line is pressed If KEYIF has pull up PAD then it reads each KEYIFROW bits as HIGH except pressed ROW bit When the scanning procedure ends it det
397. cts Mux input for PWM timer 1 0000 1 1 an 0001 1 2 D MUX1 7 4 RW 7 4 0010 1 4 0011 1 8 0100 1 16 Selects Mux input for PWM timer 0 0000 1 1 i 0001 1 2 D MUX RW ivider MUKO 3 0 0010 1 4 0011 1 8 0100 1 16 SAMSUNG ELECTRONICS 11 16 ex 4412 UM 11 Pulse Width Modulation Timer 11 5 1 3 TCON e Base Address 0x139D_0000 PWM Base Address 0x1216 0000 ISP e Address Base Address 0x0008 Reset Value 0x0000 0000 RSVD 81 23 Reserved 0x000 Timer 4 auto reload on off 0 One shot 0 0 1 Interval mode auto reload Timer 4 manual 0 No operation 1 Updates 4 0 Stops Timer 4 Timer 4 start stop 20 1 Starts Timer 4 Timer 3 auto 0 One shot 0 Interval mode auto reload reload on off Timer 3 output 0 Inverter Off 0 inverter on off TOUT 3 inverter on Timer 3 manual 0 No operation 0 update Updates TCNTB3 0 Stops Timer 3 Timer 3 start stop Starts Timer 3 0 0 One shot Interval mode auto reload 0 Inverter Off TOUT_2 inverter on I update Timer 2 start stop Timer 1 auto reload on off 0 Stops Timer 2 Starts Timer 2 0 One shot Interval mode auto reload Timer 1 output 0 Inverter Off inverter on off TOUT_1 inverter on Timer 1 manual 0 No operation update 1 Updates 1 andTCMPB1 0 Stops Timer 1 Timer 1 start stop 1 Starts Timer 1 De
398. current serial output enable bit I2CSTAT setting 14 18 4412 UM 14 6 1 5 2 0 to 7 Filter enable Base Address Base Address Base Address Base Address Base Address Base Address Base Address Base Address Base Address 0x1386_0000 0x1387_0000 0x1388_0000 0x1389_0000 0x138A_0000 0x138B_0000 0x138C_0000 0x138D_0000 0x138E_0000 14 Inter Integrated Circuit Address Base Address 0x0010 Reset Value 0x00 SDA output delay SAMSUNG ELECTRONICS Reserved 12C bus filter enable bit When SDA port is operating as input set this bit to High This filter prevents error caused by glitch between two PCLK clocks 0 Disables Filter 1 Enables Filter 12C bus SDA line delay length selection bits The 2 controller delays the SDA line by following clock cycle 00 0 clock 01 5 clocks 10 10 clocks 11 15 clocks 14 19 4412 UM 15 Serial Peripheral Interface Serial Peripheral Interface 15 1 Overview Serial Peripheral Interface Exynos 4412 transfers serial data by using various peripherals SPI includes two 8 16 and 32 bit shift registers to transmit and receive data During an SPI transfer it simultaneously transmits shifts out serially and receives shifts in serially data SPI supports the protocols for National Semiconductor Microwire and Motorola Serial Peripheral Interface 15 2 Features The features of inclu
399. d Sets signaling method of EXT_INT2 2 0 0 Low level 0x1 High level EXT INT2 CON 2 10 8 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved Sets signaling method of EXT_INT2 1 0 0 Low level 0x1 High level EXT INT2 CON 1 6 4 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved SAMSUNG ELECTRONICS 4 63 ex 4412 UM 4 General Purpose Input Output GPIO Control Sets signaling method of EXT_INT2 0 0 0 Low level 0x1 High level EXT INT2 CON 0 RW 0x2 Triggers falling edge 0 0 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0 7 Reserved SAMSUNG ELECTRONICS 4 64 en 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 83 EXT_INT3CON e Base Address 0x1140_0000 e Address Base Address 0x0708 Reset Value 0x0000_0000 RSV ne 0 Sets signaling method of EXT_INT3 7 0x0 Low level 0x1 High level EXT_INT3_CON 7 80 28 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0 7 Reserved 85 2 ne fm Sets signaling method of EXT INT3 6 0x0 Low level 0 1 High level EXT CON 6 26 24 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0 7 Reserved SVO gp Rem ov _ Sets signaling method of EXT
400. d Should be zero W GPK1DRVin n 2n 1 2n R 0x0000 0106 SAMSUNG ELECTRONICS 4 130 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 11 GPK1CONPDN e Base Address 0x1100 0000 e Address Base Address 0x0070 Reset Value 0x0000 0 0 Outputs 0 2n 1 21 0 1 Outputs 1 OPRALA n 0t06 FW ox2 Input 999 0 3 Previous state 4 3 3 12 GPK1PUDPDN Base Address 0x1100_0000 e Address Base Address 0x0074 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down GPR 0106 0 2 Reserved 990 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 131 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 13 GPK2CON Base Address 0x1100 0000 e Address Base Address 0x0080 Reset Value 0x0000_0000 0 0 Input 0 1 Output GPK2CON 6 27 24 RW 0 2 SD 2 DATA 3 0 00 0x3 to Reserved EXT INT25 6 0 0 Input 0 1 Output GPK2CON 5 23 20 RW 0 2 SD 2 DATA 2 0 00 0x3 to Reserved EXT INT25 5 0 0 Input 0 1 Output GPK2CON 4 19 16 0 2 SD_2 DATA 1 0 00 0x3 to Reserved EXT INT25 4 0 0 Input 0 1 Output GPK2CON 3 15 12 0 2 SD 2 DATA 0 0 00 0x3 to Reserved EXT INT25 3 0 0 Input 0 1 Output 0 2 SD 2 CDn GPK2CON 2 11 8 0x3 GNSS GPIOL10 0 00 0 4 to Reserved
401. data and D 4 0 Blue data SAMSUNG ELECTRONICS 16 14 x 4412 UM 16 Display Controller 16 3 3 2 7 16 BPP Display 1555 Figure 16 11 illustrates the 16 BPP display WSWP 1 WSWP DI 63 48 P8 Pi re ra Pa LCD Panel Figure 16 11 Memory Format of 16 BPP 1555 Display NOTE D 14 10 D 15 Red data D 9 5 D15 Green data and D 4 0 D 15 Blue data SAMSUNG ELECTRONICS 16 15 ex 4412 UM 16 Display Controller 16 3 3 2 8 16 BPP Display 565 Figure 16 12 illustrates the 16 BPP display BSWP 0 HWSWRP 0 WSWP 0 D 63 48 D 47 32 000H P1 P2 008H P5 P6 010H P9 BSWP 0 HWSWR 0 WSWP 1 000H D 63 48 P3 D 47 32 008 7 010H BSWP 0 HWSWRE 1 WSWP 063 48 D 47 32 D 31 16 D 150 000H P4 P2 P1 008H P8 P6 P5 010H P9 Pi Pe 16 12 LCD Panel NOTE D 15 10 Red data D 10 5 Green data and D 4 0 Blue data SAMSUNG ELECTRONICS 16 16 Memory Format of 16 BPP 565 Display 4412 UM 16 Display Controller Figure 16 13 illustrates the 16 BPP 5 6 5 display types 31 30 29 2
402. ddress 0 524 Reset Value 0 0000 0000 ASVD peg mesemes 0 0 DIVTV_BLK Clock Divider Ratio Te BEE RATIO P jii SCLK PIXEL SCLKVPLL TV BLK RATIO 1 SAMSUNG ELECTRONICS 5 85 ex 4412 UM 5 Clock Management Unit 5 10 1 54 CLK_DIV_MFC e Base Address 0x1003 0000 e Address Base Address 0xC528 Reset Value 0 0000 0000 RSV ove meseros 09 DIVMFC Clock Divider Ratio 8 0 SCLK MOUTMFC MFC RATIO 1 5 10 1 55 DIV G3D e Base Address 0 1003 0000 e Address Base Address 0xC52C Reset Value 0x0000 0000 ASV ove SCS DIVG3D Clock Divider Ratio 5 0 SCLK G3D MOUTG3D G3D RATIO 1 5 10 1 56 CLK DIV LCD Base Address 0x1003 0000 e Address Base Address 0xC534 Reset Value 0x0070 0000 RSVD 31 24 0x0 x7 MIPIO_PRE_ 23 20 RW DIVMIPIO_PRE Clock Divider Ratio 0 SCLK_MIPIO DOUTMIPIO MIPIO_PRE_RATIO 1 DIVMIPIO Clock Divider Ratio MIPIO RATIO 19 16 RW SCLK_MIPIDPHY4L MOUTMIPIO 0 RATIO 1 DIVMDNIE PWMO Clock Divider Ratio MDNIE_PWM E PRE 15 12 RW SCLK MDNIE PWMO DOUTMDNIE PWMO _ _ _ 1 DIVMDNIE PWMO Clock Divider Ratio MDNIE PWM RATIO 11 8 RW DOUTMDNIE PWMO MOUTMDNIE PWMO MDNIE PWMO RATIO 1 DIVMDNIEO Clock Divider Ratio MDNIEO RATIO 7 4 RW SCLK MDNIEO MOUTMDNIEO MDNIEO RATIO 1 DIVFIMDO Clock Divid
403. ddress 0x1100 0000 e Address Base Address 0x0C04 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPXODAT 7 0 7 0 output port then pin state should be same as 0x00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 3 196 GPXOPUD Base Address 0x1100 0000 e Address Base Address 8 Reset Value 0x5555 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down GPXOPUDIn N 0t07 RW 0x2 Reserved 0x5555 0x3 Enables Pull up 4 3 3 197 GPX0DRV e Base Address 0x1100_0000 e Address Base Address 0x0C0C Reset Value 0x00_0000 23 16 Reserved Should be zero W GPXODRVIn 2n 1 2n 0107 0x0000 SAMSUNG ELECTRONICS 4 254 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 198 GPX1CON e Base Address 0x1100 0000 e Address Base Address 0x0C20 Reset Value 0x0000 0000 0 0 Input 0 1 Output 0 2 Reserved GPX1CON 7 31 28 WA 2 0x00 0 5 ALV DBG 11 0x6 to OxE Reserved OxF WAKEUP_INT1 7 0 0 Input 0 1 Output 0 2 Reserved GPX1CON 6 27 24 0x00 0 5 ALV DBG 10 0x6 to 0xE Reserved OxF WAKEUP_INT1 6 0 0 Input 0 1 Output 0 2 Reserved GPX1CONI 5 23 20 Ne E 0x00 0 5 ALV DBG 9 0x6 to OxE Reserved WAKEUP INT1 5 0 0 Input 0 1 Outp
404. de e Full duplex e 8 16 32 bit shift register for Tx Rx e Supports 8 bit 16 bit 32 bit bus interface Supports the Motorola SPI protocol and National Semiconductor Microwire e Two independent 32 bits wide transmit and receive FIFOs depth 64 in port 0 and depth 16 in port 1 and 2 e Master mode and Slave mode e Receive without transmit operation e maximum frequency at up to 50 MHz SAMSUNG ELECTRONICS 15 1 ex 4412 UM 15 Serial Peripheral Interface 15 2 1 Operation of SPI SPI transfers 1 bit serial data between Exynos 4412 and external device The in Exynos 4412 supports the CPU or DMA to transmit or receive FIFOs separately and to transfer data in both directions simultaneously SPI has two channels namely Tx channel and Rx channel Tx channel has the path from Tx FIFO to external device Rx channel has the path from external device to Rx FIFO CPU or DMA must write data on the register SPI_TX_DATA to write data in FIFO Data on the register are automatically moved to Tx FIFOs To read data from Rx FIFOs CPU or DMA must access the register SPI_RX_DATA and data are automatically sent to the SPI_RX_DATA register CMU registers can control SPI operating frequency Refer to CMU chapter for more information 15 2 1 1 Operation Mode SPI has two modes namely master and slave mode In master mode SPICLK is generated and transmitted to external device XspiCS which is the signal to
405. defined value will be read 4 3 2 51 GPF1PUD Base Address 0x1140_0000 e Address Base Address 0x01A8 Reset Value 0x5555 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down GPF1PUD n n 0io7 RW x Reserved 0x5555 0 3 Enables Pull up 4 3 2 52 GPF1DRV e Base Address 0x1140 0000 e Address Base Address 0x01AC Reset Value 0x00 0000 23 16 Reserved should be zero W GPF1DRV n n 2n 1 2 0x0000 0107 SAMSUNG ELECTRONICS 4 47 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 53 GPF1CONPDN e Base Address 0x1140_0000 e Address Base Address 0x01B0 Reset Value 0x0000 0x0 Outputs O 2n 1 2n 0x1 Outputs 1 0107 RW 0x2 Input me 0 3 Previous state 4 3 2 54 GPF1PUDPDN e Base Address 0x1140 0000 e Address Base Address 0x01B4 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down 0107 BW 0 2 Reserved oe 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 48 ex 4412 UM 4 3 2 55 GPF2CON Base Address 0x1140 0000 e Address Base Address 0 01 0 Reset Value 0 0000 0000 GPF2CON 7 GPF2CON 6 GPF2CON 5 GPF2CON 4 31 28 SAMSUNG ELECTRONICS 0 0 Input 0 1 Output 0 2 LCD VD 19 0x3 to Reserved EXT_INT15 7 0 0 Input 0 1 Output 0 2 LCD VD 18 0x3 to Reserv
406. divider is changing SE nes DIVHPM Status DIV HPM 4 0 Stable 1 Status that the divider is changing SE DIVCOPY Status DIV COPY 0 Stable 1 Status that the divider is changing 5 10 1 140 CLK GATE IP CPU e Base Address 0x1004 0000 e Address Base Address 0x4900 Reset Value FFFF RSVD 31 2 Reserved OxFFFF FFF3 Gating all clocks for CoreSight and SecureJTAG CLK_CSSYS 1 0 Mask 1 Pass Gating all clocks for CLK HPM 0 Mask 0 1 1 Pass SAMSUNG ELECTRONICS 5 149 ex 4412 UM 5 Clock Management Unit 5 10 1 141 CLKOUT CMU CPU e Base Address 0x1004 0000 e Address Base Address 0x4A00 Reset Value 0x0001_0000 ASV Rea 1 Enable CLKOUT CLKOUT 16 RW 0 Disables 1 Enables RSVD 15 14 Reserved Divide Ratio Divide ratio DIV RATIO 1 DIV_RATIO 13 8 ASV 75 Es MUX Selection 00000 APLL FOUT 2 00001 Reserved 00010 Reserved 00011 Reserved 00100 ARMCLK 2 00101 ACLK_COREMO 00110 ACLK COREM1 MUX_SEL 4 0 RW 00111 ACLK CORES 0 0 01000 ATCLK 01001 PERIPHCLK 01010 PCLK DBG 01011 SCLK HPM ATCLK and PCLK DBG are the gated clocks You should not gate ATCLK or PCLK_DBG clocks before changing the DIV_RATIO value on selection of ATCLK or PCLK_DBG 5 10 1 142 CLKOUT_CMU_CPU_DIV_STAT e Base Address 0x1004 0000 e Address Base Address 0
407. down mode configuration register 0 0000 GPY4PUDPDN 0x01B4 4 power down mode pull up pull down 0x0000 GPY5CON 0x01C0 Port group GPY5 configuration register 0x0000_0000 GPY5DAT 0x01C4 Port group data register 0 00 GPY5PUD 0x01C8 Port group GPY5 pull up pull down register 0x5555 GPYSDRV 0x01CC Port group GPY5 drive strength control register 0 00_ GPY5CONPDN 0 0100 Port group GPY5 power down mode configuration register 0 0000 GPYSPUDPDN 0x01D4 ae GPY5 power down mode pull up pull down 0x0000 GPY6CON 0 01 0 Port group GPY6 configuration register 0x0000_0000 GPY6DAT 0x01E4 Port group GPY6 data register 0 00 GPY6DRV 0 01 Port group GPY6 drive strength control register 0 00_ GPY6CONPDN 0 01 0 Port group GPY6 power down mode configuration register 0 0000 GPYGPUDPDN 0x01F4 m GPY6 power down mode pull up pull down 0x0000 ETCOPUD 0x0208 Port group ETCO pull up pull down register 0x0400 ETC6PUD 0x0228 Port group ETC6 pull up pull down register 0 000 ETC6DRV 0x022C Port group ETC6 drive strength control register 0x00 0000 GPMOCON 0x0260 Port group GPMO configuration register 0x0000 0000 GPMODAT 0 0264 Port group GPMO data register 0 00 GPMOPUD 00268 Port group GPMO pull up pull down register 0x5555 GPMODRV 0 026 Port group GPMO drive strength control register 0x00 0000 GPMOCONPDN 0x0270 Port group GPMO power down mode configuration register 0 0000
408. dress 0x0830 Reset Value 0x0000_0000 Filter Enable for EXT_INT27 3 FLTEN7 3 31 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH7 3 30 24 Filtering width of EXT_INT27 3 Filter Enable for EXT_INT27 2 FLTEN7 2 23 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH7 2 22 16 Filtering width of EXT INT27 2 Filter Enable for EXT INT27 1 FLTEN7 1 15 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH7 1 14 8 Filtering width of EXT INT27 1 Filter Enable for EXT INT27 0 FLTEN7 O 7 RW Disables Filter 0 1 Enables Filter FLTWIDTH7 0 1601 RW Filtering width of EXT INT27 0 4 3 3 140 EXT INT27 1 Base Address 0x1100 0000 e Address Base Address 0x0834 Reset Value 0x0000 0000 RSV eee 9 Filter Enable for EXT_INT27 6 FLTEN7 6 23 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH7 6 22 16 Filtering width of EXT INT27 6 Filter Enable for EXT INT27 5 FLTEN7 5 15 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH7 5 14 8 Filtering width of EXT_INT27 5 Filter Enable for EXT_INT27 4 FLTEN7 4 7 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH7 4 1601 RW Filtering width of EXT 27 4 SAMSUNG ELECTRONICS 4 218 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 141 EKT INT28 FLTCONO e Base Address 0x1100 0000 e Address B
409. dress 0x1140_0000 e Address Base Address 0x086C Reset Value 0x0000_0000 Filter Enable for EXT INT14 7 FLTEN14 7 31 RW 0 0 Disables filter 0 1 Enables filter FLTWIDTH14 7 30 24 Filtering width of EXT INT14 7 Filter Enable for EXT INT14 6 FLTEN14 6 23 RW 0 0 Disables filter 0x1 Enables filter FLTWIDTH14 6 22 16 Filtering width of EXT INT14 6 Filter Enable for EXT_INT14 5 FLTEN14 5 15 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH14 5 14 8 Filtering width of EXT INT14 5 Filter Enable for EXT INT14 4 FLTEN14 4 7 RW 0 0 Disables filter 0x1 Enables filter FLTWIDTH14 4 6 0 RW Filtering width of EXT_INT14 4 SAMSUNG ELECTRONICS 4 94 en 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 112 EXT_INT15_FLTCONO Base Address 0x1140_0000 e Address Base Address 0x0870 Reset Value 0 0000 0000 Filter Enable for EXT_INT15 3 FLTEN15 3 31 RW 0 0 Disables filter 0 1 Enables filter FLTWIDTH15 3 30 24 Filtering width of EXT INT15 3 Filter Enable for EXT INT15 2 FLTEN15 2 23 RW 0 0 Disables filter 0x1 Enables filter FLTWIDTH15 2 22 16 Filtering width of EXT_INT15 2 Filter Enable for EXT_INT15 1 FLTEN15 1 15 RW 0 0 Disables filter 0 1 Enables filter FLTWIDTH15 1 14 8 Filtering width of EXT INT15 1 Filter Enable for EXT INT15 0 FLTEN15 0 7 RW 0x0 Disables filt
410. e Descripti n Reset Value ASVO Guss SYSMMU MFC M1 1 30 Sets the corresponding interrupt enable bit to 1 If you interrupt enable bit interrupt combiner SYSMMU MFG 29 serves the interrupt request SYSMMU_TV_MO 1 28 RW Write 0 Does not change the current setting RSVD 27 1 Sets the interrupt enable bit to 1 o SYSMMU LCDO MO 26 RW Read The current interrupt enable bit 59000 0 Masks SYSMMU_GPS 1 125 1 Enables __ SYSMMU_ROTATOR 1 24 0000 SYSMMU 2011 23 EN NN SYSMMU JPEG 1 22 Sets the corresponding interrupt enable bit to 1 If SYSMMU FIMC3 1 21 you set the interrupt enable bit interrupt combiner serves the interrupt request SYSMMU FIMC2 1 20 Write 0 Does not change the current setting 0 SYSMMU FIMC1 1 19 1 Sets the interrupt enable bit to 1 SYSMMU FIMCO 1 18 BW Read The current interrupt enable bit 0 Masks SYSMMU 5550 17 1 Enables NE NE RSVD us __ SYSMMU_MFC_M1 0 14 Sets the corresponding interrupt enable bit to 1 If SYSMMU 13 you set the interrupt enable bit interrupt combiner serves the interrupt reguest SYSMMU MO 0 12 Write 0 Does not change the current setting o RSVD 11 MEN 1 Sets the interrupt enable bit to 1 SYSMMU_LCDO_MOJO 10 R
411. e 8 gt CLKEN C2C SCLKupu El Er 8 synchronous co 4 clocks MOUTec ACLK DMCD SCLKyou wa A ACLK DMCP gt 1 ACLK gt r DiVace i fo 1 1 8 MOUT 1 8 gt A SCLKwu PHY DLL clock synchronous DIV SCLK DPHY clocks SC i 3 DOSCLK_DPHY1_GATED 3 EOS _ 2 DiVosu IECDPMCLKEN PCLKIEM IEC 17128 IECDVSEMCLKEN DIVovsem 1 128 gated when IEM_IEC clocks are turned off XusbXTI UXpwi HDMI27M SCLK USBPHYO SCLK_PWI SCLK MOUTewn SCLK you SCLK you SCLKwu SK EST MOUTazo ace 1 DiVaci 400 se to MCUISP 1 8 a to GPS to MFC PCLK PERIL PERIR to CAM TV LCDO USB PHY HDMI PHY SAMSUNG ELECTRONICS 5 11 4412 UM 5 Clock Management Unit ACLK GDL is also used for G3D ACLK for synchronization ACLK GDL ACLK GDR ACLK GPL ACLK GPR gt synchronous synchronous clocks clocks gt ACLK MCUISP DIVO DIVucuispoivo 1 8 ACLK_MCUISP_DIV1 DiVucuisPpivi GLK MGUISP ACLK 200 MUXED gt DlVisepivo ACLK
412. e 0x3 Triggers Rising edge 0 4 Triggers Both edge 0 5 to 0 7 Reserved SAMSUNG ELECTRONICS 4 269 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 213 EXT_INT43CON e Base Address 0x1100 0000 e Address Base Address OxOEOC Reset Value 0x0000 0000 RSV eee Sets signaling method of EXT_INT43 7 0 0 Low level 0x1 High level EXT INT43 CON 7 30 28 RW 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0x5 to 0 7 Reserved 85 2 mee Sets signaling method of EXT_INT43 6 0 0 Low level 0x1 High level EXT_INT43_CON 6 26 24 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0 7 Reserved SVO Eq nene pf 9 _ Sets signaling method of EXT INT43 5 0 0 Low level 0 1 High level EXT INT43 CON 5 22 20 RW 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0x5 to 0 7 Reserved 85 0 pm Sets signaling method of EXT INT43 4 0 0 Low level 0 1 High level EXT INT43 CON 4 18 16 RW 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0x5 to 0 7 Reserved 85 9 mp ov Sets signaling method of EXT_INT43 3 0 0 Low level 0x1 High level EXT INT43 CON 3 14 12 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to
413. e 16 BPP L1 DATA16 25 23 RW 001 16 2 bit mode 18 BPP 010 9 9 bit mode 18 BPP 011 16 8 bit mode 24 BPP 100 18 bit mode 18 BPP 101 8 8 bit mode 16 BPP 4412 UM 16 Display Controller 0 RGB parallel format Controls inverting RGB ORDER atVIDCONS3 0 Normal RGBORDER 2 atVIDCON3 PNRMODE 17 RW 1 Invert to AIMIDCONS NOTE You can use this bit for the previous version of FIMD You do not have to use this bit if you use RGB ORDER atVIDCONG register Selects CLKVAL F update timing control CLKVALUP 16 RW 0 Always 1 Start of a frame only once per frame avo eee 1995 Determines rates of and CLKVAL 7 0 CLKVAL F 13 6 RW gt wnaem CLKVAL gt 1 NOTE The maximum frequency of VCLK is 80 MHz 80 MHz for Display Controller Controls VCLK Free Run only valid at RGB IF mode VCLKFREE 5 RW 0 Normal mode controls using ENVID 1 Free run mode Reserved dd 4 2 NOTE This bit should be set 0 Enables disables video output and logic immediately ENVID 1 RW 0 Disables the video output and display control signal 1 Enables the video output and display control signal Enables disables video output and logic at current frame end 0 Disables the video output and display control signal ENVID F RW 1 the video output and display control signal If this bit is set
414. e Address 0x0024 Reset Value 0x0000 0000 RSVD mea Reed T EBLK_ADDR2 23 16 The 3 block address of the block erase operation EBLK_ADDR1 15 8 The 2 block address of the block erase operation 0 00 The 1 block address of the block erase operation ADORO 91 Only bit 7 5 are valid NOTE Address of Advance Flash block starts from 3 address cycle block address register only reguires 3 bytes Refer to 10 4 12 Lock Scheme for Data Protection for more information on lock scheme SAMSUNG ELECTRONICS 10 22 ex 4412 UM 10 NAND Flash Controller 10 7 2 11 NFSTAT Base Address OXOCEO 0000 e Address Base Address 0x0028 Reset Value 0xF080 OFOD The status of RnB 3 0 input pin Flash RnB GRP 31 28 RW 0 flash memory busy 1 NAND flash memory ready to operate When RnB 3 0 low to high transition occurs this bit is RnB TransDetect _ GBP 27 24 set and an interrupt is issued if RnB TransDetect GRP is enabled To clear this write 1 Flash nCE 3 0 11 8 Read only 0 RnB transition is not detected 1 RnB transition is detected 12 8 MLCEncodeDone MLCDecodeDone 5 clear this write 1 1 It completes 4 bit ECC encoding When it completes 4 bit ECC decoding this bit is set and it issues an interrupt if it enables MLCDecodeDone The RW NFMLCLO and NFMLCEL1 have valid values To
415. e Address Base Address 0xC340 Reset Value 0 0101_1111 RSV ras noe 0 Mask output clock of MUXMIPIHSI MIPIHSI_MASK 24 RW 0 Mask 1 Unmask mo Mask output clock of MUXMMC4 MMC4 MASK 16 RW 0 Mask 1 Unmask SE fm Mask output clock MUXMMC3 MMC3 MASK 12 RW 0 Mask 1 Unmask SE ma om Mask output clock of MUXMMC2 MMC2 MASK RW 0 Mask 1 Unmask S va eva mo Mask output clock of MUXMMC 1 MMC1_MASK 4 RW 0 Mask 1 Unmask 85 0 Rewd AN Mask output clock of MUXMMCO MMCO MASK RW 0 Mask 1 Unmask SAMSUNG ELECTRONICS 5 76 x 4412 UM 5 Clock Management Unit 5 10 1 44 CLK SRC MASK PERILO e Base Address 0x1003 0000 e Address Base Address 0xC350 Reset Value 0x0001 1111 RSVD am mesoner 0 Mask output clock of MUXUART4 UART4_MASK 16 RW 0 Mask 1 Unmask SE mo Mask output clock of MUXUART3 UART3_MASK 12 RW 0 Mask 1 Unmask SE ma mo Mask output clock of MUXUART2 UART2_MASK 8 RW 0 Mask 1 Unmask SE fo Mask output clock of MUXUART 1 UART1_MASK 4 RW 0 Mask 1 Unmask SE ___ fo Mask output clock of MUXUARTO UARTO_MASK 0 RW 0 Mask 1 Unmask SAMSUNG ELECTRONICS 5 77 IT 4412 UM 5 Clock Management Unit 5 10 1 45 CLK SRC MASK PERILI e Base Address 0x1003 0000
416. e Address Base Address 0xC354 Reset Value 0 0111_0111 RSV eras 100 Mask output clock of MUXSPI2 SPI2 MASK 24 RW 0 Mask 1 Unmask SE o Mask output clock of MUXSPI1 SPI1_MASK 20 RW 0 Mask 1 Unmask S mem Jo Mask output clock of MUXSPI0 SPIO MASK 16 RW 0 Mask 1 Unmask Avo mss Mask output clock of MUKSPDIF SPDIF MASK RW 0 Mask 1 Unmask Avo Mask output clock of MUXAUDIO2 AUDIO2_MASK 4 RW 0 Mask 1 Unmask 85 9 AT Mask output clock of MUXAUDIO1 AUDIO1_MASK RW 0 Mask 1 Unmask SAMSUNG ELECTRONICS 5 78 x 4412 UM 5 Clock Management Unit 5 10 1 46 CLK_MUX_STAT_TOP e Base Address 0 1003 0000 e Address Base Address 0xC410 Reset Value 0 1111_1111 RSV on noen Selection signal status of MUXONENAND ONENAND SEL 30 28 e 1 Status that the is changing SE moms 99 Selection signal status of MUXACLK 133 ACLK 133 SEL 26 24 1 Status that the is changing SE Eq eee 99 Selection signal status of MUXACLK 160 ACLK 160 SEL 22 20 ae B SCAM 1xx Status that the is changing SE 99 Selection signal status of MUXACLK 100 ACLK 100 SEL 18 16 1 Status that the is changing SE mq eee 99 Selection signal status of MUXACLK 200 ACLK
417. e location of 4 bit error RSVD Reewd ao MLCErrLocation3 o R Error byte location of 3 bit error 0 000 NOTE These values are updated when ECCDecodeDone NFSTAT 6 is set 1 10 7 2 14 NFMECCO e Base Address OXOCEO 0000 e Address Base Address 0x0034 Reset Value OxFFFF_FFFF When ECC Type is 1 bit ECC MECC3 31 24 for data 2 23 16 2 for data 15 8 for data MECCO 70 ECCO for data NOTE The NAND flash controller generate 1 when read or write main area data while the MainECCLock 7 bit is 0 Unlock When ECC Type is 4 bit ECC 4 Parity 31 24 4 Check generated from main area 512 byte 3 23 16 NN 3 Check parity generated from main area 512 byte 2 Parity 15 8 NM 27 Check generated from main area 512 byte 0 00 1 7 0 1 Check generated from main area 512 byte 0x00 NOTE The NAND flash controller generates these ECC parity codes when write main area data while the MainECCLock NFCON 7 bit is 0 unlock SAMSUNG ELECTRONICS 10 27 x 4412 UM 10 NAND Flash Controller 10 7 2 15 NFMECC1 e Base Address OXOCEO 0000 e Address Base Address 0x0038 Reset Value OxFFFF_FFFF When ECC Type is 4 bit ECC 7 23 16 7 Check generated from main area 512
418. e writing data 2 Whenever data is written the corresponding 8 12 16 bit ECC module generates ECC code internally 3 After you complete writing 512 byte data excluding spare area data the parity codes are automatically updated to the NFECCPRGO NFECCPRGECCE registers If you use a flash memory that contains 512 byte page you can program these values to spare area However if you use a NAND flash memory more than 512 byte page you cannot program immediately In this case you should copy these ECC parity codes to other memory like DRAM After writing all main data you can write the copied ECC values to spare area The parity codes have self correctable information including parity code itself The following table describes the ECC parity size ECC Type Size of ECC Parity Codes 8 bit ECC 13 byte 4 generate spare area ECC code for meta data the steps are similar from 1 3 except setting the MsgLenght NFECCCONF 25 16 to the size that you prefer When you set NFECCCONT 2 all ECC parity codes generated for main data are cleared Therefore you should copy the ECC parity codes for main data NOTE You should set the ECC parity conversion codes to verify free page error Refer to 10 4 11 ECC Conversion Code Guide for 8 12 16 bit ECC for more information SAMSUNG ELECTRONICS 10 10 II 4412 UM 10 NAND Flash Controller 10 4 10 8 12 16 bit ECC Programming
419. ect this pending status u 25 0 The interrupt is not pending LCDO 0 24 1 The interrupt is pending DMC1 PPC PEREV M 23 R DMC1 PPC PEREV A 22 DMCO PPC PEREV M 21 Interrupts pending status se DMCO PPC PEREV A 20 The corresponding interrupt enable bit does not HEER Cua R affect this pending status 0 The interrupt is pending L2CACHE 18 1 The interrupt is pending RP TIMER R GPIO_AUDIO R a RSVD reserved 1 a PPMU_MFC_MO 13 PPMU MFC MO 13 pending status PPMU 30 12 The corresponding interrupt enable bit does not __ PPMU TV MO 11 affect this pending status PPMU FILE D MO 10 0 The interrupt is pending ee 1 The interrupt is pending PPMU_LCDO PPMU_IMAGE MO m R 6 PPMU D RIGHT MO BI R Interrupt pending status E ow D LEFT The corresponding interrupt enable bit does not PPMU D LEFT MO 4 a R affect this pending status _ n 0 The interrupt is not pending PPMU_XIU_R_S1 1 The interrupt is pending R SAMSUNG ELECTRONICS 7 20 IT 4412 UM 7 Interrupt Combiner 7 6 2 12 IMSR2 e Base Address 0x1044 0000 e Address Base Address 0x00
420. ects the pressed key one or more Figure 17 3 illustrates the keypad scanning procedure ull up PAD lt s P P P P NNN Y lt lt lt F lt F F lt PC PC COP PS P Ps Pc NNN F lt lt P NN x Fx Fx Fx Fx F lt F lt NY N Ny NY lt lt lt hat lt lt lt lt lt N N le lt Ny 1 N ID TE N lt N N NN IN x P PP Ye y else NNN NNN NNN F lt x lt x lt lt PC lt lt Ne NC e i lt lt lt e lt x Inn Ivy x DPI X PX YC YC NNN NN NN SN x lt S N S P lt N N SYN N NM x x x x SCAN X 13 X 13 SCAN_Y 0 SCAN Y 0 SCAN Y 7 SCAN Y 7 Figure 17 3 Keypad Scanning Procedure SAMSUNG ELECTRONICS 17 4 iD 4412 UM Figure 17 4 illustrates the keypad scanning procedure Il Interrupt generated and knows which row is pressed 17 Keypad Interface ead KEYIN register All High if not matche a
421. ed OxF EXT_INT15 6 0 0 Input 0 1 Output 0 2 LCD VD 17 0x3 to Reserved OxF EXT INT15 5 0 0 Input 0 1 Output 0 2 LCD VD 16 0x3 to Reserved EXT INT15 4 0 0 Input 0 1 Output 0 2 LCD VD 15 0x3 to Reserved OxF EXT_INT15 3 0 0 Input 0 1 Output 0 2 LCD VD 14 0x3 to Reserved EXT INT15 2 0 0 Input 0x1 Output 0 2 LCD VD 13 0x3 to Reserved OxF EXT_INT15 1 0 0 Input 0 1 Output 0 2 LCD VD 12 0x3 to Reserved OxF EXT_INT15 0 4 49 4 General Purpose Input Output GPIO Control 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 56 GPF2DAT Base Address 0x1140_0000 e Address Base Address 0x01C4 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPF2DAT 7 0 7 0 output port the pin state should be same as the 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 2 57 GPF2PUD Base Address 0x1140_0000 e Address Base Address 0x01C8 Reset Value 0x5555 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down GPF2PUD n n 0io7 RW x Reserved 0x5555 0 3 Enables Pull up 4 3 2 58 GPF2DRV e Base Address 0x1140 0000 e Address Base Address 0x01CC Reset Value 0x00
422. een data s Blue data Red data Window 0 Window 1 s Data Data Data Data 1 Background s blending equationl factor al Foreground s blending equationl factor b2 Background s blending equation2 factor a2 Foreground s blending equation2 factor lt Alpha value blending gt AR G B 01 AR 0 x ql AR G B 1 x pl AR G B 012 AR G B 01 x q2 AR G B 2 x p2 AR G B 0123 AR G B 012 x q3 AR G B 3 x p3 where Window 0 s Window 0 s Window 0 s Window 1 s Red blending factor Green blending factor Blue blending factor Red blending factor 16 Display Controller RO1 601 01 Window01 s Blue blending factor 8012 Window012 s Window01 s Red blending factor alpha value blending between ARO and ARI alpha value blending between AGO and AG1 alpha value blending between ABO and 1 alpha value blending between ARO1 and AR2 Window01 s Green blending factor pp PP PP Pp Red blending factor Background s Alpha value blending equationl factor Foreground s Alpha value blending equationl factor value Background s Alpha blending equation2 factor Foreground s Alpha value blending equation2 factor SAMSUNG ELECTRONICS 16 27 4412 UM 16 Display Controller Figure 16 23 illustrates the blending eguation alphaB alphaA axA bxB Blending T alphaB p x alphaA alphaB a b p q 0
423. elect Pin FSEL 27 RW 0 our Frer 1 Fvco our em ee RD _____ ov The reset value of MPLL_CONO generates a 800 MHz output clock for an input clock frequency of 24 MHz The equation to calculate the output frequency is FOUT x FIN PDIV x 2597 24 9 MHz lt FOUT lt 1400 MHz The conditions SDIV APLL and MPLL should meet are PDIV 1 lt lt 63 e 64 lt lt 1023 e SDIV 0 lt SDIV lt 5 Fref FIN PDIV Fref should fall in the range of 2 MHz lt Fref lt 12 MHzFVCO x FIN PDIV should fall in the range of 700 MHz lt FVCO lt 1400 MHz Refer to the section 5 4 1 Recommended PLL PMS Value for APLL and MPLL for recommended PMS values SAMSUNG ELECTRONICS 5 122 ex 4412 UM 5 Clock Management Unit 5 10 1 106 MPLL_CON1 e Base Address 0x1004 0000 e Address Base Address 0x010C Reset Value 0 0080_3800 Specifies status of Linear Region Detector LDR 0 when it detects low signal Specifies VCO range boost up when the signal is high If BYPASS 1 then it enables bypass mode Four Fly If BYPASS 0 then the PLL3500X operates normally RSVD 81 25 BYPASS 22 PCG ENB 21 1 Disables DCC is an active low signal R EN ES m Decides whether AFC is enabled or not 0 Enables AFG LENS 20 RW Disables A
424. em Interface Write Cycle Timing Figure 16 31 illustrates the indirect 180 system interface write cycle timing VCLK Internal 1 1 SYS RS LCD CS SETUP 1 i gt LCD WR HOLD 1 f gt H 1 4 LCD WR gt LCD CS SETUP 0 LCD WR SETUP 0 LCD WR ACT 0 LCD WR HOLD 0 Figure 16 31 Indirect i80 System Interface Write Cycle Timing SAMSUNG ELECTRONICS 16 45 II 4412 UM 16 Display Controller Table 16 4 describes the timing reference code KY Definition Table 16 4 Timing Reference Code KY Definition 16 BPP 65 vore RA vwe me ma ma n om von am ww wm mm vo m E EE r on EE EE ES AA SE pu oF wg em NEC vu og e Me vog m GN EE pe NECEM 3 5 VD 5 VD 4 VD 3 VD 2 VD 1 VD 0 SAMSUNG ELECTRONICS 16 46 IT 4412 UM 16 Display Controller 16 4 1 0 Description Table 16 5 describes the 1 0 Table 16 5 WO Signals of Display Controller LCD HSYNC 22 Synchronization XvHSYNC sYs VD 7 0 In Out Pata to from Display Controller 17 to xyvD_0 Muxed from to Display Module SYS we Address Output SYS RS f SYS ADD 0 SYS ADD 0 is Register State KVVDEN select VSYNC 101 Ma signal for Vsync Interface XvVSYNC_LDI LCD FRM Frame Se men Signal for XpwmTout 0
425. enable bit interrupt PPMU 3D 12 combiner serves the interrupt request o PPMU TV MO 11 Write 0 Does not change the current setting 0 1 Sets the interrupt enable bit to 1 PPMU_FILE D_M0 10 RW Read The current interrupt enable bit PPMU_ISP_MX 0 Masks PPMU_CAMIF_MO Sets the corresponding interrupt enable bit to 1 o D RIGHT MO If you set the interrupt enable bit interrupt 5 combiner serves the interrupt request PPMU D LEFT MO RW Write 0 Does not change the current setting PPMU ACPO MO 1 Sets the interrupt enable bit to 1 Read The current interrupt enable bit 05000 PPMU KIU S1 2 RW XIU R 51 e RW DS PPMU_XIU_R 1 Enables NE SAMSUNG ELECTRONICS 7 18 4412 UM 7 Interrupt Combiner 7 6 2 10 IECR2 Base Address 0x1044 0000 e Address Base Address 0x0024 Reset Value 0x0000_0000 ASVD 8128 reserved mo gt LCDO 3 27 Clears the corresponding interrupt enable bit to 0 If you clear the interrupt enable bit interrupt LCDO 2 2 RW 26 RW combiner will mask the interrupt LCDO 1 25 Write 0 Does not change the current setting 1 Clears the interrupt enable bit to 0 LCD0 0 24 RW Read interrupt enable bit 1 Enables DMC1_PPC_PEREV_M 23 DMC1 PPC PEREV 22 Clears the corresponding interrupt enable bit to e 0 If you clear
426. ent Unit 5 10 1 90 CLKDIV2_STAT e Base Address 0 1003 0000 e Address Base Address 0xC680 Reset Value 0 0000 0000 RSV eee PCLK Divider Status in TV_BLK GPS_BLK 24 0 Stable 1 Status that the divider is changing SE den fm PCLK Divider Status in TV_BLK TV_BLK 20 0 Stable 1 Status that the divider is changing fm PCLK Divider Status in LCD for 160 MHz domain LCD 12 Stable 1 Status that the divider is changing S ms mew fm PCLK Divider Status in CAM BLK CAM BLK 4 0 Stable 1 Status that the divider is changing S reens fo PCLK Divider Status in FSYS BLK FSYS BLK 0 Stable 1 Status that the divider is changing SAMSUNG ELECTRONICS 5 106 ex 4412 UM 5 Clock Management Unit 5 10 1 91 CLK_GATE_BUS_FSYS1 Address 0 1003_ 744 Reset Value OKFFFF FFFF 6123 Ont Gating APB clock for PCLK_ASYNCAXIS 22 ASYNCAXIS_GPS_FSYSD GPS FSYSD 0 Mask 1 Pass Gating APB clock for AKI FSYSS PCLK AKI FSYSS 21 0 1 Pass 85 0 CIE Gating APB clock for PPMUFILE PCLK PPMUFILE 17 RW 0 Mask 1 Pass Gating APB clock for FSYS ADC PCLK ADC 16 RW 0 Mask 0 1 Pass Gating APB clock for AXI FSYSD PCLK AXI FSYSD 20 0 Mask 0x1 1 Pass x1 SAMSUNG ELECTRONICS 5 107 IT 4412 UM 5 Clock Management Unit 5 10 1 92 CLK GATE IP CAM e Base Address 0x1003
427. ent the PWM feature TCNTBn determines PWM frequency A As illustrated in Figure 11 6 TCMPBn determines a PWM value For a higher PWM value decrease the value For a lower PWM value increase the value you enable the output inverter the increment decrement can be disabled Due to the double buffering feature you should write a counter value for next PWM cycle into the TCMPBn register SAMSUNG ELECTRONICS 11 10 ex 4412 UM 11 Pulse Width Modulation Timer 11 3 7 During Current ISR Interrupt Service Routine Output Level Control Figure 11 7 illustrates the inverter Inverter off Inverter on Initial State 1 Period 1 1 Period 2 stop Figure 11 7 Inverter On Off Steps to maintain TOUT as high or low when inverter is turned Off 1 Turn Off the auto reload bit Then TOUTn goes to high level and it stops the timer after TCNTn reaches to 0 This method is recommended 2 Stop the timer by clearing the timer start stop bit to 0 If TCNTn lt the output level is high If TCNTn gt TCMPn the output level is low 3 You invert TOUTn signal by setting 1 to Inverter On Off bit of TCON register The inverter removes the additional circuit to adjust the output level SAMSUNG ELECTRONICS 11 11 IT 4412 UM 11 Pulse Width Modulation Timer 11 3 8 Dead Zone Generator Dead Zone Generator feature inser
428. eo line OFFSIZE_F should have value that is multiple of 4byte size or 0 Specifies virtual screen page width number of byte This value defines the width of view port in the frame PAGEWIDTH_F 12 0 RW PAGEWIDTH should have bigger value than the burst size and you should align the size word boundary NOTE You should align the sum of PAGEWIDTH F and OFFSIZE F double word 8 byte boundary SAMSUNG ELECTRONICS 16 94 IT 4412 UM 16 Display Controller 16 5 3 36 VIDINTCONO e Base Address 0x11C0_0000 e Address Base Address 0x0130 Reset Value 0x0000_0000 RSVD ove FIFOINTERVAL 25 20 RW Controls interval of the FIFO interrupt SYSMAINCON SYSSUBCON FRAMESELO 16 15 Sends complete interrupt enable bit to Main LCD 0 Disables Interrupt 1 Enables Interrupt NOTE This bit is valid if both INTEN and I80IFDONE are high Sends complete interrupt enable bit to Sub LCD 0 Disables Interrupt 1 Enables Interrupt NOTE This bit is valid I if both and I80IFDONE are high Enables 180 Interface Interrupt only for 180 Interface mode 0 Disables Interrupt1 Enables Interrupt NOTE This bit is valid if INTEN is high 2 Specifies Video Interrupt 0 at start of 00 BACK Porch 01 VSYNC 10 11 Specifies Video Frame Interrupt 1 at start of 00 None 01 BACK Porch gt
429. er 0x1 Enables filter FLTWIDTH15 0 6 0 Filtering width of EXT_INT15 0 SAMSUNG ELECTRONICS 4 95 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 113 EXT_INT15_FLTCON1 e Base Address 0x1140_0000 e Address Base Address 0x0874 Reset Value 0x0000_0000 Filter Enable for EXT_INT15 7 FLTEN15 7 31 RW 0 0 Disables filter 0x1 Enables filter FLTWIDTH15 7 30 24 Filtering width of EXT_INT15 7 Filter Enable for EXT_INT15 6 FLTEN15 6 23 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH15 6 22 16 Filtering width of EXT_INT15 6 Filter Enable for EXT_INT15 5 FLTEN15 5 15 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH15 5 14 8 Filtering width of EXT_INT15 5 Filter Enable for EXT_INT15 4 FLTEN15 4 7 RW 0 0 Disables filter 0x1 Enables filter FLTWIDTH15 4 6 0 RW Filtering width of EXT_INT15 4 SAMSUNG ELECTRONICS 4 96 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 114 EXT_INT16_FLTCONO Base Address 0x1140_0000 e Address Base Address 0x0878 Reset Value 0 0000 0000 Filter Enable for EXT INT16 3 FLTEN16 3 31 RW 0 0 Disables filter 0x1 Enables filter FLTWIDTH16 3 30 24 Filtering width of EXT INT16 3 Filter Enable for EXT INT16 2 FLTEN16 2 23 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH16 2 22 16 Filtering width of EXT_INT16 2 Filte
430. er level of Tx FIFO is set to 00 Empty When UART uses FIFO check for Tx FIFO Count bits and Tx FIFO Full bit in UFSTAT instead of this bit It automatically sets this bit to 1 when receive buffer contains valid data which is received over the RXDn port 0 Buffer is empty 1 Buffer has a received data In Non FIFO mode it requests interrupt or DMA When UART uses the FIFO check for Rx FIFO Count bits and Rx FIFO Full bit in UFSTAT instead of this bit t 13 22 ex 4412 UM 13 Universal Asynchronous Receiver and Transmitter 13 6 1 6 UERSTATn 0 to 4 e Base Address 0x1380 0000 Base Address 0x1381_0000 Base Address 0x1382 0000 e Base Address 0x1383 0000 Base Address 0x1384 0000 e Address Base Address 0x0014 Reset Value 0x0000_0000 Rev Bra It automatically sets this bit to 1 to indicate that a break signal Break has been received Detect Frame Error 0 No break signal is received 1 Break signal is received Interrupt is requested It automatically sets this bit to 1 when a frame error occurs during the receive operation 0 frame error occurs during the receive operation 1 Frame error occurs Interrupt is requested during the receive operation It automatically sets this bit to 1 when a error occurs during the receive operation 0 No parity error occurs during receive the receive operation 1 Parity error occurs Interrup
431. er 0x0000 GPK1PUDPDN 0x0074 i GPK1 power down mode pull up pull down 0x0000 GPK2CON 0x0080 Port group GPK2 configuration register 0x0000 0000 GPK2DAT 0x0084 Port group GPK2 data register 0x00 GPK2PUD 0x0088 Port group GPK2 pull up pull down register 0x1555 GPK2DRV 0 008 Port group GPK2 drive strength control register 0x00_0000 GPK2CONPDN 0x0090 Port group GPK2 power down mode configuration register 0x0000 GPK3DAT 0x00A4 Port group GPK3 data register 0x00 GPK3PUD 0x00A8 Port group GPK3 pull up pull down register 0x1555 GPK2PUDPDN 0x0094 4 2 power down mode pull up pull down 0x0000 GPK3CON Ox00A0 Port group GPK3 configuration register 0x0000_0000 GPK3DRV 0x00AC Port group GPK3 drive strength control register 0x00 0000 GPK3CONPDN 0x00BO Port group GPK3 power down mode configuration register 0 0000 0x00B4 id power down mode pull up pull down 050000 GPLOCON 0x00CO Port group GPLO configuration register 0 0000 0000 Por group contiguraton register GPLOPUDPDN 0 0004 eis GPLO power down mode pull up pull down 0 0000 0 00 Port group GPL1 configuration register 0x0000 0000 GPL1DAT 0 00 4 Port group GPL1 data register 0x00 SAMSUNG ELECTRONICS 4 10 4412 UM 4 General Purpose Input Output GPIO Control GPL1PUD OxOOE8 Port group GPL1 pull up pull down register 0x0005 GPL1DRV OxOOEC Port group GPL1 drive st
432. er Ratio SCLK FIMDO MOUTFIMDO FIMDO RATIO 1 SAMSUNG ELECTRONICS 5 86 4412 UM 5 Clock Management Unit 5 10 1 57 CLK DIV ISP e Base Address 0x1003 0000 e Address Base Address 0xC538 Reset Value 0 0000 0000 DIVUART_ISP Clock Divider Ratio i 31 28 SCLK_UART_ISP DOUTUART ISP UART ISP RATIO 1 DIVSPI1 ISP PRE Clock Divider Ratio 27 20 SCLK_SPI1_ISP DOUTSPI1_ISP SPI1 ISP RATIO 1 SPI ISP PRE RATIO DIVSPI1 ISP Clock Divider Ratio SPI ISP RATIO 19 16 DOUTSPH ISP MOUTSPI1 ISP SPI ISP RATIO 1 SPIO ISP PRE RATIO DOUTSPIO ISP SPIO ISP PRE RATIO 1 DIVSPIO ISP Clock Divider Ratio SPIO ISP RATIO 7 4 DOUTSPIO ISP MOUTSPIO ISP SPIO ISP RATIO 1 DIVPWM ISP Clock Divider Ratio PWM ISP RATIO 3 0 SCLK ISP MOUTPWM ISP PWM ISP RATIO 1 5 10 1 58 CLK DIV MAUDIO 15 8 SCLK SPIO ISP DIVSPIO ISP PRE Clock Divider Ratio 0x0 e Base Address 0x1003 0000 e Address Base Address 0xC53C Reset Value 0x0000 0000 RSVD 31 12 Reserved 0 0 DIVPCMO Clock Divider Ratio POMO LER SCLK PCMO SCLK AUDIOO PCMO RATIO 1 0x0 DIVAUDIOO Clock Divider Ratio AUDIOO RATIO 3 0 RW SCLK AUDIOO MOUTAUDIOO AUDIOO RATIO 1 SAMSUNG ELECTRONICS 5 87 ex 4412 UM 5 Clock Management Unit 5 10 1 59 CLK DIV 5 50 e Base Address 0x1003 0000 e Address Base Address 0xC540 R
433. er clock Programmable Clock Select Logic for individual PWM Channels Four Independent PWM Channels with Programmable Duty Control and Polarity Static Configuration lt stops PWM Dynamic Configuration PWM 1 running Auto Reload and One Shot Pulse Mode Dead Zone Generator on two PWM Outputs Level Interrupt Generation The PWM has two operation modes They are Auto Reload Mode In this mode continuous PWM pulses are generated based on programmed duty cycle and polarity One Shot Pulse Mode In this mode only one PWM pulse is generated based on programmed duty cycle and polarity To control the functionality of PWM 18 special function registers are provided The PWM is an AMBA slave module which has programmable outputs and a clock input and the PWM connects to the Advanced Peripheral Bus These 18 special function registers within PWM are accessed via transactions SAMSUNG ELECTRONICS 11 4 IT 4412 UM 11 Pulse Width Modulation Timer 11 3 PWM Operation PWM timer of Exynos 4412 can operate as a general timer and a pulse generator with TOUT signal 11 3 1 Prescaler and Divider An 8 bit prescaler and 3 bit divider generates these output frequencies Table 11 1 describes the minimum and maximum resolution based on prescaler and clock divider values Table 11 1 Minimum and Maximum Resolution Based on Prescaler and Clock Divider Values 4 bit Divider Settinas Minimum Resolution Maximum Resolution Maximu
434. er is designed to operate at maximum 5 MHz clock so the prescaler value should be set such that the resulting clock does not exceed 5 MHz ma Reseed 1975 Standby mode select 0 Normal operation mode STANDBY 2 RW 1 Standby mode NOTE In standby mode prescaler should be disabled to reduce more leakage power consumption A D conversion start by read 1 RW 0 Disables start by read operation 1 Enables start by read operation A D conversion starts by enable i hi lue i lid ENABLE ST If HERD START is enabled this value is not valid ART 0 No operation 1 A D conversion starts and this bit is automatically cleared after the start up SAMSUNG ELECTRONICS 18 7 ex 4412 UM 18 ADC 18 6 1 2 ADCDLY Base Address 0x126C_0000 e Address Base Address 0x0008 Reset Value 0x0000_00FF Reference clock source for delay FILCLKsrc 16 RW 0 X tal clock 1 clock In case of ADC conversion mode Normal Separate Auto conversion ADC conversion is delayed by counting this value Counting clock is PCLK ADC conversion delay value In case of waiting for Interrupt mode DELAY 15 0 RW When stylus down occurs in waiting for interrupt mode it generates interrupt signal INT PENn at interval of several ms for Auto X Y position conversion If this interrupt occurs in STOP mode it generates Wake Up signal having interval several ms for Exiting STOP MODE NO
435. erefore you must reset ECC value by writing the InitSECC NFCONT 4 bit as 1 and clear the SpareECCLock NFCONT 6 bit to 0 Unlock before reading data SpareECCLock NFCONT 6 bit controls whether ECC code is generated or not Whenever data is read the 4 bit ECC module generates ECC parity code internally After you complete reading 24 byte excluding spare area data you should read parity codes 4 bit ECC module needs parity codes to detect whether error bits have occurred or not Therefore ensure to read ECC parity codes immediately after reading 24 byte After ECC parity code 1 read 4 bit ECC engine starts searching for error internally to verify whether ECC decoding is completed or not When ECCDecDone is set 1 NFECCERRO indicates whether error bit exists or not If any error exists you can fix it by referring to NFECCERRO 1 and NFMLCBITPT registers SAMSUNG ELECTRONICS 10 9 ex 4412 UM 10 NAND Flash Controller 10 4 9 8 12 16 bit ECC Programming Guide ENCODING 1 To use 8 12 16 bit in software mode set the MsgLength NFECCCONF 25 16 to 511 512 byte message length and the ECCType to 001 100 101 enable 8 12 16 bit ECC respectively ECC module generates ECC code for 512 byte write data Therefore reset ECC value by writing the NFECCCONT 2 bit as 1 before writing data and clear the MainECCLock NFCONTT 7 bit to 0 unlock befor
436. ers data from its transmit FIFO register to transmit shifter and the number of data left in transmit FIFO is less than or equal to the trigger level of Tx FIFO Tx interrupt is generated This occurs when Transmit mode in control register is selected as Interrupt request or polling mode In non FIFO mode transferring the data from transmit holding register to transmit shifter causes Tx interrupt in the interrupt request and polling mode Remember that the Tx interrupt is always requested when the number of data in the transmit FIFO is smaller than the trigger level This means that an interrupt is requested as soon as you enable the Tx interrupt unless you fill the Tx buffer Fill the Tx buffer first and then enable the Tx interrupt The interrupt controllers of Exynos 4412 are of the level triggered type Set the interrupt type as Level when you program the UART control registers When you select Receive and Transmit modes in control register as DMA request mode DMAn request occurs instead of Rx or Tx interrupt in the above situation SAMSUNG ELECTRONICS 13 5 ex 4412 UM 13 Universal Asynchronous Receiver and Transmitter Table 13 1 describes the interrupts in connection with FIFO Table 13 1 Interrupts in Connection with FIFO FIFO Mode Non FIFO Mode Generated when Rx FIFO count is greater than or equal to the trigger level of received FIFO Generated when the number of data in FIFO does Generated by receive holding
437. ers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved Sets signaling method of EXT_INT14 0 0 0 Low level 0x1 High level EXT INT14 CON O 2 0 RW 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 74 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 90 EXT INT15CON e Base Address 0x1140 0000 e Address Base Address 0x0738 Reset Value 0x0000 0000 RSV Sets signaling method of EXT_INT15 7 0 0 Low level 0x1 High level EXT_INT15_CON 7 30 28 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0x7 Reserved 85 2 99 Sets signaling method of EXT_INT15 6 0 0 Low level 0x1 High level EXT_INT15_CON 6 26 24 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0x7 Reserved SVO gp Rem Jo Sets signaling method of EXT INT15 5 0 0 Low level 0 1 High level EXT INT15 CON 5 22 20 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved 85 0 Sets signaling method of EXT_INT15 4 0 0 Low level 0x1 High level EXT_INT15_CON 4 18 16 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0x7 Reserved
438. es NOTE The other PLL control inputs should be set as RESV1 0 RESVO 0 DCC_ENB 1 EXTAFC 0 LOCK CON IN 3 LOCK CON OUT 0 LOCK CON DLY 8 AFC 0 SAMSUNG ELECTRONICS 5 143 ex 4412 UM 5 Clock Management Unit 5 10 1 134 CLK SRC CPU e Base Address 0x1004 0000 e Address Base Address 0x4200 Reset Value 0x0000_0000 RSV Reseed _ Controls MUXMPLL MUX_MPLL_USER_SEL_C 24 RW 0 FINPLL 1 FOUTMPLL SE ne mw Controls MUXHPM MUX HPM SEL 20 RW 0 MOUTAPLL 1 SCLKMPLL SE 99 Controls MUXCORE MUX CORE SEL 16 RW 0 MOUTAPLL 1 SCLKMPLL SE vs A Controls MUXAPLL SEL RW 0 FINPLL 1 MOUTAPLLFOUT SAMSUNG ELECTRONICS 5 144 IT 4412 UM 5 Clock Management Unit 5 10 1 135 CLK_MUX_STAT_CPU e Address 0x1004 4400 Reset Value 0 0111 0001 RSV een reseve S Selection signal status of MUXMPLL 001 FINMPLL MPLL_USER_SEL_C 26 24 010 FOUTMPLL 1xx Status that the mux is changing Selection signal status of MUXHPM 001 MOUTAPLL ecce 010 SCLKMPLL 1 Status that the is changing wo ea wo 00 7 mw i3 esa Selection signal status of MUXAPLL 001 FINPLL APLL SEL 2 S 2 0 010 MOUTAPLLFOUT 1 Status that the mux is changing Selection signal status of MUXCORE CORE_SEL 18 16 s 2 0 1 1 St
439. escaler value and frequency division factor Valid prescaler values range from 0 to 2 1 You can select the frequency division factor as 16 32 64 or 128 Use this equation to calculate the WDT clock frequency and the duration of each timer clock cycle t watchdog 1 PCLK Prescaler value 1 Division_factor SAMSUNG ELECTRONICS 12 2 ex 4412 UM 12 Watchdog Timer 12 3 2 WTDAT and WTCNT After you enable the WDT you cannot reload the value of the Watchdog Timer Data WTDAT register automatically into the Watchdog Timer Counter WTCNT register Therefore you must write an initial value to the register before WDT starts 12 3 3 WDT Start To start WDT set WTCON 0 WTCON 5 as 1 12 3 4 Consideration of Debugging Environment WDT should not operate if the Exynos 4412 is in debug mode that uses Embedded In Circuit Debugger ICE WDT determines whether CPU core is currently in the debug mode from the CPU core signal signal After CPU core asserts the DBGACK signal it does not activate the reset output of WDT as WDT expires SAMSUNG ELECTRONICS 12 3 ex 4412 UM 12 Watchdog Timer 12 4 Register Description 12 4 1 Register Map Summary e Base Address 0x1006 0000 WTCON 0 0000 Watchdog timer control register 0x0000 8021 WTDAT 0x0004 Watchdog timer data register 0x0000 8000 WTCNT 0x0008 Watchdog timer count register 0x0000_8000 WTCLRINT 0x000C Watchdog t
440. escription of SROMC we SAMSUNG ELECTRONICS 9 4 27 4412 UM 9 SROM Controller 9 6 Register Description 9 6 1 Register Map Summary Base Address 0x1257 0000 SROM BW 0x0000 Specifies the SROM bus width and wait control 0x0000 0009 SROM BCO 0x0004 Specifies the SROM bank 0 control register 0 000 0000 SROM BC1 0x0008 Specifies the SROM bank 1 control register 0 000 0000 SROM BC2 0x000C Specifies the SROM bank 2 control register 0x000F 0000 SROM_BC3 0x0010 Specifies the SROM bank 3 control register 0 000 0000 SAMSUNG ELECTRONICS 9 5 IT 4412 UM 9 SROM Controller 9 6 1 1 SROM_BW e Base Address 0x1257 0000 e Address Base Address 0x0000 Reset Value 0x0000 0009 Sw AI nWBE nBE for UB LB control for memory bank 3 0 Does not use UB LB XrnWBE 1 0 is dedicated ByteEnabl nWBE 1 0 1 Uses UB LB XrnWBE 1 0 is dedicated nBE 1 0 Wait enable control for memory bank 3 WaitEnable3 0 Disables WAIT 1 Enables WAIT Select SROM ADDR base for memory bank 3 0 is half word base address SROM ADDR 22 0 HADDR 23 1 AddrMode3 1 SROM ADDR is byte base address SROM ADDR 22 0 lt HADDR 22 0 NOTE When DataWidth3 is 0 SROM ADDR is byte base address It ignores this bit Data bus width control for memory bank 3 DataWidth3 0 8 bit 1 16 bit nWBE nBE for UB LB control for memory bank 2 0 Does not use UB LB XrnWBE 1 0 is
441. eset 0 Disables NOTE When UART does not reach the trigger level of FIFO it does not receive data during the specified timeout interval in DMA receive mode with FIFO It generates the Rx interrupt receive time out Ensure to verify the FIFO status and read out the rest SAMSUNG ELECTRONICS 13 18 II 4412 UM Base Address Base Address Base Address 13 6 1 4 UMCONn 0 1 2 4 0x1380 0000 0x1381 0000 0x1382 0000 13 Universal Asynchronous Receiver and Transmitter Base Address 0x1383 0000 Base Address 0x1384 0000 e Address Base Address 0x000C Reset Value 0x0000 0000 mv po Determines the trigger level of Rx FIFO to control nRTS signal When it enables AFC bit and Rx FIFO have bytes that are greater than or equal to the trigger level it deactivates nRTS signal Channel 0 000 255 bytes 001 224 bytes 010 2 192 bytes 011 2 160 bytes 100 128 bytes 101 96 bytes 110 64 bytes 111 32 bytes Channel 1 4 RTS trigger 000 63 bytes Level 001 56 bytes 010 48 bytes 011 40 bytes 100 32 bytes 101 24 bytes 110 16 bytes 111 2 8 bytes Channel 2 000 15 bytes 001 14 bytes 010 12 bytes 011 2 10 bytes 100 8 bytes 101 6 bytes 110 4 bytes 111 2 bytes Auto Flow 0 Disables Control 1 Enables 0 Disables 1 Enables Reserved These bits must be 0 58 SAMSUNG ELECTRONICS 13 19 II en
442. eset Value 0x00B0_0000 m rea 09 DIVMIPIHSI Clock Divider Ratio MIPIHSI RATIO 23 20 Mr MIPIHSI MOUTMIPIHSI MIPIHSI RATIO mm mme 5 10 1 60 CLK DIV FSYS1 Base Address 0 1003 0000 e Address Base Address 0xC544 Reset Value 0x0000 0000 DIVMMC1 PRE Clock Divider Ratio MMC1 PRE RATIO 31 24 RW SCLK MMC1 DOUTMMC1 MMC1 PRE RATIO 1 MMC1 RATIO 16 DIVMMC1 Clock Divider Ratio DOUTMMC1 MOUTMMC1 MMC1_RATIO 1 MMCO RATIO 3 0 Reserved 00 DIVMMCO Clock Divider Ratio DOUTMMCO MOUTMMCO MMCO_RATIO 1 DIVMMCO_PRE Clock Divider Ratio MMCO_PRE_RATIO 15 8 RW SCLK_MMCO DOUTMMCO MMCO_PRE_RATIO 1 SAMSUNG ELECTRONICS 5 88 ex 4412 UM 5 Clock Management Unit 5 10 1 61 CLK DIV FSYS2 e Base Address 0x1003 0000 e Address Base Address 0xC548 Reset Value 0 0000 0000 DIVMMC3_PRE Clock Divider Ratio W SCLK_MMC3 DOUTMMC3 MMC3 PRE RATIO 0 0 1 RSVD 23 20 Reserved DIVMMG3 Clock Divider Ratio MMS RATIG 12 16 DOUTMMC3 MOUTMMC3 MMC3 RATIO 1 DIVMMC2 PRE Clock Divider Ratio R MMC3 PRE RATIO 31 24 R 0 0 MMC2_PRE_RATIO 15 8 W SCLK_MMC2 DOUTMMC2 MMC2_PRE_RATIO 0x0 MMC2_RATIO 3 0 1 DIVMMC2 Clock Divider Ratio 0 0 DOUTMMC2 MOUTMMC2 MMC2_RATIO 1 5 10 1 62 CLK_DIV_FSYS3 e Base Address 0x1003_0000 e Address Base Address 0xC54C Reset V
443. ess 0x0828 Reset Value 0 0000 0000 Filter Enable for EXT INT6 3 FLTEN6 3 31 RW 0 0 Disables filter 0 1 Enables filter FLTWIDTHe 3 30 24 Filtering width of EXT INT6 3 Filter Enable for EXT INT6 2 FLTEN6 2 23 RW 0x0 Disables filter 0 1 Enables filter FLTWIDTH6 2 22 16 Filtering width of EXT_INT6 2 Filter Enable for EXT INT6 1 FLTENe 1 15 RW 0x0 Disables filter 0 1 Enables filter FLTWIDTH6 1 14 8 Filtering width of EXT_INT6 1 Filter Enable for EXT INT6 0 FLTEN6 0 7 RW 0x0 Disables filter 0 1 Enables filter FLTWiDTHe o 16 0 RW Filtering width of EXT_INT6 0 4 3 2 105 EXT_INT6_FLTCON1 Base Address 0x1140 0000 e Address Base Address 0x082C Reset Value 0x0000_0000 SAMSUNG ELECTRONICS 4 89 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 106 EXT_INT7_FLTCONO Base Address 0x1140_0000 e Address Base Address 0x0830 Reset Value 0 0000 0000 Filter Enable for EXT_INT7 3 FLTEN7 3 31 RW 0 0 Disables filter 0 1 Enables filter FLTWIDTH7 3 30 24 Filtering width of EXT INT7 3 Filter Enable for EXT INT7 2 FLTEN7 2 23 RW 0x0 Disables filter 0 1 Enables filter FLTWIDTH7 2 22 16 Filtering width of EXT INT7 2 Filter Enable for EXT INT7 1 FLTEN7 1 15 RW 0x0 Disables filter 0 1 Enables filter FLTWIDTH7 1 14 8 Filtering width of EXT INT7 1 Filter Enable for
444. et Fow MHz P S K For MHa __ EA E 2 1806 3 90 2 16 1086 gt 16 90 2 2072 1806336 B N NS N a efefefo o e 200 400 two 2 o 2 Ee 416 tt B i 416 1 K value description Positive value Negative value Positive values is that you should write to EPLLCON VPLLCON register Negative value is that you can calculate PLL output freguency with it 2 Although there is an eguation for choosing PMS values we strongly recommend only the values in the above table If you have to use other values please contact us 3 You should set K to 0 in EVTO This restriction will be fixed in EVT1 SAMSUNG ELECTRONICS 5 8 IT 4412 UM 5 Clock Management Unit 5 4 3 Recommended PLL PMS Value for VPLL Table 5 4 describes the recommended PLL PMS value for VPLL Table 5 4 VPLL PMS Value runa P s men wm ssco zx NOTE 1 Although there is an equation for choosing PMS values we strongly recommend only the values in the above table If you have to use other values please contact us 2 K value description Positive value Negative value Positive values is that you should write to EPLLCON VPLLCON register Negative value is that you can calculate PLL output frequency with it SAMSUNG ELECTRONICS 5 9 IT
445. et Value FFFF 31 0 Configuration for DCG Index Map 31 0 OxFFFFFFFF 5 10 1 119 DCGIDX MAP1 Base Address 0 1 DCGIDX_MAP1 004_0000 Address Base Address 0x1004 Reset Value FFFF 31 0 IEC Configuration for DCG Index Map 63 32 OXFFFFFFFF 5 10 1 120 DCGIDX_MAP2 Base Address 0x1 DCGIDX_MAP2 004_0000 Address Base Address 0x1008 Reset Value FFFF 31 0 RW Configuration for DCG Index Map 95 64 OxFFFFFFFF 5 10 1 121 DCGPERF MAPO Base Address 0 1 DCGPERF_MAPO 004_0000 Address Base Address 0x1020 Reset Value OxFFFF_FFFF 31 0 Performance 31 0 OXFFFFFFFF 5 10 1 122 DCGPERF MAP1 Base Address 0 1 DCGPERF_MAP1 SAMSUNG ELECTRON 004_0000 Address Base Address 0x1024 Reset Value OxFFFF_FFFF 31 0 63 32 ICS 5 136 4412 UM 5 Clock Management Unit 5 10 1 123 DVCIDK MAP e Base Address 0x1004 0000 e Address Base Address 0x1040 Reset Value OxOOFF_FFFF DCGPERF_MAPO 23 0 IEC Configuration for DVC Index Map 23 0 OxFFFFFF 5 10 1 124 FREQ CPU e Base Address 0x1004 0000 e Address Base Address 0x1060 Reset Value 0x0000_0000 FREQ_CPU 23 0 Maximum Frequency of CPU in KHz 5 101125 FREQ Base Address 0x1004 0000 e Address Base Address 0x1064 Reset Value 0x0000 0000
446. evel 0x1 High level EXT INT40 CON 0 2 0 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0 5 to 0 7 Reserved SAMSUNG ELECTRONICS 4 265 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 211 EXT INT41CON e Base Address 0x1100 0000 e Address Base Address 4 Reset Value 0x0000 0000 RSV eee Sets signaling method of EXT_INT41 7 0 0 Low level 0x1 High level EXT INT41 CON 7 30 28 RW 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0 5 to 0x7 Reserved 85 2 Ep eena ooo Sets signaling method of EXT_INT41 6 0 0 Low level 0x1 High level EXT_INT41_CON 6 26 24 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0 7 Reserved SVO Eq mesen pm Sets signaling method of EXT INT41 5 0 0 Low level 0 1 High level EXT INT41 CON 5 22 20 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0 5 to 0x7 Reserved 85 0 pf 99 Sets signaling method of EXT INT41 4 0x0 Low level 0 1 High level EXT INT41 CON 4 18 16 RW 0x2 Falling edge triggered 0x3 Rising edge triggered 0 4 Both edge triggered 0x5 to 0x7 Reserved 85 9 Sets signaling method of EXT_INT41 3 0 0 Low level 0x1 High level EXT INT41 CON 3 14 12 RW 0 2 Tr
447. ex 4412 UM 13 Universal Asynchronous Receiver and Transmitter 13 3 7 Interrupt DMA Reguest Generation Each UART in Exynos 4412 consists of seven status Tx Rx Error signals namely e Overrun error e Parity error e Frame error e Break condition e Receive buffer data ready e Transmit buffer empty e Transmit shifter empty The corresponding UART status register UTRSTATn UERSTATn indicates these conditions The overrun error parity error frame error and break condition specify the receive error status When you set receive error status interrupt enable bit to 1 in the control register UCONn the receive error status generates receive error status interrupt When a receive error status interrupt request is detected you can identify the source of interrupt by reading the value of UERSTATn When you set Receive mode in control register UCONn as interrupt request or polling mode Rx interrupt is generated in this case When you set Receive mode in control register UCONn as interrupt request or polling mode Rx interrupt is generated in this case When the receiver transfers data of the receive shifter to the receive FIFO register in FIFO mode and the number of received data is greater than or equal to the trigger level of Rx FIFO In non FIFO mode transferring the data of receive shifter to receive holding register causes Rx interrupt in the interrupt request and polling modes When the transmitter transf
448. f 49 51 APLL also generates DMC_BLK LEFTBUS_BLK RIGHTBUS_BLK and CMU_TOP clocks as supplement of MPLL MPLL mainly drives the DMC_BLK LEFTBUS_BLK RIGHTBUS_BLK and CMU_TOP clocks It generates frequencies up to 1 GHz with a duty ratio of 49 51 MPLL also generates CPU BLK clocks when it blocks APLL for locking during the Dynamic Voltage Frequency Scaling DVFS EPLL mainly generates an audio clock VPLL mainly generates video system operating clock of 54 MHz G3D clock or 440 MHz clock at 1 1 SAMSUNG ELECTRONICS 5 6 ex 4412 UM 5 Clock Management Unit 5 4 1 Recommended PLL PMS Value for APLL and MPLL Table 5 2 describes the recommended PLL PMS value for APLL and MPLL Table 5 2 APLL and MPLL PMS Value 2 ww w 300 200 300 s 200 ws 3 o9 w 3 o w L 3 s w s m x s es o m 2 o sm ao s 3 ao v o NOTE Although there is an equation for choosing PMS values strongly recommend only the values the above table If you have to use other values please contact us Co a ji 700 800 SAMSUNG ELECTRONICS 5 7 27 4412 UM 5 Clock Management Unit 5 4 2 Recommended PLL PMS Value for EPLL Table 5 3 describes the recommended PLL PMS value for EPLL Table 5 3 EPLL PMS Value Fm MHz Targ
449. f EXT INT13 7 Filter Enable for EXT INT13 6 FLTEN13 6 23 RW 0 0 Disables filter 0x1 Enables filter FLTWIDTH13 6 22 16 Filtering width of EXT INT13 6 Filter Enable for EXT INT13 5 FLTEN13 5 15 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH13 5 14 8 Filtering width of EXT INT13 5 Filter Enable for EXT INT13 4 FLTEN13 4 7 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH13 4 6 0 RW Filtering width of EXT_INT13 4 SAMSUNG ELECTRONICS 4 92 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 110 EXT_INT14_FLTCONO e Base Address 0x1140 0000 e Address Base Address 00868 Reset Value 0 0000 0000 Filter Enable for EXT_INT14 3 FLTEN14 3 31 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH14 3 30 24 Filtering width of EXT_INT14 3 Filter Enable for EXT_INT14 2 FLTEN14 2 23 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH14 2 22 16 Filtering width of EXT_INT14 2 Filter Enable for EXT INT14 1 FLTEN14 1 15 RW 0 0 Disables filter 0x1 Enables filter FLTWIDTH14 1 14 8 Filtering width of EXT INT14 1 Filter Enable for EXT INT14 0 FLTEN14 0 7 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH14 0 6201 Filtering width of EXT INT14 0 SAMSUNG ELECTRONICS 4 93 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 111 EXT_INT14_FLTCON1 Base Ad
450. face Specification RGB Interface Spec includes e Signals e LCD RGB Interface Timing e Parallel Output e Serial 8 bit Output e Output Configuration Structure 16 3 8 1 Signals Table 16 2 describes the signals Table 16 2 RGB Interface Signals of Display Controller Display Controller In Out Description GPIO Control GPFOCON GPFOCONN GPF0CON GPF0CON 2 GPF0CON 4 GPFOCONIS GPFOCON S GPFOCONT GPF ICON GPFICONN GPFICONE GPFICONG GPFICONS GPA CON GPFICONP GPF2CON GPF2CONN GPF2CON 2 GPF2CON 3 GPF2CON 4 GPF2CONS GPFZCONIS LCD HSYNC LCD VSYNC LCD VCLK LCD VDEN LCD VD 0 LCD VD 1 LCD VD 2 LCD VD 3 LCD VD 4 LCD VD 5 LCD VD 6 LCD VD 7 LCD VD 8 LCD VD 9 LCD VD 10 LCD VD 11 LCD VD 12 LCD VD 13 LCD VD 14 LCD VD 15 LCD VD 16 LCD VD 17 LCD VD 18 SAMSUNG ELECTRONICS 16 40 4412 UM 16 Display Controller SA Display Controller In Out Description LCD VD 19 RGB data output XvVD_19 GPF2CON 7 co RGB deta output GPF3CONO co voen RGB deta output con co voga RGB deta output co RGB deta output __ ___ While using RGB interface the LBLKx bit fields LCDBLKC_CFG 0x1001 0210 register should be set to RGB Interface out 2 b00 even though you use 051 Video Mode SAMSUNG ELECTRONIC
451. fies Window 1 Palette entry 1 address Undefined 0 0_2 yA 0x0 Specifies Window 1 Palette entry 255 address Undefined SAMSUNG ELECTRONICS 16 136 ex 4412 UM 16 Display Controller 16 5 6 3 Win2 Palette Ram Access Address not SFR Base Address 0x11C0_0000 e Address Base Address 0x2C00 0x0C00 Reset Value 0 0000 0000 e Address Base Address 0x2C04 0x0C04 Reset Value 0 0000 0000 e Address Base Address Ox2FFC OxOFFC Reset Value 0x0000 0000 oo 0x0_2C00 Specifies Window 2 Palette entry 0 address Undefined 0x0_2C04 Specifies Window 2 Palette entry 1 address Undefined 0x0_2FFC Specifies Window 2 Palette entry 255 address Undefined 16 5 6 4 Win3 Palette Ram Access Address not SFR e Base Address 0x11C0_0000 e Address Base Address 0x3000 Reset Value 0x0000_0000 e Address Base Address 0x3004 Reset Value 0x0000_0000 e Address Base Address 0x33FC Reset Value 0x0000 0000 0 0 0_3000 Specifies Window 3 Palette entry 0 address Undefined 0x0_3004 Specifies Window 3 Palette entry 1 address Undefined 0x0_33FC Specifies the Window 3 Palette entry 255 address Undefined 16 5 6 5 Win4 Palette Ram Access Address not SFR Base Address 0x11C0_0000 e Address Base Address 0x3400 Reset Value 0x0000_0000 e Address Base Address 0x3404 Reset 0x0000 0000 e Address Base Address 0x37FC Reset Value 0x0000 0000 0
452. g SE mew ATI Selection signal status of MUXACLK 400 MCUISP ACLK 400 MCUISP 10 8 001 SCLKMPLL _SEL 010 SCLKAPLL 1 Status that the 15 changing Selection signal status of MUKACLK 266 GPS ACLK 266 GPS 6 4 001 SCLKMPLL _SEL 010 SCLKAPLL 1 Status that the is changing SE esme fm SAMSUNG ELECTRONICS 5 81 ex 4412 UM 5 Clock Management Unit 5 10 1 48 CLK_MUX_STAT_MFC e Base Address 0x1003 0000 e Address Base Address 0xC428 Reset Value 0x0000 0111 RSV 9 Selection signal status of OO ao 1xx Status that the mux is changing Selection signal status of MUKMFC 1 1 SCLKEPLL MES 1 SEL 6 4 lo 1 Status that the is changing Selection signal status of MUKMFC 0 1 SCLKMPLL MFG 0 SEL 2 0 Sio 5111 1 Status that the is changing 5 10 1 49 CLK_MUX_STAT_G3D e Base Address 0x1003 0000 e Address Base Address 0xC42C Reset Value 0 0000_0111 RSV ou w Selection signal status of MUXG3D 001 MOUTG3D 0 G3D SEL 10 8 010 MOUTG3D 1 0 1 1 Status that the is changing Selection signal status of MUKG3D 1 1 SCLKEPLL G3D 1 SEL 6 4 ME x 0 1 1 Status that the is changing 0 1 CTI m ee 07 Selection signal status of MUXG3D_0 1 SCLKMPLL G3D 0 SEL 2 0 40 1 Status that the i
453. g edge 0 4 Triggers both edge 0 5 to 0 7 Reserved 85 2 99 Sets signaling method of EXT_INT14 6 0 0 Low level 0x1 High level EXT INT14 CON 6 26 24 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0x7 Reserved ASVO gp Jo Sets signaling method of EXT_INT14 5 0 0 Low level 0x1 High level EXT_INT14 CON 5 22 20 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0x5 to 0x7 Reserved SVO nome Jo Sets signaling method of EXT INT14 4 0 0 Low level 0 1 High level EXT INT14 CON 4 18 16 RW 0 2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved 85 9 mi Sets signaling method of EXT_INT14 3 0 0 Low level 0x1 High level EXT INT14 CON 3 14 12 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved mw on SAMSUNG ELECTRONICS 4 73 ex 4412 UM 4 General Purpose Input Output GPIO Control Sets signaling method of EXT_INT14 2 0 0 Low level 0x1 High level EXT_INT14_CON 2 10 8 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0x7 Reserved Sets signaling method of EXT INT14 1 0 0 Low level 0x1 High level EXT INT14 CON 1 6 4 RW 0x2 Trigg
454. g method of EXT_INT11 2 0 0 Low level 0x1 High level EXT_INT11_CON 2 10 8 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT11 1 0 0 Low level 0x1 High level EXT_INT11_CON 1 6 4 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT11 0 0 0 Low level 0x1 High level EXT INT11 CON O 2 0 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0 5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 211 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 130 EXT_INT12CON e Base Address 0x1100 0000 e Address Base Address 0x0734 Reset Value 0x0000 0000 RSV reen 9 Sets signaling method of EXT INT12 7 0 0 Low level 0x1 High level EXT INT12 CON 7 30 28 RW 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved 85 2 Mod Sets signaling method of EXT INT12 6 0 0 Low level 0 1 High level EXT INT12 CON 6 26 24 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0 5 to 0x7 Reserved ASVO gp Rese fm Sets signaling method of EXT INT12 5 0 0 Low level 0 1 High level EXT INT12 CON 5 22 20 RW 0x2 Triggers Falling edge 0
455. g width of EXT INT32 1 Filter Enable for EXT INT32 0 FLTEN3 0 7 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH3 o 1601 RW Filtering width of EXT INT32 0 SAMSUNG ELECTRONICS 4 327 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 45 EXT_INT32_FLTCON1 Base Address Ox106E 0000 e Address Base Address 0x0814 Reset Value 0x0000 0000 Filter Enable for EXT INT32 7 FLTENS 7 31 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH3 7 30 24 Filtering width of EXT INT32 7 Filter Enable for EXT INT32 6 FLTENS 6 23 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH3 6 22 16 Filtering width of EXT INT32 6 Filter Enable for EXT INT32 5 FLTENS 5 15 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH3 5 14 8 Filtering width of EXT INT32 5 Filter Enable for EXT INT32 4 FLTEN3 4 7 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH3 4 6 0 RW Filtering width of EXT_INT32 4 SAMSUNG ELECTRONICS 4 328 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 46 EXT_INT33_FLTCONO Base Address Ox106E 0000 e Address Base Address 0x0818 Reset Value 0x0000 0000 Filter Enable for EXT INT33 3 FLTEN4 3 31 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH4 3 30 24 Filtering width of EXT INT33 3 Filter Enable for EXT INT33 2 FLTENA 2 23 RW 0 0 Disables F
456. ge 0x4 Triggers both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT21 1 0 0 Low level 0x1 High level EXT INT21 CON 1 6 4 RW 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0x7 Reserved Sets signaling method of EXT INT21 0 0 0 Low level 0 1 High level EXT INT21 CON O 2 0 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 80 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 93 EXT_INT22CON Base Address 0x1140 0000 e Address Base Address 0x0744 Reset Value 0x0000 0000 RSV mp mw Sets signaling method of EXT INT22 4 0 0 Low level 0 1 High level EXT INT22 18 16 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved 85 9 nome AA Sets signaling method of EXT_INT22 3 0 0 Low level 0x1 High level EXT INT22 CON 3 14 12 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved 85 0 mw Sets signaling method of EXT_INT22 2 0 0 Low level 0x1 High level EXT_INT22_CON 2 10 8 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT22 1 0 0 Low level 0x1
457. gers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved 85 9 mp esea ov Sets signaling method of EXT_INT6 2 0x0 Low level 0x1 High level EXT INT6 CON 2 10 8 RW 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved Sets signaling method of EXT_INT6 1 0 0 Low level 0x1 High level EXT INT6 CON 1 6 4 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved Sets signaling method of EXT INT6 0 0 0 Low level 0x1 High level EXT INT6 CON 0 2 0 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 69 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 87 EXT_INT7CON Base Address 0x1140_0000 e Address Base Address 0x0718 Reset Value 0x0000_0000 RSVD na fo Sets signaling method of EXT_INT7 3 0x0 Low level 0x1 High level EKT INT7 CON 3 14 12 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0x5 to 0x7 Reserved 85 9 mp nome Sets signaling method of EXT_INT7 2 0 0 Low level 0x1 High level EXT INT7 CON 2 10 8 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved Sets signaling method of EXT_INT7 1
458. gers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved 85 9 mp 99 Sets signaling method of EXT INT13 3 0 0 Low level 0 1 High level EXT INT13 CON S 14 12 RW 0 2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved v m mew o SAMSUNG ELECTRONICS 4 71 ex 4412 UM 4 General Purpose Input Output GPIO Control Sets signaling method of EXT_INT13 2 0 0 Low level 0x1 High level EXT_INT13_CON 2 10 8 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT13 1 0 0 Low level 0x1 High level EXT INT13 CON 1 6 4 RW 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0x7 Reserved Sets signaling method of EXT INT13 0 0 0 Low level 0 1 High level EXT INT13 CON 0 2 0 RW 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 72 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 89 EXT_INT14CON Base Address 0x1140_0000 e Address Base Address 0x0734 Reset Value 0 0000 0000 RSV ns To Sets signaling method of EXT INT14 7 0 0 Low level 0 1 High level EXT INT14 CON 7 30 28 RW 0 2 Triggers falling edge 0 3 Triggers risin
459. hanges the logic level of TOUTn from low to high When TONTn reaches to 0 it generates interrupt request It automatically reloads TCNTn and TCMPn with TCNTBn TCMPBn as 79 20 59 and 59 It disables the auto reload and interrupt request to stop the timer in the ISR IFTCNTn and TCMPn have similar value then it changes the logic level of TOUTn from low to high Even if TCNTn reaches to 0 it does not generate interrupt request Because auto reload is disabled it does not reload TCNTn and stop the timer SAMSUNG ELECTRONICS 11 9 ex 4412 UM 11 Pulse Width Modulation Timer 11 3 5 Initialize Timer Setting Manual Up Data and Inverter You should define the starting value of the TCNTn because an auto reload operation of the timer occurs when the down counter reaches to 0 In this case the starting value should be loaded by setting 1 to the manual update bit of TCON register 1 Write the initial value into and 2 Setthe manual update bit and clear only manual update bit of the corresponding timer NOTE We recommend you to set the inverter On Off bit whether inverter is used or not 3 Set the start bit of the corresponding timer to start the timer 11 3 6 PWM Figure 11 6 illustrates the example of PWM Write TCMPBn 60 Write TCMPBn 40 Write TCMPBn 30 Write TCMPBn 50 Write TCMPBn 30 Write TEMPER next PWM Figure11 6 Example of PWM Use to implem
460. horizontal screen coordinate for right bottom pixel of OSD image Specifies vertical screen coordinate for right bottom pixel of OSD image OSD_RightBotY_F 10 0 RW For interlace TV output this value should be set to half of the original screen y coordinate The original screen coordinate should be value NOTE Registers should have word boundary X position Therefore 24 BPP mode should have X position by 1 pixel For example 0 1 2 3 16 BPP mode should have X position by 2pixel For example X 0 2 4 6 8 BPP mode should have X position by 4pixel For example X 0 4 8 12 SAMSUNG ELECTRONICS 16 86 ex 4412 UM 16 Display Controller 16 5 3 21 VIDOSD1C e Base Address 0x11C0_0000 e Address Base Address 0x0058 Reset Value 0x0000_0000 Svo tg Remd Specifies Red Alpha upper value case AEN 0 Specifies Green Alpha upper value case AEN 0 E E o EE Specifies Blue Alpha upper value case AEN E Specifies Red Alpha upper value case AEN 1 o Specifies Green Alpha upper value case 1 NOTE For more information refer to VIDW1ALPHAQ 1 register 16 5 3 22 VIDOSD1D e Base Address 0x11C0_0000 e Address Base Address 0x005C Reset Value 0 0000 0000 RW Reserved RSVD 25 24 gt 2924 NOTE
461. hould be seto 0 Specifies Buffer Status read only NOTE BUFSTATUS BUFSTATUS BUFSTATUS Lj BUFSEL L Selects Buffer set NOTE BUFSEL BUFSEL H BUFSEL 1 Specifies Double Buffer Auto control bit BUFAUTOEN 19 0 Fixed by BUFSEL 1 Auto changed by Trigger Input BITSWP F 18 BYTSWP F 17 HAWSWP F 16 0 Disables swap 1 Enables swap Specifies Word swap control bit WSWP F 15 RW 0 Disables swap 1 Enables swap BUF MODE 14 BW Selects auto buffering mode 0 Double SAMSUNG ELECTRONICS 16 78 RW RW Specifies Bit swap control bit 0 Disables swap 1 Enables swap Specifies Byte swap control bit 0 Disables swap 1 Enables swap Specifies Half Word swap control bit 4412 UM 16 Display Controller Name Type Description Reset Value AA Reserved RSVD 13 11 ES NOTE This bit should be set to O MEM Selects DMA Burst Maximum Length 00 16 word burst 1 RW SURSELEN 19 31 01 8 word burst 10 4 word burst RSVD ALPHA Selects blending category BLD_PIX_F RW 0 Per plane blending 1 Per pixel blending Selects Bits Per Pixel BPP mode in Window image 0000 1 BPP 0001 2BPP 0010 4 0011 8 BPP palletized 0100 8 BPP non palletized A 1 R 2 G 3 B 2 0101 16 BPP non palletized R 5 G 6 B 5 0110 16 BPP non palletized A 1 R 5 G 5 B 5 0111 16 BPP non palletized 1 R 5 G 5 B 5 1000
462. iagram SAMSUNG ELECTRONICS 17 8 II 4412 UM 17 Keypad Interface 17 6 Keypad Scanning Procedure for Hardware Scan At initial stage the keypad scanning procedures are same as software scan If any key is pressed the hardware automatically scans the corresponding row and column lines and writes the information into the register After scan and write to the register it generates keypad interrupt The CPU software can get the row and column number by accessing the KEYIFSCAN1 first key or KEYIFSCAN2 second key register The value of KEYIFSCAN1 KEYIFSCAN2 is valid when the key is pressed At hardware scan mode you should set the H_CNT value in KEYIFCON register The initial value is OxF In each scanning step after driving the column scanning hardware waits for H_CNT cycle When the row input signal is stable after H_CNT cycle scanning hardware verifies the row input signal It limits the multiple key press support in hardware scan mode to dual key with other row SAMSUNG ELECTRONICS 17 9 ex 4412 UM 17 Keypad Interface 17 7 I O Description Table 17 1 describes the keypad interface Table 17 1 Keypad Interface I O Description Type XEINT_29 XEINT_29 GPX3 5 GPX3 5 KP ROW 13 KEYPAD interface row 13 data muxed ROW 12 ROW 11 KP ROW 10 KP ROW 9 j KP_ROW 8 KP_ROW 7 KP_ROW 6 KP_ROW 5 KP_ROW 4 KP_ROW 3 KP_ROW 2 KP_ROW
463. ical back porch specifies the number of inactive lines at 0 00 the start of a frame after vertical synchronization period VFPD 15 8 RW Vertical front porch specifies the number of inactive lines at 0x00 the end of a frame before vertical synchronization period Vertical synchronization pulse width determines the high VSPW 7 0 RW level width of VSYNC pulse by counting the number of inactive lines 16 5 3 6 VIDTCON1 e Base Address 0x11C0_0000 e Address Base Address 0x0014 Reset Value 0x0000 0000 Vertical front porch specifies the number of inactive lines at VFPDE 31 24 RW the end of a frame before vertical synchronization period only for the even field of YVU interface Horizontal back porch specifies the number of VCLK periods 2826 between the falling edge of and start of active data 0x09 Horizontal front porch specifies the number of VCLK periods between the end of active data and rising edge HSYNG 9 08 Horizontal synchronization pulse width determines the high HSPW 7 0 RW level width of HSYNC pulse by counting the number of 0 00 VCLK SAMSUNG ELECTRONICS 16 64 x 4412 UM 16 Display Controller 16 5 3 7 VIDTCON2 e Base Address 0x11C0_0000 e Address Base Address 0x0018 Reset Value 0x0000_0000 Determines vertical size of display In the Interlace mode LINEVAL 1 should be even HOZVAL 10 0 Determines
464. ies size of palette data format of Window 3 000 16 bit 5 6 5 001 16 bit A 5 5 5 010 18 bit 6 6 6 WSPAL 2 0 011 2 18 bit A 6 6 5 100 19 bit A 6 6 6 101 24 bit 8 8 8 110 25 bit A 8 8 8 111 32 bit 8 8 8 8 A 8 bit Specifies size of palette data format of Window 2 000 16 bit 5 6 5 001 16 bit A 5 5 5 010 18 bit 6 6 6 W2PAL 2 0 011 18 bit A 6 6 5 100 19 bit A 6 6 6 101 24 bit 8 8 8 110 25 bit A 8 8 8 111 32 bit 8 8 8 8 A 8 bit SAMSUNG ELECTRONICS 16 106 ex 4412 UM 16 Display Controller Specifies size of palette data format of Window 1 000 25 bit A 8 8 8 001 24 bit 8 8 8 010 19 bit A 6 6 6 011 18 bit A 6 6 5 100 18 bit 6 6 6 101 16 bit A 5 5 5 110 16 bit 5 6 5 111 32 bit 8 8 8 8 8 bit Specifies size of palette data format of Window 0 000 25 bit A 8 8 8 001 24 bit 8 8 8 010 19 bit A 6 6 6 WOPAL 2 0 011 18 bit A 6 6 5 100 18 bit 6 6 6 101 16 bit A 5 5 5 110 16 bit 5 6 5 111 32 bit 8 8 8 8 A 8 bit 2 The bit map for W0 W1 is different from W2 W3 W4 SAMSUNG ELECTRONICS 16 107 IT 4412 UM 16 Display Controller 16 5 3 58 TRIGCON e Base Address 0x11C0_0000 e Address Base Address 0x01A4 Reset Value 0x0000_0000 RSV nome po SWTRGCMD Specifies Window 4 double buffer trigger W4BUF 26 RW 1 Enables Software Trigger Co
465. iggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0x5 to 0 7 Reserved mw eme mw SAMSUNG ELECTRONICS 4 266 IT 4412 UM 4 General Purpose Input Output GPIO Control Sets signaling method of EXT_INT41 2 0 0 Low level 0x1 High level EXT_INT41_CON 2 10 8 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT41 1 0 0 Low level 0x1 High level EXT_INT41_CON 1 6 4 W 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0 5 to 0 7 Reserved Sets signaling method of EXT_INT41 0 0 0 Low level 0x1 High level EXT INT41 CON O 2 0 RW 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0 5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 267 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 212 EXT_INT42CON e Base Address 0x1100 0000 e Address Base Address 8 Reset Value 0x0000 0000 RSV o Sets signaling method of EXT_INT42 7 0 0 Low level 0x1 High level EXT 42 CON 7 30 28 RW 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved 85 2 eens oo Sets signaling method of EXT_INT42 6 0 0 Low level 0x1 High level EXT 42 CON 6 26 24 RW 0x2 Triggers Falli
466. ilter 0 1 Enables Filter FLTWIDTH4 2 22 16 Filtering width of EXT_INT33 2 Filter Enable for EXT_INT33 1 FLTENA 1 15 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH4 1 14 8 Filtering width of EXT INT33 1 Filter Enable for EXT INT33 0 FLTENA 0 7 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH4 0 1601 RW Filtering width of EXT INT33 0 SAMSUNG ELECTRONICS 4 329 II 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 47 EXT_INT33_FLTCON1 Base Address Ox106E 0000 e Address Base Address 0x081C Reset Value 0x0000 0000 Filter Enable for EXT INT33 7 FLTEN4 7 31 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH4 7 30 24 Filtering width of EXT INT33 7 Filter Enable for EXT INT33 6 FLTENA 6 23 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH4 6 22 16 Filtering width of Filter Enable for EXT_INT33 5 FLTENA 5 15 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH4 5 14 8 Filtering width of EXT INT33 5 Filter Enable for EXT INT33 4 FLTENA 4 7 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH44 60 RW Filtering width of EXT INT33 4 SAMSUNG ELECTRONICS 4 330 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 48 EXT_INT34_FLTCONO Base Address Ox106E 0000 e Address Base Address 0x0820 Reset Value 0x0000 0000
467. ilter Enable for EXT INT9 1 FLTEN11 1 15 RW 0x0 Disables Filter 0x1 Enables Filter FLTWIDTH11 1 14 8 Filtering width of EXT_INT9 1 Filter Enable for EXT INT9 0 FLTEN1 1 0 7 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH11 0 6 0 RW Filtering width of EXT 9 0 4 3 3 148 EXT INT9 FLTCON1 e Base Address 0x1100 0000 e Address Base Address 0x0854 Reset Value 0x0000 0000 RSV area eee 9 Filter Enable for EXT INT9 6 FLTEN11 6 23 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH11 6 22 16 Filtering width of EXT_INT9 6 Filter Enable for EXT_INT9 5 FLTEN11 5 15 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH11 5 14 8 Filtering width of EXT INT9 5 Filter Enable for EXT INT9 4 FLTEN 1 114 7 RW 0x0 Disables Filter 0 1 Enables Filter FLTWIDTH11 4 6 0 RW Filtering width of EXT INT9 4 SAMSUNG ELECTRONICS 4 224 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 149 EXT_INT10_FLTCONO e Base Address 0x1100 0000 e Address Base Address 0x0858 Reset Value 0x0000_0000 Filter Enable for EXT INT10 3 FLTEN12 3 31 RW 0 0 Disables Filter 0 1 Enables Filter FLTWIDTH12 3 30 24 Filtering width of EXT INT10 3 Filter Enable for EXT INT10 2 FLTEN12 2 23 RW 0 0 Disables Filter 0x1 Enables Filter FLTWIDTH12 2 22 16 Filtering width of EXT INT10
468. ilter Selection for EXT INT42 1 FLTSEL17 1 0 0 Delays filter Ox1 Digital filter clock count Filtering width of EXT INT42 1 FLTWIDTH17 1 This value is valid when FLTSEL17 of EKT INT42 is 0x1 Filter Enable for EXT_INT42 0 FLTEN17 0 0x0 Disables Filter 0 1 Enables Filter Filter Selection for EXT_INT42 0 FLTSEL17 0 0 0 Delays filter Ox1 Digital filter clock count Filtering width of EXT INT42 0 FLTWIDTH17 0 This value is valid when FLTSEL17 of EXT INT42 is Ox1 SAMSUNG ELECTRONICS 4 276 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 219 EXT_INT42_FLTCON1 e Base Address 0x1100 0000 e Address Base Address OxOE94 Reset Value 0x8080 8080 Filter Enable for EXT INT42 7 FLTEN17 7 0 0 Disables Filter 0x1 Enables Filter Filter Selection for EXT INT42 7 FLTSEL17 7 0 0 Delays filter 0x1 Digital filter clock count Filtering width of EXT_INT42 7 FLTWIDTH17 7 This value is valid when FLTSEL17 of EXT_INT42 is 0x1 Filter Enable for EXT_INT42 6 FLTEN17 6 0x0 Disables Filter 0x1 Enables Filter Filter Selection for EXT_INT42 6 FLTSEL17 6 0 0 Delays filter 0 1 Digital filter clock count Filtering width of EXT_INT42 6 FLTWIDTH17 6 This value is valid when FLTSEL17 of EXT INT42 is Ox1 Filter Enable for EXT INT42 5 FLTEN17 5 0x0 Disables Filter 0x1 Enables Filter Filter Selection for EXT_INT42 5 FLTSEL17 5 0 0
469. imer interrupt clear register Undefined SAMSUNG ELECTRONICS 12 4 ex 4412 UM 12 Watchdog Timer 12 4 1 1 WTCON e Base Address 0x1006 0000 e Address Base Address 0 0000 Reset Value 00000 8021 RSV Prescaler value 15 8 The valid range is 0 to 25 1 Reserved nove 7 6 These two bits should 00 in normal operation Enables or disables WDT bit WDT timer 5 RW 0 Disables WDT bit 1 Enables WDT bit Determines the clock division factor 00 16 Clock select 4 3 RW 01 32 10 64 11 128 Enables or disables interrupt bit 2 RW 0 Disables interrupt bit 1 Enables interrupt bit Reserved RSVD This bit should 0 normal operation Enables or disables WDT output bit for reset signal Reset 0 Disables the reset function of the watchdog timer enable disable 1 Asserts reset signal of the Exynos 4412 at watchdog time out The WTCON register e Allows you to enable disable the watchdog timer Selects the clock signal from four different sources e Enables disables interrupts e Enables disables the watchdog timer output You can use WDT to restart the Exynos 4412 to recover from malfunction If you do not want to restart the controller disable WDT If you want to use the normal timer that WDT provides enable the interrupt and disable the WDT SAMSUNG ELECTRONICS 12 5 II 4412 UM 12 Watchdog Timer
470. in Blend Equation 2 2 BPPMODE F BLD_PIX ALPHA SEL at WINCONx and WxPAL at WPALCON decides the alphaA and alphaB SAMSUNG ELECTRONICS 16 126 x 4412 UM 16 Display Controller 16 5 3 82 BLENDEQ3 e Base Address 0x11C0 0000 e Address Base Address 0x024C Reset Value 0x0000_00C2 Bt22 Specifies constant that it uses in alphaB alpha value of background 1 0000 0 zero 0001 1 maximum 0010 alphaA 2 alpha value of foreground 1 0011 1 alphaA 0100 alphaB 0101 1 alphaB FUNC F 21 18 RW 0110 ALPHA0 0111 Reserved 100x Reserved 1010 A foreground color data 1011 1 1100 background color data 1101 1 111 Reserved RSVD 17 16 Specifies constant that it uses in alpha P FUNC F 15 12 RW Le Same as above see COEF 9 RD Specifies constant that it uses in B B FUNC F RW Same as above see COEF 9 RSVD 164 Specifies constant that it uses in A A FUNC F RW 3 0 Same as above see COEF 9 NOTE For more information Refer to Figure 16 23 Blending eguation 1 Background Window 012 foreground Window 3 in Blend Eguation 3 2 BPPMODE BLD PIX ALPHA SEL WINCONx and WxPAL WPALCON decides the alphaA and alphaB SAMSUNG ELECTRONICS 16 127 x 4412 UM 16 Display Controller 16 5 3 83 BLENDEQ4 e Base Address 0x11C0_0000 e Address Base Address 0x0250 Reset
471. indow control bit If it enables this bit then Video DMA stops and MAPCOLEN F 24 RW MAPCOLOR appears on background image instead of original image 0 Disables 1 Enables MAPCOLOR 23 0 Specifies color value 16 5 3 52 WIN1MAP e Base Address 0x11C0_0000 e Address Base Address 0x0184 Reset Value 0x0000_0000 Specifies the color mapping of window control bit If it enables this bit then Video DMA stops and MAPCOLOR MAPCOLEN_F 24 RW appears on background image instead of original image 0 Disables 1 Enables MAPCOLOR 23 0 Specifies the color value 16 5 3 53 WIN2MAP e Base Address 0x11C0_0000 e Address Base Address 0x0188 Reset Value 0x0000_0000 Specifies the color mapping of window control bit If it enables this bit then Video DMA stops and MAPCOLEN F 24 RW MAPCOLOR appears on background image instead of original image 0 Disables 1 Enables MAPCOLOR 23 0 Specifies color value SAMSUNG ELECTRONICS 16 104 ex 4412 UM 16 Display Controller 16 5 3 54 WIN3MAP e Base Address 0x11C0_0000 e Address Base Address 0x0_018C Reset Value 0x0000_0000 Specifies color mapping of window control bit If it enables this bit then Video DMA stops and MAPCOLEN F 24 RW MAPCOLOR appears on background image instead of original image 0 Disables 1 Enables MAPCOLOR 23 0 Specifies color value 16 5 3 55 WIN4MA
472. ing all clocks for 2 1 ISP 1261 ISP 26 0 1 Gating all clocks 2 0 ISP 1260 ISP 25 0 1 Gating all clocks for MPWM_ISP CLK_MPWM_ISP 24 0 Mask 1 Pass Gating all clocks for MCUCTL_ISP CLK_MCUCTL_ISP 23 0 Mask 0 1 1 Pass ASV MEC Gating all clocks for PPMUISPK CLK_PPMUISPX 21 RW 0 Mask 0 1 1 Pass Gating all clocks for PPMUISPMK CLK_PPMUISPMX 20 RW 0 Mask 0 1 1 Pass Gating all clocks for SMMU LITE1 CLK SMMU LITE1 12 RW 0 Mask 0 1 1 Pass Gating all clocks for SMMU_LITEO CLK_SMMU_LITEO 11 RW 0 Mask 1 Pass SAMSUNG ELECTRONICS 5 159 4412 UM 5 Clock Management Unit Gating all clocks for SMMU FD CLK_SMMU_FD 10 RW 0 Mask 1 Pass Gating all clocks for SMMU DRC CLK SMMU DRC 0 Mask Gating all clocks for SMMU_ISP CLK_SMMU_ISP RW CLK_GICISP Gating all clocks for GICISP RW RSVD MCUISP MOM Gating all clocks for MCUISP 5 RW 0x1 Gating all clocks for ISP CLK_ISP RW 0 Mask 0 1 1 Pass SAMSUNG ELECTRONICS 5 160 en 4412 UM 5 Clock Management Unit 5 10 1 155 CLK_GATE_IP_ISP1 e Base Address 0x1004 0000 e Address Base Address 0x8804 Reset Value OxFFFF_FFFF Gating all clocks for SPI1_ISP except SCLK CLK_SPI1_ISP 13 RW 0 Mask 1 Pass Gating all clocks for SPIO_ISP except SCLK CLK SPIO ISP 12 RW 0 Mask 1
473. interface o Supports byte and half word access Interface Supports industry standard interface x8 data bus LPDDR2 interface o x32 data bus up to 800 Mbps pin 1 2 interface voltage Density support up to 4 Gb per port 2CS SAMSUNG ELECTRONICS 1 5 IT 4412 UM 1 Product Overview 1 2 3 Multimedia The features of multimedia are Camera Interface Multiple input support o ITU R 601 656 mode 64 bit interface mode CSI mode o Direct FIFO mode from LCDC Multiple output support o 64 bit interface mode o Direct FIFO mode to Digital Zoom In 071 capability Multiple camera input support Programmable polarity of video sync signals nput horizontal size support up to 4224 pixels for scaled and 8192 pixels for un scaled resolution Image mirror and rotation X axis mirror Y axis mirror 90 180 and 2709 rotation Various image formats generation Capture frame control support mage effect support JPEG Codec supports Compression Decompression up to 65536 x 65536 Supported format of compression o raw image YCbCr4 2 2 or RGB 565 o Output JPEG file Baseline JPEG of YCbCr4 2 2 or YCbCr4 2 0 General purpose color space converter 2D Graphic Engine supports BitBLT Maximum 8000 x 8000 image size Window clipping 90 180 270 Rotation X Flip Y Flip T
474. interrupt enable bit 0 Masks SYSMMU_FIMC_LITEO 0 1 Enables 0 ex SAMSUNG ELECTRONICS 7 26 4412 UM 7 Interrupt Combiner 7 6 2 18 IECR4 Base Address 0x1044 0000 e Address Base Address 0x0044 Reset Value 0x0000_0000 RSVD 31 CPU nIRQOUT 3 30 Clears the corresponding interrupt enable bit to 0 If you clear the interrupt enable bit interrupt 2 RW PARDO MESS fg aw combiner will mask the interrupt PARITYFAILS 28 Write 0 Does not change the current setting RW 1 Clears the interrupt enable bit to 0 CPU nCTIIRQ 3 Read Th ble ea e current interrupt enable bit CPU PMUIRQ 3 W 0 Masks RSVD W 1 Enables MCT LO RW RSVD 23 CPU nIRQOUT 2 22 Clears the corresponding interrupt enable bit to 0 If you clear the interrupt enable bit interrupt IL 2 21 RW _ 2 RW combiner will mask the interrupt PARITYFAIL2 20 Write 0 Does not change the current setting CPU nCTIIRQ 2 19 RW 1 Clears the interrupt enable bit to 0 Read The current interrupt enable bit CPU PMUIRQ 2 18 RW 0 Masks RSVD 17 RW 1 Enables 11 16 RW MCT L2 15 RW RSVD 14 Er Clears the corresponding interrupt enable bit to 0 If you clear the interrupt enable bit interrupt ISP CX 1 1 RW SEM A na RW combiner will mask the interrupt SYSMMU FIMC FD 1 12 Write 0 Does not change the current setting 1 Clears the interrupt enable bit
475. isables filter 0x1 Enables filter FLTWIDTH1 7 30 24 Filtering width of EXT_INT1 7 Filter Enable for EXT INT1 6 FLTEN 1 6 23 RW 0 0 Disables filter 0 1 Enables filter FLTWIDTH1 6 22 16 Filtering width of EXT INT1 6 Filter Enable for EXT INT1 5 FLTEN1 5 15 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH1 5 14 8 Filtering width of EXT_INT1 5 Filter Enable for EXT_INT1 4 FLTEN1 4 7 RW 0 0 Disables filter 0x1 Enables filter FLTWIDTH1 4 6 0 Filtering width of EXT_INT1 4 SAMSUNG ELECTRONICS 4 83 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 96 EXT_INT2_FLTCONO Base Address 0x1140_0000 e Address Base Address 0x0808 Reset Value 0 0000 0000 Filter Enable for EXT_INT2 3 FLTEN2 3 31 RW 0 0 Disables filter 0 1 Enables filter FLTWIDTH2 3 30 24 Filtering width of EXT INT2 3 Filter Enable for EXT INT2 2 FLTEN2 2 23 RW 0 0 Disables filter 0x1 Enables filter FLTWIDTH2 2 22 16 Filtering width of EXT INT2 2 Filter Enable for EXT_INT2 1 FLTEN2 1 15 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH2 1 14 8 Filtering width of EXT_INT2 1 Filter Enable for EXT_INT2 0 FLTEN2 0 7 RW Disables filter 0 1 Enables filter FLTWIDTH2 0 6 0 RW Filtering width of EXT_INT2 0 4 3 2 97 EXT_INT2_FLTCON1 e Base Address 0x1140_0000 e Address Base Address 0x080C
476. ister SPI 107 104 0 0000 0000 ICDIPTR35 Processor targets register SPI 111 108 0x0000_0000 ICDIPTR36 Processor targets register SPI 115 112 0x0000_0000 SAMSUNG ELECTRONICS 6 18 4412 UM 6 Interrupt Controller ICDIPR2_CPU1 Priority level register SGI 11 8 0x0000 0000 SAMSUNG ELECTRONICS 6 19 4412 UM 6 Interrupt Controller ICDIPR2_CPU2 Priority level register SGI 11 8 0 0000_0000 SAMSUNG ELECTRONICS 6 20 4412 UM 6 Interrupt Controller Register __ Description Reset value Active status register SGI Priority level register 1 81 Priority level register PPI 15 12 Processor targets register SGI 3 0 Processor targets register PPI 11 8 Processor targets register PPI 15 12 Interrupt configuration register SGI 15 0 Interrupt configuration register 5 01 SAMSUNG ELECTRONICS 6 21 ex 4412 UM 7 Interrupt Combiner Interrupt Combiner 7 1 Overview Interrupt controller in Exynos 4412 consists of PrimeCell generic interrupt controller PL390 e combiner A few interrupt sources are grouped in Exynos 4412 Interrupt combiner combines several interrupt sources as a group Several interrupt requests in a group make a group interrupt request and a single request signal As a result the interrupt input sources of PrimeCell generic interrup
477. it ECC RSVD 22 10 Reserved 0000000 and ALE duration setting value 0 15 15 12 TABLE pes Nd Duration HCLK x TACLS TWRPHO duration setting value 0 15 TWRPHO 11 8 Duration HCLK x TWRPHO 1 NOTE You should add additional cycles about 10ns for page read because of additional signal delay on PCB pattern TWRPH1 duration setting value 0 15 7 4 E Duration HCLK x TWRPH1 1 This bit indicates the page size of NAND flash memory 00 2048 byte 01 2 512 byte 10 4096 byte PageSize 3 2 11 2048 byte NOTE Using 1 bit ECC it determines the message length It does not determine the message length using MsgLength NFCONF 25 field NFCON does not consider the actual page size of external NAND Software handles the page size This bit indicates the number of address cycle of NAND flash memory When Page Size is 512 Bytes 0 3 Address cycle 1 4 Address cycle AddrCycle RW When size is 2 or 4 0 4 Address cycle 1 5 Address cycle NOTE It is only used for Lock scheme Refer to section 10 4 12 Lock Scheme for Data Protection for more information mw m ne SAMSUNG ELECTRONICS 10 17 4412 UM 10 NAND Flash Controller 10 7 2 2 NFCONT e Base Address OXOCEO 0000 e Address Base Address 0x0004 Reset Value 0x00C1 00 6 RSV prea AT NAND flash memory nRCS 3 signal control Reg_nCE3 23 RW 0 Force nRCS 3 to lo
478. ittle Invalid value Invalid value 2 1 0 7 0 1 1 0 7 0 3 Byte Access Register Enden Busse NFDATA Little Invalid value Invalid value Invalid value 1 1 0 7 0 SAMSUNG ELECTRONICS 10 4 ex 4412 UM 10 NAND Flash Controller 10 4 2 1 4 8 12 16 bit ECC NAND flash controller supports 1 4 8 12 16 bit ECC For 1 bit ECC NAND flash controller includes ECC modules for main and spare meta data Main data ECC module generates ECC parity code for 2048 bytes maximum data message length whereas spare meta data ECC module generates ECC parity code for 32 bytes maximum For 4 bit ECC NAND flash controller includes an ECC module It generates 512 or 24 bytes of ECC parity code Set MsgLength NFCONF 25 to select 512 or 24 bytes message length For 8 12 16 bit ECC NAND flash controller includes ECC modules for each ECC You can select data message length for main and spare meta data length Usually the length of main data is 512 bytes and the length of spare meta data depends on user application Since these ECC modules support variable length of main and spare meta data you should set the ECC parity conversion codes to handle free page Refer to 10 4 11 ECC Conversion Code Guide for 8 12 16 bit ECC for more information on ECC parity conversion codes Free page specifies an erased page The value of erased page is Oxff Therefore set the ECC conversio
479. ixer supports Overlapping and blending input video and graphic layers 480p 576p 720p and 1080i p display size Four layers 1 video layer 2 graphic layer and 1 background layer e TFT LCD Interface The TFT LCD Interface supports 24 18 16 bpp parallel RGB Interface LCD 8 6 bpp serial RGB Interface Dual i80 Interface LCD 1 2 4 8 bpp Palletized or 8 16 24 bpp Non Palletized Color TFT Typical actual screen size 1080 x 1024 1024 x 768 800 x 480 640 x 480 320 x 240 160 x 160 and so on Virtual image up to 16M pixel 4K pixel x 4K pixel Five Window Layers for PIP or OSD Real time overlay plane multiplexing Programmable OSD window positioning 16 level alpha blending SAMSUNG ELECTRONICS 1 7 x 4412 UM 1 2 4 Audio Subsystem The features of audio subsystem are Reconfigurable Processor RP progresses audio processing Low power audio subsystem 5 1 channel 125 with 32 bit width 64 depth FIFO 128 KB audio play output buffer Hardware mixer mixes primary and secondary sounds 1 2 5 Image Signal Processing Subsystem The features of ISP subsystem are e Dual camera input e Image signal processing e Dynamic range correction e Face detection SAMSUNG ELECTRONICS 1 8 1 Product Overview 4412 UM 1 Product Overview 1 2 6 Connectivity The features of connectivity are PCM Audio Interface supports 16 bit mono audio in
480. k N m O O O O gt po x aj ajajaja A S N N N 00 l N N GPIO_RT RTC TIC SAMSUNG ELECTRONICS 6 7 4412 UM 6 Interrupt Controller SPI Port No x o qmomew gt x jw Ima S mere Imc Rem A mos uomo mr mem T A mem E M AS O1 O gt O cO 00 TIMERO hen He E ERES EAT ME essem ______ 0 000 fens Ewemditemp Esd femme fema Eqema interrupt fem Ewemditemp ENMO ___ ___ Evemditemp femme Evemdiemp _______ fem Ewemditemp femme emaner ENE Ewemdiemp femme femme Ewemditemp femme Ewemditemp EN Ewemditemp EN Ewemdiemp 27 SAMSUNG ELECTRONICS 6 8 4412 UM 6 Interrupt Controller UC TT 0 mors o mas EI mo 11 mora E moms ETT mo 1 mors CO E SGUEVABORT Fo 1 m
481. ks belong to their respective owners e Exynos Exynos4412 FlexOneNAND and OneNAND are trademarks of Samsung Electronics e ARM Jazelle TrustZone and Thumb are registered trademarks of ARM Limited e Cortex ETM ETB Coresight ISA and Neon are trademarks of ARM Limited e Java is a trademark of Sun Microsystems Inc SD is registered trademark of Toshiba Corporation e and eMMC are trademarks of MultiMediaCard Association e JTAG is registered trademark of JTAG Technologies Inc e Synopsys is a registered trademark of Synopsys Inc e 12S is a trademark of Phillips Electronics e 2C is a trademark of Phillips Semiconductor Corp e and Slimbus are registered trademarks of the Mobile Industry Processor Interface Alliance All other trademarks used in this publication are the property of their respective owners SAMSUNG ELECTRONICS 227 Chip Handling Guide Precaution against Electrostatic Discharge When using semiconductor devices ensure that the environment is protected against static electricity 1 Wear antistatic clothes and use earth band 2 Allobjects that are in direct contact with devices must be made up of materials that do not produce static electricity 3 Ensure that the equipment and work table are earthed Use ionizer to remove electron charge Contamination Do not use semiconductor products in an environment to dust or dirt adhesion Temper
482. l Bus Interface EBI which uses two different clocks source The constraint occurs because EBI operates using OneNAND external interface clock and EBI interface between is handled as asynchronous interface so that a few clock latencies consume for bus handshaking The clock of NFCON should be set lower than internal operation clock Refer to the and Clock Management Unit CMU manual for more information 10 6 1 0 Description SAMSUNG ELECTRONICS 10 14 IT 4412 UM 10 NAND Flash Controller 10 7 Register Description 10 7 1 Register Map Summary e Base Address _0000 register Reservalue 1 4 bit Register 1 and 2 main ECC data register 3 and 4 main ECC data register SAMSUNG ELECTRONICS 10 15 ex 4412 UM 10 Flash Controller e Base Address OXOCE2 0000 Register Desempti n Reset Value 8 12 16 bit ECC Register SAMSUNG ELECTRONICS 10 16 IT 4412 UM 10 NAND Flash Controller 10 7 2 NAND Flash Interface and 1 4 bit ECC Registers 10 7 2 1 NFCONF e Base Address OXOCEO 0000 Address Base Address 0x0000 Reset Value 0x0000 1000 mw _ eee 9 512 byte message length G 24 byte message length This bit indicates the type of ECC to use 00 1 bit ECC ECCType0 24 23 RW 10 4 bit ECC 11 Disables 1 bit and 4 b
483. l down GPY3PUDIn n 0to7 RW 0x2 Reserved 0x5555 0x3 Enables Pull up 4 3 3 64 GPY3DRV e Base Address 0x1100_0000 e Address Base Address 0x018C Reset Value 0x00_AAAA 23 16 Reserved Should be zero W GPY3DRV n n 2n 1 2n R ERA 0107 SAMSUNG ELECTRONICS 4 158 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 65 GPY3CONPDN Base Address 0x1100 0000 e Address Base Address 0x0190 Reset Value 0x0000 0 0 Outputs 0 2n 1 21 0 1 Outputs 1 0107 FUN 0x2 Input n 0 3 Previous state 4 3 3 66 GPY3PUDPDN Base Address 0x1100 0000 e Address Base Address 0x0194 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down 0107 i 0x2 Reserved 990 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 159 ex 4412 UM 4 3 3 67 GPY4CON Base Address 0x1100 0000 e Address Base Address 0x01A0 Reset Value 0x0000 0000 GPY4CON 7 GPY4CON 6 GPY4CON 5 GPY4CON 4 GPY4CON 3 GPY4CON 2 GPY4CON 1 SAMSUNG ELECTRONICS 31 28 11 8 0 0 Input 0 1 Output 0 2 EBI ADDR 15 0 3 Reserved 0 4 XhsiCAREADY 0 5 to Reserved OxF 0 0 Input 0 1 Output 0 2 EBI ADDR 14 0x3 Reserved 0 4 XhsiACFLAG 0 5 to Reserved OxF 0 0 Input 0 1 Output 0 2 EBI ADDR 13 0 3 Reserved 0
484. l down GPYOPUD n nudos RW 0x2 Reserved OxOFFF 0x3 Enables Pull up 4 3 3 46 GPYODRV e Base Address 0 1100 0000 e Address Base Address 0x012C Reset Value 0x00 0AAA 23 16 Reserved Should be zero W GPYODRVIn n 2n 1 2n R DOARA 0105 SAMSUNG ELECTRONICS 4 148 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 47 GPYOCONPDN Base Address 0x1100 0000 e Address Base Address 0x0130 Reset Value 0x0000 0 0 Outputs 0 2n 1 21 0 1 Outputs 1 POI 0105 FW oxo lt input 552 0 3 Previous state 4 3 3 48 GPYOPUDPDN Base Address 0x1100_0000 e Address Base Address 0x0134 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down 0105 0 2 Reserved 990 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 149 ex 4412 UM 4 3 3 49 GPY1CON Base Address 0x1100 0000 e Address Base Address 0x0140 Reset Value 0x0000_0000 SAMSUNG ELECTRONICS 0 0 Input 0 1 Output 0 2 EBI DATA RDn 0 4 to Reserved 0 0 Input 0 1 Output 0 2 SROM_WAITn 0 4 to Reserved 0 0 Input 0 1 Output 0 2 EBI BEn 1 0 4 to Reserved 0 0 Input 0 1 Output 0 2 EBI BEn 0 0 4 to Reserved 4 150 4 General Purpose Input Output GPIO Control 4412 UM 4 General Purpose Input Output GPIO Cont
485. l resync pulse form DREX2 during _ 28 DDRPHY DLL Locking time RSVD pa CURR STATE 17 16 Specifies current status for debugging DUR LOCK WAIT 15 8 Sets Duration for DLL Lock Wait of DDR_PHY E DUR CTRL ST 7 0 Sets Duration for clearing ctrl start signal of 0 CLR DDR PHY 5 10 1 130 C2C STATE Base Address 0x1004 0000 e Address Base Address 0x109C Reset Value 0x0000 0000 ASVD pup 0 0 CURR STATE R Current State ofC2C SEC FSM SAMSUNG ELECTRONICS 5 139 ex 4412 UM 5 Clock Management Unit 5 10 1 131 APLL LOCK e Base Address 0x1004 0000 e Address Base Address 0x4000 Reset Value 0x0000 OFFF RSV pug eee Required period to generate stable clock output Set 270cycles x to PLL LOCKTIME for the PLL maximum lock time PLL LOCKTIME 15 0 RW 1 cycle 1 FREF 1 FIN PDIV The maximum PLL lock time is 22 5 usec where FIN 24 MHz is 2 and PLL_LOCKTIME is 540 The maximum lock time means the waiting time for locking in the worst case Therefore the user of this PLL must wait for more than the maximum lock time unconditionally before the PLL is locked Waiting time before locking gt the maximum locktime SAMSUNG ELECTRONICS 5 140 ex 4412 UM 5 Clock Management Unit 5 10 1 132 APLL CONO e Base Address 0 1004 0000 e Address Base Address
486. ld be same as 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 3 97 GPM1PUD Base Address 0x1100 0000 e Address Base Address 0x0288 Reset Value 0 1555 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down GPM1PUD n n 0to6 RW 0x2 Reserved 0x1555 0x3 Enables Pull up 4 3 3 98 GPM1DRV e Base Address 0x1100_0000 e Address Base Address 0x028C Reset Value 0x00_ 0000 23 16 Reserved Should be zero W GPM1DRV n n 2n 1 21 0x0000 0106 SAMSUNG ELECTRONICS 4 179 II 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 99 e Base Address 0x1100 0000 e Address Base Address 0x0290 Reset Value 0x0000 0 0 Outputs 0 2n 1 21 0 1 Outputs 1 n 0t06 PW 0 2 Input 999 0 3 Previous state 4 3 3 100 GPM1PUDPDN e Base Address 0x1100 0000 e Address Base Address 0x0294 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down Gemini 0106 Du 0x2 Reserved 990 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 180 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 101 GPM2CON e Base Address 0x1100 0000 e Address Base Address 0x02A0 Reset Value 0x0000 0000 0 0 Input 0 1 Output 0 2 CAM GPIO 1 GPM2CON 4 19 16 0x3 MPWM2 OUT ISP 0x00 0 4 t
487. le bit to 1 Read The current interrupt enable bit cpu 3 Es 0 Masks RSVD 25 1 Enables NENNEN er 10 p ar CPU nIRQOUT 2 22 Sets the corresponding interrupt enable bit to 1 If you interrupt enable bit interrupt 21 combiner serves the interrupt request PARITYFAIL2 20 RW Write 0 Does not change the current setting CPU nCTIIRQ 2 19 1 Sets the interrupt enable bit to 1 Read The current interrupt enable bit cpu 2 CENE 0 Masks RSVD 17 1 Enables TENE s arusa RSVD 14 Sets the corresponding interrupt enable bit to 1 If you interrupt enable bit interrupt S SMU 13 combiner serves the interrupt request SYSMMU FD 1 12 RW Write 0 Does not change the current setting SYSMMU DRC 1 11 1 Sets the interrupt enable bit to 1 Read The current interrupt enable bit SYSMMU_FIMC_ISP 1 10 0 Masks SYSMMU_FIMC_LITEO 1 9 Rw 1 Enables DUE RSVD fe Sets the corresponding interrupt enable bit to 1 If you set interrupt enable bit interrupt SYSMMUTSE CNIU combiner serves the interrupt request SYSMMU FIMC FD 0 RW Write 0 Does not change the current setting __ SYSMMU FIMC DRC 0 1 Sets the interrupt enable bit to 1 Read The current
488. lears the corresponding interrupt enable bit to If o0 PMUIRQ ISP 29 you clear the interrupt enable bit interrupt combiner 3 Write 0 Does not change the current setting 27 1 Clears the interrupt enable bit to PMUIR 1 26 RW Read The current interrupt enable bit de PARITYFAILSC 1 25 0 Masks RSVD Rema a 22 Clears the corresponding interrupt enable bit to 0 L8 PARRDINTR 21 you clear the interrupt enable bit interrupt combiner I 33 ou CTIIRQIO Write 0 Does not change the current setting 0 19 1 Clears the interrupt enable bit to PMUIRQ 0 18 RW Read The current interrupt enable bit PARITYFAILSCU O 17 0 Masks RSVD fo TZASC1 1 11 Clears the corresponding interrupt enable bit to If TZASC1 1 RW you clear the interrupt enable bit interrupt combiner i ET will mask the interrupt TZASCOM RW RW write 0 Does not change the current setting 1 Clears the interrupt enable bit to TZASCO O Read 2 interrupt enable bit 1 Enables RSVD ma RSVD Clears the corresponding interrupt enable bit to 0 If RSVD 9 Rw you clear the interrupt enable bit interrupt combiner RSVD Write 0 Does not change the current setting 1 Clears the interrupt enable bit to RSVD RW Read The current interrupt enable bit 0
489. lects clock source for CMU_CPU 0x0000_0000 0x4204 to CLK_MUX_STAT_CPU 0x4400 Clock MUX status for CMU_CPU 0x0011_0101 0x4404 to CLK_DIV_CPUO 0x4500 Sets clock divider ratio for CMU_CPU 0x0000_0000 CLK DIV CPU1 0x4504 Sets clock divider ratio for CMU CPU 0x0000 0000 SAMSUNG ELECTRONICS 5 32 4412 UM 5 Clock Management Unit CLK DIV STAT CPUO 0x4600 Clock divider status for CMU CPU 0x0000 0000 DIV STAT 0x4604 Clock divider status for CMU CPU 0x0000 0000 0x4608 to CLK GATE IP CPU 04900 Controls IP clock gating for CMU_CPU OxFFFF FFFF 0x4904 to CLKOUT_CMU_CPU 0x4A00 CLKOUT control register 0x0001_0000 PWR_CTRL 0x5020 Power control register 0x0000_04FF PWR_CTRL2 0x5024 Power control register 0x0000_0000 0x5028 to A L2 STATUS 05400 L2 cache status register 0x0000_0000 0x5404 to CPU STATUS 0x5410 Cortex A9 processor status register 0x0000_0000 0x5414 to PTM_STATUS 0x5420 2 0x0000 0000 CLK DIV ISPO 0x8300 Set clock divider ratio for CMU ISPO 0x0000 0000 Set clock divider ratio for MPWM in DIV ISP1 0x8304 CMU ISP1 0x0000 0000 CLK DIV STAT ISPO 0x8400 Clock divider status for CMU ISPO 0x0000 0000 DIV STAT ISP1 0x8404 Clock divider status for MPWM in CMU ISP1 0x0000 0000 0x8408 to CLK_GATE_IP_ISPO 0x8800 Control IP clock gating for ISP register0 OxFFFF_FFFF CLK GATE IP ISP1 0x8804 Control IP cl
490. ledgement Current State of Rx DMA FSM 0x0 IDLE 0 1 Burst Request 0 2 Burst Acknowledgement 0 3 Burst Next intermediate state for next request RX DMA 11 8 0 4 Single Reguest FSM State 0x5 Single Acknowledgement 0x6 Single Next intermediate state for next request 0 7 Last Burst Request 0x8 Last Burst Acknowledgement 0x9 Last Single Request 0x10 2 Last EE M Acknowledgement Time out status when read 0 Rx Time out did not occur 1 Rx Time out RX Time out RWX Clears Rx Time out status when write status Clear 0 No operation 1 Clears Rx Time out status NOTE When UCONn 10 is set to 1 writing 1 to this bit resumes Rx DMA FSM that was lA Yestmes Fx Mat was suspended when Rx time out ________ when Rx time out SAMSUNG ELECTRONICS 13 21 menes 70000 02 5 amm 4412 UM Transmitter empty Transmit buffer empty Receive buffer data ready SAMSUNG ELECTRONICS 13 Universal Asynchronous Receiver and Transmitter This bit is automatically set to 1 when the transmit buffer has no valid data to transmit and the transmit shift is empty 0 Not empty 1 Transmitter includes transmit buffer and shifter empty This bit is automatically 1 when transmit buffer 15 empty 0 is not empty 1 Buffer is empty in non FIFO mode it requests interrupt or DMA In FIFO mode it requests interrupt or DMA when the trigg
491. lem Exynos 4412 SPI provides fast slave Tx mode by setting 1 to HIGH SPEED bit CFG register In that mode it reduces MISO output delay by half cycle so that the SPI master device has more setup margin However you can use the fast slave Tx mode only when CPHA 0 15 2 1 7 Feedback Clock Selection Under SPI protocol specification SPI master should capture the input data launched by slave MISO with its internal SPICLK When SPI runs at high operating frequency such as 50 MHz it is difficult to capture the MISO input because the required arrival time of MISO is half cycle period in Exynos 4412 It is shorter than the arrival time of MISO that consists of SPICLK output delay of SPI master MISO output delay of SPI slave and MISO input delay of SPI master To overcome the problem Exynos 4412 SPI provides three feedback clocks that are phase delayed clock of internal SPICLK A selection of feedback clock depends MISO output delay of SPI slave To capture MISO data correctly it selects the feedback clock that satisfies the following constraint tspimis S lt tperioa 2 tspison tspimis S MISO input setup time of SPI master on given feedback clock selection s MISO output delay of SPI slave tperiod SPICLK cycle period If multiple feedback clocks meet the constraint then it should select the feedback clock with smallest phase delay Because of a feedback clock with large phase delay it ma
492. ling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved 85 2 Reeves fo Sets signaling method of EXT INT29 6 0 0 Low level 0 1 High level EXT INT29 CON 6 26 24 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved SVO gy eee wp 9 Sets signaling method of EXT INT29 5 0 0 Low level 0 1 High level EXT INT29 CON 5 22 20 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0x7 Reserved 85 0 mp mose wp 0 Sets signaling method of EXT INT29 4 0x0 Low level 0 1 High level EXT INT29 CON 4 18 16 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved 85 9 Jason fe Sets signaling method of EXT INT29 3 0 0 Low level 0 1 High level EXT 29 CON S 14 12 RW 0 2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0x5 to 0 7 Reserved mw n new mw SAMSUNG ELECTRONICS 4 203 eL 4412 UM 4 General Purpose Input Output GPIO Control Sets signaling method of EXT_INT29 2 0 0 Low level 0x1 High level EXT_INT29_CON 2 10 8 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT29 1 0 0 Low level 0x1 High level EXT_INT29_CON 1
493. lling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0x5 to 0 7 Reserved 85 0 fo Sets signaling method of EXT INT31 4 0 0 Low level 0 1 High level EXT INT31 CON 4 18 16 RW 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0x5 to 0 7 Reserved 85 9 E mw Sets signaling method of EXT_INT31 3 0 0 Low level 0x1 High level EXT INT31 CON 3 14 12 RW 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0x5 to 0 7 Reserved mw fm Jan SAMSUNG ELECTRONICS 4 316 II 4412 UM 4 General Purpose Input Output GPIO Control Sets signaling method of EXT_INT31 2 0 0 Low level 0x1 High level EXT_INT31_CON 2 10 8 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT31 1 0 0 Low level 0x1 High level EXT_INT31_CON 1 6 4 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT31 0 0 0 Low level 0x1 High level EXT INT31 CON O 2 0 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 317 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 37 EXT_INT32CON Base Address Ox106E 0000 e Address Base
494. lock operations are e Clock gating control register for function blocks e Clock gating control register for IP The two clock gating control registers ANDed to generate the final clock gating enable signal As a result if it turns OFF either of the two registers filed then the resulting clock will stop For example to stop the clocks provided to the Mixer module you should set the CLK_MIXER field in CLK_GATE_IP_TV register to 0 or CLK_TV field in CLK GATE BLOCK register to 0 For latter case all clocks in TV block not only MIXER clocks are turned off Caution Ensure that the software does not access the IPs whose clock is gated as it may cause system failure 5 6 2 Clock Diving Whenever clock divider control register is changed it is recommended to check clock divider status registers before using the new clock output This guarantees the corresponding divider finishes changing to a new dividing value before its output is used by other modules SAMSUNG ELECTRONICS 5 16 ex 4412 UM 5 Clock Management Unit 5 7 Special Clock Description Special Clock Description section describes special clock in Exynos 4412 5 7 1 Special Clock Table Table 5 5 describes the special clocks in Exynos 4412 Table 5 5 Special Clocks in Exynos 4412 Description Range Sows SCLK_ONENAND ONENAND operating clock 160 MHz ACLK_160 ACLK_133 SCLK G3D G3D core operating clock
495. lue 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down 0106 PNN 0x2 Reserved Oxu 0x3 Enables Pull up SAMSUNG ELECTRONICS 4 291 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 4 7 e Base Address 0x0386 0000 e Address Base Address 0x0700 Reset Value 0 0000 0000 Red o o mv fen o Sets signaling method of EXT INT50 6 0 0 Low level 0x1 High level EXT_INT50_CON 6 26 24 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0 7 Reserved 85 9 NEON Sets signaling method of EXT_INT50 5 0 0 Low level 0x1 High level EXT_INT50_CON 5 22 20 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0 7 Reserved 85 0 1 4 Sets signaling method of EXT_INT50 4 0 0 Low level 0x1 High level EXT_INT50_CON 4 18 16 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0 7 Reserved 85 0 Rewa mw Sets signaling method of EXT INT50 3 0x0 Low level 0 1 High level EXT INT50 CON S 14 12 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0x5 to 0 7 Reserved 85 0 m fesen mw Sets signaling method of EXT_INT50 2 0x0 Low level 0x1 High level EXT_INT50_CON 2 10 8 RW 0x
496. lue 0x0000 1000 RSVD on DIVDPM Clock Divider Ratio 20 55 LE Penamet It decides frequency of DPM channel clock KN LM Clock Divider Ratio DVSEM RATIO 22 16 RW It decides frequency for PWM frame time slot DVS emulation mode RSVD C2C ACLK Clock Divider Ratio C2C ACLK RATIO 14 12 RW ACLK 2 MOUTC2C ACLK C2C ACLK RATIO 1 DIVPWI Clock Divider Ratio 11 8 SCLK_PWI MOUTPWI PWI_RATIO 1 C2C clock divider ratio CAERA SCLK C2C MOUTC2C C2C_RATIO 1 DIVG2D_ACP clock divider ratio G2D ACP RATIO 3 0 RW SCLK G2D ACP 0 0 MOUTG2D ACP G2D ACP RATIO 1 SAMSUNG ELECTRONICS 5 129 IT 4412 UM 5 Clock Management Unit 5 10 1 112 CLK_DIV_STAT_DMCO e Base Address 0x1004 0000 e Address Base Address 0x0600 Reset Value 0x0000_0000 RSVD en gt DIVDMCP Status DIV DMCP 20 0 Stable 1 Status that the divider is changing SE vem mw DIVDMCD Status DIV DMCD 16 0 Stable 1 Status that the divider is changing SE AC DIVDMC Status DIV DMC 12 0 Stable 1 Status that the divider is changing SE ma sn AC DIVDPHY Status DIV DPHY 0 Stable 1 Status that the divider is changing SE wews mo DIVACP_PCLK Status DIV_ACP_PCLK 4 0 Stable 1 Status that the divider is changing RSV eee mw DIVACP Status DIV ACP 0 Stable 1 Status that
497. ly the restricted and fixed part of some SFR PL330 TRM shows detailed information of other parts and other SFRs SAMSUNG ELECTRONICS 8 12 ex 4412 UM 8 Direct Memory Access Controller DMAC 8 3 1 1 CC CC includes Base Address 0x1284 0000 MDMA e Base Address 0x1268 0000 0x1269 0000 1 e Address Base Address 0x0408 Reset Value 0x0080_0200 0 e Address Base Address 0x0428 Reset Value 0x0080_0200 CC 1 e Address Base Address 0x0448 Reset Value 0x0080 0200 2 e Address Base Address 0x0468 Reset Value 0x0080 0200 3 e Address Base Address 0x0488 Reset Value 0x0080_0200 CC 4 e Address Base Address 0x04A8 Reset Value 0x0080 0200 5 e Address Base Address 0x04C8 Reset Value 0x0080_0200 CC 6 e Address Base Address 0x04E8 Reset Value 0x0080_0200 CC 7 SAMSUNG ELECTRONICS 8 13 ex 4412 UM 8 Direct Memory Access Controller DMAC 8 4 Instruction Please refer to the PL330 TRM AMBA DMA Controller DMA 330 technical reference manua revision r1p0 from ARM 8 4 1 1 Security Scheme DMA_mem runs in both secure and non secure modes while DMA_peri runs in non secure mode only 8 4 1 2 Summary 1 You can configure the DMAC with up to eight DMA channels Each channel supports single concurrent thread of DMA operation Additionally there is a single DMA manager thread to initialize the DMA channel th
498. m Interval 9 Prescaler Value 1 Prescaler Value 255 TCNTBn 4294967295 1 1 PCLK 66 MHz 0 030 us 33 0 MHz 3 879 us 257 8 kHz 16659 27s 1 2 PCLK 66 MHz 0 061 us 16 5 MHz 7 758 us 128 9 kHz 33318 535 1 4 PCLK 66 MHz 0 121 8 25 15 515 us 64 5 kHz 66637 07 1 8 PCLK 66 MHz 0 242 us 4 13 MHz 31 03 us 32 2 kHz 133274 14s 1 16 PCLK 66 MHz 0 485 2 06 MHz 62 061 us 16 1 kHz 266548 275 SAMSUNG ELECTRONICS 11 5 ex 4412 UM 11 Pulse Width Modulation Timer 11 3 2 Basic Timer Operation Figure 11 3 illustrates the timer operations start bit 1 timer is started TCNTn TCMPn TCNTn TCMPn timer is stopped A TCMPBn 0 manual update 0 auto reload 1 Figure 11 3 Timer Operations The timer except the timer channel 4 includes four registers They are e TONTBn e TCNTn lt lt TCMPBn e CMPn If the timer reaches 0 then TCNTBn and registers are loaded into TCNTn TCMPn If TCNTn reaches 0 then the interrupt request occurs if it enables the interrupt TCNTn and TCMPn are the names of the internal registers lt reads the register from the register To generate interrupt at intervals 3cycle of XpwmTOUTn set TCNTBn TCMPBn and TCON register as shown in Figure 11 3 SAMSUNG ELECTRONICS 11 6 IT 4412 UM 11 Pulse Width Modulation Timer Steps to generate interrupt 1 2
499. m background image only in OSD area 1 If the pixel value matches background image with COLVAL then it displays the pixel from foreground image only in OSD area Each bit corresponds to COLVAL 23 0 If some position bit is set then it disables the position bit of COLVAL Controls color key Chroma key direction 0 If the pixel value matches foreground image with NOTE Set BLD PIX 1 ALPHA SEL 0 A FUNC 0x2 and B_FUNC 0x3 to enable alpha blending using color key SAMSUNG ELECTRONICS 16 97 x 4412 UM 16 Display Controller 16 5 3 39 W1KEYCON1 e Base Address 0x11C0_0000 e Address Base Address 0x0144 Reset Value 0x0000_0000 COLVAL_F 23 0 Specifies color key value for transparent pixel effect 0 16 5 3 40 W2KEYCONO e Base Address 0x11C0_0000 e Address Base Address 0x0148 Reset Value 0x0000_0000 Enables blending 0 Disables blending RW 26 1 Enables blending using original alpha for area and KEY_ALPHA for key area Enables color key Chroma key KEYEN_F 25 RW 0 Disables color key 1 Enables color key Controls color key Chroma key direction 0 If the pixel value matches foreground image with then it displays the pixel from background image DIRCON F 24 RW only in OSD area 1 If the pixel value matches background image with then it displays the pixel from foreground image only in OSD area Each bit corre
500. mmand write only a NOTE Only when TRGMODE WABUF is set to 1 TRGMODE Specifies 4 double buffer trigger 25 RW 0 Disables trigger _W4BUF 1 Enables trigger 85 0 SWTRGCMD Specifies Window 3 double buffer trigger W3BUF 21 RW 1 Enables Software Trigger Command write only T NOTE Only when TRGMODE WB3BUF is set to 1 TRGMODE Species Window 3 double buffer trigger 20 RW 0 Disables trigger _W3BUF 1 Enables trigger 86 0 CI eee SWTRGCMD Specifies Window 2 double buffer trigger W2BUF 16 RW 1 Enables Software Trigger Command write only T NOTE Only when TRGMODE W2BUF is set to 1 TRGMODE Window 2 double buffer trigger 15 RW 0 Disables trigger _W2BUF 1 Enables trigger RSVD 14 12 Reseved AA SWTRGCMD Specifies Window 1 double buffer trigger W1BUF 11 RW 1 Enables Software Trigger Command write only zm NOTE Only when TRGMODE W1BUF is set to 1 TRGMODE Specifies 1 double buffer trigger 10 RW 0 Disables trigger _W1BUF 1 Enables trigger mvo Specifies Window 0 double buffer trigger pur RW 1 Enables Software Trigger Command write only B NOTE Only when TRGMODE WOBUF is set to 1 TRGMODE nO 0 double buffer trigger UF 5 RW 0 Disables trigger 1 Enables trigger ASVD wal SOS SWFRSTATUS Specifies Frame Done Status read only 180 start SAMSUNG ELECTRONICS 16 10
501. n any consequential or incidental damages Customers are responsible for their own products and applications Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use in applications intended to support or sustain life or for any other application in which the failure of the Samsung product could reasonably be expected to create a situation where personal injury or death may occur Customers acknowledge and agree that they are solely responsible to meet all other legal and regulatory requirements regarding their applications using Samsung products notwithstanding Copyright O 2012 Samsung Electronics Co Ltd Samsung Electronics Co Ltd San 24 Nongseo Dong Giheung Gu Yongin City Gyeonggi Do Korea 446 711 Contact Us bach1004 samsung com Home Page http www samsungsemi com SAMSUNG ELECTRONICS any information provided in this publication Customer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim including but not limited to personal injury or death that may be associated with such unintended unauthorized and or illegal use
502. n codes to generate Oxff ECC parity codes for all Oxff data This setting allows ECC module to detect errors on a free page ECC parity codes are e 28 bit ECC Code 22 bit Line 6 bit Column e 10 bit ECC Code 4 bit Line parity 6 bit Column Each 1 4 8 12 16 bit ECC module guarantees up to 1 4 8 12 16 bit errors respectively If the errors cross the number of guaranteed errors it cannot guarantee the result 10 4 3 2048 Byte 1 bit ECC Parity Code Assignment Table and 10 4 4 32 Byte 1 bit ECC Parity Code Assignment Table describes 1 bit ECC parity code assignment SAMSUNG ELECTRONICS 10 5 ex 4412 UM 10 NAND Flash Controller 10 4 3 2048 Byte 1 bit ECC Parity Code Assignment Table omm omm DATAS paras DATA3 DATA DATO mecano Pes Pes Pa Poe P16 Pro Pe Pe 10 4 4 32 Byte 1 bit ECC Parity Code Assignment Table bara DATAS DATAS pata DATAS DATA2 pata Datao SECCn o 2 P P1 Pr Pie P P8 SES 10 4 5 1 bit ECC Module Features The ECC Lock MainECCLock and SpareECCLock bit of the control register generates the 1 bit ECC If ECCLock is low the hardware ECC modules generate the ECC codes 1 bit ECC Register Configuration The NAND Flash Memory interface table describes the configuration of 1 bit ECC value read from spare area of external NAND flash memory The
503. n mode configuration register GPJ1CONPDN 0x0270 Port group GPJ1 power down mode configuration register 0 0000 EXT_INT21_CON 0x0740 External interrupt EXT_INT21 configuration register 0x0000_0000 SAMSUNG ELECTRONICS 4 7 4412 UM 4 General Purpose Input Output GPIO Control EXT_INT5_FLTCONO 0x0820 External interrupt EXT_INT5 filter configuration register 0 0x0000_0000 EXT INT5 FLTCON1 0x0824 External interrupt 5 filter configuration register 1 0x0000 0000 EXT INT6 FLTCONO 0x0828 External interrupt EXT 6 filter configuration register 0 0x0000 0000 EXT INT6 FLTCON1 0 082 External interrupt 6 filter configuration register 1 0x0000_0000 EXT INT7 FLTCONO 0x0830 External interrupt EXT INT filter configuration register 0 0x0000 0000 EXT INT7 FLTCON 1 0x0834 External interrupt EXT INT filter configuration register 1 0x0000 0000 EXT INT13 FLTCONO 0x0860 External interrupt EXT INT13 filter configuration register O 0x0000 0000 EXT INT13 FLTGONI 0x0864 0x0000 0000 EXT INT14 FLTCONO 0x0868 External interrupt EXT INT14 filter configuration register 0 0x0000 0000 0x0864 External interrupt EXT INT13 filter configuration register 1 EXT INT14 1 0x086C External interrupt EXT INT14 filter configuration register 1 0x0000 0000 EXT INT15 FLTCONO 0x0870 External interrupt EXT INT15 filter configuration register 0 0x0000 0000 EXT INT15 FLTCO
504. n when the reaches 0 The value written to 15 loaded to if the reaches to 0 and auto reload is enabled If the TCNTn is 0 and the auto reload bit is 0 then TCNTn does not operate further Figure 11 4 illustrates the example of double buffering feature Write TCNTBn 100 Write Start TCNTBn 200 TCNTBn 150 auto_reload interrupt Figure 11 4 Example of Double Buffering Feature SAMSUNG ELECTRONICS 11 8 ex 4412 UM 11 Pulse Width Modulation Timer 11 3 4 Timer Operation Example Figure 11 5 illustrates the example of a timer operation Figure 11 5 Example of a Timer Operation Steps to use PWM as a timer 1 2 1Enable the auto reload feature Set the TCNTBn as 159 50 109 and TCMPBn as 109 Set the manual update bit On and set the manual update bit Off Set the inverter On Off bit The manual update bit sets TCNTn and TCMPn to the value TCNTBn and TCMPBn Set and TCMPBn as 79 40 39 and 39 Start Timer Set the start bit in TCON If TCNTn and TCMPn have the same value then it changes the logic level of TOUTn from low to high When TCNTn reaches 0 it generates interrupt request It automatically reloads TCNTn and TCMPn with TCNTBn and TCMPBn as 79 40 39 and 39 In the Interrupt Service Routine ISR the and TCMPBn are set as 79 20 59 and 59 IFTCNTn and TCMPn have the same value then it c
505. nable bit does not PARITYFAIL2 20 CREN affect this pending status OPU PETIR 2 LS 0 The interrupt is not pending EE __ o O __ __ __ E o MESE NEN EE EN __ CPU_PMUIRQ_2 18 1 The interrupt is pending RSVD 17 05 MCT L1 16 er s 8 meo a EM sne ro a 9 SYSMMU FIMC 11 0 The interrupt is not pending Wr SYSMMU FIMC ISP 1 10 1 The interrupt is pending Ooo SYSMMU_FIMC_LITEO 1 SYSMMU_FIMC_LITEO 1 __ po Mp NE HN __ __ NEM mere mr fej SYSMMU ISP CX0 51 Interrupt pending status vom meri eratio on nai SYSMMU_FIMC_DRC O 8 0 The interrupt is not pending SYSMMU FIMC ISP 2 1 The interrupt is pending svswwu FIMG LITEOOL ni R svewwu FIMO 01 R SAMSUNG ELECTRONICS 7 28 4412 UM 7 Interrupt Combiner 7 6 2 20 IMSR4 e Base Address 0x1044 0000 e Address Base Address 0x004C Reset Value Undefined RSVD 31 CPU nIRQOUT 3 80 R PARITYFAILSCU3 29 Masked interrupt pending status PARITYFAIL3 28 If the corresponding interrupt enable bit is 0 the IMSR bit reads as 0 Ore 27 R 0 The interrupt is not pending CPU PMUIRA 3 26 1 The interrupt is pending RSVD
506. nd logic immediately ENWIN_F RW Disables the video output and video control signal 1 Enables the video output and video control signal SAMSUNG ELECTRONICS 16 80 ex 4412 UM 16 Display Controller 16 5 3 14 SHADOWCON e Base Address 0x11C0_0000 e Address Base Address 0x0034 Reset Value 0x0000_0000 Reserved NOTE This bit should be set to O Protects to update window 4 s shadow register xxx_F W4 SHADOW 0 Updates shadow register per frame _ 1 Protects to update updates shadow register at next frame after SHADOW_PROTECT turns to be 1 b0 Protects to update window 3 s shadow register xxx_F W3_SHADOW 0 Updates shadow register per frame _PROTECT 1 Protects to update updates shadow register at next frame after SHADOW_PROTECT turns to be 1 b0 Protects to update window 2 s shadow register xxx_F W2_SHADOW 0 Updates shadow register per frame _PROTECT 1 Protects to update updates shadow register at next frame after SHADOW_PROTECT turns to be 1 b0 Protects to update window 1 s shadow register xxx_F W1_SHADOW 0 Updates shadow register per frame _ 1 Protects to update update shadow register at next frame after SHADOW_PROTECT turns to be 1 b0 Protects to update window 0 5 shadow register xxx_F WO SHADOW 0 Updates shadow register per frame _ 1 Protects to update update shadow register at next frame after SHADOW_PROTECT t
507. neral Purpose Input Output GPIO Control 4 3 2 13 GPBCON e Base Address 0x1140_0000 e Address Base Address 0x0040 Reset Value 0x0000_0000 0 0 Input 0 1 Output GPBCON 7 31 28 RW 0 2 SPI 1 MOSI 0 00 0x3 to Reserved OxF EXT_INT3 7 GPBCONI 5 GPBCONJ 4 2 0 0 Input 0 1 Output 0 2 SPI_1_MISO 0 00 0 3 to Reserved OxF EXT INT3 6 0 0 Input 0 1 Output 0 2 SPI 1 nSS 0x3 Reserved 0 00 0 4 IEM_SPWI 0 5 to OxE Reserved OxF EXT_INT3 5 0 0 Input 0 1 Output 0 2 SPI_1_CLK 0 3 Reserved 0x00 0 4 IEM_SCLK 0 5 to OxE Reserved OxF EXT_INT3 4 0 0 Input 0 1 Output 0 2 SPI 0 MOSI 0x3 I2G 5 SCL anne 0x4 to OxE Reserved OxF EXT_INT3 3 0x0 Input 0 1 Output 0 2 SPI 0 MISO 0x3 I2C 5 SDA oe 0 4 to Reserved OxF EXT_INT3 2 0x0 Input 0x1 Output 0 2 SPI 0 nSS GPBCON 1 7 4 0x3 120 4 SCL 0x00 0x4 to OxE Reserved OxF EXT_INT3 1 0 0 Input SAMSUNG ELECTRONICS 4 27 ex GPBCON 3 GPBCON 2 2 2 2 2 4412 UM 4 General Purpose Input Output GPIO Control 0 2 SPI 0 0x3 126 4 SDA 0 4 to Reserved OxF EXT_INT3 0 SAMSUNG ELECTRONICS 4 28 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 14 GPBDAT e Base Address 0x1140 0000 e Address Base Address 00044 Reset Value 0x00
508. nfigurable Features During implementation of the features that depend on the configuration are e Exynos 4412 GIC Configuration e Total 160 interrupts including Software Generated Interrupts SGls Private Peripheral Interrupts PPIs and Shared Peripheral Interrupts 5 15 are supported e For SPI you can service maximal 32 x 4 128 interrupt requests Table 6 1 describes the GIC configuration values Table 6 1 Configuration Values Configuration Values 1 eg cx 0 ppi cx 5 edge ppi cx 6 ppi cx 10 level ppi cx 11 edge ppi cx 12 level ppi cx 13 ppi cx 14 edge ppi cx 15 level PPI Registering Synchronized for all PPI SPI Registering Synchronized for all SPI PPI sensitivity SAMSUNG ELECTRONICS 6 3 ex 4412 UM 6 Interrupt Controller 6 3 Interrupt Source This section includes e Interrupt source connection e GIC interrupt table 6 3 1 Interrupt Sources Connection Figure 6 1 illustrates the interrupt sources connection ARM Core GIC PL390 AXI IF for AXI IF for Distri CPU IF Non Combined Interrupt Core_SFR Interconnections uc N a 7 2 5 3 IF for Non Combined m Combined Interrupt INT COMBINER Interrupt 127 32 Non Combined Interrupt Figure 6 1 Interrupt Sources Connection GIC interrupt s
509. ng edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0 5 to 0x7 Reserved ASVO Eq pf 9 Sets signaling method of EXT INT42 5 0 0 Low level 0 1 High level EXT INT42 CON 5 22 20 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0x5 to 0x7 Reserved 85 0 Sets signaling method of EXT INT42 4 0 0 Low level 0 1 High level EXT 42 CON 4 18 16 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0 5 to 0 7 Reserved 85 9 mp mew ov Sets signaling method of EXT INT42 3 0 0 Low level 0 1 High level EXT INT42 CON 3 14 12 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0 5 to 0 7 Reserved mw mw SAMSUNG ELECTRONICS 4 268 ITT 4412 UM 4 General Purpose Input Output GPIO Control Sets signaling method of EXT_INT42 2 0 0 Low level 0x1 High level EXT_INT42_CON 2 10 8 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT42 1 0 0 Low level 0x1 High level EXT_INT42_CON 1 6 4 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT42 0 0 0 Low level 0x1 High level EXT INT42 CON 0 2 0 RW 0x2 Triggers Falling edg
510. nput 0 1 Output GPV3CON 1 7 4 0 2 C2C TXD 9 0 00 0x3 to Reserved OxF EXT_INT33 1 0 0 Input 0 1 Output GPV3CON 0 3 0 0 2 C2C_TXDI 8 0x3 to OxE Reserved OxF EXT INT33 0 SAMSUNG ELECTRONICS 4 308 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 22 GPV3DAT Base Address Ox106E 0000 e Address Base Address 0x0084 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPV3DAT 7 0 7 0 output port then pin state should be same as 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 5 23 GPV3PUD Base Address 0x106E_0000 e Address Base Address 0x0088 Reset Value 0x5555 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down GPV3PUDIn n201o7 RW x Reserved 0x5555 0x3 Enables Pull up 4 3 5 24 GPV3DRV e Base Address 0x106E_0000 e Address Base Address 0x008C Reset Value 0x00_0000 23 16 Reserved Should be zero W GPV3DRVIn n 2n 1 2 0x0000 0107 SAMSUNG ELECTRONICS 4 309 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 25 GPV3CONPDN Base Address 0x106E_0000 e Address Base Address 0x0090 Reset 0x0000 0x0 Outputs O 2n 1 2n 0 1 Outputs 1 0107 RW 0 2 Input 2599 0 3 Previous st
511. nterrupt pending status If the SYSMMU_FIMC2 0 ij enable bitis 0 the IMSR E o SYSMMU_FIMC1 0 8 0 The interrupt pending __ SYSMMU_FIMCO O 21 R 1 The interrupt is pending svewwusssp ___ R Eo SYSMMU moma Ca 27 SAMSUNG ELECTRONICS 7 17 4412 UM 7 Interrupt Combiner 7 6 2 9 IESR2 e Base Address 0x1044 0000 e Address Base Address 0x0020 Reset Value 0 0000 0000 RSVD reserved LCDO 3 27 Sets the corresponding interrupt enable bit to 1 LCDOr2 26 RW you set the interrupt enable bit interrupt combiner tobo RW mo interrupt request LCDO 1 25 Write 0 Does not change the current setting 1 Sets the interrupt enable bit to 1 Ea WA 1 Enables DMC1_PPC_PEREV_M 23 DMC1_PPC_PEREV_A 22 Set the corresponding interrupt enable bit to 1 If oS o r you set the interrupt enable bit interrupt combiner DMCO PPC PEREV M 21 serves the interrupt request DMCO PPC PEREV A 20 RW Write 0 Does not change the current setting 19 1 Sets the interrupt enable bit to 1 Read The current interrupt enable bit L2CACHE 1 RW L2CACHE i8 RW D MESS RP TIMER 17 1 Enables GPIO_AUDIO 16 85 0 Reewd 207 PPMUL MPO MI 14 Sets the corresponding interrupt enable bit to 1 AA PPMU_MFC_MO 13 If you set the interrupt
512. ntroller 16 3 3 2 12 4 BPP Display Palette Figure 16 17 illustrates the 4 BPP display BYSWP 0 HWSWP 0 WSWP 0 D 63 60 D 59 56 D 55 52 D 51 48 D 47 44 D 43 40 D 39 36 D 35 32 000H P1 P2 P3 P4 P5 P6 P7 8 008H P17 P18 P19 P20 21 22 23 24 D 31 28 _D 27 24 0123 20 1916 15121 D 11 8 P9 P10 P11 P12 P13 P14 P25 P26 P27 P28 P29 P30 BYSWP 1 HWSWR 0 WSWP 0 D 63 60 D 59 56 D 55 52 D 51 48 D 47 44 D 43 40 000H P15 P16 P13 P14 P11 P12 008H P31 P32 P29 P30 P27 P28 D 27 24 D 19 18 D 15 12 P8 P6 P3 P 24 P22 P19 Figure 16 17 Memory Format of 4 BPP Display NOTE AEN Specifies the transparency value selection bit with WPALCON Palette output format AEN 0 Selects ALPHAO AEN 1 Selects ALPHA When it sets per pixel blending then this pixel blends with alpha value that AEN selects SFR selects the alpha value as ALPHAO ALPHAO ALPHAO B ALPHA1 ALPHA1 G ALPHA1 For more information refer to the section on SFR SAMSUNG ELECTRONICS 16 21 ex 4412 UM 16 Display Controller 16 3 3 2 13 2 BPP Display Palette Figure 16 18 illustrates the 2 BPP display Figure 16 18 Memory Format of 2 BPP Display NOTE A
513. ntry palette data Undefined SAMSUNG ELECTRONICS 16 56 ex 4412 UM 16 Display Controller 16 5 3 Control Register 16 5 3 1 VIDCONO e Base Address 0x11C0_0000 e Address Base Address 0x0000 Reset Value 0x0000_0000 Reserved RSVD 81 ES NOTE This bit should be set to 0 Enables DSI 05 EN 30 RW 0 Disables 1 Enables 180 24 bit data interface SYS ADD 1 Reserve b 23 NOTE This bit should be set to 0 Determines output format of Video Controller 000 RGB interface 001 Reserved 010 Indirect 80 interface for LDIO VIDOUT 28 26 RW 011 Indirect i80 interface for LDI1 100 Write Back interface and RGB interface 101 Reserved 110 WB Interface and 80 interface for LDIO 111 WB Interface and i80 interface for LDI1 Selects output data format mode of indirect 180 interface LDIO VIDOUT 1 0 2 b10 000 16 bit mode 16 BPP LO DATA16 22 20 RW 001 16 2 bit mode 18 010 9 9 bit mode 18 BPP 011 16 8 bit mode 24 BPP 100 18 bit mode 18 BPP 101 8 8 bit mode 16 BPP Reserved HEVD 19 ES NOTE This bit should be set to 0 Selects display mode VIDOUT 1 0 2 b00 0 RGB parallel format HA PSEL 18 i 1 RGB serial format Selects the display mode VIDOUT 1 0 2 b00 SAMSUNG ELECTRONICS 16 57 Selects output data format mode of indirect i80 interface LDI1 VIDOUT 1 0 2 b11 000 16 bit mod
514. o OxE Reserved EXT INT10 4 0 0 Input 0 1 Output 0 2 GPIO 0 GPM2CON 3 15 12 RW 0x3 MPWM1 OUT ISP 0x00 0 4 to OxE Reserved OxF EXT INT10 3 0 0 Input 0 1 Output 0 2 Reserved 0 3 CLKOUT 2 11 GPMSGONIS regl 0x4 Reserved ar 0 5 TraceData 15 0 6 to Reserved OxF EXT_INT10 2 GPM2CON 1 0 0 Input 0 1 Output 0 2 Reserved 0 3 VSYNC GPM2CON 0 3 0 RW 0 4 Reserved 0 00 0 5 TraceData 13 0 6 to Reserved OxF EXT INT10 0 SAMSUNG ELECTRONICS 4 181 ex 0 0 Input 0 1 Output 0x2 Reserved 0x3 CAM HREF dude 0x4 Reserved px 0 5 TraceData 14 0x6 to OxE Reserved OxF EXT_INT10 1 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 102 GPM2DAT Base Address 0x1100 0000 e Address Base Address 0x02A4 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPM2DAT 4 0 4 0 output port then pin state should be same as 0x00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 3 103 GPM2PUD e Base Address 0 1100_0000 e Address Base Address 0x02A8 Reset Value 0x0155 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down GPM2PUD n Oto 4 RW 0x2 Reserved 0x0155 0x3 Enables Pull up 4 3 3
515. ock Diagram of the 16 7 Memory Format of 25 BPP A888 Display 16 8 Memory Format of 32 BPP 8888 Display sse eene u uu 16 9 Memory Format of 24 BPP A887 16 10 Memory Format of 24 BPP 888 nennen 16 11 Memory Format of 19 BPP A666 16 12 Memory Format of 18 BPP 666 16 13 Memory Format of 16 BPP A555 Display 16 14 Memory Format of 16 BPP 1555 emen 16 15 Memory Format 16 BPP 565 nennen 16 16 16 BPP 5 6 5 Display u qI reiten entro rectae 16 17 Memory Format of 13 BPP A444 nenne 16 18 Memory Format of 8 BPP A232 Display nennen 16 19 Memory Format of 8 BPP 16 20 Memory Format of 4 BPP nennen eren eren 16 21 Memory Format of 2 BPP 16 22 32 BPP 8 8 8 8 Palette Data 16 23 25 BPP 8 8 8 Palette Data 16 24 19 BPP 6 6 6 Palette Data 4 4 16 24 16 BPP 5 5 5 Palette Data Format 16 25 Blending 16 28 Blending DI8gram
516. ock gating for ISP registert OxFFFF FFFF SAMSUNG ELECTRONICS 5 33 4412 UM 5 Clock Management Unit 0x8808 to CLKOUT CMU ISP 0x8A00 CLKOUT control register 0x0001 0000 0x8A04 Clock divider status for CLKOUT 0x0000_0000 The six address spaces that SFRs fall into are SFRs with address 0x0_4000 to 0x0 7FFF These special function registers control clock related logics for LEFTBUS block They control clock source selection clock divider ratio and clock gating SFRs with address 0x0_8000 to 0x0_BFFF These special function registers control clock related logics for RIGHTBUS block They control clock source selection clock divider ratio and clock gating SFRs with address 0 0 C000 to 0x0 FFFF These special function registers control clock related logics for MFC G3D TV LCD ISP CAM FSYS PERIL and PERIR blocks They control EPLL and VPLL clock source selection clock divider ratio and clock gating SFRs with address 0x1_0000 to 0x1_3FFF These special function registers control clock related logics for DMC block They control MPLL clock source selection clock divider ratio and clock gating SFRs with address 0x1_4000 to 0x1_7FFF These special function registers control clock related logics for CPU block They control APLL clock source selection clock divider ratio and CPU related logics SFRs with address 0x1_8000 to 0x1_BFFF These special function registers control clock related logics for IS
517. ode Set SFR PACKET CNT REG to receive any number of packets SPI stops generating SPICLK if the number of packets is similar to PACKET CNT REG The size of one packet depends on channel width One packet is one byte when you configure channel width as byte and one packet is four bytes when you configure channel width as word It is mandatory to follow software or hardware reset before reloading this function Software reset can clear all registers except special function registers but hardware reset clears all registers SAMSUNG ELECTRONICS 15 2 ex 4412 UM 15 Serial Peripheral Interface 15 2 1 5 Chip Select Control Chip select XspiCS is active low signal In other words a chip is selected when XspiCS input is 0 You can control KspiCS automatically or manually No need to change When you use manual control mode you should clear AUTO_N_MANUAL default value is 0 NSSOUT bit controls XspiCS level When you use auto control mode AUTO N MANUAL must be set as 1 XspiCS toggled between packet and packet automatically NCS TIME COUNT controls inactive period of XspiCS NSSOUT is not available at this time 15 2 1 6 High Speed Operation as Slave Exynos 4412 SPI supports Tx Rx operations up to 50 MHz but there is a limitation When Exynos 4412 SPI works as a slave it consumes large delay more than 15 ns in worst operating condition Such a large delay can cause setup violation at SPI master device To overcome the prob
518. oftware mode read this register when you need to 0x00 read 3 ECC value flash memory This register has the similar Read function as NFDATA 10 7 2 8 NFSECCD e Base Address OXOCEO 0000 e Address Base Address 0x001C Reset Value FFFF mw era mem 9 27 ECC SECCData1 23 16 RW NOTE In software mode read this register when you need OxFF to read 2 ECC value flash memory av me 1 ECC NOTE In software mode read this register when you need ECCD 7 RW FF 7 0 to read 1 ECC value from flash memory This register dis has the similar Read function as NFDATA NOTE It allows only word access SAMSUNG ELECTRONICS 10 21 ex 4412 UM 10 NAND Flash Controller 10 7 2 9 NFSBLK e Base Address OXOCEO 0000 e Address Base Address 0x0020 Reset Value 0x0000 0000 ASVD 8124 Reewd SBLK ADDR2 23 16 The 3 block address of the block erase operation ADDR1 15 8 The 27 block address of the block erase operation The 1 block address of the block erase operation SBLK ADDRO 70 Only bit 7 5 are valid NOTE Address of Advance Flash block starts from 3 address cycle So block address register only requires 3 bytes Refer to 10 4 12 Lock Scheme for Data Protection for more information on lock scheme 10 7 2 10 NFEBLK e Base Address OXOCEO 0000 e Address Bas
519. ol 4 3 2 8 GPA1DAT e Base Address 0x1140_0000 e Address Base Address 0x0024 Reset Value 0 00 RWX When you configure port as input port then corresponding bit is the pin state When configuring as GPA1DAT 5 0 5 0 output port the pin state should be same as the 0x00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 2 9 GPA1PUD Base Address 0x1140 0000 e Address Base Address 0x0028 Reset Value 0x0555 0 0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down GPA1PUDIn 0105 RW 0x2 Reserved 0x0555 0x3 Enables Pull up 4 3 2 10 GPA1DRV e Base Address 0x1140_0000 e Address Base Address 0x002C Reset Value 0x00_ 0000 23 16 Reserved Should be zero W GPA1DRV n n 2n 1 21 R 0x0000 0105 SAMSUNG ELECTRONICS 4 25 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 11 GPA1CONPDN e Base Address 0x1140_0000 e Address Base Address 0x0030 Reset Value 0x0000 0x0 Outputs O 2n 1 2n 0x1 Outputs 1 SPAIN 0105 FW Input 552 0 3 Previous state 4 3 2 12 GPA1PUDPDN Base Address 0x1140_0000 e Address Base Address 0x0034 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down RO 0105 di 0x2 Reserved 990 0x3 Enables Pull up SAMSUNG ELECTRONICS 4 26 ex 4412 UM 4 Ge
520. on Color Key Chroma Key 4412 UM 16 Display Controller Supports gamma control Image Enhancement Supports hue control Supports color gain control Video Clock Source SCLK_FIMDO for display controller from CMU module Maximum VCLK in RGB Interface Display Controller 80 MHz SAMSUNG ELECTRONICS 16 3 ex 4412 UM 16 Display Controller 16 3 Functional Description The functional description section describes the functionality of display controller 16 3 1 Brief Description The display controller consists of a VSFR VDMA VPRCS VTIME and video clock generator To configure the display controller the VSFR has e 121 programmable register sets e gamma LUT register set 64 registers e one 180 command register set 12 registers e five 256 x 32 palette memories VDMA is dedicated display that transfers video data in frame memory to VPRCS By using this special DMA you can display video data on screen without CPU intervention VPRCS receives video data from VDMA and sends it to display device LCD through data ports RGB VD or SYS VD after changing the video data into a suitable data format for example 8 bit per pixel mode 8 BPP mode or 16 bit per pixel mode 16 BPP mode VTIME consists of programmable logic to support the variable requirement of interface timing and rates commonly found in different LCD drivers The VTIME block generates RGB VSYNG RGB HSYNG RGB VCLK RGB
521. on sleep mode but in off part it is not same Therefore registers in alive part keep their values during sleep mode Figure 4 1 illustrates the block diagram of GPIO Register File APB Bus APB Interface Async Interface Register File Pad control Mux control External Interrupt Interrupt Control Controller Pad control Mux control Interrupt Controller amp Wake up controller External Interrupt Control Alive Part Figure 4 1 SAMSUNG ELECTRONICS 4 4 GPIO Block Diagram 4412 UM 4 General Purpose Input Output GPIO Control 4 3 Register Description 4 3 1 Registers Summary Base Address 0x1140 0000 Por group power down mode configuration register GPAOCONPDN 0x0010 Port group GPAO power down mode configuration register 0x0000 GPAOPUDPDN 0 0014 2 power down mode pull up pull down 0 0000 Register GPA1PUDPDN 0x0034 4 GPA1 power down mode pull up pull down 0 0000 GPBPUDPDN 0x0054 2 power down mode pull up pull down 0 0000 Por group GPC0 power down mode configuration register GPCOCONPDN 0x0070 Port group GPCO power down mode configuration register 0x0000 GPCOPUDPDN 0x0074 GPCO power down mode pull up pull down 0 0000 GPBCON 0x0040 Port group GPB configuration register 0x0000_0000 SAMSUNG ELECTRONICS 4 5 4412 UM 4 General Purpose Input Output GPIO Control A GPDOPUDPDN 0x00B4 2 GPDO power
522. ontrol bit BYTSWP F 17 0 Disables swap 1 Enables swap NOTE Set it to 0 when ENLOCAL is 1 Specifies Half Word swap control bit HAWSWP F 16 RW 0 Disables swap 1 Enables swap NOTE Set it to 0 0 when ENLOCAL is 1 Specifies Word swap control bit WSWP F 15 BW 0 Disables swap 1 Enables swap NOTE Set it to 0 when ENLOCAL is 1 Selects auto buffering mode BUF MODE 0 Double 1 Triple Specifies input color space of source image only for EnLcal enable INRGB x 0 RGB 1 YCbCr Reserved NOTE This bit should be set to 0 Selects the DMA s Burst Maximum Length 00 16 word burst BURSTLEN 10 RW URS 10 31 01 8 word burst 10 4 word burst RSVD NES Reserved should be 0 9 Specifies Multiplied Alpha value mode 0 Disables multiplied mode 1 Enables multiplied mode When ALPHA_MUL is 1 set BLD PIX 1 sd RW ALPHA SEL 1 and BPPMODE F 5 2 4101101 or 4 b1110 NOTE Alpha value alpha_pixel from data x ALPHAO R G B Selects blending category BLD PIX F RW 0 Per plane blending 1 Per pixel blending Selects Bits Per Pixel BPP mode in Window image 0000 1 BPP BPPMODE F 5 2 RW 0001 2 BPP 0010 4 BPP 0011 8 BPP i SAMSUNG ELECTRONICS 16 73 II 4412 UM 16 Display Controller 0100 8 BPP non palletized A 1 R 2 G 3 B 2 0101 16 BPP non palletized R 5 G 6 B 5 0110 16 BPP non palletized A 1 R 5 G 5 B 5 0111 16 BPP non p
523. ontrols MUKG3D 0 0 SCLKMPLL G3D 0 SEL RW 1 SCLKAPLL MUXG3D_0 is the source clock of G3D core SAMSUNG ELECTRONICS 5 60 ex 4412 UM 5 Clock Management Unit 5 10 1 31 CLK SRC LCDO Base Address 0x1003 0000 e Address Base Address 0xC234 Reset Value 0x0000_1111 Controls 0000 0001 XusbXTI 0010 SCLK HDMI24M 0011 SCLK USBPHYO MIPIO SEL 15 12 0101 SCLK_HDMIPHY 0110 SCLKMPLL_USER_T 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved MUXMIPIO is the source clock of DSIMO Controls MUXMDNIE PWMO 0000 XXTI 0001 XusbXTI 0010 SCLK HDMI24M 0011 SCLK USBPHYO MDNIE PWMO 0101 SCLK_HDMIPHY _SEL 0110 SCLKMPLL USER 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved MUXMDNIE PWMO is the source clock of MDNIE PWMO Controls MUXMDNIEO 0000 XXTI 0001 XusbXTI 0010 SCLK HDMI24M 0011 USBPHYO MDNIEO SEL 0101 SCLK_HDMIPHY 0110 SCLKMPLL_USER_T 0111 SCLKEPLL 1000 SCLKVPLL Others Reserved is the source clock of MDNIEO Controls MUXFIMDO 0000 0001 XusbXTI FIMDO SEL 0010 SCLK HDMI24M 0011 USBPHYO 0101 SCLK HDMIPHY 0110 SCLKMPLL USER 0111 SCLKEPLL SAMSUNG ELECTRONICS 5 61 4412 UM 5 Clock Management Unit 1000 SCLKVPLL Others Reserved MUXFIMDO is the source clock of FIMDO SAMSUNG ELECTRONICS 5 62 ex 4412 U
524. or MIPIHSI CLK_MIPIHSI 10 RW 0 Mask CLK SDMMC4 SDMMC3 CLK SDMMC2 SDMMC1 SDMMCO SAMSUNG ELECTRONICS 5 114 ex 4412 UM 5 Clock Management Unit Reserved Gating all clocks for 1 CLK_PDMA1 1 RW 0 Mask 1 Pass Gating all clocks for CLK PDMAO RW 0 Mask 1 Pass SAMSUNG ELECTRONICS 5 115 IT 4412 UM 5 Clock Management Unit 5 10 1 99 CLK GATE IP GPS e Base Address 0x1003 0000 e Address Base Address 0xC94C Reset Value OxFFFF_FFFF Gating all clocks for PPMUGPS CLK PPMUGPS 0 Mask 1 Pass Gating clocks for SMMUGPS CLK_SMMUGPS 0 Mask 0 1 1 Pass Gating all clocks for GPS CLK GPS 0 Mask 0 1 1 Pass SAMSUNG ELECTRONICS 5 116 IT 4412 UM 5 Clock Management Unit 5 10 1 100 GATE PERIL e Base Address 0x1003 0000 e Address Base Address 950 Reset Value OxFFFF_FFFF Gating all clocks for AC97 0 Mask 1 Pass Gating clocks for SPDIF 0 Mask 1 Pass RSVD 31 28 Gating all clocks for Slimbus 0 Mask 1 Pass Gating all clocks for PWM 0 Mask 1 Pass Gating all clocks for 2 0 Mask 1 Pass D CLK SPIO 16 1 Pass 85 0 D Gating all clocks for I2CHDMI CLK I2CHDMI 14 R 0 Mask 1 Pass SAMSUNG ELECTRONICS 5 117 Gating all clocks 1251 0 Mask 1 Pass Reserved Gating all clocks for SPI2 0 Ma
525. ort is the input port in Master mode You can use SPI 0 MISO input mode to get data from slave output port It transmits XspiMISO 0 SPI 1 MISO In Out data to master through this port in slave mode XspiMISO 1 muxed SPI 2 MISO Out when used as slave Xi2s2SDI In when used as master This port is the output port in Master mode It uses this SPI 0 MOSI port to transfer data from master output port It receives XspiMOSI 0 SPI 1 MOSI In Out data from master through this port in slave mode XspiMOSI 1 muxed SPI 2 MOSI Out when used as master Xi2s2SDO In when used as slave NOTE Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals SAMSUNG ELECTRONICS 15 6 ex 4412 UM 15 Serial Peripheral Interface 15 5 Register Description 15 5 1 Register Map Summary e Base Address 0x1392 0000 e Base Address 0x1393_0000 Base Address 0x1394 0000 Resistor Reset Value Setting Sequence of Special Function Register Steps to set Special Function Register nCS manual mode are 1 Set Transfer Type CPOL and CPHA set 2 Set Feedback Clock Selection register 3 Set SPI MODE CFG register 4 Set SPI INT EN register 5 Set PACKET CNT REG register if necessary 6 Set Tx or Rx Channel on 7 Set nSSout low to start Tx or Rx operation a Set nSSout Bit to low then start Tx data writing b When auto chip selection bit is set nSSout i
526. os 4412 The six CMUs in Exynos 4412 contain the CLKOUT control logic If necessary you can select and divide one of the clocks in the CMU generates CLKOUT signal from each CMU and feeds this into the power management unit lt is then muxed with CLKOUT signals and KKTI XUSBXTI RTC_TICK_SRC and RTCCLK Figure 5 3 illustrates the CLKOUT control logic in Exynos 4412 CMU DMC CMU TOP DIV 1 64 CMU_LEFTBUS XCLKOUT CMU_RIGHTBUS CMU_CPU CMU_ISP DIV 1 64 gt XUSBXTI gt RTC TICK SRC gt RTCCLK gt Figure 5 3 Exynos 4412 CLKOUT Control Logic SAMSUNG ELECTRONICS 5 20 ex 4412 UM 5 Clock Management Unit Table 5 7 describes the CLKOUT input clock selection information Table 5 7 CLKOUT Input Clock Selection Information No ceu omu TOP RIGHTS omu LEETBUS _ Pwu fe muon gg _ DEE MPWM_ISP See 8 E s TES me e ERN qa A aW MN 100 1 SCLK G3D G3D 400 _ MCUISP alo OQ O CAM A PCLK _ _ PCLK S RKBYTE CLKHSO 2L S RXBYTE METERS TT 4L SAMSUNG ELECTRONICS 5 21 Lm o m 4412 UM 5 Clock Management Unit
527. ose Input Output GPIO Control 4 3 3 129 EXT_INT11CON e Base Address 0x1100 0000 e Address Base Address 0x0730 Reset Value 0 0000 0000 RSV reen 00 Sets signaling method of EXT_INT11 7 0 0 Low level 0x1 High level EXT INT11 CON 7 30 28 RW 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0 5 to 0x7 Reserved 85 2 Mod Sets signaling method of EXT_INT11 6 0 0 Low level 0 1 High level EXT INT11 CON 6 26 24 RW 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0 7 Reserved SVO mq f fm Sets signaling method of EXT INT11 5 0 0 Low level 0 1 High level EXT INT11 CON 5 22 20 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved SVO mp most fm Sets signaling method of EXT_INT11 4 0 0 Low level 0 1 High level EXT INT11 CON 4 18 16 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0x5 to 0 7 Reserved ASV 0 Sets signaling method of EXT_INT11 3 0 0 Low level 0x1 High level EXT INT11 CON S 14 12 RW 0 2 Triggers Falling edge 0x3 Rising edge triggered 0 4 Both edge triggered 0 5 to 0 7 Reserved v fn mew SAMSUNG ELECTRONICS 4 210 ex 4412 UM 4 General Purpose Input Output GPIO Control Sets signalin
528. otally 4 operand raster operation ROP4 Alpha blending user specified constant alpha value per pixel alpha value 8 16 24 32 bpp Packed 24 bpp color format Premultiplied Non premultiplied alpha format 1 bpp 4 bpp 8 bpp 16 bpp 32 bpp Mask format YCbCr format SAMSUNG ELECTRONICS 1 6 ex 4412 UM 1 Product Overview e Digital TV Interface supports High Definition Multimedia Interface HDMI 1 4 a Upto 1080 p 60 Hz 8 channel 112 kHz 24 bit audio 480 p 576 p 720 10801 cannot support 480i HDCP V1 1 93D support e Rotator Supported image format YCbCr422 Interleave YCbCr420 Non interleave and RGB565 and RGB888 unpacked Supported rotate degree 90 180 270 flip vertical and flip horizontal e Video processor The video processor supports BOB 2D IPC mode Production YCbCr 4 4 4 output to help the mixer blend video and graphics 1 AXto 16X vertical scaling with 4 tap 16 phase polyphase filter 1 4 to 16X horizontal scaling with 8 tap 16 phase polyphase filter Pan and scan Letterbox NTSC PAL conversion using scaling Flexible scaled video positioning within display area 1 16 pixel resolution Pan and Scan modes Flexible post video processing o Color saturation brightness contrast enhancement edge enhancement o Color space conversion between BT 601 and BT 709 Video input source size up to 1920 x 1080 e Video Mixer The Video M
529. ount Filtering width of EXT_INT43 1 FLTWIDTH18 1 This value is valid when FLTSEL18 of EXT_INT43 is 0x1 Filter Enable for EXT INT43 0 FLTEN18 0 0 0 Disables Filter 0 1 Enables Filter Filter Selection for EXT INT43 0 FLTSEL18 0 0 0 Delays filter Ox1 Digital filter clock count Filtering width of EXT INT43 0 FLTWIDTH18 0 This value is valid when FLTSEL18 of EXT INT43 is Ox1 SAMSUNG ELECTRONICS 4 278 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 221 EXT_INT43_FLTCON1 e Base Address 0x1100 0000 e Address Base Address OxOE9C Reset Value 0x8080 8080 Filter Enable for EXT_INT43 7 FLTEN18 7 0 0 Disables Filter 0x1 Enables Filter Filter Selection for EXT_INT43 7 FLTSEL18 7 0 0 Delays filter Ox1 Digital filter clock count Filtering width of EXT INT43 7 FLTWIDTH18 7 This value is valid when FLTSEL18 of EXT_INT43 is 0x1 Filter Enable for EXT INT43 6 FLTEN18 6 0 0 Disables Filter 0 1 Enables Filter Filter Selection for EXT INT43 6 FLTSEL18 6 0x0 Delays filter 0 1 Digital filter clock count Filtering width of EXT INT43 6 FLTWIDTH1 8 6 This value is valid when FLTSEL18 of EXT_INT43 is 0 1 Filter Enable for EXT_INT43 5 1 8 5 0 0 Disables Filter 0 1 Enables Filter Filter Selection for EXT_INT43 5 FLTSEL18 5 0 0 Delays filter Ox1 Digital filter clock count Filtering width of EXT INT43 5 FLTWIDT
530. ources are passed INT COMBINER block that is combined interrupt sources for GIC SAMSUNG ELECTRONICS T IT 4412 UM 6 Interrupt Controller 6 3 2 GIC Interrupt Table Total 160 interrupts including Software Generated Interrupts SGls 15 0 ID 15 0 Private Peripheral Interrupts PPIs 15 0 ID 31 16 and Shared Peripheral Interrupts SPIs 127 0 ID 159 32 are supported For SPI you can service a maximal 32 x 4 128 interrupt requests Table 6 2 describes the GIC interrupt SPI 127 Table 6 2 GIC Interrupt Table SPI 127 0 SPI Port No 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 CN 5 ek 4 mi rr oa oa TS 5 N C T O C 5 5 0 o 00 IntG17_3 SYSMMU_FIMC_DRC 1 IntG17 2 SYSMMU ISP 1 IntG17 1 SYSMMU FIMC Lite1 1 IntG17 0 SYSMMU_FIMC_Lite0 1 IntG16_7 L3_IRQ IntG16 5 SYSMMU ISP CX 0 MCT MCT SAMSUNG ELECTRONICS T x 4412 UM 6 Interrupt Controller ib Combiner interrupt Source Source Bock pm wo Paca me _ s o wc CSI 4LANE SDMMC HSMMC3 HSMMC2 SAMSUNG ELECTRONICS a IU 4412 UM 6 Interrupt Controller SPI Port No 4 3 Int Combiner Interrupt Source Source Bloc
531. pare area data it updates the parity codes automatically to NFMECCO and registers If you use 512 byte NAND Flash memory you can program these values to spare area However if you use NAND Flash memory more than 512 byte page you cannot program immediately In this case you have to copy these parity codes to other memory like DRAM After writing all main data you can write the copied ECC values to spare area The parity codes have self correctable information including parity code itself To generate spare area ECC code set the MsgLength to 1 24 byte message length and the ECC Type to 1 enable 4 bit ECC ECC module generates ECC parity code for 24 byte write data To reset ECC value write the NFCONT 5 bit as 1 and clear the MainECCLock NFCONTT 7 bit to 0 unlock before writing data MainECCLock NFCONT 7 bit controls whether ECC code is generated or not Whenever it writes data the 4 bit ECC module generates ECC parity code internally When you complete writing 24 byte meta or extra data it automatically updates the parity codes to NFMECCO and NFMECC1 registers You can program these parity codes to spare area The parity codes have self correctable information including parity code itself SAMSUNG ELECTRONICS 10 8 ex 4412 UM 10 NAND Flash Controller 10 4 8 4 bit ECC Programming Guide DECODING 1 To use 4 bit ECC in software mode set the MsgLength
532. pose Input Output GPIO Control 4 3 3 77 Base Address 0x1100 0000 e Address Base Address 0x01D0 Reset Value 0x0000 0 0 Outputs 0 2n 1 2n Ox1 Outputs 1 Gram 0107 FUN 0x2 Input n 0 3 Previous state 4 3 3 78 GPYSPUDPDN e Base Address 0x1100 0000 e Address Base Address 0x01D4 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down 0107 i 0x2 Reserved 990 0 3 Disables Pull up SAMSUNG ELECTRONICS 4 166 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 79 GPY6CON Base Address 0x1100 0000 e Address Base Address 0x01E0 Reset Value 0x0000 0000 0 0 Input 0 1 Output GPY6CON 7 31 28 0 2 EBI_DATA 15 0 00 0x3 to Reserved 0 0 Input 0 1 Output GPY6CON 6 27 24 RW 0 2 DATA 14 0 00 0x3 to Reserved 0 0 Input 0 1 Output GPY6CON 5 23 20 0x2 EBI_DATA 13 0 00 0x3 to OxE Reserved OxF 0 0 Input 0 1 Output GPY6CON 4 19 16 0 2 EBI_DATA 12 0 00 0x3 to Reserved 0 0 Input 0 1 Output GPY6CON S 15 12 0 2 DATA 11 0x00 0x3 to OxE Reserved OxF 0 0 Input 0 1 Output GPY6CON 2 11 8 0 2 DATA 10 0 00 0x3 to Reserved 0 0 Input 0 1 Output GPY6CON 1 7 4 0 2 DATA 9 0x00 0x3 to O
533. pports 16 BPP non palletized color Supports unpacked 18 BPP non palletized color Supports unpacked 24 BPP non palletized color Supports X Y indexed position Supports 8 bit Alpha blending Plane Pixel CSC Internal RGB to YCbCr 4 2 2 Window 0 Supports 1 2 4 or 8 BPP palletized color Supports 16 18 or 24 BPP non palletized color Supports RGB 8 8 8 local input from Local Bus FIMCO Window 1 Supports 1 2 4 or 8 BPP palletized color Supports 16 18 or 24 BPP non palletized color Source format Supports RGB 8 8 8 local input from Local Bus FIMC1 Window 2 Supports 1 2 4 or 8 BPP palletized color Supports 16 18 or 24 BPP non palletized color Supports RGB 8 8 8 local input from Local Bus FIMC2 Window 3 4 Supports 1 2 4 or 8 BPP palletized color Supports 16 18 or 24 BPP non palletized color Configurable Burst Length Programmable 4 8 16 Burst DMA Window 0 1 2 3 4 Palette Supports 256 x 32 bits palette memory BEA One palette memory for each window Hori 1 i Soft Scrolling orizonta resaman Vertical 1 pixel resolution Virtual i i ize Virtual Screen irtua image can have up to 16 MB image size Each window can have its own virtual area Transparent Overlay Supports transparent overlay Supports color key function Supports simultaneously color key and blending function Partial Display Supports LCD partial display function through 180 interface SAMSUNG ELECTRONICS 16 2 27 OSD functi
534. pt Controller register ai Reset vawe INTERRUPT _ OUT CPU3 0xC044 Interrupt output register 0x0000_0000 SAMSUNG ELECTRONICS 6 15 ex 4412 UM 6 Interrupt Controller Base Address 0x1049 0000 ICDISER2 Interrupt set enable register SPI 63 32 0x0000_0000 ICDICER3 Interrupt clear enable register SPI 95 64 0x0000_0000 nei SPI i SAMSUNG ELECTRONICS 6 16 4412 UM 6 Interrupt Controller ICDIPR5_CPUO Priority level register PPI 7 4 0x0000_0000 ICDIPR18 Priority level register SPI 43 40 0 0000_0000 SAMSUNG ELECTRONICS 6 17 4412 UM 6 Interrupt Controller ICDIPTRO_CPUO 0x0800 Processor targets register SGI 3 0 0x0101_0101 ICDIPTR1_CPUO 0x0804 Processor targets register SGI 7 4 0x0101_0101 ICDIPTR2_CPUO Processor targets register SGI 11 8 0x0101_0101 ICDIPTR3_CPUO Processor targets register SGI 15 12 0x0101_0101 ICDIPTR4_CPUO Processor targets register PPI 3 0 0x0101_0101 ICDIPTR5_CPUO Processor targets register PPI 7 4 0x0101_0101 ICDIPTR6 CPUO Processor targets register PPI 11 8 0x0101_0101 ICDIPTR7_CPUO Processor targets register PPI 15 12 0x0101 0101 ICDIPTR8 Processor targets register SPI 3 0 0x0000_0000 ICDIPTR9 Processor targets register SPI 7 4 0x0000_0000 ICDIPTR10 Processor targets register SPI 11 8 0x0000_0000 ICDIPTR11 Processor targets register SPI 15 12 0 0000_0000 ICDIPTR12 P
535. pt request to inform the CPU that the timer operation is complete If the timer down counter reaches zero the value of corresponding automatically reloads into the down counter to start a next cycle However if the timer stops for example by clearing the timer enable bit of during the timer running mode the value of does not reload into the counter The PWM function uses the value of the TCMPBn register The timer control logic changes the output level if down counter value matches the value of the compare register in timer control logic Therefore the compare register determines the turn on time or turn off time of a PWM output Each timer is double buffer structure with the and registers to allow the timer parameters to update in the middle of a cycle The new values do not take effect until the current timer cycle completes SAMSUNG ELECTRONICS 11 1 ex 4412 UM 11 Pulse Width Modulation Timer Figure 11 1 illustrates the simple example of a PWM cycle Figure 11 1 Simple Example of a PWM Cycle Steps to use PWM as a pulse generator are 5 6 7 8 9 Initialize the TCNTBn register with 159 50 4 109 and TCMPBn with 109 Start Timer Set the start bit and manually update this bit to off The value of 159 is loaded into the down counter and then the output is set to low If down counter counts down the value from TCNT
536. r 0 1 Interrupt occurs EXT PEND 0 RWX 0 0 Not occur 0 1 Interrupt occurs 4 3 2 134 EKT INT2 PEND Base Address 0x1140_0000 e Address Base Address 0x0A04 Reset Value 0x0000 0000 EXT INT2 PEND 5 RWX 0x0 Not occur 0 1 Interrupt occurs EXT INT2 PEND 4 RWX 0x0 Not occur 0 1 Interrupt occurs RW W EXT INT2 PEND 3 X 0x0 Not occur 0 1 Interrupt occurs EXT_INT2_PEND 2 RWX 0x0 Not occur e 0 1 Interrupt occurs EXT INT2 PEND 1 1 RWX 0x0 Not occur 0 1 Interrupt occurs EXT INT2 PEND 0 RWX 0x0 Not occur 0 1 Interrupt occurs SAMSUNG ELECTRONICS 4 109 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 135 EKT INT3 PEND Base Address 0x1140 0000 Address Base Address 0x0A08 Reset Value 0x0000 0000 EXT INT3 PEND 7 7 Rw x 0x0 Not occur Ox1 Interrupt occurs EXT_INT3_PENDI 6 6 RWX 0 0 Not occur 0 1 Interrupt occurs EXT_INT3_PENDI 5 5 RWX 0 0 Not occur PP 0x1 Interrupt occurs 0x0 Not occur EXT INT3 PEND 4 4 RWX EXT INT3 PEND 3 3 RWX 00 Not occur 0 1 Interrupt occurs EXT INT3 PEND 2 2 0X0 Not occur 0x1 Interrupt occurs EXT INT3 PEND 1 1 RWX 0 0 Not occur 0 1 Interrupt occurs EXT INT3 PEND 0 RWX 0x0 Not occur 0 1 Interrupt occurs SAMSUNG ELECTRONICS 4 110 ex 4412 UM 4
537. r The error interrupt occurs if the character is read out Time sequence Flow Errorimemupt Note when no characteris read out ReccvesABGOade Frame error in B interrupt occurs o o Parity error in interrupt occurs gt a er cu reads out gt Figure 13 3 illustrates that UART receives the five characters including two errors E WEE Error Status FIFO 4 Nu break error parity error frame error Figure 13 3 UART Receives the Five Characters Including Two Errors SAMSUNG ELECTRONICS 13 7 ex 4412 UM 13 Universal Asynchronous Receiver and Transmitter 13 3 8 1 Infra Red Mode The 4412 UART block supports both infra red IR transmission and reception You can select the IR mode by setting the IR mode bit in the UART line control register ULCONn Figure 13 4 illustrates how to implement the IR mode In IR transmit mode the transmit pulse moves at the rate of 3 16 that is normal serial transmit rate when the transmit data bit is set to 0 However IR receive mode the receiver must detect the 3 16 pulsed period to recognize a 0 value Refer to frame timing diagrams shown in Figure 13 5 and Figure 13 7 for more information Figure 13 4 illustrates IrDA function block diagram IrDA Tx IrDA Rx Encoder Decoder Figure 13 4 IrDA Function Block Diagram Figure
538. r clock count Filtering width of EXT_INT40 2 FLTWIDTH15 2 This value is valid when FLTSEL15 of EXT_INT40 is 0 1 Filter Enable for EXT_INT40 1 FLTEN15 1 0x0 Disables Filter 0x1 Enables Filter Filter Selection for EXT_INT40 1 FLTSEL15 1 0 0 Delays filter 0x1 Digital filter clock count Filtering width of EXT_INT40 1 FLTWIDTH15 1 This value is valid when FLTSEL15 of EKT INT40 is 0x1 Filter Enable for EXT_INT40 0 FLTEN15 0 0 0 Disables Filter 0x1 Enables Filter Filter Selection for EXT_INT40 0 FLTSEL15 0 0 0 Delays filter Ox1 Digital filter clock count Filtering width of EXT INT40 0 FLTWIDTH15 0 This value is valid when FLTSEL15 of EXT INT40 is Ox1 SAMSUNG ELECTRONICS 4 272 x 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 215 EXT_INT40_FLTCON1 Base Address 0x1100 0000 e Address Base Address OxOE84 Reset Value 0x8080 8080 Filter Enable for EXT INT40 7 FLTEN15 7 0 0 Disables Filter 0x1 Enables Filter Filter Selection for EXT_INT40 7 FLTSEL15 7 0 0 Delays filter 0x1 Digital filter clock count Filtering width of EXT_INT40 7 FLTWIDTH15 7 This value is valid when FLTSEL15 of EXT_INT40 is 0x1 Filter Enable for EXT_INT40 6 FLTEN15 6 0 0 Disables Filter 0x1 Enables Filter Filter Selection for EXT_INT40 6 FLTSEL15 6 0 0 Delays filter 0x1 Digital filter clock count Filtering width of EXT_INT40 6 FLTWI
539. r Enable for EXT INT16 1 FLTEN16 1 15 RW 0x0 Disables filter 0 1 Enables filter FLTWIDTH16 1 14 8 Filtering width of EXT INT16 1 Filter Enable for EXT INT16 0 FLTEN16 0 7 RW 0x0 Disables filter 0 1 Enables filter FLTWIDTH16 0 6 0 RW Filtering width of EXT INT16 0 4 3 2 115 EXT INT16 FLTCON1 e Base Address 0x1140 0000 e Address Base Address 0x087C Reset Value 0x0000 0000 Filter Enable for EXT INT16 5 FLTEN16 5 15 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH16 5 14 8 Filtering width of EXT INT16 5 Filter Enable for EXT INT16 4 FLTEN16 4 7 RW 0x0 Disables filter 0 1 Enables filter FLTWIDTH16 4 60 RW Filtering width of EXT_INT16 4 SAMSUNG ELECTRONICS 4 97 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 116 EXT_INT21_FLTCONO e Base Address 0x1140 0000 e Address Base Address 00880 Reset Value 0 0000 0000 Filter Enable for EXT_INT21 3 FLTEN17 3 31 RW 0 0 Disables filter 0 1 Enables filter FLTWIDTH17 3 30 24 Filtering width of EXT INT21 3 Filter Enable for EXT INT21 2 FLTEN17 2 23 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH17 2 22 16 Filtering width of EXT_INT21 2 Filter Enable for EXT_INT21 1 FLTEN17 1 15 RW 0 0 Disables filter 0 1 Enables filter FLTWIDTH17 1 14 8 Filtering width of EXT INT21 1 Filter Enable for EXT INT21
540. r Integrated Circuit 14 2 Features Features of I2C bus interface are 9channels multi master Slave I2C bus interfaces 8 channels for general purpose 1 channel dedicated for High Definition Multimedia Interface HDMI e 7 bit addressing mode Serial 8 bit oriented and bi directional data transfer e Supports to 100 kbit s in the Standard mode e Supports up to 400 kbit s in the Fast mode e Supports master transmit master receive slave transmit and slave receive operation e Supports interrupt or polling events 14 3 Functional Description 14 3 1 Block Diagram Figure 14 1 illustrates the block diagram of 12C bus Address Register Comparator 12C Bus Control Logic I2 CCON I2CSTAT 4 bit Prescaler Shift Register lt gt SDA Shift Register 2 05 Data Bus Figure 14 1 I2C Bus Block Diagram SAMSUNG ELECTRONICS 14 2 ex 4412 UM 14 Inter Integrated Circuit 14 4 12C Bus Interface Operation The four operation modes of the Exynos 4412 I2C bus interface are e Master Transmitter Mode e Master Receive Mode e Slave Transmitter Mode e Slave Receive Mode The functional relationships among these operating modes are described in these sections e Start and Stop conditions e Data transfer format e ACK signal transmission Read Write operation e Bus arbitration procedures e Abort conditions e Configuring IIC bus SAMSUNG ELECTRONICS 14 3 II 4412 UM 14 Inter In
541. r and Transmitter 13 6 1 8 UMSTATn 0 1 2 4 e Base Address 0x1380 0000 Base Address 0x1381_0000 Base Address 0x1382 0000 e Base Address 0x1383 0000 Base Address 0x1384 0000 Address Base Address 0x001C Reset Value 0 0000_0000 REL TA This bit indicates that the nCTS input to the Exynos 4412 has changed its state since the last time CPU read it Refer to Figure 13 9 for more information Delta CTS 4 0 Has not changed 1 Has changed NOTE In UMSTATA reset value of this bit is undefined It depends on the GPIO configuration of GPS mw Jem faen pf 0 Does not activates CTS signal NCTS pin is high 1 Activates CTS signal NCTS pin is low NOTE UMSTATA reset value of this bit is undefined It depends on the GPIO configuration of GPS Figure 13 9 illustrates the nCTS and delta Clear to Send CTS timing diagram Delta CTS Read_UMSTAT Modem interrupt Figure 13 9 nCTS and Delta CTS Timing Diagram SAMSUNG ELECTRONICS 13 25 ex 4412 UM 13 Universal Asynchronous Receiver and Transmitter 13 6 1 9 UTXHn 0 104 e Base Address 0x1380 0000 Base Address 0x1381_0000 Base Address 0x1382 0000 e Base Address 0x1383 0000 Base Address 0x1384 0000 e Address Base Address 0x0020 Reset Value 0x0000 0000 UTXHn 7 0 Transmits data for UARTn o 13 6 1 10 URXHn n 0 to 4 e Base Address 0x1380 0000 Ba
542. r clock generation SAMSUNG ELECTRONICS 1 1 IT 4412 UM 1 Product Overview 1 2 Features The features of Exynos 4412 are ARM Cortex A9 based Quad CPU Subsystem with NEON 32 32 32 32 KB 1 0 Cache 1 MB L2 Cache Operating frequency up to 800 MHz at 0 9 V 1 GHz at 1 0 V and 1 4 GHz at TBD 128 bit 64 bit Multi layer bus architecture Core D domain for ARM Cortex A9 Quad CoreSight and external memory interface Operating frequency up to 200 MHz at 1 0 V Global D domain mainly for multimedia components and external storage interfaces Operating frequency up to 100 MHz at 1 0 V Core P Global P domain mainly for other system component such as system peripherals peripheral DMAs connectivity IPs and Audio interfaces Operating frequency up to 100 MHz at 1 0 V A Audio domain for low power audio play Advanced power management for mobile applications 64 KB ROM for secure booting and 256 KB RAM for security function 8 bit ITU 601 656 Camera Interface supports horizontal size up to 4224 pixels for scaled and 8192 pixels for un scaled resolution 2D Graphics Acceleration support 1 2 4 8bpp Palletized or 8 16 24bpp Non Palletized Color TFT recommend up to WXGA resolution HDMI interface support for NTSC and PAL mode with image enhancer MIPI DSI and MIPI CSI interface support One AC 97 audio codec interface and 3 channel PCM serial audio interface Three 24 bit 125 interface support One TX only
543. r more information ve OxOFEO to Specifies the peripheral identification registers 0 3 Refer to Configuration peripn io OxOFEC page 3 48 of PL330 for more information dependent cell id n OxOFFO to Specifies the primecell identification registers 0 3 Refer to Configuration poet 10 OxOFFC page 3 50 of PL330 TRM for more information dependent SAMSUNG ELECTRONICS 8 8 IT 4412 UM 8 Direct Memory Access Controller DMAC Base Address 0x1268 0000 0x1269 0000 PDMAO PDMA1 S 0x0000 Specifies the DMA status register Refer to page 3 11 of 0x00000200 PL330 for more information i mg En ECL DANA PRESS rmi Specifies the interrupt status register Refer to page 3 16 of PL330 for information p Specifies the interrupt clear register Refer to page 3 17 of INTGER DKDD2C PL330 TRM for more information oxp Specifies the fault status DMA manager register Refer to 030040 page 3 18 of PL330 for more information Specifies the fault status DMA channel register Refer to unas 3 19 of PL330 for more information ene Specifies the fault type DMA manager register Refer to vr page 3 20 of PL330 TRM for more information FTCO 0x0040 Specifies the fault type for DMA channel 0 0 0044 Specifies the fault type for DMA channel 1 FTC2 0x0048 Specifies the fault type for DMA channel 2
544. rByteLoc9 RSVD ErrByteLoc12 RSVD ErrByteLoc11 RSVD ErrByteLoc14 SAMSUNG ELECTRONICS 10 33 4412 UM 10 NAND Flash Controller ErrByteLoc13 9 0 Error byte location of 13 bit error 0 000 2516 Eror byie caron orre eiren TEnayetocis ig Eror bye caron oria eiren NOTE It updates these values when DecodeDone NFECCSTAT 24 is set 1 SAMSUNG ELECTRONICS 10 34 ex 4412 UM 10 NAND Flash Controller 10 7 3 7 NFECCERPn 0 to 3 e Base Address OXOCE2 0000 e Address Base Address Reset Value 0x0000 0000 NFECCERPO e Address Base Address 0x00F4 Reset Value 0x0000 0000 NFECCERP1 e Address Base Address 0x00F8 Reset Value 0 0000 0000 NFECCERP2 e Address Base Address 0 00 Reset Value 0x0000 0000 NFECCERP3 4 ErrBitPattern 31 24 4 Error Bit Pattern 0x00 3 ErrBitPattern 23 16 Hy 3 Error bit pattern 0 00 0 00 0x00 8 ErrBitPattern 31 24 8 Error bit pattern 7 ErrBitPattern 23 16 7 Error bit pattern 6 ErrBitPattern 15 8 6 Error bit pattern 5 ErrBitPattern 7 0 5 Error bit pattern 12 ErrBitPattern 31 24 12 Error bit pattern 11 ErrBitPattern 23 16 11 Error bit pattern 10 ErrBitPattern 15 8 10 Error bit pattern 9 ErrBitPattern 7 0 EN 9 Error bit pattern 16 ErrBitPattern 31 24 16 Error bit pattern 15 E
545. read 2 Channel thread Each channel thread can operate the DMA Accordingly write an assembly code If you require a number of independent DMA channels write a number of assembly codes for each channel Assemble and link the codes into one file and load this file into the memory SAMSUNG ELECTRONICS 8 14 ex 4412 UM 9 SROM Controller SROM Controller 9 1 Overview Exynos 4412 SROM Controller SROMC supports e External 8 16 bit NOR Flash PROM SRAM memory e 4 bank memory up to maximum 128 Kbyte per bank 9 2 Features The features of SROMC are e Supports SRAM various ROMs and NOR flash memory e Supports only 8 or 16 bit data bus e Address space Up to 128 KB per bank e Supports 4 bank e Fixed memory bank start address e External wait to extend the bus cycle e Supports byte and half word access for external memory 9 3 Block Diagram Figure 9 1 illustrates the block diagram of SROMC introduction SFR AHB I F for SROM SFR SROM I F SROM N NTROL IGNAL ME SROM MEM I 2 STATE MACHINE GENERATON Cs I F for SROM DECODER Figure 9 1 Block Diagram of SROMC Introduction SAMSUNG ELECTRONICS 9 1 ex 4412 UM 9 SROM Controller 9 4 Functional Description SROMC supports SROM interface for Bank 0 to Bank 3 This section includes e nWAIT Pin Operation e Programmable Access
546. register 1 0x0000 0000 EXT_INT12_FLTCON1 External interrupt EXT_INT12 filter configuration register 1 0x0000_0000 EXT_INT23_MASK 0 0908 External interrupt EXT_INT23 mask register 0x0000_007F EXT_INT24_MASK 0 090 External interrupt EXT_INT24 mask register 0x0000_007F EXT_INT25_MASK 0 0910 External interrupt EXT_INT25 mask register 0x0000_007F EXT_INT8_MASK 0x0924 External interrupt EXT_INT8 mask register 0x0000_00FF EXT_INT9_MASK 0x0928 External interrupt EXT_INT9 mask register EXT_INT10_MASK 0x092C External interrupt EXT_INT10 mask register 0x0000_001F EXT_INT11_MASK 0x0930 External interrupt EXT_INT11 mask register 0x0000_00FF 0x0000_007F SAMSUNG ELECTRONICS 4 14 4412 UM 4 General Purpose Input Output GPIO Control EXT_INT26_PEND 0 0 14 External interrupt 26 pending register 0x0000_0000 EXT_INT27_PEND External interrupt EXT_INT27 pending register EXT_INT28_PEND External interrupt EXT_INT28 pending register 0x0000_0000 29 PEND External interrupt EXT INT29 pending register 0x0000 0000 EXT_INT8_PEND 0 0 24 External interrupt EXT_INT8 pending register 0 0000_0000 0 0000_0000 EXT INT9 PEND External interrupt EXT INT9 pending register 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0 EXT INT10 PEND Ox0A2C External interrupt EXT INT10 pending register EXT INT11 PEND External interrupt EXT INT11 pending register EXT INT12 PEND 0 0
547. rength control register 0x00 0000 GPL1CONPDN OxOOFO Port group GPL1 power down mode configuration register 0x0000 GPL2PUDPDN 0x0114 Er GPL2 power down mode pull up pull down 0x0000 GPYOCON 0x0120 Port group GPYO configuration register 0x0000 0000 GPYODAT 0x0124 Port group GPYO data register 0 00 GPYODRV 0 012 Port group GPYO drive strength control register 0x00 0AAA GPYOCONPDN 0x0130 Port group GPYO power down mode configuration register 0x0000 GPY1CON 0x0140 Port group GPY1 configuration register 0x0000 0000 GPY1DAT 0x0144 Port group GPY1 data register GPY1PUD 0x0148 Port group GPY1 pull up pull down register 0x00FF 0x00 GPY0PUD 0x0128 Port group GPY0 pull up pull down register OxOFFF GPY1PUDPDN 0 0154 GPY1 power down mode pull up pull down 0 0000 GPY2CONPDN 0x0170 Port group GPY2 power down mode configuration register 0 0000 GPY2PUDPDN 0x0174 2 GPY2 power down mode pull up pull down 0 0000 GPY1CONPDN 0x0150 Port group GPY1 power down mode configuration register 0 0000 GPYOPUDPDN 0x0134 d GPY0 power down mode pull up pull down 0x0000 GPY1DRV 0x014C Port group GPY1 drive strength control register 0x00_O0AA SAMSUNG ELECTRONICS 4 11 4412 UM 4 General Purpose Input Output GPIO Control GPY3PUDPDN 0x0194 2 power down mode pull up pull down 0x0000 Fort group GPY4 power down mode configuration register GPY4CONPDN 0x01B0 Port group GPY4 power
548. ress 0 65 Reset Value 0x0000 0000 RSV erst OO DIVSLIMBUS Status DIV SLIMBUS 4 0 Stable 1 Status that the divider is changing S ov 5 10 1 87 CLK DIV STAT PERIL4 Base Address 0 1003 0000 e Address Base Address 0xC660 Reset Value 0x0000 0000 RSV aren Rs DIVPCM2 Status DIV_PCM2 20 0 Stable 1 Status that the divider is changing SE vem ____ mo DIVAUDIO2 Status DIV_AUDIO2 16 0 Stable 1 Status that the divider is changing SE ne Jo DIVPCM1 Status DIV PCM1 4 0 Stable 1 Status that the divider is changing SE ne Jo DIVAUDIO1 Status DIV AUDIO1 0 0 Stable 1 Status that the divider is changing SAMSUNG ELECTRONICS 5 104 ex 4412 UM 5 Clock Management Unit 5 10 1 88 CLK_DIV_STAT_PERIL5 e Base Address 0x1003 0000 e Address Base Address 0xC664 Reset Value 0 0000 0000 RSVD er DIVI2S2 Status 1252 8 0 Stable 1 Status that the divider is changing SE mp mew mo DIVI2S1 Status DIV 1251 0 Stable 1 Status that the divider is changing 5 10 1 89 CLK DIV STAT CAM1 e Base Address 0x1003 0000 e Address Base Address 0xC668 Reset Value 0x0000 0000 RSVD au eee o DIVJPEG Status DIV_JPEG 0 0 Stable 1 Status that the divider is changing SAMSUNG ELECTRONICS 5 105 IT 4412 UM 5 Clock Managem
549. ress Base Address Reset Value 0 0190 0180 GAMMALUT 7 6 e Address Base Address 0X03B0 Reset Value 0X01BO 01A0 GAMMALUT 9 8 e Address Base Address 0X03B4 Reset Value 0X01D0 01C0 GAMMALUT_R_11_10 e Address Base Address 0X03B8 Reset Value 0X01F0_01E0 GAMMALUT_R_13_12 e Address Base Address 0X03BC Reset Value 0 0210 0200 GAMMALUT R 15 14 e Address Base Address 0 03 0 Reset Value 0 0230 0220 GAMMALUT_R_16 e Address Base Address 0X03C4 Reset Value 0 0250 0240 GAMMALUT_R_1_0 e Address Base Address 0 03 8 Reset Value 0 0270 0260 GAMMALUT 3 2 e Address Base Address Reset Value 0 0290 0280 GAMMALUT 5 4 e Address Base Address 0X03D0 Reset Value 0 02 0 02 0 GAMMALUT R 7 6 e Address Base Address 0X03D4 Reset Value 0 0200 02 0 GAMMALUT_R_9 8 e Address Base Address 0X03D8 Reset Value 0 02 0 02 0 GAMMALUT_R_11_10 e Address Base Address Reset Value 0 0310 0300 GAMMALUT 13 12 e Address Base Address Reset Value 0 0330 0320 GAMMALUT 15 14 e Address Base Address 0X03E4 Reset Value 0 0350 0340 GAMMALUT_R_16 GM_LUT_x 26 18 Specifies Gamma LUT value register of index x Undefined GM_LUT_y 10 2 Specifies Gamma LUT value register of index y Undefined SAMSUNG ELECTRONICS 16 133 ex 4412 UM 16 Display Controller 16 5
550. ription Author s 1 00 Aug 22 2011 SAMSUNG ELECTRONICS x Revision Descriptions for Revision 1 00 Chapter Name Major Changes comparing with Last Version 1 1 01 Product Overview A SAMSUNG ELECTRONICS 227 Table of Contents 1 PRODUCT OVERVIEW caiste ati 1 1 TINTO UCI A ee 1 1 1 2 Features aa m m 1 2 1 2 1 Multi Core Processing 1 4 1 2 2 Memory SUDSYSTO 1 5 1 6 1 2 4 Audio SUBSYSTEM 1 8 1 2 5 Image Signal Processing Subsystem 1 8 1 2 6 dada 1 9 1 2 7 System Peripheral a 1 11 1 3 6 latina wa 1 13 1 3 1 Register RW Conventions 0 aiana 1 13 1 32 Register Value Conventions 1 13 2 MEMORY 2 1 OO EE 2 1 2 2 SFR Base Address iii A adeat e eee ee 2 2 CHIP AA 3 1 ST VEME patada DE 3 1 3 2 Register uu Lu dd 3 2 3 2 1 Register iii anida 3 2 4 GENERAL PURPOSE INPUT OUTPUT GPIO CONTROL 4 1 A OE mE 4 1 4 2 EOS Sc ia PR 4 3 4 2 1 Input Output a dis 4 3 4 3 Register u AA
551. rite the data Exynos 4412 holds the interrupt to identify the completion of current data transfer After the CPU receives the interrupt request it writes new data to the I2CDS register again When the 2 controller receives data in receive mode the I2C bus interface waits until 12CDS register is Read Before you read out the new data the SCL line is held Low The 2 controller releases the SCL line after you read the data Exynos 4412 holds the interrupt to identify the completion of new data reception After the CPU receives the interrupt request it reads the data from the 2 5 register 14 4 5 Bus Arbitration Procedures Arbitration occurs on the SDA line to prevent the conflict on the bus between two masters If a master with a SDA High level detects other master with a SDA active Low level it does not initiate a data transfer This is because the current level on the bus is not corresponding to initiate a data transfer The arbitration procedure extends until the SDA line turns High When two or more masters assert the SDA line Low simultaneously each master evaluates whether it has the mastership or not For the purpose of evaluation each master detects the address bits While each master generates the Slave address it detects the address bit on the SDA line This is because the SDA line becomes Low instead of High Let us assume that one master generates a Low as first address bit while the other master is maintaining High In
552. rmines which function is able to Write Tx data to the UART transmit buffer 00 Disables 01 Interrupt request or polling mode 10 DMA mode 11 Reserved Determines which function is able to Read data from UART receive buffer 00 Disables a 13 15 4412 UM 13 Universal Asynchronous Receiver and Transmitter 01 Interrupt reguest or polling mode 10 mode 11 Reserved 1 DIV VAL UBRDIVn UFRACVAL 16 Refer to 13 6 1 11 UBRDIVn and 13 6 1 12 UFRACVALn for more information 2 4412 uses a level triggered interrupt controller Therefore you must set these bits to 1 for every transfer 3 If UART does not reach the trigger level of FIFO and does not receive data during the time specified at the Rx Timeout Interrupt Interval field in DMA receive mode with FIFO UART generates the Rx interrupt receive time out Ensure to verify the FIFO status and read out the rest 4 Both UCONn 11 and UCONn 7 should be set to 1 if you want to enable Rx time out feature when Rx FIFO counter is set to 0 SAMSUNG ELECTRONICS 13 16 ex 4412 UM 13 Universal Asynchronous Receiver and Transmitter 13 6 1 3 UFCONn n 0 to 4 e Base Address 0x1380 0000 Base Address 0x1381 0000 Base Address 0x1382 0000 e Base Address 0x1383 0000 Base Address 0x1384 0000 Address Base Address 0x0008 Reset Value 0x0000_0000 aaa Determines the
553. rocessor targets register SPI 19 16 0 0000_0000 ICDIPTR13 0x0000_0000 x ICDIPTR14 0 0838 Processor targets register SPI 27 24 0x0000_0000 ICDIPTR15 Processor targets register ICDIPTR16 Processor targets register SPI 35 32 0x0000 0000 ICDIPTR17 Processor targets register SPI 39 36 0x0000 0000 ICDIPTR18 Processor targets register SPI 43 40 0 0000 0000 SPI 31 28 0x0000_0000 ICDIPTR19 0x084C Processor targets register SPI 47 44 0x0000 0000 ICDIPTR20 0x0850 Processor targets register SPI 51 48 0x0000_0000 ICDIPTR21 0x0854 Processor targets register SPI 55 52 0x0000_0000 ICDIPTR22 Processor targets register SPI 59 56 0 0000 0000 ICDIPTR23 Processor targets register SPI 63 60 0x0000 0000 ICDIPTR24 Processor targets register SPI 67 64 0 0000_0000 ICDIPTR25 0x0864 Processor targets register SPI 71 68 0x0000_0000 ICDIPTR26 0x0868 Processor targets register SPI 75 72 0x0000_0000 ICDIPTR27 0 086 Processor targets register SPI 79 76 0x0000_0000 ICDIPTR28 Processor targets register SPI 83 80 0x0000_0000 ICDIPTR29 Processor targets register SPI 87 84 0x0000_0000 7 ICDIPTR30 Processor targets register SPI 91 98 0x0000_0000 ICDIPTR32 Processor targets register SPI 99 96 0x0000_0000 ICDIPTR33 Processor targets register SPI 103 100 0x0000_0000 ICDIPTR34 Processor targets reg
554. rol 4 3 3 50 GPY1DAT e Base Address 0x1100 0000 e Address Base Address 0x0144 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPY1DAT 3 0 3 0 output port the pin state should be same as the 0x00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 3 51 GPY1PUD Base Address 0x1100 0000 e Address Base Address 0x0148 Reset Value 0x00FF 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down GPY1PUD n n 0to3 RW G2 Reserved 0x00FF 0x3 Disables Pull up 4 3 3 52 GPY1DRV e Base Address 0x1100_0000 Address Base Address 0x014C Reset Value 0x00_00AA 23 16 Reserved Should be zero W GPY1DRV n n 2n 1 2n R OKODARA 0103 SAMSUNG ELECTRONICS 4 151 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 53 GPY1CONPDN Base Address 0x1100 0000 e Address Base Address 0x0150 Reset Value 0x0000 0 0 Outputs 0 2n 1 21 0 1 Outputs 1 n 0t03 ox2 Input 999 0 3 Previous state 4 3 3 54 GPY1PUDPDN Base Address 0x1100_0000 e Address Base Address 0x0154 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down 0103 0 2 Reserved 990 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 152 ex 4412 UM
555. rror bit pattern 23 16 15 Error bit pattern 14 ErrBitPattern 15 8 14 Error bit pattern 13 ErrBitPattern 7 0 13 Error bit pattern NOTE It updates these values when DecodeDone NFECCSTAT 25 is set 1 SAMSUNG ELECTRONICS 10 35 ex 4412 UM 10 NAND Flash Controller 10 7 3 8 NFECCCONECCn 0 to 6 e Base Address OXOCE2 0000 e Address Base Address 0x0110 Reset Value 0x0000 0000 NFECCCONECCO e Address Base Address 0x0114 Reset Value 0x0000 0000 NFECCCONECC1 e Address Base Address 0x0118 Reset Value 0x0000 0000 NFECCCONECC2 e Address Base Address 0x011C Reset Value 0x0000 0000 NFECCCONECC3 e Address Base Address 0x0120 Reset Value 0x0000 0000 NFECCCONECC4 e Address Base Address 0x0124 Reset Value 0x0000 0000 NFECCCONECC5 e Address Base Address 0x0128 Reset Value 0x0000 0000 NFECCCONECC6 6 ECC Parity conversion code 0 00 9 Conversion Code 9 ECC conversion code 0 00 7 7 Conversion Code 16 Conversion Code 16 ECC Parity conversion code 0 00 MN RW RW 6 Conversion Code 15 8 5 Conversion Code 7 0 12 Conversion Code 31 24 11 Conversion Code 23 16 19 Parity conversion code 0 00 18 Parity conversion code 0 00 20 Conversion Code 19 Conversion Code 18 Conversion Code 7 Conversion Code 7 0 4 Conversion Code 31 24 1 7 ECC Parity conversion
556. rupt EXT_INT23 configuration register 0x0000_0000 EXT 24 0 070 External interrupt EXT_INT24 configuration register 0x0000_0000 EXT_INT25_CON 0x0710 External interrupt EXT_INT25 configuration register 0x0000_0000 EXT_INT26_CON 0x0714 External interrupt EXT_INT26 configuration register 0x0000_0000 EXT_INT27_CON 0x0718 External interrupt EXT_INT27 configuration register 0x0000_0000 EXT_INT29_CON 0x0720 External interrupt EXT_INT29 configuration register 0x0000_0000 EXT_INT28_CON 0x071C External interrupt EXT_INT28 configuration register 0x0000_0000 EXT_INT8_CON 0x0724 External interrupt EXT_INT8 configuration register 0x0000_0000 EXT 9 0 0728 External interrupt EXT_INT9 configuration register 0x0000_0000 EXT_INT10_CON 0x072C External interrupt EXT_INT10 configuration register 0x0000_0000 EXT_INT11_CON 0x0730 External interrupt EXT_INT11 configuration register 0x0000_0000 EXT_INT12_CON 0x0734 External interrupt EXT_INT12 configuration register 0x0000_0000 EXT_INT23_FLTCONO 0 0810 External interrupt EXT_INT23 filter configuration register 0 0 0000_0000 EXT_INT23_FLTCON1 0 0814 External interrupt EXT_INT23 filter configuration register 1 0 0000_0000 SAMSUNG ELECTRONICS 4 13 4412 UM 4 General Purpose Input Output GPIO Control EXT_INT24_FLTCONO 0 0818 External interrupt EXT_INT24 filter configuration register 0 0 0000_0000 EXT_INT24_FLTCON1 0x081C
557. rupt Occurs 0 0 Not occur INTSO PENDIA 4 0 1 Interrupt Occurs 0 0 Not occur EXT INT50 PEND 2 2 RWX 0 1 interrupt Occurs 0 0 Not occur 0x1 interrupt Occurs 0 0 Not occur FAT NS EB KWA 0 1 Interrupt Occurs EXT INT50 PEND 1 1 RWX EXT 50 PENDIS 3 RWA on E Min Des SAMSUNG ELECTRONICS 4 295 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 4 12 EXT_INT_SERVICE_XD e Base Address 0x0386 0000 e Address Base Address 0x0B08 Reset Value 0x0000 0000 RSVD 31 8 EXT INT Service group number SVC Group Num 7 3 RW 0x1 EXT INT50 SVC Num 20 RW Interrupt number to be serviced 4 3 4 13 EXT INT SERVICE PEND XD Base Address 0x0386 0000 e Address Base Address Reset Value 0 0000 0000 0 0 Not 7 0 0 1 Interrupt Occurs 4 3 4 14 EXT_INT_GRPFIXPRI_XD e Base Address 0x0386_0000 e Address Base Address 0x0B10 Reset Value 0x0000_0000 When fixed group priority mode 0 then group Highest_GRP_NUM 3 0 RW number should be of the highest priority 0x00 0x0 EXT_INT50 SAMSUNG ELECTRONICS 4 296 x 4412 UM 4 General Purpose Input Output GPIO Control 4 3 4 15 EXT_INT50_FIXPRI e Base Address 0x0386 0000 e Address Base Address 0x0B14 Reset Value 0x0000 0000 Interrupt number of the highest priority in External Highest EIN
558. s Base Address 0x004C Reset Value 0x00_2AAA 23 16 Reserved Should be zero W GPK0DRV n n 2n 1 2n R 0106 SAMSUNG ELECTRONICS 4 126 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 5 GPKOCONPDN Base Address 0x1100 0000 e Address Base Address 0x0050 Reset Value 0x0000 0 0 Outputs 0 2n 1 21 0 1 Outputs 1 0106 FW oxo lt input 552 0 3 Previous state 4 3 3 6 GPKOPUDPDN Base Address 0x1100_0000 e Address Base Address 0x0054 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down 0106 0 2 Reserved 990 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 127 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 7 GPK1CON Base Address 0x1100 0000 e Address Base Address 0x0060 Reset Value 0x0000_0000 0 0 Input 0 1 Output 0 2 SD 1 DATA 3 GPK1CON 6 27 24 0x3 SD 0 DATA 7 0 00 0 4 SD 4 DATA 7 0 5 to Reserved EXT INT24 6 0 0 Input 0 1 Output 0 2 SD 1 DATA 2 GPK1CON 5 23 20 0x3 SD 0 DATA 6 0 00 0 4 SD 4 DATA 6 0 5 to Reserved EXT INT24 5 0 0 Input 0 1 Output 0 2 SD 1 DATA 1 GPK1CON 4 19 16 0x3 SD 0 DATA 5 0 00 0 4 SD 4 DATA 5 0 5 to Reserved OxF EXT INT24 4 0 0 Input 0 1 Output 0 2 SD 1
559. s Base Address 0x0700 Reset Value 0 0000 0000 RSV en ne 0 Sets signaling method of EXT_INT1 7 0x0 Low level 0x1 High level EXT_INT1_CON 7 30 28 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0 7 Reserved 85 2 ne Sets signaling method of EXT_INT1 6 0 0 Low level 0x1 High level EXT_INT1_CON 6 26 24 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0 7 Reserved SVO gp Red ov Sets signaling method of EXT INT1 5 0x0 Low level 0 1 High level EXT INT1 CON 5 22 20 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0x7 Reserved 85 0 none MI Sets signaling method of EXT_INT1 4 0x0 Low level 0x1 High level EXT_INT1_CON 4 18 16 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0 7 Reserved 85 9 mp Sets signaling method of EXT_INT1 3 0x0 Low level 0x1 High level EXT INT1 CON 3 14 12 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved mw ee mw SAMSUNG ELECTRONICS 4 61 IT 4412 UM 4 General Purpose Input Output GPIO Control Sets signaling method of EXT_INT1 2 0 0 Low level 0x1 High level EXT INT1 CON 2 10 8 RW 0 2 Triggers falling edge 0x3
560. s 0x1382_0000 e Base Address 0x1383_0000 Base Address 0x1384_0000 Address Base Address 0x0038 Reset Value 0x0000_0000 MODEM Masks modem interrupt ERROR Masks error interrupt Figure 13 10 illustrates the block diagram of UINTSP and UINTM UART_INT UART interrupt UINTSP Figure 13 10 Block Diagram of UINTSP and Interrupt mask contains the information about masked interrupt sources When a specific bit is setto 1 UART does not generate interrupt request signal to the Interrupt Controller even though it generates corresponding interrupt NOTE In such cases the corresponding bit of UINTSPn is set to 1 When the mask bit is set to 0 CPU services the interrupt requests from the corresponding interrupt source SAMSUNG ELECTRONICS 13 30 ex 4412 UM 14 Inter Integrated Circuit Inter Integrated Circuit 14 1 Overview The Exynos 4412 Reduced Instruction Set Computer RISC microprocessor supports four multi master Inter Integrated Circuit I2C bus serial interfaces To transmit information between bus masters and peripheral devices which are connected to the 2 bus a dedicated Serial Data Line SDA and Serial Clock Line SCL is used Both SDA and SCL lines are bi directional In multi master I2C bus mode multiple Exynos 4412 RISC microprocessors either receive or transmit serial data to or from
561. s 0x1384 0000 e Address Base Address 0x0000 Reset Value 0x0000_0000 RSVD 31 7 Infrared 2 Determines whether to use the infra red mode Parity Mode 5 3 0 Normal mode operation 1 Infra red Tx Rx mode Number of Stop Bit Word Length 1 0 Specifies how many stop bits UART uses to signal end of frame signal 0 One stop bit per frame 1 Two stop bit per frame Indicates the number of data bits UART transmits or receives per frame 00 5 bits 01 6 bits 10 7 bits 11 8 bits EN Specifies the type of parity that UART generates and checks during UART transmit and receive operation No parity RW 100 Odd parity 101 Even parity 110 Parity forced checked as 1 111 Parity forced checked as 0 m SAMSUNG ELECTRONICS 13 13 II 4412 UM 13 Universal Asynchronous Receiver and Transmitter 13 6 1 2 UCONn 0 to 4 e Base Address 0x1380 0000 Base Address 0x1381_0000 Base Address 0x1382 0000 e Base Address 0x1383 0000 e Base Address 0x1384 0000 Address Base Address 0x0004 Reset Value 0x0000_0000 Womens Burst Size is the data transfer size of one DMA transaction Tx request triggers the DMA transaction You must program the DMA program to transfer the same data size as this is the value for a single Tx DMA request 000 1 byte Single E KASI 22 20 RW 001 4 bytes 010 8 bytes 011 16 bytes
562. s changing SAMSUNG ELECTRONICS 5 82 4412 UM 5 Clock Management Unit 5 10 1 50 CLK MUK 5 1 e Base Address 0x1003 0000 e Address Base Address 0xC458 Reset Value 0x0000_0111 RSVD Selection signal status of MUXJPEG pease 0 MOUTIPEG 1 Status that the is changing Selection signal status of MUXJPEG 1 EG SEL 99 z Sun 1 Status that the is changing Selection signal status of MUKJPEG 0 003 sour 1 Status that the is changing SAMSUNG ELECTRONICS 5 83 ex 4412 UM 5 Clock Management Unit 5 10 1 51 CLK DIV TOP e Base Address 0x1003 0000 e Address Base Address 0xC510 Reset Value 0 0000 0000 m eee DIVACLK_266 Clock Divider Ratio ACLK 400 MCUISP pw ACLK 400 MCUISP _ MOUTACLK_400_MCUISP ACLK_400_MCUI SP_RATIO 1 mw ne os DIVACLK 266 Clock Divider Ratio Er e 22 20 RW ACLK 266 GPS MOUTACLK 266 GPS ACLK 266 GPS RATIO 1 mw fa ne 00 DIVONENAND Clock Divider Ratio ONENAND RATIO 18 16 RW SCLK ONENAND MOUTONENAND 1 ONENAND RATIO 1 mus DIVACLK 133 Clock Divider Ratio ACLK 133 RATIO 14 12 RW ACLK 133 MOUTACLK 133 ACLK 133 RATIO 1 mes mi nes 99 1 DIVACLK 160 Clock Divider Ratio ACLK 160 RATIO 10 8 RW 160
563. s controlled automatically SAMSUNG ELECTRONICS 15 7 ex 4412 UM 15 Serial Peripheral Interface 15 5 1 1 CH CFGn n 0 to 2 Base Address 0x1392 0000 e Base Address 0x1393 0000 Base Address 0x1394 0000 e Address Base Address 0 0000 Reset Value 0 0 Reserved Slave Tx output time control bit If this bit is enabled slave Tx output time is reduced as much as half period of SPICLKout period SKEE This bit is valid only in CPHA 0 0 Disables 1 Enables Software Reset The following registers and bits are cleared by this bit Rx Tx data STATUS register will be SW_RST reset once in the initial time And after that if we want to reset the register again we have to use SW RST bit manually 0 Inactive 1 Active Whether SPI Port is Master or Slave SLAVE 0 Master 1 Slave Determines whether active high active low clock CPOL 0 Active high 1 Active low Select one of the two fundamentally different transfer format SPRA 0 Format A 1 Format B SPI Rx Channel On RX_CH_ON 0 Channel off 1 Channel on SPI Tx Channel On TX_CH_ON 0 Channel off 1 Channel on NOTE SPI controller should reset when 1 Reconfiguration of SPI registers is done 2 Error interrupt has occurred SAMSUNG ELECTRONICS 15 8 ex 4412 UM 15 Serial Peripheral Interface 15 5 1 2 MODE CFGn n 0 to 2 Base Address 0x1392 0000 e Base Address 0x
564. s filter FLTWIDTH3 7 30 24 Filtering width of EXT INT3 7 Filter Enable for EXT INT3 6 FLTENS 6 23 RW 0 0 Disables filter 0x1 Enables filter FLTWIDTH3 6 22 16 Filtering width of EXT INT3 6 Filter Enable for EXT INT3 5 FLTENS 5 15 RW 0x0 Disables filter 0x1 Enables filter FLTWIDTH3 5 14 8 Filtering width of EXT INT3 5 Filter Enable for EXT INT3 4 FLTEN3 4 7 RW 0 0 Disables filter 0 1 Enables filter FLTWIDTH3 4 6 0 Filtering width of EXT INT3 4 SAMSUNG ELECTRONICS 4 86 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 100 EXT_INT4_FLTCONO e Base Address 0x1140_0000 e Address Base Address 0x0818 Reset Value 0x0000_0000 Filter Enable for EXT_INT4 3 FLTEN4 3 31 RW 0 0 Disables filter 0 1 Enables filter FLTWIDTH4 3 30 24 Filtering width of EXT_INT4 3 Filter Enable for EXT_INT4 2 FLTENA 2 23 RW 0 0 Disables filter 0 1 Enables filter FLTWIDTH4 2 22 16 Filtering width of EXT INT4 2 Filter Enable for EXT INT4 1 FLTENA 1 15 RW 0x0 Disables filter 0 1 Enables filter FLTWIDTH4 1 14 8 Filtering width of EXT INT4 1 Filter Enable for EXT INT4 0 FLTEN4 0 7 RW Disables filter 0 1 Enables filter FLTWIDTH4 0 1601 RW Filtering width of EXT_INT4 0 4 3 2 101 EXT INT4 FLTCON1 e Base Address 0x1140 0000 e Address Base Address 0x081C Reset Value 0x0000
565. s of the read write operation Figure 14 2 illustrates the Start and Stop condition Start Stop Condition Condition Figure 14 2 Start and Stop Condition SAMSUNG ELECTRONICS 14 4 ex 4412 UM 14 Inter Integrated Circuit 14 4 2 Data Transfer Format Every byte placed on the SDA line should be 8 bits in length There is no limit to transmit bytes per transfer The first byte that follows a Start condition should have the address field When the 2 is operating in master mode master transmits the address field An bit follows each byte The 2 controller sends first the MSB of the data and address byte to the SDA line Figure 14 3 illustrates the I2C bus interface data format Write Mode Format with 7 bit Addresses Slave Address 7bits DATA 1Byte aje 0 Write Data Transferred Data Acknowledge Read Mode Format with 7 bit Addresses Slave Address 7 bits DATA ale Mg Read Data Transferred Data Acknowledge NOTES 1 5 Start rS Repeat Start Stop A Acknowledge 2 L From Master to Slave From Slave to Master Figure 14 3 2 Interface Data Format Figure 14 4 illustrates the data transfer on the I2C bus Acknowledgement Acknowledgement Signal from Receiver Signal from Receiver 9 ACK Byte Complete Interrupt Clock Line Held Low by within Receiver receiver and or transmitter Figure 14 4 Data Transfer on the I2C Bus SA
566. s on the device Pin value The value depends on the pin status Reset Value Conventions Expression Description 0 Clears the register field 1 Sets the register field x Don t care condition Warning Some bits of control registers are driven by hardware or write operation only As a result the indicated reset value and the read value after reset might be different SAMSUNG ELECTRONICS 4412 UM 1 Product Overview Product Overview 1 1 Introduction Exynos 4412 is 32 bit RISC cost effective low power performance optimized and Coretex A9 Quad Core based micro processor solution for smart phone applications The memory system has dedicated DRAM ports and Static Memory port The dedicated DRAM ports support LPDDR2 interface for high bandwidth Static Memory Port supports NOR Flash and ROM type external memory and components To reduce the total system cost and enhance the overall functionality Exynos 4412 includes many hardware peripherals such as 24 bit true color LCD controller Camera Interface MIPI DSI CSI 2 System Manager for power management slimbus interface HSI four UARTs 24 channel DMA Timers General I O Ports three 125 S PDIF eight IIC BUS interface three HS SPI USB Host 2 0 USB 2 0 Device operating at high speed 480 Mbps two USB HSIC four SD Host and high speed Multimedia Card Interface Chip to Chip interface and four PLLs fo
567. s register bits at the time of key pressed or key released or both cases when it enables two interrupt conditions To prevent the switching noises keypad interface comprise of internal debouncing filter Figure 17 1 illustrates the key matrix interface external connection guide SAMSUNG ELECTRONICS 17 1 ex 4412 UM 17 Keypad Interface Figure 17 1 Key Matrix Interface External Connection Guide SAMSUNG ELECTRONICS 425 27 4412 UM 17 Keypad Interface 17 2 Debouncing Filter Supports debouncing filter for keypad interrupt of any key input The filtering width is approximately 62 5 usec FCLK two clock when the FCLK 1 32 kHz The keypad interrupt key pressed or key released to the CPU in software scan mode is an ANDed signal of the all row input lines after filtering Figure 17 2 illustrates the internal debouncing filter operation FILTER_IN FILTER_OUT Filter width FCLK two clock FCLK two clock width Filter Clock FCLK is a FLT_CLK or the division of that clock FLT_CLK is come from System Controller OSC_IN or USB_XTI Figure 17 2 Internal Debouncing Filter Operation 17 3 Filter Clock It divides the KEYPAD interface debouncing filter clock from FLT_CLK that is OSC_IN You can set compare value for 10 bit up counter KEYIFFC When filter enable bit FC EN is HIGH filter clock divider is ON The frequency of FCLK is frequency of FLT_CLK KEYIFFC 1 x 2 On the
568. s that the divider is changing SAMSUNG ELECTRONICS 5 100 IT 4412 UM 5 Clock Management Unit 5 10 1 81 CLK DIV STAT FSYS2 e Base Address 0 1003 0000 e Address Base Address 0xC648 Reset Value 0 0000 0000 RSV er DIVMMC3 PRE Status DIV MMC3 PRE 24 0 Stable 1 Status that the divider is changing Sw fo DIVMMC3 Stats DIV MMC3 16 0 Stable 1 Status that the divider is changing DIVMMC2_PRE Status DIV MMC2 PRE 0 Stable 1 Status that the divider is changing Avo mn nene mw DIVMMC2 Status DIV MMC2 0 Stable 1 Status that the divider is changing 5 10 1 82 CLK DIV STAT FSYS3 e Base Address 0x1003 0000 e Address Base Address 0xC64C Reset Value 0x0000 0000 RSVD 0 10 DIVMMC4 PRE Status DIV MMC4 PRE 0 Stable 1 Status that the divider is changing SE fm DIVMMC4 Status DIV MMC4 0 Stable 1 Status that the divider is changing SAMSUNG ELECTRONICS 5 101 ex 4412 UM 5 Clock Management Unit 5 10 1 83 CLK_DIV_STAT_PERILO Base Address 0x1003 0000 e Address Base Address 0xC650 Reset Value 0x0000 0000 RSV erm DIVUART4 Status DIV UART4 16 0 Stable 1 Status that the divider is changing SE usa mw DIVUART3 Status DIV UART3 12 0 Stable 1 Status that the divider is changing SE ma
569. sable bit 0 Disables 1 Enables 12C bus Tx Rx interrupt pending flag You cannot write this bit to 1 If you read this bit as 1 the I2CSCL is tied to Low and the 2 is stopped To resume the operation write this bit as 0 0 1 No interrupt is pending If Read 2 Clears pending condition and resumes the operation If Write 1 1 Interrupt is pending If Read 2 N A If Write 12C bus transmit clock prescaler 4 bit prescaler value determines the I2C bus transmit clock frequency according to the formula given here Tx clock I2CCLK I2CCON 3 0 1 7 14 14 4412 UM 14 Inter Integrated Circuit 2 2 interrupt occurs when a 1 byte Transmit or Receive operation is complete Alternatively the ACK period is finished b A general call or a Slave address match occurs c Bus arbitration fails 3 adjust the setup time SDA before SCL rising edge ensure to Write I2CDS before clearing the 12C interrupt pending bit 4 12 6 determines 2 Tx clock can vary by SCL transition time When I2CCON 6 0 I2CCON 3 0 0x0 or 0x1 is not available 5 When I2CCON 5 0 I2CCON 4 does not operate correctly Therefore set 12 5 1 even if you do not use the 2 interrupt SAMSUNG ELECTRONICS 14 15 II 4412 UM Base Address Base Address Base Address Base Address Base Address Base Address Base Address Base Address
570. se Address 0x1381 0000 e Base Address 0x1382 0000 e Base Address 0x1383 0000 Base Address 0x1384 0000 e Address Base Address 0x0024 Reset Value 0 0000 0000 mw __ mose URXHn 7 0 Receives data for UARTn NOTE When an overrun error occurs CPU must Read URXHn If not the next received data makes overrun error even though it clears the overrun bit of UERSTATn 13 6 1 11 UBRDIVn 0 to 4 e Base Address 0x1380_0000 e Base Address 0x1381_ 0000 e Base Address 0x1382_0000 e Base Address 0x1383_0000 e Base Address 0x1384 0000 e Address Base Address 0x0028 Reset Value 0x0000_0000 mw fema UBRDIVn 15 0 Baud rate division value 0 0000 NOTE When UBRDIV value is set to 0 UFRACVAL value does not affect UART Baud rate SAMSUNG ELECTRONICS 13 26 II 4412 UM 13 Universal Asynchronous Receiver and Transmitter 13 6 1 12 UFRACVALn 0 to 4 e Base Address 0x1380 0000 Base Address 0x1381_0000 Base Address 0x1382_0000 e Base Address 0x1383 0000 Base Address 0x1384 0000 e Address Base Address 0x002C Reset Value 0 0000 0000 av RE UFRACVALn 3 0 Determines the fractional part of Baud rate divisor 0 0 1 UART Baud Rate Configuration You can use the value stored in the Baud rate divisor UBRDIVn and divisor fractional value UFRACVALn to determine the serial Tx Rx clock rate Baud rate as DIV_VAL UBRDI
571. seed EN ___ Gating all clocks for LCD BLK FIMDO MIEO and ETT am METT EN Gating all clocks for CAM_BLK FIMC0 FIMC1 FIMC2 CLK CAM RW and FIMC3 SAMSUNG ELECTRONICS 5 119 ex 4412 UM 5 Clock Management Unit 5 10 1 102 CLKOUT_CMU_TOP e Base Address 0x1003 0000 e Address Base Address 0 Reset Value 0x0001 0000 RSV Enable CLKOUT ENB_CLKOUT 16 0 Disables 1 Enables RSVD 15 14 Reewed Divide Ratio DIV_RATIO 13 8 Divide ratio DIV_RATIO 1 MUX 3 00000 FOUT 00001 VPLL_FOUT 00010 SCLK_HDMI24M 00011 SCLK USBPHYO 00101 SCLK HDMIPHY 00110 AUDIOCDCLKO 00111 AUDIOCDCLK1 01000 AUDIOCDCLK2 01001 SPDIF EKTCLK 01010 ACLK 160 01011 ACLK 133 01100 ACLK 200 01101 ACLK 100 01110 SCLK 01111 SCLK G3D MUA SEL 4 0 10000 ACLK 400 MCUISP 10001 PCLK 10010 CAM PCLK 10011 5 RXBYTECLKHSO 2L 10100 S RXBYTECLKHSO 4L 10101 RX HALF BYTE CLK CSISO 10110 RK HALF BYTE CLK CSIS1 10111 2 SCLK JPEG 11000 SCLK PWM ISP 11001 2 SCLK SPIO ISP 11010 SCLK SPI1 ISP 11011 2 SCLK UART ISP 11100 SCLK MIPIHSI 11101 SCLK HDMI 11110 2 SCLK FIMDO 11111 SCLK PCMO SAMSUNG ELECTRONICS 5 120 4412 UM 5 Clock Management Unit 5 10 1 103 CLKOUT CMU TOP DIV STAT e Base Address 0x1003 0000 e Address Base Address 0xCA04 Reset Value 0
572. selection hold on 0000 0 Clock 0001 1 Clocks Tcoh 15 12 Rw 0010 2 Clocks 0011 3 Clocks 1100 12 Clocks 1101 13 Clocks SAMSUNG ELECTRONICS 9 8 4412 UM 9 SROM Controller 1110 14 Clocks 1111 15 Clocks Address holding time after nGCSn 0000 0 Clock 0001 1 Clocks 0010 2 Clocks 0011 3 Clocks 1100 12 Clocks 1101 13 Clocks 1110 14 Clocks 1111 15 Clocks NOTE More 1 2 cycles according to bus status Page mode access cycle at Page mode 0000 0 Clock 0001 1 Clocks 0010 2 Clocks Tacp 7 4 RW 0011 3 Clocks 1100 12 Clocks 1101 13 Clocks 1110 14 Clocks 1111 15 Clocks aeva Page mode configuration 00 Normal 1 Data 01 4 Data 10 Reserved 11 Reserved SAMSUNG ELECTRONICS 9 9 ex 4412 UM 10 NAND Flash Controller NAND Flash Controller 10 1 Overview Due to the recent increase in the prices of NOR flash memory and the moderately priced DRAM and NAND flash customers prefer to execute boot code on NAND flash and execute the main code on DRAM The boot code in Exynos 4412 can be executed on external NAND flash copies NAND flash data to DRAM To validate the NAND flash data Exynos 4412 includes hardware Error Correction Code ECC After the NAND flash content is copied to DRAM main program will be executed on DRAM 10 2 Features The features of NAND flash controller are Auto boot The boo
573. served OxF EXT_INT7 2 0 0 Input 0 1 Output 0 2 12C_0_SCL GPD1CON 1 7 4 0x3 MIPIO ESC 0 00 0 4 to Reserved OxF EXT_INT7 1 0 0 Input 0 1 Output 0 2 126 0 SDA GPD1CON 0 3 0 0x3 MIPIO BYTE CLK 0x00 0x4 to OxE Reserved OxF EXT INT7 0 SAMSUNG ELECTRONICS 4 40 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 38 GPD1DAT e Base Address 0x1140_0000 e Address Base Address 0x00C4 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPD1DAT 3 0 3 0 output port then pin state should be same as the 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 2 39 GPD1PUD Base Address 0x1140_0000 e Address Base Address 0x00C8 Reset Value 0x0055 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down GPD1PUDIn RW 0 2 Reserved 0x0055 0x3 Enables Pull up 4 3 2 40 GPD1DRV Base Address 0x1140_0000 e Address Base Address Reset Value 0x00 0000 23 16 Reserved should be zero W GPD1DRV n n 2n 1 2n R 0x0000 0103 SAMSUNG ELECTRONICS 4 41 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 41 GPD1CONPDN e Base Address 0x1140_0000 e Address Base Address 0 0000 Reset Value 0x0000 0x0 Outp
574. served Reserved RSV 054 These bits indicate what type of ECC is used 000 Disables 8 12 16 bit ECC 001 Reserved 010 Reserved ECCType 3 0 011 8 bit ECC 512B 100 12 bit ECC 101 16 bit ECC 512B 110 Reserved 111 Reserved 10 7 3 2 NFECCCONT e Base Address 0 0 2 0000 e Address Base Address 0x0020 Reset Value 00000 0000 MLC ECC encoding completion interrupt control 0 Disables interrupt 1 Enables interrupt MLC ECC decoding completion interrupt control 0 Disables interrupt 1 Enables interrupt RSVD EnbMLCEncInt 25 EnbMLCDecint 24 2 encoding decoding control 0 Decoding used for read 1 Encoding used for page program W 1 Initatze man EOC devoderjencoder Wite onyy 0 CTI Reset EOC log o ls E 2 9 Ls RW R SAMSUNG ELECTRONICS 10 29 II 4412 UM 10 NAND Flash Controller 10 7 3 3 NFECCSTAT e Base Address OXOCE2 0000 e Address Base Address 0x0030 Reset Value 0x0000_0000 Indicates the 8 bit ECC decoding engine 15 searching whether a error exists or not ECCBusy 31 0 Idle 1 Busy mv 71 When ECC encoding is finished this value set and issue interrupt if EncodeDone is enabled The EncodeDone 25 RWX NFMLCECCO have valid values To clear this write 1
575. served 0x5555 0x3 Enables Pull up 4 3 3 110 GPM3DRV e Base Address 0x1100_0000 e Address Base Address 0x02CC Reset Value 0x00_0000 23 16 Reserved Should be zero W GPM3DRV n n 2n 1 21 0x0000 0107 SAMSUNG ELECTRONICS 4 186 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 111 GPM3CONPDN e Base Address 0x1100 0000 e Address Base Address 0x02D0 Reset Value 0x0000 0 0 Outputs 0 2n 1 21 0 1 Outputs 1 0107 0 2 Input 2599 0 3 Previous state 4 3 3 112 GPM3PUDPDN e Base Address 0x1100_0000 e Address Base Address 0x02D4 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down 0107 zi 0x2 Reserved 990 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 187 ex 4412 UM 4 3 3 113 GPM4CON e Base Address GPM4CON 7 GPM4CONJ 6 5 GPM4CON 2 GPM4CON 1 0x1100_0000 31 28 SAMSUNG ELECTRONICS 4 General Purpose Input Output GPIO Control Address Base Address 0 02 0 Reset Value 0 0000 0000 0 0 Input 0 1 Output 0 2 CAM SPI MOSI 0x3 CAM_GPIO 17 0 4 to Reserved OxF EXT_INT12 7 0 0 Input 0 1 Output 0 2 CAM SPI MISO 0x3 CAM_GPIO 16 0 4 to Reserved EXT INT12 6 0 0 Input 0 1 Output 0
576. sion of Rx DMA FSM 1 Enables suspension of Rx DMA FSM Interrupt request type 2 0 Pulse UART requests interrupt when the Tx buffer 1 empty in the non FIFO mode or when it reaches the trigger level of Tx FIFO in the FIFO mode 1 Level Interrupt is requested when Tx buffer is empty in the non FIFO mode or when it reaches the trigger level of Tx in the FIFO mode Interrupt request type 2 0 Pulse UART requests interrupt when instant Rx buffer receives data in the non FIFO mode or when it reaches the trigger level of Rx FIFO in the FIFO mode 1 Level UART requests interrupt when Rx buffer receives data in the non FIFO mode or when it reaches the trigger level of Rx FIFO in the FIFO mode Enables disables Rx time out interrupts when you enable UART FIFO The interrupt is a receive interrupt 0 Disables 1 Enables Enables the UART to generate an interrupt upon exception such as a break frame error parity error or overrun error during a receive operation 0 Does not generate receive error status interrupt 1 Generates receive error status interrupt To set this bit to 1 triggers the UART to enter the loop back mode This mode 1 for test purposes only 0 Normal operation 1 Loop back mode To set this bit to 1 triggers UART to send a break during 1 frame time This bit is automatically cleared after sending the break signal 0 Normal transmit 1 Sends the break signal Dete
577. sk 1 Pass Gating all clocks for SPI1 0 Mask 1 Pass Gating all clocks for SPIO 0 Mask Gating all clocks for 1 PCM1 22 RW 0 Mask 1 Pass W Gating all clocks for 1252 0 Mask 0 1 1 Pass 27 4412 UM 5 Clock Management Unit Gating all clocks for 1227 1207 RW 0 Mask 1 Pass Gating all clocks for 12206 l2C6 W 0 Mask 1 Pass 1265 1264 1263 RW 0 Mask 1 Pass Gating all clocks for 2 2 RW 0 Mask I W 0 Mask I2C1 RW 0 Mask Gating all clocks for UART3 CLK UART3 0 Mask 1 Pass 0 1 1 Pass Gating all clocks for 2 4 RW 0 Mask 0 1 1 Pass 0 1 1 Pass Gating all clocks 2 1 RW 0 Mask 0 1 1 Pass 2 0 0 1 1 Pass ASVD fo Gating all clocks for UART2 UART2 0 Mask 0 1 1 Pass Gating all clocks for UARTI CLK UARTI 0 Mask 0 1 1 Pass Gating all clocks for 2 5 Gating all clocks for 12203 CLK_12C2 Gating all clocks for 2 0 Gating all clocks for UART4 CLK_UART4 0 Mask 1 Pass Gating all clocks for UARTO CLK UARTO 0 Mask 1 Pass SAMSUNG ELECTRONICS 5 118 en 4412 UM 5 Clock Management Unit 5 10 1 101 CLK GATE BLOCK e Base Address 0x1003 0000 e Address Base Address 0xC970 Reset Value OxFFFF_FFFF all clocks for GPS BLK GPS CLK GPS RW 0 Mask mv 18 Re
578. sponds to COLVAL 23 0 COMPKEY F 23 0 RW If some position bit is set then it disables the position bit of COLVAL NOTE Set BLD PIX 1 ALPHA SEL 0 A FUNC 0x2 and B FUNC 0x3 to enable alpha blending using color key 16 5 3 41 W2KEYCON1 e Base Address 0x11C0 0000 e Address Base Address 0x014C Reset Value 0x0000 0000 COLVAL F 23 0 Specifies color key value for transparent pixel effect SAMSUNG ELECTRONICS 16 98 ex 4412 UM 16 Display Controller 16 5 3 42 W3KEYCONO e Base Address 0x11C0_0000 e Address Base Address 0x0150 Reset Value 0x0000_0000 Enables blending 0 Disables blending RW KEYBEENSE 28 1 Enables blending using original alpha for non key area and KEY_ALPHA for key area Enables Color Key Chroma key KEYEN_F 25 RW 0 Disables color key 1 Enables color key Controls Color key Chroma key direction 0 the pixel value matches foreground image with COLVAL then it displays the pixel from background image DIRCON_F 24 RW only in OSD area 1 If the pixel value matches background image with COLVAL then it displays the pixel from foreground image only in OSD area Each bit corresponds to COLVAL 23 0 If some position bit is set then it disables the position bit of COLVAL NOTE Set BLD PIX 1 ALPHA SEL 0 A FUNC 0x2 and B FUNC 0x3 to enable alpha blending using color key 16 5 3 43 W3KEYCON1 e Base Address
579. ss Reset Value 0x0000 0000 RSVD Reserved 0x0000000 0 0 Not occur PENDIS 5 0 1 Interrupt occurs 0 0 Not occur 4 0x1 Interrupt occurs EXT INT16 3 RWX 0 0 Not occur Ox1 Interrupt occurs EXT INT16 PEND 2 2 RWX 0X0 Not occur 0 1 Interrupt occurs EXT INT16 PEND 1 1 RWX 0 0 Not occur 0 1 Interrupt occurs EXT INT16 PEND 0 RWX 0 0 Not occur 0 1 Interrupt occurs SAMSUNG ELECTRONICS 4 115 IT 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 144 EXT_INT21_PEND e Base Address 0x1140_0000 e Address Base Address 0x0A40 Reset Value 0x0000 0000 EXT 21 PENDI 7 7 RWX 0x0 Not occur WA 0 1 Interrupt occurs EXT 21 PEND 6 bep 0 1 Interrupt occurs EXT INT21 PEND 5 y am 0 1 Interrupt occurs EKT INT21 PEND 4 4 RWX 0 0 Not occur 0 1 Interrupt occurs EXT INT21 PEND 3 SM E a enr 0 1 Interrupt occurs EXT_INT21_PEND 2 2 RWX 0 0 Not occur 25 0 1 Interrupt occurs EXT INT21 PEND 1 0 1 Interrupt occurs EXT INT21 PEND 0 RWX 0x0 Not occur 0 1 Interrupt occurs 4 3 2 145 EKT INT22 PEND e Base Address 0x1140_0000 e Address Base Address 0x0A44 Reset Value 0x0000 0000 EXT INT22 PEND 4 4 RWX 0 0 Not occur 0 1 Interrupt occurs 0x0 Not occur 3 ES O
580. ss 0xC634 Reset Value 0x0000 0000 RSVD man fo DIVMIPIO PRE Status DIV MIPIO PRE 20 0 Stable 1 Status that the divider is changing SE vem mo DIVMIPIO Status DIV 0 16 0 Stable 1 Status that the divider is changing SE eee A DIV_MDNIE _ DIVMDNIE PWMO PRE Status PWMO_PRE 12 0 Stable 1 Status that the divider is changing SE map mew om DIVMDNIE PWMO Status DIV MDNIE PWMO 0 Stable 1 Status that the divider is changing SE mose E DIVMDNIEO Status DIV MDNIEO 4 0 Stable 1 Status that the divider is changing ASV rese o AN DIVFIMDO Status DIV FIMDO 0 Stable 1 Status that the divider is changing SAMSUNG ELECTRONICS 5 97 ex 4412 UM 5 Clock Management Unit 5 10 1 77 CLK_DIV_STAT_ISP e Base Address 0x1003 0000 e Address Base Address 0xC638 Reset Value 0 0000 0000 RSVD wa _ 00 DIVUART ISP Status DIV UART ISP 28 0 Stable 1 Status that the divider is changing SE ren Jo DIVSPI1 ISP PRE Status DIV SPI1 ISP PRE 20 0 Stable 1 Status that the divider is changing SE ___ ov DIVSPI1 ISP Status DIV SPH ISP 16 0 Stable 1 Status that the divider is changing SE mss ov DIVSPIO ISP PRE Status DIV SPIO ISP PRE 0 Stable 1 Status that the divider is changing SE Rene o DIVSPIO ISP Status
581. t GPIO Control 4 3 3 123 EKT INT27CON e Base Address 0x1100 0000 e Address Base Address 0x0718 Reset Value 0x0000_0000 Gus o mv ne Sets signaling method of EXT_INT27 6 0 0 Low level 0x1 High level EXT_INT27_CON 6 26 24 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0x4 Triggers both edge 0 5 to 0 7 Reserved 85 9 gp eee Sets signaling method of EXT_INT27 5 0 0 Low level 0x1 High level EXT INT27 CON 5 22 20 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0x7 Reserved 85 0 mp fe Sets signaling method of EXT INT27 4 0 0 Low level 0 1 High level EXT INT27 CON 4 18 16 RW 0x2 Triggers falling edge 0 3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved 85 0 mq fe Sets signaling method of INT27 3 0 0 Low level 0 1 High level EXT 27 CON 3 14 12 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved 85 0 mi fasen fe Sets signaling method of EXT INT27 2 0 0 Low level 0 1 High level EXT INT27 CON 2 10 8 RW 0x2 Triggers falling edge 0x3 Triggers rising edge 0 4 Triggers both edge 0 5 to 0 7 Reserved SAMSUNG ELECTRONICS 4 200 ex 4412 UM 4 General Purpose Input Output GPIO Control signaling
582. t GPIO Control 4 3 3 230 PDNEN e Base Address 0x1100 0000 e Address Base Address OxOF80 Reset Value 0x00 RSV a 0 Automatically by power down mode Power down mode pad state enable register 0 PADs Controlled by normal mode This bit is set to 1 automatically when system enters PDNEN R into Power down mode and clears by writing 0 to this 0x0 bit or cold reset After wake up from Power down mode this bit maintains value 1 until writing 0 1 PADs Controlled by Power Down mode control registers SAMSUNG ELECTRONICS 4 288 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 4 Part 3 4 3 4 1 GPZCON e Base Address 0x0386_0000 e Address Base Address 0x0000 Reset Value 0 0000 0000 0 0 Input 0 1 Output GPZCON 6 27 24 e MS 0x00 0 4 to OxE Reserved OxF EXT INT50 6 0 0 Input 0 1 Output GPZCON 5 23 20 s E M 0x00 0 4 to OxE Reserved OxF EXT INT50 5 0 0 Input 0 1 Output GPZCON 4 19 16 e E Em 0x00 0 4 to OxE Reserved OxF EXT INT50 4 0 0 Input 0 1 Output GPZCON 3 15 12 2 EC IN 0x00 0 4 to OxE Reserved OxF EXT INT5O 3 0 0 Input 0 1 Output 0 2 12S_0_LRCK GPZCON 2 11 8 0x3 PCM 0 FSYNC 0x00 0 4 to OxE Reserved OxF EXT INT50 2 0 0 Input 0 1 Output 0 2 125 0 CDCLK GPZCON 1 7 4 0x3 PCM 0 EXTCLK 0x00 0 4 to OxE Reserved OxF EXT IN
583. t Groups of Interrupt Combiner Combined Interrupt Combiner Group ID Source Name Interrupt Source Source Block i INTGO Reserved Reserved 3 TZASC1 1 2 TZASC1 0 INTG1 TZASC TZASC 1 TZASCO 1 TZASCO 0 PARITYFAILSC 1 PARRINTR PARRDINTR PARITYFAILO INTG2 F4 C TIO TEMO nCTIIRQ O CPUO PMUIRQ O PARITYFAIL1 SAMSUNG ELECTRONICS 7 3 IU 5 4 S 2 1 5 4 3 2 1 PARITYFAILSCU O PARITYFAIL1 INTG3 FADCTI1 PMU1 SYSMMU 2D 0 PARITYFAILO SYSMMU 5 SYSMMU FIMC3 0 INTG4 SYSMMUJ7 0 System MMU SYSMMU FIMC2 0 SYSMMU FIMC1 0 E 2 4412 UM 7 Interrupt Combiner ERAS mo 8 SYSMMU 15 8 System MMU SYSMMU ROTATOR 7 i INTG6 SYSMMU 23 16 System MMU 10 5 5 7 jer INTG7 SYSMMU 31 24 System MMU j SYSMMU ROTATOR m Pemo INTG9 PPMU 14 8 PPMU PPMU_MFC_MO SAMSUNG ELECTRONICS 7 4 27 7 PPMU IMAGE 6 PPMU CAMIF PPMU 0 RIGHT 4 PPMU D LEFT MO PPMU 7 0 PPMU 3 PPMU 4412 UM 7 Interrupt Combiner Combined Interrupt DMC1 DMCO MIU THIS L2CACHE INTG11 INTG12 MCT MIPI UART4 HSI MIPI UART4 UART CPU nIRQOUTT 0 E INTG13 i Reserved
584. t code is transferred to internal SRAM during reset After the transfer the boot code will be executed on the SRAM e flash memory interface Supports 512 Bytes 2 4 KB and 8 KB pages e Software mode You can directly access flash memory for example this feature can be used in read erase program NAND flash memory e Interface Supports 8 bit flash memory interface bus e Generates detects and indicates hardware ECC software correction e Supports both Single Level Cell SLC and Multi Level Cell MLC NAND flash memories e ECC Supports 1 4 8 12 16 bit ECC e SFR interface Supports byte half word word access to Data and ECC data registers and Word access to other registers SAMSUNG ELECTRONICS 10 1 ex 4412 UM 10 NAND Flash Controller 10 3 Functional Description 10 3 1 Block Diagram Figure 10 1 illustrates the Flash Controller block diagram ECC Gen NAND FLASH AHB Interface nWE Slave AF Control amp RnB State Machine 1 00 1 07 Figure 10 1 Flash Controller Block Diagram SAMSUNG ELECTRONICS 10 2 IT 4412 UM 10 NAND Flash Controller 10 3 2 NAND Flash Memory Timing Figure 10 2 illustrates the CLE and ALE timing TACLS 1 TWRPHO 0 TWRPH1 0 TACLS TWRPHO TWRPH1 gt lt gt CLE ALE COMMAND AD
585. t controller consists of the group interrupt requests from the interrupt combiner and uncombined interrupt sources 7 2 Features The features of Interrupt Combiner are e 116 interrupt source inputs e 18 group interrupt outputs e Enables or masks each interrupt source in a group e Provides the status of interrupt source in a group before interrupt masking e Provides the status of interrupt source in a group after interrupt masking e Provides the status of group interrupt output after interrupt masking and combining SAMSUNG ELECTRONICS 7 1 ex 4412 UM 7 Interrupt Combiner 7 3 Functional Description 7 3 1 Block Diagram There is a interrupt combiner in Exynos 4412 The interrupt combiner combines a few interrupts source into 18 group interrupt request outputs The inputs of the GIC unit outside the ARM Core unit connect to the group interrupt request outputs Figure 7 1 illustrates the block diagram of interrupt combiner ARM Core GIC PL390 Interrupt Source SPI 127 0 Non Combined da Ue Combined Interrupt Interrupt 31 0 127 32 Interrupt Figure 7 1 Block Diagram of Interrupt Combiner SAMSUNG ELECTRONICS 7 2 x 4412 UM 7 Interrupt Combiner 7 4 Interrupt Sources This section includes e Interrupt Combiner 7 4 1 Interrupt Combiner Table 7 1 describes the interrupt groups of interrupt combiner Table 7 1 Interrup
586. t enable bit __ 1 Enables Me TOS Sets the corresponding interrupt enable bit to 1 If you __ MCT_G2 8 RW set interrupt enable bit interrupt combiner serves 2 MCT GO RW Write 0 Does not change the current setting 1 Sets the interrupt enable bit to 1 RSVD 3 2 Read The current interrupt enable bit MIPI_HSI 0 Masks IKUY SAMSUNG ELECTRONICS 7 22 4412 UM 7 Interrupt Combiner 7 6 2 14 IECR3 Base Address 0x1044 0000 e Address Base Address 0x0034 Reset Value 0x0000 0000 M Reset Name ne en Ge DECERRINTR 19m o SLVERRINTR 30 Clears the corresponding interrupt enable bit to 0 If you clear the interrupt enable bit interrupt combiner will 0 ERRRDINTR 29 mask the interrupt ERRRTINTR 28 RW Write 0 Does not change the current setting O ERRWDINTR 27 1 Clears the interrupt enable bit to 0 EN Read The current interrupt enable bit 0 ERRWTINTR 2 RW ERRWTINTR 26 RW 0 Masks SCUEVABORT 2 9 _ RSvD Ex CPU nIRQOUT 1 22 RW Clears the corresponding interrupt enable bit to If _NIRQOUT_ 22 RSVD Pu you clear the interrupt enable bit interrupt combiner will ME 21 mask the interrupt RSVD 20 EN Write 0 Does not change the current setting Low RSVD 19 EN 1 Clears the interrupt enable bit to 0 Read The current interrupt enable bit RSVD 1 RSvo
587. t is requested during the receive operation It automatically sets this bit to 1 automatically if an overrun error occurs during the receive operation 0 No overrun error occurs during the receive operation 1 Overrun error occurs Interrupt is requested during the receive operation 3 2 0 Overrun Error NOTE It clears these bits UERSATn 3 0 to 0 when UART error status is Read SAMSUNG ELECTRONICS 13 23 II 4412 UM 13 Universal Asynchronous Receiver and Transmitter 13 6 1 7 UFSTATn 0 to 4 e Base Address 0x1380 0000 Base Address 0x1381 0000 Base Address 0x1382 0000 e Base Address 0x1383 0000 Base Address 0x1384 0000 e Address Base Address 0x0018 Reset Value 0x0000_0000 Rvo 125 automatically sets this bit to 1 when the transmitted FIFO is full during transmit operation Tx FIFO Full 24 2 B Tx FIFO 23 16 Number of data in Tx FIFO Count i NOTE This field is set to 0 when Tx FIFO is full Rx FIFO 9 This bit is set to 1 when Rx FIFO contains invalid data that Error results from frame error parity error or break signal It automatically sets this bit to 1 when the received FIFO is full duri i ti Rx FIFO Full 8 ha AA operation 1 Full mwo aa FIFO 7 0 Number of data in Rx FIFO Count NOTE This field is set to 0 when Rx FIFO is full SAMSUNG ELECTRONICS 13 24 ex 4412 UM 13 Universal Asynchronous Receive
588. t on the interrupt enable bits to 0 This feature will make it easy to address resource sharing issues in a multi processor system There are several interrupt sources in an interrupt group If an interrupt enable bit is 0 then it masks the corresponding interrupt All the interrupt sources in an interrupt group including the masked interrupt sources are ORed to form a combined interrupt request signal The interrupt combiner connects the combined group interrupt request output to an input of a GIC You can show each interrupt source status before an interrupt enable bit masks it by reading ISTRn register You can show the combined group interrupt request output signal by reading CIPSRO register SAMSUNG ELECTRONICS 7 8 IT 4412 UM 7 Interrupt Combiner 7 6 Register Description 7 6 1 Register Map Summary Base Address 0x1044 0000 Register onse Description Reset Value Interrupt Combiner SAMSUNG ELECTRONICS 7 9 x 4412 UM 7 Interrupt Combiner 7 6 2 Interrupt Combiner 7 6 2 1 IESRO Base Address 0x1044 0000 e Address Base Address 0x0000 Reset Value 0x0000_0000 RSVD pu Reed om 30 Sets the corresponding interrupt enable bit to 1 If PMUIRQ_ISP 29 you set the interrupt enable bit interrupt combiner TMU ______ 28 serves the interrupt request Write 0 Does not change the current setting 27 RW 1 Sets the interrupt enable bit to 1 PMU
589. t prescaler and dead zone or dead zone length 0 0004 Specifies the timer configuration register 1 that controls five 0 0000_0000 select bit SAMSUNG ELECTRONICS 11 14 ex 4412 UM 11 Pulse Width Modulation Timer 11 5 1 1 TCFGO e Base Address 0x139D_0000 PWM Base Address 0x1216 0000 PWM ISP e Address Base Address 0x0000 Reset Value 0x0000 0101 RSVD 31 24 Reserved Bits Dead zone length 23 16 Dead zone length 15 8 Prescaler 1 value for Timer 2 3 and 4 7 0 Prescaler 0 value for timer 0 and 1 Timer Input Clock Frequency PCLK fprescaler value 1 divider value prescaler value 1 to 255 divider value 1 2 4 8 16 Dead zone length 0 to 254 NOTE If deadzone length is set as real Dead Zone length is n 1 0 to 254 SAMSUNG ELECTRONICS 11 15 II 4412 UM 11 Pulse Width Modulation Timer 11 5 1 2 TCFG1 e Base Address 0x139D 0000 PWM Base Address 0x1216 0000 PWM ISP e Address Base Address 0x0004 Reset Value 0x0000 0000 Selects Mux input for PWM timer 4 0000 1 1 0001 1 2 Divider MUX4 19 16 0010 1 4 0011 1 8 0100 1 16 Selects Mux input for PWM timer 3 0000 1 1 2 0001 1 2 MUX 15 12 RW ivider MUX3 15 12 0010 1 4 0011 1 8 0100 1 16 Selects Mux input for PWM timer 2 0000 1 1 an 0001 1 2 D MUX2 11 RW ivider MU 11 8 0010 1 4 0011 1 8 0100 1 16 Sele
590. t result of hardware scan 0x0000 0000 for second key register KEYIFHSC 0x001C Specifies KEYPAD interrupt for hardware scan status and 0x0000 0000 clear register SAMSUNG ELECTRONICS 17 12 ex 4412 UM 17 Keypad Interface 17 8 1 1 KEYIFCON e Base Address 0x100A 0000 e Address Base Address 0x0000 Reset Value 0x000F 0000 H_CNT 31 16 Counter value for hardware scan column to row interval 16 hF Reeva Hi Z mode scan enable for hardware scan 0 Normal scan driving low and high iu 1 Hi Z mode scan driving low and Hi Z In Hi Z mode it should disable GPIO internal pull down Select hardware scan software scan SEL HSCAN 0 Software scan RSVD 1 Hardware scan Reserved poe 10 bit counter for debouncing digital filter clock enable 0 Disables Does not use division counter 1 Enables uses division counter 7 4 KEYPAD input port debouncing filter enable DF EN 2 RW 0 Disables 1 Enables 1 Enables KEYPAD input port falling edge key pressed interrupt RW 0 Disables INT_R_EN INT_F_EN NOTE Selects both edge interrupt when both INT_F_EN and INT_R_EN are set KEYPAD input port rising edge key released interrupt RW 0 Disables 1 Enables SAMSUNG ELECTRONICS 17 13 ex 4412 UM 17 Keypad Interface 17 8 1 2 KEYIFSTSCLR e Base Address 0x100A 0000 e Address Base Address 0x0004 Reset Value
591. te FIFO for UARTO 64 byte FIFO for UART1 and 16 byte FIFO for UART2 3 4 Programmable baud rate IrDA 1 0 SIR 115 2 Kbps mode Loop back mode for testing Norrinteger clock divides in Baud clock generation SAMSUNG ELECTRONICS 1 9 ex 4412 UM 1 Product Overview e USB 2 0 Device supports Complies to USB 2 0 Specification Revision 1 0 High speed up to 480 Mbps On chip USB transceiver USB Host 2 0 supports With the USB Host 2 0 High speed up to 480 Mbps On chip USB transceiver e HS MMC SDIO Interface supports Multimedia Card Protocol version 4 3 compatible HS MMC SD Memory Card Protocol version 2 0 compatible DMA based or interrupt based operation 128 word FIFO for Tx Rx Four ports HS MMC or four ports SDIO e SPI Interface supports With three Serial Peripheral Interface Protocol version 2 1 1 independent 64 Word FIFO for SPIO and 16 Word FIFO DMA based interrupt based operation e Chip to Chip Interface supports 8 16 bit configurable Tx and Rx for each 200 MHz DDR interface Base address and size of the accessed DRAM are configurable e GPIO SAMSUNG ELECTRONICS 1 10 ex 4412 UM 1 Product Overview 1 2 7 System Peripheral The features of system peripheral are Real Time Clock Full clock features sec min hour date day month and year 32 768 kHz operation Alarm
592. tegrated Circuit 14 4 1 Start and Stop Conditions When the I2C bus interface is inactive it is usually in Slave mode Alternatively the interface should be in Slave mode before detecting a Start condition on the SDA line a Start condition is initiated with High to Low transition of the SDA line when the clock signal of SCL is High When controller changes the interface state to master mode SDA line initiates data transfer and generates SCL signal A Start condition transfers 1 byte serial data through SDA line and a Stop condition terminates the data transfer A Stop condition is a Low to High transition of the SDA line while SCL is High The master generates Start and Stop conditions 12C bus goes into the busy state when a master or slave device generates a start condition Alternatively a Stop condition makes the 12C bus idle state When a master initiates a Start condition it should send a slave address to notify the slave device 1 byte of address field includes a 7 bit address 1 bit transfer direction indicator which shows Write or Read When bit 8 is 0 it indicates a Write operation Transmit Operation when bit 8 is 1 it indicates a request for data Read Receive Operation The master transmits Stop condition to complete the transfer operation If the master wants to continue the data transmission to the bus it should generate another Start condition and slave address In this manner there can be various format
593. ter gt SAMSUNG ELECTRONICS 4 15 4412 UM 4 General Purpose Input Output GPIO Control Desea Reset Vale SAMSUNG ELECTRONICS 4 16 ex 4412 UM 4 General Purpose Input Output GPIO Control e Base Address 0x0386_0000 Offset Desenpton Reservaiue Port group GPIO group Z GPZ configuration register GPZPUDPDN 0x0014 Be ai GPZ power down mode pull up pull down 0x0000 EXT_INT50_CON 0x0700 External interrupt EXT INT50 configuration register 0x0000 0000 EXT INT50 FLTCONO 0x0800 External interrupt EXT INT50 filter configuration register 0 0x0000 0000 EXT INT50 MASK 0x0900 External interrupt EXT INT50 mask register 0x0000 007F EXT INT50 PEND 0x0AO0 External interrupt EXT INT50 pending register 0x0000 0000 r 0x0B08 Current service register 0x0000_0000 EXT_INT_SERVICE PEND XD OxOBOC Current service pending register 0x0000_0000 po 0x0B10 External interrupt group fixed priority control register 0x0000 0000 EXT INT50 FIXPRI 0x0B14 External interrupt 50 fixed priority control register 0 0000 0000 PDNEN OxOF80 Power down mode pad configure register Base Address Ox106E 0000 EXT INT50 FLTCON1 0x0804 External interrupt EXT INT50 filter configuration register 1 0x0000 0000 GPVOPUDPDN 0x0014 Q power down mode pull up pull down 0 0000 GPV1PUDPDN 0x0034 GPV1 power down mode pull up pull down 0 0000 SAM
594. terface Master mode only PCM interface AC97 Audio Interface supports Independent channels for stereo PCM In stereo PCM Out and mono MIC In 16 bit stereo 2 channel audio Variable sampling rate AC97 Codec interface 48 kHz and below 97 full specification SPDIF Interface TX only supports Linear up to 24 bit per sample support Non Linear PCM formats such MPEG1 and MPEG2 support 2x24 bit buffers that are alternately filled with data 125 Bus Interface supports Three 12S bus for audio codec interface with DMA based operation Serial and 8 16 24 bit per channel data transfers 125 MSB justified and LSB justified data format 5 1 channel A Various bit clock frequency and codec clock frequency support 16 24 32 and 48fs of bit clock frequency o 256 384 512 and 768fs of codec clock One port for 5 1 channel 125 in audio subsystem and two ports for 2 channel 125 12C Bus Interface supports Eight Multi Master IIC Bus Serial 8 bit oriented and bi directional data transfers can be made at up to 100 Kbps in the standard mode Up to 400 Kbps in the fast mode MIPI Slim bus Interface supports 6 ports Each port has 16 entry FIFO with 32 bit width UART supports Four UART with DMA based or interrupt based operation 5 bit 6 bit 7 bit or 8 bit serial data transmit receive Rx Tx independent 256nby
595. tex A9 processor PMUPRIV 0 User mode 1 Privileged mode Specifies signals mode each Cortex A9 processor 0 Asymmetric signal 1 Symmetric signal Returns security status of the Cortex A9 processor PMUSECURE 0 Non secure state 0x0 1 Secure state 5 10 1 149 PTM_STATUS e Base Address 0x1004_0000 e Address Base Address 0x5420 Reset Value 0x0000_0000 PTMPWRUPO for CPUO is active PTMIDLENACKO for CPUO is an idle state indicator PTMIDLEnACK1 for CPU1 is an idle state indicator SAMSUNG ELECTRONICS 5 156 x 4412 UM 5 Clock Management Unit 5 10 1 150 CLK DIV ISPO e Base Address 0 1004 0000 e Address Base Address 08300 Reset Value 000 0000 ASV ee GECCE ISPDIV1 Clock Divider Ratio 6 4 ISPDIV1_CLK ACLK_200 ISPDIV1_RATIO 1 ISPDIVO Clock Divider Ratio ROA 2 0 ISPDIVO_CLK ACLK_200 ISPDIVO_RATIO 1 gt 5 10 1 151 CLK_DIV_ISP1 Base Address 0x1004 0000 e Address Base Address 0x8304 Reset Value 0x0000_0000 RSV ou msme 09 MCUISPDIV1 Clock Divider Ratio MCUISPDIV1 10 8 RW MCUISPDIV1_CLK _RATIO MOUTMCUISPDIVO CLK MCUISPDIV1 RATIO 1 a ea Dm MCUISPDIVO Clock Divider Ratio 6 4 RW MCUISPDIVO CLK ACLK 400 MCUIPS MCUISPDIVO RATIO 1 mw a Rm Dm MPWM Clock Divider Ratio 2 2 0 RW MPWMDIV_CLK MOUTISP
596. the divider is changing SAMSUNG ELECTRONICS 5 130 x 4412 UM 5 Clock Management Unit 5 10 1 113 CLK DIV STAT DMC1 e Base Address 0x1004 0000 e Address Base Address 0x0604 Reset Value 0x0000 0000 RSVD res reens DIVDPM Status DIV_DPM 24 0 Stable 1 Status that the divider is changing SE wom fo DIVDVSEM Status DIV DVSEM 16 0 Stable 1 Status that the divider is changing SE ___ fo DIVC2C ACLK Status DIV C2C ACLK 12 0 Stable 1 Status that the divider is changing SE ma ne fo DIVPWI Status DIV PWI 0 Stable 1 Status that the divider is changing SE ms ___ fo DIVC2C status DIV C2C 4 0 Stable 1 Divider is changing ASV DIVG2D status DIV G2D ACP 0 Stable 1 Divider is changing SAMSUNG ELECTRONICS 5 131 ex 4412 UM 5 Clock Management Unit 5 10 1 114 GATE IP e Base Address 0x1004 0000 e Address Base Address 0x0900 Reset Value OxFFFF_FFFF Gating all clocks for GPIOC2C CLK_GPIOC2C 31 RW 0 Mask 0 1 1 Pass CLK_ASYNC CPU Gating all clocks for ASYNC_CPU_XIUR _XIUR 0 Mask x 1 Pass Gating all clocks for ASYNC_C2C_XIUL 0 Mask 1 Pass Gating all clocks for C2C 0 Mask 0 1 1 Pass Gating all clocks for SMMUG2D ACP 0 Mask 0 1 1 Pass Gating all clocks for G2D ACP 0 Mask 1 Pass 28
597. the input clock diagram for SPI System Controller XusbXTI SCLK_HDMI27M SCLK USBPHYO DiVspio 2 PRE SCLK SPI SCLK USBPHY1 SCLK HDMIPHY MOUT pp 2 1 256 Max 100MHz SOLKupu SCLKepu gt Figure 15 2 Input Clock Diagram for SPI Exynos 4412 provides SPI with a variety of clocks As illustrated in the Figure 28 8 the SPI uses SCLK SPI clock which is from clock controller You can also select SCLK SPI from various clock sources To select SCLK SPI refer to Chapter 7 Clock Controller for more information NOTE SPI has an internal 2x clock divider You should configure SCLK SPI to have a double of the SPI operating clock frequency SAMSUNG ELECTRONICS 15 5 ex 4412 UM 15 Serial Peripheral Interface 15 4 10 Description The IO description table lists the external signals between the SPI and external device The unused SPI ports used as General Purpose l O ports Refer to General Purpose l O chapter for more information Sww vo XspiCLK is the serial clock used to control time of data SPI 0 CLK XspiCLK_0 mios transfer SPI 1 CLK In Out XspiCLK_1 muxed Out when used as master SPI 2 CLK Xi2s2CDCLK In when used as slave Slave selection signal All data Tx Rx sequences are NES executed if XspiCS is low KspiCSn 0 SPI 1 55 In Out XspiCSn_1 muxed Out when used as master SPI 2 55 Xi2s2LRCK In when used as slave This p
598. the interrupt enable bit interrupt PEN 21 combiner will mask the interrupt DMCO_PPC_PEREV_A 20 RW Write 0 Does not change the current setting 19 1 Clears the interrupt enable bit to 0 Read The current interrupt enable bit RW L2CACHE 18 RW 2 TIMER 17 1 Enables GPIO AUDIO 16 Turu PPMUL MPO MI 14 Clears the corresponding interrupt enable bit to PPMU MFC MO 113 0 If you clear the interrupt enable bit interrupt PPMU 3D 12 combiner will mask the interrupt PPMU TV MO 11 Write 0 Does not change the current setting 1 Clears the interrupt enable bit to 0 PPMU_FILE D_M0 10 RW Read The current interrupt enable bit PPMU_ISP_MX 0 Masks PPMU IMAGE PPMU MO Clears the corresponding interrupt enable bit to 0 If you clear the interrupt enable bit interrupt PPM combiner will mask the interrupt PPMU D LEFT MO RW Write 0 Does not change the current setting PPMU_ACPO_MO 1 Clears the interrupt enable bit to 0 Read The current interrupt enable bit 2 RW PPMU_XIU_R 1 Enables SAMSUNG ELECTRONICS 7 19 ex 4412 UM 7 Interrupt Combiner 7 6 2 11 ISTR2 e Base Address 0x1044 0000 e Address Base Address 0x0028 Reset Value Undefined RSVD 5128 _ Reewd LCDO 3 27 Interrupt pending status LCD0 2 26 RO The corresponding interrupt enable bit does not EN LCDOH R aff
599. ting all clocks for SMMUFIMDO CLK SMMUFIMDO 0 Mask 1 Pass Gating all clocks for DSIMO CLK_DSIMO 3 0 Mask 1 Pass Gating clocks for CLK MDNIEO 2 0 Mask 1 Pass Gating all clocks for MIEO CLK_MIEO 1 0 Mask 1 Pass Gating all clocks for FIMDO CLK FIMDO RW 0 Mask 1 Pass SAMSUNG ELECTRONICS 5 112 en 4412 UM 5 Clock Management Unit 5 10 1 97 CLK GATE IP ISP e Base Address 0x1003 0000 e Address Base Address 0xC938 Reset Value OxFFFF_FFFF Gating SCLK clocks for UART_ISP 0 Mask 1 Pass Gating SCLK clocks for SPI1_ISP CLK_SPI1_ISP_SCLK 0 Mask 1 Pass CLK_SPIO_ISP_SCLK 0 Mask 1 Pass Gating SCLK clocks for PWM_ISP CLK_PWM_ISP_SCLK 0 Mask 1 Pass Gating SCLK clocks for SPIO_ISP 0 1 SAMSUNG ELECTRONICS 5 113 IT 4412 UM 5 Clock Management Unit 5 10 1 98 GATE 5 5 e Base Address 0x1003 0000 e Address Base Address 0xC940 Reset Value OxFFFF_FFFF Gating all clocks for PPMUFILE CLK PPMUFILE 17 0 Mask 1 Pass Gating all clocks for CLK_NFCON 16 0 Mask 1 Pass Gating all clocks for CLK ONENAND 15 0 Mask 1 Pass SE mq ea fm Gating all clocks for USB Device CLK_USBDEVICE 13 RW 0 Mask 1 Pass Gating all clocks for USB HOST CLK USBHOST 12 RW 0 Mask 1 Pass Gating all clocks for SROM CLK_SROMC 11 RW 0 Mask Gating all clocks f
600. tion SAMSUNG ELECTRONICS 5 151 ex 4412 UM 5 Clock Management Unit 5 10 1 145 PWR CTRL e Base Address 0 1004 0000 e Address Base Address 0x5020 Reset Value 0x0000_04FF RSVD en DIVCORE2 on WFI WFE CORE2_RATIO 30 28 RW Set DIVCORE2 clock divider ratio when both ARM cores are in Wait For Interrupt Event state Sw eran Forces CoreSight clocks to toggle when the CSCLK AUTO 20 RW debugger is attached ENB_IN_DEBUG 0 Disables 1 Enables Sw mp ea ov DIVCORE on WFIAWFE CORE RATIO 18 16 RW Set DIVCORE clock divider ratio when both ARM cores are in Wait For Interrupt Event state 85 0 1577 Gating F4D Coresight clocks both ARM cores in F4D_CORESIGHT 10 _ IDLE mode 0 Mask 1 Enable ARMCLK Down feature when both ARM cores are in IDLE mode for DIVCORE2 0 Disables 1 Enables Enable ARMCLK Down feature when both ARM cores are in IDLE mode for DIVCORE 0 Disables 1 Enables Use ARM CORE3 STANDBYWFE to change ARMCLK frequency in ARM IDLE state Use ARM CORE2 STANDBYWFE to change ARMCLK frequency in ARM IDLE state Use ARM CORE1 STANDBYWFE to change ARMCLK frequency in ARM IDLE state Use ARM COREO STANDBYWFE to change ARMCLK frequency in ARM IDLE state Use ARM CORE3 STANDBYWFI to change ARMCLK frequency in ARM IDLE state Use ARM CORE2 STANDBYWFI to change ARMCLK frequency in ARM IDLE state Use ARM CORE1 STANDBYWFI to change
601. to 0 SYSMMU_FIMC_DRC 1 R SYSMMU_FIMC_ISP 1 R R R SYSMMU_FIMC_LITEO 1 9 isl SYSMMU_FIMC_LITEO 1 MCT_L3 R 0 If you clear the interrupt enable bit interrupt Se MESEN combiner will mask the interrupt W W Read The current interrupt enable bit 0 Masks W 1 Enables W W SYSMMU FIMG FD 0 RW Write 0 Does not change the current setting SYSMMU 1 Clears the interrupt enable bit to 0 Read Th le bit SYSMMU_FIMC_ISPIO ead c interrupt enable bit SYSMMU FIMC LITEO O 1 Enables SYSMMU_FIMC_LITEO 0 0 RW SAMSUNG ELECTRONICS 7 27 Ea Co o 58 o NE IT 4412 UM 7 Interrupt Combiner 7 6 2 19 ISTR4 Base Address 0x1044 0000 e Address Base Address 0x0048 Reset Value Undefined RSVD si CPU nIRQOUT 3 80 R PARITYFAILSCU3 29 Interrupt pending status PARITYFAIL3 28 The corresponding interrupt enable bit does not affect this pending status SEE PES 27 RO 0 The interrupt is not pending CPU PMUIRQ 3 26 1 The interrupt is pending RSVD MCT Lo 24 RSVD 231 CPU nIRQOUT 2 22 R PARITYFAILSCU2 21 Interrupt pending status PARITYFAL2 The corresponding interrupt e
602. to 1 RW 0x2 Reserved oe 0 3 Enables Pull up SAMSUNG ELECTRONICS 4 142 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 37 GPL2CON e Base Address 0x1100 0000 e Address Base Address 0x0100 Reset Value 0x0000_0000 0 0 Input 0 1 Output 0 2 GNSS GPIO 7 0x3 KP_COL 7 anne 0 4 to OxE Reserved OxF EXT_INT29 7 0 0 Input 0 1 Output 0 2 GNSS_GPIO 6 0x3 KP 0x00 0x4 to Reserved OxF EXT_INT29 6 0x0 Input 0x1 Output 0x2 GNSS_GPIO 5 0x3 anne 0 4 to OxE Reserved OxF EXT INT29 5 0 0 Input 0 1 Output 0 2 GNSS GPIO 4 0 3 KP_COL 4 0 4 to Reserved OxF EXT INT29 4 0x0 Input 0x1 Output 0 2 GNSS_GPIO 3 0x3 anne 0 4 to OxE Reserved OxF EXT_INT29 3 0 0 Input 0 1 Output 0 2 GNSS_GPIO 2 0x3 KP_COL 2 oe 0 4 to Reserved OxF EXT INT29 2 0 0 Input 0 1 Output 0 2 GNSS_GPIO 1 GPL2CON 1 0x3 0x00 0 4 to OxE Reserved OxF EXT INT29 1 0 0 Input SAMSUNG ELECTRONICS 4 143 ex GPL2CON 7 31 28 4412 UM 4 General Purpose Input Output GPIO Control 0 2 GNSS GPIO 0 0x3 _ 0x4 to Reserved OxF EXT INT29 0 SAMSUNG ELECTRONICS 4 144 27 4412 UM 4 General Purpose Input Output
603. tputs 0 2n 1 2n 0 1 Outputs 1 PMID 0107 RW 0 2 Input 0 3 Previous state 4 3 5 6 Base Address 0 106 0000 e Address Base Address 0x0014 Reset Value 0x0000 0 0 Disables Pull up Pull down 2n 1 20 0 1 Enables Pull down 0107 RW 0x2 Reserved Oxu 0x3 Enables Pull up SAMSUNG ELECTRONICS 4 300 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 7 GPV1CON Base Address Ox106E 0000 e Address Base Address 0x0020 Reset Value 0x0000 0000 0 0 Input 0 1 Output GPV1CON 7 31 28 RW 0 2 C2C RXD 15 0 00 0x3 to Reserved EXT INT31 7 0 0 Input 0 1 Output GPV1CON 6 27 24 RW 0 2 C2C RXD 14 0 00 0x3 to Reserved OxF EXT_INT31 6 0 0 Input 0 1 Output GPV1CON 5 23 20 0 2 C2C RXD 13 0 00 0x3 to Reserved OxF EXT_INT31 5 0 0 Input 0 1 Output GPV1CON 4 19 16 0 2 C2C_RXD 12 0 00 0x3 to Reserved EXT INT31 4 0 0 Input 0 1 Output GPV1CON 3 15 12 0 2 2 RXD 11 0 00 0x3 to Reserved OxF EXT INT31 3 0 0 Input 0 1 Output GPV1CON 2 11 8 0 2 C2C RXD 10 0 00 0x3 to Reserved OxF EXT_INT31 2 0 0 Input 0 1 Output GPV1CON 1 7 4 0 2 C2C_RXDI9 0 00 0x3 to Reserved OxF EXT INT31 1 0 0 Input 0 1 Output GPV1CON 0 3 0 0 2 C2C_RXDI
604. trigger level of Tx FIFO When data count of Tx FIFO 1 less than or equal to the trigger level Tx interrupt occurs Channel 0 000 0 byte 001 32 bytes 010 64 bytes 011 96 bytes 100 128 bytes 101 160 bytes 110 192 bytes 111 224 bytes Channel 1 4 000 0 byte Trigger Level 010 16 bytes 011 24 bytes 100 32 bytes 101 40 bytes 110 48 bytes 111 56 bytes Channel 2 3 000 0 byte 001 2 bytes 010 4 bytes 011 6 bytes 100 8 bytes 101 10 bytes 110 12 bytes 111 14 bytes CI Determines the trigger level of FIFO When data count of Rx FIFO is more than or equal to the trigger level Rx Rx FIFO interrupt occurs RW Trigger Level 19 4 Channel 0 000 32 byte 001 64 bytes gt SAMSUNG ELECTRONICS 13 17 4412 UM 13 Universal Asynchronous Receiver and Transmitter 010 96 bytes 011 128 bytes 100 160 bytes 101 192 bytes 110 224 bytes 111 256 bytes Channel 1 4 000 8 byte 001 16 bytes 010 24 bytes 011 32 bytes 100 40 bytes 101 48 bytes 110 56 bytes 111 64 bytes Channel 2 3 000 2 byte 001 4 bytes 010 6 bytes 011 8 bytes 100 10 bytes 101 12 bytes 110 14 bytes 111 16 bytes mi ne po Tx FIFO Automatically clears after resetting FIFO Reset 2 0 Normal 1 Tx FIFO reset Automatically clears after resetting 1 5 0 Normal 1 Rx FIFO r
605. trol register CLKOUT CMU __ DIV_STAT OxCA04 Clock divider status for CLKOUT OxCAOS to RSVD 0x0004 Reserved SAMSUNG ELECTRONICS 0x0000_0000 Undefined 0x0000_0000 Undefined OxFFFF_FFFF Undefined OxFFFF_FFFF OxFFFF_FFFF OxFFFF_FFFF OxFFFF_FFFF Undefined OxFFFF FFFF OxFFFF FFFF OxFFFF FFFF Undefined OxFFFF FFFF OxFFFF FFFF Undefined OxFFFF FFFF Undefined 0x0001 0000 0x0000 0000 Undefined 4412 UM 5 Clock Management Unit Base Address 0x10040000 MPLL_LOCK 0x0008 Controls PLL locking period for MPLL 0x0000 OFFF 0 000 to MPLL CONO 0x0108 Controls PLL output frequency for MPLL 0x0064 0300 MPLL CON1 0x010C Controls PLL AFC 0x0080 3800 0x0110 to CLK SRC DMC 0x0200 Selects clock source for CMU DMC 0x0001 0000 0x0204 to SRC MASK 0 0300 Clock source mask for DMC BLK 0x0001 0000 0x0304 to CLK_MUX_STAT_DMC 0x0400 Clock status for CMU_DMC 0x1110 1111 0x0404 to DIV DMCO 00500 Sets clock divider ratio for CMU 0x0000 0000 DIV DMC1 0x0504 Sets clock divider ratio for 0x0000 1000 0x0508 to CLK_DIV_STAT_DMCO 0x0600 Clock divider status for CMU 0x0000_0000 CLK_DIV_STAT_DMC1 0x0604 Clock divider status for CMU 0x0000_0000 0x0608 to CLK GATE BUS DMCO 00700 Control gating of clock for DMC_BLK OxFFFF FFFF CLK GATE BUS DMC1 0x0704 Control gating of APB clock for DMC BLK O
606. ts signaling method of EXT_INT30 2 0 0 Low level 0x1 High level EXT_INT30_CON 2 10 8 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT30 1 0 0 Low level 0x1 High level EXT_INT30_CON 1 6 4 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT30 0 0x0 Low level 0x1 High level EXT INT30 CON 0 2 0 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0 7 Reserved SAMSUNG ELECTRONICS 4 315 ex 4412 UM 4 General Purpose Input Output Control 4 3 5 36 EXT_INT31CON Base Address Ox106E 0000 e Address Base Address 0x0704 Reset Value 0x0000 0000 RSV ey eee To Sets signaling method of EXT INT31 7 0 0 Low level 0 1 High level EXT INT31 CON 7 30 28 RW 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0x5 to 0x7 Reserved 85 2 ea 99 Sets signaling method of EXT INT31 6 0 0 Low level 0 1 High level EXT INT31 CON 6 26 24 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved SVO reme Jo Sets signaling method of EXT INTS31 5 0 0 Low level 0 1 High level EXT INT31 CON 5 22 20 RW 0 2 Triggers Fa
607. ts the time gap between turn off and turn on of two different switching devices This time gap prohibits the two switching devices turning On simultaneously even for a very short duration TOUT 0 specifies the PWM output nTOUT 0 specifies the inversion of the TOUT 0 If you enable the dead zone the output wave form of TOUT_0 and nTOUT 0 become TOUT 0 DZ and nTOUT 0 DZ Dead zone interval cannot turn on TOUTO DZ and nTOUT 0 DZ simultaneously For functional accuracy it should set the dead zone length smaller than compare counter value Figure 11 8 illustrates the waveform when it enables Dead Zone feature TOUTO nTOUTO DEADZONE INTERVAL TOUTO DZ nTOUTO DZ Figure 11 8 Waveform when a Dead Zone Feature is Enabled SAMSUNG ELECTRONICS 11 12 ex 4412 UM 11 Pulse Width Modulation Timer 11 4 I O Description TOUT 0 PWMTIMER TOUT 0 XpwmTOUT 0 TOUT 1 PWMTIMER TOUT 1 XpwmTOUT 1 TOUT 2 PWMTIMER TOUT 2 XpwmTOUT 2 TOUT 3 PWMTIMER TOUT 3 XpwmTOUT 3 NOTE Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals SAMSUNG ELECTRONICS 11 13 II 4412 UM 11 Pulse Width Modulation Timer 11 5 Register Description 11 5 1 Register Map Summary Base Address 0x139D_0000 PWM Base Address 0x1216 0000 PWM ISP Specifies the timer configuration register 0 that configures the Tree 0x0000 two 8 bi
608. ts various color formats such as RGB 1 to 24 BPP and YCbCr 4 4 4 only local bus You can program the display controller to support the different requirements on screen that associates with the number of horizontal and vertical pixels data line width for the data interface interface timing and refresh rate Display controller transfers the video data generates the necessary control signals such as RGB VSYNG RGB_HSYNC RGB_VCLK RGB VDEN SYS 50 SYS_CS1 and SYS WE Additionally generating control signals display controller contains data ports for video data RGB VD 23 0 and SYS VD Figure 16 1 illustrates the block diagram of display controller FIMD 6 0 VTIME RGB TV _i80 lt FIFO IF mal 8bit 3 E gt gt 56x64 gt gt FIFO 5 ch Blender 5 ch Overlay YUV IF Dithering PIXSCHED 5 ch VRV Color Gain 2bit RGB I F gt ARBITER DMA 180 AHB SFRFILE Slave VF Figure 16 1 Block Diagram of Display Controller SAMSUNG ELECTRONICS 16 1 x 4412 UM 16 Display Controller 16 2 Features The features of the display controller include RGB Interface 24 bit Parallel 8 bit Serial Video Output Interface Indirect i80 interface Write Back interface Supports i80 and Write Back Dual Output Mod Supports RGB and Write Back Supports 8 BPP bit per pixel palletized color Su
609. u can re enable the output of the non glitch free clock MUX This is done to ensure that there are no glitches resulting due to the clock change selection The outputs of non glitch free MUXES are masked by the clock source mask control registers The clock source mask control registers are identified with keyword that starts with CLK SRC MASK Figure 5 1 and Figure 5 2 illustrates clock divider that indicates possible dividing value in parentheses The dividing values can be changed by clock divider registers during run time Some clock dividers have only one dividing value and you are not allowed to change the dividing value Figure 5 1 illustrates the Exynos 4412 Clock Generation Circuit CPU BUS DRAM and ISP Clocks diagram Figure 5 2 illustrates the Exynos 4412 Clock Generation Circuit Special Clocks diagram SAMSUNG ELECTRONICS 5 10 ex 4412 UM 5 Clock Management Unit Since APLL output is a very fast clock clock gating cell is added not to let it toggle when it is not used al 9 synchronous glitch free normal mux 1 mux See 23 for more details on mux type 1 1 8 Eu D PERIPHCLK TENER cssvs Voltage domain gt D crossing D PCuK Paired inverters are N 1 Do TSVALUECLK added before after the line CMU DMC Synchronous clocks EY As es
610. ue 0 0000 0000 SHD VIDWO2ADD2 e Address Base Address 0x410C Reset Value 0x0000 0000 SHD VIDWOSADD2 e Address Base Address 0x4110 Reset Value 0x0000 0000 SHD_VIDWO4ADD2 Description Reset Value OFFSIZE F 25 13 Specifies virtual screen offset size that is the number of byte shadow Specifies virtual screen page width number of byte PAGEWIDTH F 12 0 This value defines the width of view port in the frame shadow SAMSUNG ELECTRONICS 16 135 ex 4412 UM 16 Display Controller 16 5 6 Palette Ram 16 5 6 1 Win0 Palette Ram Access Address not SFR Base Address 0x11C0_0000 e Address Base Address 0 2400 0 0400 Reset Value 0 0000 0000 e Address Base Address 0x2404 0x0404 Reset Value 0x0000 0000 e Address Base Address 0x27FC 0x07FC Reset Value 0 0000 0000 Specifies Window O Palette entry 0 address Undefined sx Specifies Window 0 Palette entry 1 address Undefined 0 0_27 T 0 0 07 Specifies Window O Palette entry 255 address Undefined 16 5 6 2 Win1 Palette Ram Access Address not SFR Base Address 0x11C0_0000 e Address Base Address 0x2800 0x0800 Reset 0x0000_0000 e Address Base Address 0x2804 0x0804 Reset Value 0x0000 0000 e Address Base Address 0x2BFC 0x0BFG Reset Value 0x0000 0000 EM Specifies Window 1 Palette entry 0 address Undefined 0 0 2804 agi 0 0 0804 Speci
611. ue case 0 o NOTE R G 7 4 ALPHAO_R B _H 3 0 at VIDOSD3C ALPHAO_R G B 3 0 ALPHAO_R G B _L 3 0 at VIDW3ALPHAO SAMSUNG ELECTRONICS 16 122 x 4412 UM 16 Display Controller 16 5 3 77 VIDW3ALPHA1 e Base Address 0x11C0_0000 e Address Base Address 0x0238 Reset Value 0x0000_0000 Nam Type Description Reset Value RD bal mesorved 19 16 Specifies Red Alpha lower value case 1 11 8 Specifies Green Alpha lower value case AEN 1 mo ____ sees ALPHAT B LF 3 0 RW Specifies Blue Alpha lower value case AEN 1 0 NOTE ALPHA1_R G B 7 4 ALPHA1_R G B _H 3 0 VIDOSD3C ALPHA1_R G B 3 0 ALPHA1_R G L 3 0 EVIDW3ALPHA1 G G 16 5 3 78 VIDW4ALPHAO e Base Address 0x11C0_0000 e Address Base Address 0x023C Reset Value 0x0000_0000 Name Twe Description Reset vauc RS p reena po Ree 0 19 16 Specifies Red Alpha lower value case AEN 0 Reewd 9 11 8 Specifies Green Alpha lower value case AEN 0 mess po ALPHAD B L F 18 0 RW Species Blue Alpha lower value ease AEN 0 0 NOTE ALPHAO R G 7 4 ALPHAO G H 3 0 at VIDOSD4C ALPHAO G B 3 0 ALPHAO G B L 3 0 at VIDW4AL
612. upt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 4 337 4412 UM 4 3 5 57 EXT_INT32_PEND Base Address Ox106E 0000 e Address Base Address 0x0A08 Reset Value 0x0000 0000 RSVD EXT INT32 PEND 7 EXT INT32 PEND 6 EXT INT32 PEND 5 EXT INT32 PEND 4 EXT INT32 PEND 3 EXT INT32 PEND 2 EXT INT32 PEND 1 EXT INT32 PEND 0 5 4 3 RWX 2 RWX 1 SAMSUNG ELECTRONICS 4 General Purpose Input Output GPIO Control 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 0 0 Not occur 0x1 Interrupt Occurs 4 338 4412 UM 4 General Purpose Input Output GPIO Control 4 3 5 58 EXT_INT33_PEND Base Address Ox106E 0000 e Address Base Address Reset Value 0x0000 0000 0 0 Not occur EAT MS Too 0 1 Interrupt Occurs 0 0 Not occur NISS SPENDISI 0 1 Interrupt Occurs 0 0 Not occur EXT_INT33_ 5 0 1 Interrupt Occurs 0 0 Not 0 1 Interrupt Occurs 0 0 Not occur EXT_INT33_PEND 4 4 EXT INT33 PEND 3 3 EX s 0 0
613. ure port as input port then corresponding bit is pin state When configuring as GPJ1DAT 4 0 4 0 output port the pin state should be same as the 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 2 77 GPJ1PUD Base Address 0x1140_0000 e Address Base Address 0x0268 Reset Value 0x0155 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down GPJ1PUD n 0104 RW 0x2 Reserved 0x0155 0x3 Enables Pull up 4 3 2 78 GPJ1DRV e Base Address 0x1140_0000 e Address Base Address 0x026C Reset Value 0x00_ 0000 23 16 Reserved Should be zero W GPJ1DRV n n 2 1 21 0x0000 n 0to 4 SAMSUNG ELECTRONICS 4 59 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 79 GPJ1CONPDN Base Address 0x1140_0000 e Address Base Address 0x0270 Reset Value 0x0000 Description Reset Value 0x0 Outputs O 2n 1 2n 0x1 Outputs 1 0104 RW 0x2 Input 0 3 Previous state 4 3 2 80 GPJ1PUDPDN Base Address 0x1140_0000 e Address Base Address 0x0274 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down Set 0104 RW 0x2 Reserved Oxu 0x3 Enables Pull up SAMSUNG ELECTRONICS 4 60 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 81 Address 0x1140 0000 e Addres
614. urns to 1 b0 C2 ENLOCAL_F 0 Disables 1 Enables Enables Channel 1 Local Path C1_ENLOCAL_F 0 Disables 1 Enables Enables Channel 0 Local Path CO ENLOCAL F 0 Disables 1 Enables Enables Channel 4 C4 EN F 0 Disables 1 Enables Enables Channel 3 C3 EN F 0 Disables 1 Enables SAMSUNG ELECTRONICS 16 81 ex 4412 UM 16 Display Controller 1 Enables Enables Channel 1 0 Disables 1 Enables Enables Channel 0 0 Disables 1 Enables SAMSUNG ELECTRONICS 16 82 IT 4412 UM 16 Display Controller 16 5 3 15 WINCHMAP2 Base Address 0x11C0 0000 e Address Base Address 0x003C Reset Value 0 7051 7051 Selects Channel 4 s channel 001 Window 0 010 Window 1 H4FISEL E sd FI 101 2 Window 2 110 Window 3 111 Window 4 Selects Channel 3 s channel 001 Window 0 010 Window 1 H3FISEL ERE 101 Window 2 110 Window 3 111 Window 4 Selects Channel 2 s channel 001 Window 0 010 Window 1 H2FISEL G gt 52221 101 Window 2 110 Window 3 111 Window 4 Selects Channel 0 s channel 001 Window 0 010 Window 1 CHOFISEL 18 1 118 181 101 Window 2 110 Window 3 111 Window 4 Selects Window 4 s channel 001 Channel 0 010 Channel 1 WA4FISEL 14 12 101 Channel 2 110 Channel 3 111 Channel 4 Selects Window 3 channel 001 Channel 0 010 Channel 1 W3FISEL 11 ors 101 Channel 2 110 Channel
615. urst Maximum Length 00 16 word burst 1 RW 19 31 01 8 burst 10 4 word burst RSVD ALPHA MUL F Selects blending category BLD PIX F RW 0 Per plane blending 1 Per pixel blending Reserved NOTE This bit should be set to 0 Specifies Multiplied Alpha value mode 0 Disables multiplied mode 1 Enables multiplied mode When ALPHA is 1 set BLD PIX 1 ALPHA SEL 1 and BPPMODE _F 5 2 4b1101 or 4 b1110 NOTE Alpha value alpha pixel from data x ALPHAO R G B Selects Bits Per Pixel BPP mode in Window image 0000 1 BPP 0001 2 BPP 0010 4 0011 8 BPP palletized 0100 8 BPP non palletized A 1 R 2 G 3 B 2 0101 16 BPP non palletized R 5 G 6 B 5 0110 16 BPP non palletized A 1 R 5 G 5 B 5 0111 16 BPP non palletized 1 R 5 G 5 B 5 1000 Unpacked 18 BPP non palletized R 6 G 6 B 6 1001 Unpacked 18 BPP non palletized A 1 R 6 G 6 B 5 1010 Unpacked 19 BPP non palletized A 1 R 6 G 6 BPPMODE_F 5 2 RW 6 1011 Unpacked 24 non palletized R 8 G 8 B 8 1100 Unpacked 24 non palletized A 1 R 8 G 8 B 7 1101 Unpacked 25 BPP non palletized A 1 R 8 G 8 B 8 1110 Unpacked 13 non palletized A 1 R 4 G 4 B 4 1111 Unpacked 15 BPP non palletized R 5 G 5 B 5 NOTE 1 1101 Supports unpacked 32 BPP non palletized A 8 R 8 G 8 B 8 for per pixel blending 2 1110 Supports 16
616. ut 0 2 Reserved GPX1CON 4 19 16 0 00 0 5 ALV DBG 8 0 6 to Reserved OxF WAKEUP_INT1 4 0 0 Input 0 1 Output 0 2 Reserved GPX1CON 3 15 12 2 0x00 0 5 ALV DBG 7 0x6 to OxE Reserved WAKEUP INT 1 3 0 0 Input GPX1CON 2 11 8 0x00 0x3 KP COLI2 SAMSUNG ELECTRONICS 4 255 x 4412 UM 4 General Purpose Input Output GPIO Control 0x4 Reserved 0x5 ALV_DBG 6 0 6 to Reserved OxF WAKEUP_INT1 2 0 0 Input 0 1 Output 0x2 Reserved 0x3 KP COL 1 GPX1CON 1 7 4 RW 0 4 Reserved 0 5 ALV DBG 5 0x6 to OxE Reserved WAKEUP INT1 1 0 0 Input 0 1 Output 0x2 Reserved 0 3 _ GPX1CON 0 3 0 RW 0 4 Reserved 0 5 ALV DBG 4 0x6 to OxE Reserved OxF WAKEUP_INT1 0 SAMSUNG ELECTRONICS 4 256 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 199 GPX1DAT e Base Address 0x1100 0000 e Address Base Address 0x0C24 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPX1DAT 7 0 7 0 output port then pin state should be same as 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 3 200 GPX1PUD Base Address 0x1100 0000 e Address Base Address 0x0C28 Reset Value 0x5555
617. ut Output GPIO Control 4 3 3 171 EXT_INT27_PEND e Base Address 0x1100 0000 e Address Base Address 0x0A18 Reset Value 0x0000 0000 0x0 Not occur EAT NGT 6 0 1 Interrupt occurs 0 0 Not occur EM NGT PENDIS 5 0 1 Interrupt 5 EXT 27 PEND 4 4 RV NOGEN Ox1 Interrupt occurs EXT 27 PEND 3 3 RWX D 2 EXT INT27 PEND 2 pr 959 0 1 Interrupt occurs 0 0 Not occur 0 1 Interrupt occurs EXT 27 PEND 0 RWY 0 0 Not occur 0 1 Interrupt occurs 4 3 3 172 EKT INT28 PEND EXT INT27 PEND 1 1 RWX Base Address 0x1100 0000 e Address Base Address 1 Reset Value 0x0000 0000 EXT INT28 PEND 1 1 RWX 0 0 Not occur m 0 1 Interrupt occurs EXT INT28 PEND 0 RWX 0x0 Not occur T 0 1 Interrupt occurs SAMSUNG ELECTRONICS 4 240 ex 4412 UM 4 3 3 173 EKT INT29 PEND e Base Address 0x1100 0000 e Address Base Address 0x0A20 Reset Value 0x0000 0000 RSVD EXT INT29 PEND 7 EXT INT29 PEND 6 EXT INT29 PEND 5 EXT INT29 PEND 4 EXT INT29 PEND 3 EXT INT29 PEND 2 EXT INT29 PEND 1 EXT INT29 PEND 0 5 4 3 RWX 2 RWX 1 SAMSUNG ELECTRONICS 4 General Purpose Input Output GPIO Control 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0 Not occur 0x1 Interrupt occurs 0 0
618. uts O 2n 1 2n 0x1 Outputs 1 SPD 0103 Input 552 0 3 Previous state 4 3 2 42 GPD1PUDPDN Base Address 0x1140_0000 e Address Base Address 0x00D4 Reset Value 0x0000 0x0 Disables Pull up Pull down 2n 1 2n 0x1 Enables Pull down 0103 di 0x2 Reserved 990 0x3 Enables Pull up SAMSUNG ELECTRONICS 4 42 IT 4412 UM 4 3 2 43 GPFOCON e Base Address 0x1140 0000 e Address Base Address 00180 Reset Value 0 0000 0000 GPFOCON 7 GPFOCON 6 GPFOCON 5 GPFOCON 4 31 28 SAMSUNG ELECTRONICS 0 0 0 1 Output 0 2 LCD VD 3 0x3 to Reserved EXT_INT13 7 0 0 Input 0 1 Output 0 2 LCD VD 2 0x3 to Reserved OxF EXT INT13 6 0 0 Input 0 1 Output 0 2 LCD VD 1 0x3 to Reserved OxF EXT INT13 5 0 0 Input 0 1 Output 0 2 LCD VD 0 0x3 to Reserved EXT_INT13 4 0 0 Input 0 1 Output 0 2 LCD_VCLK 0x3 to Reserved OxF EXT_INT13 3 0 0 Input 0 1 Output 0 2 LCD VDEN 0x3 to Reserved OxF EXT_INT13 2 0 0 Input 0 1 Output 0 2 LCD_VSYNC 0x3 to Reserved OxF EXT_INT13 1 0 0 Input 0 1 Output 0 2 LCD HSYNC 0x3 to Reserved OxF EXT_INT13 0 4 43 4 General Purpose Input Output GPIO Control 4412 UM 4 General Purpose
619. vel 0 1 High level EXT 40 CON 6 26 24 RW 0 2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0x5 to 0 7 Reserved ASVO Eq mesen wp 9 Sets signaling method of EXT INT40 5 0 0 Low level 0 1 High level EXT_INT40_CON 5 22 20 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0 7 Reserved SVO Sets signaling method of EXT_INT40 4 0 0 Low level 0x1 High level EXT_INT40_CON 4 18 16 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0 7 Reserved 85 9 mp o Sets signaling method of EXT_INT40 3 0 0 Low level 0x1 High level EXT INT40 CON 3 14 12 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0 5 to 0 7 Reserved mw mi reme mw SAMSUNG ELECTRONICS 4 264 27 4412 UM 4 General Purpose Input Output GPIO Control Sets signaling method of EXT_INT40 2 0 0 Low level 0x1 High level EXT_INT40_CON 2 10 8 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT40 1 0 0 Low level 0x1 High level EXT_INT40_CON 1 6 4 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT40 0 0 0 Low l
620. verview of Window Blending e Blending Diagram e Function e Blending and Color Key Function 16 3 5 1 Overview of Window Blending Window blending is the main function of VPRCS module Display controller comprises of five window layers win O to win 4 Example 16 1 Application The system uses win0 as OS window full TV screen window and so on winl as small next channel TV screen with win2 as menu win3 as caption 4 as channel information win3 and win4 have color limitation while using color index with Color LUT This feature enhances the system performance by reducing the data rate of total system Example 16 2 Total Five Windows win0 base Local YCbCr RGB without palette winl Overlayl RGB with palette win3 Caption RGB 1 2 4 with 16 level Color win2 Overlay2 RGB with palette Cursor RGB 1 2 with 4 level Color LUT win4 Overlay Priority Win4 gt Win3 gt Win2 gt Win1 gt WinO Color Key 24 bit RGB format should set the register value to color key register SAMSUNG ELECTRONICS 16 26 ex 4412 UM Example 16 3 Blending Equation lt Data blending gt Win01 R G B Win012 R G B Win0123 R G B WinOut R G B Win0 R G B x bl Winl R G B Win01 R G B x b2 Win2 R G B Win012 R G B x b3 Win3 R G B Win0123 R G B x b4 Win4 R G B x al x 2 x al Window 0 s Red data Window 0 s Gr
621. w Enables chip select 1 Force nRCS 3 to high Disables chip select flash memory nRCS 2 signal control Reg_nCE2 22 RW 0 Force nRCS 2 to low Enables chip select 1 Force nRCS 2 to high Disables chip select 85 9 era eee 1 4 encoding decoding control MLCEccDirection 18 RW 0 Decoding 4 bit ECC It is used for page read 1 Encoding 4 bit ECC It is used for page program Lock tight configuration 0 Disables lock tight 1 Enables lock tight 17 RW 171 If this bit is to 1 you cannot clear this bit Refer to 10 4 12 Lock Scheme for Data Protection for more information Soft Lock configuration 0 Disables lock 1 Enables lock 1 RW 1 ee t6 Software can modify soft lock area any time Refer to 10 4 12 Lock Scheme for Data Protection for more information 85 0 CAI 4 bit ECC encoding completion interrupt control EnbMLCEncInt 13 RW 0 Disables interrupt 1 Enables interrupt 4 bit ECC decoding completion interrupt control EnbMLCDecInt 12 RW 0 Disables interrupt 1 Enables interrupt mw ee Illegal access interrupt control 0 Disables interrupt EnblllegalAccINT 10 Te Pene Illegal access interrupt occurs when CPU tries to program or erase locking area the area setting in NFSBLK 0 0 0 0020 to NFEBLK _0024 1 EnbRnBINT RnB status input signal transition interrupt control 0 Disables
622. x 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 185 EXT_INT26_FIXPRI e Base Address 0x1100 0000 e Address Base Address 0x0B28 Reset Value 0x0000 0000 Interrupt number of the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group 3 EXT INT26 when fixed priority 0 0 mode 0 to 7 4 3 3 186 EXT_INT27_FIXPRI e Base Address 0x1100 0000 e Address Base Address 0x0B2C Reset Value 0x0000 0000 Interrupt number of the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group 4 EXT INT27 when fixed priority 0 0 mode 0 to 7 4 3 3 187 EXT_INT28_FIXPRI Base Address 0x1100 0000 e Address Base Address 0x0B30 Reset Value 0x0000 0000 Interrupt number of the highest priority in External Highest_EINT_NUM 2 0 RW Interrupt Group 5 EXT_INT28 when fixed priority 0 0 mode 0 to 7 4 3 3 188 EKT INT29 FIKPRI Base Address 0x1100 0000 e Address Base Address 0x0B34 Reset Value 0x0000 0000 Interrupt number of the highest priority in External Highest EINT NUM 2 0 RW Interrupt Group 6 EXT INT29 when fixed priority 0x0 mode 0 to 7 IIT SAMSUNG ELECTRONICS 4 249 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 189 EXT_INT8_FIXPRI e Base Address 0x1100 0000 e Address Base Address 0x0B38 Reset Value 0x0000 0000 Interrupt number of the highest priority in External Highest EINT NUM 2 0 R
623. x0 Disables Filter 0x1 Enables Filter Filter Selection for EXT_INT41 5 FLTSEL16 5 0 0 Delays filter 0x1 Digital filter clock count Filtering width of EXT_INT41 5 FLTWIDTH16 5 This value is valid when FLTSEL16 of EXT_INT41 is Ox1 Filter Enable for EXT_INT41 4 FLTEN16 4 0 0 Disables Filter 0 1 Enables Filter Filter Selection for EXT INT41 4 FLTSEL16 4 0 0 Delays filter 0 1 Digital filter clock count Filtering width of EXT_INT41 4 FLTWIDTH16 4 This value is valid when FLTSEL16 of EXT 41 is Ox1 SAMSUNG ELECTRONICS 4 275 II 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 218 EXT_INT42_FLTCONO Base Address 0x1100 0000 e Address Base Address OxOE90 Reset Value 8080 8080 Filter Enable for EXT_INT42 3 FLTEN17 3 0 0 Disables Filter 0 1 Enables Filter Filter Selection for EXT INT42 3 FLTSEL17 3 0 0 Delays filter 0x1 Digital filter clock count Filtering width of EXT_INT42 3 FLTWIDTH17 3 This value is valid when FLTSEL17 of EXT_INT42 is 0x1 Filter Enable for EXT_INT42 2 FLTEN17 2 0x0 Disables Filter 0x1 Enables Filter Filter Selection for EXT INT42 2 FLTSEL17 2 0 0 Delays filter 0x1 Digital filter clock count Filtering width of EXT_INT42 2 FLTWIDTH17 2 This value is valid when FLTSEL17 of EXT INT42 is Ox1 Filter Enable for EXT INT42 1 FLTEN17 1 0 0 Disables Filter 0 1 Enables Filter F
624. x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 CC_1 0x0428 Specifies the channel control for DMA channel 1 0x00800200 2 0 0448 Specifies the channel control for channel 2 0 00800200 DA 1 00424 Specifies the destination address for channel 1 CC 3 00468 Specifies the channel control for DMA channel 3 0 00800200 CC 4 0x0488 Specifies the channel control for DMA channel 4 0x00800200 gt SAMSUNG ELECTRONICS 8 6 4412 UM 8 Direct Memory Access Controller DMAC DBGSTATUS 0 0000 Specifies the debug status register Refer to 3 37 of 0 0 LC1 1 0x0430 Specifies the loop counter 1 for DMA channel 1 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 PL330 for more information Specifies the debug command register Refer to page 3 37 DBGCMD 30 for more information Ungefngd ui SAMSUNG ELECTRONICS 8 7 4412 UM 8 Direct Memory Access Controller DMAC messer Om Reset Value dec MEM CIN Mr _ ee OxOEOC Specifies the configuration register 3 Refer to page 3 44 of PL330 for more information Specifies the configuration register 4 Refer to page 3 45 of PL330 more information Specifies the configuration register Refer to 3 46 DOE of PL330 TRM fo
625. x0000 0000 E DIVCLKOUT Status DIV STAT 0 Stable 0 0 1 Status that the divider is changing 5 10 1 104 MPLL_LOCK B e Base Address 0x1004_0000 e Address Base Address 0x0008 Reset Value 0x0000_0FFF RSV arse nesen _ Required period to generate stable clock output Set 270cycles to PLL LOCKTIME for the PLL maximum lock time PLL_LOCKTIME 15 0 RW 1 cycle 1 FREF 1 FIN PDIV The maximum PLL lock time is 22 5 usec where FIN 15 24 MHz 15 2 and PLL_LOCKTIME is 540 The maximum lock time means the waiting time for locking in the worst case Therefore the user of this PLL must wait for more than the maximum lock time unconditionally before the PLL is locked Waiting time before locking gt the maximum locktime SAMSUNG ELECTRONICS 5 121 ex 4412 UM 5 Clock Management Unit 5 10 1 105 MPLL CONO e Base Address 0x1004 0000 e Address Base Address 0x0108 Reset Value 0 0064 0300 PLL Enable Control ENABLE 31 RW 0 Disables 1 Enables SE 1 99 PLL Locking Indication 0 Unlocks 1 Locks If ENABLE LOCK DET 0 then this field is set to 1 after the locking time The lock time is set 29 using the MPLL LOCK SFR register If ENABLE LOCK DET 1 then this field is set when the hardware lock detector meets the PLL locking condition This bit is Read only ASV gp Monitors S
626. x1 Interrupt occurs EXT 22 2 2 RWX 0 0 Not occur 0 1 Interrupt occurs EXT_INT22_PEND 1 WA 0 1 Interrupt occurs EXT 22 PEND 0 RWX 0x0 Not occur 0 1 Interrupt SAMSUNG ELECTRONICS 4 116 27 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 146 SERVICE Base Address 0x1140 0000 Address Base Address 0x0B08 Reset Value 0 0000 0000 EXT_INT Service group number 0 1 EXT_INT1 0 2 EXT_INT2 0x3 0 4 EXT_INT4 0 5 EXT_INT5 f 0x6 6 SVC Group Num 7 3 0x7 EXT INT7 0 00 0 8 EXT_INT13 0 9 EXT_INT14 EXT_INT15 OxB EXT_INT16 0 EXT_INT21 0 0 EXT_INT22 SVC_Num 2 0 Interrupt number to be serviced 4 3 2 147 EXT_INT_SERVICE_PEND_XB Base Address 0x1140 0000 e Address Base Address Reset Value 0x0000 0000 SVC_PEND zo mw ORO Noreen 0x00 0 1 Interrupt occurs SAMSUNG ELECTRONICS 4 117 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 2 148 EXT_INT_GRPFIXPRI_XB Base Address 0x1140_0000 e Address Base Address 0x0B10 Reset Value 0x0000 0000 When fixed group priority mode 0 to 12 then group number should be of the highest priority 0x0 0 1 EXT_INT2 0 2 EXT 0 3 INT4 0 4 EXT
627. x3 Triggers Rising edge 0 4 Triggers Both edge 0 5 to 0x7 Reserved 85 0 mp Sets signaling method of EXT_INT12 4 0 0 Low level 0x1 High level EXT INT12 CON 4 18 16 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved 85 9 Rewd AI Sets signaling method of EXT_INT12 3 0 0 Low level 0x1 High level EXT INT12 CON 3 14 12 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0x5 to 0 7 Reserved mw fm a SAMSUNG ELECTRONICS 4 212 en 4412 UM 4 General Purpose Input Output GPIO Control Sets signaling method of EXT_INT12 2 0 0 Low level 0x1 High level EXT_INT12_CON 2 10 8 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0x4 Triggers Both edge 0 5 to 0x7 Reserved Sets signaling method of EXT_INT12 1 0 0 Low level 0x1 High level EXT INT12 CON 1 6 4 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0 5 to 0x7 Reserved Sets signaling method of EXT INT12 0 0 0 Low level 0 1 High level EXT INT12 CON 0 2 0 RW 0x2 Triggers Falling edge 0x3 Triggers Rising edge 0 4 Triggers Both edge 0 5 to 0x7 Reserved SAMSUNG ELECTRONICS 4 213 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 131 EXT_INT23_FLTCONO e Base Address 0x1100 0000 e Address
628. x4A04 Reset Value 0x0000 0000 DIVCLKOUT Status DIV STAT 0 Stable 0 0 1 Status that the divider is changing IKUY SAMSUNG ELECTRONICS 5 150 4412 UM 5 Clock Management Unit 5 10 1 143 ARMCLK STOPCTRL e Base Address 0x1004 0000 e Address Base Address 0x5000 Reset Value 0 0404 0404 Specifies clock freeze cycle before the LA FRE MATT CNT aiaa id CLAMP L2 and CLAMP_L2_1rising transition Specifies clock freeze cycle after the L2RET1N_0 LA POSE ONAN ONT 2946 Ww and L2RET1N_1 rising transition R R Specifies clock freeze cycle before the ARM clamp CLAMPCOREO CLAMPCORE 1 CLAMPCOREOUT CLAMPL2 0 and PRE WAIT 15 8 RW CLAMPL2 1 or reset signal nCPURESET nDBGRESET nSCURESET L2nRESET nWDRESET nPERIPHRESET and nPTMRESET transition Specifies clock freeze cycle after the ARM clamp CLAMPCOREO CLAMPCORE 1 CLAMPCOREOUT CLAMPL2 0 and POST WAIT CNT 7 0 R CLAMPL2 1 or reset signal NCPURESET nDBGRESET nSCURESET L2nRESET nWDRESET nPERIPHRESET and nPTMRESET transition 5 10 1 144 STOPCTRL Base Address 0x1004 0000 e Address Base Address 0x5004 Reset Value 0x0000 0404 RSV Specifies clock freeze cycle before the PRE WAIT CNT ATRESETn nPRESETDBG and 0x4 CSSYS nRESET signal transition Specifies clock freeze cycle after ATRESETn POST_WAIT_CNT nPRESETDBG and CSSYS nRESET signal transi
629. xE Reserved OxF 0 0 Input 0 1 Output GPY6CON 0 3 0 0 2 EBI_DATA 8 0x3 to Reserved OxF SAMSUNG ELECTRONICS 4 167 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 80 GPY6DAT e Base Address 0x1100 0000 e Address Base Address 0x01E4 Reset Value 0x00 RWX When you configure port as input port then corresponding bit is pin state When configuring as GPY6DAT 7 0 7 0 output port then pin state should be same as 0 00 corresponding bit When the port is configured as functional pin the undefined value will be read 4 3 3 81 GPY6PUD Base Address 0x1100 0000 e Address Base Address 0x01E8 Reset Value 0x5555 0x0 Disables Pull up Pull down 2n 1 2n 0 1 Enables Pull down GPY6PUDIn n 0to7 RW 0x2 Reserved 0x5555 0x3 Enables Pull up 4 3 3 82 GPY6DRV e Base Address 0x1100_0000 e Address Base Address 0x01EC Reset Value 0x00_AAAA 23 16 Reserved Should be zero W GPY6DRVIn n 2n 1 2n R ERA 0107 SAMSUNG ELECTRONICS 4 168 ex 4412 UM 4 General Purpose Input Output GPIO Control 4 3 3 83 GPY6CONPDN Base Address 0x1100 0000 e Address Base Address 0 01 0 Reset Value 0x0000 0 0 Outputs 0 2n 1 21 0 1 Outputs 1 GP Yem 0107 FUN 0x2 Input 0 3 Previous state 4 3 3 84 GPY6PUDPDN e Base Address 0x1100 0000 e Address Base Address 0x01F4 Reset
630. xFFFF FFFF 0x0708 to CLK GATE IP DMCO 0x0900 Control IP clock gating for OxFFFF FFFF CLK GATE IP DMC1 0x0904 Control IP clock gating for DMC BLK OxFFFF FFFF 0 0908 to CLKOUT CMU DMC 0x0A00 CLKOUT control register 0x0001_ 0000 CLKOUT_CMU_DMC_ DIV STAT Ox0A04 Clock divider status for CLKOUT 0x0000_0000 0x0A08 to DCGIDK MAPO 01000 DCG index OxFFFF FFFF DCGIDX MAP1 0 1004 DCG index 1 OxFFFF FFFF SAMSUNG ELECTRONICS 5 31 4412 UM 5 Clock Management Unit DCGIDX_MAP2 0x1008 DCG index map2 OxFFFF FFFF 0x100C to DCGPERF_MAPO 0x1020 DCG performance OxFFFF FFFF DCGPERF MAP1 0x1024 DCG performance OxFFFF FFFF 0x1028 to DVCIDK MAP 01040 DVC index OxOOFF_FFFF 0x1044 to FREQ_CPU 0x1060 Maximum frequency of CPU 0x0000_0000 FREQ_DPM 0x1064 Frequency of DPM 0x0000_0000 0x1068 to DVSEMCLK_EN 0x1080 DVS emulation clock enable 0x0000_0000 MAXPERF 0x1084 Maximum performance enable 0x0000_0000 0x1088 to DMC_PAUSE_CTRL 0x1094 Pause function of DREX2 for DVFS 0x0000_0000 DDRPHY_LOCK_CTRL pade CP 0 0000_0000 C2C is enabled C2C_STATE 0x109C Current state of C2C SEC FSM 0x0000_0000 0x10A0 to APLL LOCK 04000 Control PLL locking period for APLL 0x0000 OFFF 0x4004 to APLL_CONO 0x4100 Control PLL output frequency for APLL 0x0064_0300 APLL CON 1 0x4104 Control PLL AFC 0x0080 3800 0x4108 to CLK_SRC_CPU 0x4200 Se
631. y 2 Soft Lock Mode In soft lock mode you can access NAND block area between NFSBLK and NFEBLK When you try to program or erase the locked area an illegal access error occurs NFSTAT 5 bit will be set 3 Lock Tight Mode In lock tight mode you can access NAND block area between NFSBLK and NFEBLK as soft lock mode The difference is that you cannot change NFSBLK and NFEBLK registers You cannot change LockTight bits also When you try to program or erase the locked area an illegal access error occurs it sets NFSTAT 5 bit LockTight NFCONT 17 bit is only cleared when reset or wake up from sleep mode It is impossible to clear it by software Figure 10 4 illustrates the accessibility of area NAND flash memory When NFSBLK NFEBLK veden Address ocked area High Read only NFEBLK gt NFEBLK gt Prorammable NFSBLK Locked Area Readable NFEBLK I Read only NFSBLK Area NFSBLK 1 gt Locked area Read only Low when Lock tight 1 or SoftLock 1 Figure 10 4 Accessibility Area NOTE If the address of NFSBLK NFEBLK are similar then it does not allow the erase and program to all memory SAMSUNG ELECTRONICS 10 13 ex 4412 UM 10 NAND Flash Controller 10 5 Programming Constraints NFCON has a constraint to access an external NAND flash memory NFCON accesses NAND flash memory through Externa
632. y capture data of next cycle For example of Exynos 4412 SPI CH1 with master configuration of 50 MHz operating frequency 1 8 V external voltage and 15 pF load if it assumes MISO output delay of SPI slave as 11 ns tspimis s lt 10 ns 11 ns 1 ns then it should use 270 degree phase delayed feedback clock If the operating clock frequency is 33 MHz and other conditions are similar to the previous example it is better to use 180 degree phase delayed feedback clock tspimis S lt 15 ns 11 ns 4 ns SAMSUNG ELECTRONICS 15 3 ex 4412 UM 15 Serial Peripheral Interface 15 2 1 8 SPI Transfer Format The Erynos 4412 supports four different formats for data transfer Figure 15 1 illustrates four waveforms for SPICLK CPOL 0 CPHA 0 Format A Cycle 1 2 3 4 5 6 7 8 MSB MSB of previous frame CPOL 0 CPHA 1 Format B Cycle 1 MISO LSB 6 5 4 3 Y 2 Y 1 o pa LSB LSB of next frame CPOL 1 CPHA 0 Format A Cycle A RS e AAA MSB MSB of previous frame CPOL 1 CPHA 1 Format B Cycle 1 2 3 4 5 6 7 8 MOSI wseX 6 X 5 4 X 3 X 2 X t MISO LSB LSB of next frame Figure 15 1 Transfer Format SAMSUNG ELECTRONICS 15 4 ex 4412 UM 15 Serial Peripheral Interface 15 3 SPI Input Clock Description Figure 15 2 illustrates

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