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1. GPRS COMREG RO R15 i4 VARIABLES y He fees d P EXTERNAL FUNCTIONS vU DE EXTERN CopyApplicationCode FAR Copies the application code EXTERN InitializeVariables FAR Initialize global variables EXTERN Peripherallnit FAR Peripheral initialization routine EXTERN main FAR EXTERN FastIntAddress WORD Main program label in internal program RAM Fast interrupt address E EEEH He ei FUNCTIONS HH HE HH START SECTION CODE WORD PUBLIC PROGRAM PUBLIC StartUp StartUp PROC TASK INTNO 0 Routine called by reset vector PowerOnReset MOV CPUCON1 00007h MOV CPUCON2 408F3Dh MOV WDTCON 00003h SRVWDT EXTR 1 OV SYSCON1 00200h OV SYSCON2 ZEROS i MOV SYSCON3 ZEROS MOV RO 00006h EXTR 1 OV RSTCON RO E OV CP OFCOOh OV DPPO 00040h MOV DPP1 00080h P MOV DPP2 00304h MOV DPP3 00003h OV SPSEG ZEROS MOV2. Bit 11 set and 0010 gt BRANCHA cc_usr0 caddr absolute branch if usrO is set Bit 11 set and cc 0011 gt BRANCHA cc_usr1 caddr absolute branch if usr1 is set Bit 11 set and cc x1xx gt Reserved conditions Bit 11 set and cc 10xx gt Reserved conditions Note that the conditions on USRO have to be used carefully if the software was already using the USRO bit Moreover some C compilers or operating systems may also use the USRO bit 6 26 ky f f if if if if if if if if if if iy f AN1982 APPLICATION NOTE 2 7 The Enhanced Branch Capabilities 2 7 1 Branch Folding A new branch folding unit sitting within the fetch mechanism allows the execution of some jump instruc tions in the same cycle as the preceding instruction If a branch instruction has been folded and correctly predicted it will be executed in parallel with the standard instruction flow i e in zero cycle 2 7 2 Branch Detection and Prediction A new branch detection and prediction unit sitting within the prefetch mechanism deals efficiently with non linear code The prediction is static it is done by hardware for indirect intersegment relative and bit conditional branches and is user programmable for absolute branches A correctly predicted instruction flow is executed like linear code In case of misprediction a penalty of 3 to 6 cycles has to be taken 2 7
3. TI AN1982 Y7 APPLICATION NOTE FROM ST10 TO Super10 1 INTRODUCTION The Super10 core is an evolution of the existing ST10 architecture with highly improved performance This evolution has been done with a constant concern for compatibility between the two implementations for example the instruction set is fully compatible However the need for improvement requested a change in the architecture which leads to changes in the application software The goal of this application note is to give guidelines to help to convert an ST10 application for Super10 Most of the differences between the two cores do not imply that the source code has to be changed These differences may affect the timing of one instruction the way the data or program is stored into memory or the presence of new registers with reset values making them compatible with ST10 or other topics related to the new implementation The first kind of differences will be covered in Chapter 2 Archi tectural Differences these will have to be checked carefully when optimization is needed However in some rare cases the source code needs to be changed to run on the Super10 core this is covered in Chapter 3 Software Differences Rev 1 AN1982 0604 1 26 AN1982 APPLICATION NOTE 2 1 2 2 2 2 1 2 2 2 2 3 2 4 2 5 2 5 1 2 5 2 2 5 3 2 5 4 2 6 2 7 2 7 1 2 7 2 2 7 3 2 8 2 8 1 2 8 2 2 9 2 10 2 11 2 12 2 13 2 14 2 14 1 2 14 2 2 14 3 2 15 2
4. 10 as push pull output 24 address bits 3 chip select lines Ready pin enabled active low WRLn and WRHn not WRn and BHEn All EBC pins enabled master mode 16 Demux Ready disabled 0 clk No CS switch off time 1 clik ALE length C 0 clk No R W delay D 0 clk E 10 clks Wait state time F 0 clk R and W No memory tristate time 110 ns cycles 16 Demux Ready disabled 0 clk No CS switch off time 1 clk ALE length C 0 clk No R W delay D 0 clk E 2 clks Wait state time F 0 clk R and W 30ns cycle 1 Mbyte window Segment 10 to 1F 8 Demux Ready disabled A 0 clk No CS switch off time 1 clk ALE length C 0 clk No R W delay D 0 clk E 2 clks Wait state time F 0 clk R and W 30ns cycle 512 kBytes window Segment 8 to F External interrupt number 1 Falling edge sensitive 23 26 AN1982 APPLICATION NOTE OV EXISEL OV FEILIC MOV RO 08 OV RO DPP 00h Input from associated pin only P2 8 to P215 032h Fast External interrupt programmed to Group 2 level 12 and disabled 2C0h nterrupt jump table cache OV FINTOCSP RO 3 FastIntAddress OV FINTOADDR RO MOV RO 00020h OV BNKSELO RO OV BNKSEL1 ZEROS CALL PeripheralInit DISWDT MOV RO SYSSTAT JB RO 1 Nocopy CALL CopyApplicationCode Nocopy CALL Initi
5. files are provided by the tool chain to keep the full code compatibility Example 1 MOV RO FCEOh SRCPO address on ST10 MOV RO will NOT work on Super10 SRCPO address is now EC40h Example 2 MOV RO SRCPO MOV RO R1 will work both on ST10 and Super10 2 5 2 New General Purpose Registers GPRs Windowing A new approach is used for register banks in the Super10 GPRs are not directly accessed from memory but from a kind of register cache This change remains invisible from a functional point of view but it impacts notably the interrupt latency in case of CP modification for instance using a SCXT CP new_bank instruction will take twenty six cycles To maintain the performance on interrupt latency sev eral enhancements have been added They are described in the following paragraphs 2 5 3 The Local Banks In addition to the global register bank two GPR banks have been added local bank 1 and local bank 2 Switching between any of these three banks does not take any cycle On the other hand only one out of these three banks can be seen at a given time using the short addressing mode RO to R15 The global register bank is always accessible with the long addressing modes ky 5 26 AN1982 APPLICATION NOTE The local banks are not memory mapped so they do not consume any memory location after reset their value is undefined They cannot be addressed using the long addressing mode they h
6. prefetch and fetch stages feeding its five other stages decode address memory execute and write back This allows a reduction of the number of cycles needed to execute one instruction while executed in at least 2 cycles with ST10 most of instructions now need only one cycle with Super10 In addition there is no more pipeline hazard All instructions modifying any GPR E SFR or memory location can be directly followed by an instruction using the updated value For instance an instruction which modifies a DPP register can be followed by a load instruction which uses the new value of the DPP register 2 2 Memory Organization The memory organization is quite different between ST10 and Super10 the latter supporting the following kinds of memories Program memory in segment COh and above Data memory in the upper part of segment OOh It is not executable DPRAM for GPR and MAC operand storage It is no longer executable Some external memory can be added for instance at the beginning of segment 00h to store code and data This new organization might force the variables constants and executable code to be reorganized within memory using the locator 2 2 1 Efficiency in Code Fetching The fastest way to execute instructions is to place the code in internal program memory Instructions can also be located in external memory but the performance will be very similar to the ST10 one in this case no real advantage will be take
7. two bits of these DPP registers were taken into account Consequently this meant that the size of both code and data was smaller than 64K and they were fitting into segment 00h On Super10 the data fetch and code fetch have been properly distinguished Disabling the segmentation with CPUCON1 SGTDIS fixes the CSP to its current value meaning that up to 64K Bytes of code can be used The code can be placed into any segment for instance segment COh independently of data size or data location However special care has to be taken when the fixed CSP value is different from its reset value See Section 2 14 1 Interrupt Jump Table Relocation for more details Moreover the SGTDIS bit has no influence on data addressing the whole DPP register is still used for the calculation of the physical 24 bit address As an example an application using 60K Bytes of code and 90K Bytes of data can still use the non segmented mode This is particularly useful when optimization of the stack usage and low interrupt latency time are needed 2 5 Register Improvements 2 5 1 General Rule for Register Handling In order to allow a high level of performance within the Super10 core the E SFR and MAC register set has been moved into the memory area When converting an application any access to a register using its absolute memory address will have to be replaced by an access through its actual name see examples below The register names and new register definition
8. usual CoINSTR behaviour the following actions If MRW is equal to 0x0000 then USR1 is set e if MRW is different than 0x0000 then USR1 is cleared and MRW is decremented 3 3 3 The Software Replacement for Hardware Repeat Repeatable CoINSTR instructions can be simulated in software For example the following code repeat 20 times CoMACM IDX0 RO should be replaced by mov MRW 19 100 00 USR1 CoMACM IDX0 RO JMPA cc_nusrl loop00 and the following code repeat times CoMACM IDX0 RO should be replaced by loop01 USR1 CoMACM IDX0 RO JMPA cc_nusrl loop01 ky 13 26 AN1982 APPLICATION NOTE Since correctly predicted JMPA are executed in O cycle this new code offers nearly the same perfor mance on a cycle basis than the original one using a repeatable CoINSTR instruction Performance wise it has to be noted that for a low number of loops containing only one instruction approximately less than five it is better to write the number of desired instructions than to use the JMPA instruction Other wise the penalty taken during the last mispredicted JMPA three cycles would make the performance worse than on ST10 Finally to maintain the maximum compatibility the USRO bit should not be used to simulate repeatable instructions because this bit was already existing and therefore was potentially used by the programmer or the compiler 3 4 Other Multiply and Accumulate Unit Diffe
9. 15 1 2 15 2 2 15 3 2 15 4 2 26 hapieileie M ARCHITECTURAL DIFFERENCES eerte u u u THE FULLY INTERLOCKED PIP 5 iiem ditiis MEMORY ORGANIZATION nennen nennen nennen rete Efficiency in Code Fetching Efficiency in Operands Access THE NEW SYSTEM STACK a ire DPP ADDRESSING IN NON SEGMENTED REGISTER IMPROVEMENT S interet aient Ee rie EP cet ER nied General Rule for Register Handling I a New General Purpose Registers GPRS Windowing The Local Banks zie UD Rire Automatic Fast Bank Switching USRX BIT LOOPS ette i tid o Bae Gud n entra duit THE ENHANCED BRANCH CAPABILITIES sse Branch Folding u s n s u uapa ah ete dolere in RE Branch Detection and Prediction The Enhanced JMPA and CALLA Instructions MULTIPLICATION AND DIVISION ENHANCEMENTT DIV and MUL Instructions si Multiplication and Division Management sees NEW SOFTWARE BREAK INSTRUCTION ire ENHANCED WATCHDOG BEHAVIOUR iii THE NEW CLOCK TREE died ird a E acd HE a ep een eee RESET MECHANIS
10. 3 The Enhanced JMPA and CALLA Instructions JMPA and CALLA instructions use a static prediction scheme if bit 8 of the instruction long word is cleared then JMPA CALLA is assumed taken if it is set then JMPA CALLA is assumed not taken This prediction scheme is user programmable JMPA and CALLA instructions are converted into JMPA and CALLA respectively assumed taken prediction bit cleared JMPA and CALLA instructions are converted into JMPA and CALLA respectively assumed not taken prediction bit set For regular JMPA instructions the assembler applies the following rule cc z is predicted not taken prediction bit set all the other conditions being predicted taken prediction bit cleared For regular CALLA instructions the assembler assumes them taken prediction bit cleared For the JMPA instruction a prefetch hint bit is used This bit is the instruction bit 9 and is required by the fetch unit to deal efficiently with short backward loops It must be set only if 0 lt IP_jmpa IP_target lt 32 and cleared otherwise IP_jmpa being the address of the JMPA instruction and target being the target address of the JMPA instruction This bit is not user programmable but is set by the assembler according to the previous rule 2 8 Multiplication and Division Enhancement 2 8 1 DIV and MUL Instructions The divide and multiply instructions are faster A 16 by 16 multi
11. 6 level14 group2 then PSW 9 8 BNKSEL1 5 4 level14 group1 then PSW 9 8 BNKSEL1 3 2 level14 groupO then PSW 9 8 BNKSEL1 1 0 level13 group3 then PSW 9 8 BNKSELO 15 14 level13 group2 then PSW 9 8 BNKSELO 13 12 level13 group1 then PSW 9 8 BNKSELO 11 10 level13 group0 then PSW 9 8 BNKSELO 9 8 level12 group3 then PSW 9 8 BNKSELO 7 6 level12 group2 then PSW 9 8 BNKSELO 5 4 level12 group1 then PSW 9 8 BNKSELO 3 2 level12 group0 then PSW 9 8 BNKSELO 1 0 Interrupts with priority level below 12 only use the global register bank When returning from interrupt the PSW is automatically restored from the stack thus restoring the previous bank in use 2 6 USRx Bit Loops In addition to USRO a new user bit called USR1 has been created within PSW bit number 7 These two bits now allow loops linked to the MRW register See Section 3 3 2 The Modified CoINSTR Instructions for more details In accordance with this four new conditions on JMPA and CALLA branch instructions are created These new conditions are selected when the bit 11 of the instruction long word is set Then the condition field cc is used to precisely determine which of these new conditions is used Bit 11 set and cc 0000 gt BRANCHA cc nusr0 caddr absolute branch if usr0 is cleared Bit 11 set and cc 0001 gt BRANCHA cc_nusr1 caddr absolute branch if usr1 is cleared
12. C disabled 4 2 Configuration Registers 4 2 1 Core Registers The SYSCON register has not been implemented on Super10 Some bits have been removed when the capability is not supported any more For instance All bits concerning the Xbus and Xperipherals have been removed as the new architecture does not pro vide such a bus The oscillator watchdog capability is removed Bits configuring alternate functions have been removed where a dedicated pin in now provided The chip select latch capability is removed The internal ROM enable and mapping bits are removed because of the new memory organization See Section 2 2 Memory Organization The power down mode configuration has disappeared because of the new power saving modes See Section 2 13 The New Power Saving Mode The system stack size field is removed because of the new management of the system stack See Sec tion 2 3 The New System Stack Some bits can be found in other registers SGTDIS segmentation disabled can be found in the new CPUCON1 register Though its value may not be copied blindly See Section 2 4 DPP Addressing in Non Segmented Mode WRCFG write configuration can be found in the new EBCMODO register 18 26 57 AN1982 APPLICATION NOTE 4 2 2 System Registers Most of the special function register names and functions stay identical to the ST10 ones Some ST10 configuration register
13. Dk DK DK DK DK Dok Dok Dok KE KE kuku KO KK KE KO KE KE KE KE KK KE KE KE KE KK KEL KL ESCRIPTION start module KAKA KR KA KR DK Dok KK KL KE KE KE KE KL KE KE KL KK KE KE KE KE KH KE KE KE KE KL KE KL KE KE KL M S Ne Ne Ne Ne Ne MODIFICATIONS x k k k Ck k k amp kk k k k k amp k k k k k k k amp k k amp amp k k amp amp k k amp amp k k k k amp k k k k amp k k k amp amp k k KK k k k amp k Kk Kk k k ko ko lt x lt RJ THITAASHARETRAHASEAASEASRAASHASARTAHAAHHAAHEAAHEAHE IS ASSEMBLER SWITCHES SESSSSKEKKESSASSSSASKSESSSSSASSSASSASASASSASSSSASASAA ka Se a SSTDNAMES REGLONDON def ASSUME DPP3 SYSTEM ky 21 26 AN1982 APPLICATION NOTE
14. M eran Site ive e o fad d teo dc THE NEW POWER SAVING nennen nnne nnne nenne INTERRUPT JUMP TABLE ADDED FLEXIBILITY Interrupt Jump Table Relocation ss Interrupt Jump Table Scaling sess Fast Interrupt Interrupt Jump Table Cache PEC IMPROVEMENT iii Source and Destination Segmentation a Source and Destination Update ss Programmability of the PEC Interrupt Level Distinct Interrupt for End of PEC Transfer Event SOFTWARE DIFFERENCES reir inerte BINARY CODE COMPATIBILITY CO CO CO O NNN NNN d M O O1 O1 A a a A AA A A i lt Vemk O O O O 12 12 AN1982 APPLICATION NOTE 3 2 NEW PIPELINE 12 3 3 REPEAT CAPABILITY OF THE MULTIPLY AND ACCUMULATE UNIT 13 3 3 1 The Enhanced iii 13 3 3 2 The Modified CoINSTR Instructions n 13 3 3 3 The Software Replacement for Hardware Repeat 13 3 4 OTHER MULTIPLY AND ACCUMULATE UNIT DIFFERENCES 14 3 4 1 MAG V Flag 5 ue ete eng pe Bep be qoe Idee c Ree EL eos 14 3 4 2 MAG TED oit or ret abite er oie Id f Up sun Ue t Pa ua 14 3 4 3 Multip
15. ON NOTE Correct programming example Data access MOV Ry OFEOFH MOV Rx 00031H MOV FCONCS1 Rx MOV Rx FCONCS1 MOV DATA Ry Assumption Variable DATA1 is handled by CS1 4 1 2 2 External Code Fetch In addition to the measure described for data accesses see chapter above the instruction fetch pipeline has to be cleared because any prefetched code based on the old chip select configuration is wrong A write access to CPU register CPUCON1 cancels the instruction fetch FIFO Therefore the origin value of this register is read first and then written back to the register This action cancels the pipeline without modifying any system resources except the used GPR Correct programming example Code fetch MOV Rx 00031H MOV FCONCS2 Rx MOV Rx FCONCS2 MOV Rx CPUCONI MOV CPUCONI Rx JMP SEG Labell SOF Labell Assumption Labell is handled by CS2 4 1 3 CPU Performance Increase by Programming the CPUCONXx Registers The CPU control registers CPUCON1 and CPUCON should be programmed by the user application ini tialization routine before executing the EINIT instruction Note that every reset clears these two registers However the reset default value is not the optimum setting from the performance point of view Therefore itis recommended to add the following code to the initialization routine MOV CPUCONI 00007H Other bits may be set by the user MOV CPUCON2 08F3DH Fast PE
16. SP 0C000h VECSC 00 2 words DISWDT executable until EINIT Segmentation enabled Switch context interruptible Maximum performance Watchdog divider ratio 256 Service watchdog timer BUSCLK CPUCLK 2 normal IDLE mode Output drivers independant from sleep and power down modes All peripheral enabled Reset length 1024 CPU cycles RSTOUT2 enabled Global register bank address External SRAM External I O memory Data in Internal Program SRAM System page and upper 8K of Data SRAM System stack in segment zero 31 22 26 AN1982 APPLICATION NOTE OV OV OV OV XTR OV s OV OV XTR OV s OV OV MOV MOV MOV MOV MOV MOV MOV MOV OV OV OV OV OV OV OV OV EXTR OV STKUN 0C000h STKOV 0800Ch P2 00000h DP2 000FFh 1 ODP2 000FFh P3 00408h DP3 00408h 1 ODP3 00000h RO 00938h EBCMODO RO RO 21h FCONCSO RO RO 0240h TCONCSO RO RO 21h FCONCS1 RO RO 00040h TCONCS1 RO RO 01008h ADDRSEL1 RO RO 01h FCONCS2 RO RO 00040h TCONCS2 RO RO 00807h ADDRSEL2 RO 2 EXICON 00008h Reserve six words for safety Set Port 2 0 7 as output to zero XOR gate on P2 0 and P2 1 Set port 2 8 15 as input external interrupts Set Port 2 0 7 as open drain Set Port 3 as input Set P3 3 and P3 10 as output to one AND gate Set P3 3 and P3
17. Super10 the code needs to be rewritten MOV DPPO 1 MOV Meml RO Meml uses page 1 MOV Mem2 RO Mem2 uses page 1 MOV DPPO 2 MOV Mem3 R1 Mem3 uses page 2 3 3 Repeat Capability of the Multiply and Accumulate Unit The hardware repeat capability of the ST10 is no longer supported on Super10 The repeated instructions are substituted by software 0 cycle loops As there is potentially more than one instruction contained in the loop this is a big enhancement compared to the previous repeat capability 3 3 1 The Enhanced MRW becomes a complete 16 bit register This is intended to ease the integration of the 0 cycle loops by a high level language compiler by using intrinsic functions for example To have the loop count expressed on a natural integer size is important MRW 15 no longer means that a repeatable instruction has been interrupted This is a low incompatibility point since this bit was used by the ST10 hardware and was not expected to be used by software 3 3 2 The Modified CoINSTR Instructions All CoINSTR repeatable instructions are no longer repeatable but instead it is possible to specify addi tional capabilities for any CoINSTR instruction USRO CoINSTR performs in addition to the usual CoINSTR behaviour the following actions If MRW is equal 0x0000 then USRO is set if MRW is different than 0x0000 then USRO is cleared and MRW is decremented USR1 CoINSTR performs in addition to the
18. TCONCSx x 0 7 configures the corresponding chip select timings The ADDRSELx x 1 7 registers stay strictly identical to the ST10 ones they configure the address win dows of the corresponding chip selects ky 19 26 AN1982 APPLICATION NOTE In the Figure 1 an equivalence between the ST10 timings with respect to the BUSCON bit fields and the Super10 timings in demultiplexed mode is shown For a precise description of the phases A to F please refer to the external bus controller timing description in the Super10 User s Manual The A and D phases have no equivalence in ST10 Figure 1 ST10 and Super10 EBC Configuration in Demultiplexed Mode ST10 ALE CTL MCTC MTTC I 0 1 0 15 0 1 lt gt lt gt lt gt CPU Clock R W RD WR Dela MEER Super10 CPU Clock ALE 1 2 E RD WR C 1 32 F 0 3 0 3 lt 4 4 3 An example of the System Configuration Routine Let s take the assumption that we need to write the Super10 system configuration routine for the following application On power on hardware and watchdog resets the code is fetched from external non volatile memory The system configuration routine needs to configure the Super10 external bus controller and other peripherals copy the application code to internal program RAM and then jump to the main program On a software rese
19. al izeVariables OV VECSEG BSET IEN StartUp ENDP START ENDS c 2000 24 26 Ocoh or interrupt Group2 level 12 ast interrupt routine address in nternal memory ocal bank 1 is used for interrupt Group2 level 12 GPRSEL2 10b ther interrupts use global banks FJ Peripheral initialization Same as ST10 Disable watchdog In case of software reset do not copy application program Copies the application code including vector table from external Flash to internal program RAM Initialize global variables and possibly constants in internal data memory Locate interrupt vector table in internal memory Enable watchdog Service watchdog End of Initialization Interrupts global enable Call main routine in internal program memory STMicroelectronics X XCKCKCk Ck k k k k k kk kk k kkkkkkkk k END OF FILE 31 AN1982 APPLICATION NOTE Table 1 Revision History June 2004 1 First Issue ky 25 26 AN1982 APPLICATION NOTE The present note which is for guidance only aims at providing customers with information regarding their productsin order for them to save time As a result STMicroelectronics shall not be held liable for any direct indirector consequential damages with respect to any claims aris ing from the content of such a note and or the use made by customers of the information
20. ave to be accessed by their short address using the OxFO OxFF range of the SFR space or bitoff address space By default a compatible mode not using these local banks is supported meaning all ST10 code will still work They are selected using BANK bit field of PSW register This bit field 9 8 indicates which GPR bank is in use 00 means compatible mode The current bank in use is the one pointed at by CP 01 is RESERVED 10 means local bank 1 in use 11 means local bank 2 in use The selection of the bank in use can directly be done by writing to the PSW register or automatically upon interrupt entry This addition has been motivated by the fact that some applications need a very fast con text switch 2 5 4 Automatic Fast Bank Switching To improve interrupt latency at least for a set of selected interrupts two new control registers has been created BNKSELO and BNKSEL1 These registers are 16 bit wide When an interrupt occurs PSW CSP and IP are pushed on the stack Then for interrupts with an interrupt level greater or equal to 12 the PSW BANK field and thus the register bank in use can be automatically modified according to the following rule level15 group3 then PSW 9 8 BNKSEL1 15 14 level15 group2 then PSW 9 8 BNKSEL1 13 12 level15 group1 then PSW 9 8 BNKSEL1 11 10 level15 group0 then PSW 9 8 BNKSEL1 9 8 level14 group3 then PSW 9 8 BNKSEL1 7
21. contained herein in connection with their products Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademarks of STMicroelectronics All other names are the property of their respective owners 2004 STMicroelectronics All rights reserved STMicroelectronics GROUP OF COMPANIES Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States www st com 26 26 ky
22. ditional interrupt handling where the SCXT CP instruction will be performed after the completion of the JMPS instruction 2 14 3 Fast Interrupt Interrupt Jump Table Cache This mechanism allows up to two interrupts not to use the standard jump table The program directly jumps to the interrupt service routine saving the execution time of the branch instruction To support these fast interrupts four new registers have been created FINT1CSP FINT1ADDR FINTOCSP and FINTOADDR When an interrupt is entered before jumping to the corresponding Interrupt Jump Table location and if the interrupt level is greater or equal than 12 then The 2 Isb of the interrupt level are compared to FINT1CSP 11 10 and the interrupt group number is compared to FINT1CSP 9 8 If both fields match and if FINT1CSP EN is set then the processor go to the address FINT1CSP 7 0 FINT1ADDR 15 0 Otherwise the 2 Isb of the interrupt level are compared to FINTOCSP 11 10 and the interrupt group number is compared to FINTOCSP 9 8 If both fields match and if FINTOCSP EN is set then the proc essor goes to the address FINTOCSP 7 0 FINTOADDR 15 0 Otherwise the processor goes to the corresponding Interrupt Jump Table entry according to the VEC SEG register and the VECSC field value On interrupts with an interrupt level strictly less than 12 the processor always goes to the corresponding Interrupt Jump Table entry according to the VECSEG register and th
23. e VECSC field value At reset both FINT1CSP EN and FINTOCSP EN bits 15 are reset thus disabling the interrupt jump table cache 2 15 PEC Improvement 2 15 1 Source and Destination Segmentation For each PECx channel a 16 bit segment register PECSEGx has been created The 8 msb of PEC SEGx are used as the segment for SRCPx the PECx source pointer while the 8 Isb are used as the seg ment for DSTPx the PECx destination pointer This allows PEC transfers between any kind of memory or register not necessarily in segment zero After reset all the PECSEGx registers are cleared which ensures a compatible behaviour Reminder The PEC source and destination pointers have been moved from the internal RAM area on ST10 FCEOh FCFEh to the internal I O area on Super10 EC40h EC5Eh 2 15 2 Source and Destination Update In the PEC control registers PECCx the INC field can now take the value 11 In this case both the PEC source and destination pointers are automatically modified In conjunction with the previous modification this change allows the PEC transfers to be used as a kind of software DMA complete blocks of memories can be copied by stealing cycles from the CPU 10 26 57 AN1982 APPLICATION NOTE 2 15 3 Programmability of the PEC Interrupt Level On ST10 PEC transfers always have the highest possible interrupt level 14 or 15 In the PEC control registers PECCx the new PLEV field 13 12 is created to pro
24. er needed this feature has been removed notably STKSIZE in the SYSCON register This leads to a small incom patibility in the stack initialization which is now limited to the registers listed hereafter A new register is created SPSEG 7 0 Stack Pointer SEGment register This register is used to extend the stack address from 16 bit to 24 bit It is cleared at reset SP Stack Pointer becomes a 16 bit wide register At reset it takes the value 0xFC00 for compatibility STKOV and STKUN are now 16 bit wide They use implicitly SPSEG as segment register extension to 24 bit 4 26 ky AN1982 APPLICATION NOTE The stack overflow and underflow are no longer detected in the case where the Stack Pointer is greater than STKOV or lower than STKUN This may change the software management of the stack as described in Section 3 6 Stack Operations With this new architecture the system stack can be placed in any read write memory but for performance reasons it should be placed First in Data SRAM if available Second in DPRAM if it is large enough Finally in external memory huge stack but with a performance penalty Note that in this case the stack cannot cross segment boundaries 2 4 DPP Addressing in Non Segmented Mode On ST10 disabling the segmentation with SYSCON SGTDIS was done by fixing the CSP value to zero and moreover the DPP extension mechanism for data access could not be used any more as only
25. eripheral bus frequency To ensure backward compatibility with applications running at a lower frequency other clock prescalers have also been added in some peripherals general purpose timers and watchdog timer 8 26 ky AN1982 APPLICATION NOTE 2 12 Reset Mechanism From a hardware point of view the reset mechanism has been simplified It relies on a reset input RSTIN and two outputs RSTOUT and RSTOUT2 RSTIN and RSTOUT are similar to the ST10 ones only RSTIN in monodirectional asynchronous mode is supported RSTOUT2 has been added to reset devices which need to be restarted before the first instruction is fetched by the microcontroller or to emu late the bidirectional reset of the ST10 with external hardware This RSTOUT2 signal is always activated on a hardware reset and can be activated on a software or watchdog reset depending on the RST CON RSTOUT2DIS bit The absolute minimum length of the RSTOUT2 pulse is 16 CPU clocks in case of a hardware reset and then is programmable by the RSTCON RSTLEN field to up to 2048 CPU clocks From a software point of view the new SYSSTAT register allows to differentiate between the different sources of reset For instance if a long initialization of RAM content for code and data is needed it can be performed only on hardware reset where a loss of power supply might have happened but not on soft ware or watchdog reset where the RAM content is preserved 2 13 The New Power Saving Mode O
26. gram the PEC interrupt levels between 8 and 15 This allows a greater number of high level interrupts not to be interrupted by PEC transfers After reset all the PECCx registers are cleared which is compatible with ST10 see Super10 User s Manual 2 15 4 Distinct Interrupt for End of PEC Transfer Event In some applications it was tolerated that a few cycles could be stolen from a high level task by a PEC transfer But then a problem occurred when an interrupt at the same level was generated to restart the PEC transfer mechanism with other parameters This difficulty can be worked around if the end of PEC transfer interrupt is not generated at the same level In the PEC control register PECCx an end of PEC interrupt selection bit EOPINT has been created If this bit is cleared the regular interrupt of the same level is triggered compatible behaviour If this bit is set a separate interrupt called end of PEC interrupt sub node is triggered when at least one EOP event has occurred This new interrupt is controlled by the PEC Interrupt Sub Node Control PECISNC register and its level defined by the classical EOPIC register The EOP interrupt handler is expected to read the PECISNC reg ister in order to determine which PEC transfer s is are finished and to initialize it them for the next transfer It has to be noted that the CxIR bits within the PECISNC register have to be cleared by software before returning from the interrup
27. inter may be needed to perform these operations ky 15 26 AN1982 APPLICATION NOTE 4 CONVERTING THE SYSTEM CONFIGURATION ROUTINE The modification of the system configuration routine is the main task to be done to convert an application for Super10 For C programmers this conversion is transparent as the new programming features are taken into account by the toolchain For assembly programmers the new system registers need to be programmed according to what was done on ST10 or in a different way if the bits are not existing any more After showing some programming hints this chapter explains what are the equivalences between the ST10 and the Super10 and finally gives an example of a possible routine 4 1 System Programming Hints This section describes the Super10 specific considerations and gives hints for the software design Side effects of the pipeline on the system control unit are detailed 4 1 1 Register write Protection Via the Security State Machine The system control unit of the Super10 supports a special register write protection mechanism via its security state machine This state machine selects one of the three security levels Improtected Low protected the state machine controls the right accesses Protected This write protection mechanism is used for several registers within the system control unit SYSCONx RSTCON and WDTCON for the CPU control registers CPUCONx and for all external bus co
28. lication and Accumulation with Rounding een 14 3 4 4 Improved Shift Range for COSHL CoSHR and CoASHR Instructions 14 3 5 IMPROVED BEHAVIOUR OF BIT FIELD INSTRUCTIONS 15 3 6 STAGK OPERATIONS i Ferr te vielen epe Mr lero erbe neige oe 15 4 CONVERTING THE SYSTEM CONFIGURATION ROUTINE 16 4 1 SYSTEM PROGRAMMING HINTS n 16 4 1 1 Register write Protection Via the Security State Machine 16 4 1 2 External Access After External Bus Controller Configuration 17 4 1 3 CPU Performance Increase by Programming the CPUCONx Registers 18 4 2 CONFIGURATION REGISTERS sse nnne nnne nenne 18 4 2 1 Ore BSglslels zen esos te sc A t inti ee 18 4 2 2 System Registers 4 ier eee ee ote dete eee pieta 19 4 2 8 External Bus Controller Registers nens 19 4 3 AN EXAMPLE OF THE SYSTEM CONFIGURATION ROUTINE 20 5 CONCEUSION Et 21 6 REFERENCES id inner Me neta dani 21 7 ANNEXE Z uuu rage ce ect e aaae eae arap E SeA aar Aai tesctbeneeenstteteuenes 21 ky 3 26 AN1982 APPLICATION NOTE 2 ARCHITECTURAL DIFFERENCES 2 1 The Fully Interlocked Pipeline The main improvements of the core rely on a new fully interlocked pipeline This pipeline has enhanced
29. n WDTCTL is cleared compatible behaviour then ENWDT instructions are transformed into NOP by hardware After the execution of EINIT or SRWDT the DISWDT instruction is transformed into NOP When WDTCTL is set then ENWDT instructions are normally executed Even after the execution of EINIT or SRWDT the DISWDT instructions are still executed Note The watchdog timer reset indication flag has been removed from the control register A new SYSSTAT register indicates the source of reset 2 11 The New Clock Tree The distribution of the clock signal to the different parts of the chip has been rationalized From the user point of view there is now only one clock and all actions are taken on the rising edge of this clock This clock is distributed to the CPU and its maximum value defines the target frequency of the Super10 as an example a 100MHz CPU clock can be used to execute instructions in 10ns It is also distributed to the external bus controller and all timings are based on this CPU clock On the emulation chips the CLKOUT signal represents this clock Another clock called the Peripheral Clock is derived from the main clock and is distributed to all on chip peripherals Its frequency is programmable with the SYSCON1 BCLKCON field Its maximum frequency is not dependent on the main clock maximum frequency but is usually lower A division factor of one 1 can be used if the CPU clock frequency is lower than the maximum p
30. n from the Super10 architecture 2 2 2 Efficiency in Operands Access Operands should preferably be placed either in DPRAM or data memory In most cases no pipeline stalls occur when using these two memories for data access leading to one instruction to be executed per cycle Internal program memory or external memory may be used to store operands This is particularly interest ing if non volatile memory is implemented because constants can directly be accessed without copying them into data memory In this case though the pipeline stalls for two cycles when accessing operands in internal program memory and at least three cycles depending on the external bus controller configura tion when accessing operands through the external bus controller If volatile memory is implemented as internal program memory at start up it is recommended to allocate all operands variables and constants into internal data memory and to place code into internal program memory Note in case of power supply loss a non volatile memory preserves its content code and constants but as it is usually read only it cannot store any variable 2 3 The New System Stack To overcome the ST10 system stack size limitation a circular stack with hardware supported flushing and filling has been defined This impacted interrupt latency For this reason the maximum stack size has been significantly increased to 64K Bytes Since the software extension mechanism is no long
31. n to complete and look for exceptions at the end than to trigger a top priority TRAP to check and stop the calculation 3 4 3 Multiplication and Accumulation with Rounding The instructions enabling to perform a multiplication or multiplication accumulation with rounding exten sion rnd will be supported in 2 cycles in the Super10 core instead of one instruction cycle two clock cycles in ST10 Other instructions using the rounding mechanism are still performed in one cycle 3 4 4 Improved Shift Range for COSHL CoSHR and CoASHR Instructions For shift operands specified by an immediate value the CoSHL CoSHR and CoASHR instructions now support the range 0 to 16 included For instance the following instruction is now valid CoSHL 16 This is particularly interesting when moving data from the least significant word of the accumulator to its most significant word and vice versa 14 26 171 AN1982 APPLICATION NOTE For shift operands specified by the content of a GPR the CoSHL CoSHR and CoASHR instructions now support the range 0 to 15 included The actual shift operand is specified by the 4 Isb of the GPR on Super10 while it was specified by the 3 Isb on the ST10 This is an incompatibility point since ST10 ignores bit 3 and Super10 does not Note Since the shift field was already 5 bit wide on ST10 the encoding is not affected but remember that all the sub encoding of CoINSTR instruction have been changed due to the new repea
32. n top of the already existing idle and power down modes a new sleep mode has been introduced to offer improved capabilities The sleep mode is entered upon execution of the IDLE instruction when the SYSCON1 SLEEPCON field is set to 01b In this mode the core and all peripherals including the watch dog timer are stopped which is similar to the power down mode But this mode can be exited by any external interrupt or reset This new mode is only one feature offered by the Super10 to efficiently control by software the power con sumption At system level the peripheral bus clock frequency can be adjusted to reduce the global peripheral consumption and any peripheral can be individually turned on and off to completely suppress its power consumption 2 14 Interrupt Jump Table Added Flexibility 2 14 1 Interrupt Jump Table Relocation A 16 bit wide register VECSEG has been created When an interrupt a hardware trap or a software trap occurs VECSEG 7 0 indicates in which segment the interrupt table is located After reset its value is 00 if external memory is selected by the EA configuration pin or COh if internal memory is selected VECSEG 15 8 is reserved and read as 0 This register may be used to move the vector table from a slow non volatile memory where the instruc tions are fetched from boot to a fast volatile memory Special care needs to be taken when modifying this register if the non segmented mode is used In this case the prog
33. nd of the security level changing sequence the security level stays on its previous level for a certain number of peripheral bus clock cycles This delay time is caused by the periph eral bus write time and by the switching time of the security level state machine Therefore any immedi ate write access after the last security command to an access controlled register will miss if the former security level was low protected or protected Wrong programming example MOV SCUSLC OAAAAH MOV SCUSLC 05554H MOV SCUSLC 09600H MOV SCUSLC 00000H MOV SYSCON1 00001H 16 26 er AN1982 APPLICATION NOTE The software has to poll the security level status after the last security command before executing a write access to any access controlled register Correct programming example OV SCUSLC 40AAAAH OV SCUSLC 05554H OV SCUSLC 09600H OV SCUSLC 00000H loop CMP SCUSLS 00000H JMP Z loop OV SYSCON1 00001H 4 1 1 3 Write Access in Low Protected Level After executing command 4 in low protected security level an immediate write access to an access con trolled register fails because the security state machine needs some cycles to set the supervisor mode see Section 4 1 1 2 Write Access Immediately After Selecting Unprotected Level Wrong programming example MOV SCUSLC 08EFFH MOV SYSCON1 00001H The software has to poll the security level s
34. ntroller configuration registers All other registers of the Super10 are not influenced by this mechanism After reset the unprotected state is selected by default The execution of the EINIT instruction changes the security level to protected mode immediately However the security level can be changed all the time by writing a special command sequence to the security level command register SCUSLC 4 1 1 1 Write Access Immediately Before the EINIT Instruction A write command to an access controlled register immediately before executing the EINIT instruction will miss because of the pipeline runtime operation The write command will be done at the write back stage whereas the EINIT condition of the following instruction will be set earlier Therefore the security state machine will be switched to protected level before the write command has taken place Wrong programming example OV SYSCON1 00001H EINIT The initialization software has to read back the content of the last written access controlled register before executing the EINIT instruction In case of a pending IO write followed by an IO read at the same address the pipeline stalls until the write access is done Therefore the write access will be done before the EINIT instruction takes any action Correct programming example OV SYSCON1 00001H OV Rx SYSCONI EINIT 4 1 1 2 Write Access Immediately After Selecting Unprotected Level After executing the last comma
35. plication is now performed in just one cycle and a 32 by 16 division in 4 cycles The division is now score boarded four 4 cycles are executed within the pipeline and up to seventeen 17 cycles in the background The flags are available at the end of the first four cycles so any action depending on the flags resulting from the division can be taken right away Alternatively it is better to delay the reading of the result for at least seventeen cycles to avoid stalling of the pipeline To take advantage of this new feature instruction reordering may be necessary 2 8 2 Multiplication and Division Management Linked to the previous enhancement the MULIP bit multiplication division in progress in the PSW regis ter has been removed The management of the division can now use the MDRIU bit Multiply Divide Reg isters In Use in the Multiply and Divide Control Register MDC If an interrupt using the MDH or MDL registers occurs the interrupt service routine may check first that those registers were not used by the main program If they were used they must be saved and restored before returning from interrupt interrupt JNB MDRIU nosave PUSH MDL PUSH MDH BSET RAMBIT Bit location in RAM used as a reminder nosave remainder of interrupt code using the MD registers JNB RAMBIT norestore BCLR RAMBIT This bit must only be used by this interrupt POP MDH POP MDL norestore RETI r 7 26 AN1982 APPLICATION NOTE As thi
36. ram must jump to the new segment and update the VECSEG value to the new CSP value before disabling the segmentation and enabling any interrupt 2 14 2 Interrupt Jump Table Scaling The field VECSC has been created within CPUCON1 Depending on its value the number of word locations separating two vectors can be two four eight or sixteen Instead of one 32 bit instruction per interrupt entry up to eight 32 bit instructions are available for each interrupt entry This allows to put the complete interrupt routine in the table if it is really short or to put instructions before the jump to the actual interrupt routine Usually the programmer uses the JMPS instruction in the interrupt jump table It is usual to have a SCXT instruction heading the interrupt routine JMPS interruptXX 1 entry XX 1 JMPS interruptXX entry XX JMPS interruptXX 1 entry XX 1 interruptXX SCXT CP dn remainder of interruptXX code ky 9 26 AN1982 APPLICATION NOTE Now with the interrupt jump table scaled by two we can modify the code in order to have SCXT CP m entry XX 1 JMPS interruptXX 1 SCXT CP n entry XX JMPS interruptXX SCXT CP 4p entry XX 1 JMPS interruptXX 41 interruptXX remainder of interruptXX code When using a scaled interrupt table the execution of the SCXT CP instruction and the execution of the JMPS instruction are done in parallel thus saving up to 10 cycles compared to the tra
37. rences 3 4 1 MAC V Flag An overflow flag is created in the MSW register The behaviour of the SV flag is slightly modified accord ing to the following rules CoSHL V cleared SV unchanged CoSHR V cleared SV unchanged CoASHR if rnd is selected then if rnd generates an overflow then V and SV are set else V is cleared and SV unchanged else V is cleared and SV unchanged CoABS if ACC 22 0x80 0000 0000 then V and SV are set else V is cleared and SV unchanged CoCMP The V flag is set if the ACC is strictly less than the operand SV is not affected by the CoCMP instruction CoMIN V is cleared and SV unchanged CoMAX V is cleared and SV unchanged CoMOV V and SV remain unchanged CoSTORE V and SV remain unchanged For all the other CoINSTR instructions the setting of SV remains identical to ST10 The V flag is set when an overflow is generated cleared otherwise 3 4 2 MAC Trap In the ST10 implementation a class B hardware TRAP is associated to the MAC A global enable bit MCW MIE is present to enable or disable MAC traps on specific actions The TRAPs to be activated are determined by a set of bits overflow limitation carry extension This functionality is not supported on Super10 as a consequence MCW bit field 15 11 is now tied to O This is a low incompatibility point since this TRAP was bearly used in most algorithms it is less time consuming to leave the complete calcula tio
38. s code is quite complex if the stack use is not an issue it is much better to save and restore those registers in all interrupts using the multiply and divide registers Moreover if a divide instruction is inter rupted it will take a maximum of thirteen cycles to be completed With the following code the pipeline will never be stalled interrupt beginning of interrupt code not using the MD registers at least 13 instructions PUSH MDL PUSH MDH remainder of interrupt code using the MD registers POP MDH POP MDL RETI 2 9 New Software Break Instruction A new SBRK software break instruction has been introduced to ease the debug of an application the opcode 8Ch is no longer reserved It can be used to generate by software a hardware trap Class A Vec tor 8 Otherwise its behaviour is closely linked to the On Chip Emulation module 2 10 Enhanced Watchdog Behaviour The ENWDT instruction has been created and implemented as a protected instruction the opcode 85h is no longer reserved When this instruction is executed the watchdog timer unit is enabled even if this unit was previously disabled by a DISWDT instruction Then it is still possible to disable the watchdog timer again by a DISWDT instruction and so on The WDTCTL bit has been created in CPUCON1 This bit can only be modified until the execution of an EINIT or a SRWDT service watchdog instruction Thereafter its value remains fixed until a reset occurs Whe
39. s still need to be initialized as DPPO DPP1 DPP2 DPP3 CP SP STKUN STKOV and EXICON The peripheral registers are also identical to the ST10 ones but their function may have changed slightly For more information refer to Standard Peripheral User s Manual especialy sub sec tions ST10 Upgraders After reset the compatible behaviour has been chosen every time it was possi ble the concerned peripherals are The input output ports number and function changed The general purpose timers 1 and 2 slightly changed The asynchronous synchronous serial interface The synchronous serial channel The pulse width modulation The differences are listed below The SYSCON1 register needs to be initialized It configures the peripheral bus clock and the sleep mode See Section 2 11 The New Clock Tree and Section 2 13 The New Power Saving Mode The SYSCON2 and SYSCONG registers can be initialized to determine the port behaviour during power saving modes and disable unused peripherals The RSTCON register can be initialized It configures the length of reset and the behaviour of the RSTOUT2 pin See Section 2 12 Reset Mechanism The WDTCON register has slightly changed The prescaler is more configurable and it is not possible any more to detect a watchdog reset from this register The SYSSTAT register can be read before the EINIT instruction to determine the source of reset i e whether it is
40. software hardware or watchdog After the EINIT instruction this register is cleared The VECSEG register can be updated with the new vector table segment if it is different from its reset value The SPSEG register can be initialized with the system stack segment number The BNKSELO and BNKSEL 1 registers need to be initialized to use the automatic fast bank switch upon interrupt entry The FINT1CSP FINT1ADDR FINTOCSP and FINTOADDR registers need to be initialized to use the interrupt jump table cache The PECCx and PECSEGx registers must be initialized to use a PEC transfer The PECISNC and EOPIC registers can be initialized to use a PEC interrupt sub node control The EXISEL register can be initialized to select between different external interrupt sources The fast external interrupt control registers CCxIC changed their names to FEIyIC 4 2 3 External Bus Controller Registers The Super10 external bus controller is compatible with the ST10 one but it has been made more config urable Therefore the register programming has changed Moreover to take advantage of a higher clock speed the number of wait states needs to be increased if the external memory latency stays identical For these reasons the ST10 BUSCONXx registers are replaced by a set of registers EBCMODO programs the general behaviour of the external bus FCONCSx x 0 7 configures the corresponding chip select features
41. t ky 11 26 AN1982 APPLICATION NOTE SOFTWARE DIFFERENCES Most of the differences leading to a necessary change in the software are due to changes in the Super10 system such as the reset configuration the external bus controller or peripheral management but not to the core itself This means that most of the software differences will take place before the EINIT instruc tion is executed and that a lot of care will have to be taken when converting this system configuration rou tine See Chapter 4 Converting the System Configuration Routine Nonetheless the changes needed to be done in the main part of the software are described in this chapter 3 1 Binary Code Compatibility Linked to the fact that the repeat capability is removed from the Super10 core See Section 3 3 Repeat Capability of the Multiply and Accumulate Unit for more details the encoding strategy of some instruc tions especially the MAC instructions has slightly changed It means these instructions are no longer binary compatible but still code compatible A new assembler is used to generate the Super10 opcodes but no modification of the assembly source code is necessary 3 2 New Pipeline Behaviour Due to the fact that the pipeline is fully interlocked all software addendum taking care of ST10 particular pipeline effects can be removed For instance a GPR can be used in the instruction following the CP update and a new DPP or SP value can be used by
42. t scheme 3 5 Improved Behaviour of Bit Field Instructions On ST10 the bit field instructions had an unexpected behaviour This behaviour has been enhanced in Super 10 For instance let s consider the BFLDL bitoff ZAND mask OR mask instruction On ST10 bits masked with 0 in the AND mask may be unintentionally altered if the corresponding bit the OR mask contains 1 On Super10 all bits masked with a 0 in the AND mask will never be altered BFLDH RO 080h 01h clears bit RO 15 set bit R0 8 on ST10 Does not alter R0 8 on Superl0 3 6 Stack Operations For performance reasons the TRAPs for stack overflow or underflow will only be activated on system usage but no more on user arithmetic or a direct move to the stack pointer The check of SP against STKOV or STKUN is performed only on the following cases PUSH POP CALLA CALLI CALLR CALLS PCALL RETP RET RETI RETS SCXT TRAP Push sequence corresponding to the entering of an interrupt or a hardware trap For instance SUB SP 2 May result in a stack overflow but the TRAP will never be triggered Therefore it is recom mended to implement a user stack with manual checking for underflow or overflow if arithmetic operations are needed on the stack pointer This user stack should be used to allocate data dynamically or to pass parameters to functions as arithmetic operations on the stack po
43. t the system needs to be initialized again and then jump to the main program For per formance reasons the vector table needs to be in internal program memory The routine can be found in the annexe 20 26 ky AN1982 APPLICATION NOTE 5 CONCLUSION This note has described all the differences between the ST10 and the Super10 architectures It also shows the necessary changes in the application software when they are absolutely needed from a func tional point of view In addition the code can be optimized to take full advantage from the new architec ture and use efficiently all implemented features These hints will be described in a future application note Optimizing code for Super10 6 REFERENCES Super10 User s Manual Release 1 3 Super10 Megacell Specification Super10 Standard Peripheral User s Manual Release 1 2 7 ANNEXE THE SOFTWARE INCLUDED IN THIS NOTE IS FOR GUIDANCE ONLY STMicroelectronics SHALL NOT BE HELD LIABLE FOR ANY DIRECT INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM USE OF THE SOFTWARE KKKKKKKKKKKKKKKK c 2 0 0 0 STMicroelectronics KKKKKKKKKKKKKKKKKKKKKKKKKKKKK F PROJECT Super 10 Evaluation board COMPILER ST10 Superl10 Assembler TASKING MODULE Cstart asm VERSION V 1 0 CREATION DATE 03 00 LA AUTHOR Stephane MARMEY DMD Application STMicroelectronics Grenoble LA LCk ck DK
44. tatus after executing command 4 before executing a write access to any access controlled register Correct programming example MOV SCUSLC 08EFFH loop CMP SCUSLS 08800H JMP cc_Z loop MOV SYSCON1 00001H 4 1 2 External Access After External Bus Controller Configuration After modifying the EBC configuration it can take a few cycles before this modification takes place because the clock applied to the external bus register is slower than the CPU clock Therefore data accesses as well as code fetches to the modified chip select have to be delayed until the configuration is valid After the write access to the configuration register is executed the next external bus access needs to be based on this new configuration Wrong programming example Data access MOV Ry OFEOFH MOV Rx 00031H MOV FCONCS1 Rx MOV DATA1 Ry Assumption Variable DATA1 is handled by CS1 Code fetch MOV Rx 00031H MOV FCONCS2 Rx JMP SEG Labell SOF Labell Assumption Labell is handled by CS2 4 1 2 1 External Data Access The application software has to read back the content of the last written EBC configuration register before accessing any data on the modified chip select The CPU stalls the pipeline in case of a pending IO write until the write access is done before the next IO read is executed Therefore the write access is done before the data access takes place ky 17 26 AN1982 APPLICATI
45. the following instruction ST10 Code Super10 Code SCXT CP OFCOOh SCXT CP 0FCOOh NOP MOV RO data OV RO data ao MOV DPPO 44 OV DPPO 4 MOV DPPO variable R1 NOP Sse OV DPPO variable R1 MOV SP 0FA40h POP RO OV SP 0FA40h NOP POP RO When disabling interrupts the sequence of instructions starting with the one clearing the IEN bit will never be interrupted When initializing port pins no special care has to be taken anymore ST10 Code BSET DP3 13 NOP any instruction not accessing port3 BSET P3 5 Super10 Code BSET DP3 13 BSET P3 5 There will also be a difference in execution if a programmer was using a feature of the ST10 non inter locked pipeline As an example let s consider the following code OV DPPO 41 NOP Assume that all variables use DPPO OV eml RO Meml uses page 1 OV em2 RO Mem2 uses page 1 OV DPPO 42 NOP OV em3 R1 Mem3 uses page 2 12 26 AN1982 APPLICATION NOTE For performance reasons the programmer may have been tempted to write MOV DPPO 1 NOP Can not be removed on ST10 MOV Meml RO Meml uses page 1 MOV DPPO 2 MOV Mem2 RO Mem2 still uses page 1 compatibility issue MOV Mem3 R1 Mem3 uses page 2 This code assumes that no interrupt occurs between the DPP change but the same issue can exist in interruptible code For
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