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Using the Electric VLSI Design System

1. Using the Electric VLSI Design System version 8 11 243 Chapter 8 Creating New Technologies Nodes lt primitiveNode gt elements describe primitive node in the technology They have these attributes Example name is the name of the node prototype Instances of this primtive node in Electric libraries reference this name e fun describes the node function UNKNOWN PIN pins connect arcs NODE pure layer nodes CONTACT CONNECT nodes that connect all arcs TRANMOS TRADMOS TRAPMOS TRA4NMOS TRA4DMOS TRA4PMOS MOS transistors TRANPN TRAPNP TRA4NPN TRA4PNP Bipolar transistors TRANJFET TRAPJFET TRA4NJFET TRA4PJFET JFET transistors TRADMES TRAEMES TRA4DMES TRA4EMES MESFET transistors TRANS TRANS4 generic transistors TRANSREF reference transistors RESIST PRESIST WRESIST ESDDEVICE resistors CAPAC ECAPAC capacitors DIODE DIODEZ diodes INDUCT inductors METER meters BASE EMIT COLLECT Bipolar transistor parts BUFFER GATEAND GATEOR GATEXOR logic gates FLIPFLOPRSMS FLIPFLOPRSP FLIPFLOPRSN RS flipflops FLIPFLOPJKMS FLIPFLOPJKP FLIPFLOPJKN JK flipflops FLIPFLOPDMS FLIPFLOPDP FLIPFLOPDN D flipflops FLIPFLOPTMS FLIPFLOPTP FLIPFLOPTN T flipflops MUX multiplexors CCVS CCCS VCVS VCCS TLINE two port gates CONPOWER CONGROUND SOURCE power ground SUBSTRATE WELL implants ART artwork ARRAY array nodes ALIGN alignment nodes lt primitiveNode na
2. The right side of the dialog has User Preferences Each layer of every technology is listed and you can set its unit resistance area capacitance and edge capacitance The bottom section controls values for every layer in a technology You can set the minimum resistance and capacitance as well as the maximum series resistance The maximum series resistance breaks long single PI models into series of distributed PI models Include Gate In Resistance requests that a transistor s gate area be included in overall area calculations for resistance determination Include Ground Network requests that ground networks be analyzed The Gate Length Shrink is a compensation factor for gate lengths Some process technologies shrink the gate length by a fixed 334 Using the Electric VLSI Design System version 8 11 amount Chapter 9 Tools The left side of the dialog has Project Preferences e Use Verbose Naming The parasitic extractor inserts resistors and thus makes multiple networks out of a single network The new networks are automatically named by the netlister Normally the names are simple such as oldnetworkname 1 When verbose naming is requested the network names include the nodes to which they connect for example oldnetworkname m1m2conn conn 0 This makes it possible for the user to cross probe back to the layout from the expanded Spice file but it makes the file larger e Back Annotate Layout transfers schematic net
3. The User Preferences part of the dialog controls DXF input By default Electric flattens DXF input removing levels of hierarchy and creating a single cell with the DXF artwork By unchecking the Input flattens hierarchy Electric will preserve the structure of the DXF file If you uncheck Input reads all layers then unknown layers are not read into Electric Using the Electric VLSI Design System version 8 11 199 Chapter 7 Technologies 7 3 8 SUE Control SUE Schematic User Environment is the database format of the SUE schematic editor from Micro Magic www micromagic com For more information on reading SUE see Section 3 9 2 Preferences Ea ua Categories SUE USER Preferences General Display i A Yo SUE options are controlled with the SUE ey aF Preferences in menu File Preferences i GDS I O section SUE tab EDIF DEF EDLE DXF Library Copyright 7 Make 4 port transistors This dialog has two controls e Make 4 port transistors requests that transistors be 4 port with a substrate connection The default is 3 port e Convert Sue expressions to Electric requests that SUE expressions be analyzed for parameter references and E Tools E Technology I Convert SUE expressions to Electric converted to Electric parameter form Epot mot with an in front of the parameter Reset All name Only resets USER Preferences Help Apply Cancel 200 Using the Ele
4. Besides geometric layers the graphical arc description must have a highlight layer to show where the arc will be outlined when used in a circuit Although the highlighting is typically drawn around the outside of all geometry implant N Opened Thicker Polygon layers may extend beyond the highlight see the CMOS diffusion arcs foran f i f Opened Circle example of this Select the HIGH entry in the component menu to create Q this special type of layer J Filled Circle After geometry has been created there may be some confusion as to what is there To find out use the Identify Primitive Layers command in menu Edit Technology Editing which temporarily labels each piece of geometry in the arc cell Using the Electric VLSI Design System version 8 11 225 Chapter 8 Creating New Technologies 8 6 The Node Cells Creating and Deleting Node Cells Nodes are the components in a technology and they are constructed from pieces of geometry on the layers To edit an existing node select it from the cell explorer or the Edit Cell command in menu Edit To create a new node use the context menu on the TECHNOLOGY NODES entry nE Of the cell explorer and choose Add New Node A node can be deleted simply by ad New Moda deleting its cell A node can be renamed by renaming its cell but remember to use the Reorder Nodes name node in front i e the old name is node metal and the new name is node metal 1 Fina
5. C Tools Fast Henry USER Preferences Antenna Rules Compaction Coverage I Use single frequency Default thickness B DRC Ree Frequency start fo Default width subdivisions fi Export Import Frequency end fo Default height subdivisions fi PER Reset All Runs per decade fi Maximum segment length fo Only resets USER Preferences I Make mukipole lt ubcicust ind AEE MUMbEP oR Boles T20 cn This dialog allows you to set the type of frequency analysis single frequency or a sequence specified by a start end and number of runs per decade You can choose to use single or multiple pole analysis and if multiple you can specify the number of poles The FastHenry Preferences dialog also allows you to set defaults for the individual arcs that will be included in the deck You can specify the default thickness and the default number of subdivisions in height and width Using the Electric VLSI Design System version 8 11 283 Chapter 9 Tools 9 5 Simulation built in 9 5 1 IRSIM Electric has a built in simulator Stanford s IRSIM which uses RC models to accurately simulate transistors at a gate level IRSIM is not packaged with the standard Electric distribution To obtain it you must get the additional plugin JAR file from Static Free Software see Section 1 5 for instructions on installing plugins To simulate the current cell with IRSIM use the IRSIM Simulate Current Cell command in me
6. For more information about Maximum undo history see Section 6 7 The Logging Options section controls Electric log files By default log files are produced during the session but this can be disabled by unchecking Enable logging By default only one log file is created which is overwritten in subsequent Electric sessions Checking Multiple logs causes each log file to have a unique name so that multiple files are saved For more information about the Memory section see Section 1 3 The Database section controls aspects of the Electric database that do not affect most users Electric can run as two processes a client that manages the display and a server that manages the database By checking Use Client Server interactions Electric will use this experimental configuration Checking Snapshot Logging requests debugging information on the client server interactions 260 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools 9 2 Design Rule Checking 9 2 1 Introduction There are three built in design rule checkers incremental hierarchical and schematic After analysis of the circuit you can review the errors by typing gt and lt to step to the next and previous error that was found You can also see a list of errors in the cell explorer see Section 4 5 2 Incremental DRC The incremental design rule checker is always running examining your layout and issuing error messages
7. Only resets USER Preferences Help Apply Cancel Using the Electric VLSI Design System version 8 11 273 Chapter 9 Tools 9 4 3 Spice Electric can produce input decks for Spice simulation with Write Spice Deck command in menu Tools Simulation Spice After this has been done you must run Spice externally to produce a simulation output file Note that the Electric distribution does not come with a Spice simulator you must obtain it separately Once Spice has been run you can see a plot of the simulation by reading the Spice output file back into Electric Since there are may formats of Spice output you must first set the Spice Engine and the Output format fields of the Spice Preferences in menu File Preferences Tools section Spice tab The Output format field is Standard for the default output of the Spice engine Raw for rawfile dumps and Raw Smart for the rawfile dumps from SmartSpice When Electric knows what type of Spice output file to expect use the Plot Spice Listing command in menu Tools Simulation Spice to read the file If the file has the same name as the current cell you can more simply use Plot Spice for This Cell which does not need to prompt for a file name The Spice simulation information is shown in an analog waveform window see Section 4 11 2 for more Special Spice Nodes There are many powerful facilities for running Spice with Electric The example sho
8. 5 4 5 Curvature An unusual arc property used only in circular geometry is curvature Although most arcs cannot handle curvature those in the Artwork and Round CMOS rcemos technologies can The Curve through Cursor command in menu Edit Arc requests that the currently highlighted arc curve in such a way that it passes through the location of the cursor The Curve about Cursor command requests that the currently highlighted arc curve between its endpoints such that the center of curvature is at the location of the cursor After issuing these commands click and drag to see how the arc will curve The Remove Curvature command makes the arc straight 140 Using the Electric VLSI Design System version 8 11 Chapter 5 Arcs 5 5 Default Arc Properties The Arcs Preferences in menu File Preferences General section Arcs tab lets you control the arc creation process It does not affect existing arcs only those that are subsequently created The top part of the dialog allows you to set defaults for specific types of arcs You select the Technology and Arc Type and then set defaults for it such as the Default width The Default width field specifies the width of newly placed arcs When there are already arcs connected to one of the nodes being wired the new wire is made as wide as the widest existing arc on either node Also when the nodes are larger than normal arcs connected to them will be made appropriat
9. After writing deck Don t Run X Run program with args i P Use cits P GYyEHVTte existing cutBUE RIE no prompts Run probe Hela Reading Spice Output Output format Standard 7 Epic reader memory sizer fiooo Extracted network delimiter character Using the Electric VLSI Design System version 8 11 277 Chapter 9 Tools The top part of this dialog allows you to control Spice deck generation e Spice engine Can be Spice 2 Spice 3 HSpice PSpice Gnucap or SmartSpice e Spice level Can be 1 2 or 3 not used anymore e Resistor shorting Specifies which resistors get shorted when writing a Spice netlist from a schematic Choices are none no resistors are shorted This preserves all resistors useful for simulations normal only only normal schematic resistors are shorted This is useful when running external LVS tools like Calibre and Assura against a Spice netlist because it shorts out parasitic resistors such as from wire models but preserves poly resistors which are actual devices in the layout normal and poly both normal and poly schematic resistors are shorted This is available only because the Verilog netlister uses the same netlisting subsystem it is unlikely that you will want this setting for Spice netlisting e Parasitics Controls the writing of parasitics in the Spice deck Choices are Trans area perim only which writes the area and perimeter of transisto
10. Everywhere all displayed text Het Reset All Default Font SansSerif z Only resets USER Preferences Annotation text Instance names Cell text Smart Text Grid Size Ports Exports fi Units max 127 75 Points max 63 Frame 3D Anchor centered Y Seeeseeevees a P Invisible outside cell if Default global text scale Help Apply for new windows 199 perz Global text scale in Cancel the current window oe 158 Using the Electric VLSI Design System version 8 11 Chapter 6 Advanced Editing The Smart Text Preferences in menu File Preferences Display section Smart Text tab controls where new text will appear on Exports and Arcs C General E Display Display Control Component Menu Layers Toolbar Text Smart Text Grid Ports Exports Frame 3D amp o aro Tools Technology Export Import ik Reset Reset All Smart Text USER Preferences Smart Text placement indicates the default location of new text Smart Placement of Arc Text Vertical arcs Inside Left Right Horizontal arcs Inside Above C Below Smart Placement of Export Text Near celltop bottom Off Inside Outside Near cell left right Off C Inside Outside Only resets USER Preferences Help Apply Cancel gu For arcs you can choose to place the name on the i
11. For individual nodes the Object Properties dialog in menu Edit Properties lets you control its rotation and mirroring Be aware that mirroring is not the same as rotating even though both may produce the same visual results Mirroring causes the node to be flipped about its horizontal or vertical centerline and thus appear backwards 58 Using the Electric VLSI Design System version 8 11 Chapter 3 Hierarchy 3 1 Cells A collection of nodes and arcs is called a cell and instances of cells can be placed in other cells When a cell instance is placed that instance is also a node and is treated just like the simpler transistor and contact nodes Thus nodes come in two forms primitive and complex Primitive nodes are found in the component menu and are pre defined by the technologies transistors contacts pins Complex nodes are actually instances of other cells and are found in libraries Besides organizing cells into a hierarchy Electric also organizes cells into cell groups and gives CELL _ _ _ _ _ __ _ each cell a view and a version A cell s view GROUP Different Views describes its contents for example layout Old schematics netlist etc A cell s version Versions CELL CELL CELL defines its design age The full name of a cell is CELL CELLNAME VERSION VIEW ELL MyCircuit LIBRARY CELL where CELLNAME is the name of the cell VIEW is the abbreviated name of this cell s view and V
12. amt This is the constraint that all arcs must stay in their ports even across hierarchical levels of design When a node in a cell moves and has an export on it all the ports on instances of that cell also change The constraint system therefore adjusts all arcs connected to those instances and follows their constraints If those constraints change nodes with exports in the higher level cell then the changes propagate up another level of hierarchy Before After This bottom up propagation of changes guarantees a correctly connected hierarchy and allows top down design Users can create skeleton cells that are mostly empty and contain only exports on unconnected nodes They can then do high level design with these skeleton cell instances Later when circuitry is placed in the cells or when layout views are substituted for the skeletons the constraint system will maintain proper connectivity in all higher levels of hierarchy The hierarchical propagation aspect of the constraint system leaves open the possibility of an overconstrained situation For example if two different cell instances are connected to each other with two rigid wires and one connection point moves then it is not possible to keep both wires rigid Electric jogs an arc converting it into three arcs that zigzag to retain the connection Although connectivity is retained the geometry may be in the wrong place causing unexpected changes to the circui
13. if gu Layers Toolbar Text Smart Text Grid Ports Exports Frame 3D Tools Technology Import Reset All Only resets USER Preferences Apply IV Show hierarchical cursor coordinates in status bar Side Bar defaults to the right side IV Dim upper levels of hierarchy when editing Down In Place P Show cell results in new window IV Make error highlighting pulsate Panning distance Medium X Display style Operating System default X Display Algorithm Pixel Display Algorithm old vector Display Algorithm new P Use cell images when simplifying Simplify objects smaller than Bo pixels Do not simplify cells greater than 10 0 percent of screen Layer Display Algorithm experimental Pattern scale limit p s IV Use newer blending algorithm Alpha blending overcolor limit o s Reset all Layer Opacity Yalues The status area at the bottom of the screen shows current selection cursor coordinates etc If Show hierarchical cursor coordinates in status bar is checked it will also show global coordinates when traversing the hierarchy The side bar can be set to always show on the right by checking Side Bar defaults to the right side See Section 1 7 for more on the side bar When editing down in place the upper levels of hierarchy are dimmed Some displays find this difficult to do and draw slowly in down in place mode This is particularly noticeable on X Window
14. Antenna Rules Preferences Antenna Rules in menu File Compaction Arcs in technology mocmos X Preferences Tools Coverage section Antenna Rules f Ki Fast Henry tab The dialog lets you Logical Effort modify the required ratio of NCC a layer poly or metal to Network x the transistor area Brat import Polysilicon 1 200 0 Reset Reset All Only resets USER Preferences Help Apply Cancel Maximum antenna ratio fano 268 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools 9 4 Simulation Interface 9 4 1 Introduction Electric has two built in simulators IRSIM see Section 9 5 1 and ALS see Section 9 5 2 It also can generate decks for many other simulators The ability to interface to external simulators is controlled with the Tools Simulation Spice Tool Simulation Verilog and Tools Simulation Others menus Be aware that the Electric distribution does not come packaged with these external simulators You must get your own copy of Spice Verilog or any other simulator mentioned here Electric can write netlists for these simulators Netlist Command circuit Tools Simulation Spice Write CDL Deck OSMOS swith Tools Simulation Others Write COSMOS Deck Si Cosmos IRSIM PAL SIM egas erilog PAL gate Tools Simulation Others Write PAL Deck RSIM _ with_ Pools Simulation Others Write RSIM Deck Tools Simul
15. ElPrim is the Electric primitive name e g Transistor E1Func is the Electric function e g CONPOWER E1Rot is the Electric rotation e g 90 Using the Electric VLSI Design System version 8 11 195 Chapter 7 Technologies E1PortOf f is the Electric port offsets enclosed in braces e g g 1 0 The offsets are the values required to move the port to the origin so if a port is at 2 5 the offset should be 2 5 Each port on the primitive must be listed and an offset given To ignore a port use NA instead of port x y You can also specify an ignored port as NA x y if you want to affect how an attached wire s endpoint is modified NA by itself is the same as NA 0 0 If the port s name is NA use NA x y to specify the name as NA and not be ignored EdTech is the EDIF technology name e g tsmc18 EdPrim is the EDIF primitive name e g pmos2v EdFunc is the EDIF function e g symbol EdPortOf f is the EDIF port offsets enclosed in braces e g G 0 0 Each port on the primitive must be listed and an offset given The offsets are the values required to move the port to the origin so if a port is at 2 5 the offset should be 2 5 For example P schematic Ground CONGROUND 0 gnd 0 2 basic gnd symbol gnd 0 0 e Cells A line starting with C controls how cells are converted to EDIF The line has this format
16. Gates router D Preferences site Routing USER Preferences Antenna Rules Stitching Routers Mimic Stitcher Compaction Coverage DRC Auto stitcher running Restrictions when non interactive Fast Henry C Mimic stitcher running D Ports must match Logical Effort a E I Bus ports must have same width NCC Use this arc in stitching routers I Number of existing arcs must match Network Parasitic Jeciiniclouy Node sizes must match Placement age netal 1 IV Node types must match J IV No other arcs in the same direction Silicon Compiler Sea of Gates Router Ignore if already connected elsewhere Simulators Technology mocmos K ad Auto Stitcher Spice Spice Model Files gt j I Favor Prohibit avila Favor Prohibit Export Import x m Pascas F PaocbibLii Reset Reset All Maximum arc width fio Only resets USER Preferences Search complexity limit 200000 Help Apply If there are multiple processors available IV Use two processors per route Cancel Do multiple routes in parallel No stitcher running P Interactive mimicking Keep pins I Create exports where necessary ik gu 9 6 2 Auto Stitching The auto stitching router looks for adjoining nodes that make implicit connections and places wires at those connections to make them explicit For example if a cell has power and ground rails at the top and bottom
17. Overlay Signal in Waveform o lopen Library 3 9 2 Window 4 11 2 P Peek 3 4 Pan Mode 4 4 2 Q Quit 1 10 9 Cycle through windows 4 3 Window 4 11 2 U UpHiierarchy 5 G W Close Window D G Using the Electric VLSI Design System version 8 11 15 Chapter 1 Introduction Key Control 0 Zoom Out 4 4 1 1 2 Pan Down 4 4 2 ie et ee ee Pan Left 4 4 2 Pan Right 4 4 2 Zoom In 4 4 1 Pan Up 4 4 2 Wire to Poly 1 8 See AllLayers 4 S 3 ssid Wire to Metal 1 1 8 See Metal 1 4 5 3 F1 Mimic Stitch 2 EGS 9 6 3 Wire to Metal 2 1 8 See Metal 2 1 4 5 3 eee Stitch Wire to Metal 3 1 8 See Metal 3 2 4 5 3 Wire to Metal 4 1 8 See Metal 4 3 4 5 3 Wire to Metal 7 1 8 See Metal 7 6 4 5 3 Wire to Metal 8 1 8 See Metal 8 7 4 5 3 i i Fill Window 4 4 1 Increase all Text Size 6 8 4 Decrease all Text Size 6 8 4 EL SPACE Left Move more left Arrow 2 4 1 Right Move more right Arrow 2 4 1 Up Arow Move more up 2 4 1 Down Move more down Arrow 2 4 1 16 F9 Tile Windows Wire to Metal 9 1 8 See Metal 9 8 4 5 3 Erase 2 3 Repeat Last Action 6 7 Show Next Error 9 1 Show Previous Error 9 1 Show Next Error same Window 9 1 Show Previous Error same Window 9 1 Switch Wiring Target 1 8 Move more left Move left 2 4 1 2 4 1 Mov
18. Spice Code Spice Declaration Verilog Code and Verilog Declaration e Schematic and icon cells can have parameter definitions and the instances of those cells can have parameter values see Section 6 8 5 Essentially every piece of text on the display is tied to some node or arc or occasionally a cell By understanding the relationship between text and its attached object it becomes easy to manipulate that text The visibility of text can be controlled with the Layers tab of the sidebar see Section 4 5 3 This allows you to reduce the clutter of text on the display When the node or arc that the text is tied to is modified rotated or mirrored the text adjusts as well The two text factors that change are 1 the offset of the text from the center of the node and 2 the anchor point The example here shows the rotation of an offpage node that A has an export on the flat end The left side of the example Release gt shows the node and text before the node is rotated the export text is anchored on the right side the green U shows the Rele asel anchor point see Section 6 8 2 and the anchor point is offset to the left of center so that it starts at the left side of the node After rotation on the right the export text is anchored on top and the anchor is rotated to be below the node Note that all other text factors remain unchanged when the attached object is modified This includes the text rotati
19. The section labeled Display ordering controls the order in which Order by modification date the selected cells will be listed Order by skeletal structure a Pee Destination The section labeled Destination allows you to dump this listing to a disk file formatted for spreadsheets tab separated Display in messages window C Save to disk Cancel The Evaluate Numbers when Sorting Names checkbox controls how cells are sorted only relevant when cells are to be ordered by name When checked numbers inside of cell names are evaluated and sorted numerically Thus a set of cells called A8 A9 A10 and A11 will appear in that order When not checked cells are sorted lexically causing the cells to appear in this order A10 A11 A8 A9 72 Using the Electric VLSI Design System version 8 11 The result of cell information listing looks like this Cell Version Creation tech Artwork 1 Dec 31 1969 tech Bipolar ic 1 Dec 15 2004 tech Bipolar lay 1 Jul 23 1990 tech Bipolar sch 1 Jul 26 1990 tech DigitalFilter 1 Dec 31 1969 tech MOSISCMOS lay 1 Jul 24 1998 tech PCB7404 1 Dec 31 1969 tool_NCC sch 1 Mar 27 2001 The last five columns show the usage and four state bits 15 15 15 15 01 09 15 25 appears as an instance in other cells The state bits are e L if the cell contents are locked e I if instances in the cell are locked e S if th
20. Vy IPRA Aff OL ies f Y Ys A Y Highlighted Network Sas SA SSS f PPPRP IAF IE fff ff of P F Lf f IS Z PPP Yy Pd Z Z Y Sf Y Fi f A ff Yj a J Y h if It is important to understand that Electric is not exactly a WYSIWYG editor what you see is what you get Nodes that are touching on the screen may not actually be connected if there are no arcs joining them The best way to ensure that the circuit is correct is to highlight a node and see 42 Using the Electric VLSI Design System version 8 11 Chapter 2 Basic Editing the extent of the connections on it 2 1 3 Unusual Selection Areas and Text Besides highlighting nodes and arcs Electric can also highlight an arbitrary rectangular area The notion of a highlighted area as opposed to a highlighted object is used in some commands and it generally implies highlighting of everything in the area There are two ways to highlight an area If you click the eft button where there is no object and hold it down while dragging over objects all of those objects will be highlighted Object selection Area selection To more precisely define a highlighted area switch to area selection as opposed to object selection with the Select Area command in menu Edit Modes a E Select or click on the Area Selection icon in the tool bar Use Select Objects to revert back to object selection Once in area selection mode
21. create the new cell newCell Cell makeInstance Library getCurrent sample2 lay tech Technology findTechnology mocmos place a rotated transistor trP tech findNodeProto P Transistor tP NodeInst makeInstance trP Point2D Double 0 20 trP getDefWidth trP getDefHeight newCell Orientation R T1 place a metal Active contact coP tech findNodeProto Metal 1 P Active Con maP NodeInst makeInstance coP Point2D Double 8 20 coP getDefWidth coP getDefHeight newCell wire the transistor to the contact aP tech findArcProto P Active ArcInst makeInstance aP tP findPortInst diff bottom maP findPortInst metal 1l p act export the contact Export newInstance newCell maP findPortInst metal 1l p act IN PortCharacteristic IN Using the Electric VLSI Design System version 8 11 177 Chapter 6 Advanced Editing 6 12 Project Management The project management system in Electric allows multiple users to work together on the design of a circuit This is accomplished by having a repository in a shared location and local libraries in each user s disk area Users work on cells by checking them out of the repository making changes and then checking them back in The project management system ensures that only one user can access a cell at a time In addition it also applies its understanding of the circuit hierarchy to inform users of potential incons
22. x 1 and an arc called internal Both the export name and the arc name were n selected and the command Parameterize Bus Name issued in menu Edit Properties The templates are then shown near the original names Arrayed nodes can also have their names parameterized ARC_Bus_Template intemal 1 50 You may type any text into the template Wherever the string par appears it will be replaced with the parameter par In this example the parameter x has the value 7 You can also use simple arithmetic operators just and for example in 0 x 1 defines a bus that runs from 0 to one minus the value of x When parameter values change click the Update All Templates button to reevaluate all node arc and export names 6 9 4 Power and Ground Identification of a power network is done by finding e a Power node from the Schematic technology e an export in the current cell that has the power characteristic an export in the current cell that begins with the letters vdd vcc pwr or power a port on a component in the current cell that has either of the above two properties wow 2 Ground networks use the same rules except that the acceptable port names begin with vss gnd or ground Using the Electric VLSI Design System version 8 11 167 Chapter 6 Advanced Editing All supply networks defined with the Power and Ground nodes of the Schematic technology are combine
23. 100 with the metal 3 bar The second line generates the fill cell fillCW with an instance of cap and metal arcs from the rest of the input cells The third line generates the cells fillD fillD2x4 and fillID2x2 where fillD2x4 and fillD2x2 are 2x4 and 2x2 arrays of fillD that contains all arcs defined in the input cells fillB metals45 and metal6 328 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools e Generate gate layouts MoCMOS Generates the layout for schematic cells in the Purple and Red libraries see Section 9 9 To use this command you must have a schematic in the current window The command then hierarchically scans the schematic looking for instances of the Purple and Red library cells When it finds such instances it generates layout for them and places the layout in a library called autoGenLibMOCMOS If the cell already exists it is not regenerated The gate layout generator recognizes these gates from the Purple and Red libraries inv mullerC_sy nand2HTen nms2K inv2i nand2 nand3 nms2_sy inv2iKn nand2HLT_sy nand3LT nms3_sy3 inv2iKp nand2LT nand3LT_sy3_ nor2 invCLK nand2LT_sy nand3LTen nor2kresetV invCTLn nand2PH nand3MLT pms1 invHT nand2_sy nand3en pms1lK invK nand2en nms1 pms2 invLT nand2k nmslK pms2_sy inv_passgate nand2LTen nms2 Using the Electric VLSI Design System version 8 11 329 Chapter 9 Tools 9 9 Logical Effort The Logical Effort tool examines a digital s
24. 222252 DDD DDD 1222224 PADDADD DDD DDD ee Ree FE Ea a ee eeees SD DD DD Lap Sp ip Bb Sb Sb ad Ap DDD DD I j P2229 9 2 Connections between pads and ports of the 2333333 sift rEeTeT Ty gt Sb Bp BD DBD BD a SH errr rr core cell use Unrouted arcs from the Generic 99099 Fi 882 aaae technology see Section 7 6 3 After these connections are routed with real geometry a eee FEEFEE DD the finished layout is shown here fully S239 3b 2 39 3 f DDD DD DD instantiated eee ey PEPEPEPE Ap Ap AD BD DD FFFEEEr ee es Bes Be he Ea ee he he be Fe ye as as as ae TLZ LL R222222 FIYYTT Dap Sp ad 3d aaaa gt gt PDABADD DDD DDD PPADADD ry yv yyy DADAADD Pyy yy T PPDDDDD DDD DM Using the Electric VLSI Design System version 8 11 323 Chapter 9 Tools 9 8 2 Other Generators There are other generators built into Electric These commands in menu Tools Generation may be used e Coverage Implants Generator Although individual MOS nodes and arcs have the proper amount of implant around them a collection of such objects may result in an irregular implant boundary To clean this up you can place pure layer nodes of implant that neatly cover the implant area see Section 7 1 1 This command does it automatically It removes previous pieces of coverage implant before running so that the result is a clean cover e ROM Generator The ROM generator constructs many cells to describe a ROM from a p
25. About Hectric x The Electric YLSI Design System Version 8 11 Written by Steven M Rubin The Java Team Cast of Thousands N America v Gilda Garret n DRC ERC 3D technologies fill generation a David Harris ROM generator Color printing Thomas Hauck Placement tool Force Directed 1 Jochen Huck Placement tool Force Directed 1 Jason Imada ROM generator Russell Kao NCC generators Hierarchy enumeration Regressions Daniel Lechner Placement tool Force Directed 2 Frank Lee ROM generator Jochen Lutz Placement tool Simulated Annealing 2 Ivan Minevskiy NCC display Benedikt Mueller Placement tool Genetic 2 Dmitry Nadezhin Database Networks Libraries Simulation Optimizations x Copyright c 2010 Sun Microsystems and Static Free Software This is free software and you are welcome to redistribute it under certain conditions License Details Electric comes with ABSOLUTELY NO WARRANTY This manual is available while running Electric Use the User s Manual command in menu Help to see this manual you may already be doing that While inside of the manual click Menu Help to get help with Electric s pulldown menus It displays a pulldown menu inside of the manual page which mimics the real pulldown menu Select any command from this new menu to get help for the real pulldown menu entry 2 Using the Electric VLSI Design System version 8 11 Chapter 1 Introduction 1 3 Runn
26. Advanced Editing e Multi Line Text allows the text to have more than one line After checking this box it may be useful to stretch the dialog in order to have a larger field for editing the text e Highlight Owner highlights the node or arc on which the text is attached e Invisible outside cell requests that the text not be drawn when an instance of the cell is examined Changing Multiple Pieces of Text The above dialog changes information on a single piece of text There are two ways to change information on multiple pieces of text 1 select all of the text and use Object Properties or 2 use the Change Text Size command in menu Edit Text Change Text Size Ed Ahat to Change E Change size of node text C Change only selected objects Change size of arc text Change all in this cell V Change size of export text C Change all cells with view The Change Text Size command allows you to change the size font and style of any text object Instead of selecting the text you have a choice of 6 classes of text that can be changed and you can choose whether to make the changes only on selected objects in the current cell in all cells of a particular view or everywhere Change size of annotation text schematic iad Change size of instance nametext Change all in this library Change size of cell text Text runs from 3 0 to 3 0 units L j How to Change it Cance
27. Apply and2 buf4x lay and2 buF4x sch bitlinepullups ic bitlinepullups lay bitlinepullups sch bitslice fic bitslice flay bitslice sch buf4x ic buf4x lay buF4x sch controllersic datapath ic datapath lay Derive Model from Circuitry Netlist from Layout Use Model from File Browse The same function can be done by using the Set Netlist Cell From File command in menu Tools Simulation Spice This places a piece of text in the cell which you must edit to be the path to a disk file That file will then be included in the Spice deck instead of the actual subcircuit of the cell 280 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools 9 4 4 Special Spice and Verilog Nodes For both Spice and Verilog you can place special nodes in your circuit that augment the generated deck Spice even has a predefined set of these nodes available from the Spice entry in the component menu A second set called SpicePartsS3 is tailored towards Spice3 use the Spice Preferences in menu File Preferences Tools section Spice tab to switch to this set There are no Verilog nodes in the current release of Electric Users who define new nodes for Spice or Verilog are encouraged to share these with the entire community by contacting Static Free Software Users can define their own Spice or Verilog nodes by creating new icon cells The icon cell should have e Graphics This is an ico
28. Fast Henry Ignore polygons smaller than 0 25 square units Logical Effort NCC i IV Include date and version in output files Network gt Active Handling Require separate N and P active require proper select well Import P Ignore Resistors when building netlists 7 Use pure layer nodes for connectivity Export Ignore N vs P active require proper select well C Require separate N and P active ignore select well Reset Reset All L Only resets USER Preferences Flatten cells whose names match this Kin Help Apply f va IV Flatten Cadence Pcells with number at end of name Cancel 336 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools Grid align geometry before extraction causes all coordinates to be adjusted so that they are on grid units see Section 4 7 2 This is useful for data that has precision problems Approximate cut placement relaxes the requirement that the cut or via locations appear exactly in the same place once extracted When this preference is checked Electric will find contact areas and replace them with contact nodes regardless of where those nodes place the cuts Without this preference Electric will place contact nodes in such a way that the cut layers land in the correct original locations The disadvantage of forcing exact cut placement is that Electric will create many contact nodes one for each cut layer In multi cut situat
29. For P Well For N Well NCC Network Must have contact in every area Must have contact in every area Parasitic Placement Must have at least 1 contact C Must have at least 1 contact Routing Silicon Compiler Do not check for contacts Do not check for contacts Simulators Spice IV Must connect to Ground IV Must connect to Power Spice Model Files Verilog Verilog Model Files Well Check I Check DRC Spacing Rules for Wells I Find farthest distance from contact to edge kd Export Import Reset Reset All Only resets USER Preferences Help Apply Cancel JV Use multiple processors maximum fo 0 to use all The Well Checker makes sure that there are well contacts in every area of well The dialog allows you to relax that restriction and demand only 1 well contact in each cell or not to check for contacts at all Using the Electric VLSI Design System version 8 11 267 Chapter 9 Tools The Well Checker also checks that there is a connection to power and ground in the appropriate places You can disable these checks in the Well Check dialog An additional well check is to find the farthest distance from a substrate contact to the edge of that area This check takes more time to do and so it can be disabled The Well Checker can check spacing rules between well areas Although this is generally the domain of the Design Rule Checker DRC it can be
30. Import C Size ho bolder grid dots and the drawing pie of coordinate axes When the X Reset All EZE f and Y axes are shown they pass Only resets USER Preferences Size 4 fi through the cell center Help aa Peas anes el Cancel Values of zero will cause no alignment The Alignment part of this Preferences panel is discussed in the next Section gu Using the Electric VLSI Design System version 8 11 111 Chapter 4 Display 4 7 2 Aligning to a Grid When moving or creating circuitry the cursor location is snapped to a grid so that editing is cleaner This snapping is controlled by the alignment options which are not necessarily the same as the grid options The Grid Preferences in menu File Preferences Display section Grid tab presents a dialog in which alignment values may be set For example if the grid spacing is 2x3 and the alignment is 0 5 x 0 5 then there are up to six different positions for placement inside a displayed grid rectangle Categories General Display Displ Text 3D O E Tools jay Control Component Menu Layers Toolbar Smart Text Ports Exports Frame E Technology Export if Reset Help Cancel gu Import Reset All Only resets USER Preferences Apply Grid USER Preferences Grid Display Horizontal Vertical fi fi Default grid spacing For new windows fi fi Frequency o
31. In general different libraries are completely separate collections of cells that do not relate For example two cells in different libraries can have the same name without being the same size or having the same content Although a cell from one library can be used as an instance in another this causes the two libraries to be linked together It may be simpler to copy the cells from one library to another thus allowing a single library to contain the entire design A simple way to copy cells from one library to another is to drag them in the Explorer window see Section 4 5 2 A more powerful method is the Cross Library Copy command in menu Cell This command provides a dialog for copying cells between libraries The left and right columns show the contents of two different libraries and the pulldowns above each column let you select the two libraries that you want to see When there is a cell with the same name in both libraries the system compares them to determine which is newer If you check Date and content and then Compare to do comparison again Electric will compare the actual contents of cells when determining their equality Unchecking Examine quietly will cause the system to describe differences found during comparison I Date and content IV Examine quietly Cross Library Copy Ea purpleFive S purpleFour Se in 2o sch inv3tot ic in v3to1 sch invCTLni ic in
32. The Technology Creation Wizard seseseseeseesessssressesrrssreresresesrrerestestesestestessestesresesresseses 252 Chapter 9 TO0NSiicciccccttisacstissatececesacccsnsoescontessenssvaovcscncsuscesosneespuedscetssneusuuescegassseacersovoceetevesedsseesesduevesscesseseanee 259 Qa Introducti pn i e ia E EER Ea E E a AE E aa aa R aE Ia N S 259 9 2 Design Rule Checking spie nna date ia A T S i rie 261 0 3 Electrical Rule Checkin gilesni aiite a aeia ea a ee ae a ets 267 9 4 Sim lationInt rface raene e e a e a 269 9 5 Simulation H0iH aasaga a E AAE AS E bedeuve EE a AA 284 9 6 ROUNE sioe eeir ie E Ei EE ET E AEE TE EEEE T E E A e E Tes 297 9 7 Network Consistency Checking NCO eessessessseesssssessssressesssesesesssessressressesseesstessteseeeseeesseseses 302 9 8 Generato eie e aer er shes n a ov e A aae aa oeaio Tr eesi Enh 321 9 9 Logical Btortac winsileiul wana lie eine ada EAEE AEE Ee EEEREN ieee 330 9 10 Extractions s ee n a a ee Aen Oa E e a deal iden A EA RS 334 OR Tile Compac onnes eee e E E E ER A E a dos E aae a 338 O 1 22 Silicon Compiler senenn a e e E ai ol a a Ee EN a 339 Q 132 Placement n oe orerar eae a EE E aE T E ea E EE E TTEA AS ESEE S 341 Chapter 10 The JELIB and DELIB File Format sesssessocssoessccssccsscssccssocesoceccesoossoossosesoessosssesesesssessoses 343 10 41 Introductions oann nnne e a e e E a R E E E RAESTE 343 1O 2 n GE e S EANAN AEAN A a A E A acta tes 345 103 B dY murran ann aa WRAL ant
33. To zoom into an area click and Q drag out that area To zoom out hold the shift key and click in the center of the desired area The Zoom tool can also scale continuously by clicking the right button and dragging up and down This mode can also be invoked with the Toggle Zoom command in menu Edit Modes Edit The most useful scale change command is Fill Window in menu Window which makes the current cell fill the window There are four special zooming commands in the Window Special Zoom menu e Focus on Highlighted makes the highlighted objects fill the display This is useful for examining a specific area of the display To examine a specific area of the display that is not necessarily aligned with nodes and arcs use the area select commands see Section 2 1 3 e Zoom Box allows you to drag out a rectangle and then zooms to that area e Make Grid Just Visible zooms in or out until the grid is minimally visible Any further zoom out from this point will make the grid invisible If the grid is not being displayed it is turned on See Section 4 7 1 for more on the grid e Match Other Window redraws the current window at the same scale as the other If there are more than two windows you will be asked to select the window to match Using the Electric VLSI Design System version 8 11 97 Chapter 4 Display 4 4 2 Panning Besides scaling you can also pan the window contents shifting it about on the display This is typ
34. a single color is used everywhere The other general controls at the top are discussed in Section 4 11 1 9 5 3 ALS Concepts The user should be aware that the ALS simulator translates the circuit into VHDL then compiles the VHDL into a netlist for simulation This means that when a layout or schematic is simulated two new views of that cell are created VHDL and net als Use the Edit VHDL View in menu View to see the VHDL code Netlist View Schematics View Using the Electric VLSI Design System version 8 11 285 Chapter 9 Tools When simulation is requested the cell in the current window is simulated Date checking is performed to determine whether VHDL translation or netlist compilation is necessary If you are currently editing a VHDL cell it will not be regenerated from layout even if the layout is more recent Similarly if you are currently editing a netlist cell it will not be regenerated from VHDL even if that VHDL is more recent Thus simulation of the currently edited cell is guaranteed Note that the presence of VHDL in the path to simulation means that it can simulate VHDL that is entered manually You can type this VHDL directly into the cell see Section 4 9 for more on text editing Also you can explicitly request that VHDL be produced from schematics or layout with the Make VHDL View command in menu View This complete VHDL capability combined with the Silicon Compiler which places and routes
35. and a horizontal routing arc to run between the cells in the routing channel It also uses power arcs to bring power and ground to the cell rows and main power arcs to connect the rails on the left and right The VHDL description is normally placed in the vhdl view of a cell see Section 4 9 for more on text editing There is a VHDL example in cell tool SiliconCompiler vhdl of the samples library To access it use the Load Sample Cells Library command in menu Help To convert a schematic or VHDL cell into layout use the Convert Current Cell to Layout command in menu Tools Silicon Compiler To compile VHDL to the net quisc view use the Compile VHDL to Netlist View command this is typically not needed since the previous command does it automatically When creating a schematic or VHDL cell to be compiled it is important to know what primitives are available in the standard cell library Electric comes with a CMOS cell library in the MOSIS CMOS mocmos technology This library is not correct and exists only to illustrate the Silicon Compiler These component declarations are available component and2 port al a2 in bit y out bit end component component and3 port al a2 a3 in bit y out bit end component component and4 port al a2 a3 a4 in bit y out bit end component component inverter port a in bit y out bit end component component nand2 port al a2 in bit y out bit end component
36. and there are ports on the left and right of each rail then the auto stitching router can be used to connect all of these rails in a horizontal string of these cell instances The auto stitcher places a wire when all of these conditions are met e The design is layout auto stitching does not work in schematics e Ports exist on both nodes Because wires must run between two ports you must make exports at every location where wiring may occur If Create exports where necessary is checked in the Routing Preferences in menu File Preferences Tools section Routing tab then it is not necessary to have ports at all connection sites the router will create them for you e The nodes inside of the cells the ones with the exports must touch or overlap thus creating an implicit connection When a pin node has an export it should be the same size as any wires connected 298 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools to it inside of the cell This is because a small pin which is deep inside of a wide arc will not make an implicit connection when the arc touches something e The ports must not already be connected to each other To run the auto stitcher use the Enable Auto Stitching command in menu Tools Routing The router will make all necessary connections and incrementally add wires as further changes are made to the circuit To stop stitching select the menu entry again to disable it To
37. be inserted as the contact scales Although serpentine MOS transistors are a special case they cannot be automatically identified but must be explicitly indicated with a textual indicator Besides this explicit indication the transistor node must contain four ports two on the gate layer polysilicon and two on the gated layer active A standard geometry must be used that shows polysilicon and diffusion crossing in a central transistor area Any deviation from this format may cause the technology editor to be unable to derive serpentine rules for the node Besides the standard nodes for transistors contacts and other circuit elements it is necessary to build pin and pure layer nodes There should be one pin for every arc so that the arc can connect to others of its type The pin should be constructed of pseudo layers i e it has no real geometry should have the pin function and should have one port in the center that connects to one arc The technology editor will issue a warning if there is no pin node associated with an arc The pure layer nodes should also be built one for each layer They should have only one piece of geometry and have the pure layer function The technology editor will issue a warning if there is no pure layer node associated with a layer Using the Electric VLSI Design System version 8 11 229 Chapter 8 Creating New Technologies 8 7 Miscellaneous Information The Support Cell Each cell
38. locked checked out to others E tool SimulateSPICE lay F tool SimulateVERILOG sch Tauca alpa ee MANY tool SimulateVerilog4nd of the project management T tool SimulateVerilogAnd sch commands by selecting Ki tool SimulateVerilagAnd ic cells in the explorer and tool NCC using context menu E tool NCC sch c mmands i T tool NCCi lay iH spiceparts Using the Electric VLSI Design System version 8 11 179 Chapter 6 Advanced Editing To update your library so that it contains the most recent version of every cell use the Update command This will retrieve the newest version of every cell in every library that is being managed You will be given a list of cells that were replaced Advanced Commands If after a cell has been checked out you change your mind and do not wish to make changes use the Rollback and Release Check Out command or use the Rollback and Release Check Out context menu when clicking on a cell name in the cell explorer This will destroy any changes made to the cell since it was checked out and revert the cell to its state when it was checked in If in the course of design a new cell is created it must be added to the repository so that others can share it Use the Add This Cell command to include the cell in the repository Similarly if a cell is to be deleted use the Remove This Cell command to delete it from the repository To examine the history of changes to a cell use the Show His
39. probe from the schematic and Electric will automatically translate the schematic net to the appropriate layout net contained in the waveform file These commands control NCC and analyze its results e Copy Schematic User Names to Layout and Copy All Schematic Names to Layout For each pair of matching schematic and layout cells rename networks and nodes in the layout cell to have the same name as the equivalent networks in the schematic cell The first command copies only user assigned names from the schematic to the layout the second command copies all names Furthermore it only changes the names of layout networks and nodes that have no user assigned names If a layout network or node has a user assigned name that does not match the schematic then this command prints a warning This command also warns when non equivalent networks or nodes have the same user assigned name Notes These commands use the result generated by the most recent run of NCC That NCC run should be hierarchical without size checking These commands clear the saved result from the last run of NCC If you need to run a command that needs the last result for example Highlight Equivalent then you must rerun NCC e Highlight Equivalent Highlight the network or node that is equivalent to the currently selected network or node using the result of the most recent NCC run The user should be aware of a number of limitations 1 2 This command w
40. the value of the signal specified as the operand is used in the mathematical calculations The strength declaration is optional and if it is omitted a default strength of 2 gate is assigned to the output signal Using the Electric VLSI Design System version 8 11 289 Chapter 9 Tools The t Statement Time Delay The propagation delay time switching speed of a gate can be set with the t statement The format of this statement is shown below Format t lt mode gt value lt mode gt value Mode delta fixed time delay in seconds linear random time delay with uniform distribution random probability function with values between 0 and 1 0 Example t delta 5 0e 9 t delta 1 0e 9 random 0 2 It is possible to combine multiple timing distributions by using the operator between timing mode declarations The timing values quoted in the statement should represent the situation where the gate is driving a single unit load e g a minimum size inverter input The t statement sets the timing parameters for each row in the truth table i and o statement pair that follows in the gate description It is possible to set different rise and fall times for a gate by using more than one t statement in the gate description Assuming that a 2 input NAND gate had timing characteristics of t lh 1 0 nanoseconds and t hl 3 0 nanoseconds the gate description for the device would be as follows gate nand2 inl in2 outp
41. to be generated Check the desired sizes and they will be generated Each generated array cell will contain the specified size array and it will be internally wired Using the Electric VLSI Design System version 8 11 Chapter 9 Tools e Stitch Based Fill Generator Similar to the previous fill generator this stitch based fill also creates cells or tiles to meet metal density conditions but it is a more generic tool for signal distribution Unlike the previous tool it allows you to generate fill cells that drive any signal not just power and ground The fill takes a set of metal arcs stored in cells and stitches them together based on the export names The metal arcs can all be located in the same cell or distributed in different cells If the arcs are in different cells the tool will flatten all cells into one with all the signals Networks are matched by name up to the first _ character For example arcs in the networks Vdd_1 and Vdd_2 will be stitched together The tool also allows you to stitch cell instances without flattening them it will use the cell exports for the stitching process instead This is the typical case for cells containing cap transistors There are two ways to run the tool 1 by using a documentation cell containing the fill instructions and issuing the Stitch Based Fill Generator from doc input command and 2 by opening all the relevant cells in different windows and using the Stitch Based Fill Generator
42. two materials cross even though the materials extend on MQ gt all four sides Also CMOS active arcs have implants that SSS surround them but the highlight covers only the central Xs MQ active part ME i Sihn LLL4 AAVOH HA AN Besides the basic box there will be other things drawn when an object is highlighted Highlighted arcs have their constraint characteristics displayed The example above shows an arc that is both fixed angle F and slidable S The letter R is used for rigid arcs and an X appears when none of these constraints apply See Section 5 1 for more information on arc constraints When nodes are selected a port is also highlighted The port that is highlighted is the one closest to the cursor when the node is selected If the port is a single point you see a at the port If the port is larger than a single point it is shown as a line or rectangle ns a PEPA ff f DI PF yyy RX nnys 4A Highlighted Pin TLL nyyssit WN ee RA Ss Highlighted nodes will also show the entire network that RRA EN N A extends out of the highlighted port Arcs in that network will be drawn with dashed lines and nodes in that network will be indicated with dots The example here shows the highlighting of a pin node in the upper right with a single point port which is connected to a contact and a transistor tpg Sf fy ti pf Yi Fa f FA Vf LS too Highlighted Port
43. wire ends are square and extend by half of their width Using the Electric VLSI Design System version 8 11 191 Chapter 7 Technologies 7 3 3 GDS Control GDS Layer Map Association xi GDS II also called Stream format is used as an interchange Mapping these layer names to the mocmos technology between design systems and fabrication facilities For Metal 1 information on reading and writing GDS see Section 3 9 2 M2 meta 2 and Section 3 9 3 respectively In GDS files there are no ae meas names for each layer just a pair of numbers the layer number and type It is important that Electric know how these values ni Metals H correspond with layers so that it can properly read and write MS Metal s ied H GDS files You can set the correspondences by using the GDS M Metal 6 z Map File command in menu File Import to read a GDS M7 lt lt IGNoRE gt gt xj map file You can also use the GDS Preferences in menu File Preferences I O section GDS tab to edit the GDS numbers and control other aspects of GDS input and output GDS PROJECT Preference _ Categories GDS USER Preferences General Technology mocmos x Layer Type Display Foundry mosis Normal fas fo YO Import CIF EREE Pin fso fo Merge boxes slow Metal 2 51 82p 82t EDIF wore Metal 3 62 93p 93t Text 80 fo DEF Metal 4 31 63p 63t Clear these field to ignore the layer CDL J Expan
44. 0 0 khx 0 0 kly 0 0 khy 0 0 gt lt multicutbox gt lt nodeLayer gt e lt serpbox gt a box used in serpentine transistors A serpentine transistor consists of many segments of the transistor gate Each segment is described when viewed from one end of the segment to the other end Thus going to the left or right indicates how far from the centerline of the segment the geometry 248 Using the Electric VLSI Design System version 8 11 Chapter 8 Creating New Technologies extends Going top or bottom indicates how far past the end of the segment the geometry extends So in addition to the attributes found in the lt box gt element it has these additional attributes IWidth the distance from the centerline to the left edge rWidth the distance from the centerline to the right edge tExtent the extension beyond the top point of the centerline bExtent the extension beyond the bottom point of the centerline When there are multiple primitive nodes that are similar a lt primitiveNodeGroup gt can be used to define them A lt primitiveNodeGroup gt has lt primitiveNode gt subelements that define the variations among the primitives in the group Individual nodes in a lt primitiveNodeGroup gt can differ from each other only by name function some flags and their node layers Specifically 1 The lt name gt and lt fun gt attributes are moved from the lt primitiveNodeGroup gt element and appear in
45. 1 5 Easy and Hard Selection In a busy circuit many objects may overlap causing confusion when selecting To simplify selection objects can be marked so that they are no longer easy to select which means that standard selection does not work on them Special Selection To select hard to select objects use the Toggle Special Select command in menu b k Edit Modes Select You can also click on the Special Select tool bar button to Disabled Enabled enable special selection Once in this mode all objects are selectable Ease of selection extends to more than just nodes and arcs There are four classes of objects that can be selected e Basic objects all arcs primitive nodes and port names e Cell instances e Node and arc text names and other text placed on nodes and arcs e Instance names an unexpanded cell instance s name By default the first three classes are easy to select and instance names are hard to select If you uncheck Easy selection of cell instances in the Selection Preferences dialog then cell instances become hard to select Although all nodes and arcs are typically easy to select you can control them individually by unchecking the Easy to Select field in their properties dialog use the Object Properties command in menu Edit Properties If multiple objects are selected the Object Properties dialog has a popup on the right for changing their selection difficulty Specia
46. 10 107 Wires 95 Wires Parts 3 88 Ports 78 Ports Wires 21 mipscells zipper sch lay 19 mipscells datapath sch lay 27 Right clicking on a tree node or a table cell pops up a menu with an option to copy the node name or the cell text to the system clipboard see below mipscells bitslice sch lay 34 Exports 10 5i dd Parts 3 mip Mm mipscells mux4 mux4 0 in Cell Copy Node Title To Clipboard mipscells mux Copy Cell Text To Clipboard ef mipscells mux di Wires 21 320 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools 9 8 Generation 9 8 1 Pad Frame Generation The Pad Frame generator reads a disk file and places a ring of pads around your chip The pads are contained in a separate library and are copied into the current library to construct the pad frame The format of the pad frame disk file is as follows celllibrary LIBRARYFILE copy Identifies the file with the pads cell PADFRAMECELL Creates a cell to hold the pad frame views VIEWS A list of views to generate core CORECELL Places cell in center of pad frame align PADCELL INPUTPORT OUTPUTPORT Defines input and output ports on pads export PADCELL IOPORT COREPORT Defines exports on the pads place PADCELL GAP PORTASSOCIATION Places a pad into the pad frame rotate DIRECTION Turns the corner in
47. 3 Hierarchy 3 7 2 Cell Graphing Cell graphing shows the hierarchical structure of your circuit The graph is stored in a new cell called CellStructure built from Artwork nodes The Cell Graph Entire rinomina Library command in menu Edit Cell Info displays a graph of every cell in the library The Cell Graph From Current Cell command displays a graph that places the current cell at the top ringLeft lay ringRightBot lay ringLeftBot lay ringSegCapjlay tingRightTop lay A cell graph can be edited like anything else in Electric Click and drag the cell names to rearrange the graph Electric can also construct a aiid graph of library tingSegBus2 lay dependencies with the Library Graph command ringSegStop lay altCon2 lay ringSegStopDnjlay serviceBus lay join35 lay joint4 lay altConMijlay altCont lay ringSegStopUp lay strong lay join21jlay strong2 lay 74 Using the Electric VLSI Design System version 8 11 Chapter 3 Hierarchy 3 7 3 Cell Properties To examine and set more information about existing cells use the Cell Properties command in menu Cell The left side of the dialog lists cells by library On the right are the properties of the cells Every cell T Disallow modification of anything in this cell Set Clear I Disallow modification of instances in this cell Set Clear P Standard cell in a cell library Set Clear P Part of technology editor library
48. 8 aluoutreg d 8 1 t 8 1 alucontrol 0 3 vdd 1 12 Wire s in mipscells datapath sch alucontrol 2 in Cell mipscells da alucontrol 1 in Cell mipscells da alucontrol Q in Cell mipscells da regdstin Cell mipscells datapatr alusrca in Cell mipscells datapal iord in Cell mipscells datapath memtoreg in Cell mipscells data regwrite in Cell mipscells datapa pesource 1 in Cell mipscells dat alusrcb 1 in Cell mipscells datat pesource 0 in Cell mipscells dat alusrcb 0 in Cell mipscells datat 9 Wire s in mipscells datapath lay regdstin Cell mipscells datapa alusrca in Cell mipscells datap iord in Cell mipscells datapath memtoreg in Cell mipscells dat regwrite in Cell mipscells datar pesource 1 in Cell mipscells d alusrcb 1 in Cell mipscells dat pesource O in Cell mipscells d alusrcb 0 in Cell mipscells dat The tree node names contain the first mismatched wires from both lists For example in the above figure the first wire class has the node name 1 ftalwcont roel 2 5 which has the following meaning e 1 The sequence number of this class e falucontrol 2 The first mismatched wire in the first cell s list is called alucontrol 2 The ellipsis after the name suggest that there is more than one wire in the list e _ The name of the mismatched wire in the second cell s list nothing is found e 3 The number of mismatched wires
49. C ElLib ElCell ElView ElRot ElPortOff EdTech EdPrim EdFunc EdPortOff Where E1Lib is the Electric library name e g MyCells E1Cel11 is the cell name in that library e g Inverter E1View is the view name of the cell e g ic for Icon All other fields are the same as in the Primitive line e Exports A line starting with E controls how exports are converted to EDIF The line has this format ElTech ElPrim ElFunc ElRot ElPortOff EdTech EdPrim EdFunc EdPortOff Where ElTech is the Electric technology name e g schematic E1Primis the Electric primitive name e g Transistor E1Func is the Electric function e g CONNECT E1Rot is the Electric rotation e g 90 E1PortOf f is the Electric port offsets enclosed in braces e g g 1 0 The offsets are the values required to move the export to the origin so if an export is at 2 5 the offset should be 2 5 Each port on the primitive must be listed and an offset given EdTech is the EDIF technology name e g tsmc18 EdPrimis the EDIF primitive name e g pmos2v EdFunc is the EDIF function e g symbol EdPortOf f is the EDIF port offsets enclosed in braces e g G 0 0 The offsets are the values required to move the export to the origin so if an export is at 2 5 the offset should be 2 5 Each port on the primitive must be listed and an offset given For example E schematic Off Page CONNECT 0 in
50. DELIB format the cells are different color because each cell is its own file The colors and their associated state are shown below Colors at the top of the table will be displayed before colors at the bottom of the table if two states are simultaneously valid Using the Electric VLSI Design System version 8 11 181 Chapter 6 Advanced Editing onflicts with CVS version Red ssid Locally Modified Needs Update Up to date Black These are the commands implemented by Electric 182 e Commit Commit a locally modified version to CVS e Update Retrieves latest version from CVS repository e Get Status Check the status with respect to the CVS version e List Editors List other users who have a locally modified version of the file e Show Log Display a dialog of all versions of the file in CVS allows checkout of specific version e Rollback Revert to latest CVS version e Add to CVS Add the file to CVS requires a commit to actually add it e Remove from CVS Remove the file from CVS requires a commit to actually remove it e Undo CVS Add or Remove Undo a previous CVS add or remove before a commit is done e Rollforward Move local modified file to a temporary location get a fresh copy from CVS and put back the local copy This is to prevent merge cases with conflicts and still preserve local modifications Using the Electric VLSI Design System version 8 11 Chapter 6 Advanced Editing 6 14 Emergencies Electric us
51. Electric VLSI Design System version 8 11 Chapter 7 Technologies 7 6 Special Technologies 7 6 1 The Artwork Technology The Artwork technology is an unusual technology that provides general purpose sketching facilities To obtain this technology use the popup menu at the top of the component menu and select artwork Thicker Circle Spline This technology has nodes for many typical graphic objects such as rectangles triangles Crossed Box gt Arrow Head circles and arrowheads Polygonal and Spline nodes allow arbitrary shapes to be defined Of course nodes from all other technologies can be used as special electronic symbols when artwork is generated Conversely these artwork nodes can be used to embellish designs Filled Polygon Closed Polygon done in all other technologies General Pin Filled Circle Filled Box Circles can be outlines normal or thick or filled The default shape is round but Triangle elongation of the node produces an ellipse In addition by using the Object Properties Opened Dashed Polygon command in menu Edit Properties the outline circles can be reduced to a portion of the circle from 1 to 360 degrees Filled Triangle Opened Thicker Polygon Opened Polygon Opened Dotted Polygon Place Instance The Export entry creates an export for use in icons After clicking on the entry you have the choice of selecting Wire Bus or Solid Arc Dotted Arc Universa
52. Exports to bring exports to the surface level The Messages window confirms how many ports were exported The final and gate should resemble this 1 12 5 Schematics and Layout Tutorial Analysis Design Rule Checking At any time you can check your layout against the design rules by using the Check Hierarchically command in menu Tools DRC or just type the F5 key When DRC is done use the gt key to step through and highlight errors see the Messages window for comments You can also use this command to check a schematic Schematic design rules are simply rules of etiquette which report unusual situations in the circuit drawing See Section 9 2 1 for more on DRC Network Consistency Checking One of the most useful analysis tools is Network Consistency Checking NCC This compares the networks in two different cells to make sure they are equivalent this step is sometimes called LVS layout versus schematic To run NCC edit either the layout or the schematic cell and use the Schematic and Layout Views of Cell in Current Window command in menu Tools NCC This check will not consider transistor sizes only circuit connectivity 38 Using the Electric VLSI Design System version 8 11 Chapter 1 Introduction When the circuit has passed NCC at the connectivity level turn on transistor size checking To do this check Check transistor sizes in the NCC Preferences use the Preferences command in menu File secti
53. Model Files iell ZL sl Import Reset All Only resets USER Preferences Apply g Export if Reset Help Cancel gu DRC USER Preferences Incremental DRC M On M Show worst violation while moving nodes and arcs Hierarchical DRC Report Type Report just 1 error per cell Report just 1 error per pair of geometries Report all errors Report Errors By Cell P Multi threaded DRC Incremental and Hierarchical IV Save valid DRC dates with cells Clear valid DRC dates Ignore center cuts in large contacts Ignore area checking I Ignore extension rules P Interactive Logging Min4rea Algorithm Local F There are three levels of checking that can be requested for the Hierarchical DRC Each level of checking consumes more time and finds more errors 262 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools e Report just 1 error per cell tells the system to stop checking a cell after the first error has been found By using this option you can more quickly determine which cells in the design are correct without knowing exactly where the errors lie Then you can go to the cells with errors and do a more complete check e Report just 1 error per pair of geometries is the default The algorithm works by checking design rules per each possible pair of geometries and it stops
54. SPICE Resistance 0 06 SPICE Capacitance 0 04 SPICE Edge Capacitance 0 0 3D Height 24 65 ie irre 3D Thickness 2 65 Copy Pattern Coverage percent 0 0 Paste Pattern Because every layer has a default stipple pattern used for printing all that is necessary is to change the Style field from solid to patterned To do this double click on the Style text and select Patterned Outline None The technology is now modified and can be converted back with the Convert Library to Technology command 234 Using the Electric VLSI Design System version 8 11 Chapter 8 Creating New Technologies Example Creating a New Node The second example is more extensive creation of a new primitive node In this case the new node is a contact between metal 2 and polysilicon To create the node use the context menu on the TECHNOLOGY p Name of new node NODES tab of the explorer window select Create New Node gt Metal 2 Polysilican Con and name the node appropriately aa At this point the display will show only the textual information about the node because the graphical information is yet to be supplied The textual information consists of five factors that now fill the screen Function contact Serpentine transistor No Square node No You should begin by changing the Function factor to contact S double click it and select the appropriate function Then pan back so Invisible with 1 or 2 arcs No ther
55. The Rule Name fields let you describe the rule so that the design rule checker can report error names Chapter 8 Creating New Technologies Active Parameters LAm Distance Rule Name Width 4 fo Poly overhang B poo pooo Contact overhang ofo Spacing D fo Distances are in nanometers Technology Creation Wizard Technology Parameters General Active Gate Contact Well Implant Metal Via Antenna GDS C ee e 6 Al The Active panel lets you specify size and spacing values for the Active layer Note that all sizes are in nanometers For example if the Active Width A is set to 200 and the Unit size in the General panel is set to 100 then Active arcs will be 2 units wide The Rule Name fields let you describe the rule so that the design rule checker can report error names Polysilicon Parameters Distance Rule Name Width A poo Endcap B fo Active spacing fo o Spacing D oc Distances are in nanometers Load Parameters Write XML Save Parameters Using the Electric VLSI Design System version 8 11 253 Chapter 8 Creating New Technologies Technology Parameters Gate Parameters General Active Poly Contact Well Implant Metal Via Antenna GDS The Gate panel lets you specify size and spacing values for the Polysilicon layer in transistors The Rule Name fields let you describe the rule so that the design rul
56. The only four functions currently available are listed above There are two flip flops JK and D and two numeric converters that translate between a bus of 8 signals and a composite hexadecimal digit Declaring Input and Output Ports The i and o statements which follow the function declaration are used to tell the simulator which signals are responsible for driving the function and which drive other events If any signal in the event driving list changes state the function is called and the output values are recalculated The format of an i statement which contains a list of event driving inputs is shown below Format i signall signal2 signal3 signalN Example i b7 b6 b5 b4 b3 b2 b1 bO i input phi phi_bar set reset The format of an o statement which contains a list of output ports is shown below Format o signall signal2 signal3 signalN Example o out out2 out3 o q q_bar 294 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools Other Specifications Just as there are special statements that affect the operating characteristics of a gate entity so are these statements available to direct the function entity The t statement is used to set the time delay between input and output changes The load statement is used to set the relative loading capacitance for the input and output ports The priority statement is used to establish the scheduling priority The set statement is used to initialize
57. a import com sun electric database variable EvalJavaBsh transistor in it and displays the cell import com sun electric technology PrimitiveNode import com sun electric technology Technology import java awt geom Point2D Cell newCell Cell makeInstance Library getCurrent sampl lay Technology tech Technology findTechnology mocmos PrimitiveNode trP tech findNodeProto P Transistor NodeInst tP NodeInst makeInstance trP new Point2D Double 10 10 trP getDefWidth trP getDefHeight newCell EvalJavaBsh displayCell newCell import com sun electric database hierarchy Cell This example goes a import com sun electric database geometry Orientation bit further it creates import com sun electric database topology ArcInst import com sun electric database topology NodeInst import com sun electric technology ArcProto a rotated transistor and a contact wires import com sun electric technology PrimitiveNode them together and import com sun electric technology Technology exports the contact import java awt geom Point2D The transistor is named T1 create the new cell Cell newCell Cell makeInstance Library getCurrent samp2 lay Technology tech Technology findTechnology mocmos place a rotated transistor PrimitiveNode trP tech findNodeProto P Transistor NodeInst tP NodeInst makeInstance trP new Point2D Double 0 20 trP getDefWidt
58. a e Aa a eT na ath de elt 348 LOMA Miscellanous riyen oee a a n a a n ea a a aa 353 Using the Electric VLSI Design System version 8 11 jii Using the Electric VLSI Design System version 8 11 Chapter 1 Introduction 1 1 Welcome Now you have it A state of the art computer aided design system for VLSI circuit design Electric designs MOS and bipolar integrated circuits printed circuit boards or any type of circuit you choose It has many editing styles including layout schematics artwork and architectural specifications A large set of tools is available including design rule checkers simulators routers layout generators and more Electric interfaces to most popular CAD specifications including EDIF LEF DEF VHDL CIF and GDS The most valuable aspect of Electric is its layout constraint system which enables top down design by enforcing consistency of connections This manual explains the concepts and commands necessary to use Electric It begins with essential features and builds on them to explain all aspects of the system As with any computer system manual the reader is encouraged to have a machine handy and to try out each operation Using the Electric VLSI Design System version 8 11 Chapter 1 Introduction 1 2 About Electric The About Electric command in menu Help shows you the names of the Electric development team It also outlines your legal rights with respect to Electric
59. a e aAa aeaa a a aei a 188 T 3 lO Specilications is aea e iis a r e a E E th ei aaa EEEE E EAS 190 7 4 The MOS Te chnologies rs sesamin cea tele e A E Eee a aE TEASE 201 ASESCMEMALCS eset seks dnt ces E E E OE E IEE E E E E E O E E 204 7 6 Sp cial Technologies seriinin Eee eaei A E AAEE E AE E E ees 209 Chapter 8 Creating New Technologies ssssscsssscsssssssssssssssssssssssssssccsssssssnsssssssssessscssssssessssssssssssssess 217 SSL Pechnology Paitin ii esesten acieuna teien aea a NEEE EEEa E EEE EE EE RESTE 217 8 2 Converting between Technologies and Libraries eee eeeceseeeeeeseeceeceeceseceseeeseeeaeesaaeeaeens 218 8 3 Hierarchies of Technology Libraries ee eecceseescessseceeceseceeeceseeeaeecsaeceeceseeseeeeeseaeesaaesaeen 220 8 4 The Layer Cellino nnne seia aiee een UA oh ieee 221 OH WMS Are CONS cee ce eee he tesee Lect la ea ectetiatete sates dan r o ee NE a EE 224 8 0 The Node Cells orres paa cunth co eE TEE e ATEA E EEE E E E bn E E EE 226 8 7 Miscellaneous Information eneen o ree a EE E n Ee E TEE EEEN EE t 230 Using the Electric VLSI Design System version 8 11 Table of Contents Chapter 8 Creating New Technologies 8 8 How Technology Changes Affect Existing Libraries cee eeeeceesecncecneceeeceeeeeeeeeneeeaaeeneens 232 9 Examples of Usean norton meea e east a ele cose is abe Pee cece te oe ete vaults E bade eke 234 8 10 Technology XML File Format esner ana eE EEE E E A eg as 237 8 11
60. a list of primitive arcs from this technology which can connect to this port Example lt primitivePort name metal l metal 2 gt lt portAngle primary 0 range 180 gt lt portTopology gt 0 lt portTopology gt lt box gt lt lambdaBox klx 1 0 khx 1 0 kly 1 0 khy 1 0 gt lt box gt lt portArc gt Metal 1 lt portArc gt lt portArc gt Metal 2 lt portArc gt lt primitivePort gt lt serpTrans gt marks this node as serpentine transistor It supplies 6 special values lt polygonal gt marks that this node can be an arbitrary polygon Usually is not used in layout technologies lt minSizeRule gt overrides the FullRectangle of the node and supplies the name of a minimal size rule The attributes width and height describe the size of the FullRectangle The attribute rule is the name of minimal size rule By default the FullRectangle is calculated as the minimum bounding box of all points found in the NodeLayers of a standard primitive node For the Metal 1 Metal 2 Con node example shown below the FullRectangle is calculated as a box with endpoints x 2 0 y 2 0 and x 2 0 y 2 0 The FullBox of a node instance with n extendX and n extendY is x FullRectangle minX n extendX y FullRectangle minY n extendY and x FullRectangle maxX n extendX y FullRectangle maxY n extendY This may be not accurate if shapes which made the minimum bounding box of the standard size node grows more
61. add the Bean Shell to the build which can be done by changing to the trunk directory and running the make command Next start Netbeans and open the electric netbeans project that is in the trunk folder You should be able to build the man project under the Run menu and then run or debug the main project Using Ant Ant is a scripting system for building Java programs and Electric comes with an Ant script file called build xml Once the source code is extracted you can build Electric simply by typing Ant commands The Ant target runFromBin will build and run Electric The Ant target jarForGNUBinary will build a new jar file from the source code Note that when using Ant there are some Macintosh vs non Macintosh issues to consider e Build on a Macintosh The easiest thing to do is to remove references to AppleJavaExtensions jar from the Ant script This package is a collection of stubs to replace Macintosh functions that are unavailable elsewhere You can also build a native App by running the Ant target mac app Macintosh computers must be running OS 10 3 or later e Build on non Macintosh If you are building Electric on and for a non Macintosh platform remove references to AppleJavaExtensions jar from the Ant script Also remove the module com sun electric MacOS XInterface java It is sufficient to delete this module because Electric automatically detects its presence and is able to run without
62. and the wire no longer stretches when nodes move Find another arc and issue the Not Fixed angle command Now observe the effects of an unconstrained arc as its neighboring nodes move These arc constraints can be reversed with the Rigid and Fixed angle commands See Section 5 2 1 for more on these constraints Using the Electric VLSI Design System version 8 11 19 Chapter 1 Introduction 1 10 6 IC Layout Tutorial Adding Contacts to a Transistor One very common structure in IC layout is the transistor contact combination Here you will see the proper way to construct it XX e Start with a transistor in this example on the left an n transistor e Rotate the transistor so that the gate is vertical To do this use the 90 Degree Counterclockwise command in menu Edit Rotate or just type Control J e Note that the active gate on the left is highlighted it is just a line N Although the default transistor is 2x3 in size most people want them to be wider For the purposes of this example make the transistor be 12 wide To do this select the node and use the Object Properties command in menu Edit Properties X Node Properties _X Two easier ways to see Type N Transistor the objects properties see jmos 0 are to double click on the node or select it Width fiz x position 28 and type Control I et Gezim i When the node Properties dialog Rotation foo P Mirror L R J Mirror U D appears m
63. are disconnected The designer promised that all exports in all lists would be connected 318 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools Exports rectifier lay vdd vdd_2 vdd_1 rectifier lay gnd_2 gnd_1 gnd scan3 lay vdd_2 vdd_1 dd_3 vdd scan3 lay gnd_3 gnd gnd_1 All exports are individually highlightable For example if the designer clicks on the vdd export then NCC will open up a window for cell rectifier lay and highlight the net connected to the export vdd Tip If it the design includes multiple instances of cell rectifier lay then the designer can find out which particular instance failed to keep the promise by typing control U which will pop up a level in the hierarchy Export Global Network and Characteristics Conflicts In an export global network conflict a cell has both an export and a global signal with the same name but their networks are topologically different see below Both the global network export and the cell export are highlightable Mismatched Comparisons 1 Conflicting Name Global Network Export Network A mipscells dpor2 sch lay 2 ae me port Global Network Conflicts 1 dpor2 sch Export Global Characteristics Conflicts 1 In an export global characteristics conflict one cell also has both an export and a global signal with the same name but their characteristic
64. at the right end of the cell names in this example 34 is the number of mismatches In general if you see a tree node with a number in square brackets then this number is the total number of mismatches grouped under this node Selecting a top level tree node displays the number of parts wires and ports in the compared cells in the right part of the window For all other nodes the right side of the window displays a list of component names arranged in different ways as described in subsequent sections Some components are highlightable in which Using the Electric VLSI Design System version 8 11 311 Chapter 9 Tools case their names are printed as blue red or green hyperlinks A top level node has one or more subnodes Subnodes can have the following types Exports Parts Wires Parts hash code Wires hash code Sizes Export Assertions Export Global Network Conflicts Export Global Characteristics Conflicts and Unrecognized Parts For more information on the NCC graphical user interface see Kao Russell Ivan Minevskiy and Jon Lexau Design Notes for Electric s Network Consistency Check Sun Microsystems Laboratories Technical Report 2006 152 January 2006 Exports The exports node is always a leaf node with the name Exports X where X is the number of export mismatches in this comparison Selecting an exports node displays a table on the right side of the NCC graphical window see below The table has
65. automatically increase the number of cuts when they grow larger see Section 7 4 1 Because of this very large contact nodes can create excessive work for the design rule checker as it examines each of the cuts To save time check the Ignore center cuts in large contacts check box which will examine only the cut layers around the edges of contact nodes DRC rules for new technologies might require special rules which can be time consuming To ignore these errors check Ignore area checking for minimum area rules and Ignore extension rules for special overlap rules After DRC is complete errors are available in the the cell explorer If you wish to see errors while DRC is running check Interactive logging and the errors will appear incrementally The final DRC control is how minimum area detection is done Setting MinArea Algorithm to Simple uses an algorithm that is slower Setting MinArea Algorithm to Local uses an algorithm that is faster but consumes more memory Using the Electric VLSI Design System version 8 11 263 Chapter 9 Tools 9 2 3 Design Rules Four types of errors are detected by the incremental and hierarchical design rule checkers Spacing errors are caused by geometry that is too close but not connected Notch errors are caused by geometry that is too close but connected Minimum size errors are caused by geometry that is too small Resolution errors are caused by geometries that are small
66. better control the process Note also that maze routing constructs an array which is the size of the route and searches the array for a routing path Therefore long wires will use large amounts of memory and time For an example of maze routing open the Samples library and edit the cell tool RoutingMaze you can read the library with the Load Sample Cells Library command in menu Help This cell has a number of unrouted wires that can be routed 9 6 5 River Routing River routing is the running of multiple parallel wires between two facing rows presumably two cell instances or two rows of instances The wires must remain in sequential order and cannot cross each other Thus they appear as a flowing stream of lines and have the appearance of a river Top lay SSS Bottom lay o 300 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools To specify an intended path for the river router every connection must be made with an Unrouted arc Thus before river routing there should be a series of direct and presumably nonmanhattan unrouted arcs These arcs are replaced with the appropriate geometry during river routing To convert the unrouted wires into layout use the River Route command in menu Tools Routing If there are unrouted arcs selected these will be the only ones converted Otherwise all unrouted arcs in the cell will be converted If it is necessary nodes may be moved to
67. bitslice sch aluresultin Cell mipscells bitslice 0 Wire s in mipscells bitslice lay mipscells bitslice sch lay Wire Class 5 4 Wire s in mipscells bitslice sch alubiny in Cell mipscells bitslice srcisel in Cell mipscells bitslice wdsel in Cell mipscells bitslice adrsel in Cell mipscells bitslice 3 Wire s in mipscells bitslice lay srcisel in Cell mipscells bitslice wdsel in Cell mipscells bitslice adrsel in Cell mipscells bitslice i alubinvb in Cell mipscells bitslic adrselb in Cell mipscells bitslice wdselb in Cell mipscells bitslice src1selb in Cell mipscells bitslic Ej adrselb in Cell mipscells bitslice wdselb in Cell mipscells bitslice src1selb in Cell mipscells bitslic El Up to five equivalence classes can be selected simultaneously Selecting one or more subnodes of a class node is equivalent to selecting the class node itself This means that no class appears twice in the table on the right If some node of a type different from Parts Wires Parts hash code or Wires hash code is selected as well then it has a higher display priority and its contents are displayed instead For example if an exports node was selected with the three wire class nodes then the export table would be displayed on the right Sizes Both length and width mismatches in transistor and resistor sizes are collected under Sizes X node where X is the total number of size mismatche
68. buttons The Select All button selects every layer so that the Y Active Cut Make buttons will work on the entire set Metal 1 Vial z Note that the layers are listed in order of height and that you can select Select All multiple entries in the list by using the Shift key This means that you can Visible Invisible easily control visibility by depth in the chip If a different order of layers is visibility Configurations desired simply drag th dt them esired simply drag them around to rearrange them fa E x NI ara aye Set All visible a Visibility Configurations g M1 visible 3 Set M2 Visible xl As a convenient shortcut to layer visibility you can type SHIFT 1 y yy yP Highlighting double click on Set M1 Visible in the Visibility Configurations seciton or use the Set M1 Visible command in menu Window Visible Layers to Toe _cear_ make metal layer 1 be the only visible layer Type SHIFT 2 or use the Set Text Visibility M2 Visible command to make metal layers 2 and 1 be the only visible layers M Node Iv Arc In general using these commands makes the specified layer and the one M Cell Iv Port below it be the only visible layers To restore full visibility type SHIFT O or v raea use the Set All Visible command Veet IV Export Using the Electric VLSI Design System version 8 11 105 Chapter 4 Display You can also customize these commands so that an arbitrary combination of layers is visible To do thi
69. cell You can also search for objects by name the search field supports regular expressions C Arcs Networks To select everything in the cell use the Select All command in menu Edit Selection To deselect everything use Select Nothing inne contact 5 The Deselect All Arcs command deselects all selected arcs This is useful contact 6 when you wish to select a set of nodes but you have selected the entire contact 10 xl area including nodes and arcs search i Find Using the Electric VLSI Design System version 8 11 41 Chapter 2 Basic Editing To select everything in the cell that is the same as the currently selected objects use the Select All Like This command in menu Edit Selection For example if a Metal 1 arc is selected the command will select all Metal 1 arcs in the cell if a P Transistor is selected the command will select all P Transistor nodes in the cell if an export with the output characteristic is selected the command will select all output exports in the cell for more on export characteristics see Section 3 6 1 To loop through the objects similar to the selected one use Select Next Like This and Select Previous Like This 2 1 2 Selection Appearance Highlighted objects have a box drawn around them In some cases the object extends beyond the box but the box encloses the essential part of the object Highlighting For example MOS transistors are highlighted where the
70. compactor to expand the circuit if it is po Antenna Rules too close for the design rules LUE Coverage xl For an example of compaction open the Samples Export Import library and edit the cell tool Compaction you f 3 Reset Reset All Allow spreadin can read the library with the Load Sample Cells _Reset_ m p s Only resets USER Preferences Library command in menu Help iiy Help Apply Be warned that the compaction tool is experimental Cancel and doesn t always achieve optimal results __ cancel 338 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools 9 12 Silicon Compiler Electric has a silicon compiler called QUISC the Queen s University Interactive Silicon Compiler It is a powerful tool that can do placement and routing of standard cells from a schematic or a structural VHDL description The VHDL is compiled into a netlist which is then used to drive placement and routing Schematics are first converted into VHDL then compiled to a netlist and laid out Thus a byproduct of silicon compilation will be a net quisc view of a cell and potentially a vhdl view Be warned that the silicon compiler is rather old and so it produces layout that alternates standard cell rows and routing rows Modern silicon compilers use multiple metal processes to route over the standard cells but this system does not This system uses two layers a vertical routing arc to run in and out of cells
71. component nand3 port al a2 a3 in bit y out bit end component component nand4 port al a2 a3 a4 in bit y out bit end component component nor2 port al a2 in bit y out bit end component component nor3 port al a2 a3 in bit y out bit end component component nor4 port al a2 a3 a4 in bit y out bit end component component or2 port al a2 in bit y out bit end component component or3 port al a2 a3 in bit y out bit end component component or4 port al a2 a3 a4 in bit y out bit end component component rdff port d ck cb reset in bit q qb out bit end component component xor2 port al a2 in bit y out bit end component Using the Electric VLSI Design System version 8 11 339 Chapter 9 Tools The Silicon Compiler Preferences in menu File Preferences Tools section Silicon Compiler tab let you control many aspects of placement and routing ier Silicon Compiler USER Preferences i Antenna Rules Compaction Layout Well Coverage DRC Number of rows of cells fe P Well height 0 for none Fast Henry P Well offset From bottom Logical Effort Arcs NCC N Well height 0 For none Network Horizontal routing arc metal 1 m N Well offset from top Parasitic l ire width poo Placement Porzana pta via m Design Rules Routing a Vertical routing arc metal 1 7 Via size i Silicon Compiler Ept HER vertical wire width fa Moman me
72. create an image from layout Verilog Code nodes see Section 6 10 3 Verilog Declaration e Annular Ring brings up a dialog to create circular shapes see Verilog Parameter Section 6 10 3 Verilog External Code e Cell Center places a node that defines the origin of the cell see Simulation Probe Section 3 3 DRC Exclusion e Essential Bounds places a node that defines the corners of the AFG Exclusion cell s essential bounds see Section 7 6 3 Invisible Pin Universal Pin Unrouted Pin Spice Code places a text only node that will be inserted into Spice decks see Section 9 4 3 Spice Declaration places a text only node that will be inserted into Spice decks near the top see Section 9 4 3 Verilog Code places a text only node that will be inserted into the code area of Verilog decks see Section 9 4 2 Verilog Declaration places a text only node that will be inserted into the declaration area of Verilog decks see Section 9 4 2 Verilog Parameter places a text only node that will be inserted after the module header of this cell so that a parameter can be defined see Section 9 4 2 Verilog External Code places a text only node that will be inserted outside of any modules so that arbitrary external code can be inserted see Section 9 4 2 Simulation Probe places a node that can be used to display simulation results see Section 4 11 1 DRC Exclusion places a node that covers DRC error
73. creates a project setting on that technology object called ScaleFORmocmos which is a double precision value equal to 200 Using the Electric VLSI Design System version 8 11 347 Chapter 10 The JELIB and DELIB File Format 10 3 Body 10 3 1 Cells After the header information each cell is described A cell consists of a cell declaration C followed by a number of node N instance I arc A and export E lines The cell is terminated with a cell end line X Inside of a cell all nodes come first and are sorted by the node name arcs come next and are sorted by the arc name finally come exports sorted by the export name Also when there are multiple cells their appearance in the file is sorted by the cell name The syntax is C lt name gt lt group gt lt tech gt lt creation gt lt revision gt lt flags gt lt variable gt lt name gt fthe name of the cell in the form NAME VERSION VIEW the name of this cell s group if different than expected This field may be lt group gt Pacts omitted in earlier format libraries tech gt the technology of the cell The Java format for dates the creation and revision dates is in milliseconds since the epoch Midnight on January 1 1970 GMT The lt flags gt field consists of any of the following letters sorted alphabetically C if this cell is part of a cell library E if the cell should be created expanded
74. defines an 8 wide bus The indices can ascend or descend e Lists Bus names can be lists for example clock in1 out which aggregates 3 signals into a 3 wide bus e Array index lists and ranges Arrayed bus names can have lists of values separated by commas or ranges of values using the colon For example the bus b 0 c 3 5 d 1 2 e 8 6 is an 8 wide bus with signals in this order b 0 c 3 c 5 d 1 d 2 e 8 e 7 e 6 e Multidimensional array indices Arrays can be multiply indexed for example b 1 2 100 102 defines a bus with 4 entries b 1 100 b 1 102 b 2 100 and b 2 102 You can have any number of dimensions in an array Note that the order of signals in a multidimensional array is such that the rightmost index varies the fastest For example the bus D 1 2 1 2 has signals in this order D 1 1 D 1 2 D 2 1 D 2 2 e Symbolic array indices It is possible to use symbolic indices in bus naming for example the bus r x y defines a 2 wide bus with the signals r x and r y 164 Using the Electric VLSI Design System version 8 11 Chapter 6 Advanced Editing When a bus is unnamed the system determines its width from the ports that it connects Some tools such as simulation netlisters need to name everything and so use automatically generated names When this happens the system must choose whether to number the bus ascending or descending To resolve this issue use the Network Pref
75. e Plotting can be done with special commands in the Window Waveform Window submenu see Section 4 8 for more on printing 4 11 2 Analog Waveform Windows The waveform window is able to display analog simulation output This simulation output comes from external simulators such as Spice When the system is asked to display the results of an external simulation it reads the simulation output and shows it The analog waveform window looks like the picture below Note that there is a side bar with a cell explorer in the window just like in all windows but the explorer has a SIGNALS section that lists the signals found in the simulation and optionally a SWEEPS section if swept data was found When reading HSpice data the signals and sweeps sections may be further qualified by analysis for example TRANS SIGNALS DC SWEEPS etc Spice Output of toplevel sch fel E3 Components Explorer Layers E P1 Panel 1 v nf lt Main 1 2ns Center Ext 2 6ns Center Detta 1 4ns Sur Fasos mares oo o le e tan i vpulse1 niii 1 x g ng zg 3 U chop int int pulse vdd Y xnand21 net nets H xnms21 a a a ite H xsmart1 a H SWEEPS 0 1 INCLUDED 0 2 EXCLUDED 0 3 EXCLUDED 4 A JOBS ERRORS gt pulse Lan a a E 88 Using the Electric VLSI Design System version 8 11 129 Chapter 4 Display Wave Panels The waveform window contains a set of p
76. each click and drag of the left button leaves the highlight rectangle on the screen exactly as it was drawn You can convert this selection to a set of actual nodes and arcs with the Enclosed Objects command in menu Edit Selection Selecting Text Highlighted text appears as an X over the letters However text is a special case so it will not be covered until later Section 6 8 2 For now if you highlight some text it is best to click again and select something else Using the Electric VLSI Design System version 8 11 43 Chapter 2 Basic Editing 2 1 4 Controlling Selection Once a selection is made you can save it with the Push Selection command in menu Edit Selection The highlighting is not changed but it is saved on a stack To restore this selection at a later time use the Pop Selection command __ Categories Selection USER Preferences E General General There are some selection preferences Selection that can be set with Selection Key Bindings Preferences in menu File Nodes Preferences General section S amp amp iai Selection tab Project Management 3 oO CVS Printing IV Easy selection of cell instances Easy selection of cell instances Display I Dragging must enclose entire object controls whether instances can be 0 selected with simple clicks or whether I Tools they require extra effort to select see Technology V Enable Mouse over highlighting the next section for
77. endpoint T IV Play click sounds when arcs are created by half its width see Section Only resets USER Preferences 5 4 3 Help Apply IV Duplicate Array Paste increments arc names EER IV Draw arcs as wide as their connecting nodes Using the Electric VLSI Design System version 8 11 141 Chapter 5 Arcs The bottom portion of the dialog has controls for all arcs e Play click sounds when arcs are created plays a sound to confirm arc creation The sound is a single click for one arc a double click for two arcs and a triple click for three or more arcs e Duplicate Array Paste increments arc names sets whether the name on an arc should be kept unique by auto incrementing after this arc has been duplicated arrayed or pasted e Draw arcs as wide as their connecting nodes requests that arc widths expand when connected to wider than normal nodes see Section 2 2 3 142 Using the Electric VLSI Design System version 8 11 Chapter 6 Advanced Editing 6 1 Making Copies Once you have created a collection of objects it may be desirable to have other identical copies There are two ways to do this by duplication and by cut and paste Duplication The Duplicate command in menu Edit makes a copy of the selected nodes and arcs After issuing this command you can move the cursor to any location and click to place the copy While moving the cursor an outline of the duplicated objects is shown as w
78. exportsConnectedB yParent vdd vdd_ 0 9 When NCC compares a cell with an exportsConnectedByParent annotation it performs the comparison as if those exports were connected It is safe for NCC to believe this annotation because NCC also checks the assertion When NCC encounters an instance of a cell with an exportsConnectedByParent annotation it reports an error if that assertion isn t satisfied exportsTolgnore lt exportNames gt This annotation created with the Exports To Ignore command tells NCC to ignore certain exports in the cell At the next level up the equivalent ports on instance of the cell are also ignored so the network connected to that port does not see the port or the instance If the port is further exported up the hierarchy the new export needs to be ignored and another exportsToIgnore annotation is required The exportNames field can be a set of names or a regular expression surrounded by The annotation works only on the current cell not any associated cells in the same cell group For example suppose a layout cell has extra exports E1 and E2 which do not exist in the schematic This can happen when there are exports on dummy polysilicon In the layout cell add the annotation exportsTolgnore El E2 This will ignore the extra layout cells and it will also ignore the use of these exports Using the Electric VLSI Design System version 8 11 307 Chapter 9 Tools higher up the hierarchy skipNCC lt co
79. eye icon in the toolbar so that the individual nodes and arcs are available for editing use the Extract Cell Instance command in menu Cell Note that this command flattens makes a copy of the inverter cell inside of your NAND cell Study the inverter until you understand what each piece represents Start by drawing your nMOS transistors Recall that an nMOS transistor is formed when polysilicon crosses N diffusion N diffusion is represented in Electric as green diffusion surrounded by a dotted yellow N select layer all within a hashed brown P well background This set of layers is conveniently provided as a 3 terminal transistor node in Electric Move the mouse to the Components tab on the left side of the screen As you move the mouse over various nodes their name will appear in the status area at the bottom of the screen Click on the N Transistor and click again in the layout window to drop the transistor in place To Using the Electric VLSI Design System version 8 11 33 Chapter 1 Introduction rotate the transistor so that the red polysilicon gate is oriented vertically use the 90 Degrees Counterclockwise command in menu Edit Rotate or just type Ctrl J There are two nMOS transistors in series in a 2 input NAND gate so we would like to make each wider to compensate Double click on the transistor or type Ctrl I In the node properties dialog adjust the width to 12 We need two transistors i
80. format for comments the copyright text should not contain any such characters Instead the system will insert the proper comment characters for the particular export format ik gu Do not put comment characters in this message The copyright information will be inserted into decks exported for CIF LEF and PostScript as well as in simulation netlists for Verilog Spice Silos ESIM RSIM RNL COSMOS FastHenry Maxwell and IRSIM Using the Electric VLSI Design System version 8 11 83 Chapter 3 Hierarchy 3 9 4 Standard Cell Libraries Electric comes with few useful libraries for doing design see Section 3 9 1 However the system is able to make use of Artisan libraries These libraries are free provided that you sign an Artisan license Once you are licensed you will have standard cell libraries pad libraries memory libraries and more Artisan libraries are not distributed in Electric format Instead they come in a variety of formats that can be read into Electric The GDS files contain the necessary geometry and the LEF files contain the connectivity By combining them Electric creates a standard cell library that can be placed and routed and can be fabricated Note that the data is not node extracted so not all of Electric s capabilities can be used with this data To create an Artisan library follow these steps e Select the Artisan data that you want and extract the GDS and LEF files for it The GDS files
81. from open windows command When using a documentation cell to control the fill different combinations of fill cells can be generated at once It also has the advantage of being easy to re run when the fill operation must be iterated Each line in the documentation cell follows the syntax below fillCellName lt options gt celll lt option gt cell2 lt option gt cellN lt option gt exports layerName1 layerName2 Where option s can be W and or a sequence of title sizes e g 2x2 4x4 3x4 The option W allows the insertion of exports in the middle of the lowest metal arcs and different tile sizes can be arrayed depending on the area to cover By default all input cells are flattened unless option is I In that case the input cell will be instantiated instead of being flattened in the fill cell The exports line specifies that exports in the generated cells should use only the layers specified If this directive is not present exports are in the two top layers Using the Electric VLSI Design System version 8 11 327 Chapter 9 Tools Here is an example fillAB fillA 111B fillC W cap I fillA fi11B metals45 fillD 2x4 2x2 fillB metals45 metal6 si A FINA fiHB In the example above the first line takes the cells fillA and fillB and stitches the metal bars in fillAB Note that the signalB bars did not get stitched because the metal 2 bar does not overlap
82. have the same bus width e Number of existing arcs must match counts the number of arcs already connected to the other ports and ensures that they match e Node sizes must match applies to primitives and forces their sizes to be equal e Node types must match demands that the mimicked connections be on the same type of node e No other arcs in the same direction prevents arc creation when there are existing arcs wired in the same location as the proposed new arcs e Ignore if already connected elsewhere prevents arc creation in situations where the two ports are already electrically connected 9 6 4 Maze Routing The maze router replaces unrouted arcs with actual geometry To run it use the Maze Route command in menu Tools Routing If unrouted arcs are selected when the command is issued those connections are routed If nothing is selected the all unrouted arcs in the current cell are routed Note that the router is not able to handle routes that connect more than two points so collections of unrouted arcs that daisy chain to multiple locations must be routed one at a time Maze routing is done with a single arc and cannot change layers Therefore if the two ends of an unrouted arc are not able to connect to a common layout arc routing will fail Maze routing is done one wire at a time and may fail if no path can be found Therefore it may be preferable to route the unrouted wires one at a time in order to
83. hierarchy To enforce this consistency Electric stores an entire library in one disk file that is read or written at one time It is possible however to have multiple libraries in Electric Only one library is the current one and this sometimes affects commands that work at the library level When there are multiple libraries you can switch between them with the Change Current Library command in menu File or by using the library s context menu in the cell explorer see Section 4 5 2 To see which libraries are read in use the List Libraries command To create a new empty library use the New Library command in menu File To change the name of the current library use the Rename Library command To delete a library use the Close Library command This removes only the memory representation not the disk file It is possible to link two libraries by placing an instance of a cell from one library into another this is done with the Place Cell Instance command in menu Cell When this happens the library with the instance the main library is linked to the library with the actual cell this is the reference library Because the reference library is needed to complete the main library it will be read whenever the main library is read When there are many libraries used in the design of a circuit it may be the case that a consistent set of library files is read into Electric but that there are unused library files that have not bee
84. holds two components in a fixed configuration while the rest of the circuit stretches These constraints propagate through the circuit even across hierarchical levels of design so that very complex circuits can be intelligently manipulated A cell is a collection of these nodes and arcs forming a circuit description There can be different views of a cell such as the schematic layout icon etc Also each view of a cell can have different versions forming a history of design Multiple views and versions of a cell are organized into Cell groups For example a clock cell may consist of a schematic view and a layout view The schematic view may have two versions 1 older and 2 newer In such a situation the clock cell group contains 3 cells the layout view called clock lay the current schematic view called clock sch and the older schematic view called clock 1 sch Note that the semicolon and numeric version number 2 are omitted from the newest version Hierarchy is implemented by placing instances of one cell into another When this is done the cell that is placed is considered to be lower in the hierarchy and the cell where it is placed is higher Therefore the notion of going down the hierarchy implies moving into a cell instance and the notion of going up the Using the Electric VLSI Design System version 8 11 9 Chapter 1 Introduction hierarchy implies popping out to where the cell is placed Note that cell inst
85. improve chip power distribution and to avoid voltage drops by inserting cap transistors Electric has a coverage facility to evaluate the amount of fill see Section 9 2 4 This command generates fill cells Unlike other fill generators Electric s fill generator creates cells containing power and ground grids of specified layers usually starting at Metal 2 These cells can also be arrayed into tile cells to cover larger areas When Metal 1 is filled the generator will cover the area with cap transistors whose functionality is to prevent voltage drops in the power grid Fill Cell Generator for mocmos Floorplan Tiling Template Fill Fill Gell Master Cell Fill Information Width lambda 245 Type Fiat x Master CREATE z Height lambda 128 i Only 4raund Overlap Even layer orientation horiz x 7 Only Skill leval Lay Reserved Space Vdd Space Gnd Space Vdd Width Gnd Width Metal 1 6 0 lambda v 6 0 lambda 3 0 lambda v 3 0 lambda gt JV Metal 2 6 0 lambda x 6 0 lambda x 30 ambda z ao ambda z V Metal 3 6 0 lambda x 6 0 lambda 30 ambda z 30 ambda z E 30 E a I Metal 4 6 0 flambda Y 6 0 fiambda v lambda v CAL ambda v Metal 5 6 0 lambda Y 6 0 fiambda Y WE 0 ambda z 3 0 ambda v Metal 6 10 0 flambda 10 0 fiambda v 5 0 ambda z 0 ambda v The Fill dialog has two t
86. in a technology library describes a different aspect of the technology The support cell contains technology wide information To see this edit the cell factors under the TECHNOLOGY SUPPORT section of the cell explorer Scale 100 0 Description MOSIS CMOS 2 6 metals now 6 1 2 polys now 1 flex rules Now submicron Minimum Resistance 50 0 Minimum Capacitance 0 04 Gate Shrinkage 0 0 Gates Included in Resistance No Parasitics Includes Ground No Transparent Colors The support cell contains many items any of which can be changed by double clicking on it e Scale is the scaling factor between grid units and nanometers e Description is the full description of the technology e Minimum Resistance is the minimum resistance for the technology see Section 9 10 1 for this and other parasitics e Minimum Capacitance is the minimum capacitance for the technology e Gate Shrinkage is the gate shrinkage for the technology e Gates Included in Resistance tells whether to include a transistor s gate in resistance computations e Parasitics Includes Ground tells whether to include ground networks in parasitics computations Transparent Colors Change Transparent Colors ae Transparent layer 1 i fo 0 200 e Remove Double clicking on the j z Transparent Colors entry shows Transparent layer 2 a 220 0 120 Set Remove a dialog for selecting the transparent colors You must Transparent lay
87. in one of the two cells whichever is bigger In our example the schematic cell has 3 mismatched wires in this class and the layout has 0 mismatched wires in this class The maximum of 3 and 0 is 3 and therefore the tree node has 3 in its name Hash Code Partitioning If local partitioning fails to find a mismatch then NCC reports mismatches found by hash code partitioning under the nodes labeled Parts hash code and Wires hash code Unlike their local partitioning counterparts hash code partitioning classes do not have any characteristics Selecting Multiple Classes It is possible to select more than one class by holding the Control Command on Macintosh or the Shift key during selection In this case the right side will have multiple rows one row per class The figure below shows what is displayed when the three wire classes in the figure above are selected Up to five classes can be displayed at once Rows are arranged in the order in which the classes are selected 316 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools NCC Messages m Di xi mipscells bitslice sch lay Wire Class 4 Mismatched Comparisons 1 6 alubinvb 4 aluopb 1 s src2mux y aluop 1 gnd vdd zero a 1 E H E E mn 1 Wire s in mipscells
88. information e Layout technology to use for Schematics sets the technology to use for real geometry an integrated circuit technology not a schematics or artwork technology The default layout technology is used to give further information about schematics components see for example Section 9 4 3 e PSubstrate process in Layout Technology declares that the layout technologies are PWell and therefore the PWell spacing and minimum width rules should be ignored by the design rule checker Since Electric displays both wells users might be concerned with filling in notches in the PWell but in these processes it is not necessary The User Preferences section is discussed elsewhere For information about rotating transistors in the menus see Section 7 4 2 For information about Schematic primitive names see Section 7 5 1 and Section 3 11 2 Using the Electric VLSI Design System version 8 11 187 Chapter 7 Technologies 7 2 Scaling and Units 7 2 1 Scale Electric represents all distances in dimensionless units A transistor that is 2 x 3 in size is actually stored in memory as 2 x 3 To convert these units to real distances each technology has a scale measured in nanometers billionths of a meter The scale of a technology is shown in the status area after the technology s name For example if the scale for the MOSIS CMOS mocmos technology is 200 nanometers then a 2 x 3 transistor is actually 400 x 600
89. is used for holding text and it does not appear in hardcopy output this is what is created when you use place Annotation Text This pin can connect to any arc The Universal Pin is a node that can connect to any arc This is useful as an intermediate component when replacing first you replace the unwanted node with a Universal Pin to allow it to fit with the existing arcs then you replace the arcs finally you put the desired new node in place The Unrouted Pin is used when joining unrouted arcs It can also connect to anything 216 Using the Electric VLSI Design System version 8 11 Chapter 8 Creating New Technologies 8 1 Technology Editing Although there are many technology descriptions in Electric there are many more in the world To accommodate this there are three ways to define a technology in Electric e The Technology Editor allows you to modify existing technologies and create new ones The technology editor is describe here and in Sections 8 2 through 8 9 e The Technology Creation Wizard constructs technologies from simple process parameters The technology creation wizard is described in Section 8 11 e The Technology XML Files define technologies and can be created or hand edited The file format is described in Section 8 10 The technology editor works by converting a technology into a library of cells You then edit the cells using familiar Electric commands and make changes to the technology Finall
90. layout compensated well as its view and technology You can choose to show VHDL the cell in the current window or create a new one verilog documentation Cell names may not contain spaces tabs curly braces documentation waveform ha semicolons unprintable characters or a colon Technology mocmos x Cancel Make new window Another way to create a new cell is to make a copy of an existing one The Duplicate Current Cell and Duplicate Cell commands in menu Cell copy a cell to a different one with a new name you will be prompted for the new name The New Version of Current Cell command makes a copy of the cell in the current window but since it is a new version it has the same cell name The newly created cell is displayed in the window Once cells are created you can edit them with the Edit Cell command in menu Cell Cells can also be edited by using the cell explorer see Section 4 5 2 for more 60 Using the Electric VLSI Design System version 8 11 Chapter 3 Hierarchy Delete Cell Ed Library JpurpleF our l View schematic xl To delete a cell use the Delete Cell command in menu Cell When deleting a cell there cannot be any instances of this cell or the Filter deletion fails As a side effect of failure you are shown a list of all other cells that have instances of this so you can see the extent of its use To find out whether a cell is being used elsewhere in the hierarchy use
91. level block that is the FPGA An FPGA Architecture file must have the Primitive Definition section but it need not have the Block Definition or Architecture Sections This is because the placement of the primitives can be saved in an Electric library rather than the architecture file Thus after reading the Primitive Definition section which creates the primitives and reading the Block Definition and Architecture Sections which places the primitives to create a chip library the library can be saved to disk Subsequent design activity can proceed by reading only the Primitive Definition section and then reading the library with the chip definition This avoids large FPGA Architecture files the Primitive Definition section will be smaller than the Block Definition and Architecture sections Primitive Definition Section The Primitive Definition section defines the lowest level blocks which become primitive nodes in the FPGA technology A primitive definition looks like this primdef attributes name PRIMNAME size X Y ports port name PORTNAME position X Y direction input output bidir components pip name PIPNAME position X Y connectivity NET1 NET2 nets net name INTNAME segment FROMPART TOPART Using the Electric VLSI Design System version 8 11 211 Chapter 7 Technologies The attributes section defines general information about the block The ports section defines exte
92. level simulator called ALS that can simulate schematics IC layout or VHDL descriptions The simulator already knows about MOS transistors and some digital logic gates It can be augmented with functional descriptions of any circuit using the hardware description language described later in this section For an example of ALS simulation load the samples library and simulate the cell tool SimulateALS sch You can load the samples library with the Load Sample Cells Library command in menu Help To begin simulation of the circuit in the current window use the ALS Simulate This Cell command from menu Tools Simulation Built in After issuing this command a waveform window will appear to control the simulation see Section 4 11 1 for more Since the ALS engine is running inside of Electric you can place stimuli on the circuit and see the results immediately ALS is able to handle transistors with varying strength To set a transistor to be weak use the Weak command in menu Tools Simulation Verilog Transistor Strength To restore the strength to normal use the Normal command Note that this must be done before simulation begins Preferences The Simulators Preferences in menu File Preferences Tools section Simulators tab has some controls that affect ALS simulation The Multistate display check tells the simulator to show waveform signals with different colors to indicate different strengths Without this
93. library Tom These things may happen e If Copy subcells is checked then a new version of Tom B is created from Frank B and this cell is instantiated in the copied Tom A e If Copy subcells is not checked the instance in the new Tom A points to the old Frank B e If Copy subcells is not checked and Use existing subcells is checked the instance in the new Tom A points to the existing cell Tom B In order for this to work however the size and exports of Tom B must match the original in Frank B Therefore if Copy subcells is checked Use existing subcells is implied 86 Using the Electric VLSI Design System version 8 11 Chapter 3 Hierarchy 3 11 Views 3 11 1 Setting a Cell s View Each cell has a view which provides a description of its contents A view consists of a full name and an abbreviation to be used in cell naming For example the layout view is abbreviated lay and so the layout view of cell adder is called adder lay When no view name appears the cell has the unknown view Possible views are e layout for IC layout e schematic for logic designs e icon to describe a cell symbolically e layout skeleton a minimal view e documentation a text only view e VHDL or Verilog text only views for hardware description languages e a number of netlist views text only views that list connectivity for various tools such as netlisp n als
94. lt shortName gt a more descriptive name for the technology optional e lt description gt the most descriptive name for the technology e lt version gt describes Electric versions when Jelib changed and how it affects sizes The tech attribute contains an identifier of this version used in subsequent lt diskOffset gt subelements of lt arcProto gt and lt primitiveNode gt descriptions The electric attribute is a corresponding Electric version These elements are usually fixed in all technology files Examples lt version tech 1 electric 8 05g gt lt version tech 2 electric 8 050 gt e lt numMetals gt describes a possible range for the number of metall layers in the technology There is no good support for Xml technology files with a variable number of metal layers Therefore this 238 Using the Electric VLSI Design System version 8 11 Chapter 8 Creating New Technologies element should contains the same value for all three attributes Example lt numMetals min 6 max 6 default 6 gt e lt scale gt defines how many nanometers are in a display unit Electric uses dimensionless units in its interface where a transistor may be 2x3 without specifying actual distances This scale converts the units to real spacings The relevant attribute should be true for layout technologies Example lt scale value 200 0 relevant true gt e lt resolution gt defines the minimum resolution value in lambda u
95. make room for the river routed wires The river router always routes to the left or bottom side of the routing channel Thus if there is a vertical channel that is very wide the wires will run to the left side and then jog to their proper location there The only way to force routing to the right or top side is to rotate the entire circuit so that these sides are on the left and bottom For an example of river routing open the Samples library and edit the cell tool RoutingRiver you can read the library with the Load Sample Cells Library command in menu Help 9 6 6 Sea of Gates Routing The sea of gates router is able to take an arbitrary set of unrouted arcs and convert them to layout To do this use the Sea Of Gates Route command in menu Tools Routing If there are unrouted arcs selected these will be the only ones converted Otherwise all unrouted arcs in the cell will be converted The Sea of Gates router uses metal layers in the current technology You can disable the use of any layer or favor it above others to guide the routing To do this use the Routing Preferences in menu File Preferences Tools section Routing tab Another control found in the Routing Preferences sets the maximum width of a route segment By default each segment is made as wide as the widest arc already connected to that segment However in some situations very wide arcs exist and the connecting routes should not be t
96. menus on the top and lets you add or remove key bindings in the bottom area Arcs Cell Cross Library Copy Cell Merge Libraries You can remove a quick key binding with the Remove button and you can add a quick key binding with the Add button Change key bindings with caution because it customizes your user interface making it more difficult for other users to work at your computer You can get to EVERY menu command with key mnemonics The mnemonic keys are underlined in the menus For example the File menu has the F underlined and the Print command of that menu has the P underlined This means that you can hold the Alt key and type FP to issue the print command Note that the mnemonic keys are different than the quick keys 14 Using the Electric VLSI Design System version 8 11 Chapter 1 Introduction The default key bindings are shown here use the Show Key Bindings command in menu Help to see the current set For information about alternate key binding sets that mimic Cadence see Section 4 6 2 Plain Other Add Signal to Waveform Fa sela All see 2 1 1 Window 4211 1 Bis ize Interactively 2 5 1 be ged c Copy 6 1 Change 6 6 Down Hierarchy 3 5 Down Hierarchy In place 3 5 e E ii Di Place E Create Export 3 6 1 pH tal Unit Movement 24 1 1 Object Properties 2 4 J Rotate 90 Counterclockwise 2 6 K ShowNework 9 J ooo d O L Fimta d
97. metal and Metal 2 the source drain metal A capacitor is also available in the process and is formed between the gate electrode and a source drain electrode The cell tech TFTInverter lay in the sample library illustrates this technology 7 1 2 Controlling Technologies Electric has the concept of a current technology which is shown in the status bar This technology affects many things including the selection of nodes and arcs in the component menu There are a number of ways to affect the current technology both manual and automatic You can change the current technology by selecting it from the popup at the top of the side bar either the Components or Layers tab Electric automatically switches the current technology to match the cell being edited If there are multiple cells being edited from different technologies this switching can become annoying To disable automatic technology switching use the Nodes Preferences in menu File Preferences General section Nodes tab and uncheck Switch technology to match current cell 186 Using the Electric VLSI Design System version 8 11 Chapter 7 Technologies To see a list of primitive nodes and arcs in the current technology use the Describe this Technology command in menu Edit Technology Specific To see a detailed description of the current technology use the Document Current Technology command Some technologies have preferences that further customize
98. mismatches it cannot be fixed because someone else designed it When asked to continue NCC will do the following when comparing cells that use the mismatched one e If NCC found no export mismatches when comparing the mismatched cell then NCC will use the export names to identify corresponding ports in the layout and schematic e If NCC found export mismatches when comparing the mismatched cell then NCC will flatten that one level of hierarchy before performing the comparison If the check box Don t recheck cells that have passed in this Electric run is checked then NCC skips a cell if that cell passed NCC in a previous run and the designer hasn t since changed the cell Note that NCC only remembers when cells were last checked during a single run of Electric If you run NCC quit Electric restart Electric and rerun NCC all cells will be checked Reporting Progress Section This panel controls how verbose NCC is in reporting its progress Most users should leave this at 0 Error Reporting Section The error reporting section controls how many error messages are printed when the Local Partitioning algorithm has failed to find a mismatch but the Gemini algorithm has Most users will want to leave these at the default setting of 10 306 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools 9 7 4 Annotations For certain situations NCC cannot figure out that two cells are equivalent unless the designer supplies extra
99. names to layout net names after NCC completes and matches This allows one to probe networks in layout with the same name as in the schematics making it easier to compare schematic simulations against layout simulations e Extract Power Ground Always dimmed in the dialog this feature is not available e Extract R Extract C allow you to uncheck one of these to remove the R or C from RC parasitics computations e Use exemptedNets txt file looks for the file exemptedNets txt in your library directory This file specifies nets that are exempted from simple parasitic extraction There are two ways these nets are treated depending on subsequent setting if Extract all but exempted nets is selected all networks are extracted except the ones in the exempted nets file If Extract only exempted nets only the nets in the exempted nets file are extracted All nets connected to this net in subcircuits are also treated the same way Exempted Nets file format One line per network A network is specified by a library name cell name and net name When nets are not extracted a lumped capacitance value may be specified to use on the network This last argument is optional 0 if not specified and ignored when the exempted nets are the only nets extracted libraryName cellName netName replacementCapValue Example myLib myCell lay net 0 myLib myCell lay in_a 9 10 2 Node Extraction Because Electric capture
100. no number For example the ports gnd_7 gnd_9 and gnd_10 will be Select All Exports Show Selected Exports renamed gnd gnd_1 and gnd_2 Deselect All Exports Renumber Selected Numeric Export Names Using the Electric VLSI Design System version 8 11 71 Chapter 3 Hierarchy 3 7 Cell Information 3 7 1 Cell Lists g Cell Lists Ed Which cells All cells To get some basic information about the current cell size dates Only those used elsewhere etc use the Describe this Cell command in menu Cell Cell Info Only those not used elsewhere To get information about more than one cell use the General Cell z Lists command The dialog selects a subset of the cells in the Only placeholder cells current library View filter The section labeled Which cells selects the cells to be listed all V Show only this view only those used in other cells only those NOT used in the current schematic cell only those in the current cell or only placeholder cells those created because of cross library dependency failures see Section Also include icon views 3 9 1 Version fitter The section labeled View filter allows only certain views to be Exclude older versions displayed Exclude newest versions ii i Display ordering The section labeled Version filter allows removal of older or newer versions of cells Order by name V Evaluate Numbers when Sorting Names
101. of the use of a model entity gate xgate in ctl out delta 8 0e 9 delta 8 0e 9 ctl L o out X 0 ctl H in L o out L ctl H in H o out H o out X 2 model latch input en en_bar out gatel xgate input en mix gate2 xgate out en_bar mix gate3 inverter mix out_bar gate4 inverter out_bar out gate inverter in out t delta 5 0e 9 i in L o out H i in H o out L i o out X 2 H H Be H ct oct This example contains the description of a simple latch When the enable signal is asserted high en H en_bar L the input data passes through the transmission gate gate1 and then through two inverters where it eventually reaches the output When enable is asserted low en L en_bar H the input connection is broken and the feedback transmission gate gate2 is turned on The Set Statement The set statement is used to initialize signals within the model description to specific logic states before the simulation run takes place This feature is useful for tying unused inputs to power H or ground L 296 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools 9 6 Routing 9 6 1 Introduction The routing tool contains a number of different subsystems for creating wires Two stitching routers can be used in array based design to connect adjoining cells A maze router runs individual wires A river router is available for running multiple parallel wires Finally the sea of gates router han
102. on the mimic stitcher use the Enable Mimic Stitching command in menu Tools Routing To disable the stitcher use the command to uncheck it You can also request that the mimic stitcher run just once mimicking the very last wire that was created or deleted by using the Mimic Stitch Now command Finally you can request that the mimic stitcher run just once mimicking the currently selected arc by using the Mimic Selected command A set of restrictions applies to the mimic stitcher These restrictions prevent mimicking from happening Use Routing Preferences in menu File Preferences Tools section Routing tab to control these exact conditions in which arc creation and deletion will be mimicked When Interactive mimicking is checked the mimic stitcher will ignore the restrictions and present all possible mimic situations for your approval These situations will be organized by the restrictions that apply to them in order of increasingly relaxed acceptance criteria The Keep Pins checkbox requests that deleted arcs keep their pins typically pins at the ends of deleted arcs are also deleted When running noninteractively these are the restrictions that may be applied Using the Electric VLSI Design System version 8 11 299 Chapter 9 Tools e Ports must match indicates that the specific ports at the end of the arcs must be the same e Bus ports must have same width applies to schematics the ports must
103. one panel to another by dragging their names to their desired panel If you use shift click to drag signals they are copied to the new panel You can add signals to the list by double clicking on their name in the SIGNALS area or by dragging those names to the waveform part on the right The signals will be added to the highlighted panel the one with the bold vertical axis You can create a new panel with no signals in it by clicking on the button in the upper left of the waveform window or by using the Create New Waveform Panel command If the layout or schematics cell that produced the simulation is being displayed in another window and the currently selected network in that window is found in the simulation output then that output can be added to the waveform window with the Add to Waveform in New Panel command in menu Edit Selection The command Add to Waveform in Current Panel overlays the signal on top of others in the currently selected waveform panel The order of signals in the waveform window is saved in the original cell so that subsequent simulations will show the same signals You can also save the configuration of the waveform window with the Save Waveform Window Configuration to Disk command in menu Window Waveform Window and you can restore the configuration with the Restore Waveform Window Configuration from Disk command 130 Using the Electric VLSI Design System version 8 11 Chapter 4 Display Th
104. pad placement The file must have exactly one celllibrary and cell statement as they identify the pad library and the pad frame cell If the celllibrary line ends with the keyword copy then cells from that library are copied into the library with the pad ring by default they are merely instantiated creating a cross library reference to the pads library If there is a views statement it identifies a list of views to generate such as sch or lay Requesting multiple views will produce multiple pad frame cells The file may have only one core statement to place your top level circuit inside of the pad frame If there is no core statement then pads are placed without any circuit in the middle The align statement is used to identify connection points on the pads that will be used for placement Each pad should have an input and an output port that define the edges of the pad These ports are typically the on the power or ground rails that run through the pad When placing pads the output port of one pad is aligned with the input port of the next pad Each pad that is placed with a place statement is aligned with the previous pad according to the alignment factor A gap can be given in the placement that spreads the two pads by the specified distance For example the statement place padIn gap 100 requests that pad padIn be placed so that its input port is 100 units from the previous pad s output port If a core cell has been giv
105. points so it is easy to get precise 9 11e 3 measurements 40e 3 gt amp 1 06ns The time axis of the simulation window can be controlled with the appropriate Window menu commands Use Zoom Out and Zoom In to scale the time axis by a factor of two Use Focus on Highlighted in menu Window Special Zoom to display the range between the main and extension cursors m Besides controlling time with menu commands you can also use the Pan and Zoom tools of the Q a l toolbar The pan tool lets you smoothly shift time when you click and drag In the zoom tool you zoom into an area by clicking and dragging out that area To zoom out shift click in the center of the desired area You can also adjust time by clicking and dragging in the time axis at the top Using the Electric VLSI Design System version 8 11 131 Chapter 4 Display Set Window Extents xi Vertical axis Horizontal axis time You can control the horizontal and vertical range precisely low _ 8 333896 12 bo by double clicking in the vertical scale area The dialog lets you type exact values into the ranges High 0 0960086 1 0000E 8 coal Both the horizontal and vertical axis are drawn linearly Either axis can be changed to a logarithmic scale by right clicking on the ruler and choosing Logarithmic use Linear to restore the scale The different panels in the waveform window are locked in time they all show the same range of time as shown at the t
106. quisc rsim and silos e unknown no specified view i Choose alternate view xi When creating a cell with the New Cell command you can specify its view After creation you can change the current cell s 2 New view for this cell view with the Change Cell s View command in menu View schematic You can also use context menus in the cell explorer to change a cell s view ra 3 11 2 Switching between Views of a Cell When editing one view of a cell there are commands in the View menu that will switch to an alternate view of the same cell e Use Edit Layout View to switch to the layout view e Use Edit Schematic View to switch to the schematic view e Use Edit Icon View to switch to the Icon view e Use Edit VHDL View to switch to the VHDL view e Use Edit Documentation View to switch to the text only documentation view e Use Edit Skeleton View to switch to the Skeleton view For all other view types use Edit Other View and select the desired view Note that these commands are equivalent to the Edit Cell command in menu Cell with an appropriate selection Using the Electric VLSI Design System version 8 11 87 Chapter 3 Hierarchy When editing cells with text only views VHDL Documentation etc the window becomes a text editor You may then use the Text Cell Contents commands in menu File Export and File Import to save and restore this text to disk See Section 4 9 for more on text e
107. recommended style is to define NodeLayers of a transistor in electrical style and to omit electrical attribute in NodeLayers Using the Electric VLSI Design System version 8 11 247 Chapter 8 Creating New Technologies Example lt nodeLayer layer Metal 2 style FILLED gt Inside of the lt nodeLayer gt element are these subelements e lt box gt defines a rectangular shape It has attributes klx khx kly and khy If these attributes are omitted their default values are klx 1 khx 1 kly 1 khy 1 There is also a subelement lt lambdaBox gt which has attributes klx khx kly and khy Attributes of a lt lambdaBox gt describe the shape of the NodeLayer on a standard size node Attributes of a lt box gt describe how this shape grows when the node instance is larger than standard More formally let n extendX and n extendY be the internal values associated with the node instance in the Electric database The shape of the lt nodeLayer gt with lt box gt shape is a rectangle with endPoints x lambdaBox klx n extendX box klx y lambdaBox kly n extendY box kly and x lambdaBox khx n extendX box khx y lambdaBox khy n extendY box khy For example the shape of the Metal 2 NodeLayer below is a rectangle with endPoints x 2 n extendX y 2 n extendY and x 2 n extendX y 2 n extendY Example lt nodeLayer layer Metal 2 style FILLED gt lt b
108. signals to specific logic states before the simulation run takes place The format of these statement is identical to that of the gate entity Note that the Java method does not have to use the values specified in these statements and can schedule events with values that are specified directly inside the code Example of Function Use The specification for a 3 bit shift register edge triggered is shown below This circuit uses a function primitive to model the operation of a D flip flop model main input ck q2 ql q0 stage0 DFFLOP input ck q0 stagel DFFLOP q0 ck q1 stage2 DFFLOP q1 ck q2 function DFFLOP data_in clock output s Clock Oo output t delta 10e 9 load clock 2 0 It should be noted that the clock is the only event driving input for the flip flop function There is no need to call the function if the signal data_in will be sampled only when the event driving signal clock changes state The designer can write the function so that it samples the data only when the function is called and the clock input is asserted high rising edge triggered If the clock signal is low when the function is called falling clock edge the procedure can ignore the data and return control back to the simulation program The calling arguments to the Java method are set up as a linked list of signal pointers The simulator places the arguments into this list in the same order that they appear in the declaration of th
109. smaller causes more cells to be drawn fully Making this number zero turns off cell simplification The Layer Display Algorithm is the newest but still experimental It has controls for the use of pattern displays and has controls for Alpha blending used in layer composition When zoomed out below the Alpha blending overcolor limit standard alpha blending composition rule is used When zoomed in above this limit alphablending with overcolor composition rule is used 96 Using the Electric VLSI Design System version 8 11 Chapter 4 Display 4 4 Zooming and Panning 4 4 1 Zooming The scale of a window s contents can be controlled in a number of ways The Zoom In command in menu Window zooms in magnifying the contents of the display The Zoom Out command does the opposite it shrinks the display Both zoom by a factor of two During normal editing you can zoom the display with the shift right button or with the control mouse wheel see Section 1 8 Holding shift right while dragging a rectangular area causes the display to zoom into that area making it fill the screen Clicking shift right in a single location causes the display to zoom out centered at that point Holding the control key and rolling the mouse wheel also zooms in and out You can also use the Zoom tool from the tool bar to zoom in and out This has the same zoom in and out _____ functions but they are now attached to the left button no shift needed
110. so you know what you are looking at in simulation It is good practice to label every net in a design When you are done your and2 schematic should look like this Using the Electric VLSI Design System version 8 11 37 Chapter 1 Introduction Next create a new layout called and2 remember to select the layout view Instantiate the nand2 lay and inv lay layouts ALWAYS use the Place Cell Instance command to create layout from pre existing facets NEVER build a cell by cutting and pasting entire existing cells If you do then make a correction to the original cell your correction will not propagate to the new layout Initially the cell instances appear as black boxes with ports Select both instances and use the All the Way command in menu Cell Expand Cell Instances to view the contents of each layout Wire power and ground to each other Move the cells together as closely as possible without violating design rules You may need to place large blobs of pure layer nodes over the n well and p well to avoid introducing well related errors from notches in the wells Connect the output of the nand2 to the input of the inv using Metal 1 Remember that connections may only occur between the ports of the two cells Also connect the power and ground lines of the cells using Metal 2 Export the two inputs the output and power and ground An easy way to do this is to use the Re Export Everything command in menu
111. starting with the deepest subcells that are expanded at the bottom of the hierarchy The One Level Up command closes up the bottommost expanded level the All the Way command closes all levels from the bottom and the Specified Amount lets you type a number of levels of hierarchy to close You can also use the expansion opened eye and unexpansion closed eye icons from the tool bar l to expand and unexpand by one level The expansion information can also be controlled by using the Object Properties command in menu Edit Properties and clicking on the Expanded or Unexpanded buttons There are times when you want to see the layout inside of a cell instance but only temporarily The Look Inside Highlighted command in menu Cell displays everything in the highlighted area down through all hierarchical levels This is a one shot display that reverts to unexpanded form if the window is shifted scaled or redrawn There is a slight difference in specification between the Expand Cell Instances commands and the Look Inside Highlighted command The Expand Cell Instances commands affect cell instances only and thus any instances that are highlighted or in the highlighted area will be completely expanded The Look Inside Highlighted command affects layout display in an area so only those parts of instances that are inside of the highlighted area will be shown Thus the command Look Inside Highlighted is more precise in what it ex
112. technology it can be saved to disk with the Save Library command of the File menu Then in another session of Electric it can be read from disk and converted to a technology Alternatively the XML for the technology can be installed into Electric with the Added Technologies Preferences Using the Electric VLSI Design System version 8 11 219 Chapter 8 Creating New Technologies 8 3 Hierarchies of Technology Libraries Although a technology is normally described with a single library it is also possible to string together a sequence of libraries to describe a technology The sequence forms an inheritance hierarchy where later libraries in the sequence can override elements found in earlier libraries For example one library could be a base description for a family of technologies and another library could be a tailoring description that describes a specific family member The tailoring library might be very small consisting of a single node description That information would then override or augment the base library To connect a sequence of libraries a list is placed in the bottommost library pointing to the earlier or dependent libraries In the example below the current library is smallPads and it is tailored with two other libraries pads and cmos the base library Note that the list implicitly begins with the current library and continues in reverse order In this example the first library examined is padsSmall follow
113. the Bean shell If the script is then the script is read from the standard input e batch run in batch mode no windows or other user interface are shown batch mode implies no GUI and nothing more e version provides full version information including build date e y provides brief version information e NOMINMEM ignore minimum memory requirements and start JVM e help prints a list of available command options Using the Electric VLSI Design System version 8 11 3 Chapter 1 Introduction Memory Control One problem with Java is that the Java Virtual Machine has a memory limit This limit prevents programs from growing too large However it prevents large circuits from being edited If Electric runs out of memory you can request more To do this use General Preferences in menu File Preferences General section General tab At the bottom of the dialog are two memory limit fields for heap space and permanent space Changes to these values take effect when you next run Electric The heap space limit is the most important because increasing it will offer much more circuitry capacity Note that 32 bit JVMs can only grow so far On 32 bit Windows systems you should not set it above 1500 1 5 Gigabytes On 32 bit Linux or Macintosh system you should not set it above 3600 3 6 Gigabytes Permanent space is an additional section of memory that can be insufficiently small For very large chips a valu
114. the Electric VLSI Design System version 8 11 201 Chapter 7 Technologies Contact nodes also have the ability to place the cuts according to different rules The default shown on the left is to pack them as closely as possible in the center of the contact Using the Object Properties command in menu Edit Properties you can change the Cut Placement to At node edges the middle example or In node corner the rightmost example Although individual MOS nodes and arcs have the proper amount of implant around them a collection of such objects may result in an irregular implant boundary To clean this up you can place pure layer nodes of implant that neatly cover the implant area Also you can do this automatically with the Coverage Implants Generator command in menu Tools Generation see Section 9 8 2 7 4 2 The MOSIS CMOS Technology The MOSIS CMOS technology describes a scalable CMOS process that is fabricated by the MOSIS project of the University of Southern California To obtain this technology use the popup menu at the top of the component tab in the side bar and select mocmos Pure Misc Cell This technology can have from 2 to 6 layers of metal 4 are shown here 6 is the default It has 1 polysilicon layer but can be changed to use 2 Metal 4 gg The technology can be set to use either standard rules SCMOS submicron rules or deep rules You can choose whether to allow Metal 3 m stacked vias and
115. the current directory preferably a clean directory with nothing else in it The next step is to get a version of Java that can build source code Although a JRE Java Runtime Environment is sufficient for running Electric it is not able to build the source code For that you must have a JDK Java Development Kit In addition you may want to use an IDE Integrated Development Environment such as NetBeans at www netbeans org or Eclipse at www eclipse org Running under Eclipse Here are some notes about building Electric under Eclipse e Setup Workspace The Workspace is a point in the file system where all source code can be found You can use the directory where you extracted the Electric source code or any point above that e Create Project The Project defines a single program that is being built Use New Project under the File menu and choose Java Project Choose Create project from existing source and browse to the folder where the files were extracted Give the project a name for example Electric e Configure Source Code The Source tab of the Eclipse project settings shows the files that were discovered Make sure that the extracted directory is included along with everything else under it e Configure Libraries The Libraries tab of the Eclipse project settings lets you add other packages that may be relevant to the build There are no required libraries but many optional ones see Section 1 5 on plug ins Use t
116. the file is written or M Enable logging Multiple logs overwritten without prompt S i t p A pt Export Import Memory This is useful in repetitive Maximum memory 1300 megabytes iterations of design simulate and Reset Reset All Current memory usage 1389 megabytes saves the cumbersome Only resets USER Preferences Maximum permanent space JO megabytes file selection dialog However Changes to memory take effect when Electric is next run Help Apply Database M Use Client Server interactions overwrites files without asking Cancel MEE it can be dangerous because it Using the Electric VLSI Design System version 8 11 259 Chapter 9 Tools When reading and writing files Electric remembers the last directory and uses it in subsequent file selection dialogs Since different types of files are often stored in different locations the system remembers many different directories organized by type Thus there may be a current directory for Database work library files for Spice simulation etc Choose the type of file to examine and change the directory associated with it In the Jobs section Beep after long jobs requests that any job which runs longer than a minute make a beep sound when done The Verbose mode requests that all changes made by a job be described in the messages window You can set the maximum number of errors that will be reported at once By default there is no limit to the number of errors
117. the locations Export Import C Crosses C Crosses Reset Reset All z With short names the exports Power left and Only resets USER Preferences Move node with export name Power 1 are both written as Power which Help Apply allows multiple exports with the same functionality but different names to be ema displayed as if they have the same name To remove port display completely use the Layers tab of the side bar see Section 4 5 3 In this panel are options to make exports text completely invisible 70 Using the Electric VLSI Design System version 8 11 Chapter 3 Hierarchy 3 6 3 Export Deletion and Movement You can delete an export simply by selecting its name and using the Selected command of the Edit Erase menu or typing the Delete key You can also use the Delete Export command in menu Export To remove many exports at once the Delete Exports on Selected command removes all exports on all highlighted nodes Also the Delete Exports in Highlighted Area command removes only those exports that are in the selected area When an export is deleted all arcs connected to that port on instances of the current cell higher up the hierarchy are also deleted see Section 2 3 To move export text simply select it and drag it The location of the text has no effect on the location of the export moving the text is only for improvement of the display However if you check Move node with ex
118. the waveform part on the right If the layout or schematics cell that produced the simulation is being displayed in another window and the currently selected network in that window is found in the simulation output then that output can be added to the waveform window with the Add to Waveform in New Panel command in menu Edit Selection You can also use the Remove from Waveform command to remove the currently selected network from the waveform display The order of signals in the waveform window is saved in the original cell so that subsequent simulations will show the same signals You can also save the configuration of the waveform window with the Save Waveform Window Configuration to Disk command in menu Window Waveform Window and you can restore the configuration with the Restore Waveform Window Configuration from Disk command Time Control Two vertical cursors appear in the window called main and extension the extension cursor is dotted Their time values and their difference are shown at the top of the window You can click over the cursors and drag them to different time locations You can also use the Center buttons to bring these cursors to the center of the display The time axis of the simulation window can be controlled with the appropriate Window menu commands Use Zoom Out and Zoom Im to scale the time axis by a factor of two Use Focus on Highlighted in menu Window Special Zoom to display the range between t
119. them The Technology Preferences command in menu File Preferences Technology section Technology tab lets you control many User and Project preferences The Project Preferences are on the left and the bottom part of the Project Preferences is specific to the MOSIS CMOS technology More information about this can be found in Section 7 4 2 Technology PROJECT Preferences _ Categories Technology USER Preferences Defaults Startup technology mocmos X Layout technology to use for Schematics mocmos X IV PSubstrate process in Layout Technology mocmos Technology Metal layers fe Layers v Submicron rules SCMOS rules 4 metal or less Deep rules 5 metal or more IV Second Polysilicon Layer Disallow stacked vias P Alternate Active and Poly contact rules M Analog General Display Io C Tools Technology i Added Technologies Pchematic primitives Buffer buffer inverterRy Design Rules Scale Units Icon mocmos VHDL For primitive buffer Export Import i VHDL for negated primitive linverter EE Hetel I Rotate layout transistors in menu Only resets USER Preferences Help Apply Cancel The Defaults section at the top of the Project Preferences section has these controls e Startup technology controls the technology that is used when Electric first begins It is also used when reading old libraries that are missing some technology
120. two columns one per compared cell The header contains cell names Each row corresponds to a mismatch A table cell has zero or more export lists An export list is a list of all the exports found on a network and is displayed as a list of export names surrounded by curly brackets Each export list is a single hyperlink which highlights all the exports in the list Multiple export lists in a table cell occur when a single network in one design e g the schematic has one or more exports that match multiple exports attached to more than one network in the other design e g the layout For example the mismatch on the third row from the top in the figure below has layout exports the second column attached to a single network matching schematic exports the first column attached to two networks heater NS_pads sch heater NS_padsflay E_core_sclk W_core_TxPlate W_vPIt 1 core_W_vPIt 1 EWN vP W yP vPIt_10 vPIt_11 vPIt_13 vPlt_15 vPlt_16 vPlt W_yvPIt 0 core_W_vPIt 0 i 4 z gt vdd_10 vdd_11 vdd_13 vdd_15 vdod_16 vdd_17 vdd_2 vdd_7 W_LoVo 0 core_W_LoVo 0 W_Lo Vof1 core_W_LoVo 1 W_LoVo 0 W_LoVo 1 loVo_10 loVo_11 loVo_13 loVo_15 loVo An empty table cell means one design has exports that match no exports with the same names in the other design For example the mismatch in the top row above has the layout export E_core_sclk match
121. when an error is detected It checks only the current cell and does not consider the contents of cell instances lower in the hierarchy It therefore offers an instant analysis but not a complete one The incremental DRC also shows simple design rules violations when a node or arc is being moved See Section 2 4 1 for more on this Hierarchical DRC The hierarchical design rule checker uses the same rules and techniques as the incremental checker but it checks all levels of hierarchy below the current cell To run it use the Check Hierarchically command in menu Tools DRC To check only a selected subset of the current cell use Check Selection Hierarchically When checking hierarchically it may be the case that a cell is not designed to be checked in isolation but must have higher levels of the hierarchy considered For example notches in the well areas may be covered at higher levels of hierarchy When this happens tell the DRC to ignore the cell by using the command Add Skip Annotation to Cell Schematic DRC The schematic design rule checker looks for issues that make drawing or editing of the cell difficult These are the errors that is finds 1 Nodes Nodes whose parameters don t match the cell definition check export names units and visibility Stranded pins with no connections exports or attached text Inline pins those that sit in a line between two arcs both of which could be replaced by a s
122. when the first violation for a given pair is found in this mode e Report all errors tells the system to continue checking all possible violations in a pair of geometries even if an error has already been found This is the exhaustive mode and therefore time consuming that will report all violations found Hierarchical errors appear in the cell explorer see Section 4 5 2 Since there can be many errors involving many different rules you can control how they appear by setting Report Errors to e By Cell creates a separate error section for each cell This is the default e By Rule creates a separate error section for each different design rule e Flat creates a single error section with all errors Users with multiprocessor computers can check Multi threaded DRC to speed up the hierarchical design rule checking process The design rule checker remembers the date of the last clean check If a cell has not changed since then it does not need to be rechecked This date information can be stored in the libraries requiring them to be saved or can be held only in Electric s memory requiring them to be rechecked if Electric is restarted You can also request that all date information be removed so that a full recheck is done To see which cells have passed DRC use the General Cell Lists command in menu Cell Cell Info A D is shown in on the right for cells that are DRC current see Section 3 7 1 MOS contact nodes
123. whether or not to use alternate contact rules Finally you can set the technology into Analog mode which provides an Metal 2 e m NPN transistor a Polysilicon Capacitor and many different resistors All of this is done with the Technology Preferences in menu File Metal 1 ag Preferences Technology tab The default orientation of transistors both in the menu and when first placed can be rotated by checking Rotate transistors in menu in the Technology Preferences N Active ad l m j Users of Electric version 6 02 or earlier will have a different MOSIS P Active r CMOS technology called mocmossub This technology attempted to match the submicron rule set but did not do so as accurately as the current mocmos technology If you have designs in that technology they will be automatically converted to the new mocmos when read Well Contacts Transistors 202 Using the Electric VLSI Design System version 8 11 Chapter 7 Technologies Scalable Transistors The MOSIS CMOS technology also has two transistor nodes that can take a text attribute to control their width These transistors also have contacts built into them Without the text attribute the maximum width is displayed However by adding a width attribute they shrink to that size Note that the ports never change location thus allowing them to scale without triggering constraints The scaling feature of these transistors is not very useful beca
124. will have the extension gds2 which is not what Electric expects Electric expects them to end with gds so you may want to rename them e Read the LEF file into Electric with the LEF Library Exchange Format command in menu File Import Keep in mind that the LEF data may come in multiple versions for different numbers of metal layers Read the GDS data into Electric with the GDS II Stream command in menu File Import Note that the proper GDS layers must be established first with the GDS Preferences see Section 7 3 3 There will now be two libraries in memory one with the GDS data and one with the LEF data e Merge the port information from the LEF library into the GDS library It is important that the GDS library be the current library use the Change Current Library command in menu File if it is not To merge the LEF port information use the Add Exports from Library command of menu Cell Merge Libraries You will be prompted for another library and should select the one with the LEF data e At this point the GDS library now has standard cells in it including the export information that was in the LEF library Before saving it to disk you should probably use the Cell Properties command of menu Cells see Section 3 7 3 and set all of the cells to be Part of a cell library 84 Using the Electric VLSI Design System version 8 11 Chapter 3 Hierarchy 3 10 Copying Cells Between Libraries
125. window is the side bar that has 3 tabbed sections the components menu the cell explorer and the layers You can move it to the right side with the On Right command of menu Windows Side Bar and move it back with the On Left command You can also request that the side bar always be on the right by checking Side bar defaults to the right side in the Display Control Preferences in menu File Preferences Display section Display Control tab The cell explorer lets you examine the hierarchy system activity and error messages see Section 4 5 2 for more The components menu shows a list of nodes blue border and arcs red border that can be used in design The arrangement of the entries in the components menu varies with the different technologies For MOS technologies see Section 7 4 2 for schematics see Section 7 5 1 and for artwork see Section 7 6 1 The top three entries in the components menu let you place pure layer nodes see Section 6 10 1 miscellaneous objects see Section 7 6 3 and instances of cells see Section 3 3 The layers tab lets you control which parts of the display are visible See Section 4 5 3 for more on layer visibility Below the edit window is the messages window which is used for all textual communication Above the edit windows is a pulldown menu along the top with command options On some operating systems the pulldown menu is part of the edit window and on oth
126. wires in their Manhattan orientations For example if a rigid arc vertical fixed angle arc connects two nodes and the bottom node moves left then the arc and the top node also move left by the same amount If that bottom node moves down the arc simply stretches without affecting the other node If the bottom node moves down and to the left the arc both moves and stretches Rotation of nodes causes no change to fixed angle arcs unless the arc is connected to an off center port in which case a slight translation and stretch may occur Contact rotated fixed angle arc Eeh Most IC layout is done with Manhattan geometry If you suspect that some of your wires have become skewed use the Show Nonmanhattan command in menu Edit Cleanup Cell 5 2 2 Slidable Arcs Another constraint available only for nonrigid arcs is slidability When an arc is slidable it may move about within its port To understand this fully you should know exactly where the arc endpoint is located Most arcs are defined to extend past the endpoint by one half of their width This means that the arc endpoint is centered in the end of the arc rectangle If the arc is 2 wide then the endpoint is indented 1 from the edge of its rectangle All arc endpoints must be inside of the port to which they connect If the port is a single point then there is no question of where the arc may attach If however the port has a larger area as in the case of contacts then
127. world Its name will be N MQQQQYY Y WN visible on the unexpanded instance node in the i ANY higher level cell igher level ce MyCircuit lay N gt You can now connect wires to that node in just N the same way as you wired the contact SY WN RQ hA SY N N 1 10 9 IC Layout Tutorial Final Points Some final commands that should be mentioned in this introductory example are the Save Library and the Quit commands which can be found in the File menu They do the obvious things Using the Electric VLSI Design System version 8 11 25 Chapter 1 Introduction 1 11 Schematics Tutorial 1 11 1 Schematics Tutorial Make a Cell This section takes you through the design of some simple schematics T New Cell xi Library noname v Name MyCircuit Before you can place any schematics the editing window must have a cell in it Use the New Cell command in menu Cell Type the name MyCircuit is used here View and select the schematic view Technology Cancel Make new window The editing window will no longer have the No cell in this window message and circuitry may now be created Note that the component menu on the left will change to show schematics primitives Also the Schematic technology is now listed in the status area at the bottom of the screen After creating a cell look at the cell explorer in the status bar on the left side of the EENE LIBRARIES E noname Cu
128. y gt lt width gt lt height gt lt orientation gt lt flags gt lt variable gt I lt type gt lt name gt lt nameTD gt lt x gt lt y gt lt orientation gt lt flags gt lt TD gt lt variable gt the type of the node instance For primitive node instances this has the form lt technology gt lt primitive node gt If lt technology gt is omitted the technology lt type gt of the cell is assumed For cell instances it has the form lt library gt lt cell gt lt version gt lt view gt If lt library gt is omitted the library defined by this JELIB file is assumed lt name gt _ the name of the node instance lt nameTD gt fa text descriptor for the name when displayed lt x gt the X coordinate of the anchor point of the node instance lt y gt the Y coordinate of the anchor point of the node instance f the difference between width of the primitive node and the standard width of lt width gt E i tee this primitive tein fh difference between height of the primitive node and the standard height of lt height gt a a this primitive The lt orientation gt field consists of any of the following letters with an optional numeric part at the end X if the node instance is X mirrored mirrored about Y axis Y if the node instance is Y mirrored mirrored about X axis R each letter rotates the node instance at 90 degrees counter clockwise Using th
129. you cannot make changes to it Any change is immediately undone by the project management system This means that a change which affects unchecked out cells higher up the hierarchy will also be disallowed To check out the current cell use the Check Out This Cell command If there are related cells hierarchically above or below this that are already checked out to other users you will be given warnings about potential conflicts that may arise To check the current cell back in use the Check In This Cell command You will be prompted for a documentation message about the change No further changes will be allowed to the cell Note that when checking in a cell other cells above and below this in the hierarchy will also be checked in This is because changes affect other cells in the hierarchy and so consistent pieces of the hierarchy must be updated at the same time PEHEE LIBRARIES The cell explorer shows the samplesCl Current state of cells that are under tech Bipolar project management tech Bipolartsch Checked Out to You unlocked a tech Bipolarfic a tech Bipolar lay T tech MOSISCMOS lay t Checked In locked but key available control see Section 4 5 2 Locks are drawn over cells to indicate their tech SchematicsAnalog sch state checked in T tech SchematicsDigita sch checked out to you or tool PadFrameilay Checked Out to Others
130. 0 2 microns as shown in the status area When the grid is displayed the dots are therefore 0 2 microns apart For more information on scaling Section 7 2 1 Note that the grid display changes as you zoom in and out When zoomed too far out to show all of the dots only the bolder dots are shown When zoomed too far out to show even the bolder dots the grid is not displayed However the fact that the grid should be on is remembered so it reappears when you zoom back in Use the Make Grid Just Visible command in menu Window Special Zoom to change the zoom factor so that the grid is minimally visible _ Categories Grid USER Preferences E G ana The Grid Preferences in menu i nalts Grid Display File Preferences Display Display Control Horizontal Vertical section Grid tab presents a Component Menu Grid dot spacing a fi fi dialog in which grid dot spacing Layers for current window may be set You can change the bd lai N R Tex grid spacing for the current Smart Text For new windows fi fi window and also set a default grid e spacing to be used in new Ports Exports Frequency of bold dots fio fio windows The grid spacing is also Im show X and Y axes used by arrow keys when they Loe move objects see Section 2 4 1 a Alignment of Cursor to Grid Horizontal Vertical oe E Technology Additional grid graphics are C Size 1 largest 20 available such as the display of Export
131. 1 number of pads180nm_150um PAD_raw padRaw ports The name suggests that all wires in this class are connected to the padRaw ports of 3 instances of parts with type PAD_raw from library pads180nm_150um NCC Messages heater NS_pads sch lay 31 Exports 28 Wires 3 12 VW_ PIt O 4 eae E_core_eq o 10 o s E pads1 80nm_150ur PAD_raw welltapL ports pads180nm_150um PAD_inbuf_6stage dyddL ports a pads 80nm_150um PAD_inbuf out ports 5 di 1 number of pads180nm_150um PAD_raw padRaw ports He 324 vdd_3 4 E When a wire class node is selected the right half of the window displays a two column table see figure below Each column corresponds to one of the compared cells and has a list of that cell s wires which belong to the selected wire class Matched wires are printed in green the two wires on the same line match each other Mismatched wires are printed in red in no particular order Using the Electric VLSI Design System version 8 11 315 Chapter 9 Tools NCC Messages Di xi Mismatched Comparisons 3 C Parts 5 4 Wires 22 1 falucontrol 2 2 src2 3 4 aluopb 1 G3 5 or 6 alubiny 7 d 8 mipscells bitslice sch lay 34 mipscells zipper sch lay 19 4 mipscells datapath sch lay 27 4 3
132. 3D display In Electric there are 3 types of behaviors available Effect 1 Orbit Behavior combines three basic mouse behaviors zoom pan and rotate The left button rotates the right button pans and the DOWN Arrow Move along Z axis UP Arrow Move along Z axis CTRL DOWN Arrow Move along Y axis iddle butt Click and drag to alt eared Be er nen fee CTRL UP Arrow Move along Y axis the display 2 3D Axis Behavior is available when the 3D axis is shown Clicking on the axis affects rotation but not panning or zooming This axis is not part of the standard Electric ALT LEFT Arrow Move along X axis ALT RIGHT Arrow Move along X axis RIGHT Arrow Rotate along Y axis Ree LEFT Arrow Rotate along Y axis distribution and must be installed separately CTRL RIGHT A R i T see Section 1 5 1row otate along Z axis CTRL LEFT Arrow Rotate along Z axis ALT DOWN Arrow Rotate along X axis ALT UP Arrow Rotate along X axis W as shown in the table Navigator Behavior is controlled by special keys Use the up down left right arrow keys Using the Electric VLSI Design System version 8 11 123 Chapter 4 Display Animation A 3D display can be animated by creating key frames along a time line Interpolators examine the key frames and smoothly animate the 3D view There are two types of interpolators simple and path Simple interpolators have a start and end frame varying th
133. 5 2 The Cell Explorer The cell explorer resides in the Explorer tab of the side bar It shows a hierarchical tree with three main sections LIBRARIES ERRORS and JOBS PREF LIBRARIES The LIBRARIES section of the explorer lists all libraries and cells T AB heater Current padin lay You can examine them in three different ways f noname Current adder sch e Alphabetically all cells are listed alphabetically latch e By group all cells are listed alphabetically but are also S apai organized into cell groups 1 ater adic e By hierarchy only the top level cells of each library are iatchilay listed top level cells are those that are not used as instances T ERRORS in any other cells Inside of a cell are the subcells that DRC full Current comprise it along with the number of times that that cell Spacing layer Metal 2 node Metal 1 Spacing layer Metal 2 node Metal 2 appears A JOBS Design Rule Check running To change the view right click on the LIBRARIES icon and choose a view Note that libraries and cells which have been modified are listed in bold face When an entry in the explorer is shown in boldface it means that it has been changed and not saved When a schematic cell in the explorer has after its name it means that the cell is the main schematic this happens only when there are multiple schematic cells in a single cell group The second part of the cell explor
134. 6 Advanced Editing 6 5 Spreading Circuitry When a large amount of circuitry has been placed too close together or too far apart Electric s constraint system can help All that is necessary is to make all arcs in an area rigid and then move one node Of course you may have to move more than one node if the one you pick is not connected to everything else you want to move Also you must make sure that arcs connecting across the area boundary are nonrigid Finally setting arc rigidity should be done temporarily so that it does not spoil an existing constraint setup All these operations are handled for you by the Spread command in menu Edit Move Spread About Highlighted xi With the Spread command the highlighted node is a focal point about which objects move A dialog is presented in which an amount and a direction up down left or right are specified An infinite line Spread down is passed through the highlighted node s center and everything above rai C Spread left below to the left of or to the right of the line is moved by the P C Spread right Distance to spread Spread up specified amount Negative spread distances compact the circuit 150 Using the Electric VLSI Design System version 8 11 Chapter 6 Advanced Editing 6 6 Replacing Circuitry Change of x Cells CellA lay The Change command in menu Edit removes the currently highlighted node or arc and replaces it w
135. 8 11 Chapter 8 Creating New Technologies on the same network This does not mean that a device arc cannot contain a well layer Device arcs will be declared as p diffusion or n diffusion and their well layer will be handled correctly the arc connectivity is really defined by the device diffusion layer For example a p device arc will have an N well or N substrate under it and a p type diffusion will end up as part of the drain or source of the P transistor to which it is connected Editing Arc Geometry In addition to the above information the arc must also be described with pieces of geometry on the various layers Thus a prototypical arc must be drawn in this cell The length of the arc is not important but the smaller dimension is presumed to be the width and defines the default for this arc type Use the entries from the component menu of the side bar to create new layers The typical layer in an IC technology is a Filled box third from the top After the geometry is created it can be moved and resized with standard ix Outlined Box Electric commands Remember to keep all arc geometry separate from the information messages in the cell so that the technology editor can distinguish them Once a piece of geometry is created its layer can be set by double clicking on it A menu is then presented with possible layers ignore the last entries SET MINIMUM SIZE and CLEAR MINIMUM SIZE which are used only for nodes
136. Algorithm is newer and is faster for panning and zooming This algorithm optimizes the display of circuitry by simplifying the display of objects when they get to be very small For example when zoomed out very far a transistor may be only 1 screen pixel in size and it does not make sense to carefully compute and draw all of its parts In such cases the algorithm simplifies display of the object usually drawing it as a single dot Besides simplifying individual nodes and arcs Electric also simplifies the display of entire cells if their contents are all too small to draw Such simplification can consist of rendering the cell with a single approximating color or keeping a small image of the cell and using it in the proper place There are some controls for the Vector Display Algorithm The first control selects whether cell simplification uses an image of the cell or just an approximating color The next control determines the size at which objects are simplified The default is to Simplify objects smaller than 3 pixels Making this value smaller will cause more detailed drawing but take longer The last control determines the threshold for simplifying entire cells Although a cell s contents may be small the cell may be quite large on the screen and so should not be simplified this happens to top level cells in a deep hierarchy The default limit is to Do not simplify cells greater than 10 percent of the screen Making this number
137. DOWN IN PLACE BORDER To disable the graying out of upper levels of hierarchy use the Display Control Preferences and uncheck Dim upper levels of hierarchy when editing Down In Place Using the Electric VLSI Design System version 8 11 65 Chapter 3 Hierarchy The Down Hierarchy In Place To Object command finds the object under the cursor at any level of the hierarchy and descends to that level This may go down the hierarchy many times It descends in place so that the original geometry is visible but higher levels are grayed out It is useful when trying to quickly find the hierarchy that exists at that point and see which instances were used to construct it Note that there may be many different levels of hierarchy under the cursor which will cause a popup to appear listing the possible subcells to edit This popup will list only one object at a given level of hierarchy even though there may be many more Schematic Considerations If an icon is selected the Down Hierarchy commands will take you to the associated schematic If the icon that is selected is already in its own schematic you can place an icon inside its own schematic for documentation purposes then the Down Hierarchy command takes you to the actual icon so that you can edit it The Down Hierarchy In Place command takes you directly to the icon showing it in the context of the upper level schematic Schematic nodes can be arrayed by giving them array names se
138. E EEE HE Copy Pattern Paste Pattern 3D Thickness 2 65 Coverage percent 0 0 The stipple pattern can be changed by double clicking on any grid squares You can also do operations on the entire stipple pattern Clear Pattern Invert Pattern Copy Pattern and Paste Pattern by double clicking on their name below the pattern area Using the Electric VLSI Design System version 8 11 221 Chapter 8 Creating New Technologies Change Color xi z The color of the layer can be changed by double clicking on the Color entry The dialog lets you choose a color Opacity 0 1 oas opacity and foreground factor for the layer Opacity ranges from 1 0 fully opaque to 0 transparent The foreground flag is on to indicate that the non opaque colors can be Cancel combined with others Transparency lets a layer have a unique appearance where it overlaps other layers The overlap is defined in the technology s color map You can double click on the Transparency entry to assign this factor to a layer Non transparent layers with Transparency none are opaque so they obscure anything under them when drawn In general the most commonly used layers should be transparent See Section 4 6 1 for more information on transparency Color Foreground jon x The Style entry on the right can be solid or patterned with varying outline types around the pattern None Solid Solid Thick Soli
139. ERSION is the version number of this view c l GROUP Different Views oft da of EAA no VA Daa is displayed ersiahe CELL CELL CELL CELL it implies that this cell is the most recent version jatch sch has the largest number Thus the cell gate 2 lay is more recent than gate 1 lay CELL but less recent than gate lay which must have a higher version number probably 3 PHEE LIBRARIES In this example there is a library with two cell groups One MyCircuit Current group has a set of cells called gate and the other has a set of gate cells called latch On the right is the explorer view of these gate sch cells See Section 4 5 2 for more on the cell explorer gatefic gateflay Although it is not necessary for cells in a group to all have the x ane same name the system presumes that common names will be latch grouped together Once in a group you can rename a cell to give latch sch it a different name than the others in its group Use the Rename WH atch 1 sch Cell command in menu Cell You can also use context menus latch ic in the cell explorer to rearrange groups x EPOPEA Using the Electric VLSI Design System version 8 11 59 Chapter 3 Hierarchy 3 2 Cell Creation and Deletion New Cell xi Library noname v Name Adder Cells are created with the New Cell command in menu Cell The New Cell command requests a new cell name as viek
140. Generation to automatically generate fill see Section 9 8 2 9 2 5 Assura and Calibre DRC Electric is able to read the output of Cadence s Assura and Mentor s Calibre design rule checkers Assura error files with the extension err can be read with the Import Assura DRC Errors for Current Cell command in menu Tools DRC Calibre error files with the extension db can be read with the Import Calibre DRC Errors for Current Cell command After reading the error file you can review the errors by typing gt and lt to step to the next and previous error that was found You can also see a list of errors in the cell explorer see Section 4 5 2 266 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools 9 3 Electrical Rule Checking 9 3 1 Well and Substrate Checking To check the well and substrate layers use the Check Wells command in menu Tools ERC This does a more thorough job of checking the layers than the design rule checker After analysis is done you can review the errors by typing gt to see the next error and lt to see the previous error You can also see the list of errors in the cell explorer see Section 4 5 2 You can control the Well Checker with the Well Check Preferences in menu File Preferences Tools section Well Check tab JD Preferences Tools Well Check USER Preferences Antenna Rules Compaction Coverage DRC Fast Henry Logical Effort
141. HDL or Verilog into schematic or layout 3 11 3 Creating and Deleting Views T View Control If the list of possible views is not sufficient to describe a cell new views can be created with the View Control command in menu View This command shows all views and lets you create and delete them layout skeleton lay sk layout compensated lay comp VHDL vhdl When creating a new view a name and an abbreviation are required The abbreviation should be the first few letters of the full view name This abbreviation will be used when Verilog ver describing cells with that view For example the view documentation doc H fast layout might have the abbreviation fast view name tast layout Abbreviation fast Text view Done Create The Delete button deletes views that you have created it cannot delete the views that exist on startup such as layout schematic etc Also there must be no cells with the view that is being deleted The Text View checkbox indicates that this is a text only view like Documentation Netlist Verilog and VHDL 88 Using the Electric VLSI Design System version 8 11 Chapter 3 Hierarchy 3 11 4 Automatic Icon Generation A particularly useful view type is icon The icon cell is used for instances of an associated contents cell which contains schematics For example you may have a cell called adder sch which contains a schematic You may then
142. I if instances in the cell are locked L if everything in the cell is locked T if this cell is part of a technology library Example CrxArray 1l lay mocmos 1092185029000 1092185060000 I Declares cell rxArray lay version 1 associated with the mocmos technology The cell was created at date 1092185029000 and last modified at date 1092185060000 All instances in the cell are locked 348 Using the Electric VLSI Design System version 8 11 Chapter 10 The JELIB and DELIB File Format Groups In older JELIB files the group information appears in special group lines Each group line consists simply of a list of cells in that group The first cell listed is the main schematics of the group If there is no such cell the first field is empty After that the cells appear in alphabetical order When multiple groups are declared they appear sorted by the group name which is derived from the cell names in it The syntax is G lt cell gt lt cell gt lt cell gt the name of the cells in the group lt cell gt may consists only of proto name lt cell gt because all cells with the same base name are put into the same group 10 3 2 Node Instances Inside of a cell definition node instances are declared with the N and I lines N is for primitive nodes and I is for cell instances All nodes are sorted by the node name The syntax is N lt type gt lt name gt lt nameTD gt lt x gt lt
143. L file with preference information which can be read back into Electric with the Import button or the Preferences commands in menu File Import Project Preferences are also saved with your circuitry so that the values will be correct when the circuits are read back in By default project preferences are saved in each library that is written to disk However for multiple library projects this can be troublesome if some libraries have different preferences than others The solution is to create a file in the same directory as the libraries called projsettings xml If this file exists then preferences are taken from it and ignored in the libraries To write this file use the Project Preferences command in menu File Export To override current settings and explicitly read a project preferences file use the Project Preferences command in menu File Import When Electric finds Project Preferences JD Project Setting Reconciliation that are inconsistent Library mipsparts wants to use the Following project settings which differ From the current project settings with the current values this dialog SETTING CURRENT VALUE LIBRARY VALUE SETTING LOCATION appears You must choose whether you want to use the new MOSIS CMOS Number of Metal Layers C 6 3 Technology tab MOSIS CMOS scale 200 0 300 0 Scale tab setting values or the current setting This an be done on an Use All Current Settings Use All New Settin
144. Mismatched Comparisons 1 2 Part s in mipscells bitslice sch in mi mipscells bitslice sch lay 34 Exports 10 5i M Parts 3 CE 1 2 mipscells mux4 11 Wires attached 2 1 mipscells inv 3 4 mipscells mux2 I ad Wires 21 mipscells mux4 mux4 0 in Cell mipscells mux4 src2mux in Cell mipscells mux4 sre2mux in Cell The number of attached Wires as a Part class characteristic 314 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools Parts on the same line match each other Mismatched parts are printed in red in no particular order Wires NCC partitions wires into equivalence classes based upon the number of different port types attached to them Examples of port types include an NMOS gate port a PMOS diffusion port and a NAND output port Port type counts are represented as a list of leaf nodes under the wire class node Since zero value counts at the beginning of the list tend to be numerous and are rarely used by designers they are further grouped under a 0 s node For example in the figure below the second wire class is expanded and we can see its four characteristics the first three of which are zero The first characteristic has a leaf node called pads180nm_150um PAD_raw welltapL ports which means that wires in this class are not attached to the port welltapL of the part PAD_raw from the library pads180nm_150um The fourth characteristic is
145. Note that ports on primitive nodes are not exported with these commands See Section 6 4 for more about arrays and see Section 9 6 1 for more on automatic wiring Another special command for export creation is Add Exports from Library in menu Cell Merge Libraries which copies exports from another library into the current one The other library is examined for cells whose names match ones in the current library When a cell is found in the other library all of its 68 Using the Electric VLSI Design System version 8 11 Chapter 3 Hierarchy exports are copied to the cell in the current library if they don t already exist and placed in the same location This command is useful in managing standard cell libraries that are imported from other file formats see Section 3 9 4 on Standard Cell Libraries Because some formats contain geometry and others contain connectivity this command is needed to put them together 3 6 2 Export Information Exports are selected by clicking on their text or by clicking on the node from which they are exported If a very dense design makes export selection hard you can choose from a list by using the Select Object command in menu Edit Selection To see all exports that have been defined in the current cell use the Show Exports command in menu Export This command highlights the exports on the screen using the global text scale to affect size see Section 6 8 4 The List Expo
146. Polysilicon 1 Polysilicon 1 Pin Metal 1 Polysilicon Node POPUP POPUP letal 1 N Active C Node POPUP POPUP Metal 1 P Active C Node Node vietal 1 P VVell Co Bvletal 1 N Vell Co Zanet mot Popup menu entry Add Row Below Current Reset Reset All Metal 1 Polysilicon 2 Con H Delete Row With Current Only resets USER Preferences a gt Help Foe Angle Add Column to Right of Current Function contact x er aaa Cancel repel Fd elete Column With Curre if ik The structure of the menu can be altered with the buttons in the lower right Use Add Row Below Current to add a new row below the selected entry Use Delete Row With Current to delete the row that includes the selected entry Use Add Column to Right of Current to add a new column to the right of the selected entry Use Delete Column With Current to delete the column with the selected entry Using the Electric VLSI Design System version 8 11 101 Chapter 4 Display When a menu entry with a node is selected the fields in the lower left let you add information to that node e Angle indicates the angle that the node will be placed For example if you want a transistor node to appear and be placed with 90 degree rotation set this field to 90 e Function indicates the function of the node This information is used for grouping like nodes and scaling them together e Label is optional text that will appear in the menu entry 4
147. Preferences I O section DEF tab to affect how DEF is read see Section 7 3 5 Using the Electric VLSI Design System version 8 11 79 Chapter 3 Hierarchy e DXF AutoCAD is a solid modeling interchange format and so it may contain 3D objects that cannot be read into Electric Nevertheless Electric creates a library of artwork primitives as well as it can Use the DXF Preferences in menu File Preferences I O section DXF tab to affect how DXF is read see Section 7 3 7 e SUE Schematic User Environment is a schematic editor that captures a single cell in each file The circuitry in SUE files is added to the current library instead of being placed in its own library because many SUE files may have to be read to build up a single Electric library When reading a SUE file any subdirectories that start with suelib_ will also be examined for dependent SUE cells Use the SUE Preferences in menu File Preferences I O section SUE tab to affect how SUE is read see Section 7 3 8 e Spice Decks are input to the Spice simulator and define a netlist of circuitry See Section 9 4 3 for more on Spice Reading Spice Decks will create wired instances but the placement of the instances will be automatically generated because that information is not in the Spice deck e Applicon 860 is a layout format from old Applicon EDA systems e Verilog is a hardware description language used for simulation and fabrication El
148. Primitives command in menu Edit Technology Specific FPGA You will be prompted for an architecture file To read only the primitives from an architecture file use the Read Primitives command Once an FPGA is on the screen two aspects of its display can be controlled the wires and the text Three commands control the display of wires Show All Wires displays every wire Show No Wires hides every wire and Show Active Wires shows only the wires that have been connected to PIPs that have been programmed Two commands control the display of text Show Text displays text and Hide Text turns text display off Once an FPGA has been created you can program the PIPs by selecting a component and using the Edit Pips command This will display a list of active PIPs on the component For example after clicking on one of the SampleBlock instances you can type the string pip1 pip4 to program two of the pips in that instance 7 6 3 The Generic Technology One particularly interesting technology is the Generic technology which is a grab bag of miscellaneous facilities It is not necessary to actually switch into this technology for all of its nodes and arcs are available through other means Special Arcs The Universal arc in the Generic technology is able to make a connection between any two components even if they are in different technologies This is useful when mixing technologies while still maintaining proper connectivity for e
149. R HIGHLIGHT is the color of highlighting when the mouse roams over a new object default light blue e NODE HIGHLIGHT is the color of highlighted nodes in special situations default blue e PORT HIGHLIGHT is the color of highlighted ports in special situations default blue e TEXT is the color of text that has not been assigned a specific color default black e WAVEFORM are special colors used in drawing the waveform window see Section 4 11 1 e 3D are special colors used in drawing the waveform window see Section 4 10 2 Using the Electric VLSI Design System version 8 11 107 Chapter 4 Display Preferences Preferences Layers USER Preferences General H 0 Display Technology imocmos Layer Metal 1 x Display Control Component Menu Coloxp n Pattern Transparency ftr ansparent 1 P Use Fill Pattern on Screen Toolbar i Text Swatches H5B RGB Smart Text Grid 3 H 1974 Ports Exports Ce s 625 Frame 3D B 104 1 0 Tools Technology R 96 G 209 B 255 Export Import Reset Reset All C n i i m Only resets USER Preferences Oukine pattern aT a bs Transparen Help Apply eae ae 1 Opaque IV Use Fill Pattern on Printer Each layer has a color on the left and a pattern on the right The color can be specified directly in the color picker or it can b
150. SI Design System version 8 11 Chapter 1 Introduction 1 12 Schematics and Layout Tutorial 1 12 1 Schematics and Layout Tutorial Introduction This tutorial was originally written by David Harris at Harvey Mudd College as the first in a set of lab instructions for an undergraduate level CMOS VLSI design class It provides very basic instructions to acclimatize first time users with Electric As such it is not a full introduction to using Electric nor does it cover many commonly used commands What this tutorial does cover is e Basic schematic editing You will create a simple nand gate e Layout drawing You will create the IC layout of the nand gate e Hierarchy You will assemble the nand with an inverter to build an and gate e Analysis You will run the design rule checker on the layout and will compare the layout with the schematic To begin load the mipscells library from the Static Free Software website www staticfreesoft com productsLibraries html This library contains many parts of the MIPS processor that are provided to you You will add your new design to the library as you work through the tutorial 1 12 2 Schematics and Layout Tutorial Schematic Entry Your first task is to create a schematic for a 2 input NAND gate Each design is kept in a cell for example your schematic will be in the nand2 sch cell while your layout will eventually go in the nand2 lay cell and your AND gate will go i
151. Set Clear IV Expand new instances of this cell Set Clear Technology artwork x For Textual Cells Font DEFAULT FONT x Size fiz Cell Frame Landscape Size None v I Title Box C Portrait Designer Name Cancel OK The checkbox Disallow modification of anything in this cell allows you to control whether the contents of a cell is editable or not When modification is disallowed no changes may be made This is useful when you want to allow examination without accidental modification The checkbox Disallow modification of instances in this cell also prevents changes to the selected cell but in this case only instances of sub cells are locked This is useful when you have a correct instance placement and are doing wiring Allow changes x If you make a change that has been disallowed a AN Changes to cell gallery sch are locked Change anyway dialog appears that asks if you want to override the lock Yes Always You may make the change Yes disallow the change No or remove the lock Always which Using the Electric VLSI Design System version 8 11 75 Chapter 3 Hierarchy unchecks the locks in this dialog The check box Standard cell in a cell library indicates that this cell is a standard cell and should be treated accordingly Verilog generation uses this information see Section 9 4 2 The check box Part of technology editor librar
152. TACT4 CONTACTS CONTACTO6 cuts CONTACT7 CONTACT8 CONTACT9 CONTACT10 CONTACT11 CONTACT12 cuts RESISTOR CAP resistor capacitor TRANSISTOR transistor EMITTER BASE COLLECTOR bipolar parts DMY DEXCL dummy and dummy exclusion for different layers BUS ART schematics and artwork PLUG OVERGLASS GUARD ISOLATION specialty TILENOT CONTROL specialty e extraFun optional functions for this layer taken from this list nonelectrical connects metal connects poly connects diff heavy light depletion_heavy depletion_light enhancement_heavy enhancement_light vt thick native inside_transistor deep carb nano n type deprecated use fun IMPLANTN p type deprecated use fun IMPLANTP Example lt layer name Poly Cut fun CONTACTI extraFun connects poly gt Inside of the lt layer gt element are these subelements 240 e lt transparentColor gt the transparent color to use if omitted this is an opaque layer e lt opaqueColor gt the opaque color to use e lt patternedOnDisplay gt true to use the lt pattern gt when drawing on the screen e lt patternedOnPrinter gt true to use the lt pattern gt when printing e lt pattern gt the stipple pattern to use if requested on either the screen or printed page e lt outlined gt true to outline the layer sensible only for patterned layers Using the Electric VLSI Design System version 8 11 Chapter 8 Creating New Technologies e lt opacity gt intensity of this
153. To add a Verilog declaration in this cell select Verilog Declaration under the Misc entry in the component menu To add a Verilog parameter to this cell select Verilog Parameter under the Misc entry in the component menu To add external Verilog code outside of this cell select Verilog External Code under the Misc entry in the component menu These pieces of text can be manipulated like any other text object see Section 6 8 1 on text For an example of Verilog layout and code look at the cell tool SimulateVERILOG in the Samples library get this library with the Load Sample Cells Library command in menu Help Additional control of Verilog deck generation is accomplished with the Verilog Preferences in menu File Preferences Tools section Verilog tab 270 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools Verilog USER Preferenc Antenna Rules Compaction Coverage DRC Fast Henry Logical Effort NCC Network Parasitic amp 2 a amp Placement poput Routing P Run Placement after import Silicon Compiler Output Simulators Spice T Do not netlist Standard Cells Spice Model Files IV Preserve Verilog formatting x J Parameterize Verilog module names Export Import P Write Separate Module for each Icon Reset Reset All Only resets USER Preferences Help Apply Cancel The left side is the Verilog Project Preferences
154. Using the ELECTRIC VLSI Design System Version 8 11 Steven M Rubin Static Free Software and Sun Microsystems Author s affiliation Static Free Software and Sun Microsystems ISBN 0 9727514 3 2 Published by R L Ranch Press 2010 Copyright c 2010 Static Free Software and Sun Microsystems Permission is granted to make and distribute verbatim copies of this book provided the copyright notice and this permission notice are preserved on all copies Permission is granted to copy and distribute modified versions of this book under the conditions for verbatim copying provided also that they are labeled prominently as modified versions that the authors names and title from this version are unchanged though subtitles and additional authors names may be added and that the entire resulting derived work is distributed under the terms of a permission notice identical to this one Permission is granted to copy and distribute translations of this book into another language under the above conditions for modified versions Electric is a trademark of Static Free Software a division of RuLabinsky Enterprises Incorporated Table of Contents Chapter 1 MntrOd uti On ss cs siesedseidssssssccancosssssavessevecossessasevebsesssssessesesvonsescosceosceecssevoase svbacsoaneesbaces sS ospis obedeesenssses 1 DEW CLC OME cess ciate e cee dade aed sch e ae e E e ss E a E e AE etaa A A EE 1 1 2 gt ADOUt Eleti eni enn eeen Mates a se
155. When done editing the outline switch to standard selection mode the Click Zoom Wire command in menu Edit Modes Edit Using the Electric VLSI Design System version 8 11 171 Chapter 6 Advanced Editing 6 10 3 Special Outline Generation To generate text shaped outlines use the Layout Text command under the Misc entry in the component menu This dialog prompts for text and a Annulus Construction Ed Layer to use for ring Metal 1 Node Inner Radius Outer Radius Number of segments Number of degrees Cancel To generate a doughnut shaped outline use the Annular Ring command under the Misc entry in the component menu This dialog prompts for a layer to use and an inner and outer radius for the annulus By default it is made as a full circle 360 degrees but this can also be changed Also the number of line segments used in the construction can be set allowing for smoother or coarser shapes 5 0 32 360 Ati Size max 63 fiz Scale Factor fi layer to use as well as the size scale font and style A nonzero dot separation causes each pixel of the text to be placed separately some design rules need this Font Dot separation units fo arial v Reverse Video inverts the placement of the dots that make up the text 172 P Italic Bold f Underline Layer Metal 4 Node ba I Reverse video Message VDD Cancel Using the Electric VLSI D
156. a horizontal or vertical path from the originating node To see where the wire will end click but do not release the button and drag the outline of the wire s terminating node a pin until it is in the proper location It is highly recommended that you do all wiring operations this way because wiring is quite complex and can follow many different paths Once a wire has been created the other end is highlighted see above This is the highlighting of a pin node that was created to hold the other end of the arc Because it is a node the right button can be used again to continue the wire to a new location If during wiring the cursor is dragged on top of an existing component the wire will attach to that component To remove wires or components you can issue the Undo command in menu Edit to remove the last created object Alternatively you can select the component and use the Selected command in menu Edit Erase 1 10 5 IC Layout Tutorial Constraints Once components are wired moving them will also move their connecting wires Notice that the wires stretch and move to maintain the connections What actually happens is that the programmable constraint system follows instructions stored on the wires and reacts to node changes The default wire is fixed angle and slidable so the letters FS are shown when the wire is highlighted Select a wire and issue the Rigid command in menu Edit Arc The letters change to R on the arc
157. a in any order DELIB Format In order to enable CVS version control see Section 6 13 Electric also has a delib format This format is actually a directory with the delib extension that contains multiple jelib format files Each of the files in a delib directory contains a single view of a single cell although it may contain multiple versions of that cell Instead of naming these files with the jelib extension they use the cell name for their file name and the cell view for their file extension The cell files in a delib directory have no V views T technologies O tools or G group lines see above Instead these lines appear in a separate file called header which also has a copy of the H line Where C cell lines should appear the header file contains this text C SEARCH_FOR_CELL_FILES For example assume that library X has cells A lay A sch and two versions of cell B lay B lay and B 1 lay When written as a jelib all four of these cells will be stored in the file X jelib When written as a delib there will be a directory called X delib with the files A lay A sch B lay with two cells in it and header When a cell is deleted from a library its delib file is not deleted but is retained for archival purposes To mark it as deleted however it is renamed so that it has the extension deleted 344 Using the Electric VLSI Design System version 8 11 Cha
158. abs Floorplan and Tiling The Floorplan section specifies what is inside of a single fill cell The Tiling section specifies how those cells are arrayed The Floorplan section offers two fill techniques Template Fill and Fill Cell not yet available Template Fill generates fill cells of a given width and height The default values reflect the minimum spacing rules given by the technology The Reserved Space section lets you specify which layers of metal will be in the fill cells These metal layers alternate running horizontally and vertically the Even layer orientation controls which layer runs horizontally first Using the Electric VLSI Design System version 8 11 325 Chapter 9 Tools The fill cell will have four metal wires running in each direction the outer two are Ground and the inner two are Power The spacing between the inner two is given in the Vdd Space section next to the selected metal layer The spacing between the ground wires and the edge is half of the Gnd Space value The spacing between the power and ground wires is the minimal design rule spacing for that layer of metal The width of the wires is then adjusted to fill the remaining space in the cell Fill Cell Generator Ed Floorplan Tiling Which tiled cells to generate Bee Bees l 4x4 Bees 6x6 Dea coe 326 M 8x8 9x9 T 10x10 Bile Book Bees The Tiling section lets you request arrays of fill cells
159. acts to that layer of metal For example if you are running a metal 1 wire and type 3 during the wiring then two contacts will be added metal 1 metal 2 and metal 2 metal 3 to make the wire run in metal 3 If the cursor is over another object when the right button is released the new wire attaches to that object If there are multiple objects under the cursor press the space bar while the right button is pressed to cycle through the possible endpoints including the possibility of connecting to none of them To prevent the wire from connecting to anything under the cursor hold the control key while routing If an Unrouted arc is attached to the original node that arc moves to the new pin This allows you to replace Unrouted arcs incrementally one segment at a time When both ends of the Unrouted arc are replaced by a segment that arc is removed See Section 9 6 1 for more about Unrouted Arcs Two Point Wiring The other way that the creation button can operate is two point wiring in which two nodes are highlighted and one or more arcs are created to connect them Highlighting of these two nodes is done by clicking the left button over the first one and then using the shift eft button on the second Note that if the second node is obscured by other objects you can cycle through the objects under the cursor with the control shift left button Once the two nodes are highlighted use the right button to wire them toge
160. agonal array array is laid out backwards replications are Draw Apply placed in the reverse direction Generate array indices ces P Only place entries that are DRC correct There are four ways to specify spacing edge overlap centerline distance essential bounds spacing or measured distance The edge overlap amounts indicate the amount by which the rows and columns will be squeezed together zero overlap causes the each arrayed copy to touch the next one negative overlap can be specified to spread the objects apart Centerline distance is the distance between object centers and defaults to the size of the selected objects which causes the copies to touch Essential bounds is a size that is set for set for specific cells by placing two or more Essential Bounds nodes in the cell see Section 7 6 3 If a cell with essential bounds is arrayed that value can be used Finally the last measured distance can be used to determine the array spacing for more on measuring see Section 4 7 4 I Transpose placement ordering Checkboxes at the bottom of the dialog are special cases e Linear diagonal array indicates that the array is linear one of the repeat factors must be 1 but that both spacing rules will be applied This therefore creates a single line that runs diagonally e Generate array indices requests that the array entries be drawn with index information When this is checked array entries are labeled with the in
161. ain example Join the ports with a universal arc Do not put this internal connection on any example other than the main one To see the location of all ports on the main example use the Identify Ports command in menu Edit Technology Editing For simple nodes such as pins and contacts there is typically one port which is in the center of the node However some of Electric s built in technologies give these ports a nonzero size The idea behind doing this is to allow arcs to slide within that port see Section 5 2 2 Many disagree with the idea of having nonzero ports on pin nodes and so it is now recommended that all pin nodes have zero size ports As with arcs use the Identify Primitive Layers command to label each piece of geometry in the main example Node Variations It is sometimes the case that two or more primitive nodes are nearly the same and differ only by the shape of their layers When this happens it is possible to define them all in the same cell using the notion of variations To create a variation on a node create a 5th example in the cell for two variations create a 5th and 6th example Each variation example must follow these rules e It must have the same layers as the main four examples Functan cantac Variations are not able to add or remove layers this is done by SepenGne kans tar No creating separate nodes Caua naama hv de with 1 or 2 arcs Na e A central node must be named Pick any piece o
162. ake the More Apply Enei x le 12 and click Length N 20 Using the Electric VLSI Design System version 8 11 Chapter 1 Introduction X Next we need a contact Choose a Metal 1 N Active Con to connect the N Active to Metal 1 Make its size be 5x12 instead of the default 5x5 Notice that contacts are smart about the cuts and add them to fill the node Note also that the port the inner rectangle grows with the node N Designers who have used polygon based systems will be tempted to move these two nodes together so that they form the desired structure X THIS IS WRONG Electric is a connectivity oriented system and insists that these components be wired together N The easiest way to connect the contact to the transistor is to spread the nodes apart wire them and then push them back together These two figures show the transistor and contact nodes spread apart and connected by an arc Using the Electric VLSI Design System version 8 11 21 Chapter 1 Introduction On the left the nodes and their ports on the right the arc The arc was made by selecting one node clicking and HOLDING the right button dragging the mouse over the other component and then releasing the button to create the arc Notice that the ends of an arc are centered and indented from the edge by half of the arc s width the ends are illustrated by on the right The ends of an arc must sit i
163. alog allows you to examine and modify the spacing limits for the current technology Each rule has a numeric value size or distance as well as a textual description of the rule The dialog is divided into two parts Node Rules and Layer Rules Export Import Reset All Only resets USER Preferences Apply Reset Help Not connected E 7 2 Mosis SUBM Edge Wide rules Distance Rule Rule 1 x B 7 4 Mosis SUBM IF Width gt fioo and Length gt Delete Wide Rule Add Wide Rule j Multiple via cuts Distance Rule gt PO Poo oo Cancel E Min resolution fo o1 use 0 to ignore resolution check In the Node Rules section you may set the minimum size of each node in the current technology 264 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools In the Layer Rules section you may set the minimum size area and enclosure area of each layer You may also set the inter layer spacing between the From Layer and the To Layer Use the Show only to entries with rules to restrict the displayed rules to those with valid values The layer to layer spacing rules appear in 3 forms normal wide and multicut Normal rules come in three flavors connected unconnected and edge The connected rules apply to pieces of geometry that are electrically connected the unconnected rules apply to unconnected geometry edge rules apply to uncon
164. als associated with it A simulation node can have 3 values L H or X and can have 4 strengths off node gate and VDD in order of increasing strength It is thus a 12 state simulator In deciding the state of a simulation node at a particular time of the simulation the simulator considers the states and strengths of all inputs driving the node Input Vector User Driving inputs may be from other simulation nodes in which case the driving strength is gate i e H gate indicates a logic HIGH state with gate driving q Strength from a power or ground supply VDD strength or from the user any strength If no user vector has been input at the current simulation time then the input defaults to the off strength H gate SUM out L gate in2 In the above example the combination of a high and a low driving input at the same strength from the signals out and in2 result in the simulation algorithm assigning the X undefined state to the output signal represented by q This example also shows the behavior of part of the simulation engine s arbitration algorithm which dictates that an undefined state exists if a simulator node is being driven by signals with the same strength but different states providing that the strength of the driving signals in conflict is the highest state driving the node Another important concept for the user to remember is that the simulator is an event driven simulator When a si
165. an also change the appearance of the export by editing the size font color style anchor point and rotation of the name See Section 6 8 1 for more about text appearance See Section 6 8 4 for smart export text control Using the Electric VLSI Design System version 8 11 69 Chapter 3 Hierarchy Special buttons in the Export Properties dialog allow you to examine related objects The Highlight Owner button shows the node on which this export resides You can change the characteristics of many exports at once by selecting them and using the Object Properties command in menu Edit Properties This multi object dialog has popups that will change all export characteristics at once You can change the name of exports by using the Rename Export command in menu Export Displaying Ports and Exports Ports and exports can be displayed on the screen in many different ways To control this use the Ports Exports Preferences in menu File 5 Ports Exports USER Preferences Preferences Display section Display Control Ports Exports tab E n Or p j Layers Toolbar i i Ports in instances Exports in cells The dialog offers three options for ports and Text exports Full Names shows full text names Smart Text Full Names Full Names Grid Short Names shows port and export names Ports Exports Short Names C Short Names only up to the first nonalphabetic character and Crosses shows crosses at
166. an attribute LEGATE which is set to 1 e The cell has only one output which may have a logical effort attribute explained below e The cell has zero or more inputs bidirectional ports Each of these must have a logical effort attribute explained below e The cell has an attribute whose name does not matter but whose value is LE getdrive and whose code is set to Java 330 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools X INV P to N width ratio Is 2 to 1 X le 1 Delay 100 le 1 X LE getd riv e ores ll X is drive strength LEGATE 1 On the input and output exports of the cell we can define an attribute named le use the Add LE Attribute to Selected Export command in menu Tools Logical Effort to add this attribute The value of this attribute is the logical effort of that port For example a NAND gate typically has a logical effort on each input of 4 3 and an output logical effort of 2 An inverter is defined to have an input logical effort of 1 and an output logical effort of 1 The size assigned to the logical effort gate is retrieved via the LE getdrive call This value can then be used to size transistors within the gate The size retrieved is scaled with respect to a minimum sized inverter as are all other logical effort parameters So a size of 1 denotes a minimum sized inverter While these attributes are defined on the layout or schematic cell defini
167. ances are actually nodes just like the primitive transistors and gates By defining exports inside of a cell these become the connection sites or ports on instances of that cell A collection of cells forms a library and is treated on disk as a single file Because the entire library is handled as a single entity it can contain a complete hierarchy of cells Any cell in the library can contain instances of other cells A complete circuit can be stored in a single library or it can be broken up into multiple libraries 10 Using the Electric VLSI Design System version 8 11 Chapter 1 Introduction 1 7 The Display The Electric display varies from platform to platform The image below shows a typical display with some essential features D Electric jet File Edit Cell Export View Window Tool Help ABr YQ BN A omw A R E et el ee NONE Components Explorer Layers REE LIBRARIES noname Current A JOBS T ERRORS No cell in this window Electric Messages NOTHING SELECTED TECH mocmos scale 200 0nm foundry Mosis The editing window is the largest window that initially says No cell in this window this indicates that no circuit is being displayed in that window You can create multiple editing windows to see different parts of the design Using the Electric VLSI Design System version 8 11 11 Chapter 1 Introduction Components Explorer Layers mocmos The left side of the edit
168. and tell IRSIM to use it In addition to the parameter file you can select the simulation model that IRSIM uses The default is a RC model but a Linear model is also available Export Reset ik Help Cancel gu Simulators USER Preferences For all Built in Simulators V Resimulate each change I Auto advance time P Multistate display jm Model RC X IRSIM Parasitics Parameter file Set IRSIM Debugging Event Scheduling J Final value Computation I Tau Delay Computation I TauP Computation Spike Analysis Tree Walk IRSIM Control Show IRSIM commands NV Use Delayed X Propagation Advanced users who edit their own command files may enter specialized IRSIM debugging commands These commands depend on a set of flags to determine the type of debugging to do Checkboxes in the IRSIM Debugging section control these debugging flags 284 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools The bottom section has two miscellaneous IRSIM controls e Show IRSIM commands requests that the system display the command file instructions as they are applied during simulation e Use Delayed X propagation does less conservative but potentially more accurate calculation of the time required to propagate an undefined X value in the circuit This improved propagation delay calculation has been shown to be effective in asynchronous circuits 9 5 2 ALS Electric has a built in gate
169. and are no longer recommended elib is a binary format and txt is a text readable format Electric can still read and write these files but support for them is limited and for legacy use only JELIB files are text readable files Each line of a JELIB file starts with an identifying character that distinguishes the line Blank lines and those that start with the comment identifying character are ignored There is no limit to the length of a line of text After the identifying character at the start of a line there are a set of fields All of the fields are separated by the separator character except for the first field which begins immediately after the identifying character No blank spaces are allowed on a line that is any blank spaces are treated as valid characters Control characters such as the identifying characters must be upper case In order to insert a l or n or r into a field it must be enclosed in the quotation mark characters Backslash character can be used inside enclosed strings to denote special characters Characters Meaning n line feed character n r carriage return character r quotation mark character backslash character Each of the different types of lines in the file has a fixed set of fields that must appear Some line types also allow additional fields at the end to add variables attribute value pairs see Section 10 4 1 The JELIB file has 3 parts th
170. and the perpendicular arc will keep the circuit connected Perpendicular Beginning users often leave many extra pins in their circuits With the Cleanup Pins command in menu Edit Cleanup Cell these pins are automatically removed from your circuit leaving a cleaner network The command does other pin organizations such as making sure that text on these pins is located correctly identifying zero sized pins and identifying oversized pins The Cleanup Pins Everywhere command does this function for all cells at once 50 Using the Electric VLSI Design System version 8 11 Chapter 2 Basic Editing 2 3 Circuit Deletion To remove circuitry select nodes and or arcs and use the Selected command in menu Edit Erase A keyboard shortcut for this is the Delete key If there is a highlighted area rather than a highlighted object everything in the area is erased Note that an arc always connects two nodes and therefore it cannot remain if one of the nodes is gone This means that certain rules apply to circuit deletion e When a node is erased all connecting arcs are also deleted However if a node is deleted that has exactly two arcs connected as though the node were in the middle of a single arc then the node and two arcs are replaced with a single arc Circuit Higher level Cell In the interest of cleanliness NY l 5 NS if an arc is erased any isolated pins are also erased e If an erased node has an export o
171. anels each with one or more signals and waveforms In a panel signal names are shown on the left and their waveform on the right Above the signal names in each panel are 5 names and controls e Panel number each panel is numbered so that it can be hidden and retrieved Close an X to remove the panel from the waveform window e Hide to stop displaying the panel but keep it available it can be restored by selecting its name from the popup at the top of the waveform window e Remove Signal remove the selected signal from the panel the DELETE key works for this too e Remove All Signals remove all signals from the panel The command Clear All Signals in Waveform Window in menu Window Waveform Window removes all waveform panels from the display You can select a signal by selecting either its name or the actual waveform Note that when you click on a signal the equivalent network in the associated schematic or layout window is also highlighted If a Spice deck was generated from the schematic then crossprobing its simulation results to layout may not work properly This can be fixed with the Run NCC for Schematic Cross Probing command in menu Tools NCC see Section 9 7 2 You can change the color of a signal by right clicking on its name and choosing a different color You can rearrange the order of the waveform panels by clicking on their panel number and dragging the panel to a new location You can move signals from
172. ant h Selection and movement wiring and zooming are done in selection mode which is the default mode This mode is indicated by having the selection icon highlighted in the tool bar Selection is done with clicks of the left button Individual nodes and arcs are selected by clicking over them You can tell in advance what will be selected by the button click because the next object to be selected is shown in blue This advance selection is called mouse over highlighting and can be disabled see Section 2 1 4 Once selected objects are highlighted on the screen If you use the shift left button unhighlighted nodes and arcs are added to the selection but objects that are already highlighted become deselected There are often multiple objects under the cursor for example in the area where an arc overlaps a node To get the object you want hold the control key while clicking The control left button cycles through all objects under the cursor The notion of toggling selection shift left and cycling through what is under the cursor control left can be combined If there are multiple objects under the cursor and you are trying to toggle the selection use the control shift left button to cycle through them Select Object xi Nodes C Exports To select an object by its name use the Select Object command in menu Edit Selection The resulting dialog lets you select nodes arcs exports or networks in the
173. ant box information however it is faster to generate and uses simpler constructs If you check this box all connecting regions on the same layer are merged into one complex polygon This requires more processing produces a smaller file and generates more complex constructs Output Instantiates Top Level controls whether or not to instantiate the circuit in the CIF By default the currently displayed cell becomes the top level of the CIF file and is instantiated at the end of the file This causes the CIF file to display the current cell If however the CIF file is to be used as a library with no current cell then uncheck this box and there will be no invocation of the current cell Output scale controls the scaling factor used in cell headers when writing CIF Be advised that the CIF format has a minimum resolution of 10 nanometers Since nothing smaller can be accurately represented in the file the CIF output of smaller geometries will generate errors The workaround is to set a large scale here which will cause all numbers in the CIF file to be scaled by that amount and then divided by that amount in the cell header The resulting CIF will be the same size but it will be able to represent smaller values User Preferences There is just one User Preference Input Squares Wires When reading CIF files the CIF wire statements are assumed to have rounded geometry at the ends and corners If you check this box CIF input assumes that
174. aol EE zoom factors The X Center and Y Center fields are the database coordinates of the center of the screen The Horizontal Grid Units field is Horizontal Grid Units 58 556 the number of database grid units across the screen Cancel Center All Using the Electric VLSI Design System version 8 11 99 Chapter 4 Display 4 5 The Sidebar 4 5 1 The Component Menu The component menu shows the nodes and arcs of the current technology The Components l Explorer Layers popup menu at the top lets you change the current technology and see its nodes mocmos M and arcs In the component menu nodes have a blue outline and arcs have a red outline To place a node in the current cell click on its entry and then click again in the cell to place the node If you type or before clicking to place the node then the rotation of the placed node changes To select a default arc for wiring click on its entry note that the default arc has a heavier red outline Some node entries in the component menu have multiple nodes in them as indicated by a black arrow in the lower right corner Clicking on the arrow shows a menu of possible nodes to create Once selected that node becomes the default for the menu entry Special component menu entries with text in them are provided for special functions e Pure places pure layer nodes see Section 6 10 1 e Misc places unusual nodes see Section 2 2 1 e C
175. asic Editing 2 4 2 Other Modification Node Properties xi Another way to move a node is to use the Object Type N Transistor Properties command in menu Edit Properties aie fimose and type new X and Y positions This dialog allows other modifications to be made as well orientation width E X position 11 etc Lenath 2 position jp The dialog shows the location of the anchor point of Rotation fo Mirror L R Mirror U D the node More Apply Cancel The dialog also has a field for the node s name This name is not related to network information but it must be unique and can be used for identification If a schematic node is given an arrayed name such as and 0 3 then it indicates that the node is arrayed that many times Nodes and arcs are automatically given unique names when first created such as nmos 0 Node Properties xi Type JatchAAlay Name atch44 o The Object Properties dialog is modeless 5 fo X position 228 5 it can remain on the screen while other MET fe positon po editing is being done If a different node is selected the dialog updates to show that Rotation 0 Mirror L R Mirror U D node s information The Apply button Less Apply Cancel changes the selected node to match the a pe am new values typed into the dialog C Expanded Unexpanded V Easy to Select J Invisible Outside Cell The Object Properties dialog can also expand to show more informa
176. ated at that point and connected to the port e Abort Type ESCAPE to abort the current operation Using the Electric VLSI Design System version 8 11 13 Chapter 1 Introduction 1 9 The Keyboard Key Bindings USER Preferences C General General Many common commands can be Selection Cell New Cell ctrl N invoked by typing quick keys for Key Bindings Cell Edit Cell them These quick keys are shown in Nodes Cell Place Cell Instance N h ild he i Cell Rename Cell the pulldown menus next to the item i P Project Management Cell Duplicate Cell For example the New Cell cys Cell Delete Cell command in menu Cell has the i Printing Cell Multi Page Cells quick key Control N On the Macintosh the menu shows N indicating that you must hold the command key while typing the N Cell Down Hierarchy on Windows and UNIX systems the Cell Up Hierarchy menu shows Ctrl N indicating C Cell Cell Viewing History pe a ae hold the Commorkey Cell New Version of Current Cell while typing N There are also i Cell Duplicate Current Cell unshifted quick keys for example gt the letter n runs the Place Cell Instance command Add Apply Remove Reset To change the bindings of quick keys use the Key Bindings Preferences in menu File Preferences General section Key Bindings tab The dialog shows the hierarchical structure of the pulldown
177. ater time e Window Special Pan Center Cursor shifts the time so that the location of the cursor is in the center this command is only sensibly executed by using its quick key binding e Pan tool in tool bar freehand drag of time e Zoom tool in tool bar drag area to zoom in hold shift to zoom out e Measure tool in tool bar for measuring time see Section 4 7 4 Stimuli for Built in Simulators only When the waveform window displays the output of built in simulators you can set stimuli on the signals to affect the simulation Each stimulus that you set is marked with a large red box at the time of the stimulus see signals cc and in You can select the stimuli by clicking on the red box A selected stimulus has a green box in it see the rightmost stimulus on signal in Using the Electric VLSI Design System version 8 11 127 Chapter 4 Display To set stimuli select either a waveform or the equivalent network in the original schematic or layout Once selected use the Set Signal High at Main Time in menu Tools Simulation Built in to make that signal go to high at the time indicated by the Main cursor Use Set Signal Low at Main Time to set the selected signal low and use Set Signal Undefined at Main Time to set the selected signal undefined X Use the Get Information about Selected Signals command to show stimuli and other information on the selected signals To remove the selected stimulus u
178. ating new technology nocmos be used to install the technology permanently If a Already a technology with this name technology already exists with the name you want you can a f Rename existing technology to request that it be renamed or you can choose a different name for the new technology Also write XML code Cancel If there is an error in the library conversion is aborted and you are given a chance to fix the library Generally the offending part of the library is highlighted If no errors have occurred in the translation there will be a new technology in Electric and it will be the current one Before creating any circuitry with the new technology it is advisable to create a new library use the New Library command of menu File so that the test circuitry is not stored with the library that describes it 218 Using the Electric VLSI Design System version 8 11 Chapter 8 Creating New Technologies Once a technology has been created you can make it a permanent part of Electric by adding its XML code to the system Added Technologies PROJECT Preferences Categories Technologies that will be added to Electric when it next runs General This is done with the Added these are XML files created by the Technology Editor in o Technologies Preferences in E menu File Preferences Tools i une Technology Technology section Added o RGR Lechnologies tab Use the Export I
179. ation Others Write SILOS Deck Spice circuit Tools Simulation Spice Write Spice Deck T For more control of netlist generation see Section 3 9 3 C C E R For more information on Spice see Section 9 4 3 for Verilog see Section 9 4 2 and for FastHenry see Section 9 4 5 Using the Electric VLSI Design System version 8 11 269 Chapter 9 Tools 9 4 2 Verilog Electric can produce input decks for Verilog simulation with Write Verilog Deck command in menu Tools Simulation Verilog After this has been done you must run Verilog externally to produce a dump file Note that the Electric distribution does not come with a Verilog simulator you must obtain it separately After running a Verilog simulation you can read the dump file into Electric and display it in a waveform window This is done with the Plot Verilog VCD Dump command in menu Tools Simulation Verilog You can also use the Plot Verilog for This Cell command if the cell name and file name are the same The Verilog simulation information is then shown in a digital waveform window see Section 4 11 1 for more Electric also understands the output of Modelsim and can plot it Before generating Verilog decks it is possible to annotate circuits with additional Verilog text that will be included in the deck To add Verilog code to this cell select Verilog Code under the Misc entry in the component menu of the side bar
180. ation fo v Highlight Owner Invisible outside cell center of the attached object Anchor centered Boxed width 4 height fez e Rotation is in 90 degree increments only DEFAULT EOW EI e Anchor is the point in the Color DEFAULT COLOR text that remains unchanged see Section 6 8 2 Code Not Code e Font can be the default font Units none X or any font installed on your Show vaes o SY system e Color can be any color Cancel e Bold Italic and Underline can be set in any combination These additional factors can be controlled e Code allows the text to be code in an interpretive language in which case the evaluation of that code is displayed The code choices are Not Code the text is taken as is Java the text is handed to a Java interpreter for evaluation For example the expression Math abs 4 5 will be converted to 20 Spice the text is handled as a Spice expression Spice allows simple expressions and Electric is able to evaluate them These expressions are not as powerful as Java One advantage of Spice code is that the Spice deck writer can send them unevaluated to the Spice deck e Units can be any electrical type capacitance resistance etc See Section 7 2 2 for more on units e Show allows you to show the text value the name of the piece of text or both 156 Using the Electric VLSI Design System version 8 11 Chapter 6
181. ation and other formatting of all inserted text e Parameterize Verilog module names causes Verilog deck generation to create multiple Verilog cell descriptions when the cells are parameterized e Write Separate Module for each Icon requests that schematic cells with multiple icons be written multiple times to the Verilog deck once for each icon variation This preserves the hierarchical structure of the circuit but creates duplicate modules A final set of Verilog controls can be found in the Verilog Model Files Preferences in menu File Preferences Tools section Verilog Model Files tab The Verilog Model Files Preferences dialog lets you attach disk files with Verilog code to any cell in the library 272 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools Once attached the generated Verilog verilog Model Files USER Preferences Spice Spice Model Files Verilog Verilog Model Files otherwise incorrect will use the contents Antenna Rules of that file instead Compaction of examining the Coverage DRC cell contents This Fast Henry Derive Model from Circuitry allows you to create Logical Effort fete onley your own NCC definitions in Network C Use Model from File Browse situations where the Parasitic j derived Verilog i Aena outing would be too Silicon Compiler complex or Simulators amp e o e b Export Import Reset Reset All
182. attention to the dimensions of the icon the overall design will look more readable if icons are of consistent sizes 36 Using the Electric VLSI Design System version 8 11 Chapter 1 Introduction To edit the icon click on it and use the Down Hierarchy command in menu Cell Down Hierarchy or just type Ctrl D The Component tab will now show with various shapes this is the Artwork technology Delete the generic black box but leave the input and output wires Turn on the grid The body of the NAND is formed from an open C shaped polygon a semicircle and a small negating circle To form the semicircle create an unfilled circle node Double click to change its size to 6x6 and to span only 180 degrees of the circle Use the rotate commands under the Edit menu to rotate the semicircle into place Place another circle adjust its size to 1x1 and move it into place Alternatively you can type h and use the arrow keys to move objects by 1 2 grid increments then press f to return to full grid movement The Opened Polygon node can be used to form the C shaped body When first created it appears as a zigzag shown here To manipulate its shape select it and enter outline edit mode by using the Toggle Outline Edit command in menu Edit Modes Edit or just type y or click on the icon in the toolbar In this mode you can use the left button to select and move points and the right button to create points Since the default Op
183. ayer is highlighted in the list on the left and shown in red in the right hand view Change the 3D HIGHLIGHTED INSTANCES entry in the Layers Preferences to change the color used for highlighting layers in the 3D view and in the preferences Preferences Preferences C General Display Display Control Component Menu Layers Toolbar Text Smart Text Grid Ports Exports Frame Las ds a a a E 8 1 0 Tools F Technology Import Reset All Only resets USER Preferences Apply Export Reset Help Cancel Using the Electric VLSI Design System version 8 11 3D USER Preferences Layer cross section for technology mocmos Transparency Options Factor jo z Mode NONE x IV Use Perspective IV Cell Bounding Box Use Antialiasing P Show Axes Max Nodes 1000 Alpha 20000 Initial Transformation Initial Zoom fi Rotation Xx fo fi Rotation Y fo Rotation Z fo z Scale Light Information IV Enable Light 1 V Enable Light 2 x fio x fio vho wf Z fio Z fio 121 Chapter 4 Display The distance of the layer from the wafer bottom and its thickness are the most important values These values are not only used for the 3D view they are also used whenever layers are presented in height order Once selected you can type new values into the Thickness and Distance fields By default a perspective view i
184. bol in the Components tab on the left side of the screen Then click in your schematic window to place the transistor in the circuit perform this as two separate clicks not drag and drop Repeat until you have two nMOS transistors two pMOS transistors the Power a symbol and the Ground symbol arranged on the page nand2 These symbols are nodes in Electric parlance You may move the nodes around by clicking and dragging The transistors default to a width length value of 2 2 Double click on the pMOS transistor and change its width to 12 Recall that nMOS transistors are roughly twice as strong as pMOS transistors So a single nMOS transistor would only have to be 6 wide However because the nMOS transistors are in series they should also be 12 wide Now connect the nodes with wires called arcs in Electric parlance Notice that when you click on a node the closest port is also selected These ports are the sides of arc connections Click on a port such as the gate source or drain of a transistor Right click hold the mouse and drag away from the node When you release the mouse an arc will be created from the original node to the location of the cursor A new pin node will also be created at the cursor to hold the other end of the arc If you right click and drag over an existing node then you will connect to it If two objects to be connected are not lined up Electric will create two arcs to join them The location of the
185. cal portrait You For Textual Cells can choose to Font DEFAULT FONT v Size 12 display a title box in the Cell Frame lower right Landscape one The Size None M Title Box designer name Portrait can also be set Designer Name _ for each cell dec sch die aml fied x Cancel Besides the designer name cell frames have a company name and a project name These values are not set for each cell but instead are preferences that are set for each user Individual libraries can override these defaults as well e Using the Electric VLSI Design System version 8 11 207 Chapter 7 Technologies The Frame Preferences in menu File Categories Preferences General Display section Display Frame tab lets you Display Control set all of these ee Monu defaults Note that the Toolbar designer name is taken Text first from the cell then Smart Text from the library if the Grid Library default Ports Export General default tet J cell does not set a orts Exports value and finally from ee 3D Company Name Static Free Software ie nal Gokai Designer Name Steven Rubin the library and cell do Tools not set a value Technology Project Name Import Reset All Only resets USER Preferences Help Apply Cancel Frame USER Preferences amp g I H E ca fa i D m EE a E gu 208 Using the
186. cale by This scales the GDS by the given factor when read from disk User Preferences These dialog elements are available on the right side the GDS User Preferences Merge boxes slow This requests GDS input to combine overlapping boxes into complex polygons It takes more time but produces a more compact database Include text Text annotations in the GDS file can often clutter the display so they are ignored during input If you check this item annotation text will be read and displayed Expand cells This controls whether cell instances are expanded or not in the Electric circuit By default cell instances are not expanded they appear as a simple box If you check this item cells are expanded so that their contents are displayed Expansion of cells can always be changed after reading GDS by using the subcommands of the Expand Cell Instances and Unexpand Cell Instances commands of the Cells menu Simplify contact vias This requests GDS input to find combinations of metal and via cuts and replace them with Electric contacts It takes time and may simplify some GDS Use NCC annotations for exports The network consistency checker NCC allows special circuit annotations to join two networks see Section 9 7 4 For example two separate power networks Using the Electric VLSI Design System version 8 11 193 Chapter 7 Technologies 194 may be joined higher in the circuit hierarchy and the NCC needs to know thi
187. cation and thickness in the third axis out of the screen For example to show how poly and diffusion interact the poly layer can be at height 21 and the diffusion layer at height 20 both with O thickness This will appear as two ribbons one over the other See Section 4 10 2 for more information on 3D display The last option on the right side of the layer cell specifies the minimum coverage percentage see Section 9 2 4 for more 222 Using the Electric VLSI Design System version 8 11 Chapter 8 Creating New Technologies Layer Function The Function entry allows a general purpose description to be attached to the layer Change Layer Function xi A function consists of a single base description plus optional additional modifiers The additional modifiers are found in the LEE Me cols last entries of the function list Cancel These additional modifiers can be added to the base function wou n e p type n type depletion that are process specific e pseudo indicates that this layer is a pseudo layer used for pin construction e nonelectrical indicates that this layer is decorative and not part of a real circuit e connects metal connects poly and connects diff indicate that this contact layer joins the specified real layers e inside transistor indicates that the polysilicon is not field poly but is part of a transistor enhancement light heavy and thick describe la
188. ch by name but are not on equivalent networks have red hyperlinks Such exports might have suggested matches as well which are printed in green In the first row of the table below the jtag 1 export in the schematic does not topologically match the jtag 1 export in the layout but does match the jtag 8 export in the layout acvernierxandy_fullyernier_ 0x1 4ndsch acvernierxandy_fullyernier_ 0x1 4ndlay jtag t chtagti jtagl8 jtag 1 jtagl2 jtag 7 Exports that match by name but are not on equivalent networks have red hyperlinks Parts and Wires NCC finds mismatches by applying two partitioning techniques in sequence First it uses local partitioning and then it uses hash code partitioning If local partitioning finds mismatches then NCC reports only those The mismatches in local partitioning of parts and wires are grouped under nodes with names Parts X and Wires X where X is the number of mismatched local partitioning classes see figure below Each class node represents a class of parts or wires sharing the same local characteristics Using the Electric VLSI Design System version 8 11 313 Chapter 9 Tools Parts Parts are partitioned into equivalence classes based upon their type and the number of wires attached to them The figure below shows a list of two part classes Mismatched Comparisons 1 4 Part s in mipscells bitslice sch 3 Part s in mipscells bitslice lay mipsce
189. chematic and determines the optimal transistor size to use in order to get maximum speed The tool is based on the book Logical Effort by Ivan Sutherland Bob Sproull and David Harris Morgan Kaufmann San Francisco 1999 It is highly recommended that the user be familiar with the concepts of this book before using the Logical Effort Tool Logical Effort PROJECT Preferences E Tools Antenna Rules Compaction Coverage DRC Fast Henry Global Fan Out step up 4 7 To control Logical Convergence epsilon 0 0010 Effort use the Logical ei AE Dae ee ee Effort Pre ferences in aximum number or iterations menu File Keeper size ratio keeper size driver size b i Preferences Tools section Logical Effort Placement tab This lets you m Tech specific Routing zl control a number of For Technology mocmos z Export meni settings for Logical Effort analysis Gate capacitance FF Lambda fo 167 Reset Reset All Only resets USER Preferences Default wire cap ratio Cwire Cgate fo 16 Help Apply _ Diffusion to gate cap ratio alpha 0 7 Cancel NCC Network IV Use Local cell LE Settings Parasitic e eeee a E a 6 amp if gu Logical Effort Gates A design that is intended to be analyzed with Logical Effort must be composed of special Logical Effort gates A Logical Effort gate is simply a schematic or layout cell that conforms to the following specifications e The cell has
190. ching yyy 34 Using the Electric VLSI Design System version 8 11 Chapter 1 Introduction Once the contacts are connected to the transistors you will need a gap of only 1 unit between the metal and polysilicon Use the design rule checker to ensure you are as close as possible but no closer Using similar steps draw two pMOS transistors in parallel and create contacts from the P diffusion to Metal 1 At this point your layout should look something like this Draw wires to connect the polysilicon gates forming inputs a and b and the Metal 1 output node y Then add Metal 2 power and ground lines You can create these Metal 2 wires by creating a Metal 2 Pin node and right clicking on it to draw a wire Use the grid to make sure that the Metal 2 wires are 80 units apart This is the same spacing as the power ground lines of the inverter Note that when two objects are selected the Properties dialog box Ctrl D also tells the distance between them A via called Metal 1 Metal 2 Con is required to connect the Metal 1 to the Metal 2 lines Select an active contact and right click to connect it to the ground line Electric will automatically create the necessary via for you while making the connection Complete the other connections to power and ground Let power and ground extend 2 units beyond the contents of the cell excluding wells on either side so that cells may snap together with their contents se
191. chnologies project settings of the technology The first Via Once installed in Electric the technology can panel that appears General Antenna be Further edited with the Technology Editor describes the wizard and GDS j Use Save Parameters to save these values requests some basic Use Load Paramerers to restore saved values information The Unit size is the number of nanometers per grid square The Resolution is the smallest Unit size rim feature size allowed The Load Parameters Write XML Resolution nm Psubstrate process controls 7 Psubstrate process well generation The EeP iE IV Horizontal transistors Horizontal transistors controls the orientation of transistors The values in these panels can be saved to disk with the Save Parameters button and restored from disk with the Load Parameters button When all parameters have been filled in use the Write XML button to generate an XML file for the technology This file can then be installed into Electric with the Added Technologies Preferences panel see Section 8 2 for more Technology name Description 252 Using the Electric VLSI Design System version 8 11 Technology Creation Wizard x Technology Parameters General Contact well Implant Metal via Antenna GDS eeeeeeeee Load Parameters Write XML Save Parameters The Poly panel lets you specify size and spacing values for the Polysilicon layer
192. com productsLibraries html 78 Using the Electric VLSI Design System version 8 11 Chapter 3 Hierarchy 3 9 2 Reading Libraries The Open Library command in menu File brings a new library into Electric from disk These libraries may have the extension elib jelib or delib the jelib format is the default see Section 10 1 There is also a Open Recent Library entry that lists all recently opened libraries B You can also use the open library icon from the tool bar Electric users with very old elib files may have difficulty reading them into Electric If you have been using versions of Electric prior to 7 00 it may help to upgrade to that version and read the libraries Saving elib files from version 7 00 will work properly in the current system By default Electric searches for libraries in the working directory absolute file path references and Electric s internal library directory Users can specify additional directories to search by using a file called LIBDIRS placed in the working directory This file specifies additional paths to search for library files The file has the following syntax lt comments gt include lt another_LIBDIRS_file gt lt library_directory gt Paths may be absolute or relative Besides Electric libraries it is possible to read circuit descriptions that are in other formats with these commands in the File Import menu e CIF Caltech Intermediate Format is used to desc
193. connected the node automatically expands adding additional space along the side for new arcs To properly wire inputs to an And Or Xor or Multiplexor node cursor placement is very important for it determines which of the locations to use on the left side If an arc gets connected in the wrong location try connecting more arcs until one appears in the right place and then delete the unwanted ones The Switch node can also take an arbitrary number of poles on its left side Simply stretch it along the line of the poles and their number will grow Analog Schematics The analog nodes Resistor Inductor Capacitor and Diode have values on them which can be selected and edited Double clicking on them brings up a special dialog for editing their value The Resistor can be treated as a connecting or nonconnecting node By default it does not connect the networks on its two ends and this is the correct way to treat it when doing low level simulation such as Spice However for higher level simulations such as Verilog the resistor should be ignored and treated as if it connects its two networks To make this happen use the Networks Preferences in menu File Preferences Netlists tab and check Ignore Resistors when building netlists Note that if resistors are being ignored Spice deck generation will temporarily include them while the netlist is being created 206 Using the Electric VLSI Design System version 8 11 Chapte
194. create a cell called adder ic that contains a circle with a plus sign inside these are nodes in the Artwork technology This is then the icon for the contents cell adder sch Now if you create an instance of the schematic cell the icon cell will actually be placed because it is the symbol that gets used for instances To generate an icon cell automatically use the Make Icon View command in menu View Be sure to create all relevant exports before issuing this command so that the proper icon can be constructed Note that any export that has its Body only attribute checked will be omitted from the icon To control the look of the icons use the Icon Preferences in menu File Preferences Technology section Icon tab Icon USER Preferences C General a fig Display Rules For automatic icon generation rs 10 Export location Tools Place by Characteristic C Place by Location in Cell Technology Added Technologies Inputs on Left Side x Text rotated Top text rabeten Technology Outputs on Right Side Text rotated Bottom text rota Design Rules i Scale Bidir on Top Side x Text rotated LefEbeXt robeted Units Power on Bottom Side x Text rotated Right text rot i J Ground on Bottom Side x Text rotated p Use exact schematic location Clock on Left Side x Text rotated Place Exports in Reverse Alphabetical Order Body and Leads IV Drawleads Lead l
195. ct but that the implant regions are not N P distinct and must be derived from the active information Flatten cells whose names match this is a way to automatically flatten the hierarchy when extracting This is useful in situations where parts of a node are encapsulated in subcells For example some designers place all via layers into a subcell and construct all contacts with instances of these cells The node extractor does not examine subcells when extracting and so it will not detect the contacts By placing the subcell names into this field the extractor will extract those cells and find the contacts Note that wildcards can be used here Flatten Cadence Pcells requests that Cadence Pcells be flattened without having to list their names Cadence Pcells can be recognized by the fact that their cell name ends with and a number Using the Electric VLSI Design System version 8 11 337 Chapter 9 Tools 9 11 Compaction The compaction tool squeezes layout down to minimal design rule spacing It does this by doing single axis compaction alternating horizontal and vertical directions until no further space can be found Each pass of compaction squeezes either to the left or to the bottom of the circuit To compact use the Do Compaction command in menu Tools Compaction The Compaction Preferences in menu File Preferences Preferences Tools section Compaction tab B Tools Compaction USER Prefere can tell the
196. ctions of single signals that display integer values for example himb 1 10 To expand a bus and show its individual signals in separate panels double click on its name To contract the bus removing its individual signals double click on the bus name again Using the Electric VLSI Design System version 8 11 125 Chapter 4 Display Although the color of the waveforms is usually the same it can vary with the strength of the signal To enable such a display check Multistate display in the Simulators Preferences in menu File Preferences Tools section Simulators tab To control the actual colors used in multistate display use the Layers Preferences in menu File Preferences Display section Layers tab and set the colors for WAVEFORM OFF STRENGTH WAVEFORM NODE WEAK STRENGTH WAVEFORM GATE STRENGTH and WAVEFORM POWER STRENGTH see Section 4 6 2 You can select a signal by selecting either its name or the actual waveform A selected signal is highlighted and the selected panel is marked with a bold white line see the out signal above Note that when you click on a signal the equivalent network in the associated schematic or layout window is also highlighted more on this below You can rearrange the order of the signals by dragging their names to a new location You can add a new panel to the waveform window by double clicking on its name in the SIGNALS area or by dragging that name to
197. ctric VLSI Design System version 8 11 Chapter 7 Technologies 7 4 The MOS Technologies 7 4 1 Introduction There are both nMOS and CMOS technologies available in Electric with many different design rules Use the popup at the top of the component menu to select a different MOS technology There is one nMOS technology nmos the specifications used in the Mead and Conway textbook There are a few CMOS technologies available The most basic is cmos which uses an idealized set of design rules from a paper by Griswold The most popular CMOS technology is mocmos MOSIS design rules which has two layers of polysilicon and up to 6 layers of metal with standard submicron or deep rules this is described more fully in the next Section There is even rcmos which uses round geometry Each MOS technology has two transistors enhancement and depletion in nMOS technologies n and p in CMOS These nodes can have serpentine paths by highlighting them and using Outline Edit mode see Section 6 10 1 The contact nodes in the MOS technologies automatically increase the number of cut layers when the contact grows in size For very large contacts however the display of these cuts can waste time Therefore when very large contacts are displayed at small scale the interior cuts may not be drawn as shown on the right Be assured however that the cuts are actually there and will appear in all appropriate output Using
198. cursor determines the angle of the bend so wiggle it to see how the two arcs will run before releasing the button and creating the connection See Section 2 2 2 for more on arc creation When the schematic is wired you will need to create exports which define inputs and outputs of the cell From the Components tab select the Off Page symbol and place it in the circuit Connect the tip of the arrow the proper place in the circuit To make an export on the other side of the Off Page select that port and use the Create Export command in menu Export or just type Ctrl E Name the export a and define its characteristic as input Similarly create Off Page symbols and exports for b and y Now is a good time to save your library Use the Save Library command in menu File or just type Ctrl S Get into the habit of saving your library regularly Also learn the keyboard shortcuts for the commands you use frequently 1 12 3 Schematics and Layout Tutorial Layout Now that you have a schematic it is time to draw the layout Use the New Cell command in menu Cell to bring up the new cell dialog Enter nand2 as the cell name and layout as the view Notice that the Components change from schematic symbols to layout primitives The default technology is mocmos MOSIS CMOS but can be changed with the pop up menu at the top of the Components tab The mocmos technology has many options such as the number of metal layers To se
199. d but for contacts one is sufficient Select the PORT entry from the menu on the left and place it in the display You will be prompted for a port name N Active Disallowed z after which you can further move or stretch the port Besides a location and a P Active Disallowed name ports must specify which arcs may connect to them To do this i double click on the port Polysilicon 1 Angle The resulting menu lists all of the arcs and indicates possible connectivity Angle range 180 Note that the last two entries define the permissible range of angles to which No meaning arcs may connect For a contact such as this arcs may connect at any angle Transistor meaning No meaning so the default values are correct Cancel Metal 2 When all of the geometry highlighting and ports have been placed you can double check your work with the Identify Primitive Layers command in menu Edit Technology Editing which will display Polysilicon Highlight this information note that the port name Center has been moved nter away for clarity Contact Cut The final step in the definition of this node is to create three more copies that illustrate scaling in both axes This is done simply by selecting all five objects and using the Duplicate command in menu Edit Once duplicated in a new location each piece must be stretched appropriately In this example the contact cut is designed so that the number of cut elements grows
200. d into one network This means for example that two arcs each connected to a separate Ground node appear on the same network regardless of their actual connectivity in the circuit As a debugging aid for power and ground networks the command Show Power and Ground in menu Tools Network shows the entire power and ground network The Validate Power and Ground command checks all power and ground networks in the circuit Any power or ground networks that are named according to the prefixes listed above must have the proper characteristics If for example a power network is called gnd007 then it will be flagged by this command The command Repair Power and Ground changes the characteristics where necessary Many designs require multiple power and ground rails Electric allows additional power and ground signals through the use of the Global node see next Section 6 9 5 Global Networks When wiring an IC layout the only way to get a signal from one point to another is to physically place the wires Signals that span a large circuit such as power and ground must be carefully wired together at each level of the hierarchy In schematics however it is often the case that a signal is used commonly without explicitly being wired or exported Examples of such signals are power ground clocks etc The power and ground signals can be established in any schematic with the use of the Power and Ground nodes To create another such signal use t
201. d Thicker Dotted Close Dotted Far Dashed Short Dashed Long Dotted Dashed Short Dotted Dashed Long Dotted Close Thick Dotted Far Thick Dashed Thick Dotted Close Thicker Dotted Far Thicker The Style can also specify printer patterns PRINTER Solid and PRINTER Patterned When using solid styles the 16x16 stipple pattern is ignored except for hardcopy Transparent layers should be solid because they distinguish themselves in the color map Layers with opaque colors should probably be patterned so that their combination is visible Many of the entries on the right side of the layer cell provide correspondences between a layer and various interchange standards The CIF Layer entry is the string to use for CIF I O see Section 7 3 2 The GDS II layer entry can be as simple as a single layer number but it can also be two numbers separated by a the layer number and its type You can also add a comma and then another layer type pair with the letter t for text or p for pin at the end see Section 7 3 3 Another set of options on the right side of the layer cell is for Spice parasitics You may assign a resistance capacitance and edge capacitance to the layer for use in creating Spice simulation decks see Section 9 10 1 The 3D Height and 3D Thickness are used when viewing a chip in 3 dimensions The height and thickness are arbitrary values which describe the lo
202. d a e ea a a r a A a ellen 2 123 Runnin Electi epoi R E E a E ES e EE a E A aaa saa 3 1 4 Building Electric from Source Code esseeeeeseeeeeseeseeresserrstesesessesrestessertestentestesentestestesesseesese 5 EA a aa EES E E EE A AE T A 7 1 6 Fundamental once pts aenieei eea atteeth e E E a Naha E ea 8 T 7 Fhe Displayascri reio reaa aeniea E a Ta a ee Ge ce e ie 11 1 58 The MOUSE 2 noir a A BE EG a Ae 13 129 The KE yD Oar i n oee ee E eie A E eke dae eek g otek e a e a a lee e aa 14 1 1021 Layout T t ria hna enaae ohana lads e ee Mea ceed Wide a a a eE 17 Tell Schematics Tutorial inei en eera E E e a tiles etek satin E eTe petai Sss 26 1 12 Schematics and Layout Tut rial sessies ea E E E E eii 31 Chapter 2 Basic Editing lt iciccscccssssesccsseonscessevsnetssencceucstensessvecesnvesscesstencvonccocebessduuceasensvedeosenassoucosenvessesssasesssectes 41 2l Selecuon eiee sein eee E EE res Nara aye acai edi aint SE aeie RE 41 2 2 Circuit Creati onns iee aoea ane a E Ea a EEE Aa E aa eked a a ae 46 29 Circuit Deleon eneo e pasts ea laces EE E E E E E e E a e A 51 2 4 Crreust Modification sesionar a aeia a E a EEE e E A s 53 22S Changing SiE e e e eie Ar a EEN A E a a eect 56 2 6 Chanine Orienta Om sn aoreet eria iee ia dene hdl ea eee ee ee eed 58 Chapter 3 Hierarchy yicisssiccscsicsscssseccsssoeccecsevesnssseosvesecsuntesoanseosuessses sessevonwesveessssuaneueaveceetossaeeseueessavedessdssensewonss 59 SH Pe Cel E E
203. d cells Metal 5 33 64p 64t Export i DXF a Metal 6 37 68p 68t 5 3 SUE I Simplify contact vias Polysilicon 1 46 77p 7 I Output merges Boxes slow Lib ray F Use NCC annotations for exports Copyright I Output writes export Pins Tools Collapse YDD GND pin names ro Tackralac I Output all upper case IV Instantiate arrays V Output converts brackets in exports Export Import Array simplification None X Max chars in output cell name f32 Reset Reset All Unknown layers ignore v Output default text layer so Only resets USER Preferences IV Cadence compatibility Import Help Apply Scale by fi Bae Project Preferences The left side of the dialog shows the Project Preferences which control the mapping of GDS layer numbers to Electric layers The list on the left shows all of the Electric layers in the current technology By clicking on a layer name its GDS numbers are shown in the top right and can be edited In addition to GDS numbers to 192 Using the Electric VLSI Design System version 8 11 Chapter 7 Technologies use for layout there are also two other types of GDS numbers pin for exports and text for export names To ignore a layer clear the layer field it is not sufficient to set it to zero it must be blank These dialog elements apply to the export of GDS Output merges Boxes This controls the merging of adjoining geometry It is an issue because
204. d more In layout they can be directional and extended by half of their width 4 The most important property of an arc is its ability to remain connected when physical changes are made to the circuit Constraining properties provide for intelligent circuit layout Electric allows you to control how layout changes when the circuit is modified This is done by placing constraints on the arcs that react to node changes Electric has a set of four constraints that although not complete have been found to be useful in circuit design Using the Electric VLSI Design System version 8 11 135 Chapter 5 Arcs 5 2 Constraints 5 2 1 Rigid and Fixed Angle Arcs The first constraint in Electric is the rigid constraint When an arc is made rigid it cannot Original Structure change length If a node on either end is moved the other node and the arc move by the E Isan same amount Besides keeping a constant length rigid arcs attach in a fixed way to their Contact qeansistor nodes This means that if the node rotates or mirrors the arc spins about so that the e overall configuration does not change Without this rigidity constraint arcs simply stretch Contact rotated and rotate to keep their connectivity unconstramad ore The second constraint which is used only if an arc is not rigid is the fixed angle constraint This constraint forces a wire to remain at a constant angle usually used to Contact rotated keep horizontal and vertical
205. d the Buffer is highlighted in the example here The little sign is the currently highlighted port there are two possible ports on these nodes on the input and the output To highlight a node use the left button The node and the closest port to the cursor will be selected After highlighting you can hold the mouse button down and drag the highlighted object to a new location If nothing is under the cursor when the selection button is pushed you may drag the cursor while the button remains down to define an area in which all objects will be selected Another way to affect what is highlighted is to use the shift eft button This button causes object highlighting to be reversed highlighted objects become unhighlighted and unhighlighted objects are highlighted The shape of the highlighted port is important Ports are the sites of arc connections so the end point of the arc must fall inside this port area Ports may be rectangles lines single points displayed as a or any arbitrary shape For example the entire left side of the And gate is the input port and so its highlighting is a line 1 11 4 Schematics Tutorial Make an Arc Highlighted Pin node To wire a component select it move the cursor away from the component and use the right button If you click the right button and hold it without releasing then you can move around and see where the wire will go when you do release Wire Arc A wire will be created
206. de s model select it and use the Set Spice Model command in menu Tools Simulation Spice The Add Multiplier subcommand places a multiplier on the currently selected node Multipliers also called M factors scale the size of transistors inside of them Another piece of text that can be added to a circuit is for separate flattened analysis files This is useful for Nanosim timing assertions hierarchical measurements etc The Add Flat Code subcommand places a piece of text in the circuit that will be flattened and written to a separate file with the flatcode extension Using the Electric VLSI Design System version 8 11 275 Chapter 9 Tools Flattening adds global scope to these statements For example if you place a Nanosim timing assertion in a cell with the flat code and t tv_n here are 3 insta tv_n tv_n tv_n ode_set ode_set ode_set ode_set If clk is actually a tv_n tv_n 276 tv_n ode_set ode_set ode_set uph ces uph uph uph uph uph uph old of the cell then there will be 3 flattened ass old xt old xt clk rf in rf 100p top xf top xflop2 clk rf xtop old xt top xfl single signal that comes from the top level it is s 100p ertions in the flatcode file 100p old clk rf xtop flopl in ri old clk rf xtop flop2 in ri old clk rf xtop flop3 in ri lopl clk rf xtop flo
207. declared with the E line All exports are sorted by their name The syntax is E lt portID gt lt name gt lt TD gt lt originalNode gt lt originalPort gt lt flags gt lt variable gt Using the Electric VLSI Design System version 8 11 351 Chapter 10 The JELIB and DELIB File Format lt originalPortID gt re z x the port on the exported node instance may be blank if there are no lt flags gt flags for the export see below lt variable gt fa list of variables on the export see Section 10 4 1 The lt flags gt field has the format lt characteristics gt A B lt characteristics gt the nature of the export Choose from the following U unknown I input O output B bi directional P power G ground C clock C1 clock phase 1 C2 clock phase 2 C3 clock phase 3 C4 clock phase 4 C5 clock phase 5 C6 clock phase 6 RO reference output RI reference input RB reference base A indicates that the export is always drawn B indicates that the export is body only no equivalent on the icon Example s 18 conn 14 a D5G2 I B wo Exports port a of node instance conn 14 and calls it s 18 The text of the export is attached at the center of the port D5 and is 2 units high G2 It is of type input and only appears in the contents not the icon 352 Using the Electric VLSI Design System version 8 11 C
208. derline 0 25 increments maximum 4088 P Invisible outside cell Font DEFAULT FONT v Color DEFAULT COLOR X Using the Electric VLSI Design System version 8 11 Chapter 6 Advanced Editing The bottom part of the dialog has controls for the appearance and nature of the selected parameter e Code determines whether the parameter is code or pure data This can be changed to one of the interpretive languages in Electric When this happens the parameter value is treated as code that is sent to that interpreter Then the true value of the parameter is the evaluation of that code For example if the value of a parameter is 3 5 and the parameter is set to be Java code then the Java interpreter will be invoked and the parameter will actually be 8 e Units determines the type of unit choices are capacitance resistance inductance current voltage or distance See Section 7 2 2 for more on these units e Show controls the way that a parameter is displayed in the circuit You can request that various combinations of the parameter s name and value be displayed Text Size gives the size of the parameter text which can be in relative or absolute units X Y offset is the distance of the text s anchor point from the center of the cell Rotation is the text orientation in 90 degree increments Anchor controls the anchor point of the parameter text When the anchor style is Boxed the Boxed width and h
209. dex of each entry The original copy is labeled 0 0 and 148 Using the Electric VLSI Design System version 8 11 Chapter 6 Advanced Editing the copy to its right is labeled 1 0 These names are simply visual tags that have no bearing on the contents use the Object Properties command in menu Edit Properties to set or remove these names e Only place entries that are DRC correct requests that array entries only be placed where they do not create design rule violations This option is only available if a single node is being arrayed After the array is created the design rule checker is run on each entry and if it causes an error it is removed e Transpose placement ordering requests that array placement go by column instead of by row This is useful if the arraying includes names which are being auto incremented in the array By transposing the order of arraying the names will run in the orthogonal direction Note that the Array dialog is modeless and can remain on the screen while other work is being done Both the OK and Apply buttons create an array but the OK button also closes the dialog The Draw button lets you drag an area on the screen in which the array will be placed As you are dragging the area the individual array elements are shown so that you can see the extent of the array When the button is released the array is created Using the Electric VLSI Design System version 8 11 149 Chapter
210. dialogs You can set the color pattern and outline texture of any Artwork node and arc Predefined patterns are available below the pattern editing area If transparent colors are selected they are taken from the current color map which in turn is taken from the most recently selected technology other than the Artwork technology Note that artwork elements which do not have a color assigned use the DEFAULT ARTWORK color see Section 4 6 2 D Artwork Color and Pattern Pattern Color V Use Fill Pattern Ee EEES SSS EE Click on a pattern below to use it above N 210 Using the Electric VLSI Design System version 8 11 Chapter 7 Technologies 7 6 2 The FPGA Technology The FPGA technology is a soft technology that creates primitives according to an FPGA Architecture file Special commands in the Edit Technology Specific FPGA menu let you create the FPGA primitives build FPGA structures and program them The FPGA Architecture file contains all of the information needed to define a specific FPGA chip It has three sections the Primitive Definition section the Block Definition section and the Architecture section The Primitive Definition section describes the basic blocks for a family of FPGA chips these are primitives in the FPGA technology The Block Definition section builds upon the primitives to create higher level blocks Finally the Architecture section defines the top
211. diting The commands to edit another view work only when that cell exists To create a new cell of a particular type use the Make commands of the View menu These view conversion commands are available e Make Icon View creates an icon from a schematic see Section 3 11 4 for more on this e Make Schematic View creates a schematic from a layout e Make Alternate Layout View converts from layout or schematic to an alternate layout You must choose a specific layout technology and the new layout will use components from that technology You can also request that the converted layout be placed into a new library This is useful if the conversion creates a hierarchy of cells in the new technology e Make Skeleton View makes a skeletonized layout from a layout the only thing in the skeleton is the exports and the frame it is a layout icon e Make VHDL View converts the current layout or schematic into structural VHDL This VHDL is used by the Silicon Compiler see Section 9 12 and the ALS simulator see Section 9 5 2 Note that there are 5 schematic primitives which can exist in a normal and negated form buffer and or xor and mux You can choose the names to use for these two forms in the Schematics section of the Technology Preferences in menu File Preferences Technology section Technology tab Note that Electric does not have any commands that convert from hardware description languages such as V
212. dles many wires in arbitrary connection situations All of the non stitching routers make use of the Unrouted Arc a thin line arc that can connect any two components Creating rats nests of these arcs forms a graphical specification that the router can use The unrouted arc is from the Generic Technology see Section 7 6 3 To create one use the Get Unrouted Wire command in menu Tools Routing Then use standard wiring commands to run the unrouted arc Another way to get unrouted wires is to select all or part of an existing route made with any arc and use the Unroute command Another way to get Unrouted arcs for router input is to use the Copy Routing Topology and Paste Routing Topology commands These copy the network topology from one cell the copied cell to another cell the pasted cell The copied cell should be properly routed The Paste Routing Topology command uses node and arc names to associate the two cells Using the Electric VLSI Design System version 8 11 297 Chapter 9 Tools The Routing Preferences in menu File Preferences Tools section Routing tab controls all of the different routers The section in the upper left applies to the two stitching routers Mimic and Auto Specific sections apply to specific routers see Section 9 6 3 for the Mimic Stitcher Section 9 6 2 for the Auto Stitcher and Section 9 6 6 for the Sea of
213. dssesedcssosedeseses sunesucsessses 143 Gal Making COpiesiesiicisseisicstzsaincseieds ideoblaacsthistagesst a aniei a Ea e eai N E a En a EEA 143 G 2 Creation DefatltS n eraen aaen e e uth a a tea sade aa ae ee Taea a AT E aS 144 60 3 Preferences aroia iea a Vaaa EAE EEE AE al asian EEE EEE aaria 146 6 4 Making AtraySes ciccc5 eeiiiel Anis Met TE itt AS aa sen tein ae eae 148 60 5 Spreading Circus ery eck cs secesesdeees E EEE cages ca E E hea estee amp des E a de ca O A 150 670 Replacin amp Circuitry 22 cccscsctee cassie ite tatieebe a a dec a el aia E T E ven ata tien apts 151 7 Undo Control sees ceeeseters Slots weed ota cand es aee EAE e EE ESET E tebe E ECEE REEE 153 Ean A D gt RE E E E E E E S AE 154 GOP NEtWOTK S earar enrete araoe aa aa aE EEEE EE E A EAE OERE EEE E 163 G TOP OUINE S a stances e nieee a Aoi Ee E A e E a Ea EEN N oa at 170 6 11 Interpretive Language Siriei e aa irea A E E E Aaa EAEE eE DOETE OETA INESE 174 6 12 Project Management cnisa ables ieee A aa HA ra iaae Sini aie ia 178 6 132CVS Project Management acisi eieiei oeir ie NE Eei E e eE EOE AEE 181 614 EmersentieS onnee e e a A i a e A a T a R A Aa 183 Chapter 7 Technologies sc s scs cvssecsocessesocessscecesncvsuassvecessetesuetecdsccessusstondesescedevetsesecsbabecssntecsdocsesedessessnetoecsesetes 185 T 1 Introd ction to Technolo giesscsi iccisssszensscdscehescaseedacdestalesee hs ae EE ESEE NERE S ENESA 185 T 2Se lin and UNIS e a r a AE Tae R
214. e Voltage Source primitive is used as an pl S example Graphics is placed to describe the look of the symbol a battery look Exports are created at the top and bottom of the battery with the names plus and Voltage 0V minus A single parameter is defined called Voltage with a default value of OV Finally a Spice template is created that has the string mi US VS node_name plus minus DC Voltage This string contains substitution expressions of the form SOMETHING where SOMETHING can be an export a parameter or node_name In this example node_name will be replaced with the name of the voltage node plus will be replaced with the net name attached to the positive export minus will be replaced with the net name attached to the negative export and Voltage will be replaced with Using the Electric VLSI Design System version 8 11 281 Chapter 9 Tools the voltage value specified by the user When defining technologies it is possible to place Spice templates onto primitive nodes see Section 8 6 These templates can make use of two additional substitution expressions width and length which access the size of the node 9 4 5 FastHenry FastHenry is an inductance analysis tool see the papers of Jacob White When a FastHenry deck is generated a subset of the arcs in the current cell are written To include an arc in the FastHenry deck select it and use the FastHenry Arc Prope
215. e use the Show Undo List command in menu Edit In Electric almost every command is undoable but there are some exceptions Commands that write disk files are not undoable because Electric would not be so presumptuous as to delete a disk file Also commands that read a disk file are undoable but because users generally do not want to remove libraries from memory once read in the system prompts you to be sure that such a large undo is really desired Another useful command in for controlling changes being made is Repeat Last Action in menu Edit This repeats the last command but only works for commands that can sensibly be repeated Using the Electric VLSI Design System version 8 11 153 Chapter 6 Advanced Editing 6 8 Text 6 8 1 Understanding Text There are a number of ways to place text in a circuit e Each unexpanded instance of a cell has text that describes it and its ports e Each export has a text label e Nodes and arcs can be named with Object Properties so that they have text on them They can also have additional attributes that appear as text for example NCC annotations Spice multipliers Verilog transistor strength etc e Certain primitive nodes such as the Flip Flop component of the Schematic technology have text as an integral part of their image e It is even possible to create a special node that is only text with some of the commands under the Misc entry of the component menu Annotation Text
216. e Electric VLSI Design System version 8 11 349 Chapter 10 The JELIB and DELIB File Format Num Any digits at the end are additional rotation in tenths of a degree The lt flags gt field consists of any of the following letters sorted alphabetically with the numeric part at the end A if the node instance is hard to select L if the node instance is locked V if the node instance is visible only inside the cell Num Any digits at the end are the technology specific bits Examples Nschematic Transistor mos 0 2 0 R 2 ATTR_length D5G0 5 X 0 5 Y 1 S2 Places a schematic Transistor called mos O at 2 0 standard size rotated 90 degrees The flag field 2 is numeric and therefore is technology specific information in this case it makes the transistor be pMOS There is one attribute on the node called length with the value 2 a string This attribute is displayed anchored at its center D5 is 1 half grid unit in size G0 5 and is offset 0 5 1 from the node center X 0 5 Y 1 ITlow 1 lay HAPPY 14 12 Y A D5G4 Places an instance of cell low lay from the library defined in this JELIB file The instance is named HAPPY It is at 14 12 mirrored in Y and is rotated 0 The A means that the node is hard to select Its name is described by D5G4 D5 means a centered anchor point G4 means size 4 units 10 3 3 Arc Instances Inside of a cell definition arc instances a
217. e Electric can compare any two circuits including two layouts or two schematics we use the term Network Consistency Checking NCC The Electric Network Consistency Checker has two algorithms for matching networks e NCC firsts attempts to discover circuit mismatches using an algorithm called Local Partitioning Local Partitioning provides precise and intelligible mismatch diagnostics e After Local Partitioning NCC uses the Gemini algorithm Ebeling Carl Geminill A Second Generation Layout Validation Program Proceedings of ICCAD 1988 p322 325 In practice upwards of 95 of all errors are found by Local Partitioning NCC has a hierarchical mode which starts at the bottom of the hierarchy in the leaf cells and proceeds upward This mode is recommended because it allows the Local Partitioning algorithm to provide even more precise and intelligible mismatch diagnostics Example For an example of network consistency checking open the Samples library with the Load Sample Cells Library command in menu Help and compare the cells tool NCC lay and tool NCC sch These two cells are equivalent and the checker will find them to be so 9 7 2 Commands To run NCC use these commands in menu Tools NCC e Schematic and Layout Views of Cell in Current Window Use a heuristic to figure out what to compare against the cell in the current window If the current cell is a schematic then compare it against some layout cell in the sam
218. e Export Simulation Data command in menu Window Waveform Window writes a tab separated file with all simulation data names and values The Export Simulation Data As CSV command writes a comma separated file with all simulation data These commands are useful for doing spreadsheet analysis of the data Sweeps If the simulation had sweeps those values are shown in the cell explorer in the SWEEPS area You can right click on a sweep and choose to include or exclude it from the display double clicking on the sweep toggles its inclusion Right clicking on the SWEEPS icon lets you include or exclude all of them A single sweep can be highlighted to distinguish it on the display Right click on that sweep and choose Highlight To remove all highlighting right click on the SWEEPS icon and choose Remove Highlighting Time Control Two vertical cursors appear in the window called main and extension the extension cursor is dotted Their time values and their difference are shown at the top of the window You can click over the cursors and drag them to different time locations You can also use the Center buttons to bring these cursors to the center of the display Another way to measure in the waveform window is to use the measure tool see Section 4 7 4 This tool lets you drag a rectangle and it shows the left right time with difference as well as the top bottom values with difference The tool snaps to data
219. e Section 6 9 3 When you descend into an arrayed node the system does not know which element of the array you are entering Most of the time the specific element is irrelevant but if the circuit is being simulated the specific instance may be necessary for cross probing Therefore if the cell is being simulated and you descend into an arrayed node you will be prompted for the specific element that you wish to visit There are other situations that cannot be detected where the specific element needs to be known To solve this problem you can request that Electric prompt for the specific element in all situations where an arrayed node is visited To do this check Always prompt for index when descending into array nodes in the Nodes Preferences in menu File Preferences General section Nodes tab 66 Using the Electric VLSI Design System version 8 11 Chapter 3 Hierarchy 3 6 Exports 3 6 1 Export Creation All nodes in Electric have connection sites called ports which indicate where wires may be attached The primitive nodes have predefined ports but ports on cell instances must be defined by the user To do this simply select a port on a node inside the cell and turn it into an export which makes it available on all instances of the current cell Although most ports are on nodes along the edge of the cell Electric makes no port location restrictions so they may appear anywhere To see the location of all p
220. e advantages of connectivity based IC layout are many e No node extraction Node extraction is not a separate error prone step Instead the connectivity is part of the layout description and is instantly available This speeds up all network oriented operations including simulation layout versus schematic LVS and electrical rules checkers No geometry errors Complex components are no longer composed of unrelated pieces of geometry that can be moved independently In paint systems you can accidentally move the gate geometry away from a transistor thus deleting the transistor In Electric the transistor is a single component and cannot be accidentally destroyed More powerful editing Browsing the circuit is more powerful because the editor can show the entire network whenever part of it is selected Also Electric combines the connectivity with a layout constraint system to give the editor powerful manipulation tools These tools keep the design well connected even as the circuit is modified on different levels of hierarchy Tools are smarter when they can use connectivity information For example the Design Rule checker knows when the layout is connected and uses different spacing rules Simpler design process When doing schematics and layout at the same time getting a correct LVS typically involves many steps of design rule cleaning This is because node extraction must be done to obtain the connectivity of the IC layout and
221. e cell group If the current cell is a layout then compare it against some schematic cell in the same cell group Since most cell groups have one layout cell and one schematic cell this form of the NCC command is usually the most convenient NCC expects that all layout cells in given group match the corresponding schematic cells found in the that group regardless of the dependencies between them e Cells from Two Windows Compare the two cells that are displayed in the two opened windows there must be exactly two windows This is useful when the schematic and layout are not in the same cell group The command can also be used to compare schematics with schematics or layout with layout However the command refuses to compare icon cells since icons cells don t have connectivity 302 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools e Run NCC for Schematic Cross Probing This command runs NCC and saves the net associations between schematic and layout The user can generate a Spice netlist for example from an Electric layout cell Simulating this netlist will result in a waveform file that uses layout hierarchy and net names If this waveform file is loaded into Electric it cannot be cross probed from the schematic It can be cross probed from the layout but that is often difficult to do In this case the user can run this NCC command which will save net associations between schematic and layout Then the user can cross
222. e cell is a standard cell e D if the cell has passed design rule checking For more cell information use the commands of menu Cell Cell Info Revision 2004 2004 2004 2004 2000 2001 2004 2002 0 vaovao 0 OrFoOOCOOC OR Chapter 3 Hierarchy Size Usage L I S D 1310x383 10 0x12 37 0x73 58 75x59 48 0x45 85 5x83 12 5x28 44 0x41 The usage is the number of times that this cell e List Nodes Arcs in this Cell counts the number of nodes and arcs in current cell and below This is a hierarchical count if two cell instances each have two transistors inside of them the total is 4 transistors However it counts only actual nodes ignoring arrayed nodes see Section 6 9 3 o List Cell Instances shows all cell instances below the current cell e List Cell Usage looks up the hierarchy and finds cells that contain the current cell as an instance e List Cell Usage Hierarchically looks up the hierarchy and finds cells that contain the current cell as an instance or as a subinstance For example if cell A contains cell B and cell B contains cell C then using this command on cell C will mention both cells A and B whereas the nonhierarchical version of this command will mention only cell B e Number of Transistors counts the number of transistors in the current cell and below considering arrayed instances see Section 2 4 2 Using the Electric VLSI Design System version 8 11 73 Chapter
223. e checker can report error names eeeeee 6 of Distance Length 4 o Width B lo Contact spacing con fo Rule Name Load Parameters write XML Save Parameters Spacing D Distances are in nanometers Contact Parameters Technology Parameters General Active Poly The Contact panel lets you specify size and spacing values for the Contact layer The Rule Name fields let Well Implant Metal Via Antenna GDS you describe the rule so that the design rule checker can report error names Note that inline spacing is for one dimensional arrays of contacts and array spacing is for two dimensional eeee 88 E Distance Rule Name a a Cut array spacing C oO Metal overhang inline of o oo Cut size 4 Cut inline spacing B arrays Metal overhang all E fo Load Parameters Write XML Poly overhang F fo Active spacing G fo __Save Parameters Distances are in nanometers 254 Using the Electric VLSI Design System version 8 11 Chapter 8 Creating New Technologies Technology Creation Wizard x Technology Parameters Well Implant Parameters General Active Poly Gate Contact Well Implant Metal Via Antenna GDS ee ee 8 E The Well Implant panel lets you specify size and spacing values for the Well and Implant layers The Rule Name fields let you Distance Rule Name describe the rule so that the NPlus width A des
224. e driving against it multiplied by the Keeper Ratio e Attribute LEPARALLGRP 0 If set to 0 this gate drives by itself If an integer greater than zero all gates with that value whose outputs drive the same network are assumed to drive in parallel The size needed to drive the load on the network will be equally divided among those gates e Attribute su 1 This specifies the step up fanout of the gate and overrides the global fanout specified in the preferences If set to 1 this attribute is ignored and the global value is used LEWIREs A cell marked with an attribute LEWIRE 1 denotes a wire load There are two ways to specify the capacitance of an LEWIRE The first is to use the LEWIRECAP attribute to specify the capacitance in fF The second is to use two attributes L and width to specify the size of the wire however this method has been deprecated because it unnecessarily complicates the defintion of the Wire Ratio setting The LEWIRECAP is converted to X size by the following formula X size LEWIRECAP wire_ratio xlinverter_totalgate In this case wire_ratio is defined as lambda of gate per fF of wire capacitance x linverter_totalgate is the total lambda of gate of an X 1 inverter which is defined as the sum of x linverter_nwidth plus x linverter_pwidth see LEsettings Capacitors are likewise converted to X size by the formula X size Capacitance gate_cap le 15 xlinverter_totalgate Commands T
225. e function entity The programmer requires some knowledge of the internals of the simulator to extract the correct information from this list and to schedule new events A complete discussion of function entity programming is beyond the scope of this document Using the Electric VLSI Design System version 8 11 295 Chapter 9 Tools 9 5 6 ALS Models As previous examples have shown the model entity provides connectivity between other entities including other model entities The model may be used in conjunction with gate and function entities to describe the behavior of any circuit The model entity is headed by a model declaration statement and followed by a body which references instances of other entities lower in the hierarchy The model name and a list of exports which are referenced in a higher level model description are included in this statement The format of the model declaration statement is Format model name signall signal2 signal3 signalN Example model dff d ck set reset q q_bar References to instances of primitive objects gates and functions and lower level models are used to describe the topology of the model to the simulator The format of an instance reference statement is Format instance model signall signal2 signal3 signalN Example gatel subgate input en mix It should be noted each instance reference in a model entity must have a unique instance name The following is an example
226. e header cells and trailer The header has these elements Header information variable fields are allowed View information External library information External cell in the above external library External export in the above external cell Technology information variable fields are allowed OJHA AlA r jy lt ja Tool information variable fields are allowed Using the Electric VLSI Design System version 8 11 343 Chapter 10 The JELIB and DELIB File Format The cells have these elements Cell header variable fields are allowed Primitive node information in the current cell variable fields are allowed Cell instance information in the current cell variable fields are allowed Arc information in the current cell variable fields are allowed Export information in the current cell variable fields are allowed KIS IR za Cell termination The trailer has this optional element Group information Everything in the file is completely ordered There is an ordering to the external libraries cells in those libraries technologies tools cells nodes arcs exports in a cell etc Even the extra variables on a line are ordered The ordering is usually a name sort By ordering everything in the file the exact same file is generated every time and text comparison operations will accurately find differences between two files Note however that the JELIB reader does not require any sorting and can handle the dat
227. e is one more special type of anchor called boxed Boxed text has a centered anchor point but is limited in size to a particular box It appears as an X but also has four lines that indicate the edge of the box Boxed text is typically used on unexpanded cell instance names so that the text does not exceed the size of the instance D lay 100 Pe Note that text can be moved away from its attached node or arc If this has been done then selection of the text will also indicate the attached component by drawing a dashed line to it Using the Electric VLSI Design System version 8 11 155 Chapter 6 Advanced Editing 6 8 3 Modifying Text Like nodes and arcs text can be moved simply by clicking and dragging Text can be erased by selecting it and using the Selected command of the Edit Erase menu the Delete key Changing a Single Piece of Text To change text double click on it and type a new value To change other aspects of selected text and use the Object Properties command ftran 35 in menu Edit Properties Besides the text at the top of the dialog these fields can be modified fi7 Points min 1 max 63 All Text Sizes are Name of node P Transistor P Multi Line Text Text Size i fi Units min 0 25 max 127 75 Scaled by 100 e Text Size can be absolute x offset fo 0 25 increments Bold f Italic ie ra ae PONE AUNE Y offset fo maximum 4088 Underline ep e X Y offset is relative to the Rot
228. e is room to describe the node graphically The other factors are Lockable No properly set for a contact Spice template To place a piece of geometry for example some polysilicon click over the Filled Box entry in the component menu third Change Layer from the top and then click in the edit window This New layer for this geometry geometry now has shape but no layer associated with it To ee assign a layer double click on the geometry Then choose polysilicon 1 The black box will change appearance to that of a polysilicon layer You can move and stretch this box appropriately In this example assume that a contact between polysilicon and metal 2 has three layers polysilicon 1 metal 2 and contact cut Therefore the above operation must be done two more times to place the metal 2 and contact cut layers Besides this pure geometry there must be two other items in the node a highlight layer and a port The highlight layer is obtained by selecting the HIGH entry from the component menu It is then placed and stretched so that it encloses the contact highlight layers define the size of the node and this means that they will typically surround the geometry Using the Electric VLSI Design System version 8 11 235 Chapter 8 Creating New Technologies Change Port x Metal 1 Disallowed v The other item that must be created is a port more than one can be created Metal 2 alowe
229. e it look better Note that the Cell Center and Essential Bounds nodes are made hard to select by default which means that they can be selected only by using Special Select mode see Section 2 1 5 for more The Spice Code and Spice Declaration entries create text for Spice decks see Section 9 4 3 The Verilog Code Verilog Declaration Verilog Parameter and Verilog External Code entries create text for Verilog decks see Section 9 4 2 These entries actually create Invisible Pin nodes with appropriate text on them Cell Instance Annotation Text Layout Text Layout Image Annular Ring Cell Center Essential Bounds Spice Code Spice Declaration Verilog Code Verilog Declaration Verilog Parameter Verilog External Code Simulation Probe DRC Exclusion AFG Exclusion Invisible Pin Universal Pin Unrouted Pin A special primitive called Simulation Probe is recognized by simulators and visually modified to reflect whatever it is connected to The simulators that reflect the state of the circuit by drawing lines along arcs also fill in these probe nodes It provides a visual display of simulation activity and works especially well with the VCR controls in the waveform window See Section 4 11 1 for more The DRC Exclusion node is used by the design rule checker see Section 9 2 3 The AFG Exclusion node is used by the auto fill generator see Section 9 8 2 The Invisible Pin
230. e more right Move right 2 4 1 2 4 1 Move up 2 4 1 Move more up 2 4 1 Move more down Move down 2 4 1 2 4 1 Using the Electric VLSI Design System version 8 11 Chapter 1 Introduction 1 10 IC Layout Tutorial 1 10 1 IC Layout Tutorial Make a Cell This section takes you through the design of some simple IC layout J New Cell xi Library noname v Name MyCircuit _ Before you can place any IC layout the editing window must have a cell in it Use the New Cell command in menu Cell This will show a dialog that lets you type a new cell name Type the name MyCircuit is used here and click OK The editing window will no longer have the No cell in this window message and circuitry may now verilog Z be created Technology mocmos x Cancel Make new window View E SHEE LIBRARIES After creating a cell look at the cell explorer in the status bar on the left side of the E noname Current edit window Under the LIBRARIES icon you will see the list of libraries MyCircuitlay currently only one called noname If you open that library s icon you will see La JOBS the cells in the library currently only MyCircuit T ERRORS 1 10 2 IC Layout Tutorial Create a Node Layout is placed by selecting nodes from the side bar s components menu and then wiring them together This example shows two nodes that have been created This was done by clicking on the ap
231. e of 200 or larger may enhance performance 4 Using the Electric VLSI Design System version 8 11 Chapter 1 Introduction 1 4 Building Electric from Source Code It is not necessary to rebuild Electric from the source code because the downloads are ready to run For people who wish to explore the source code this section describes some of the necessary steps The first step in building the source code is to extract it from the jar file To do this place the jar file in its own directory change to that directory and run the following command jar xf electric version jar Windows users may want to install cygwin from www cygwin com in order to more easily run jar and other commands The jar command will create a number of files and folders on your disk e com is a folder with all of the source code e packaging is a folder with support files for building Electric e META INF is a support folder used when running the jar file and can be deleted build xml is an Ant script for building Electric e ChangeLog txt is a detailed list of changes to Electric e COPYING txt is the GNU copyright document that applies to your use of Electric e README txt is a file of notes about Electric Electric source code is also available from the GNU Savannah repository with one of these commands svn co svn svn savannah gnu org svn electric trunk svn co http svn savannah gnu org svn electric trunk which will extract the code into
232. e of the circuit and point in the given direction The default directions of 1 1 1 and 1 1 1 illuminate the 3D view from the front Although the lights have a default color of white this can be changed by editing the SPECIAL 3D DIRECTIONAL LIGHT entry in the Layers Preferences Ambient light is the background light that fills a space It is used to illuminate those areas that are not directly hit by the directional lights The default color of the ambient light is gray but this can be changed by editing the SPECIAL 3D AMBIENT LIGHT entry in the Layers Preferences 122 Using the Electric VLSI Design System version 8 11 If Java3D is not installed the distance and the thickness can still be controlled In such a situation the 3D Preferences dialog has much more limited information The cross section information on the right shows layers and their range of depth You can choose either the layer name or its cross section name Chapter 4 Display D Preferences Preferences 3D USER Preferences General E Display Display Control Component Menu Layers Toolbar Text Smart Text Grid Ports Exports Frame Layer cross section for technology mocmos ee 8 lo C Tools Technology Export Import Reset Reset All Only resets USER Preferences Help Apply 65 Cancel 16 35 if ib 4 10 3 Behaviors and Animation Behaviors are controls that affect the
233. e of these size fields empty that 4 0 4 0 coordinate is not changed Cancel Note that when typing size amounts into a dialog specify the size of the highlighted area In a typical MOS transistor the highlighted area where active and polysilicon cross is 2x3 even though the component is much larger if you include the four overlap regions sticking out 56 Using the Electric VLSI Design System version 8 11 Chapter 2 Basic Editing 2 5 2 Arc Sizing To change the width of an arc issue the Interactively command in menu Edit Size Note that the arc stretches about its center so that an edge is at the cursor location Click a button to make the change To change the size of more than one arc at a time select the arcs and use the All Selected Arcs command Arc Properties Rife Xx Type Metal 1 Network out Another way to change an arc s width is to select it and E 7 Name Props use the Object Properties command in menu Edit Emm Properties Width y Length 20 Angle 0 V Easy to Select Note that when typing size amounts into a dialog specify ices Jv Easy Eo Selec the size of the highlighted area A CMOS active arc shows Head _RatationLower lay Rotation 0 a highlighting only on its active area even though the At 1 0 43 5 complete arc has implant regions that are much larger iit Metal 1 Pin pin 13 ai etal 1 Pin pin 13 Hen iri ENT Ati 21 0 43 5 e Name field lets
234. e set to one of the transparent layers If you change the color of a layer that has transparency assigned to it the change will affects all layers assigned to that transparency You can draw in the pattern area to set a pattern and you can choose from a set of predefined patterns by clicking on their image below the pattern editing area You can also choose an outline texture to draw The lower right controls the appearance of the layer on the printed page A separate Use Fill Pattern control lets you use patterns on a printer even if they are not used on the display The Opacity is also used for printer blending and for some display algorithms When changing the background color note that it must contrast with both the highlight color and the inverse of the highlight color the inverse is black in the default settings To automatically switch to a black or white background there are commands in the Window Color Schemes menu that change the special colors background highlighting grid etc These commands do not affect individual layer appearance just the special colors that define the overall look of the display e Black Background Colors sets the background to black 108 Using the Electric VLSI Design System version 8 11 Chapter 4 Display e White Background Colors sets the background to white e Restore Default Colors sets the background to gray the default e Cadence Colors Layers and Keystrokes loads a set of colo
235. e the right button to draw wires out of it Each wire will connect at a different location in the input port and once the side fills with arcs it will automatically grow to fit more Note that the vertical cursor location along the input side is used to select the position that will be used when a new wire is added D gt To negate an input or output of a digital gate select the port or the arc and use the Toggle Port Negation command in menu Edit Technology Specific With this facility you can construct arbitrary gate configurations 1 11 6 Schematics Tutorial Constraints Once components are wired moving them will also move their connecting wires Notice that the wires stretch and move to maintain the connections What actually happens is that the programmable constraint system follows instructions stored on the wires and reacts to component changes The default wire is fixed angle so the letter F is shown when the wire is highlighted Select a wire and issue the Rigid command in menu Edit Arc The letter changes to R on the arc and the wire no longer stretches when components move Find another arc and issue the Not Fixed angle command Now observe the effects of an unconstrained arc as its neighboring nodes move These arc constraints can be reversed with the Rigid and Fixed angle commands See Section 5 2 1 for more on these constraints 28 Using the Electric VLSI Design System version 8 11 Chapter 1 Intr
236. e these options use the Preferences 32 Using the Electric VLSI Design System version 8 11 Chapter 1 Introduction command in menu File and choose the Technology tab In the MOSIS CMOS section set the number of Metal layers to 6 This preference is remembered and you will not have to set it again in future sessions with Electric See Section 7 4 2 for more on the MOSIS CMOS technology Your goal is to draw a layout like the one shown here It is important to choose a consistent layout style so that various cells can snap together In this project s style power and ground run horizontally in Metal 2 at the top and bottom of the cell respectively The spacing between power and ground is 80 units center to center No other Metal 2 is used in the cell allowing the designer to connect cells with Metal 2 over the top later on nMOS transistors occupy the bottom half of the cell and pMOS transistors occupy the top half Each cell has at least one well and substrate contact Inputs and outputs are given Metal 1 exports within the cell You may find it convenient to have another sample of layout visible on the screen while you draw your gate Use the Place Cell Instance command in menu Cell and select inv lay Then click to drop this inverter in the layout window To view the contents of the inverter highlight the inverter and use the One Level Down command in menu Cell Expand Cell Instances or click on the opened
237. e used to construct primitive nodes and arcs in a technology Because of this the layers must be edited before the nodes and arcs To edit an existing layer select it from the cell explorer or the Edit Cell command in menu Edit To create a new layer use the context menu on the TECHNOLOGY LAYERS entry of the cell explorer and choose Add New Layer A layer can be deleted simply by deleting its cell A layer can be renamed by renaming its cell but remember to use the name layer in front i e the old name is layer metal and the new name is layer metal 1 Finally you can rearrange the order in which the layers will be listed with the Reorder Layers command from the context menu fee TECHNOLOGY LAYERS Add New Layer Reorder Layers Editing Special Layer Information Function metal 1 Color 96 209 255 0 8 0n Transparency layer 1 n tipple Pattern ed Style solid eae an SEE E CIF Layer CMF PTT rer ann E a a E There are many pieces of information H E E E GDS II Layer 49 80p 80t W E _ in a layer most of which can be updated by double clicking on them There is a 16x16 stipple pattern a large square of color above that and a number of pieces of textual information along the right side SPICE Resistance 0 06 EEE Ee rT TT Tt yy a eee eee SPICE Capacitance 0 07 E E EEE Eee HOLLLO SPICE Edge Capacitance 0 0 Clear Pattern Invert Pattern 3D Height 19 0 EEE BE
238. e view between them linearly Path interpolators allow multiple key frames to combine into a single smooth animation 3D Demo Control Dialog xi Spline interpolators can be created and controlled with the m Capture Frame Animate command in menu Window 3D V Auto viewplatform a Window To animate you must create a sequence of key frames that define the view changes Each key frame Enter Frame Read Demo Save Demo represents a different 3D view of the scene Create Movie Close To control the animation make changes to the display and click Enter Frame You can enter as many frames as you want and animate them later The animated sequence is a demo that can be saved to disk and restored later for playback A QuickTime movie can be created by using the Create Movie button For this option the JMF plugin must be available see Section 1 5 There is a built in demo of animation available in the Help 3D Showcase menu First use the Load Library command to load the demo library Next use the 3D View of Cage Cell command to start the 3D viewer on the cage cell used on the cover page of this manual Finally use the Animate Cage Cell command to start an animation demo on the 3D view of the cage cell 124 Using the Electric VLSI Design System version 8 11 Chapter 4 Display 4 11 Waveform Windows 4 11 1 Digital Waveform Windows The waveform window is able to display digital simulation output T
239. ection to individual instances bottom illustration If the wire port Y is connected to a 3 wide bus C then each element of the bus connects to port Y on a different instance of cell X C 1 connects to Y on M 2 C 2 connects to Y on M 3 and C 3 connects to Y on M 4 If the bus port Z is connected to a 6 wide bus D then it is viewed as 3 pairs of signals and each pair connecting to the two wide bus Z on a different instance of cell X D 1 and D 2 connect to Z 1 and Z 2 on M 2 D 3 and D 4 connect to Z 1 and Z 2 on M 3 and D 5 and D 6 connect to Z 1 and Z 2 on M 4 Note that it is not possible to array a primitive node from the Schematic technology Instead you must place that node inside of a cell and array instances of the cell 166 Using the Electric VLSI Design System version 8 11 Chapter 6 Advanced Editing Parameterized Bus Names Library clock v Parameters It is possible to have variable width busses by heat Parameter Value parameterizing their names Electric maintains a list of Poo global parameters and these can be manipulated with the Edit Bus Parameters command in menu Edit New Parameter Properties You can create and delete parameters and Delete Parameter can set values for each Update All Templates Done To use these parameters you must add a template to an arc node or export name This figure shows an export called in EXPORT_Bus_Template in
240. ectric reads the Verilog file and constructs a schematic representation Because there is no placement in Verilog files the schematic is topologically correct but visually messy e ELIB is an older Electric library format that is in an undocumented binary format e Readable Dump is an older Electric library format that captures the entire database in a text readable format These files were used when the elib file was the main way of saving libraries because a way was needed of reading library files Now that the newer jelib format is also text readable there is no need to use Readable Dumps anymore e Text Cell Contents is used to read a text file into a text cell The current window must be a textual view such as VHDL Verilog documentation etc See Section 4 9 for more on text windows Some file formats CIF GDS EDIF LEF DEF SUE and Applicon 860 are technology specific Before reading them you will be prompted for the layout technology to use The default is to use the current technology If you import a library that already exists in Electric the following warning appears Save Library Ea A Library u1_I has changed Save before replacing click Merge to combine the new data with the existing library No Cancel No to Al Merge You can save the previous library overwrite the previous library cancel the operation or merge the new library into the previous library The Merge option creates ne
241. ed by pads and finally the base library cmos When a piece of technology information is found in more than one library the latest one is used i e the current library s version is used before a dependent library s version and a dependent library s version is used before that of another dependent library higher up the list Note that the version which is used is expected to be the most recently created version and a warning message will be issued if this is not the case Control of the library list is done with the Edit Library Dependencies command in menu Edit Technology Editing Dependent Library Selection xi Dependent Libraries All Libraries A dialog is presented with two lists of libraries The list on the left cmos Remove shows the dependent libraries and pads the list on the right shows all current libraries By selecting a library name from the list on the ssaa right and clicking on the lt lt Add button it is added to the list on the left To add a library not shown Library iF not in list type its name into the box on the oo right and click the lt lt Add button Current smallPads Libraries are examined from bottom up Cancel To remove a library from the list on the left select it and click the Remove button 220 Using the Electric VLSI Design System version 8 11 Chapter 8 Creating New Technologies 8 4 The Layer Cells Creating and Deleting Layer Cells Layers ar
242. eeeeeeeaeecsaecsaeeeeesseeesaeeaaes 94 4 4 Zooming and Panning esiisa cdi eesi seta cai a ai Ge ae ee tition 97 4 5 ThE Sidebar riiscia ata ia a Ea ga ase ae TG ae ee Tea 100 AO FCOLOLE AN EE E A A I eh reine Coated ts Lata lt cadets deat Meee tae beat asee 107 4 72 Grids and Al SnMe nt vecssecec verse ssceecteshdk a ei eae e e that les tee dette ep teweines E ei a 111 A Printinge nenen sade ios seteogcsabeepensseten ouaacwencadeusessecdovsesgavannasagens N eE E NE sabaaes ASE SO RE OE ERa 114 Using the Electric VLSI Design System version 8 11 Table of Contents Chapter 4 Display 49 Text WANG OW Soene tea e E EAE E E e E a a a a e 117 A10 3D WIndows aeeoe eaaa e E AEE RE ETE E le EEE ean ETE a 119 4 1 1 Waviel Orin WiINdOW Sosnin onae ee a A ENT EN E EE EE NTE 125 Chapter S AreSissccscccssccessiscsonsscsssnccscscsossstennsssduvesvaceseanccsseceadsceveesovesesientvessescuestsseeseasssdencesedeevsedeseensessessecsoeste 135 S INMOdUCHONEO ATCS anren oeae vec e A E even coabuascheansecitcedeucdaaseoes 135 5 2 C nsttaitS ho epee POEN rE E AAE bedt o aeaa EES ASNES ane das AEE eE TEETER ETRIE EAER 136 5 3 Setting Constants a aaa WMG an ele ad ue eee edn 138 D4 Other Propertie Sneinen n e e Re aR ESE a LeU Sen Sedat dance nna E hg E hate Sates een 139 S 5 Default Are Properti esmenten eae cuteese col E A E E A EN E AE 141 Chapter 6 Advanced Editing ccccciscssacssscecesscsvensssasessosessocecessevssuessensesescesnonssesssebsncse
243. efines a network Networks may span many arcs or they may reside on only a single export on a single node Because networks are stored in the Electric database they can be immediately accessed when needed Whenever a port on a node is selected the highlighting indicates the entire network that is connected to that port Another way to see an entire network is to use the Show Network command in menu Tools Network This will highlight all arcs on the currently selected networks If a cell instance is selected but no individual port is selected such that there is no single network selected then all wired ports will be highlighted Repeated use of this command causes the network to be highlighted at successively lower levels of the hierarchy If the design is very dense you can select one or more networks by name with the Select Object command in menu Edit Selection The Show All Networks command in menu Tools Network highlights every network in a different color useful if there are not too many nets There are many commands in menu Tool Network that can be used to get information about the networks in a cell List Networks shows a list of the networks in the current cell List Exports on Network lists all export names on the currently highlighted network This list contains the names of exports at all levels of the hierarchy above and below the current cell The facility is useful if for example you have propagated clock li
244. eft lt gt Right 2 6 Alt Show Exports 3 6 2 Using the Electric VLSI Design System version 8 11 109 Ei s y x Chapter 4 Display Y Redo 6 7 Mirror Up lt gt Down 2 6 2 222000 O z Zoom In 4 4 1 Zoom Box 4 4 1 Shift Zoom Out 4 4 1 Zoom Out 4 4 1 WiretoPoy a o Key Pan Left 4 4 2 Center cursor 4 4 2 Pan Right 4 4 2 Wire to Metal 4 1 8 Wire to Metal 5 1 8 F5 Run DRC 9 2 1 SPACE 110 Zoom In 4 4 1 Pan Up 4 4 2 Wire to Metal 6 1 8 F6 Array 6 4 Wire to Metal 7 1 8 Wire to Metal 8 1 8 F8 NCC Cells in Windows 9 7 2 Fill Window 4 4 1 Wire to Metal 9 1 8 F9 Tile Windows Vertically 4 3 Increase all Text Size 6 8 4 Decrease all Text Size 6 8 4 DEL Erase 2 3 Show Next Error 9 1 Show Previous Error 9 1 Switch Wiring Target 1 8 Repeat Last Action 6 7 S O Using the Electric VLSI Design System version 8 11 Chapter 4 Display 4 7 Grids and Alignment 4 7 1 Drawing a Grid The Toggle Grid command in menu Window turns the grid display on and off The grid consists of dots at every grid unit and bolder dots every 10 units but both of these distances are settable Initially the grid dots are spaced 1 unit apart The size of a grid unit can be related to real world distance by considering the scale of the technology For example in the MOSIS CMOS technology the scale is
245. eight 2 defaultHeight lambda lt nodeBase gt defines the BaseRectangle of the node It has a subelement lt box gt which has in it a subelement lt lambdaBox gt In the lt lambdaBox gt the attributes klx khx kly and khy are the coordinates of the base rectangle of a standard size node lt sizeOffset gt is deprecated lt protection gt defines the protection frame of the cell lt nodeLayer gt a list of NodeLayers described below lt primitivePort gt a list of primitive ports on the node The name attribute describes the port name To make a library conversion from one technology to another it would help to unify port names in Using the Electric VLSI Design System version 8 11 245 Chapter 8 Creating New Technologies 246 some manner Port names of single port nodes are not very important because the library reader can unambiguously connect arcs to the renamed port However port names of transistors could have compatable names like poly top poly bottom diff left diff right lt primtivePort gt has these subelements lt portAngle gt can restrict direction of arcs which can connect to this port lt portTopology gt is a small integer that is unique among PrimitivePorts on the PrimitiveNode When two PrimitivePorts have the same topology number it indicates that these ports are connected lt box gt a rectangle which constraints the position of end point of connected arc lt portArc gt
246. eight fields give the size limits See Section 6 8 2 for more on text anchors Font is the text font Color is the text color Bold Italic and Underline control the style of the text Invisible outside cell requests that the parameter not be drawn when viewed farther up the hierarchy The Done button terminates this dialog Note that there is no Cancel button this dialog makes changes as they are entered Special Considerations To use a parameter inside of a cell create text that has the code set to Java and has a in front of the parameter name For example if a cell has the parameter size defined and you want a transistor in the cell to be size 2 in width then edit the transistor and set its width to size 2 and its code to Java To display the current value of a parameter from up the hierarchy create a piece of Annotation Text found in the Misc entry of the component menu and set its code to Java and its value to PNAME where PNAME is the parameter name Note that when a parameter is used in a cell but there is no value from up the hierarchy the text appears as not found Parameters on cells are not tied to any node or arc Instead they float freely inside of the cell You can select the text and drag it to any location in the cell Parameters get inherited when the cell is instantiated This means that each new icon when created will have all of the parameters shown on it with defaul
247. ele th adeeb daa spi cease E awa ee anes tao asi aes eee 59 3 22 Cell Cr ation and Deletion sis scsi ccs ok nan A eh ee eS 60 9 3 Cre atime INSANE Sre alec cohesion Medel cede eE ea Ei erie ev Mtesns tases adndecs Durtiets a 62 3 4 Examining Cell Instances rreri eean e e A E a ET e eE 64 3 5 Moving Up and Down the Hierarchy eseeeeeeseeeseeesesreesesresresrestessesresressesteseesrestesentesresresessreet 65 36 EX POMS n o ri a e r aT aaa E E EE E a aie a Wa 67 3 7 Cell Information eiela ane ea nae a E le costelescebbeaatslocaal sladasthealacpieshtaset tees 72 3 8 Rearranging Cell Hierarchy eiscicsoice eneee eea ned che a ai hase desta Ea a ata Ea ATE 77 3 9 Librat eS aea ea ti Ria ieee are ace ease aad 78 3 10 Copying Cells Between Libraries eee cseesesseceseceseceseeeseeeseesseceaeceaeceeeseaeeeaeeeaecnaeeseeneeeees 85 SPI VAC W Sites iaraa A a Amite lalate ate near hp aes Ate te bec O e Aedes dahoels votevls cadet siete 87 Chapter 4 Dis playicsisssccscssascsvecsesssconnstossesscseesssscssacecebecosostedesestoseesensSeessccssessduedd soesteansosessssnsieseacessontsseatesesesoseess 91 4a 1 Th TOOK B at seen sees eek sansven viens Hees eetes vn ceaaaeeaea vent tee reg saa esa eee ee Bon fasta ann ee eas 91 A 2 The Messages Window i ic ide cia doses ensthid sicdesscachestssactebedagtybocdieebabecuaabcevstetd cabitts Lageulbigeebilaaetsiteads 93 4 3 Creating and Deleting Editing WindOWS ce eeseecceeeeseeeseecssecseeseces
248. ell places cell instances see Section 3 3 e Spice places special Spice nodes see Section 9 4 3 e Export places export nodes when editing icon artwork see Section 7 6 1 100 Using the Electric VLSI Design System version 8 11 Chapter 4 Display The layout of the component menu is controlled by the Component Menu Preferences in menu File Preferences Display section Component Menu tab The menu is shown on the left and the possible entries Nodes Arcs Cells and Special are on the right To change a menu entry select it the selected entry is highlighted in green and choose either Remove to empty that entry or lt lt Add to add the selected Node Arc Cell or Special to the entry Adding multiple nodes to a menu entry allows that entry to have a popup menu to select among the nodes _ Categories Component Menu USER Preferences E General Display mocmos Component menu 3 by 13 Nodes Component Menu Are Node Layers Metals Metal8 Pin Toolbar Arc Node Node Text Metal 6 Metal5 Pin Jvbtal 5 Metal 6 Co Smart Text Are Node Node Grid Metal4 Metal4 Pin Jvetal 4 Metal 5 Co Ports Exports Are Node Node Frame Metal3 Metal 3 Pin Jvetal 3 Metal 4 Co Seeeeeeeevee 3D Arc Node Node Metal 2 Metal 2 Pin vetal 2 IMetal 3 Co fs Tools Are Node Node Metal 1 Metal 1 Pin Pvletal 1 Metal 2 Co F Technology Remove _ POPUP Polysilicon 2 Polysilicon 2 Pin Are Node Node
249. ell and any circuitry below that in the hierarchy e Eagle is an interface to the Eagle schematics design system its netlist format Before writing Eagle files you must give every node the ref_des attribute and every port on these nodes the pin attribute If you also place the pkg_type attribute on the node it overrides the cell name e ECAD is an interface to the ECAD schematics design system its netlist format Before writing ECAD files you must give every node the ref_des attribute and every port on these nodes the pin attribute If you also place the pkg_type attribute on the node it overrides the cell name e Pads is an interface to the Pads schematics design system its netlist format Before writing Pads files you must give every node the ref_des attribute and every port on these nodes the pin attribute If you also place the pkg_type attribute on the node it overrides the cell name e Text Cell Contents is used to write a text file from a text cell The current window must be a textual view such as VHDL Verilog documentation etc See Section 4 9 for more on text windows e PostScript is the Adobe printing language The output file contains only a visual representation of the current cell or part of that cell PostScript options can be controlled with the Printing Preferences in menu File Preferences General section Printing tab e HPGL is the Hewlett Packard printing language The output fi
250. ell as the amount of motion If you have disabled Move after Duplicate in the Nodes Preferences in menu File Preferences General section Nodes tab then the duplicated objects are placed immediately without dragging Initially they are moved by a predefined amount However Electric remembers motion that is made after a duplication and uses that offset in subsequent duplications If any of the nodes have exports on them they are not duplicated unless Duplicate Array Paste copies exports is set in the Nodes Preferences The Duplicate command forces newly created nodes and arcs to have unique names This means that if any nodes or arcs are named using the Object Properties command in menu Edit Properties and then duplicated the new ones will have different names specifically the old names with numbers appended or modified Cut and Paste Another way to make copies of nodes and arcs is with the cut and paste commands The Copy and Cut commands in menu Edit copy the currently selected nodes and arcs to a special buffer Cut also removes the objects after copying them The Paste command then copies the objects from the special buffer to the display After issuing this command an outline of the pasted objects attaches to the cursor When you click the objects are placed at that location You can right click during the paste drag to affect the location and to abort the paste Note that if you copy a node or arc a
251. ell centers e Reconstruct arcs and exports when deleting instances requests that arcs connected to cell instances be reconstructed when the cell instances are deleted These reconstructed arcs appear to be the same as before but they now connect to pins that end where the instance ports used to be In addition exports that were on deleted cell instances are moved to pins in the same location When this box is not checked arcs and exports connected to deleted instances are also deleted e Always prompt for index when descending into array nodes controls whether nodes with array specifications should be precisely tracked when descending the hierarchy see Section 3 5 for more The bottom part of the dialog applies to all nodes e Disallow modification of complex nodes requests that all cell instances transistors and other complex nodes be anchored Pins and contacts are not considered to be complex e Disallow modification of locked primitives requests that all lockable primitive node instances be anchored Once locked these nodes cannot be created deleted or modified in any way Typically only primitives in array technologies are lockable such as the FPGA technology see Section 7 6 2 presuming that these components will be used to define the fixed circuitry that is then customized Design of the fixed circuitry is done with this lock off and then the customization phase is done with this lock on e Move after Duplicate al
252. ely wider The Placement angle is the granularity for running this type of arc in degrees A value of 90 lets arcs run at 0 90 180 or 270 degrees manhattan geometry A value of 45 lets it run at any of 8 angles useful for schematics A value of 0 lets it run at any angle used in artwork The Pin is the node that gets used for connecting two of these arcs It is typically a Pin node see Section 7 1 1 If changed to a node with geometry such as a contact node then these contacts will be placed at the bends of this arc The checkboxes in the Default State section have these meanings f categories General e Rigid whether the arc is General rigid in length and Selection Technology mocmos x Key Bindings relationship to its nodes see e Node asc Type Metal 1 Section 5 2 1 e M e Fixed angle whether the Project Management Default width E arc stays at the same angle cvs i ll _ _ _ _ when one end moves see Printing Section 5 2 1 C Display Pin Metal 1 Pin x Arcs USER Preferences gt For New 4rcs i Spo e Slidable whether the arc a ee slides around in its node s Technology Default State port see Section 5 2 2 I Rigid IV Fixed ange V Slidable e Directional whether the arc has an arrow drawn on it see Section 5 4 1 Export Import For All Arcs e Ends extended whether the I Directional IV Ends extended arc extends past its
253. em Typically the most commonly used layers are transparent because it is clearer to distinguish The remaining layers in a technology are opaque meaning that when drawn they completely obscure anything underneath These layers typically have stipple patterns so that they do not cover all of the bits In this way the opaque layers can combine without obscuring the display Because opaque color does obscure everything under it the less common layers are drawn in this style When editing colors the opaque layers have only one color whereas the transparent layers have many different colors considering their interaction with other transparent layers 4 6 2 Editing Colors and Patterns The Layers Preferences in menu File Preferences Display section Layers tab controls the appearance of layers and other display elements The top of the dialog lists all of the technologies and their layers It also lists special colors at the bottom of the Layer list e BACKGROUND is the color of the background default gray e DEFAULT ARTWORK is the color of artwork primitives that have not been assigned a specific color default black e DOWN IN PLACE BORDER is the color of the cell edge when editing down in place default red e GRID is the color of grid dots default black e HIGHLIGHT is the color of highlighting default white e INSTANCE OUTLINES is the color of unexpanded cell instances default black e MOUSE OVE
254. en you can also indicate wiring between the pads and the core ports This is done by having one or more port associations in the place statements The format of a port association is simply PADPORT COREPORT For example the statement place padOut tap y Using the Electric VLSI Design System version 8 11 321 Chapter 9 Tools indicates that the tap port on the placed pad will connect to the y port on the core cell The port association can also create an export on the pad The statement place padOut export io o7 export tap core_o7 creates two exports on the pad 07 on its io port and core_o7 on its tap port For many instances of this pad type this notation can be condensed with the use of the name keyword in conjunction with exports defined for the pad at the start of the file For example defining the IO ports as export padOut io tap and then changing the place statement to place padOut name o7 results in the same ports being exported with the same names This shorted notation always prepends name with core_ on the core port export The rotate statement rotates subsequent pads by the specified amount The statement has only two forms rotate cto rotate clockwise and rotate cc to rotate counterclockwise Here is an example of a pad frame disk file with the finished layout There is a cell in the Samples library called tool PadFrame get it with the Load Sample Cells Library command in menu Help This te
255. en draw your wire Electric is agnostic about the polarity of well and substrate it generates both n and p well layers In our process that has a p substrate already the p well indicated by brown slanting lines will be ignored The n well indicated by small brown dots will define the well on the chip Electric only generates enough well to surround the n and p diffusion regions of the chip Electric creates well contacts that are only 11 units wide This will generate a DRC error but this behavior is intentional Wells should be 12 units wide to meet DRC s expectations It is a good idea to create rectangles of well to entirely cover each cell so that when you abut multiple cells you don t end up with awkward gaps between wells that cause design rule errors To do this click on the Pure entry of the Components tab and select N Well Node or P Well Node To change its size so that it entirely covers the existing well resize it with the Interactively command in menu Edit Size or just type Ctrl B You will find the pure layer nodes are annoying because you will tend to select them when you really want to select a transistor or wire To avoid this problem select them and use the Make Selected Hard command in menu Edit Selection to make the node hard to select Once an item is defined as hard to select you must use special select mode to be able to select it click on the arrow with Using the Electric VLSI De
256. ences Display section Text tab end ACC package buses is type BUSS is array 0 to 7 of BIT end buses Instead of using the built in text editor you can architecture ACC_BODY of acc is request an external text editor be used for component SENSOR_BOX port pulses reset example EMACS Do this with the Edit Text component TRANSMITTER BOX1 port eq ck Cell Externally command in menu Edit signal EQUAL BIT Text Specify the external editor to use with the Text Preferences The contents of a text window can be saved to disk with the Text Cell Contents command in menu File Export and restored from disk with the Text Cell Contents command in menu File Import Note that there is no saving of text windows because they are editing internal data structures Therefore every change updates the information in Electric but the library must be saved to truly preserve changes Using the Electric VLSI Design System version 8 11 117 Chapter 4 Display Find Text searching is done with Replace S the Find Text command in I Case Sensitive I Regular Expressions Find Reverse menu Edit Text You can Find i i Ja EAA find and or replace text with e __Replace _Replace and Find _ _ Replace al the appropriate buttons Line Number Go To Line Done Check boxes allow the search to be case sensitive have Objects to Search regular expressions and to go M Node Names M Arc Name
257. ences and two panels on the left and right for setting the Project and User aspects of the preferences If a particular preference has no User or Project part that panel does not appear The differences between User and Project preferences is e User Preferences on the right affect the user s interaction with the system Examples are printer control display colors and keyboard bindings Each user may have different preferences and it does not impact the design being done e Project Preferences on the left affect the actual circuitry being edited and so should be the same for every user who is editing that circuitry Examples are GDS layer mappings and technology scaling CIF PROJECT Preferences _ Categories CIF USER Preferences General Technology mocmos 7 Fl Display TEEN Eglo Metal 1 CMF CMF Metal 3 CMT P Output Mimics Display el Metal 4 CMQ A AEE Metal 5 CMP Output Merges Boxes I Input Squares Wires 5 Export Import Metal 6 CM6 time consuming Polysilicon 1 CPG R j eset Reset All Polysilicon 2 CEL IV Output Instantiates Top Level P Active CAA Only resets USER Preferences N Active CAA Hel Appl P Select CSP Output scale fi z ll N Select CSN gt Cancel The Preferences dialog is modeless meaning that it can remain on the screen while other work is done For this reason the dialog has an Apply button so that changes can be made without dismissing the dialo
258. ened Polygon node has 4 points already you should be able to form the C shape simply by clicking and dragging these points Outline edit mode is not entirely intuitive at first but you will master it with practice When done use the same command to exit the mode just type y See Section 6 10 1 for more on outline editing Electric is finicky about moving the lines with inputs or outputs If you click and drag to select the line along with the input everything moves as expected If you try to move only the export name it won t move as you might expect Therefore make a habit of moving both the line and export simultaneously when editing icons For appearance remove the thin export connector lines Replace these with bold black lines You can easily do this by left clicking on a wire of the icon then right clicking placing the cursor where you want the end point of the wire to be Electric draws a wire that extends from the artwork of the icon Use the Text item in the Component menu to place a label nand2 in the icon Make the text be 2 units high Now that you have an icon with three exports create a new schematic called and2 don t forget to set the view to schematic Use the Place Cell Instance command in menu Edit to instantiate a nand2 ic and an inv ic Wire the two together and create exports on inputs a and b and output y Double click on the wire between the two gates and give it a name like yb
259. ength B Lead spacing 2 IV Draw body Text size 2 P Make exports Always Drawn Export location Lead End Export Import Export style Centered Reset Reset Al Export technology Schematic Only resets USER Preferences Instance location Upper right Help Apply Cancel Current cell ptest sch Make Icon Using the Electric VLSI Design System version 8 11 89 Chapter 3 Hierarchy The top part of the dialog lets you control where exports are placed You may choose to place them according to their characteristics input output etc or to place them relative to their location in the schematic cell When placed by characteristics exports are arranged alphabetically around the icon and you can choose to reverse the alphabetical order Text can be rotated in any of four directions When placed by location in the cell you can request that the exact location of schematic exports be used in the icon The middle section of the dialog controls the body and leads of the icon You can choose whether or not to draw the body and leads You can set the spacing and length of leads You can control the size of the text used on the cell body You can request that exports be Always Drawn which means that they appear even when wired or reexported see Section 3 6 1 You can choose the location of the exports at the end of the leads in the middle of the leads or on the body You can choose the style of the export text wh
260. ent be written at the end of the deck This can be disabled in situations where the deck is part of a larger Spice deck e Use Header cards from files with extension specifies that header cards placed at the start of the Spice deck can be found in a file with the cell s name and the given extension e Use Header cards from file lets you specify the file with header cards e No Header cards prevents any header cards from being written to the Spice deck e Use Trailer cards from files with extension specifies that trailer cards placed at the end of the Spice deck can be found in a file with the cell s name and the given extension e Use Trailer cards from file lets you specify the file with trailer cards e No Trailer cards prevents any trailer cards from being written to the Spice deck 278 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools Note that the header and trailer information is specific to a particular technology If you set this information for one technology but then use another technology when generating the Spice deck the information that you set will not be used Note also that schematics although a technology in Electric are not considered to be Spice technology You can set the proper layout technology that you want to use when dealing with schematics by using the Layout technology to use for schematics popup This popup can be found in the Technology Preferences in menu File Preferences Technolo
261. ent layers and provides the color of each The system automatically determines the blending colors where multiple transparent layers overlap Example lt transparentLayer transparent 1 gt lt r gt 96 lt r gt lt g gt 209 lt g gt lt b gt 255 lt b gt lt transparentLayer gt e lt layer gt a list of layer descriptions see below e lt arcProto gt a list of primitive arc descriptions see below lt primitiveNode primitiveNodeGroup gt a list of primitive node and primitive node group descriptions see below e lt spiceHeader gt default spice models e lt menuPalette gt description of the default component menu optional Using the Electric VLSI Design System version 8 11 239 Chapter 8 Creating New Technologies e lt foundry gt information for the Foundry Each has default DRC rules and default GDS mapping Layers The lt layer gt elements define layers in the technology They contains these attributes e name the name of this layer Layer names are not referenced in Library files They are used only in the description of primtive nodes and arcs and in DRC rules e fun the function of this layer taken from this list UNKNOWN METAL1 METAL2 METAL3 METAL4 METALS METAL6 metal METAL7 METAL8 METAL9 METAL10 METALI1 METAL12 metal POLY 1 POLY2 POLY3 polysilicon GATE gate polysilicon DIFF DIFFP DIFFN active IMPLANT IMPLANTP IMPLANTN SUBSTRATE WELL WELLP WELLN implants CONTACT1 CONTACT2 CONTACT3 CON
262. enter of Selection command from menu Edit Move Schematic Instances When drawing schematics you place instances of the icon cell not the schematics cell An icon cell can be automatically created with the Make Icon View command in menu View see Section 3 11 4 The icon cell can then be edited to have any appearance see Section 7 6 1 Using the Electric VLSI Design System version 8 11 63 Chapter 3 Hierarchy 3 4 Examining Cell Instances When instances are initially created they are drawn as black boxes with nothing inside This form of instance display is called unexpanded When the instances show the actual layout inside of them they are expanded This distinction applies only in layout schematic icons never show their actual contents To expand a cell instance select it and use the commands of the Cell Expand Cell Instances menu The One Level Down command opens up the next closed level the All the Way command opens up all levels to the bottom and the Specified Amount lets you type a number of levels of hierarchy to expand These commands expand all highlighted cells If a highlighted cell is already expanded this command expands any subcells inside of the instance repeatedly down the hierarchy Once expanded a cell instance will continue to be drawn with its contents shown until the commands of the Cell Unexpand Cell Instances command are used These commands return cell instances to their black box form
263. entry under Spice it has 7 parameters ccysS There are both voltage and current sources in AC and DC form There is a DCCurrent piecewise linear PWL source and two pulses voltage and current A set of DCVoltage two gate devices are also available CCCS CCVS VCCS VCVS and DiffAmp Transmission Extension NodeSet It is possible to specify Transient DC or AC analysis by using the Transient Pw Analysis DC Analysis and AC Analysis subcommands The Probe lets Probe you graphically specify signals of interest to Spice Only one such element may Pulse exist in a circuit PulseCurrent Transmission CCS CVS For advanced users there are two special Spice nodes Node Set and Extension The Node Set may be parameterized with an arbitrary piece of Spice code Truly advanced users may create their own Spice nodes by modifying the cells in the Spice library see next Section Spice Text This example also shows the ability to add arbitrary text to the Spice deck as shown in the lower right To create this text use the Spice Code or Spice Declaration entries under the Misc button in the component menu These command create text that can be modified arbitrarily Whatever the text says will be added to the Spice deck declarations go near the top Another option that can be used when modeling transistors and other component is to set a specific Spice model to use for that component To set a no
264. er 3 Ej 70 250 70 Set Remove define as many colors as you have used in the layers Add 230 Using the Electric VLSI Design System version 8 11 Chapter 8 Creating New Technologies Design Rules Unfortunately it is not possible to edit design rules associated with the technology However you can add design rules to the XML files produced by the technology editor To do this examine the XML files for some existing technologies for example CMOS and copy these lines to the new XML file editing where appropriate for layer names and spacings The Component Menu Technology Edit Component Menu Layout Ed mocmos Component menu 3 by 13 anes ined vetal 1 P Well C Bvietal 1 N Well C jetal 3 Metal 4 CMetal 4 Ivietal 5 GMetal 5 Metal 6 C Transistor Sca IfMetal 1 IMetal 2 CMetal 2 Metal 3 C hick P Transistoffhick N TransistofP Transistor Scal Pa rar wetal 1 Polysilicof _P Tran sistor N Transistor Node Node Node Cels none Ee P Active Pin N Active Pin fetal 1 P Active Metal6 Pin Polysilicon 1 Pin Polysilicon 2 Pin Metal 3 Pin Metal4 Pin Metal 5 Pin Are Node Node Remove Are Arc Are Metal4 Metal 5 Metal 6 Are Arc Are Add Row Below Current _ Node entry Metal 1 Polysilicon 1 Con Delete Row With Current Add Column to Right of Current Angle jo Delete Column With Current Function contact Label OK Cancel To customize the layout of the component menu use
265. er 9 Tools The netlist describes a system where ASCII characters are represented by 0x01 Ox7F The value 0x00 indicates there is no data in the channel and the value OxFF indicates a corrupted character It is assumed that there is an external data source which supplies characters to the channel input It should be noted that the random declaration is placed on only one of the two gate descriptions rather than both of them Unpredictable events occur if the random declaration is placed on both gate descriptions The Fanout Statement The fanout statement is used to selectively enable disable fanout calculations for a gate when the database is being compiled The format for a fanout statement is shown below Format fanout on or fanout off When fanout calculation is enabled the default setting for all gates the simulator scans the database and determines the total load that the gate is driving It then multiplies the gate timing parameters by an amount proportional to the load If an inverter gate was found to have a propagation delay time of 1 nanosecond when driving a single inverter input an instance of that gate would have a propagation delay time of 3 nanoseconds if it was driving a load equivalent to 3 inverter inputs If fanout calculation is turned off for a gate primitive fanout calculations for all instances of that gate will be ignored This feature allows the user to force switching times to a particular value and not have t
266. er is the ERRORS section This lists all errors that were generated by other tools DRC ERC NCC etc and which can be examined with the lt and gt keys The third section of the explorer is the JOBS section Here are listed all running tasks in Electric The section is usually empty but if multiple jobs are running at the same time you can examine and manipulate them Many special functions can be done in the cell explorer You can double click on any cell name to see that cell in the right half of the window You can drag a cell or cell group from one library to another This makes a copy of that cell or group in the destination library 102 Using the Electric VLSI Design System version 8 11 Context Menus for Libraries Chapter 4 Display There are special context menus available by right clicking on an entry use command click on the Macintosh The context menu for the LIBRARIES icon has 5 parts The top three entries let you control the expansion of the tree The next entry lets you create a new cell The next three entries lets you view the libraries in different ways explained above The Evaluate Numbers when Sorting Names checkbox is explained in Section 3 7 1 The bottom entries lets you search for cells by name and get information about the library vr FE Open Open all below here Close all below here Create New Cell Show Cells Alphabetically Show Cells by Group Show Cells by Hiera
267. er than a specified limit In addition to examining geometry the design rule checkers use connectivity information to help find violations This use of network information helps the designer to debug circuit connectivity For example if two overlapping nodes are not joined by an arc they may be considered to be in violation even if their geometry looks right This is because the checkers know what is connected and have a separate set of rules for such situations To help guide the design rule checker an exclusion layer can be placed over areas that are not to be examined This exclusion layer is created by clicking the Misc entry of the component menu and selecting DRC Exclusion see Section 7 6 3 Any errors that fall inside of this _ Categories C General F Display Design Rules USER Preferences Design Rules For Technology mocmos with Foundry MOSIS Node Rules yo Tools Technology Added Technologies Technology Design Rules Min Size Rule Width Height ofl Layer Rules From Layer Min Value Rule fs P 1 Mosis Size node s area are ignored Metal 2 w Area 4 Enclosure Area fT To edit the design rules use ae To Layer I Show only to entries with rules the Design Rules Pref j File Normal Distance Rule references in menu File sian conected E 7 2 Most SUM Preferences Technology section Design Rules tab The di
268. er to manipulate hierarchical circuits it is useful to create and delete levels of the hierarchy The Package Into Cell command in menu Cell collects all of the highlighted objects into a new cell You will be prompted for the cell name To package everything in an area use the Area Selection commands see Section 2 1 3 When packaging an area every node touching the area and all arcs between nodes in the area are included in the new cell Packaging does not affect the highlighted circuitry However after packaging circuitry into a new cell that circuitry can be deleted and replaced with an instance of the cell The opposite function is the removal of levels of hierarchy This is done with the Extract Cell Instance subcommands in menu Cell which takes the currently highlighted cell instances and replaces them with their contents The One Level Down subcommand just replaces the selected instances with their contents The All the Way subcommand continues to extract instances inside of instances until there are no more instances just primitives The Specified Amount prompts for a number of levels of hierarchy and extracts that many levels deep All arcs that were connected to the cell instances are reconnected to the correct parts of the instantiated circuitry Using the Electric VLSI Design System version 8 11 77 Chapter 3 Hierarchy 3 9 Libraries 3 9 1 Introduction A library is a collection of cells that forms a consistent
269. erences in menu File Preferences Tools section Network tab and choose Ascending or Descending For information about the Node Extraction portion of the Network Preferences see Section 9 10 2 Preferences Network PROJECT Preferences _ Categories Network USER Preferences C General Display Default bus order Ascending 0 N Mayo Descending N 0 Tools Node Extraction Antenna Rules I Grid align geometry before extraction Compaction Coverage I Approximate cut placement DRC Fast Henry I Ignore polygons smaller than 0 25 square units Logical Effort NCC IV Include date and version in output files Network Ignore Resistors when building netlists 7 Use pure layer nodes for connectivity zj Active Handling adh Require separate N and P active require proper select well Export Import C Ignore N vs P active require proper select well C Require separate N and P active ignore select well Reset Reset All Only resets USER Preferences Flatten cells whose names match this Kin Help Apply va IV Flatten Cadence Pcells with number at end of name Cancel Individual wires that connect to a bus must be named with names from that bus As an aid in obtaining individual signals from a bus the Rip Bus command in menu Edit Arc will automatically create such wires for the selected bus arc To find out what signals are on a bus select that bus a
270. ers it is separate Below the pulldown menu is a tool bar which has buttons for common functions Finally the status area gives useful information about the design state It appears along the bottom of the editing window or in this example at the bottom of the screen The status area shows cursor coordinates and can show global coordinates when traversing the hierarchy see Section 4 3 12 Using the Electric VLSI Design System version 8 11 Chapter 1 Introduction 1 8 The Mouse Electric makes use of only two mouse buttons left and right On systems with three button mice the middle button pans the display On Macintosh systems with only one button the right button is obtained by holding the Command key when clicking Left Click SHIFT Left Click CTRL Left Click Cycle through selected objects CTRL SHIFT Left Click Cycle through objects to Invert Left Double Click Fett Drag Move selected objects Move selected objects CTRL Left Drag Raa Ta Right Click Draw or Connect Wire _ Wheel Up Down Sero Up Down By combining special keystrokes with the mouse functions advanced layout operations can be done e Switch Wiring Targets Hit Space while holding the Right mouse button to switch between possible wiring targets under the mouse e Switch Layers Hit a number between 7 6 to switch layout layers Additionally if you have a port highlighted that can connect to the new layer a contact cut will be cre
271. ersonality file You will be prompted for the personality file The first line of the ROM personality file lists the degree of folding For example a 256 word x 10 bit ROM with a folding degree of 4 will be implemented as a 64 x 40 array with 4 1 column multiplexors to return 10 bits of data while occupying more of a square form factor The number of words and degree of folding should be a power of 2 The remaining lines of the file list the contents of each word The parser is pretty picky There should be a carriage return after the list word but no other blank lines in the file Here is a sample ROM file 1 010101 011001 100101 101010 4 00000000 10000000 01000000 11000000 e MOSIS CMOS PLA Generator The MOSIS CMOS PLA generator reads two personality files AND and OR and generates a PLA array Each file has only two numbers on the first line to define the size of the array and the values of the array on subsequent lines Both the AND file and the OR file are similar Here is some sample PLA logic 0 0 0 0 f a and b and not c or not b and not a g a and c or not a and not c Here is the AND file for the above logic 4 3 OrROFR O H Oo xx OF 324 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools e Fill MoCMOS Fill cells are used to meet metal density rules in modern fabrication processes by filling spaces with certain metal layers Fill cells are also created to
272. erter Using the Electric VLSI Design System version 8 11 333 Chapter 9 Tools 9 10 Extraction 9 10 1 Parasitic Extraction Parasitic Extraction is used by netlisters and other parts of the system that need to know about geometric factors Control of parasitic extraction is done with the Parasitic Preferences in menu File Preferences Tools section Parasitic tab Preferences __ Categories Parasitic USER Preferences 4 General Display Technology mocmos v aie Individual Layers ___ Tools Antenna Rules Compaction Coverage DRC Fast Henry Logical Effort NCC al Network Resistance 0 078 Parasitic PROJECT Preferences Layer Simple Parasiticts IV Use verbose Naming I Back Annotate Layout P Extract Power Ground Ioi Area Cap fF um 2 0 1209 Placement rea Cap fFfum 2 fo Routing Perimeter Cap FF um fo 1104 Silicon Compiler Simulators Spice Min Resistance 4 0 Spice Model Files C Extract only exempted nets Min Capacitance FF fo 1 os Export Import ji w IV Extract R IV Extract C I Use exemptedNets txt file For All Layers fe Extract all bub exempted iets eeeeeeee e808 0 4 Max Series Resistance fio 0 Reset Reset All P Include Gate In Resistance Only resets USER Preferences Help Apply Include Ground Network Cancel Gate Length Shrink Subtraction um fo ik gu
273. es separate Java threads for all activities Because of this if the system encounters an error it aborts the thread but the main program continues to run If a thread crashes and leaves a Job running then you will not be able to issue other commands because their Jobs will be queued behind the stuck one see Section 4 5 2 for more viewing Jobs Even the Quit command is a job and so it cannot run To solve this problem use the Force Quit and Save command in menu File If you suspect that the database is corrupt use the subcommands of the Check Libraries command in menu File The Check command examines the database but does not fix errors The Repair command checks and repairs the database if it can Using the Electric VLSI Design System version 8 11 183 Chapter 6 Advanced Editing 184 Using the Electric VLSI Design System version 8 11 Chapter 7 Technologies 7 1 Introduction to Technologies 7 1 1 Technologies A technology is an environment in which design is done Technologies can be layout specific for example MOSIS CMOS or they can be abstract for example Schematics and Artwork There are multiple CMOS variations to handle popular design rules such as MOSIS submicron etc Each technology consists of a set of primitive nodes and arcs These in turn are constructed from one or more layers Each technology also includes information necessary to do design such as design rules connectivity rules simulatio
274. esign System version 8 11 Chapter 6 Advanced Editing Layout Image x Image file name I Width of smallest dot Z To generate images in layout use the Layout Image command width of largest dot faz Nea sas under the Misc entry in the component menu This dialog Minimum gutter between dots fis prompts for an image file and a layer to use as well as other factors in generating the image Layer Metal 1 Node P Reverse video I Monochrome Cancel _oK Using the Electric VLSI Design System version 8 11 173 Chapter 6 Advanced Editing 6 11 Interpretive Languages Electric has two scripting languages Java using the Bean Shell and Python using Jython These languages enable you to load custom code that adds functionality to Electric Neither of these languages is part of the default Electric distribution You must add them as plug ins see Section 1 5 for more on plug ins To run a Java script use the Run Java Bean Shell Script command in menu Tools Languages To run a Python script use the Run Jython Script command Scripts 3 You can attach a script to the Tools Add Script w C DevelE Electric TESTLIBS BeanShellSample bsh Languages menu by using the Manage t C DevelE Electric TESTLIBS ToggleSelectionEnclosure bsh Mnemonic k Scripts command Scripts can have Remove Script Cancel ee mnemonic letters assigned to them see Section 1 9 for more on
275. et of high level primitives transistors and contacts which have their own ways of appearing in the layout Therefore it is not always possible to extract layout precisely For example the design rules for a transistor typically require that polysilicon extend beyond the gate area by 2 units so transistor primitives typically have this extra geometry built into them But what would happen if the geometry to be extracted extends by 3 units Electric adds an extra 1 unit arc to fill out the geometry that it finds Worse yet what would happen if the geometry extends by only 1 unit Electric simply cannot represent this with its primitives It will create the transistor but it will no longer match the original geometry In general the system attempts to create high level primitives that mimic the original geometry It often leaves small pure layer nodes behind to complete the extraction As an aid in debugging the extraction process these extra pure layer nodes are highlighted in the resulting cell Control of node extraction is done with the Network User Preferences in menu File Preferences Tools section Network tab D Preferences x Network PROJECT Preferences _ Categories Network USER Preferences General E Display Default bus order Ascending 0 N 3 fo Descending N 0 Tools Node Extraction Antenna Rules Compaction I Grid align geometry before extraction Coverage I Approximate cut placement DRC
276. ether it grows inward outward The bottom part of the dialog has miscellaneous controls You can choose the technology of the exports Schematic uses nodes from the Schematic technology and can connect only to other Schematic arcs Universal uses nodes from the Generic technology which can connect to any arc You can choose the location of the example icon instance in the original schematic when you use the Make Icon View command it generates the icon and places an example instance of that icon in the schematic One of the choices is No Instance which prevents placement of example icons A button at the bottom requests that an icon be made now and takes the place of the Make Icon View command The icon cell is correctly tied to its contents in most respects If you descend into it with the commands in the Cell Down Hierarchy menu then you actually find yourself editing the associated contents cell The Up Hierarchy command properly returns you to the location of the icon instance Also the network consistency checker and the simulators correctly substitute the contents whenever an icon appears In order for this to work however all exports in the contents cell must exist with the same name in the icon cell with the exception of those that are marked Body Only 90 Using the Electric VLSI Design System version 8 11 Chapter 4 Display 4 1 The Tool Bar The tool bar sits near the top of the screen below the menu bar It
277. ew technology to the old name and then saving the library Finally modifying miscellaneous information is typically transparent changed information appears in all existing libraries and affects those subsystems that make use of the information For example a change to the Spice resistance will be seen when a Spice deck is next generated Using the Electric VLSI Design System version 8 11 233 Chapter 8 Creating New Technologies 8 9 Examples of Use To fully understand technology editing some examples are appropriate Two examples will be given a simple one that modifies the appearance of a pattern and a more complex example in which a new primitive node is created Both examples are based on the MOSIS CMOS technology so they presume that the Convert Technology to Library for Editing command in menu Edit Technology Editing has been issued and the mocmos entry was selected Example Modifying a Layer s Appearance In this first example the user simply wishes to change the Metal 2 layer from a solid fill to a stipple pattern This particular task is so basic that it can be done with the Layers Preferences but it illustrates the basic steps of making a change First edit the layer cell for metal 2 The display will show the layer with all of its associated information Function metal 2 Color 224 95 255 0 7 on Stipple Pattern Transparency layer 4 Style solid New drawing style For this layer Cancel
278. example here and make sure its view is schematic View layout compensated VHDL A new empty cell will appear in a separate window Try Verilog creating a few simple nodes in this new window place a documentation gate or two documentation waveform x Technology mocmos v Cancel V Make new window Library noname OO View a Filter Now place an instance of the other cell by using the Place Cell Instance command in menu Cell You can also click the Cell entry in the component menu You will be given a list of cells to create select the one that is in the OTHER window the one called MyCircuit ic in this example Then click in the newer cell to create the instance JV Evaluate Numbers when Sorting Names Cancel New Instance amp Close The icon that appears is a node in the same sense as the Buffer and And gate it can be moved wired and so on In addition because the node contains subcomponents you can see its contents by selecting it and using the Down Hierarchy command in menu Cell Down Hierarchy Note that if the objects in a cell no longer fit in the display window use the Fill Window command in menu Window tty Circuit Oy 1 11 8 Schematics Tutorial Final Points Some final commands that should be mentioned in this introductory example are the Save Library and the Quit commands which can be found in the File menu They do the obvious things 30 Using the Electric VL
279. f signal names Reset Reset All Only resets USER Preferences Help Apply Cancel gu 198 Using the Electric VLSI Design System version 8 11 Chapter 7 Technologies 7 3 7 DXF Control DXF Drawing eXchange Format is a solid modeling format used by AutoCAD systems For more information on reading and writing DXF see Section 3 9 2 and Section 3 9 3 respectively DXF I O is controlled with the DXF Preferences in menu File Preferences I O section DXF tab The Project Preferences part of the dialog controls the list of acceptable DXF DXF PROJECT Preferences layers These layers can be typed into the edit field separated by commas If a layer amp name in the DXF file amp is not found in the list DXF Input will accpt all of these layers of acceptable layers it separate layer names with a comma CDL a a will be ignored esr o i i DXF Output will use the first layer in the list IV Input reads all layers To control scaling you Export Import an chan i can c ge the DXF Scale MicroMeter v FERR Reset All meaning of units in the Only resets USER Preferences DXF file The default pda ies unit is Muillimeters Help Apply which means that a value of 5 in the DXF _ cancel file becomes 5 millimeters in Electric _ Categories DXF USER Preferences General Display 6 9 Ho H CIF GDS EDIF DEF IV Input flattens hierarchy
280. f bold dots fio fio Show X and Y axes Grid dot spacing For current window Alignment of Cursor to Grid Horizontal C Size 1 largest 20 C Size 2 fio m T Size 5 smallest j0 5 Vertical C Size 3 Size 4 Values of zero will cause no alignment There are 5 alignment values all settable in the dialog The current alignment setting is shown in the toolbar see Section 2 4 1 Note that these alignment values are also used to determine the distance moved by arrow keys You can change the alignment setting with the commands Grid Alignment 1 largest Grid Alignment 2 Grid Alignment 3 Grid Alignment 4 and Grid Alignment 5 smallest in menu Edit Modes Movement You can also change the alignment by a single step by using the commands Make Grid Larger attached to the f key and Make Grid Smaller attached to the h key The Align to Grid command in menu Edit Move cleans up the selected objects by moving them to aligned coordinates This is useful for circuitry that has been imported from external sources and needs to be placed cleanly for further editing 112 Using the Electric VLSI Design System version 8 11 Chapter 4 Display 4 7 3 Aligning to Objects It is often the case that a collection of objects should line up uniformly The commands of the Edit Move menu offer six possible ways to do this The command Align Horizontally to Left and Alig
281. f geometry that is centered in the example contact cuts are good choices This piece of geometry must be named using the Object Properties command in menu Edit Properties The name on the piece of geometry will be the name of the variation e The only rule used to compute layer size is the distance from the outer edge It is not possible to use other stretching rules because only one example is being provided The picture shown here illustrates a variation in which the polysilicon layer is inset The text Small Poly is the name of the cut node moved up to make it readable Lockadle Na Spice template Small Paty Special Node Considerations There are some special cases available in node descriptions A piece of geometry in the main example may be changed by double clicking on its function to SET MINIMUM SIZE This indicates that the current size is the smallest possible and it cannot scale any smaller this is used by the mocmos technology for the metal layer in contacts The restriction can be removed with the CLEAR MINIMUM SIZE description This option cannot be used in serpentine transistors 228 Using the Electric VLSI Design System version 8 11 Chapter 8 Creating New Technologies Another special case in node description is the ability to specify multiple cut layers If the larger examples have more cut layers rules are derived for cut spacing and indentation so that an arbitrary numbers of cuts can
282. f pure layer nodes overlap each other use Show Redundant Pure Layer Nodes to identify those that are enclosed by others and therefore are redundant 170 Using the Electric VLSI Design System version 8 11 Chapter 6 Advanced Editing 6 10 2 Manipulating Outlines To manipulate outline information on the currently highlighted node use Outline Edit mode click on the icon in the tool bar or use the Toggle Outline Edit command in menu Edit Modes Edit In this mode there is always a current point identified with an X over it To further identify this point the lines coming into and out of the point have arrows on them indicating the direction of the outline In outline edit mode the left button is used to select and move a point on the outline and the right button adds a new point after the selected one Besides selecting points with the mouse you can also step through the points of the outline with the key next outline point and key previous outline point These keys are under the gt and amp lt keys so you can think of them as the next point gt and previous point lt commands The Selected command in menu Edit Erase deletes the current outline point this is the Delete key When the Object Properties command is issued in outline edit mode a special dialog appears to show the point coordinates of the outline x 1 63 5 Delete Point we 7 5 Duplicate Point
283. f signal names that can be placed in the list If there is not enough room on a single line to accommodate all the names simply continue the list on the next line The i and o Statements Input and Output The i and o statements are used to construct a logical truth table for a gate primitive The signal names and logical assertions which follow the i statement represent one of many possible input conditions If the logic states of all the input signals match the conditions specified in the i statement the simulator will schedule the outputs for updating as specified in the corresponding o statement The logical truth table for a two input AND gate is shown below gate and2 inl in2 output i inl H in2 H o output H i inl L o output L i in2 L o output L i o output X The last line of the truth table represents a default condition in the event that none of the previous conditions are valid e g inl H and in2 X It should be noted that the simulator examines the input conditions in the order that they appear in the truth table If a valid input condition is found the simulator schedules the corresponding output assignments and terminates the truth table search immediately 288 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools Signal References in the i Statement Besides testing the logical values of a signal the i statement can also compare them numerically The format of a signal references whic
284. from VHDL descriptions gives Electric a powerful facility for creating testing and constructing complex circuits from high level specifications See Section 9 12 for more on the Silicon Compiler Behavioral Models When the VHDL for a circuit is compiled into a netlist both connectivity and behavior are included This is because the netlist format is hierarchical and at the bottom of the hierarchy are behavioral primitives Electric knows the behavioral primitives for MOS transistors AND OR NAND NOR Inverter and XOR gates Other primitives can be defined by the user and all of the existing primitives can be redefined To create or redefine a primitive s behavior simply create the net als view of the cell with that primitive s name Use the New Cell command in menu Cell and select the netlist als view For example to define the behavior of an ALU cell edit alu net als and to redefine the behavior of a two input And gate edit and2 net als The compiler copies these textual cells into the netlist description whenever that node is referenced in the VHDL The netlist format provides three different types of entities model gate and function The model entity describes interconnectivity between other entities It describes the hierarchy and the topology The gate and function entities are at the primitive level The gate uses a truth table and the function makes reference to Java coded behavior which must be compi
285. g The Preferences dialog also has Export and Import buttons for saving Preferences to an XML file this function is also available from the File Import and File Export menus Use the Help button to see the page in the user s manual that explains the current panel Finally the Preferences dialog has a Reset button for resetting the current User Preferences panel to its factory default state and a Reset All button for resetting all User Preferences to their factory default state Note that Project Preferences are not affected by the reset buttons 146 Using the Electric VLSI Design System version 8 11 Chapter 6 Advanced Editing Where Preferences Are Stored All Preferences are stored permanently on your computer and are remembered each time you run Electric The actual location of this information varies with each operating system e Windows In the registry Look in HKEY_CURRENT_USER Software JavaSoft Prefs com sun electric e UNIX Linux In your home directory Look in java userPrefs com sun electric e Macintosh In your home directory under Library Preferences Look at Library Preferences com sun electric plist You can delete the appropriate data to reset Electric to its factory state To save your preferences to disk for saving and transporting to other systems use the Export button in the Preferences dialog or use the Preferences commands in menu File Export This will write an XM
286. g the right button removes the measurements The measurement text is scaled by the global text scale see Section 6 8 4 The measured distance can be used by the Array command in menu Edit to specify spacing see Section 6 4 Measuring in a Waveform Window When waveform windows are measured the display shows a rectangle with low and high time values as well as low and high waveform values Each new click drags out a different measurement Use the right click to clear all measurement displays in the panel Using the Electric VLSI Design System version 8 11 113 Chapter 4 Display 4 8 Printing To make a paper copy of the contents of the current window use the Print command in menu File You can use the Page Setup command for general print settings As an alternative to printing you can request the system to write a PostScript HPGL or PNG file To do this use the PostScript HPGL and PNG Portable Network Graphics commands in menu File Export To print a waveform window use there are special commands in the Window Waveform Window submenu that invoke gnuplot which must be installed already e Plot Simulation Data as PS creates a PostScript file with the simulation data e Plot Simulation Data On Screen shows the simulation data in a Gnuplot window Finally it is always possible to do a screen capture in order to get a copy of the image The following table shows the tradeoffs between the d
287. ge at the top of the dialog shows the current state of the toolbar This can be manipulated by dragging icons within the dialog To add a new toolbar button drag a command from the list at the bottom to the toolbar image at the top To insert a separator drag the Sep to the toolbar image To remove a toolbar button or separator drag it from the toolbar image at the top to the trash icon To rearrange the toolbar drag the buttons within the toolbar image Preferences Preferences Toolbar USER Preferences General Display Display Control l h HQ EN FO Saker o a gt Component Ment Layers Toolbar To add commands drag them from the Commands to the Toolbar 00DA Text To remove commands drag them from the Toolbar to the trash To add separators drag the Sep icon to the Toolbar Smart Text Grid To rearrange icons drag them around the Toolbar Ports Exports Commands E Edit aj 2 Edit Cut i Export Import 9 Edit Copy 2 Edit Paste Reset Reset All so 9 Edit Duplicate Only resets USER Preferences WA Edit Undo Help Apply f Edit Redo x Cancel Attach Image to Command Most commands in Electric do not have icons associated with them You can drag these commands to the toolbar but they will all show a To add an icon to a command select the command from the list at the bottom click the Attach Image to Command button and choose an image fi
288. gmented with an outline which is a polygonal description Metal s Node Metal 4 Node There are quite a few primitive nodes that make use of outline information The ees MOS transistors use the outline to define the gate path in serpentine P Active Node configurations see Section 7 4 1 The Artwork technology has nodes that use eos outline information Opened Solid Polygon Opened Dotted Polygon ae Opened Dashed Polygon Opened Thicker Polygon Closed Polygon N Select Node Filled Polygon and Spline see Section 7 6 1 Poly Cut Node Active Cut Node For arbitrary shapes on arbitrary layers use the pure ayer nodes in the IC Vie 1 Node layout technologies The pure layer nodes are found under the Pure entry in Vie 2 Node the component menu For example the node called Metal 1 Node in the ies texte CMOS technologies looks like a rectangle of the Metal 1 until you add outline cena YVel Node information With an outline this node can take any shape It is even possible to have multiple disjoint outlines in a single pure layer node users cannot create this situation but some tools such as GDS import can Passivation Node Pad Frame Node Poly Cap Node P Active VVell Node Transistor Poly Node Silicide Block Node Because pure layer nodes are unusual it is useful to be able to identify them Use the Show Pure Layer Nodes command in menu Edit Cleanup Cell to highlight all of them in the current cell I
289. gs Use Above Settings e i is done or a individual basis or for all settings that conflict Using the Electric VLSI Design System version 8 11 147 Chapter 6 Advanced Editing 6 4 Making Arrays If one copy is not enough Electric has a command for building an array of circuitry The Array command in menu Edit takes the currently highlighted objects and replicates them many times You specify the number of replications in the X and Y directions and the geometry is arrayed Arbitrary expressions can be used in this dialog for example 3 4 1 Aray Oy x P Flip alternate columns x repeat Factor fi Stagger alternate columns Arrays are generated by X row with Y Corker about original column following a raster scan order If you request that alternate rows or columns Flip alternate rows be flipped then they are mirrored in the Y repeat factor fi Stagger alternate rows direction of repetition If you request that alternate rows or columns be staggered then each element is offset by an alternating amount If you request that the X edge overlap lo rows or columns be centered then the Y edge overlap lo I Center about original Space by edge overlap Space by centerline distance original circuitry will be placed in the Space by cell essential bound middle of the array instead of the corner If C Space by last measured distance the X or Y values are negative then the aa Linear di
290. gy tab see Section 7 1 2 The middle part of the dialog controls how Spice can be run after a deck has been written e After writing deck Electric can create an external process as specified by the user to run Spice on the generated netlist If the pull down box is set to Don t Run nothing is done If the pull down box is set to Run Ignore Output the external process is run and the user is notified when it is finished If set to Run Report Output a dialog box is opened to show the user the output produced by the process Please note that this is a process and not a command line command For example echo blah gt file will NOT work Encapsulate it in a script if you want to do such things e Run program Identifies the Spice program to run e With args the arguments passed to the program e Use dir if specified this is the working directory of the program e Overwrite existing file no prompts this will overwrite the existing netlist without prompting the user e Run probe this will run the waveform viewer on the output of the Spice run e Help tells which environment variables are exported to be used by the process The following variables are available to use in the program name and arguments e WORKING_DIR The current working directory e USE_DIR The Use Dir field if specified otherwise defaults to WORKING_DIR e FILENAME The output file name with extension e FILENAME_NO_EXT The output file name withou
291. h trP getDefHeight newCell Orientation R T1 place a metal Active contact PrimitiveNode coP tech findNodeProto Metal 1 P Active Con NodeInst maP NodeInst makeInstance coP new Point2D Double 8 20 coP getDefWidth coP getDefHeight newCell wire the transistor to the contact ArcProto aP tech findArcProto P Active ArcInst makeInstance aP tP findPortInst diff bottom maP findPortInst metal l p act export the contact com sun electric database hierarchy Export newInstance newCell maP findPortInst metal 1l p act IN PortCharacteristic IN Using the Electric VLSI Design System version 8 11 175 Chapter 6 Advanced Editing Python Script Examples from com sun electric database hierarchy import Cell from com sun electric database topology import NodeInst from com sun electric tool import Job from java util import Iterator get the current cell c Job getUserInterface getCurrentCell find all transistors it c getNodes while it hasNext ni it next if ni getFunction isTransistor print Found transistor ni describe 0 find all exports that start with A it c getPorts while it hasNext e it next if e getName lower startswith a print Found export e getName from com sun electric database hierarchy import Cell from com sun electric database hierarchy import Library fr
292. h follow the i statement is show below Format or Operators Example signal lt operator gt state_value signal lt operator gt other_signal Test if equal Test if not equal lt Test if less than gt Test if greater than nodel H input1 input2 There is no limit on the number of signal tests that can follow an i statement If there is not enough room on a single line to accommodate all the test conditions the user can continue the list on the next line of the netlist Signal References in the o Statement The signal references which follow the o statement are used as registers for mathematical operations It is possible to set a signal to a logic state and it is possible to perform mathematical operations on its contents The format for signal references which follow the o statement is shown below Format Operators Strengths Example signal lt operator gt operand lt strength gt equate signal to value of operand increment signal by value of operand decrement signal by value of operand multiply signal by value of operand divide signal by value of operand modulo signal by value of operand 0 off 1 node 2 gate 3 VDD qbar H 3 outl 3 out out 4 It should be noted that the logic state of the operand can be directly specified such as H 3 or it can be indirectly addressed through a signal name such as out1 modulus_node In the indirect addressing case
293. h occur on a percentage basis e g bit error rate packet routing The format for random probability declaration is shown below Format random value Example random 0 75 The value associated with random declaration must be in the range 0 0 lt value lt 1 0 This value represents the percentage of the time that the event is intended to occur A gate which uses the random probability feature must be operated in parallel with another gate which has a common event driving input Both these gates should have the same timing distributions associated with them When the common input changes state a probability trial is performed If the probability value is less than or equal to the value specified in the random declaration the gate containing the random declaration will have its priority temporarily upgraded and its outputs will change state before the outputs of the other gate This feature gives the user some level of control on a percentage basis over which gate will process the input data first As an example a system which models a communication channel that corrupts 1 of the data bytes that pass through it is shown below model main in out transl good in out 0 99 trans2 bad in out good gate good in out IN OUT t delta 1 0e 6 i in gt 0x00 o out in in 0x00 bad gate bad in out t delta 1 0e 6 random 0 01 i in gt 0x00 o out 0OxFF in 0x00 Using the Electric VLSI Design System version 8 11 291 Chapt
294. h the copied objects Therefore to duplicate some circuitry select it Copy click away to deselect and then Paste e If you want to rotate or mirror these structures select all of it both nodes and the arc and use the Rotate or Mirror commands in menu Edit Using the Electric VLSI Design System version 8 11 23 Chapter 1 Introduction 1 10 7 IC Layout Tutorial Hierarchy s Library noname X Electric supports hierarchy by allowing you to place instances of Name another cell These instances are nodes just like the simpler ones in the component menu To see hierarchy in action create a new cell with the New Cell command View in menu Cell Make sure the Make new window option is documentation checked in the dialog Then type documentation waveform Dd the new cell name Higher is used in the example here Technology mocmos F Cancel JV Make new window x A new empty cell will appear in a separate window Try creating a few simple nodes in this new window place a contact or two New Cell Instance xi Library noname zl view fai Now place an instance of the other cell by using the ae Rd Place Cell Instance command in menu Cell You can also click the Cell entry in the component menu You will be given a list of cells to create select the one that is in the OTHER window the one called MyCircuit in this example Then click in the newer cell to create the i
295. hapter 10 The JELIB and DELIB File Format 10 4 Miscellaneous 10 4 1 Variables Variables may be attached to any object in the Electric database They appear at the end of many of the lines in the file When more than 1 variable is listed on an object they are sorted by the variable name The syntax is lt name gt lt TD gt lt type gt lt value gt lt name gt the name of the variable lt TD gt the text descriptor when the variable is visible lt type gt the type of data attached the data If it starts with itis an array of the form lt name gt and lt value gt fields may be enclosed in quotation marks Backslash character can be used inside enclosed strings to denote special characters The lt type gt field can be one of these B Boolean T or F C Cell of the form lt library gt lt cell gt D Double E Export of the form lt library gt lt cell gt lt exportID gt F Float G Long H Short I Integer L Library name O Tool name P Primitive Node prototype of the form lt technology gt lt node name gt R Arc prototype of the form lt technology gt lt arc name gt S String T Technology name V Point2D of the form lt x gt lt y gt Y Byte 0 255 Examples ART_message D5G8 StxArray4x4B Adds a variable called ART_message with the string txArray4x4B The text descriptor indicates centered text D5 tha
296. hat wide By setting the maximum width this limits the size of generated layout Yet another control in the Routing Preferences sets the maximum number of steps that the router will take to find a route The larger the value the longer the router will run until giving up The final Routing Preferences control the use of multiple processors when doing a Sea Of Gates route If your computer has only one processor these controls are ignored The Use two processors per route preference is the best use of two processors because it uses two processors for each segment that is to be routed The Do multiple routes in parallel preference attempts to use as many processors as possible to run multiple routes at once If your computer has two processors it is recommended that you use Use two processors per route to get the best performance If your computer has four processors it is recommended that you check both options so that two different segments can be routed at once and each can have two processors working on it as opposed to checking only the second preference and having four different segments routed more slowly but in parallel Using the Electric VLSI Design System version 8 11 301 Chapter 9 Tools 9 7 Network Consistency Checking NCC 9 7 1 Introduction Electric can compare two different cells and determine whether their networks have the same topology This operation is sometimes called Layout vs Schematic LVS but becaus
297. he Add External JARs button to add any extra libraries Using the Electric VLSI Design System version 8 11 5 Chapter 1 Introduction e Handle Macintosh variations If you are building on a Macintosh no changes are needed If you are not building on a Macintosh you must decide whether or not you want the code that you produce to also run on a Macintosh If you do not care about being able to run on a Macintosh remove the source code module com sun electric tool user MacOS XInterface java which probably has a red X next to it indicating that there are errors in the file If you want the final code to be able to run on all platforms download the stub package AppleJavaExtensions jar from developer apple com samplecode AppleJavaExtensions and add this as an external JAR file Run Electric Use the Run command under the Run menu to create a run configuration Under the Main tab of the run configuration dialog give the configuration a name for example Electric set the Project to match the one that you have created and set the Main class to be com sun electric Launcher Under the Arguments section of the dialog it is a good idea to increase Electric s memory size by entering mx1000m under VM arguments Running under Netbeans The best way to use Netbeans is to extract the source code from the Savannah repository as described above If you do this you will have a directory called trunk The first step is to
298. he ERRORS section has a context menu with 8 entries The top three entries let you control the expansion of the tree Delete removes this collection of errors Export saves is collection of errors to a disk file for later import Show All highlights all of the errors in this collection this is also accomplished with Delete the Show Current Collection of Errors command in the Edit Selection menu Set Export Current makes this the current collection of errors which can be examined with the Show All lt and gt keys and Get Info describes this collection of errors Set Current Get Info lt The context menu for individual jobs under the JOBS icon has 3 entries Get Info requests panio any additional information about the job Abort requests that the Job stop itself not always SiE possible and Delete removes a job from the queue Delete 4 5 3 Layer Visibility The nodes and arcs on the display are composed of more basic layers By using the Layers tab of the Side Bar you can control which layers are actually drawn Components Explorer Layers The layers tab shows the layers in the current technology Changing the mocmos O technology popup at the top of this tab will change the current technology When a layer is checked it is visible You can turn the check on and off by Polysilicon 1 a Transistor Poly double clicking on a line or by using the Make Visible and Make Poly Cut Invisible
299. he Electric VLSI Design System version 8 11 Chapter 5 Arcs 5 4 Other Properties 5 4 1 Directionality For documentation purposes it is possible to display a directional arrow on arcs gt to indicates flow This property can be changed with the Toggle Directionality command in menu Edit Arc It may also be controlled by the Object Properties dialog in menu Edit Properties The controls in the Object Properties dialog offer the option of placing the arrow head on either end both ends or neither end This allows arbitrary combinations of arrow heads and bodies to display arbitrarily intricate directionality schemes 5 4 2 Negation Arcs in the Schematic technology may be negated which causes them to have a bubble drawn where they attach to schematic elements This property can be changed with the Toggle Port Negation command in menu Edit Technology i Specific It may also be controlled by the Object Properties dialog in menu Edit Properties Note that you can toggle negation when an arc is selected which leaves the system to guess which end you want to negate or you can toggle negation when a node and port is selected in which case the arc attached to that port is negated Note that the Object Properties dialog offers precise control of the negating bubbles allowing you to specify which ends have the bubbles on them Negated arcs make no sense in layout technologies and are ignored 5 4 3 End E
300. he Global node of the schematics technology see Section 7 5 1 The Global node is diamond shaped and it has a name and characteristic similar to exports input output etc All signals with the same global name are considered to be connected when netlisting occurs Thus the Global symbol can be used to route clock signals as well as to define multiple power and ground rails Note that with multiple power and ground rails only one of them is the true power and ground as defined by the Power and Ground symbols All others declared with Global nodes are not true power and ground signals but are simply globals The distinction is made by some netlisters which treat the true power and ground signals specially 168 Using the Electric VLSI Design System version 8 11 Chapter 6 Advanced Editing Global Partitioning It is sometimes the case that the designer wishes to isolate a global signal and wire it differently For example a schematic cell may be defined with power and ground symbols connecting it to the global power and ground But a particular instance of the cell may need to be wired to alternate power and ground rails for example dirty power Another example of rewiring happens when you want to test a specific instance of a cell and you need to connect its globals differently for the purposes of simulation The solution is to place a vddR Global Partition node inside Ci of the schematic see Section 7 5 1 This symbol ac
301. he Java3D package which is available from the Java Community Site www j3d org This is not a plugin but rather an enhancement to your Java installation e 3D Axis Controller Once the 3D facility is installed there is one extra part that can be added to enhance the display a 3D axis controller The 3D axis controller is available from Static Free Software at www staticfreesoft com electricJava3D 8 11 jar e Animation Another extra that can be added to the 3D facility is 3D animation This requires the Java Media Framework JMF and extra animation code The Java Media Framework is available from Sun Microsystems at java sun com products java media jmf this is not a plugin it is an enhancement to your Java installation The animation code is available from Static Free Software at www staticfreesoft com electricJMF 8 11 jar e Russian User s Manual An earlier version of the user s manual 8 02 has been translated into Russian This manual is available from Static Free Software at www staticfreesoft com electricRussianManual 8 11 jar To attach a plugin it must be in the CLASSPATH The simplest way to do that is to invoked Electric from the command line and specify the classpath For example to add the beanshell a file named bsh 2 0b1 jar type java classpath electric jar bsh 2 0bl jar com sun electric Launcher Note that you must explicitly mention the main Electric class com sun electric Launcher when using plug ins since al
302. he arc s function which is a different set than the Fixed angle Yes layer functions As with layer functions the arc functions should be Wipes pins Yes carefully considered Extend arcs Yes e Fixed angle lets you choose whether or not default arcs of this type are Angle increment 90 drawn at fixed angles see Section 5 2 1 In many layout technologies Antenna Ratio 400 0 the correct state is yes The particular fixed angle is specified by the Angle increment field below rc e Wipes pins lets you choose whether or not these arcs completely erase connecting pins the sensible state is yes because pins are drawn in the same layer and would not be visible anyway e Extend arcs lets you choose whether or not these arcs extend beyond their endpoints by half of their width see Section 5 4 3 The typical state is yes e Angle increment is the preferred angle granularity of this type of arc see Section 5 5 The typical state is 90 which requests Manhattan arcs e Antenna Ratio is used in antenna rules calculations see Section 9 3 2 A well arc that contains a well layer and does not contain device diffusion i e opposite doping to the well must not be defined as diffusion it must be defined as well diffusion This prevents the Spice extractor from incorrectly adding any p or n doped area found in the well arc to the source or drain area of a transistor 224 Using the Electric VLSI Design System version
303. he icon for generation in the Spice deck see Section 9 4 4 To define parameters on a cell it is necessary to be editing either the schematic or one of its icons it does not matter which because the set of parameters is the same inside of the cell group Use the Cell Parameters command in menu Edit Properties A list of parameters is shown at the top You can create a new parameter by typing its name in the Name field its default value in the Value field and then clicking the Create New button If Show new parameter on instances is checked this new parameter will be seen on all instances with its default value The Edit button next to the Value field lets you change the value in a separate dialog useful for major changes You can delete a parameter with the Delete button and change its name with the Rename button You can also copy parameters from another parameterized cell using the Copy From Cell button 160 D Edit Parameters Parameters on disconHigher2 Rename Delete P Show new parameter on instances Done Name heat Value jis Edit Evaluation Code Not Code Units none Show name value X js Points min 1 max 63 Text Size fi Units min 0 25 max 127 75 x offset fo Y offset lo Rotation fo Anchor centered x Boxed width height All Text Sizes are Scaled by 100 Bold f gt Italic P Un
304. he main and extension cursors Besides controlling time with menu commands you can also use the Pan and Zoom tools of the 7 J toolbar to change the view You can also adjust time by clicking and dragging in the time axis at Q the top a The pan tool lets you smoothly shift time when you click and drag In the zoom tool you zoom into an area by clicking and dragging out that area To zoom out hold the shift key and click in the center of the desired area 126 Using the Electric VLSI Design System version 8 11 Chapter 4 Display The time axis is drawn linearly but it can be changed to a logarithmic scale by right clicking on the ruler and choosing Logarithmic use Linear to restore the scale The different panels in the waveform window are locked in time they all show the same range of time as shown at the top of the waveform window If you click on the time lock button at the top of the waveform window looks like a lock with the time on it E m then time is unlocked and each panel has its own time scale Now individual panels can show a different range of time than the rest Electric does crossprobing between the waveform window and an edit window with the original circuit If the original circuit is being displayed selection in the waveform window is mirrored in that cell Also whenever the main time cursor changes the electrical state of the circuit is shown in that cell Wires are colored differently acco
305. hem modified by the simulator at run time The Load Statement The load statement is used to set the relative loading capacitance for an input or output signal The format of a load statement is shown below Format load signall value signal2 value Example load in1 2 0 in2 1 5 in3 1 95 load sa 2 5 The value associated with the signal represents the relative capacitance of the simulation node When the timing parameters are specified for a gate description it is assumed that they are chosen for the situation where the gate is driving a single 1 0 unit load such as a minimum size inverter input The load command tells the simulator that some input structures are smaller or larger more capacitive than the reference standard The simulator by default assumes that all signals associated with gate primitives have a load rating of 1 0 unit load unless they are overridden by a load statement 292 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools The Priority Statement The priority statement is used to establish the scheduling priority for a gate primitive The format for a priority statement is shown below Format priority level Example priority 1 priority 7 In the event that two gates are scheduled to update their outputs at exactly the same time the gate with lowest priority level will be processed first All gate primitives are assigned a default priority of 1 unless they contain random ti
306. hese commands may be given to the Logical Effort tool in menu Tools Logical Effort e Optimize for Equal Gate Delays Optimizes all logical effort gates cells to have the same delay The delay is specified by the Global fan out step up project setting This is NOT a path optimization algorithm 332 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools e Optimize for Equal Gate Delays no caching It is intended that both the caching and non caching algorithms obtain exactly the same result however due to the difficulty in obtaining and maintaining correctness when it comes to caching the non caching algorithm is also available o List Info for Selected Node After running sizing information about a specific logical effort gate can be found by selecting the gate instance and running this command e Back Annotate Wire Lengths for Current Cell Runs NCC on the current cell against it s matching layout or schematic cell Assuming they match for each LEWIRE in the schematic cell it finds the half perimeter of the matching wire in the layout cell as if the layout was flattened and then changes the L parameter on the LEWIRE to the value Note back annotation is only performed on top level LEWIREs and it takes into account the wire s length throughout the layout hierarchy e Clear Sizes on Selected Node s Logical effort sizes are stored as parameters on the LEGATE Sometimes the sheer number of sizes can overwhel
307. hical User Interface GUI Introduction When NCC finds mismatches a window pops up displaying the mismatches Below is a typical display with some essential features NCC Messages Fi oi x Mismatched Comparisons 1 Summary of bitslice sch Summary of bitslice lay i mipscells bitslice sch lay 34 23 Parts 20 Parts Exports 10 107 Wires 95 Wires Ji Parts 3 88 Ports 78 Ports 1 2 mipscells mux4 11 Wires 2 1 mipscells inv 3 4 mipscells mux2 1 aluopb 0 2 b2 3 aluop 0 4 4 f aluresult 1 mipscells dpor2 a 1 mipscells Flop d 1 mipscells mux4 d0 1 mipscells mux4 y 5 alubinv 6 alubinvb 7 aluopb 1 8 src2mux y 9 f aluop i 4 bb The left side of the window is a tree providing an overview of the kinds of mismatches that NCC found The right side has information corresponding to the currently selected tree node s Each top level tree node corresponds to a comparison of two cells In the above example the label on the top level node indicates that the comparison that failed was between the cells bitslice sch and pitslice lay in the library mipscells If the two cells have different names or are from different libraries then their names are shown individually For example libraryA gateA sch amp libraryB gateB sch The number in square brackets
308. his last choice can produce highly complex pure layer nodes but is fastest and uses the least amount of memory Unknown layers This controls how unknown layers in the GDS file are treated The default is Convert to DRC Exclusion layer which creates an orange DRC Node wherever an unknown layers appears If you set this to Ignore the unknown layers are simply ignored A final choice is Convert to random layer which picks a different layer in the technology for each unknown GDS layer number This allows the distinction between layers to be seen even if the correct layer associations are not known e Cadence compatibility This forces a GDS import to do things that assume the GDS has come from a Cadence system Export locations are forced to be inside of the geometry on which they reside Using the Electric VLSI Design System version 8 11 Chapter 7 Technologies 7 3 4 EDIF Control EDIF Electronic Design Interchange Format is used to exchange design information between different CAD systems Although EDIF is currently at version 4 0 0 Electric reads and writes version 2 0 0 For more information on reading and writing EDIF see Section 3 9 2 and Section 3 9 3 respectively EDIF options are controlled with the EDIF Preferences in menu File Preferences I O section EDIF tab ES EDIF USER Preferences E General i Display IV Use Schematic View when writing This dialog controls whether EDIF E Io output wri
309. his simulation output can come from external simulators such as Verilog and ArchSim or built in simulators such as ALS and IRSIM When displaying the results of external simulators the system reads the simulation output and shows it When internal simulators are displayed you have the additional capability of changing the stimuli The digital waveform window looks like the picture below Note also that there is a side bar with a cell explorer in the window just like in all windows but the explorer has a SIGNALS section that lists the signals found in the simulation IRSIM simulation of latchAA lay M Ol x Components ih Panel 4 af Main 3 33ns Center Ext 6 61ns Center Deta 3 28ns Explorer Layers cc in neta TY himb 1 10 LH 1 10 out himb 1 10 Wave Panels The waveform window contains a set of panels each with a signal name and signal waveform In each panel signal names are shown on the left and their waveform on the right Signals can be high line at the top low line at the bottom X solid bar from top to bottom or Z solid bar in the middle Between the name and the waveform are two control buttons e Close an X to remove that panel from the waveform window e Hide to stop displaying the panel but keep it available it can be restored by selecting its name from the popup at the top of the waveform window The waveforms can be single signals or busses Busses are colle
310. ically done with the sliders on the right and bottom of the window On systems that have a mouse wheel you can use it to pan vertically and hold the shift key while rolling the mouse wheel to pan horizontally On systems with a middle mouse button this button pans the display __ You can also use the Pan tool from the tool bar to move the window contents Once in this mode d clicking and dragging slides the circuitry smoothly This mode can also be invoked with the Toggle Pan command in menu Edit Modes Edit Yet another way to control screen panning is to use menu commands The Pan Left Pan Right Pan Up and Pan Down commands in menu Window all shift the window contents appropriately and because they are bound to quick keys these operations can even be done from the keyboard By default these commands shift the screen by about 30 of its size You can use the Display Control Preferences in menu File Preferences Display section Display Control tab to change that amount The Small panning distance causes subsequent shifts to be about 15 of the screen size The Medium panning distance causes subsequent shifts to be about 30 of the screen size The Large panning distance causes subsequent shifts to be about 60 of the screen size There are five special panning commands in the Window Special Pan menu Center Selection makes the window shift so that the highlighted objects are in the center of the window e Center C
311. ierarchical comparison because it is faster and the mismatch diagnostics are much more precise and intelligible However transistor size checking limits what NCC can compare hierarchically because the size of a schematic transistor may depend upon the instance path 304 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools The best way to use NCC is to initially perform all comparisons hierarchically This will typically require many iterations Once the circuit has passed hierarchical comparison turn on size checking This will report transistor size mismatches Size Checking Section The Size Checking section controls how NCC compares transistor widths and lengths This section affects two distinct NCC phases netlist comparison and series parallel combination Netlist comparison After each topological comparison NCC can optionally perform size checking If NCC finds no topological mismatches and if Check transistor sizes is checked then NCC checks for each pair of matching transistors that the widths and lengths are approximately equal The two tolerance values allow the user to specify how much more the larger of the two matched transistors may be than the smaller before NCC reports a size mismatch The Relative size tolerance is the difference in percentage The Absolute size tolerance is the difference in units NCC reports a size mismatch when both tolerances are exceeded If you choose Check transi
312. ifferent ways of obtaining hardcopy from the screen METHOD TEXT QUALITY LAYOUT QUALITY Print command High o s be dithered Screen capture Low High PostScript export High but different fonts Dithered HPGL export High but different fonts Dithered PNG export Low High 114 Using the Electric VLSI Design System version 8 11 Chapter 4 Display For specific printing and PostScript settings use the Printing Preferences in menu File Preferences General section Printing tab Categories General The For all printing section at the top has some general options The default is to include the entire cell but you can choose to print only what is highlighted or only what is displayed by selecting the appropriate buttons 10 over Export Reset General Selection Key Bindings Nodes Arcs Project Management cys Import Reset All Display Only resets USER Preferences Help Cancel Apply Printing USER Preferences For all printing Plot Entire Cell C Plot only Highlighted Area Plot only Displayed Window For PostScript Encapsulated Color Printer Plotter width in 8 5 Height in it Margin in 0 75 Rotation No Rotation For cell ptest sch Synchronize to file Set Print resolution DPI soo Black amp white x Line width fi Ne T Plot Date In Corner EPS Scale fi Note that when prin
313. ign rule checker can NPlus active overhang B report error names NPlus poly overhang C NPlus spacing D PPlus width E PPlus active overhang F PPlus poly overhang G PPlus spacing H NwWell width I NWell P active overhang 3 fo Load Parameters Write XML NWell N active overhang wf NWell spacing L fo _5ave Parameters Distances are in nanometers Using the Electric VLSI Design System version 8 11 255 Chapter 8 Creating New Technologies The Metal panel lets you oo Metal Parameters specify size and spacing paola values for the Metal layer Poly You can change the number Gate of Metal layers with the Contact B Add Metal and Remove ial a Metal buttons The via Antenna number of metal layers should be established in GDS this panel before using Add Metal Remove Metal subsequent panels that Distance Rule Name depend on this The Rule Metal 1 width 4 fo Name fields let you Metal 1 spacing B booo describe the rule so that the Metal 2 width 4 fo design rule checker can Load Parameters Write XML T report error names Metal 2 spacing B Save Parameters Distances are in nanometers Technology Creation Wizard x Technology Parameters Via Parameters General Active Poly Gate Contact Well Implant The Via panel lets you Meia specify size and spacing values A for the Via layer A popup lets GDS
314. ign System version 8 11 Chapter 2 Basic Editing 2 4 Circuit Modification 2 4 1 Movement Components can be moved by clicking on them with the eft button and then dragging them around while keeping the button pressed During the drag the new location of the components will be shown as well as the amount of motion and once the button is released the circuitry will be moved While moving simple design rules are applied and a warning is shown if the object is in violation In the example here the Metal 1 Metal 2 contact is moved down toward the Metal 1 arc and is too close Use DRC Preferences to control these error messages see Section 9 2 2 R Metal 1 spacing is 1 5 MINIMUM IS 3 Another way to move objects is to use the arrow keys When a node or arc is selected each press of an arrow key moves that object by one grid unit If the shift key or the control key is held then the arrow keys move the object by a block of grid units A block of grid units is defined in the Grid Preferences in menu File Preferences Display section Grid tab to be the frequency of bold dots in the grid initially 10 If you hold both the shift key and the control key then the distance moved will be a block squared i e initially 100 Note that these arrow keys are available in the Edit Move menu with the commands Move Objects Left Right Up Down for a single unit Move Objects More Left Right Up Down for a block of units and M
315. ile Preferences Technology When real units are specified Titel Sane __ Import they are used in display and in dialogs section Units tab allows you to request that dimensions be shown in real units such as Reset Reset All __Reset all nanometers Only resets USER Preferences Help Apply Using the Electric VLSI Design System version 8 11 189 Chapter 7 Technologies 7 3 I O Specifications 7 3 1 Introduction Electric is able to read and write circuits in a number of different formats This is done with the Import and the Export commands in menu File See Section 3 9 2 for more on Import see Section 3 9 3 for more on Export To properly control translation use the many Preferences dialogs for the different file types in menu File Preferences I O section Unfortunately many of these formats are pure geometry with no information about the circuit connections When read they appear as pure layer nodes This means that transistors contacts and other multi layer nodes are not constructed properly Although the cell appears visually correct and can be used to export the same type of file it cannot be analyzed at a circuit level The node extractor can be used to convert these pure layer nodes to true Electric components see Section 9 10 2 The next few sections describe control of different I O formats 7 3 2 CIF Control CIF Caltech Intermediate F
316. imitive See Section 9 4 4 for more on Spice templates Change Node Function xi New function for this node Cancel Editing Node Geometry The Function entry describes the node s function which is a different set than the arc and layer functions A dialog offers a list of possible node functions contact For nodes it is common to sketch four different examples of the node in varying scales so that X and Y scaling rules can be derived square nodes need only two examples If only one example is specified linear scaling rules will be presumed The smallest example called the main example is used as the default size and also contains all of the special port information Needless to say it is important to keep the geometry of each example well apart from the others so that the technology editor can distinguish them Each example must contain the same geometric layers only stretched As in the Arc cells pieces of geometry can be created by selecting from the component menu of the side bar creating the geometry and then double clicking to assign a layer If any polygonal geometry is used for example the Filled polygon entry sixth from the top they require outline information to be assigned see Section 6 10 1 If the Opened circle arc entry is selected second from the bottom you can specify the number of degrees of the circle with the Object Properties command in menu Edit Properties Each exam
317. in active devices 2 A p or n layer that is used to make a contact in a well of the same semiconductor type for example p in a P well must not be defined with the layer function Diffusion it must be declared as Well In the well contact shown below both the p layer and the P well layer will be defined with the layer function Well P type Using the Electric VLSI Design System version 8 11 223 Chapter 8 Creating New Technologies 8 5 The Arc Cells Creating and Deleting Arc Cells Arcs are the wires in a technology and they are constructed from pieces of geometry on the layers To edit an existing arc select it from the cell explorer or the Edit Cell command in menu Edit E TECHNOLOGY ARCS Add New Arc Reorder Arcs To create a new arc use the context menu on the TECHNOLOGY ARCS entry of the cell explorer and choose Add New Arc An arc can be deleted simply by deleting its cell An arc can be renamed by renaming its cell but remember to use the name arc in front i e the old name is arc metal and the new name is arc metal 1 Finally you can rearrange the order in which the arcs will be listed with the Reorder Arcs command from the context menu Editing Special Arc Information Arc cells show a sample arc on the bottom and a few pieces of textual information above it The textual information can be updated by double clicking on it Function metal 1 e Function describes t
318. information The designer supplies this information by adding NCC annotations to layout and or schematic cells This is done with the subcommands of the Tools NCC Add NCC Annotations to Cell menu NCC annotations are represented by attributes placed on cells The attribute s name is NCC and it contains one or more lines of text each with a separate NCC annotation Thus although a cell can have at most one attribute named NCC that attribute can contain any number of NCC annotations exportsConnectedByParent lt string or regular expression gt Layout cells sometimes contain multiple exports that are supposed to be connected by the parent cell For example a layout cell might export vdd vdd_1 vdd_2 and vdd3 The designer expects that instances of this cell will connect all the vdd exports to a single network However because the corresponding schematic cell usually only contains a single export vdd the NCC of the schematic and layout cells fails This situation is most common for the power and ground networks although it occasionally arises for signal networks such as clock or precharge The Exports Connected by Parent vdd and Exports Connected by Parent gnd commands create this annotation which tells NCC which exports will be connected by the parent The keyword is followed by a list of strings and or regular expressions regular expressions must begin and end with a For example exportsConnectedB yParent vdd vdd_1 vdd_2
319. ing Electric Electric is written in the Java programming language and is distributed as a single jar file typically called electric version jar where version is 8 09 8 10 etc There are two variations on the jar file with or without source code the version without source code has the word Binary in its name Either of these files can run Electric but the one with source code is larger because it also has all of the Java code Electric requires Java version 1 5 or 1 6 from Sun Microsystems It can also run with Apache Harmony However it does not run properly on some open source implementations of Java including the version shipped on Fedora Core systems You will have to reinstall Java from Sun or Apache in such cases Running Electric varies with the different platforms Most systems also allow you to double click on the jar file If double clicking doesn t work try running it from the command line by typing either java jar electric jar or java classpath electric jar com sun electric Launcher There are a number of options that can be given at the end of the command line e mdi force a multiple document interface style where Electric is one big window with smaller edit windows in it e sdi force a single document interface style where each Electric window is separate Note that the MDI SDI settings can also be made from the Display Control Preferences see Section 4 3 e s script run the script file through
320. ing no exports in the schematic Some exports are implied For example if a schematic cell uses a global ground but does not contain an export for that ground then NCC will automatically insert an implied export for ground This is done because most often the corresponding layout cell has a ground export and we want the schematic and layout cells to match Implied exports are not hyperlinked and have implied added to their names see below 312 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools When NCC does not find any topological mismatches it attempts to suggest possible matches for exports that failed to match by name Such suggestions are printed in green The first row of the table below indicates that the outO 1 T export in the layout topologically matches the outO T export in the schematic even though they have different names The second row indicates that the outE 1 F export in the layout topologically matches the net 4 1 wire in the schematic even though the net 4 1 wire has no exports Note that a wire name is not an export list and is not surrounded by curly brackets rxPadsHeater rxSenseAmp sch rxPadsHeater rxSenseAmp lay outO T outO 1 7 net 4 1 i outE 1 F vdd i vdd_1 vdd_2 vdd_3 vdd_4 vdd_5 vdd_6 net 4 0 outE 1 T outO F outO 1 F Implied exports are marked by implied Suggestions are printed in green Exports that mat
321. ingle straight arc Nodes whose ports touch but are not connected Invisible pins with text that is offset from the node center this is an internal consistency check Using the Electric VLSI Design System version 8 11 261 Chapter 9 Tools Nodes whose names are the same as network names in the cell Schematic exports whose characteristics are different from the equivalent export in the icon 2 Arcs Unnamed arcs that dangle one end is unconnected and unexported does not apply to busses Bus arcs whose width is inconsistent with its two nodes Bus pins that float do not connect to bus arcs and are not exported Bus pins that connect to more than 1 wire Network names that differ only by their case i e networks A and a are actually different networks 9 2 2 DRC Preferences To control the DRC use the DRC Preferences in menu File Preferences Tools section DRC tab By default the incremental design rule checker is on To turn it off uncheck the On checkbox in the Incremental DRC section You can also control the incremental display of design rule violations that occurs when moving nodes and arcs see Section 2 4 1 _ Categories E General E Display f g Yo Tools so Antenna Rules Compaction Coverage DRC Fast Henry Logical Effort NCC Network Parasitic Placement Routing Silicon Compiler Simulators Spice Spice Model Files Verilog Verilog
322. ions this may be many more nodes than are necessary Ignore polygons smaller than limits the size of extracted polygons When unusual geometries are extracted there can be many tiny polygons needed to fill in gaps By default any polygon smaller than 1 4 unit in area is ignored Use pure layer nodes for connectivity requests that all wires in the extracted layout be run using pure layer nodes When unchecked arcs and pins are created to make connections Because complex layout can cause many little arcs and pins to be created in order to mimic the geometry this preference lets a simpler set of pure layer nodes do the wiring Pure layer nodes are harder to edit but simpler when modeling complex geometry Active and implant regions can be handled in a number of different ways depending on the way that these layers are defined in the original CIF GDS e Require separate N and P active require proper select well assumes that there are distinct N and P active layers being extracted and that they are surrounded by the proper select and well layers Extraction is easiest when all of this information is guaranteed to be correct e Ignore N vs P active require proper select well assumes that there is only one active layer for N and P regions and so the correct select and well implants will be used to determine the type of active e Require separate N and P active ignore select well assumes that the N and P active layers are corre
323. is does not invalidate libraries that use the layers but it does invalidate the node and arc descriptions in the technology The geometry in these nodes and arcs will have to be moved to another layer Deleting nodes or arcs will cause error messages when libraries are read that make use of the deleted objects When the library is read you can substitute another node or arc to use in place of the now unknown component Deleting miscellaneous information depends entirely on where that information is removed For example an analysis tool may fail to find the information that it requires Modifying layers nodes arcs and miscellaneous information Modifying layers is a totally transparent operation Any change to the color style or stipple information including changes to the color map will appear in all libraries that use the technology Changes to I O equivalences or Spice parasitics will be available to all existing libraries A change of the layer function may affect the technology editor s ability to decode the nodes and arcs that use this layer for example if you change the function of the polysilicon or diffusion layers that form a transistor the editor will be unable to identify this transistor Renaming a layer has no effect Modifying arcs and nodes is not as simple as layer modification because the arcs and nodes appear in the circuit libraries whereas the layers do not If you rename a node or arc it will cause errors whe
324. istencies that may arise The project management system uses the full power of cell naming to accomplish its task It handles design history by creating a new version of a cell each time it is checked out of the repository The user s library contains only the most recent version of each cell taken from the repository When a user updates their library from the repository newer versions are brought in and substituted for older versions Unless the user specifically asks for an older version it is removed from their library Because the project management system uses versions to manage design progress users are discouraged from managing versions explicitly Thus the command New Version of Current Cell in menu Cell is not allowed Also it is not appropriate for a user to use two different versions of a cell explicitly because they are considered to be part of a single cell s history All commands to the project management t Management USER Pr system can be found under F fa ae Repository the Project Management Selection The repository contains the latest version of your circuit command in menu File Key Bindings a history of changes to each cell and the user database Subcommands exist there Nodes Tt must be a directory that everyone can access on a network for checking cells in and Arcs Currently etc electric repository Project Management CyS Printing out updating local libraries from the repository and more Many projec
325. it e Build on non Macintosh to run on all platforms To build Electric so that it can run on all platforms Macintosh and other you will need to keep the module com sun electric MacOS XInterface java However in order to build it you will need the stub package AppleJavaExtensions jar The package can be downloaded from Apple at developer apple com samplecode AppleJavaExtensions 6 Using the Electric VLSI Design System version 8 11 Chapter 1 Introduction 1 5 Plug Ins Electric plug ins are additional pieces of code that can be downloaded separately to enhance the system s functionality Currently these plug ins are available e IRSIM The IRSIM simulator is a gate level simulator from Stanford University Although originally written in C it was translated to Java so that it could plug into Electric The Electric version is available from Static Free Software at www staticfreesoft com electricIRSIM 8 11 jar e Bean Shell The Bean Shell can be added to Electric to enable Java scripting and parameter evaluation Advanced operations that make use of cell parameters will need this plug in The Bean Shell is available from www beanshell org e Jython Jython can be added to Electric to enable Python scripting Jython is available from www jython org Build a standalone installation to create a JAR file that can be used with Electric e 3D The 3D facility lets you view an integrated circuit in three dimensions It requires t
326. ith a new one of a different type Change selected ones only Change all connected to this test lay Primitives Change all in this cell This same effect can be had by copying one Active Cut Node Change all in this library bject and th ting it ont ther Hi Res Node Q JEC ane vaen pas me i Sea ve See Metal 1 Metal 2 Con Change all in all libraries Section 6 1 A dialog is presented in which the Metal t N Active Con possible replacements are shown For node Metal 1 N Well Con Selected 1 nodes changing you can choose to show primitives Metal 1 Node from the current technology cells from the Metal 1 P Active Con m gt Metal 1 P Well Con current library or both pie I Shaw primitives a Metal 1 Polysilicon 1 2 C When replacing an arc the existing nodes on Metal 1 Polysilicon 1 Cor Iv Show cells either end must be able to reconnect to the new Metal 1 Polysilicon 2 Cor type of arc If Change nodes with arcs is Metal 2 Metal 3 con Tonore port names checked nodes will be changed to allow the new E Allow missing ports type of arc to remain connected Library TestCells z Done a Change When replacing a node the existing arcs on it must be able to reconnect properly to the new node However the sizes of the replaced object can be different and the layout will be adjusted Electric determines which ports on the replaced node to use by examining the port name
327. l Points max 63 Size s o Units max 127 75 Font DEFAULT FONT 7 Bold J talic P Underline Using the Electric VLSI Design System version 8 11 157 Chapter 6 Advanced Editing 6 8 4 Text Defaults To change default information for all new text use the Text Preferences in menu File Preferences Display section Text tab The top part of the dialog controls how new text will appear Select the type of text and then its appearance size anchor font etc The middle section is For Textual Cells and controls the fonts used to display textual cells see Section 4 9 Text USER Preferences General Display Display Control Component Menu Nodetext Arctext Porttext Export text Layers Default Style For New Text Which type of new text The bottom part of the dialog controls text drawn in circuitry You can set the default font and a global text scale for the current and new windows Normally all text is drawn at 100 of its stated size a eer Font DEFAULT FONT However you can globally 3 Technology scale all text by typing a Italic Bold I Underline value other than 100 into this field You can also use the Increase All Text Size p For Textual Cells and Decrease All Text Font SansSerif x Size 12 Size commands in menu Edit Text to change this External editor NOT SET Set Clear value and alter the size of Export Import
328. l exports see Section 3 11 4 for more on icon generation Thicker Arc Dashed Are There are four different polygon styles opened closed filled and spline The opened polygon can be drawn with solid lines dotted lines dashed lines or thicker lines These nodes require that you use the Outline Edit mode see Section 6 10 1 The illustration below shows how outline information applied to Artwork nodes results in different shapes In each of the shapes the outline has the same 5 points as illustrated in the upper left The nodes interpret this outline information to produce their shape Note that the spline curve does not run through the outline points only near them Using the Electric VLSI Design System version 8 11 209 Chapter 7 Technologies Ps E IN if if m4 M4 2s o m4 4 4 o4 3 54 fo4 S z J i 1 A f f y yO f 4 of H n g y of 4 SS t yor ae t wir an i Vt 5 3 1 2 se A t w 4 Opened Solid P olygon Opened Dotted Polygon Opened Dashed Polygon Filled P olygon Spline Opened Thicker Polygon Closed P olygon The final feature of the Artwork technology is its ability to set the appearance of any of its nodes or arcs Use the Artwork Color and Pattern command in menu Edit Technology Specific to set the color and pattern of any Artwork node or arc You can also invoke this dialog by clicking on the Color and Pattern button in the node or arc Properties
329. l A may have a wire with the export gnd and a different wire with the export gnd_1 When cell B instantiates A cell B connects A s exports gnd and gnd_1 However A s schematic typically has only one combined gnd wire When NCC compares A s schematic and layout it finds that the ground wires mismatch As a solution the designer adds the following NCC annotation into A s layout cell exportsConnectedByParent gnd gnd_1 This annotation constitutes a promise that whenever A is instantiated its exports gnd and gnd_1 will be connected Then when NCC compares A s schematic and layout it assumes that the promise has been kept and the comparison passes However when NCC compares B s schematic and layout it checks to see if the designer is keeping the promise If the promise is not kept and no new promise to connect exports in the next parent is given then NCC reports an export assertion error in the Export Assertions leaf node When an Export Assertions node is selected it displays a table with two columns and one or more rows see below Each row corresponds to a broken promise The first column has cell names The second column lists exports that the designer promised would be connected but which remained disconnected The exports are organized into two or more export lists Each export list is a comma separated list of exports enclosed in curly brackets Exports in the same list are connected Exports in different lists
330. l commands exist in the Selection menu for dealing with easy to select nodes and arcs You can select all of the easy to select objects in the current cell with the Select All Easy command Similarly you can select those that are not easy to select with the Select All Hard command To change the ease of selection for a set of objects highlight them and use either Make Selected Easy or Make Selected Hard Using the Electric VLSI Design System version 8 11 45 Chapter 2 Basic Editing 2 2 Circuit Creation 2 2 1 Node Creation Node creation is done by selecting a node from the component menu in the side bar on the left Nodes in the component menu are outlined in blue After clicking on one of these nodes click in the edit window to place the node The location of the cursor is aligned to the nearest grid unit This adjustment can be controlled with the Grid Preferences in menu File Preferences Display section Grid tab see Section 4 7 2 When placing a node the cursor points to the anchor point of the newly created node This is the center for primitives or the location of the cell center for cell instances Cell instances can change their anchor point by moving the Cell Center node inside of their layout see Section 3 3 When placing a node but before you click to actually create the node it is possible to temporarily switch from node placement to zoom pan mode This allows you to better select
331. l of the jar files are grouped together as the classpath On Windows you must use the to separate jar files and you might also have to quote the collection since separates commands java classpath electric jar bsh 2 0bl jar com sun electric Launcher The above text can be placed into a bat file to make a double clickable Electric launch You can also add Java switches and special Electric controls mentioned in Section 1 3 For example to add in IRSIM and extend the memory to 1GB you can put this line in the bat file java classpath electric jar electricIRSIM jar mx1000m com sun electric Launcher Using the Electric VLSI Design System version 8 11 7 Chapter 1 Introduction 1 6 Fundamental Concepts MOST CAD SYSTEMS use two methods to do circuit design connectivity and geometry e The connectivity approach is used by every Schematic design system you place components and draw connecting wires The components remain connected even when they move e The geometry approach is used by most Integrated Circuit IC layout systems rectangles of paint are laid down on different layers to form the masks for chip fabrication ELECTRIC IS DIFFERENT because it uses connectivity for all design even IC layout This means that you place components MOS transistors contacts etc and draw wires metal 2 polysilicon etc to connect them The screen shows the true geometry but it knows the connectivity too Th
332. lay units Future versions of Electric may implement a symbolic style of Xml technology files Currently technology files contain two kinds of information 1 Electric independent information This includes physical and electrical details of the foundry process Most of these details are attached to Layers and includes design rules simulation information etc 2 Electric specific information This includes the primitive nodes and arcs that Electric uses for design It also has connectivity rules display and print styles component menus for the technology etc Primitive nodes and arcs can be considered to be layout macros Node description consists of a set of two dimensional shapes Arcs description consists of a set of one dimensional intervals which are stretched in the other dimension The technology file describes primitive nodes and arcs of a standard size usually the DRC minimum and also includes information about how they can grow larger Instances of these nodes and arcs in Libraries can be larger than standard A primitive node or arc can consists of many shapes in different technology Layers Each shape in a primitive node is called a NodeLayer Each interval in a primitive arc is called an ArcLayer The minimum bounding box of all NodeLayers of a primitive node is called its FullRectangle Description of a primitive node can also define the FullRectangle explicitly The largest of all ArcLayers in a primitive arc defines it
333. layer from 0 to 1 e lt foreground gt true to place this layer in the foreground e lt display3D gt defines thickness and height above the substrate for 3D display and parasitics The element has these attributes thick 3D thickness of the layer in display units height 3D height of the bottom of the layer in display units mode 3D display style factor 3D display style Example lt display3D thick 0 75 height 15 75 mode NONE factor 0 2 gt e lt cifLayer gt CIF layer name e lt skillLayer gt Skill layer name e lt parasitics gt parasitic extractor subelements e lt pureLayerNode gt description of the pure layer node for this layer This node is used to represent arbitrary polygons of this Layer It is also used when importing from external formats like GDS The standard pure layer node has zero FullRectangle and BaseRectangle So library files contain exact geometric information for instances of pure layer node All the shape of pure layer node is considered a port shape of the single port of the node There are these optional subelements lt oldName gt if the pure layer node has another name in older versions of the technology lt lambda gt the default width of this pure layer node when it is placed manually lt portArc gt the list of arc names which can connect to this pure layer node Example lt pureLayerNode name Transistor Poly Node port trans poly 1 gt lt lambda gt 2 0
334. le The image to be attached to a command must be 16 pixels high and will be scaled down if it is larger 92 Using the Electric VLSI Design System version 8 11 Chapter 4 Display 4 2 The Messages Window The messages window is a text window near the bottom of the screen Many commands list their results in the messages window and minor error messages are reported there The text in the messages window can be selected with the cursor and edited with the Cut Copy and Paste commands in menu Edit You can remove all text with the Clear command in menu Window Messages Window In addition you can right click in the messages window to Cut Copy Cut All Copy All Clear or Paste text The text in the messages window can be saved to disk by using the Save Messages command in menu Window Messages Window You will be prompted for the place to save the text This saves all future text but not the text currently there To save all text currently in the messages window right click on the window and choose Save All You can select the messages window font with the Set Font command The command Tile with Edit Window adjusts the messages window so that it abuts the edit window cleanly Using the Electric VLSI Design System version 8 11 93 Chapter 4 Display 4 3 Creating and Deleting Editing Windows Initially there is only one editing window on the screen Elec
335. le contains only a visual representation of the current cell or part of that cell e PNG Portable Network Graphics is an image format that captures the current window e SVG is a web format Scalable Vector Graphics that captures the current window e DXF AutoCAD is a solid modeling interchange format Use the DXF Preferences in menu File Preferences I O section DXF tab to affect how DXF is written See Section 7 3 7 for more on DXF e ELIB Version 6 writes old format binary files These files can be read by version 6 of Electric e JELIB Version 8 03 writes old format JELIB files These files are useful for versions 8 03 and earlier Using the Electric VLSI Design System version 8 11 Chapter 3 Hierarchy The exported files from Electric are often considered to be proprietary information and must be marked appropriately Copyright information can be inserted into exported files with the Copyright Preferences in menu File Preferences I O section Copyright tab Categories General Display 5 1 0 H CIF GDS EDIF DEF CDL a Ea Copyright PROJECT Preferences 4 Copyright message can be added to every generated deck No copyright message C Use this copyright message DXF SUE Library ae Copyright Tools Technology Export Import Reset Reset All Only resets USER Preferences Help Apply Cancel Since each export file has a different
336. led into Electric see the module com sun electric tool simulation als UserCom java Both primitive entities also allow the specification of operational parameters such as switching speed capacitive loading and propagation delay The simulator determines the capacitive load and thus the event switching delay of each node of the system by considering the capacitive load of each primitive connected to a node as well as taking into account feedback paths to the node 286 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools A sample netlist describing an RS latch model is shown below Note that the character starts a comment model MAIN model declaration for the figure model main set reset q q_bar instl nor2 reset q_bar q inst2 nor2 q set q bar reset gate description of nor2 gate nor2 inl in2 out t delta 4 5e 9 linear 5 0e 10 inl L in2 L o out H 2 inl H o out L 2 in2 H o out L 2 o out X 2 q bar set When combined these entities represent a complete description of the circuit Note that when a gate function or other model is referenced within a model description there is a one to one correspondence between the signal names listed at the calling site and the signal names contained in the header of the called entity Simulator Internals The ALS simulator simulates a set of simulation nodes A simulation node is a connection point which may have one or more sign
337. les for Bulk CMOS VLSI Design III 5 62 67 September October 1982 It was never aligned with an actual process and exists only for illustration e efido a high level digital filter architecture technology The cell tech DigitalFilter in the sample library illustrates this technology e fpga a customizable technology that can describe field programmable gate array architectures The basic technology does not have any FPGA capabilities it must be customized with a special Using the Electric VLSI Design System version 8 11 185 Chapter 7 Technologies architecture file see Section 7 6 2 for more e gem a temporal logic technology that illustrates Electric s capability to do graph editing in nonelectrical environments Based on the paper Lansky A L and Owicki S S GEM A Tool for Concurrency Specification and Verification Proceedings 2nd Annual ACM Symposium on Principles of Distributed Computing 198 212 August 1983 The cell tech Gem in the sample library illustrates this technology e generic a technology used for special features such as inter technology connections routing specifications cell definitions etc This technology is never used for actual design but its nodes and arcs appear in many places See Section 7 6 3 for more e mocmos a CMOS technology that conforms to MOSIS design rules This is the most used CMOS technology in Electric because it is kept current with MOSIS rules See Sectio
338. lib format between 8 05g and 8 05n wrote sizes of BaseRectangle and BaseWidth The Full and Base sizes can be redefined in future versions of technology file To be able to read older Jelib formats correctly after redefinition of Full and Base Technology file can containe explicit sizes of standard nodes and arcs in older library files All sizes in technology files are in display units There is a scale declaration which relates this unit to nanometers Overall Structure Here is a description of Xml technology file in Electric relreases 8 05 and 8 06 lt technology gt is the main element of the Xml technology file It has many Xml specific attributes e name contains the name of this technology inside Electric e class optional contains the name of a Java class which is a subclass of com sun electric technology Technology It can be used to describe things which are not described by the Xml technology class yet The interface with this class is not specified and can be changed If you need a non standard technology feature the better way is to contact Electric developers about this Example lt technology name mocmos class com sun electric technology technologies MoCMOS xmlns http electric sun com Technology xmlns xsi http www w3 org 2001 XMLSchema instance xsi schemaLocation http electric sun com Technology technology Technology xsd gt Inside of the lt technology gt element are these subelements e
339. lister The Always drawn check box requests that the export label should always appear regardless of the connection or expansion of its cell Typically an export label on an instance of a cell is not displayed when that port is connected to an arc or when the instance is expanded This check box overrides the suppression Another special check box Body only requests that this export not appear when an icon is generated for the cell This is useful for power and ground exports or duplicate connection sites on a single network Using the Electric VLSI Design System version 8 11 67 Chapter 3 Hierarchy You can control exporting of all of the ports on Ports on node Flip Flop Ffrsms 0 the currently highlighted node with the een je 5 Manipulate Ports on Node command in T Ick linput wire 0 menu Export This dialog shows all ports and I clear input wire 0 lets you select sets of them for reexport iit input wire 1 Toggle Selection ReExport Selected Ports Select All Ports Delect Exports on Selected Ports Deselect All Ports Show Selected Ports There are many special exporting commands that are primarily used in array based layout If a cell instance is replicated many times and the instances are wired together then ports on the edge of the array are the only ones that are not wired These ports define the connections for the next level of hierarchy What you want to do is to create exports for all unwired port
340. lls bitslice sch lay 34 Exports 10 FI Parts 3 1 2 mipscells mux4 11 Wires attached 2 1 mipscells inv o 3 4 mipscells mux2 t db Wires 21 mipscells mux2 mux2 0 in Cell mipscells mux2 src1 mux in Cell mipscells mux2 src1 mux in Cell mipscells mux2 wdmux in Cell n f mipscells mux2 wdmux in Cell m mipscells mux2 adrmux in Cell r mipscells mux2 admux in Cell m 2l gt The tree node corresponding to the first class is selected and has the name 3 4 mipscells mux2 which has the following meaning e 3 The sequence number of this class e 4 The number of mismatched parts in one of the two cells whichever is bigger In our example the schematic cell has 4 mismatched part in this class and the layout has 3 mismatched parts in this class The maximum of 4 and 3 is 4 and therefore the tree node has 4 in its name e mipscells Part library e mux2 Part type In the example above part types were enough to partition parts into classes In many other cases like the one in the figure below types are not enough and the number of different wires attached to a part is employed as an additional partitioning criterion When a part class node is selected the right half of the window displays a two column table Each column corresponds to one of the compared cells and has a list of that cell s parts which belong to the selected part class Matched parts are printed in green
341. lly you can rearrange the order in which the nodes will be listed with the Reorder Nodes command from the context menu Editing Special Node Information The node cell contains four pictures of the Function contact node on the bottom and textual information above that You can update the textual information entries by double clicking on Square node No them Serpentine transistor No Invisible with 1 or 2 arcs No The Serpentine transistor entry indicates Lockable No that this is a MOS transistor and it can take Spice template arbitrary outline information to describe its geometry see Section 7 4 1 The Square entry forces the node to nto acon AES always have the same X and Y dimension when scaled The Invisible with 1 or 2 arcs entry indicates that the node will not be drawn if it is connected to exactly one or two arcs metat 1 This is useful in schematic pins which are visible only when unconnected or forming a junction of 3 or more wires The Lockable entry indicates that this node can be made unchangeable along with other lockable primitives when the lock is turned on during editing see Section 6 2 for more on locking these primitives This is typically used in array technologies such as FPGA see Section 7 6 2 226 Using the Electric VLSI Design System version 8 11 Chapter 8 Creating New Technologies The Spice template entry is an overriding line of Spice code to be emitted for this pr
342. lows duplicated objects to be positioned interactively This is the default condition However if this is unchecked then the Duplicate command in menu Edit will place a copy automatically without allowing the new location to be specified by the cursor e Duplicate In Place causes the duplicate command to place the duplicated object exactly where the original was This is useful when you have layout geometry that needs to stay on a grid e Duplicate Array Paste copies exports requests that these node copying operations also copy their exports This includes the Duplicate Array and Paste commands in menu Edit See Section 6 4 for more on arrays e Increment rightmost array index requests that when multidimensional busses or nodes are duplicated the rightmost index is incremented When this is not checked the leftmost index is incremented See Section 6 9 3 for more on bus naming e Extract copies exports requests that extraction of cell instances also copy the exports Extraction is done with the Extract Cell Instance command in menu Cell See Section 3 8 for more on extraction Using the Electric VLSI Design System version 8 11 145 Chapter 6 Advanced Editing 6 3 Preferences All preferences in Electric are controlled with the Preferences command in menu File You can also get Preferences with this icon on the tool bar This dialog has a central panel with a tree structured list of all of the prefer
343. lt lambda gt lt portArc gt Polysilicon 1 lt portArc gt lt pureLayerNode gt Using the Electric VLSI Design System version 8 11 241 Chapter 8 Creating New Technologies Arcs lt arcProto gt elements describe primitive arcs in the technology They have these attributes e name is the name of the arc prototype The instances of the primtive arc in Electric libraries reference this name e fun describes the arc function UNKNOWN METAL1 METAL2 METAL3 METAL4 METALS METAL6 metal METAL7 METAL8 METAL9 METAL10 METAL11 METAL12 metal POLY 1 POLY2 POLY3 polysilicon DIFF DIFFP DIFFN DIFFS DIFFW active BUS busses UNROUTED unrouted for routers NONELEC non electrical for constraints Example lt arcProto name P Active fun DIFFP gt Inside of the lt arcProto gt element are these subelements 242 e lt oldName gt the name of this primitive arc in previous versions of the technology optional e lt wipable gt flag to mark that the arc erases its pins This flag is usually present in layout technologies e lt curvable gt flag to described round arcs It is not supported in the current implementation e lt special gt flag related to the component menu e lt skipSizeInPalette gt flag related to the component menu e lt notUsed gt flag to forbid use of this primtive arc in libraries e lt extended gt default state of end extension for this arc e lt fixedAngle gt default state of
344. lt primitivePort name metal 1 metal 2 gt lt portAngle primary 0 range 180 gt lt portTopology gt 0 lt portTopology gt lt box gt lt lambdaBox k1x 1 0 khx 1 0 kly 1 0 khy 1 0 gt lt box gt lt portArc gt Metal 1 lt portArc gt lt portArc gt Metal 2 lt portArc gt lt primitivePort gt lt minSizeRule width 5 0 height 5 0 rule 8 3 9 3 gt lt primitiveNode gt Node Layers lt nodeLayer gt elements describe NodeLayers in the primitive nodes They have these attributes e layer references the layer of the NodeLayer e style is either FILLED CLOSED or CROSSED Layout nodes should be FILLED CROSSED is used only with pins o portNum relates a primitive port to this NodeLayer It is the O based index of the lt primitivePort gt subelement of lt primitiveNodeElement gt Negative values mean that this NodeLayer is not related to any port If this attribute is omitted the first primitive port in the list is chosen e electrical marks this NodeLayer be used only in either electrical or non electrical node layers For example a transistor s Polysilicon is defined with electrical layers as a gate poly and two poly ends The same transistor s Polysilicon is defined with one long stripe in non electrical layers If this attribute is omitted the NodeLayer appears in both electrical and non electrical lists This feature may be removed in future Electric versions So the
345. m the allocated process memory and can also bloat file sizes when they are no longer needed This command deletes saved sizes on a per node basis e Clear Sizes in all Libraries This command deletes saved sizes everywhere e Estimate Delays This command computes load factors for every network in the cell The LEsettings Cell There is a cell called LEsett ings with the following attributes e su The step up or fan out per stage e wire_ratio The lambda of gate per fF of wire capacitance to convert wire capacitance to equivalent gate size see LEWIREs e epsilon The convergence limit Make smaller to get more accurate results but requires more iterations e max_iter The maximum number of iterations the algorithm will go through before giving up e gate_cap The fF per lambda of gate e alpha A modulation applied to the logical effort defined on each gate s output It is defined as the ratio of diffusion capacitance to gate capacitance and it converts the output self loading diffusion capacitance to equivalent units of input loading capacitance The self loading is calculated as selfXsize outputLE alpha Therefore if you set alpha to 0 the self loading load is ignored for logical effort calculation e xlinverter_length The length in lambda of the gates in a X 1 inverter e xlinverter_nwidth The width in lambda of the nmos gate in a X 1 inverter e xlinverter_pwidth The width in lambda of the pmos gate in a X 1 inv
346. m the popup list click in the edit window to place the instance Library purpleFour 0 view al Fite J Another way to place an instance of a cell is to use the Place Cell Instance command in menu Cell You will be shown a list of cells that are available for creation After selecting one click to create an instance in the current cell The cell selection dialog has three controls at the top for viewing cells The Library popup lets you choose which library to examine You can choose ALL to see cells from all libraries The View popup lets you see inv_passgate ic inv_passgate sch only those cells in the specified view Again you can inv doc choose All to see all views The Filter field contains inv ic a regular expression that must match a cell name in invisch order to list it For an explanation of the Evaluate Numbers when Sorting Names checkbox see Section 3 7 1 V Evaluate Numbers when Sorting Names Cancel New Instance amp Close If you place an instance from a different library that library will be linked to the current one Linked libraries are read from disk together and form a single hierarchy that spans multiple files See Section 3 9 1 for more on libraries An alternate way to create a cell instance is to duplicate an existing one on the screen This requires that an instance of that particular cell already exist Select the existing cell and use the Duplicate command in
347. me Metal 1 Metal 2 Con fun CONTACT gt Inside of the lt primitiveNode gt element are these subelements 244 e lt oldName gt optional name of this primitive node in previous versions of the technology e lt shrinkArcs gt flag to shrink arcs connected to the node This flag should be on only for PIN nodes e lt square gt flag to restrict the node to be square It is used in round layout technologies e lt canBeZeroSize gt flag to allow the size to become zero not used in layout technologies Using the Electric VLSI Design System version 8 11 Chapter 8 Creating New Technologies e lt wipes gt flag which is not used in layout technologies e lt lockable gt flag which is used in arrayed technologies like FPGA e lt edgeSelect gt flag which is not used in layout technologies e lt skipSizeInPalette gt flag related to the component menu lt notUsed gt flag to forbid use of this primtive node in libraries lt lowVt gt flag to mark a low vt transistor lt highVt gt flag to mark a high vt transistor lt nativeBit gt flag to mark a native transistor lt od18 gt flag to mark an od18 transistor lt od25 gt flag to mark an od25 transistor lt od33 gt flag to mark an 0d33 transistor lt diskOffset gt tells how sizes were written in older library files It has this attribute untilVersion references the tech attribute of lt version gt elements above This disk offset is applied to Jelib libraries wi
348. ments an interface to the Concurrent Versioning System CVS program a popular version control system This section assumes the user is familiar with how CVS works and the various CVS commands Such information is readily available on the web _ Categories CVS USER Preferences General General Selection Key Bindings Nodes To enable Electric to use CVS you must Spee first configure the CVS Preferences in File Project Management Preferences General section CVS tab CVS must be enabled and the Printing repository location must be specified rii I Enable cvs Electric does not implement the CVS H O Tools protocol it merely provides an interface to Technology CVS Repository interact with an external CVS program so CVS program evs that program must be specified in the Export Import preferences Reset Reset All Only resets USER Preferences Help Apply The Electric GUI allows the user to perform the common CVS commands via the menu File CVS or via the popup context menu on the libraries and cells listed in the explorer tree The menu commands apply to all libraries the explorer tree context menus apply only to the selected library With CVS enabled in Electric the explorer tree uses colors to show the state of libraries or cells in CVS When using a JELIB or ELIB library format the library name and all cells are the same color because the entire library is a single file When using a
349. menu Edit Then move the cursor to the intended location of the new instance and click to create the copy Note that this command copies all attributes of the original node including its orientation 62 Using the Electric VLSI Design System version 8 11 Chapter 3 Hierarchy Y9OQ4QQAAQQ _ jb 4 QQQQAO MQW SRR XX QRQQY XQ Qn SV RQ NN WSN i r ANN NANN When a cell instance is being NX SS created the cursor points to its SX SOOO anchor point The anchor point is RN WS r F r ASS O SN that point inside of the cell where Cell Instance NLL SS WOO SSS the coordinate space has its origin This is often defined by the location of a cell center node inside of the cell see Section 7 6 3 Cell Center Most cells have a cell center node placed automatically in them If there isn t one and you want it click on the Misc button in the component menu on the left and choose Cell Center A cell center node placed inside of the cell definition affects the anchor point for all subsequent creation of instances of the cell The cell center is always at the origin of the cell If you move it then the origin moves in other words moving the cell center is really like moving everything else in the cell Note that the cell center is hard to select and can only be moved in special select mode see Section 2 1 5 You can move the cell center to the center of the selected objects by using the Cell Center to C
350. ming declarations in the gate description In this case the primitive is assigned a default priority of 2 This base priority can be temporarily upgraded to a value of 1 if a random trial is successful during the course of a simulation run The user is advised to leave the priority settings at their default values unless there is a Specific requirement which demands priority readjustment The Set Statement The set statement is used to initialize signals to specific logic states before the simulation run takes place The format for the set statement is shown below Format set signall lt state gt lt strength gt signal2 lt state gt lt strength gt Example set inputl H 2 input2 L input3 X 0 set count 4 multiplier 5 divisor 7 2 If the user does not specify a strength value the signal will be assigned a default logic strength of 3 VDD This default setting will override any gate output because the default strength of 2 is used for gate outputs The user will find this feature useful in situations where some of the inputs to a logic gate need to be set to a fixed state for the entire duration of the simulation run For example the set and reset inputs of a flip flop should be tied low if these inputs are not being driven by any logic circuitry All instances of a gate entity which contains a set statement will have their corresponding simulation nodes set to the desired state Using the Electric VLSI Design System
351. mment gt The skipNCC annotation should be added to a cell when e Its schematic and layout won t pass either flat or hierarchical NCC and e You want a hierarchical NCC of the cell s parent to flatten the cell If a cell has a skipNCC annotation then a hierarchical comparison won t check it and will flatten through that cell s level of hierarchy A common reason for needing this annotation is the unfortunate situation in which the exports of the schematic and the layout don t match A skipNCC prevents NCC from reporting export mismatches because 1 The cell is not checked by itself and 2 When a parent of the cell is checked the cell s exports are discarded because NCC flattens through the cell Although not always possible it s better to fix export mismatches because fixing them will yield clearer mismatch diagnostics when there is a problem All the characters following the keyword to the end of the line serve as a comment This is useful for documenting why this annotation was necessary When you ask NCC to compare every cell in the design NCC will tell you which cells it is skipping and why For example if a cell includes the NCC annotation skipNCC layout is missing ground connection then NCC will print Skipping NCC of A because layout is missing ground connection The skipNCC annotation is created by the Skip NCC command and may be placed on any schematic or layout cell in the cell group In general it is preferable to place the anno
352. mnemonics Java Script Examples Here are some example scripts in the Java Bean Shell For more information about accessing the internals of Electric read the Javadoc in the source code com sun electric database hierarchy Cell This example searches the com sun electric database topology NodeInst current cell printing all com sun electric tool Job transistors and all exports java util Iterator that start with the letter the current cell a Job getUserInterface getCurrentCell Notice that Electric s find all transistors Export object must be a for Iterator it c getNodes it hasNext full lified NodeInst ni it next uuy quatiea name if ni getFunction isTransistor because the name System out println Found transistor Export is used for other ni describe false reasons in the Bean Shell This also applies to Electric s EPoint class find all exports that start with A for Iterator it lay getPorts it hasNext com sun electric database hierarchy Export e com sun electric database hierarchy Export it next if e getName toLowerCase startsWith a System out println Found export e getName 174 Using the Electric VLSI Design System version 8 11 Chapter 6 Advanced Editing import com sun electric database hierarchy Cell This example creates import com sun electric database topology NodeInst a new cell places
353. more Cancel move if move done within 200 ms ca aia a fa O e IV Highlight Connected Objects Export Import I Can select objects whose layers are invisible The Dragging must enclose entire object requests that area selection Reset Reset All completely enclose an object in order to Only resets USER Preferences select it The default is that any object Help Apply touching the area is selected To prevent accidental moving of an object after selecting it object movement is disabled for a short time after the selection click This delay can be controlled When the cursor roams over a circuit it shows a preview of what will be selected by the next click The advance preview is shown in a different color than the actual highlighting initially blue but this can be changed with the Layers Preferences see Section 4 6 2 This feature is called mouse over highlighting If you do not want to see this preview uncheck Enable Mouse over highlighting When a node is selected all connected circuitry is also selected To disable this uncheck Highlight Connected Objects When all of the layers of a node or arc are made invisible the nodes and arcs are not selectable To allows invisible nodes and arcs to be selectable check Can select objects whose layers are invisible See Section 4 5 3 for more on layer visibility 44 Using the Electric VLSI Design System version 8 11 Chapter 2 Basic Editing 2
354. mport Reset Reset All changes to installed Only resets USER Preferences Help Apply until Electric is next started Cancel Technology Add button and browse to Design Rules the XML file that was ae produced by the technology Icon editor If you no longer want to have a technology installed in Electric select it and use the Remove button Note that technologies do not take effect Since XML files describe technologies you can also edit technologies manually by editing these files see Section 8 10 for the XML file format To generate the XML file for a given technology use the Write XML of Current Technology command in menu Edit Technology Specific It is also possible to extract an XML file for a technology from an older version of Electric To do this you need the JAR file for that release Use the command Write XML of Technology from Old Electric Build and specify both the Electric JAR file and the desired technology from that build Note that XML files cannot be produced for the special technologies Schematics and Artwork Cleaning Up After a few rounds of technology editing there may be many libraries and technologies You can delete the current library with the Close Library command of the File menu to make another library current use the Change Current Library command of the File menu Using Technology Libraries Once a library has been successfully built that describes a
355. mulation node changes state the simulation engine looks through the netlist for other nodes that could Using the Electric VLSI Design System version 8 11 287 Chapter 9 Tools potentially change state Obviously only simulation nodes joined by model gate or function entities can potentially change state If a state change or event is required based on the definition of the inter nodal behavior as given by the model gate or function definition the event is added to the list of events scheduled to occur later in the simulation When the event time is reached and the event is fired the simulator must again search the database for other simulation nodes which may potentially change state This process continues until it has propagated across all possible nodes and events 9 5 4 ALS Gates The gate entity is the primary method of specifying behavior It uses a truth table to define the operational characteristics of a logic gate Many behavioral descriptions need contain only a gate entity to be complete The gate entity is headed by the gate declaration statement and is followed by a body of information The gate declaration contains a name and a list of exported simulation nodes which are referenced in a higher level model description The format of this statement is shown below Format gate name signall signal2 signal3 signalN Example gate nor2 in1 in2 out gate and3 a b c output There is no limit on the number o
356. n 7 4 2 for more The cell tech MOSISCMOS lay in the sample library illustrates this technology e mocmosold an older version of the mocmos technology kept for compatibility with older designs The technology should not be used for any new designs e mocmossub an older version of the mocmos technology that focuses on submicron facilities The technology should not be used for any new designs because the mocmos technology incorporates these submicron features e nmos an old nMOS technology based on the book Mead C and Conway L Introduction to VLSI Systems Addison Wesley Reading Massachusetts 1980 The cell tech nMOS lay in the sample library illustrates this technology e pcb a printed circuit board technology with 8 layers The cell tech PCB sch in the sample library illustrates this technology e remos a round CMOS technology based on work at CalTech The cell tech RoundCMOS lay in the sample library illustrates this technology e schematic a schematic capture facility See Section 7 5 1 for more The cells tech SchematicsDigital sch and tech SchematicsAnalog sch in the sample library illustrates the digital and analog capabilities of this technology o tft an organic thin film technology Thin film transistors are p type depletion devices formed with an aluminum gate gold source drain electrodes and a pentacene active area Two layers of metal are available for routing signals Metal 1 the aluminum gate
357. n Horizontally to Right moves all of the selected objects so that their left edge or right edge is moved to the leftmost or rightmost edge of those objects The command Align Horizontally to Center moves all of the selected objects so that their X center is at the location of the X center coordinate of those objects The command Align Vertically to Top and Align Vertically to Bottom moves all of the selected objects so that their top edge or bottom edge is moved to the topmost or bottommost edge of those objects The command Align Vertically to Center moves all of the selected objects so that their Y center is at the location of the Y center coordinate of those objects 4 7 4 Measuring a If you wish to find the distance between any two points on the display use the Measure tool from the tool bar This mode can also be invoked with the Toggle Measure Distance command in menu Edit Modes Edit or the Toggle Measurement Mode command in menu Window Measurements Another way to measure distances is to use the cursor coordinates displayed in the status area Measurements remain on the screen until removed with the Clear Measurements command in menu Window Measurements Measuring in an Edit Window In measure mode each click places a new point on the display and shows the distance to the previous point Clicking the right button lets you start a new measure point without connecting it to the previous one Double clickin
358. n System version 8 11 119 Chapter 4 Display Cell instances will be drawn as bounding K boxes if they are unexpanded top illustration and will show their contents if expanded bottom illustration Troubleshooting If you are running on Windows and are using MDI mode multiple document interface the 3D display may not work properly See Section 1 3 for instructions on running Electric in SDI mode Because Java3D makes use of the graphics hardware on your computer it may be useful to test that hardware with the Test Hardware command in menu Window 3D Window 120 Using the Electric VLSI Design System version 8 11 4 10 2 Preferences Chapter 4 Display To control the 3D view use the 3D Preferences in menu File Preferences Display section 3D tab This provides access to most of the parameters that control 3D viewing The only other controls available are the colors used to draw 3D features which are available in the Layers Preferences see Section 4 6 2 In the 3D Preferences the thickness and Z distance height of each layer can be controlled as well as the view mode the Z axis scale and use of antialiasing On the left side of this dialog is a list of layers in the current technology On the right side is a cross sectional view of the chip showing the relative position of each layer You can select a layer by clicking on either side of the dialog The currently selected l
359. n be costly you might want to delay resimulation until all stimuli have been set If you uncheck this item you must issue the Update Simulation Window command to re run the simulation Other Controls At the top of the waveform window above the signal names are many useful controls Those relating to time have already been discussed Here are the remaining buttons e Refresh Refreshing the simulation causes it to reload from the original source In the case of external simulation it is assumed that the simulation was re run and the output file is different so the simulation output file is re read In the case of built in simulators it is assumed that the original circuit has changed so it is re evaluated and reloaded into the simulator This function is also 128 Using the Electric VLSI Design System version 8 11 Chapter 4 Display available with the Refresh Simulation Data command in menu Window Waveform Window e The Panel popup This is a list of all panels including the hidden ones Selecting a panel from this list toggles its hidden state making a visible one disappear and making a hidden one reappear e Grow and Shrink These buttons which show a waveform being stretched or squeezed cause the minimum panel size to change By shrinking the panel size more of them can fit in the window without having to use a slider to access them Also the panels can be resized individually by dragging any of the dividers
360. n cell so it typically will have nodes from the Artwork technology to describe its appearance See Section 7 6 1 for more on the Artwork technology e Exports optional This allows the icon cell to be connected to the circuitry e Parameters optional This allows custom values to be specified on each node Parameters are created with the Cell Parameters command in menu Edit Properties See Section 6 8 5 for more on parameters e At least one template The template is the essential part of the Node because it describes exactly what Spice or Verilog will be emitted The Spice template is created with the Set Generic Spice Template command in menu Tools Simulation Spice If the template is specific to a particular version of Spice use the appropriate template command Set Spice 2 Template Set Spice 3 Template Set HSpice Template Set PSpice Template Set GnuCap Template Set SmartSpice Template Set Assura CDL Template or Set Calibre Spice Template You can also create a Verilog template by using the Set Verilog Template command in menu Tools Simulation Verilog And can customize instances of the current cell by prepending per instance parameters with Set Verilog Default Parameter Note that a single cell can contain both Verilog and Spice templates Once a template has been created double click on the text to edit it To explain the format of a template a DC SPICE_template V node_name plus minus DC Voltag
361. n export becomes the network name for all arcs connected to that export Similarly the name given to an arc by setting the name field in the Object Properties dialog becomes the name of the network for all connected arcs You can rename a network by changing the name of a connected export or arc Two phenomena can occur in network naming a network can be multiply named and it can span disjoint circuitry A network has multiple names when two or more connected arcs or exports are named with different names For example if you make an export on a contact node and call it clock then you select an arc connected to that contact node and name it sig the circuitry will be on the network clock sig Thus both names now apply to the same network The other phenomenon of network naming is that a single network can include unconnected parts of the circuit This happens when arcs in unconnected parts of the circuit are given the same name This causes the two arcs to be implicitly joined into one network Because this network naming phenomena is most commonly used in schematics the unification of like named networks only happens in cells with the schematic view 6 9 3 Bus Naming The Bus arc of the Schematics technology is a special arc that can carry multiple signals see Section 7 5 1 When giving a network name to Bus arcs it is possible to specify complex bus names e Simple arrays Bus names can be arrays for example A 0 7 which
362. n information etc The primitive nodes in a technology come in three styles e PINS are used to join arcs so there is one pin for every arc in the technology e COMPONENTS are the basic nodes used in design contacts transistors etc e PURE LAYER NODES are used for geometric manipulation see Section 6 10 1 There is one pure layer node for every layer in the technology The component menu in the side bar on the left side of the editing window shows arcs on the left the menu entries with red border pin nodes in the center column these appear as boxes with a cross inside and components on the right the more complex layer combinations See Section 4 5 1 for more on the component menu These are the technologies that come with Electric Some of these technologies are illustrated with sample cells in the built in sample library To access this library use the Load Sample Cells Library command in menu Help e artwork is used for drawing graphics for example when designing icons See Section 7 6 1 for more The cell tech Artwork in the sample library illustrates this technology e bicmos a hybrid bipolar CMOS technology as specified by MOSIS using older N Well SCE rules e bipolar a bipolar technology self aligned single poly The cell tech Bipolar lay in the sample library illustrates this technology e cmos a generic CMOS technology described in a old paper Griswold Thomas W Portable Design Ru
363. n it as in this example then the export disappears and so do all arcs connected to the port on instances of the current cell for more information on hierarchy see Chapter 3 of output node NN The exception to these rules is the Nodes Preference Reconstruct arcs and exports when deleting instances see Section 6 2 which requests that when a cell instance is deleted and it has arcs connected to it or exports from it these arcs and exports will be reconstructed so that they continue to exist Reconstruction consists of creating pins where the cell instance ports used to be so that the arcs and exports can continue to exist Using the Electric VLSI Design System version 8 11 51 Chapter 2 Basic Editing When an area is selected instead of objects see Section 4 7 2 the Edit Erase Selected command erases all geometry in the highlighted area All arcs that cross into that area will be truncated Thus this command erases precise geometry independent of the structure of nodes and arcs Note that the area to be erased is adjusted by the current alignment values see Section 4 7 2 Before After Two special arc deletion commands are Arcs Connected to Selected Nodes and Arcs Connected Between Selected Nodes in menu Edit Erase The first command removes all arcs that have either end on a selected node The second command removes all arcs that have both ends on selected nodes 52 Using the Electric VLSI Des
364. n libraries are read that make use of nodes with the old name Therefore you must create a new node or arc first convert all existing ones to the new type and then delete the old node or arc 232 Using the Electric VLSI Design System version 8 11 Chapter 8 Creating New Technologies Many of the pieces of special information on the top of the node and arc cells apply to newly created circuitry only and do NOT affect existing components already in libraries The arc factors Fixed angle Wipes pins Extend arcs and Angle increment have no effect on existing libraries The node factor Square node also has no effect on existing circuitry and gets applied only in subsequent designs Other factors do affect existing circuitry Changes to the Function field in both arcs and nodes pass to all existing components thus affecting how analysis tools treat the old circuits If the Serpentine Transistor field in nodes is turned off any existing transistors that have serpentine descriptions will turn into large rectangular nodes with incorrect connections i e get trashed Unfortunately it may become impossible to keep the Serpentine Transistor field on if the geometry does not conform to standards set by the technology editor for recognizing the parts If a node is not serpentine turning the factor on has no effect Finally the node factors Invisible with 1 or 2 arcs and Lockable correctly affect all existing circuitry A more c
365. n menu Edit Selection or just type a To set a 1 value on a signal select it in either the waveform or the schematic layout and use Set Signal High at Main Time in menu Tools Simulation Built in or just type V You can drag the main time cursor the dashed line to any point in the waveform window Notice that as you drag it level information is displayed in the schematic layout See Section 9 5 1 for more on the IRSIM simulator Besides built in simulation Electric can generate input decks for many popular external simulators see Section 9 4 1 For example to simulate with Spice follow these steps e Use the Spice Preferences to select the Spice engine that you have Spice 3 HSpice PSpice etc Use the Write Spice Deck command in menu Tools Simulation Spice to generate an input deck for Spice e Run the simulation externally e Use the Plot Spice Listing command in menu Tools Simulation Spice to read the output of Spice and display it in a waveform window See Section 9 4 3 for more on Spice Using the Electric VLSI Design System version 8 11 39 Chapter 1 Introduction 40 Using the Electric VLSI Design System version 8 11 Chapter 2 Basic Editing 2 1 Selection 2 1 1 Selecting Nodes and Arcs Electric is a noun verb system meaning that all commands work by first selecting something the noun and then doing an operation the verb For this reason selection is import
366. n read To detect this situation use the Find Unused Library Files in menu File Check Libraries This command will look for unused library files in the disk directories used by the circuit and will report them to you so that the disk can be cleaned up The command does not delete the library files that is left to the user If referenced libraries are edited independently it is possible that a reference to a cell in another library will not match the actual cell in that library When this happens Electric creates a placeholder cell that matches the original specification Thus the link to the referenced library is broken because the cell there does not fit where the instance should be To see a list of all placeholder cells that were created because of such problems use the General Cell Lists command in menu Cell Cell Info and select Only placeholder cells Electric comes with some built in libraries e There are two Spice primitive libraries see Section 9 4 3 e A library of examples can be loaded with the Load Sample Cells Library command in menu Help Another simple library can be found in the Load Library command in menu Help 3D Showcase e A set of gates useful for Logical Effort see Section 9 9 can be loaded with the Load Logical Effort Libraries Purple Red and Orange command in menu Tools Logical Effort Additional libraries are available at the Static Free Software website www staticfreesoft
367. n series so copy and paste the transistor you have drawn You can also duplicate the selected object with the Duplicate command in menu Edit or just type Ctrl M Drag the two transistors along side each other so they are not quite touching Click the diffusion source drain of one of the transistors and right click on the diffusion of the other transistor to connect the two Notice that Electric uses nodes and arcs in IC layout as well as in schematics Once connected drag the two transistors until the polysilicon gates are 3 units apart looking like they do below You will probably find it helpful to turn on the grid type Ctrl G The grid defaults to small dots every unit and large dots every 10 units You can change this with the Preferences command in menu File Display section Grid panel Change the Frequency of bold dots to 7 because the cells in this library have a wire pitch of seven You can move objects around with the arrow keys on the keyboard The distance that they move defaults to 1 unit but this can be changed by using the Make grid larger or Make grid smaller icons in the toolbar or by pressing the f or h keys You will avoid messy problems by keeping your layout on a unit grid as much as possible Inevitably though you will create structures that are an odd number of units in width and thus will have either centers or edges on a half unit boundary To move an object 7 units per click or the equivalent of
368. n the and2 sch cell Use the New Cell command in menu Cell or just type Ctrl N Enter nand2 as the cell name and select schematic as the view The editing window will now have the title mipscells nand2 sch indicating the library cell name and view It is useful to put a label inside a cell in addition to assigning its given name To label your cell select the Components tab of the sidebar on the left click on Misc and select Annotation text Move the cursor to the location where you want the label to appear and click to create the text Change the text by double clicking on it and typing nand2 When done typing click away from the text to exit the in place editing the text is now selected with an X through it Then bring up the full properties dialog for this text with the Object Properties command in menu Edit Properties or just type Ctrl I Set the Text Size to 5 units and click OK When your cell is finished you can move this label to a sensible location Electric defines various technologies for schematics and layout To draw transistor level schematics you can use the symbols in the Components tab of the side bar Using the Electric VLSI Design System version 8 11 31 Chapter 1 Introduction Your goal is to draw a gate like the one shown here Turn on the grid to help you align objects To do this use the Toggle Grid command in menu Window or just type Ctrl G Click on an nMOS transistor sym
369. nanometers or 0 4 x 0 6 microns To set the scale use the Scale Preferences in menu File Preferences Technology section Scale tab Scale only applies to integrated circuit layout technologies There is no scale for Schematics Artwork and other nonlayout technologies 188 Scale PROJECT Preferences The technology scale converts grid units to real spacing on the chip bicmos scale 1000 0 nanometers bipolar scale 2000 0 nanometers cmos scale 2000 0 nanometers fpga scale 2000 0 nanometers MOCT 0 0 nanometers mocmosold scale 1000 0 nanometers mocmossub scale 200 0 nanometers nmos scale 2000 0 nanometers pcb scale 1270000 0 nanometers remos scale 2000 0 nanometers tft scale 5000 0 nanometers Technology scale 200 0 nanometers 0 2 microns Categories General Display 0 G Tools C Technology Added Technologies Technology Design Rules Import Reset All Only resets USER Preferences Apply Export ik Reset Help Cancel il Using the Electric VLSI Design System version 8 11 Chapter 7 Technologies 7 2 2 Units Preferences YO Units USER Preferences Tools Technology so Added Technologies Technology By default distances are expressed in Design Rules dimensionless units and the true unit size is Scale i CA shown in the status bar The Units Preferences in ie menu F
370. nd then select another before pasting then the copied object will replace the selected object changing its type and other properties similar to the Change command see Section 6 6 If you want the Paste command to make a second copy be sure that nothing is selected when you issue the command Thus duplicating an object cannot be done by issuing a Copy and then a Paste You must do a Copy then deselect the object then do a Paste Using the Electric VLSI Design System version 8 11 143 Chapter 6 Advanced Editing 6 2 Creation Defaults The Duplicate command is useful because a node may have been modified rotated scaled etc and duplication preserves all of those changes Using Copy and Paste does the same thing Another way to create nodes that are nonstandard is to set creation defaults Preferences _ Categories E General General Selection Key Bindings Arcs Project Management cys Printing Display a yo Tools Technology To do this use the Nodes Preferences in menu File Preferences General section Nodes tab The top part of the dialog controls new primitive nodes You can change the default size of any primitive node by choosing the node and changing the values Export Import Reset All Only resets USER Preferences Apply The middle section of the dialog controls cells Reset Help Cancel e Check cell dates during editing requests tha
371. nd use the Object Properties command in the Edit Properties menu In the full dialog obtained by clicking the More button select List Shows Bus Members to see a list of networks on the selected bus arc When a node s port is a bus you can see the signals on that bus by selecting that port of the node and using the Object Properties command In the full dialog select Bus Members on Port to see the signals Using the Electric VLSI Design System version 8 11 165 Chapter 6 Advanced Editing Arrayed Nodes Besides using array names on busses you can also give array names to cell instances in a schematic Netlisters will create multiple copies of that node named with the individual elements of the array When a cell instance is arrayed the connections to its ports can be similarly arrayed For example suppose that schematic cell X has wire port Y and bus port Z 1 2 An instance of cell X is arrayed by giving it the name M 2 4 Ports Y and Z can be connected in two ways e Implicit connection to all instances top illustration If the wire port Y is connected to a single wire A then wire A connects to port Y on all three instances of cell X If the bus port Z is connected to a 2 wide bus B then each element of that bus connects to the same element of bus port Z on all three instances of cell X So B 1 connects to port Z 1 and B 2 connects to Z 2 on all three instances M 2 M 3 and M 4 e Explicit conn
372. nected layers and ignore overlap when considering spacing distance The wide rules apply to large geometry Although some technologies may have many different rules for different definitions of large the MOSIS CMOS technology has only one such rule Additional rules can be controlled with the Add Wide Rule and Delete Wide Rule buttons The bottom of the dialog has a Min resolution field which is the minimum resolution that can be manufactured If zero no resolution check is done When checking resolution all geometry of that size or less will be flagged as resolution errors For example current MOSIS rules require that no boundaries be quarter unit or less so a value of 25 in this field will detect such violations When rules have been changed they are saved with your Preferences To save them independently of the Preferences use the Export DRC Deck command in menu Tools DRC to write an XML file with the design rules Use the Import DRC Deck command to restore these rules Note that the MOSIS CMOS design rule 6 7b is not checked by Electric because it is difficult to detect properly This error is never fatal and the worst case of missing this error is that active and poly are closer by 1 2 lambda which merely results in an increase in capacitive coupling between them If this fringing capacitance is important you ve probably got so much polysilicon in your circuit that it has bigger problems Using the Electric VLSI De
373. nes throughout the circuit and wish to make sure that all of the export names on this network have some variant of the name phi By quickly examining this list you can see all of the names that have been used on the network throughout the hierarchy List Exports below Network lists all export names on the currently highlighted network This list is similar to the one generated by List Exports on Network except that it works only on cells below the current one List Connections on Network lists all nodes in the current cell that are connected to the current network This list includes only those nodes at the ends of the net not the pin or contact nodes used inside of the network The command is useful if you are at one end of a wire and want to check to see what is at the other end List Geometry on Network lists all geometry in the current cell that is connected to the current network This reports the area and perimeter of all attached layers List Total Wire Lengths on All Networks lists the lengths of all networks in the current cell Show Undriven Networks lists all networks in the current cell or below it in the hierarchy that are undriven An undriven network is one that does not connect to the source or drain of a transistor Using the Electric VLSI Design System version 8 11 163 Chapter 6 Advanced Editing 6 9 2 Naming Networks Network names are derived from export names and arcs that are named in a cell The name given to a
374. node extractors cannot work when the design rules are bad So each time LVS problems are found the layout must be fixed and made DRC clean again Since Electric can extract connectivity for LVS without having perfect design rules the first step is to get the layout and schematics to match Then the design rules can be cleaned up without fear of losing the LVS match Common user interface One CAD system with a single user interface can be used to do both IC layout and schematics Electric tightly integrates the process of drawing separate schematics and has an LVS tool to compare them The disadvantages of connectivity based IC layout are also known o It is different from all the rest and requires retraining This is true but many have converted and found it worthwhile Users who are familiar with paint based IC layout systems typically have a harder time learning Electric than those with no previous IC design experience 8 Using the Electric VLSI Design System version 8 11 Chapter 1 Introduction e Requires extra work on the user s part to enter the connectivity as well as the geometry While this may be true in the initial phases of design it is not true overall This is because the use of connectivity early in the design helps the system to find problems later on In addition Electric has many power tools for automatically handling connectivity e Design is not WYSIWYG what you see is what you get because objec
375. nside of the arc the default or on one side of the arc depending on whether it is vertical or horizontal For export names you can control their offset relative to the arc attached to that export For example if a node on the left end of a wire has an export and the Horizontal placement is set to Inside then the export text will attach on the left side causing the label to appear inside of the wire Using the Electric VLSI Design System version 8 11 159 Chapter 6 Advanced Editing 6 8 5 Cell Parameters Parameters are special pieces of text that are passed from icon instances to the schematic cells Parameters are defined in the icon or schematic cell and then they appear on the icon instances Users can set different values on each icon instance and these values will be passed down into the schematic and applied as necessary The computer programming equivalent of this is that the cell s parameter is the formal value and the instance parameters are the actual values For example an inverter schematic may have transistor sizes defined with a parameter The actual transistors inside of the inverter schematic will use the parameter values and each inverter instance will have a different parameter value causing that particular inverter to have a different transistor ratio Another example of the use of cell parameters is in the Spice primitives where user defined values such as voltage are communicated into t
376. nside of the ports If an arc moves such that its ends are still in the ports then the nodes don t have to move See Section 5 4 3 for more on arc geometry XV THIS IS RIGHT Now that the nodes are wired together bring the contact in close Notice that the arc has shrunk down to a square with the endpoints very close together If you make the arc rigid the two nodes will be held together in this configuration To do this use the Rigid command in menu Edit Arc As shown here the R on the selected arc tells you that it has been made rigid See Section 5 2 1 for more arc constraints S Another common situation in making contacts meet transistors is when the sizes are not the same In this example the contact is the default size The arc runs from the center of the contact s port to the top of the transistor s port The finished layout is shown on the right 22 Using the Electric VLSI Design System version 8 11 Chapter 1 Introduction X Here are some points about connecting nodes with arcs e By doing it the system understands your circuit connectivity and uses it in many other places e The design rule checker will flag objects that touch but are not connected e After you create one of these structures it can be copied and pasted many times Use the Copy and Paste commands in menu Edit Note that when pasting you must not have anything selected or else it tries to replace the selected objects wit
377. nstance MyCircuit lay Cancel New Instance amp Close 24 Using the Electric VLSI Design System version 8 11 Chapter 1 Introduction The box that appears is a node in the same sense as the contacts and transistors it can be moved wired and so on In addition because the node contains subcomponents you can see its contents by selecting it and using the One Level Down command in menu Cell Expand Cell Instances or click on the hay reu tl ayj opened eye button in the tool bar Note that if the objects in a cell no longer fit in the display window use the Fill Display command in menu Window 1 10 8 IC Layout Tutorial Exports Before you can attach wires to the instance node there must be connection sites or ports on that node Primitive nodes such as contacts and transistors already have their ports established but you must explicitly create ports for cell instances This is done by creating exports inside the cell definition Create New Export xi Export name connection Move the cursor to the window with the lower level cell MyCircuit and select SNE eeii funknown Zl the contact node Then issue the Create Export command in menu Export You will be prompted for an export name Body only and its characteristic the characteristics can be ignored for now Cancel Always drawn Reference export This takes the port on the contact node and exports it to the outside
378. nu Tools Simulation Built in After issuing this command a waveform window will appear to control the simulation see Section 4 11 1 for more To generate an input deck for IRSIM without running the simulator use the IRSIM Write Deck command To simulate an IRSIM deck that is simulate the file not the circuit use the IRSIM Simulate Deck command Note if these commands do not appear in the menu then IRSIM has not been installed Since the IRSIM engine is running inside of Electric you can place stimuli on the circuit and see the results immediately also described in Section 4 11 1 Note that the command to save stimuli Save Stimuli to Disk of menu Tools Simulation Built in writes an IRSIM command file which can be edited by hand Tools Antenna Rules Compaction Coverage DRC Fast Henry Logical Effort NCC Network Parasitic Placement Routing Silicon Compiler ators The Simulators Preferences in menu File Preferences Tools section Simulators tab offers some controls for IRSIM The general controls at the top are discussed in Section 4 11 1 i d Spice Model Files x Import Reset All Only resets USER Preferences Apply IRSIM uses a parameter file to describe timing and parasitic information Two of these files come packaged with Electric scmos0 3 prm and scmos1 0 prm but you can create your own
379. odes with the given name in the schematic and layout to be associated This annotation is useful when local partitioning fails to detect a mismatch but hash code partitioning does In that case force WireMatch can be used to tell NCC that certain node were intended to match With luck a strategically placed forcePartMatch can cause NCC to display fewer hash code mismatches and help the user narrow in on the actual error After fixing the problem you should try to remove all forcePartMatch annotations forceWireMatch lt wireName gt Same as forcePartMatch except that this command works on wires rather than nodes blackBox lt comment gt This annotation placed with the Black Box command tells NCC to ignore the cells in this cell group and assume they are topologically equivalent This annotation is useful when a particular arrangement of layout geometry implements a construct that Electric doesn t understand For example to handle resistors and parasitic bipolar transistors in the layout The blackBox annotation should be used with care because unlike the other annotations NCC has no way of double checking the assertion to insure that it is correct The blackBox annotation may be placed on any schematic or layout cell in the cell group In general it is preferable to place the annotation on the schematic cell because it s more visible to the designer 310 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools 9 7 5 Grap
380. oduction 1 11 7 Schematics Tutorial Hierarchy and Icons Electric supports hierarchy by allowing you to create icons for a schematic and place them in another cell Before creating an icon all connection points to the schematic should be defined To define connection points for a schematic you must create exports on the schematic Create New Export xi Export name fout To see an example of this select the output port Export characteristics output of the Buffer node and issue the Create Export command in menu Export You will Always drawn Salih esl he be prompted for an export name and its EN TA characteristics set the characteristics to Cancel output ou The output port on the buffer node is now exported to the outside world Run a wire from the input side of the And node and export the pin at the end of the wire Your circuit should look like this ou ty Circuit CHi You can now make an icon for this circuit by using the Make Icon command in menu View The icon will be placed in your circuit you may have to move it away from the rest of the circuitry The result will look like this Using the Electric VLSI Design System version 8 11 29 Chapter 1 Introduction New Cell xi Library noname X Name Higher To test this icon in a circuit create a new cell in which to place instances of the icon Use the New Cell command in menu Cell Type the new cell name Higher is used in the
381. of hierarchy and a Global Partition node allows globals to be treated locally See Section 6 9 5 for more on global networks Some commands that analyze a schematic circuit need to know which layout technology will be used to fabricate the design For example when generating a Spice deck from a schematic it is necessary to know the sizes and parasitics that are associated with the actual circuit To set the layout technology to use for schematic circuits use the Technology Preferences in menu File Preferences Technology section Technology tab and set the Use scale values from this technology popup Using the Electric VLSI Design System version 8 11 205 Chapter 7 Technologies Digital Schematics Digital schematics are built with the And Or Xor Buffer Multiplexor and Flip Flop nodes that appear in the component menu By attaching arcs to these components and negating them with the Toggle Port Negation command in menu Edit Technology Specific these turn into NAND NOR Inverter and many other specialized components see Section 5 4 2 The And Or Xor and Multiplexor nodes can accept any number of input connections on the left so they require some care in wiring see Section 1 11 5 The left side has one large input port that allows an arbitrary number of connections Initially wires may attach at only three input locations spaced evenly along the left side However when all three locations are
382. of the ArcLayer The attribute style is either FILLED or CLOSED Layout arcs should be FILLED The lt lambda gt subelement describes extent half width of the ArcLayer from the central line of the arc More formally let a extend be the internal value associated with the arc instance in the Electric database The width of the P Select lt arcLayer gt below is 2 a extend 3 5 The FullWidth of the arc instance is the width of the widest ArcLayer It is 2 a extend 7 5 in the above P Active arc The BaseWidth of the arc instance is the width of the first ArcLayer in the list It is 2 a extennd 1 5 in the above P Active arc Example lt arcLayer layer P Select style FILLED gt lt lambda gt 3 5 lt lambda gt lt arcLayer gt Example lt arcProto name P Active fun DIFFP gt lt wipable gt lt extended gt t rue lt extended gt lt fixedAngle gt true lt fixedAngle gt lt angleIncrement gt 90 lt angleIncrement gt lt antennaRatio gt 200 0 lt antennaRatio gt lt diskOffset untilVersion 1 width 7 5 gt lt diskOffset untilVersion 2 width 1 5 gt lt arcLayer layer P Active style FILLED gt lt lambda gt 1 5 lt lambda gt lt arcLayer gt lt arcLayer layer N Well style FILLED gt lt lambda gt 7 5 lt lambda gt lt arcLayer gt lt arcLayer layer P Select style FILLED gt lt lambda gt 3 5 lt lambda gt lt arcLayer gt lt arcProto gt
383. of the duplication and overlap that occurs wherever arcs and nodes meet The default action is to write each node and arc individually This makes the file larger because of redundant box information however it is faster to generate and uses simpler constructs If you check this item all connecting regions on the same layer are merged into one complex polygon This requires more processing produces a smaller file and generates more complex constructs Output writes export Pins This controls whether pins are written to the GDS file for each export If checked and there is a valid pin layer then it is written Output all upper case This controls whether the GDS file uses all upper case The default is to mix upper and lower case but some systems insist on upper case GDS Output converts brackets in exports This controls whether the square brackets used in array specifications should be converted to underscores Some GDS readers cannot handle the square bracket characters Max chars in output cell name This limits the number of characters in a cell name Names longer than this are truncated and adjusted to ensure uniqueness Output default text layer This is the layer number to use when writing text When exports are being written and there is a text layer number associated with the appropriate Electric layer then that layer number is used instead of this default number This dialog element applies to the import of GDS S
384. om com sun electric database topology import NodeInst from com sun electric technology import Technology from java awt geom import Point2D tech Technology findTechnology mocmos trP tech findNodeProto P Transistor tP NodeInst makeInstance trP Point2D Double 10 10 trP getDefWidth trP getDefHeight newCell EvalJython displayCell newCell 176 Using the Electric VLSI Design System version 8 11 from com sun electric database variable import EvalJython newCell Cell makeInstance Library getCurrent samplel lay This example searches the current cell printing all transistors and all exports that start with the letter a This example creates a new cell places a transistor in it and displays the cell Chapter 6 Advanced Editing from com sun electric database geometry import Orientation This example goes a from com sun electric database hierarchy import Cell bit further it creates from com sun electric database hierarchy import Library from com sun electric database hierarchy import Export from com sun electric database prototype import PortCharacteristic a rotated transistor and a contact wires from com sun electric database topology import ArcInst them together and from com sun electric database topology import NodeInst exports the contact from com sun electric technology import Technology The transistor is from java awt geom import Point2D named T1
385. ommands in menu Window Waveform Window e Show Grid Displays a grid in the waveform panels The button toggles between showing and not showing the grid This function is also available with the Toggle Grid Points command in menu Window Waveform Window e The Panel popup This is a list of all panels including the hidden ones Selecting a panel from this list toggles its hidden state making a visible one disappear and making a hidden one reappear e Grow and Shrink These buttons which show a waveform being stretched or squeezed cause the minimum panel size to change These functions are also available with the Increase Minimum Panel Height and Decrease Minimum Panel Height commands in menu Window Waveform Window By shrinking the panel size more of them can fit in the window without having to use a slider to access them Also the panels can be resized individually by dragging any of the dividers e Plotting can be done with special commands in the Window Waveform Window submenu see Section 4 8 for more on printing Using the Electric VLSI Design System version 8 11 133 Chapter 4 Display 134 Using the Electric VLSI Design System version 8 11 Chapter 5 Arcs 5 1 Introduction to Arcs The arcs in a circuit are much more than simple connecting wires They can a take many different forms according to the needs of the design environment In schematics arcs can be negated directional zigzag an
386. ommon modification of arcs and nodes is to change their graphical descriptions A simple rule applies to all such changes the size of existing nodes and arcs is the amount that their highlighted area is larger than the default highlighted area Thus an arc or node that is at its default size will be saved with a zero size increase If you change the default size it will make all default sized nodes and arcs change as well If the node is larger than the default size it will grow accordingly BEFORE AFTER For example assume that an arc has a default default width is 2 default width is 4 width of 2 and there are two of these arcs ae one that is 2 wide an increase of 0 beyond the Increment 0 I 2 default and one that is 3 wide an increase of 1 beyond the default Increment 1 ERA t 3 a 5 If you redefine the technology such that these arcs are now 4 wide by default then the old 2 wide arc becomes 4 wide and the old 3 wide arc becomes 5 wide Because of these changes it may be preferable to keep the old technology and give the new technology a different name Then the old libraries can be read into the old technology and the Make Alternate Layout View command in menu View can be used to translate into the new technology This command uses node and arc functionality to associate components scaling them appropriately relative to their default sizes The change is completed by deleting the old technology renaming the n
387. on Tools tab NCC Electric ideally likes layout schematic and icons of the same items to be named identically i e nand2 sch and nand2 lay have identical names Having the same name places cells in the same cell group Much of this naming happens automatically in Electric when new views of a current cell are made If the two cells to be compared are not in the same group additional work is needed to tell NCC what to compare See Section 9 7 1 for more on NCC Simulation Electric has two built in simulators and can interface to many more The built in simulators are ALS and IRSIM ALS is a logic level simulator and is not useful for transistor level design IRSIM is a gate level simulator and can handle the transistors in this example Unfortunately IRSIM is not packaged with the basic Electric system it is a free but separate plugin See Section 1 5 for details on adding the IRSIM simulator to Electric To simulate a circuit with IRSIM use the IRSIM Simulate Current Cell command in menu Tools Simulation Built in A waveform window appears to show the simulation status To get the waveform window and your schematic layout to appear side by side use the Tile Vertically command in menu Window Adjust Position The exported signals of your design will automatically appear in the waveform window To add an internal signal to the waveform display select it and use the Add to Waveform in New Panel i
388. on which can be set only in the Properties dialog see Section 6 8 3 154 Using the Electric VLSI Design System version 8 11 Chapter 6 Advanced Editing 6 8 2 Selecting Text The only category of text that is not selectable is the text that is integral to a node s graphics i e the Flip Flop For the rest you can select and manipulate the text just as you would the object on which the text resides Note that port names on cell instances are not selectable instead select their export name inside of the cell definition Note that the name of an unexpanded cell instance is not easily selectable This is a feature that prevents accidental selection of unimportant text For these hard to select pieces of text the only way to select them is to use special select mode see section 2 1 5 All text is attached to its node arc or cell at an anchor point This is the one point on the text that never moves regardless of the size of the text The highlighting of selected text varies according to the anchor point Typically the highlighting consists of an X through the text This indicates that the anchor point is in the center If a U is drawn in any of four orientations it indicates that the anchor point is on the side and that the text grows out of the opened end If an L is drawn in any of four orientations it indicates that the anchor point is in a corner upper righ pper left Besides these 9 anchor points ther
389. one bold spaced unit press Control and then press the appropriate arrow key If you first hit h and then the control arrow key will move an item one half the distance of a bold spaced unit 3 5 in this case Electric has an interactive design rule checker DRC If you place elements too closely together it will report errors in the Messages window Try dragging one of the transistors until its gate is only 2 units from the other Observe the DRC error Then drag the transistors back to proper spacing When you are in doubt about spacing you can recheck the cell with the Check Hierarchically command in menu Tools DRC or just type the F5 key Next we will create the contacts from the N diffusion to Metal 1 Diffusion is also referred to as active Drop a Metal 1 N Active Contact node in the layout window and double click to change its Y size to 12 You will need a second contact for the other end of the series stack of nMOS transistors so duplicate the contact you have drawn type Ctrl M Move the contacts near each end of the transistor stack and draw diffusion lines to connect to the transistors NA A quick way to connect many items that are touching is to use the auto router To do this select all of the objects to be routed click and drag a selection box over them and use the Auto Stitch Highlighted Now command in menu Tools Routing or just type the F2 key See Section 9 6 2 for more on auto stit
390. ool stored as variables see Section 10 4 1 Example Ologeffort GlobalFanout D12 0 Declares a project setting on the Logical Effort tool object The GlobalFanout is set to the floating point value 12 10 2 2 External References After the header line all external libraries cells and exports must be declared This allows the file reader to quickly find all libraries that will be needed for the design and to reconstruct any missing cells and exports The cells are listed under their libraries The exports are listed under their cells If there are multiple external library lines they are sorted by library name where there are multiple external cells in a library they are sorted by their name and where there are multiple external exports in a cell they are sorted by their name The syntax of an external library reference is L lt name gt lt path gt The name of the library is used in JELIB file to references to this library The actual name of this library is obtained from the path The syntax of an external cell reference is R lt name gt lt lowX gt lt highX gt lt lowY gt lt highY gt lt name gt the name of the external cell lt lowX gt reserved for the low X bounds of the cell contents lt highX gt reserved for the high X bounds of the cell contents lt lowY gt __ reserved for the low Y bounds of the cell contents lt highY gt reserved for the high Y bounds of the cell con
391. op of the waveform window If you click on the time lock button at the top of the waveform window looks like a lock with the time on it Eh or use the Toggle Horizontal Panel Lock command then time is unlocked and each panel has its own time scale Now individual panels can show a different range of time than the rest A set of VCR buttons is available to animate the main time cursor The play rate can be controlled by the up arrow and down arrow buttons to the right of the VCR controls These buttons make the playback run faster or slower As the time cursor sweeps across the waveform window the original circuit can be seen to change levels These VCR controls are also available by using the Rewind Main X Axis Cursor to Start Play Main X Axis Cursor Backwards Stop Moving Main X Axis Cursor Play Main X Axis Cursor Move Main X Axis Cursor to End Move Main X Axis Cursor Faster and Move Main X Axis Cursor Slower commands These window functions apply to the analog simulation windows e Window Fill Window make all data fit in window If you wish to fill only in X use the Fill Only in X command in the Window Waveform Window menu To fill only in Y use Fill Only in Y e Window Zoom Out show twice as much time e Window Zoom In show half as much time e Window Special Zoom Focus on Highlighted show from main to extension cursors e Window Pan Left show earlier time e Window Pan Right show later time e Window S
392. opology gt lt box khx 1 0 gt lt lambdaBox k1lx 3 5 khx 3 5 kly 0 0 khy 0 0 gt lt box gt lt portArc gt Polysilicon 1 lt portArc gt lt primitivePort gt Using the Electric VLSI Design System version 8 11 249 Chapter 8 Creating New Technologies lt primitiveNodeGroup gt Design Rules Design rules appear in a lt Foundry gt section usually at the end of the XML file This section starts with lt Foundry name foundryname gt where foundryname is the name of the integrated circuit manufacturer whose rules are enclosed The section ends with lt Foundry gt Each rule in the section has some common attributes e ruleName gives the name of the rule used when printing error messages e when tells when the rule applies Most rules apply all the time in which case the attribute has the value ALL If a rule only applies in certain states of the technology then the when field will limit its use For example the mocmos technology has Deep rules which are triggered by when DE e type tells what kind of rule is being described The choices vary with the different rule formats e value tells the value of the rule which varies with the type of the rule If two numbers are given they are X and Y values for asymetric rules e maxW and minLen control the use of spacing rules in the presence of long and wide wires If maxW is given then at least one of the pieces of geomet
393. or Auto rotate plot to fit Using the Electric VLSI Design System version 8 11 Plot Date In Corner requests that additional information appear in the corner of the plot EPS Scale sets the scale factor of the specified cell when it is written as encapsulated PostScript 115 Chapter 4 Display e Synchronize to file requests that PostScript files be synchronized with the current cell Clicking the Set button prompts you for a file name which is stored with the current cell Whenever you write any PostScript Electric checks all synchronized cells to see if they are newer than their associated disk file If they are newer the files are regenerated Thus you can specify PostScript files for many different cells in a library and when PostScript is generated all of the files will be properly updated to reflect the state of the design 116 Using the Electric VLSI Design System version 8 11 Chapter 4 Display 4 9 Text Windows VHDL design of Automobile Cruise Control Some cells are textual in nature VHDL Verilog Netlists or Documentation and cause text to appear in the edit window When editing a textual cell a standard point and click editor appears You can use the Cut Copy and Paste commands in menu Edit You can specify the __rop LEVEL ENTITY acc font and size to use in textual editing windows yse puses all with Text Preferences in menu File entity ACC is port DR_SPEED CONTROL in BIT Prefer
394. orks best for networks in the top level cells compared by the most recent NCC run This command also works for nodes in the top level cells compared by the most recent NCC run as long as those nodes are primitive transistors or were treated as primitives because NCC compared them hierarchically Because NCC combines MOS transistors that are in series into a single NWMOS_ STACK NCC can t find equivalents for certain networks and nodes For example when NCC merges two series MOS transistors into a single NMOS_2STACK it removes the network between them from NCC s database Therefore if you click on that network and ask to highlight the equivalent NCC won t be able to find an equivalent Because NCC combines MOS transistors that are in parallel it can t find equivalents for certain networks and nodes For example when NCC detects two parallel MOS transistors it removes one from NCC s database but adds it s width to the other Therefore if you click on the transistor that was discarded and ask to highlight the equivalent NCC won t be able to find an equivalent Using the Electric VLSI Design System version 8 11 303 Chapter 9 Tools e Add NCC Annotation to Cell This is a submenu that allows user to select which NCC annotation to add to a cell Note that the designer should replace text surrounded by angle brackets amp lt amp gt See Section 9 7 4 on NCC Annotations for a description of each NCC annotation 9 7 3 Preference
395. ormat is used as an interchange between design systems and fabrication facilities Control of CIF I O is done with the CIF Preferences in menu File Preferences I O section CIF tab CIF PROJECT Preferences Categories CIF USER Preferences E General Technology mocmos x Display 6 6 Yo o wi H0 GDS H EDIF w arr Metal 1 CMF CMF Output Mimics Display P Output Merges Boxes IV Input Squares Wires A Export Import time consuming M Output Instantiates Top Level Reset Reset All Only resets USER Preferences Output scale fi ep eat x Cancel 190 Using the Electric VLSI Design System version 8 11 Chapter 7 Technologies Project Preferences The CIF Project Preferences let you can assign CIF names to each layer in the technology It also offers these controls Output Mimics Display lets you use CIF output for printing By default CIF output writes the entire hierarchy below the current cell If you check this box cell instances that are unexpanded will be represented as an outline in the CIF file This is useful when the CIF output is intended for hardcopy display and only the screen content is desired Output Merges Boxes controls the aggregation of geometry when writing CIF This is an issue because of the duplication and overlap that occurs wherever arcs and nodes meet The default action is to write each node and arc individually This makes the file larger because of redund
396. orts on the selected nodes use the Show Ports on Node command in menu Export This command highlights the ports on the screen using the global text scale to affect size see Section 6 8 4 To create an export select a port on a node and use the Create Export command in menu Export The resulting dialog requests an export name and some characteristics O Create New Export xi All export names on a cell must be unique if a nonunique name is given it is modified to be Export name fat unique This modification involves adding _1 Export characteristics unknown x _2 etc to the end of scalar export names or changing the index from 1 to 2 etc for Always drawn Reference export arrayed export names Like cell names export Body only names may not contain spaces tabs or unprintable characters Cancel Behavioral characteristics can be associated with an export by selecting the appropriate field in the export creation dialog These behavior characteristics are stored with the export and used primarily by simulators The characteristics include the following n e Directional input output and bidirectional e Supply power and ground e Clocking clock a generic clock export and clock phase 1 through clock phase 6 e Reference reference input reference output and reference base In addition reference exports carry an associated export name that is used by the CIF net
397. ove Objects Most Left Right Up Down for a squared block of units Also note that the amount moved is always grid aligned useful when squaring the block amount causes off grid distances The distance that the arrow keys move is also affected by the grid alignment setting see Section Si Obey 4 7 2 The current alignment movement is shown and there are buttons to increase or decrease the size Clicking on the size amount brings up a menu that lets you change to any of the 5 movement alignment sizes or bring up the Preferences dialog for further control Note also that the f key increases the size by one step and the h key decreases the size by one step To move objects along only one line just horizontally or vertically but not both hold the Control key down during motion Note that holding the Control key down before clicking will change the nature of the mouse action so you must click first and then press Control When editing schematics this will constrain objects to movement along 45 degree angles When arcs are moved by a large amount they cause the connecting nodes to move with them However for small arc motion the arc may shift within its ports This can only happen if the port has nonzero area and if the arc has the slidable constraint shown with the letter S when highlighted These constraints are discussed in greater detail in Section 5 2 2 Using the Electric VLSI Design System version 8 11 53 Chapter 2 B
398. ox gt lt lambdaBox k1x 2 0 khx 2 0 kly 2 0 khy 2 0 gt lt box gt lt nodeLayer gt e lt points gt is followed by lt techPoint gt elements which describe vertices of a polygon lt techPoint gt elements have attributes xm xa ym and ya which define a point x techPoint xa 2 n extendX techPoint xm y techPoint ya 2 n extendY techPoint ym Notice that meaning of techPoint xm and techPoint ym is inconsistent with meanding of box klx box khx box kly box khy e lt multicutbox gt a rectangular region where centers of contact cuts are placed in a uniformly spaced array This is similar to lt box gt but it has additional attributes e sizex and sizey describe the size of a contact cut sepld describes the separation between contact cuts in a one dimensional array sep2d describes the separation between contact cuts in a two dimensional array The centers of contact cuts are constrained to be in the box defined by the lt lambdaBox gt subelement and multicutbox s attributes klx khx kly and khy The NodeLayer of a Vial layer on a standard size node will generate a single contact cut of size 2x2 with the center in origin When the n extendX amp ge 2 5 2 0 3 0 2 or n extendY amp ge 2 5 then the NodeLayer will generate more contact cuts Example lt nodeLayer layer Vial style FILLED gt lt multicutbox sizex 2 0 sizey 2 0 sepld 3 0 sep2d 3 0 gt lt lambdaBox klx
399. pands and can be used in conjunction with Area selection to show only a specific part of the circuit see Section 2 1 3 for more on area selection 64 Using the Electric VLSI Design System version 8 11 Chapter 3 Hierarchy 3 5 Moving Up and Down the Hierarchy Each editing window in Electric displays a single cell Editing changes can be made only to that cell and not to any subcells that appear as instances Thus you may be able to see the contents of a cell instance but you cannot edit it To edit a cell instance use one of these commands in the Cell Down Hierarchy menu e Down Hierarchy descends into the definition of the currently selected cell instance You will now be able to edit that cell e Down Hierarchy Keep Focus descends while keeping the same window zoom and pan e Down Hierarchy New Window creates a new window in which to show the lower level cell Down Hierarchy Keep Focus New Window creates a new window in which to show the lower level cell while maintaining the zoom and pan factor The opposite of going down the hierarchy is the Up Hierarchy command in menu Cell Up Hierarchy which pops you to the next higher cell in the hierarchy If there was an associated Down Hierarchy command then this returns you to the place where you started up the hierarchy If the Down Hierarchy commands were not used Electric attempts to figure out the next higher cell in the hierarchy switching icons for schematics whe
400. parated by 4 units so design rules are satisfied Recall that well contacts are required to keep the diodes between the cells and source drain diffusion reverse biased We will place an N well contact and a P well contact in each cell It is often easiest to drop the Metal 1 N Well Con near the desired destination near VDD then right click on the power line to create the via Then drag the contact until it overlaps the via to form a stack of N diffusion the diffusion to Metal 1 contact Metal 1 the Metal 1 Metal 2 Con and Metal 2 Repeat with the P well In our datapath design style we will be connecting gates with horizontal and Metal 2 lines Metal 2 cannot connect directly to the polysilicon gates Therefore we will add contacts from the polysilicon gate inputs to Metal 1 to facilitate connections later in our design Place a Metal 1 Polysilicon 1 Con node near the left polysilicon gate Connect it to the polysilicon gate and drag it near the gate You will find a 3 unit separation requirement from the Metal 1 in the contact to the metal forming the output y Add a short strip of Metal 1 near the contact to give yourself a landing pad for a via later in the design You may find Electric wants to draw your strip from the contact in polysilicon rather than Metal 1 To tell Electric explicitly which layer you want click over the Metal 1 arc in the Component tab arcs have red borders Th
401. pe lt type gt This annotation created with the Transistor Type command changes the nature of transistors in the cell This is rarely used anymore but was once important when there were fewer known transistor types The type field may be one of the following N Transistor VWTH N Transistor VTL N Transistor OD18 N Transistor OD25 N Transistor 0D33 N Transistor NT N Transistor NT OD18 N Transistor NT OD25 N Transistor NT OD33 N Transistor P Transistor Using the Electric VLSI Design System version 8 11 309 Chapter 9 Tools VTH P Transistor VTL P Transistor OD18 P Transistor OD25 P Transistor or OD33 P Transistor resistorType lt type gt This annotation created with the Resistor Type command changes the nature of all polysilicon resistors in the cell The type field may be one of the following N Poly RPO Resistor N Poly RPO Resistor P Poly RPO Resistor or P Poly RPO Resistor Unlike all other resistors polysilicon resistors are not treated as short circuits by NCC Instead NCC tries to match these schematic polysilicon resistors with layout polysilicon resistors Warning This annotation is used very infrequently Typically it is used only inside special libraries such as the red library see Section 9 9 Most designers simply instantiate resistors from those special libraries forcePartMatch lt partName gt This annotation created with the Force Part Match command forces n
402. pecial Pan Center Cursor shifts the time so that the location of the cursor is in the center this command is only sensibly executed by using its quick key binding e Pan tool in tool bar freehand drag of time e Zoom tool in tool bar drag area to zoom in hold shift to zoom out e Measure tool in tool bar for measuring time Eye Plots The horizontal axis does not have to represent time Any signal can be used in the horizontal axis simply by dragging that signal onto the horizontal ruler To restore the horizontal axis to show time right click on it and choose Make the X axis show Time 132 Using the Electric VLSI Design System version 8 11 Chapter 4 Display Other Controls At the top of the waveform window above the signal names are many useful controls Those relating to time have already been discussed Here are the remaining buttons e Refresh Rereads the simulation output file and updates the display If the simulation has been re run and the output file is different then this button shows the new data This function is also available with the Refresh Simulation Data command in menu Window Waveform Window e Show Vertices TL IL 2 Controls the display of dots on the vertices of the waveforms The button toggles between three states 1 showing lines only 2 showing lines and dots and 3 showing dots only These functions are also available with the Show Points and Lines Show Lines and Show Points c
403. pl ne name intv2 segment port outbot2 port outtop2 name inthl name inth2 segment port inleft2 coord 30 20 segment port inleftl coord 30 40 X FEE chee ne ne Block Definition and Architecture Sections The Block Definition and Architecture sections define higher level blocks composed of primitives They looks like this blockdef attributes name CHIPNAME size X Y wirecolor COLOR repeatercolor COLOR 212 Using the Electric VLSI Design System version 8 11 Chapter 7 Technologies ports port name PORTNAME position X Y direction input output bidir components instance attributes ATTPAIRS type BLOCKTYPE name BLOCKNAME position X Y rotation ROT repeater name BLOCKNAME e porta X Y portb X Y direction vertical horizontal nets net name INTNAME segment FROMPART TOPART The only difference between the Architecture section and the Block Definition section is that the Architecture section has the keyword architecture instead of blockdef There can be only one architecture section but there can be many blockde fs defining a complete hierarchy The attributes section defines general information about the block The ports section defines external connections The components section defines logic in the block currently instances of other blocks or repeaters The rotation of an in
404. pl in rf 100p Flop2 in rf 100p lop3 clk rf xtop flop3 in rf 100p mart enough to recognize this f 100p 100p F 100p 100p f 100p 100p Using the Electric VLSI Design System version 8 11 100p 100p Spice Preferences Chapter 9 Tools Some nongraphical information can also be given to the Spice simulator with the Spice Preferences in menu File Preferences Tools section Spice tab Preferences amp Export Reset Display yo Tools Antenna Rules Compaction Coverage DRC Fast Henry Logical Effort NCC Network Parasitic Placement Routing Silicon Compiler Simulators Spice Model Files Verilog Verilog Model Files Well Check Technology gt Import Reset All Only resets USER Preferences Help Cancel Apply Writing Spice Deck Spice engine HSpice Write YDD GND in top cell v Spice level 1 r P Use cell parameters Resistor shorting none ti Parasitics Trans areajperim only Globals Use GLOBAL block Spice primitive set spiceparts I Write trans sizes in units I Write subckt for top cell IV Write end statement Use Header cards from files with extension Use Header cards from file Browse No Header cards Use Trailer cards From files with extension Tal C Use Trailer cards From File No Trailer cards Running Spice
405. ple must also contain a highlight layer to indicate the correct highlighting on the display Select the HIGH entry from the component menu to create this special type of layer Change Port x Metal 1 Each example must also contain port information Select the PORT entry in the component menu to create this special type of layer You will have to provide a name for each port and the name must be the same on each Metal 2 example Disallowed N Active Disallowed v P Active Disallowed v connected arcs Double click on the port to set this Polysilicon 1 allowed M Ports on the main example must also have connectivity information which arcs can connect to them and range information the permissible angle of i Angle The range consists of two numbers an angle in degrees counterclockwise ss from 3 O clock and an angle range For example a port angle of 90 witha Angle range port angle range of 45 describes a port that points upward and can connect at angles up to 45 degrees off from this direction The range will be graphically depicted wl i 4 Transistor meaning Gate Cancel Using the Electric VLSI Design System version 8 11 227 Chapter 8 Creating New Technologies The ports on the main example must also indicate any internal electrical connectivity by actually connecting them together For example the two polysilicon ports on a MOS transistor should be connected in the m
406. ply o Cancel Changes are only made in the fields where you type a value To remove an item from the list of selected objects use the Remove button To remove all but the selected item use Remove Others If only two objects are selected this dialog shows the distance between their centers Using the Electric VLSI Design System version 8 11 55 Chapter 2 Basic Editing 2 5 Changing Size 2 5 1 Node Sizing To change the size of a node select it and use the Interactively command in menu Edit Size Clicking and dragging on any handle will resize the node appropriately When you release the button the node changes size While stretching the node hold the Control key to constrain the size to just one axis and hold the Shift key to constrain the X and Y sizes so that they scale uniformly If you hold the Control and Shift keys then the node will resize about its center The command will show 8 handles around the node four in the corners and four on the sides a It is recommended that you hold the mouse button down while dragging so you can see the final size of the node Release the mouse button to actually resize the node To abort this operation type Escape SetNodeSize EG X Size To change the size of more than one node at a time select the nodes and use the All Selected Nodes command in menu Edit Size The dialog allows you to set the X Y Size and Y sizes of the selected nodes If you leave on
407. port name in the Ports Exports Preferences in menu File Preferences Display section Ports Exports tab then moving an export name will cause the node and the export to move as well It is sometimes desirable to keep an export but to transfer it to another node If a cell is in use higher in the hierarchy unexporting and then reexporting deletes all existing connections Instead the Move Export command in menu Export can be used Before using this command two nodes and their ports must be highlighted with left button and shift left button The export is moved from the first node to the second node QD Manipulate Exports x You can control all existing exports in Exports in cell tool PadFrame lay the current cell with the Manipulate a a Exports command This dialog shows C Metal 1 Metal 2 ground False the exports and lets you sort them by E Metal 1 Metal 2 input false name layer characteristic or body C jin2 Metal 1 Metal 2 input false only see Section 3 6 1 You can M outi Metal 1 Metal 2 output false change export names and T lout2 Metal 1 Metal 2 output false ie rH pulse Metal 1 Metal2 fica characteristics You can also delete M Wd Metal 1 Metal2 Sower Fale show or renumber selected exports Renumbering of exports presumes that the exports have numbers in their names and renames them so that there are no gaps in the sequence and the first has Toggle Selection Delete Selected Exports
408. propriate component menu entry and then clicking again in the editing window to place that node After clicking on the component menu entry the cursor changes to a pointing hand to indicate that you must select a location for the node When placing the node if you press the button and do not release it you will see an outline of the new node which you can drag to its proper location before releasing the button Using the Electric VLSI Design System version 8 11 17 Chapter 1 Introduction Highlight Port In this example the top node is called Metal 1 Polysilicon 1 Con a contact between metal layer 1 and polysilicon layer 1 found in the fifth entry from the bottom in the right column of the component menu The node on the bottom is called N Transistor lower right entry of the component menu Both of these nodes are from the MOSIS CMOS technology which is listed as mocmos in the status area Highlight Box 1 10 3 IC Layout Tutorial Highlighting Fiii Box A highlighted node has two selected areas the node and a port on that node Note that the transistor is highlighted in the previous example and the contact is highlighted in the example here The larger selected area covers the node and it surrounds the important part for example on the Transistor it covers only the overlap area excluding the tabs of active and gate on the four sides The smaller selected area is the currently highlighted port there a
409. provides shortcuts for many common commands ABr ma KUAN FH 10 wem A eee ela ew Library Editing Modes and Object ig Expansion ontro or Area Control Arrow A Distance Hierarchy Hard Select Preferences The tool bar has these sections e Library Control Icons to read a library Section 3 9 2 and to save libraries Section 3 9 3 e Editing Modes Icons for selection Section 2 1 1 panning Section 4 4 2 zooming Section 4 4 1 outline edit Section 6 10 2 and measuring Section 4 7 4 e Alignment and Arrow Distance The center shows the current alignment value and the distance that arrow keys will move Icons on the left and right make that distance larger or smaller Clicking on the distance value shows a popup with more choices Section 2 4 1 e Object or Area Icons switch between object selection and area definition Section 2 1 3 e Hard Select Icon to toggle the selection of hard to select objects Section 2 1 5 e Preferences Icon to show the preferences dialog Section 6 3 e Undo Icons to undo and redo Section 6 7 e Hierarchy Icons to go back and forward while traversing the hierarchy Section 3 5 e Expansion Icons to expand and unexpand cell instances Section 3 4 Using the Electric VLSI Design System version 8 11 91 Chapter 4 Display The toolbar can be rearranged with the Toolbar Preferences in menu File Preferences Display section Toolbar tab An ima
410. pter 10 The JELIB and DELIB File Format 10 2 Header 10 2 1 Header View and Tool Headers The first line in the JELIB file should be the H header line The syntax is H lt name gt lt version gt lt variable gt lt name gt _ the name of the library lt version gt lthe version of Electric that wrote the library lt variable gt fa list of variables on the library see Section 10 4 1 The name of the library is used in the JELIB file to identify references to this library The actual name of this library is obtained from the file path of this JELIB file Example Hlatches 8 01 Declares that library latches was written from Electric version 8 01 Views All views used in the library must be declared V lt full name gt lt name gt lt fullname gt ithe full name of the view lt name gt fthe abbreviation name of the view Example Vlayout lay Declares view with abbreviation name lay and full name layout Using the Electric VLSI Design System version 8 11 345 Chapter 10 The JELIB and DELIB File Format Tools There is no need to declare all tools in the header The only reason for a tool declaration to exist is if the tool has project setting variables stored on it If there are multiple tool lines they are sorted by the tool name The syntax is O lt name gt lt variable gt lt name gt the name of the tool lt variable gt fa list of preferences on the t
411. put a 2 0 y 2 0 basic ipin symbol NA NA e Variables A line starting with V controls how variables are converted to EDIF The line has this format V ElVarName EdVarName Scale Append ee gt eee o F 196 Using the Electric VLSI Design System version 8 11 Chapter 7 Technologies Where El1VarName is the Electric variable name e g ATTR_M EdVarName is the EDIF primitive name e g m Scale isa scale from Electric to EDIF e g 1 Append is an optional string to append to EDIF e g u For example V ATTR_length 10 9 u e FigureGroups A line starting with F controls how figure groups are converted to EDIF The line has this format F ElName EdName Where E1Name is the Electric technology name e g ARTWORK EdName is the EDIF figure group name e g DEVICE For example F ARTWORK DEVICE e Globals A line starting with G controls how global names are converted to EDIF The line has this format G ElName EdName Where E1Name is the Electric global name e g GND EdName is the EDIF global name e g gnd For example G GND gnd 7 3 5 DEF Control DEF USER Preferences E E General Display DEF Design Exchange Format is a recent interchange format for CAD systems It i
412. r 7 Technologies 7 5 2 Multipage Schematics and Frames Multipage schematics are implemented in Electric by having each page map to a different area of a vast schematic cell To create one of these multipage cells use the Make Cell Multi Page command in menu Cell Multi Page Cells You will then be editing page 1 of the multi page schematic You can add pages to the current multipage schematic with the Create New Page command in menu Cell Multi Page Cells You can delete the current page with Delete This Page To advance to the next page use Edit Next Page Older versions of Electric implemented multipage schematics with different view types p1 p2 If these views appear instead of proper pages use the Convert old style Multi Page Schematics command As a graphical aid to schematic design frames can be displayed in a cell by using the Cell Properties command in menu Cell Multi page schematics require a cell frame on every page but their presence is optional in other cells Every cell I7 Disallow modification of anything in this cell Set Clear The frame size can be Disallow modification of instances in this cell Set Clear Half A Standard cell i II lib Set cl MePa Oa andard cell in a cell librar e ear R HEN d D and E Part of technology editor library Set Clear The frame can be horizontal IV Expand new instances of this cell Set Clear landsc ape or Technology atwo o verti
413. r active but does not write any Resistor Capacitor information Conservative RC writes Resistor Capacitor information in addition to the area perimeter e Globals Has three options for the treatment of global signals such as power and ground No special treatment causes globals to be treated like other signals Use GLOBAL block places global signals in a GLOBAL block not supported by all versions of Spice Create SUBCKT ports causes globals to be added to SUBCKT headers as explicit ports Note that this preference should be used when Global Partitions are in use see Section 6 9 5 e Spice primitive set Switches between Spice primitive sets Currently there are only two spiceparts and spicepartsG3 e Write VDD GND in top cell Whether to write power and ground signals in the top level cell e Use cell parameters When set any parameters defined on the cell will appear in the Spice deck When not checked each parameterized cell appears multiple times in the deck once for each different parameter combination See Section 6 8 5 for more on parameters e Write trans sizes in units Requests that the Spice deck contain scalable size information instead of absolute size information e Write subckt for top cell Requests that a the top level cell be written as a subcircuit and a call made to it The default is to write the top level cell without a subcircuit wrapper e Write end statement Requests that an end statem
414. rarchy cell low has 3 nodes two arcs and an export as shown here The top level of hierarchy cell high has two instances of the cell the right instance is rotated 90 degrees and an arc connecting them as shown here Here is the JELIB file for the above layout fan Example 8 09 Views Vlayout lay Technologies mocmos header information Cell high 1 lay Chigh 1 lay mocmos 1093555876000 1094258888640 Ngeneric Facet Center art 0 0 0 14V Tlow 1l lay low 0 14 12 D5G4 Tlow 1 lay low 1 15 12 R D5G4 AMetal 1 net 0 SO low 1 a 5 22 low 0 a 4 22 x Cell low 1 lay Clow 1 lay mocmos 1093555232000 1094258870406 Ngeneric Facet Center art 0 0 0l AV NMetal 1 Metal 2 Con contact 0 10 10 NMetal 1 Pin pin 0O 10 10 NMetal 2 Pin pin 1 10 10 AMetal 1 net 0 S1800 contact 0 10 10 pin O 10 10 AMetal 2 net 1 S900 contact 0 10 10 pin 1 10 10 Ea D5G2 pin 0 U X 356 Using the Electric VLSI Design System version 8 11
415. rchy v Evaluate Numbers when Sorting Names Search Get Info iH Open Open all below here Close all below here The context menu for each library icon has 5 parts The top three entries Make This the Current Library let you control the expansion of the tree The next entry lets you make Create New Cell Rename Library Save Library Close Library Reload Library Add to Project Management Repository _ the library the current library The next entry lets you manage the library with Project Management see Section 6 12 The next entry lets you create a new cell in the library The bottom four entries let you rename save delete or reload the library Using the Electric VLSI Design System version 8 11 103 Chapter 4 Display Edit Edit in New Window Place Instance of Cell The context menu for each cell icon has 5 parts The top two entries let you edit Create New Cell the cell in the current or in a new window The next two entries let you place an instance of the cell and create a new cell The next four entries let you create a eee new cell version create a new cell copy delete the cell and copy the cell to a Duplicate Cell different library The next two entries let you rename the cell or change its view Delete Cell The bottom entry lets you rearrange cell groups Copy Cell gt Rename Cell Change View gt Change Cell Group Open Open all below here The context menu for each cell group has 3 pa
416. rding to their high low X Z value in the simulation at that time If you connect Simulation Probe nodes to any part of the circuit those nodes light up with the appropriate color instead which allows better visualization of activity patterns see Section 7 6 3 You can control the colors used in crossprobing by using the Layers Preferences in menu File Preferences Display section Layers tab and setting the colors for WAVEFORM CROSSPROBE LOW WAVEFORM CROSSPROBE HIGH WAVEFORM CROSSPROBE UNDEFINED and WAVEFORM CROSSPROBE FLOATING see Section 4 6 2 For best visualization of the simulation activity there is a set of VCR buttons to control an animation of the main time cursor The play rate can be controlled by the up arrow and down arrow buttons to the right of the VCR controls These make the playback run faster or slower As the time cursor sweeps across the waveform window the original circuit can be seen to change levels These window functions apply to the digital simulation windows e Window Fill Window make all data fit in window If you wish to fill only in X use the Fill Only in X command in the Window Waveform Window menu To fill only in Y use Fill Only in Y e Window Zoom Out show twice as much time e Window Zoom In show half as much time e Window Special Zoom Focus on Highlighted show from main to extension cursors e Window Pan Left show earlier time e Window Pan Right show l
417. re appropriate If there are multiple possibilities because the current cell is used in many locations then you will be prompted for a specific location An alternate version of this command is Up Hierarchy Keep Focus which moves up the hierarchy but keeps the current cell s zoom and pan factors the same so that the circuitry does not move on the screen Besides traversing the hierarchy you can also traverse the sequence of cells that has been edited To edit the cell that was previously displayed use the Go Back a Cell command in the Cell Cell Viewing History menu and to go forward in the list use the Go Forward a Cell These commands are also accessible from the tool bar back and forward buttons If you 4 i right click on these buttons you are given a list of cells and can jump directly to one of them When going down or up the hierarchy if an export or port is selected then the equivalent port or export is shown after the level of hierarchy has changed Layout Considerations If a layout cell is selected you can use the Down Hierarchy In Place command to edit the cell while showing the upper level of the hierarchy A red border is drawn around the cell now being edited and the surrounding geometry at the upper level which is not editable is grayed out To change the border color use the Layers Preferences in menu File Preferences Display section Layers tab and set the colors for the layer SPECIAL
418. re declared with the A line All arcs are sorted by the arc name The syntax is A lt type gt lt name gt lt nameTD gt lt width gt lt flags gt lt headNode gt lt headPortID gt lt headX gt lt headY gt lt tailNode gt lt tailPortID gt lt tailX gt lt tailY gt lt variable gt the type of the arc instance It has the form lt technology gt lt arc gt If technology is omitted the technology of the cell is assumed the name of the arc instance a text descriptor for the name when displayed the difference between width of the arc instance and standard width of this arc s prototype flags for the arc instance see below the name of the node at the head of the arc instance the ID of the port on the head node may be blank if there are no choices the X coordinate of the head of the arc instance 350 Using the Electric VLSI Design System version 8 11 Chapter 10 The JELIB and DELIB File Format lt headY gt fthe Y coordinate of the head of the arc instance tailNode gt _ the name of the node at the tail of the arc instance lt tailPortID gt the ID of the port on the tail node may be blank if there are no choices lt tailX gt the X coordinate of the tail of the arc instance lt tailY gt the Y coordinate of the tail of the arc instance lt variable gt fa list of variables on the arc instance see Section 10 4 1 The lt flags gt field consists of an
419. re four possible ports on the transistor but only one on the contact To highlight a node use the left button The node and the closest port to the cursor will be selected After highlighting you can hold the mouse button down and drag the highlighted object to a new location If nothing is under the cursor when the selection button is pushed you may drag the cursor while the button remains down to define an area in which all objects will be selected Highlight Port Another way to affect what is highlighted is to use the shift eft button This button causes object highlighting to be reversed highlighted objects become unhighlighted and unhighlighted objects are highlighted The shape of the highlighted port is important Ports are the sites of arc connections so the end point of the arc must fall inside this port area Ports may be rectangles lines single points displayed as a or any arbitrary shape For example when the active tabs of a transistor are highlighted the port is shown as a line 18 Using the Electric VLSI Design System version 8 11 Chapter 1 Introduction 1 10 4 IC Layout Tutorial Make an Arc ighlighted box on Pin node L wire Arc To wire a component select it move the cursor away from the component and use the right button A wire will be created that runs from the component to the location of the cursor Note that the wire is a fixed angle wire which means that it will be drawn along
420. rences Help Apply Electric can also write external format files with these commands in the File Export menu No backup of library files Backup of last library file if gu e CIF Caltech Intermediate Format is used to describe integrated circuit layout The output file contains only the current cell and any circuitry below that in the hierarchy Use the CIF Preferences in menu File Preferences I O section CIF tab to affect how CIF is written See Section 7 3 2 for more on CIF o GDS II Stream is also used to describe integrated circuit layout The output file contains only the current cell and any circuitry below that in the hierarchy Use the GDS Preferences in menu File Preferences I O section GDS tab to affect how GDS is written See Section 7 3 3 for more on GDS e EDIF Electronic Design Interchange Format can write either the Netlist or the Schematic view of the circuit Electric writes EDIF version 2 0 0 Use the EDIF Preferences in menu File Preferences I O section EDIF tab to affect how EDIF is written See Section 7 3 4 for more Using the Electric VLSI Design System version 8 11 81 Chapter 3 Hierarchy 82 on EDIF e LEF Library Exchange Format is an interchange format that describes the exports on cells in a library e Lis the GDT language still appearing in some commercial systems The output file contains only the current c
421. requested here by checking Check DRC Spacing Rules for Wells Since the well checker has not been designed for DRC purposes the algorithm is not efficient and therefore the option is off by default Finally the Well Checker is able to use multiple processors to speed up its task This can be disabled or the number of processors can be reduced with the Use multiple processors checkbox and field 9 3 2 Antenna Rule Checking Antenna rules are required by some IC manufacturers to ensure that the transistors of the chip are not destroyed during fabrication In such processes the wafer is bombarded with ions in order to create the polysilicon and metal layers These ions must find a path through the wafer to the substrate and active layers at the bottom If there is a large area of poly or metal and if it connects ONLY to gates of transistors not to source or drain or any other active material then these ions will travel through the transistors If the ratio of the poly or metal layers to the area of the transistors is too large the transistors will be destroyed To check for antenna rule violations use the Antenna Check command in menu Tools ERC After analysis is done you can review the errors by typing gt to see the next error and lt to see the previous error You can also see the list of errors in the cell explorer see Section 4 5 2 You can control the amenna Necker With the A Tools Antenna Rules USER Preferences
422. ribe integrated circuit layout It contains no connectivity so after the library is read it does not know about transistors and contacts just layers You can use the node extractor to convert CIF to real Electric components see Section 9 10 2 To affect how CIF is read use the CIF Preferences in menu File Preferences I O section CIF tab See Section 7 3 2 for more on CIF e GDS II Stream is also used to describe integrated circuit layout It contains no connectivity so after the library is read it does not know about transistors and contacts just layers You can use the node extractor to convert GDS to real Electric components see Section 9 10 2 To affect how GDS is read use the GDS Preferences in menu File Preferences I O section GDS tab See Section 7 3 3 for more on GDS e EDIF Electronic Design Interchange Format is used to describe both schematics and layout Electric reads EDIF version 2 0 0 Use the EDIF Preferences in menu File Preferences I O section EDIF tab to affect how EDIF is read see Section 7 3 4 e LEF Library Exchange Format is an interchange format that describes the cells in a library The cells that are read in contain ports but very little contents e DEF Design Exchange Format is an interchange format that describes the contents of a library DEF input often makes use of associated LEF files which must already have been read Use the DEF Preferences in menu File
423. rnal connections The components section defines logic in the block currently only PIPs The nets section defines internal networks There can be multiple segment entries in a net each defining a straight wire that runs from the FROMPART to the TOPART These parts can be either port PORTNAME or coord X Y depending on whether the net ends at a port or at an arbitrary position inside of the primitive For example this block has two vertical nets and two horizontal nets Four pips are placed at the intersections Six ports are defined two on the left two on the top and two on the bottom Here is the code primdef outtop outtop2 attributes name sampleblock 60 size 40 60 50 ports port name inleft1 position 0 40 inlefti 40 direction input port name inleft2 position 0 20 30 direction input port name outtopl position 10 60 inleft 20 direction output port name outtop2 position 30 60 10 direction output port name outbot1 position 10 0 direction output port name outbot2 position 30 0 direction output outboti outbot2 a a E Q 10 20 30 40 components pip name pipl position 10 20 connectivity intvl inth1 pip name pip2 position 30 20 connectivity intv2 inth1 pip name pip3 position 10 40 connectivity intvl inth2 pip name pip4 position 30 40 connectivity intv2 inth2 nets ne name intvl segment port outbotl port outto
424. rrent edit window In the LIBRARIES icon you will see the list of libraries currently MyCircutisch only one called noname If you open that library s icon you will see the cellsin _ joss the library currently only MyCircuit T ERRORS 1 11 2 Schematics Tutorial Make a Node Schematic nodes are placed by selecting them from the side bar s components gt menu on the left and then wiring them together This example shows two Highlight Port nodes that have been created This was done by clicking on the appropriate component menu entry and then clicking again in the editing window to place that node re Highlight Box e After clicking on the component menu entry the cursor changes to a pointing hand to indicate that you must select a location for the node When placing the node if you press the button and do not release it you will see an outline of the new node which you can drag to its proper location before releasing the button 26 Using the Electric VLSI Design System version 8 11 Chapter 1 Introduction In this example the top node is called a Buffer found on the right side of the component menu in the third entry from the top The node on the bottom is called an And top entry on the right 1 11 3 Schematics Tutorial Highlighting Highlight Port Paidi Box A highlighted node has two selected parts the node and a port on that node Note that the And is highlighted in the previous example an
425. rs that mimic Cadence systems In addition to changing the colors this command also changes key bindings shown below and other preferences that cannot easily be undone It is recommended that you save your current preferences before switching to Cadence mode to make it easier to revert A setea All 2 1 1 eai es hi D som Alt Align To Grid 4 7 2 B Size Interactively 2 5 1 C Copy 6 1 Duplicate 6 1 Shift Change 6 6 Down Hierarchy 3 5 Select Nothing 2 1 1 ee E foe Hierarchy 3 5 Down Hierarchy 3 5 zp ea aaa a Faso Cell All The Way lfi window 4 4 1 aay Expand Cell All The Way G Toggle Grid 4 7 1 Set Signal Low 4 1 1 1 es pH al Unit Movement 24 1 1 Object Properties 2 4 2 Pe l hift Place Instance 3 3 Show Network 6 9 1 Measure Mode 4 7 4 Pe Find Text 4 9 a aa ary eee Duplicate 6 1 Measure Mode 4 7 4 nee Cee N New Cell 3 2 Place Cell Instance 3 3 Overlay Signal in Waveform O Open Library 3 9 2 Window 4 11 2 Shift Peek 3 4 Create Export 3 6 1 Pan Mode 4 4 2 Alt Preferences 6 3 Quit 1 10 9 Object Properties 2 4 2 Redisplay Window 4 4 2 one pare noes Nn o Save All Libraries 3 9 3 Select Object C 1 D lt o lt o o Toggle Negation 5 4 2 Place Annotation Text 2 2 1 _ Up Hierarchy 3 5 Wmo 6n Pase6 D Set Signal Hight eee lt Close Window 4 3 st tee eed X Create Export 3 6 1 Mirror L
426. rties command in menu Tools Simulation Others FastHenry Arc Properties This command presents a dialog with FastHenry factors M Include this arc in FastHenry analysis for the selected arc The most important factor is at the Group name M2Group z top Include this arc in FastHenry analysis By checking this the arc is described in the FastHenry deck Once this New Group is checked other fields in the dialog become active You can set the thickness of this arc the default value shown Width 3 will be used if no override is specified You can set the Thickness defautt 2 number of subdivisions that will be used in height and width again defaults are shown You can even set the Width subdivisions default 1 height of the two ends of the arc Height subdivisions 0 default 1 Arcs can be partitioned into different groups Click the Head at X 49 5 Y 14 Z New Group button to define a group After that arcs Fees ose can be assigned to one or more groups Cancel OK After all arcs have been marked generate a FastHenry deck with the Write FastHenry Deck command in menu Tools Simulation Others Before doing that however you can set other options for FastHenry deck generation To do this use the FastHenry Preferences in menu File Preferences Tools section FastHenry tab default 24 65 282 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools
427. rts The top three entries let you control the expansion of the tree The middle entries let you create a new cell in the Create New Cell group or to delete all cells in the group The bottom two entries let you rename or Delete Entire Group duplicate every cell in the group Close all below here Rename Cells in Group Duplicate Cells in Group The context menu for a multi page schematic cell has two parts see Section 7 5 2 Edit for more on multi page schematics The top two entries let you edit the cell in the Edit in New Window current or in a new window The bottom entries let you add a new page to the current aes multi page schematic or delete the current page of the multi page schematic PeT Bags Context Menus for Errors and Jobs Open The ERRORS section has three parts The top three entries let you control the Open all below here expansion of the tree The middle section controls collections of errors Delete Close all below here All removes all error collections and Import Logger reads a saved set of errors Delete All and creates a new collection this function is also available with the XML Error fae ewe Logger command in the File Import menu The bottom section has the Get Info command to describe this collection of errors Get Info 104 Using the Electric VLSI Design System version 8 11 Chapter 4 Display ea Open Open all below here Close all below here Each collection of errors in t
428. rts command gives the same information but in text form and the Summarize Exports command gives a text list that is reduced where sensible To see a list of exports that are electrically connected to the current object at multiple levels of hierarchy use the List Exports on Network and List Exports below Network commands in menu Tools Network To see a list of cells and networks where the currently selected export is used higher up in the hierarchy use the Follow Export Up Hierarchy command Once a port has been exported its characteristics can be modified by selecting the export name and using the Object Properties command in menu Edit Properties You can change basic export information such as the name characteristic and reference name if applicable You can control export state such as whether it is always drawn and whether or not it appears on icons Export name Characteristics input sA Center 16 5 18 5 Reference name Body ony Always drawn fo Points min 1 max 63 Text Size 2 Units min 0 25 max 127 75 x offset fo Y offset fo maximum 4088 Rotation fo x Highlight Owner Anchor centered x Boxed width height All Text Sizes are Scaled by 100 Bold J Italic Underline 0 25 increments Invisible outside cell Export Properties xi ly Font DEFAULT FONT v Color DEFAULT COLOR v Attributes Apply Cancel You c
429. run the auto stitcher only once for the current cell use Auto Stitch Now To run it once and in the highlighted area only use the Auto Stitch Highlighted Now command Note that this auto stitches all cell instances that intersect the highlighted area so even if only a portion of a cell falls into the highlighted area the entire cell is stitched The auto stitcher allows you to specify a particular type of wire to use in routing By default the router figures out which wire to use However in the Routing Preferences a specified wire can be given or automatic selection can be resumed by selecting the DEFAULT ARC entry First check Use this arc in stitching routers and then select the arc 9 6 3 Mimic Stitching One problem with the auto stitcher is that it may take a different view of the circuit than originally intended In an area where more than two cells meet the auto stitcher may place many wires in an attempt to connect all touching ports Another problem with the auto stitcher is that it makes explicit only what is already implicit and so does not always add all necessary wires To control the wiring of arrays of cells more directly there is the mimic stitcher This tool lets the designer place a wire and then it adds other wires between all other similar situations in the circuit Thus it mimics your actions The router also mimics your wire removals removing arcs similar to the ones that you delete To turn
430. ry must be that wide If minLen is given then the length of the common parallel run must be at least that long value gt minLen Here are the possible rules e LayerRule is a rule for a single layer In addition to the standard attributes this rule has one or more layer names to which it applies The type of information can be MINWID minimum width of the layer MINAREA the minimum area of the layer or MINENCLOSEDAREA the minimum area of any hold in a polygon Example lt LayerRule ruleName 1 1 Mosis layerName P Well N Well when ALL type MINWID value 12 0 gt e LayersRule is a rule for the interaction of two different layers In addition to the standard attributes it has the names of the two layers The type of information can be CONSPA minimum spacing of two connected layers UCONSPA minimum spacing of two unconnected layers SPACING minimum spacing in both connected and unconnected situations UCONSPA2D minimum spacing of a two dimensional array of contact cuts FORBIDDEN disallowed combination of layers anywhere in the design EXTENSION minimum overlap of a layer extended from another or SURROUND minimum extension of a layer beyond another Example lt LayersRule ruleName 15 4 Mosis layerNames Metal 3 Metal 3 when ALL type SPACING value 6 maxW 100 minLen 0 gt e NodeRule gives rules for Electric nodes In addition to the standard attributes it has a node name The type of informa
431. s NCC options are available in the NCC Preferences in menu File Preferences Tools section NCC tab El Tools NCC USER Preferences Antenna Rules Compaction Coverage Hierarchical Comparison DRC Flat Comparison Fast Henry Logical Effort C List NCC annotations Size Checking Network Parasitic Check transistor sizes Placement Relative size tolerance 0 0 Routing Silicon Compiler Absolute size tolerance units bo Simulators Spice Body Checking Spice Model Files Verilog l verilog Model Files rChecking All Cells well Check Technology Check transistor body connections kd 5 Halt after finding the first mismatched cell Vv Don t recheck cells that have passed in this Electric run Export Import Reporting Progress Reset All How many status messages to print 0 gt few 2 gt many 0 ese Error Reporting ik Reset Only resets USER Preferences hook Maximum number of matched equivalence classes to print fio Maximum number of mismatched equivalence classes to print fio Cancel Maximum number of equivalence class members to print fio Help gu Operation Section This section allows you to select what kind of NCC operation to perform You can either compare hierarchically compare flat or list all the NCC annotations in the design It is recommended that you use h
432. s When Electric runs on the Windows operating systems each editing window lives inside of a larger frame on the display This is called an MDI Multiple Document Interface interaction On non Windows systems UNIX Linux Macintosh etc each editing window is a separate frame on the display This is called an SDI Single Document Interface interaction Note that Windows users can request an SDI interaction and non Windows users can request MDI interaction This is done with command line switches see Section 1 3 When running in SDI mode there are two extra commands in menu Windows for controlling the frames e Move to Other Display requests that the current window frame be moved to a different display Some systems Macintosh let you drag the frames between displays but others keep each display distinct requiring this command to make the move e Remember Location of Display requests that the current editing window s frame location be used as the initial location when Electric runs again This command can also be used to start the system on a different display 94 Using the Electric VLSI Design System version 8 11 Display Considerations Electric offers many settings for controlling the display available in the Display Control Preferences in menu Chapter 4 Display File Preferences Display section Display Control tab i General E Display Seeeeeeeveee Export Reset Help Cancel
433. s Resistor size mismatches are reported here because polysilicon resistors in both schematics and layout have lengths and widths Using the Electric VLSI Design System version 8 11 317 Chapter 9 Tools Wid Len MyLib NAND sch Error Wid Len MyLib NAND lay ee 5 0 3 0 PMOS pmos z2 in Cell MyLib NAND l 3 0 2 0 PMOS pmos 3 in Cell MyLib NAND sii 5 0 3 0 PMOS pmos in Cell MyLib NAND l 3 0 2 0 PMOS pmos 3 in Cell MyLib NAND 50 0 2 0 2 0 PMOS pmos 1 in Cell MyLib NAND l 3 0 2 0 PMOS pmos 2 in Cell MyLib NAND 50 0 2 0 2 0 NMOS_2stack nmos 1 in Cell MyLib NAND l 3 0 2 0 NMOS_2stack nmos 5 in Cell MyLib NAND The size mismatches table is sorted in the descending order of the relative error On the right side of the window mismatches are arranged into a table sorted in the descending order of the relative error see example above Each mismatch occupies one row and has four columns The first column contains the relative error of the mismatch The second and third columns have widths and lengths of the corresponding parts in two cells The mismatched value is printed in red The last column has hyperlinked part names If a transistor has both a length and a width mismatch then these mismatches are displayed in separate rows e g the first and the second rows above Export Assertions It is very common for a layout cell A to have multiple ground wires that are connected by it s parent cell For example cel
434. s automatically generating unique names To do this use these commands in menu Export e Re Export Everything reexports all ports on all nodes in the current cell e Re Export Selected reexports only ports on currently highlighted nodes Unwired Ports Only reexports only those ports that are not connected to an arc Wired and Unwired Ports reexports all ports Wired Ports Only reexports only those ports that are connected to an arc e Re Export Selected Port on All Nodes reexports the selected port on the every node in the cell that is the same as the current one e Re Export Power and Ground reexports only Power and Ground exports e Re Export Highlighted Area reexports only ports inside the currently highlighted area for precise area selection see Section 2 1 3 Unwired Ports Only reexports only those ports that are not connected to an arc Wired and Unwired Ports reexports all ports Wired Ports Only reexports only those ports that are connected to an arc e Re Export Deep Highlighted Area reexports only ports inside the currently highlighted area but goes all the way down the hierarchy reexporting from the lowest level This causes unconnected exports deep down the hierarchy to become available for connection Unwired Ports Only reexports only those ports that are not connected to an arc Wired and Unwired Ports reexports all ports Wired Ports Only reexports only those ports that are connected to an arc
435. s set the desired layer visibility click on an entry in the Visibility Configurations section and click the Save Visibility icon second from the left at the top of the Visibility Configurations section To rename an entry use the Rename icon rightmost icon Besides customizing the SHIFT number and Set Mnumber Visible commands you can create new visibility configurations by using the New icon leftmost icon To delete a configuration use the Delete icon second from the right Highlighting and Text Visibility The two buttons in the Highlighting section control the highlighting of layers By selecting a layer and clicking Toggle it makes that layer stand out on the display Use Clear to return to normal layer display The bottom of the tab lets you choose which of the different types of text will be visible These different types of text are described more fully in Section 6 8 1 106 Using the Electric VLSI Design System version 8 11 Chapter 4 Display 4 6 Color 4 6 1 Electric s Color Model The Layers Preferences in menu File Preferences Display section Layers tab controls the appearance of individual layers in the editing window Before explaining this panel it is useful to understand the distinction between transparent and opaque layers Every layer in a technology is either transparent or opaque Transparent layers are able to overlap each other and it is possible to see all of th
436. s Full Width Primitive nodes and arcs also have the notion of a BaseRectangle and a BaseWidth They relate to the shape of the most important layer in this node or arc The BaseRectangle of a primitive node is described explicitely The Base Width of primitive arc is the width of the first ArcLayer in the arc description The BaseRectangle and BaseWidth are highlighed in the Edit Window and they appear in Properties dialogs Instances of nodes and arcs in a library can have sizes larger than standard Electric writes size information of each instance in the library files Since release 8 05 of Electric or more precisely since the 8 050 development version library files contain the extent of the node arc over its standard size described in the technology file When you switch a design library from one technology to another compatable technology the standard size node arc in old technology is converted to the standard size node arc in the new technology The Using the Electric VLSI Design System version 8 11 237 Chapter 8 Creating New Technologies node arc which extends by 1 unit beyond the standard node arc in old technology is converted to a node arc which extends by 1 unit beyond the standard node arc in new technology Older Electric releases wrote sizes of node arc instances in another way Jelib format before Electric 8 05 actually the 8 05g developement version and all Elib files saved the size of the FullRectangle and FullWidth Je
437. s IV Export Names in the reverse direction In M Node Variables V Arc Variables IV Export Variables IV Cell variables addition you can jump Automatically Generated Node and Arc Names directly to a specified line T Limit Search to the Highlighted Area number Restrictions AI Code Values gt Al Units Values Interestingly the Find Text command can also be used outside of the text edit window If you are editing a layout or schematic this dialog will search all of the node arc export and other names The checkboxes in the Objects to Search area control which of these pieces of text will be considered Automatically Generated names are those created for you by the system They can be included in the search but normally are not The checkbox Limit Search to the Highlighted Area causes only objects that are selected or in the highlighted area to be considered in the text search See Section 2 1 3 for more on area selection Finally you can restrict selection to those pieces of text that have a specified Code or Units setting see Section 6 8 3 for more on code and units 118 Using the Electric VLSI Design System version 8 11 Chapter 4 Display 4 10 3D Windows 4 10 1 Introduction Electric has the ability to view an integrated circuit in 3 dimensions as shown below allowing a fuller understanding of the interaction between layers When displaying 3D you can rotate zoom and pan the image to get a be
438. s and causes them to be ignored see Section 9 2 3 AFG Exclusion places a node that tells Auto Fill Generation to ignore the area not currently used but see Section 9 8 2 for more on Auto Fill Generation Invisible Pin places an invisible pin node see Section 7 6 3 Universal Pin places an universal pin node see Section 7 6 3 Unrouted Pin places an unrouted pin node see Section 7 6 3 Using the Electric VLSI Design System version 8 11 47 Chapter 2 Basic Editing 2 2 2 Arc Creation As the introductory example showed arcs are created by clicking the right button This can actually function in two different ways depending on what is highlighted Segment Wiring If one node is highlighted segment wiring is done in which an arc is drawn from the highlighted node to the location of the cursor If there is nothing at that location a pin is created and it is left highlighted Using the right button again runs an arc from that pin to another location By clicking and holding the right button you can see the path that the new arc will follow In general all wiring operations should be done by clicking and holding the right button then moving the cursor until the intended wiring is shown and finally releasing This is recommended because wiring is quite complex and can follow many different paths If you type a digit key while the right button is pressed it changes the wiring layer by inserting cont
439. s and locations If the ports are aligned correctly but not named the same this matching will fail Check Ignore port names to disable name matching and use only position information If the new node is missing essential ports such that existing wires cannot be reconnected then the change will fail unless Allow missing ports is checked Besides replacing the currently highlighted node or arc Change selected ones only it is also possible to specify replacement of many other objects e Change all connected to this requests that objects of the same type which are connected to the highlighted ones be changed e Change all in this cell requests that all objects of the same type in this cell be changed e Change all in this library requests that all objects of the same type in the current library be changed e Change all in all libraries requests that all objects of the same type in every library be changed This is a modeless dialog it can remain up while other editing is being done Click Done to dismiss it and Apply to make a change Note that some Schematic nodes use parameters to further describe them For example an electrolytic capacitor is really just a capacitor with the electrolytic parameter on it Therefore you can change a node into a capacitor but not an electrolytic capacitor because it is not in the list To change a capacitor into an Using the Electric VLSI Design System version 8 11 151 Chap
440. s at the current level of design This checkbox requests that the NCC annotations be used when exporting GDS It enables external circuit analysis programs such as Assura to properly understand the circuit connectivity Collapse VDD GND pin names Requests that all names starting with VDD or GND be merged into a single power or ground signal Instantiate arrays This controls whether or not arrays in the GDS file are instantiated By default arrays are instantiated fully but this can consume excessive amounts of memory if there are large arrays If you uncheck this item only the upper left and lower right instance are actually placed Array simplification This controls the simplification of special array reference objects in GDS When an array of cell instances is found and each cell instance contains a single piece of geometry Electric can simplify the array specification so that a single pure layer node is created instead of an array of instances This pure layer node has outline information that covers each of the arrayed objects see Section 6 10 1 for more on outlines This preference can be set to None no simplification of array references is used Merge individual arrays in which the above simplification is performed and Merge all arrays in which multiple array references are combined so that a single pure layer node is place for each layer in the cell regardless of the number of array references that are used T
441. s bottom Text is anchored at its lower right Text is anchored at its left Text is anchored at its center Text is anchored at its right Text is anchored at its upper left Text is anchored at its top Text is anchored at its upper right Text is shown in the named font Text has relative size in grid units Variable is inheritable only for variables on Cells or Exports Text is italic Text is underlined Variable is written in the form NAME V ALUE Text is Java code Text is Spice code Using the Electric VLSI Design System version 8 11 X lt xoff gt Y lt yoff gt Example D4G8 Chapter 10 The JELIB and DELIB File Format Text is TCL code Variable is a parameter Text is rotated 90 degrees Text is rotated 180 degrees Text is rotated 270 degrees Text is interior seen only when inside the cell Value is in Resistance units Value is in Capacitance units Value is in Inductance units Value is in Current units Value is in Voltage units Value is in Distance units Value is in Time units Text is offset in X from object center Text is offset in Y from object center The text is anchored on the left D4 and is 8 units tall G8 Using the Electric VLSI Design System version 8 11 355 Chapter 10 The JELIB and DELIB File Format 10 4 3 Example As an example of the JELIB format let us assume a design with two levels of hierarchy The bottom level of hie
442. s connectivity information during design there is no need for node extraction the process of extracting connectivity from layout However there are situations where a circuit has only layout and no connectivity specifically when a circuit has been read into Electric from CIF GDS or other formats that have no connectivity information in them see Section 3 9 2 When CIF GDS and other foreign file formats are read into Electric the cells they create are composed entirely of pure layer nodes see Section 7 1 1 These nodes appear to represent the circuit correctly and can even be written back out to CIF or GDS correctly But the missing connectivity information means that Using the Electric VLSI Design System version 8 11 335 Chapter 9 Tools Electric cannot properly analyze these circuits cannot do DRC simulation etc The solution is to convert this geometry into properly connected components To convert the current cell into connected geometry use the Extract Current Cell command from menu Tools Network To convert the current cell and all subcells use the Extract Current Hierarchy command Electric creates new versions of the layout cells that have higher level nodes and arcs in them Although the process of converting layout into connectivity information is difficult it can usually be done correctly In Electric this process is complicated by the fact that the resulting connectivity information must be expressed as a s
443. s differ see below The cell export can be highlighted by clicking on its characteristics Mismatched Comparisons 1 9 mipscells dpor2 sch lay 2 Export Global Network Conflicts 1 dpor2 sch EEE port Global Characteristics Conflicts 1 Using the Electric VLSI Design System version 8 11 319 Chapter 9 Tools Unrecognized Parts This node has a list of parts transistors and resistors with unrecognized types see below Each part can be highlighted by clicking on its type NCC Messages A m Eg Mismatched Comparisons 1 Oooo o a Part Type mipscells dpor2 sch lay 1 3 Reno dpor2 lay Thick P Transistor Advanced Features The total number of mismatched cell comparisons is displayed in square brackets on the top of the tree Only comparisons that did not pass NCC tests are counted and displayed Each failed comparison corresponds to one top level tree node By default NCC halts after the first failed comparison and therefore the tree contains just one failed comparison If the user configures the NCC Preferences to continue even after finding mismatched cells then NCC compares all cells and displays all that mismatch When multiple cells have mismatches the left pane will display more than one top level node as shown below NCC Messages Fi m xi i i Summary of bitslice sch Summary of bitslice lay Ma mipscells bitslice sch lay 34 23 Parts 20 Parts Exports
444. s often combined with LEF Library Exchange Format files For more information on reading and writing DEF or LFF see Section 3 9 2 and Section 3 9 3 When reading DEF files respectively DEF options are controlled with the DEF 7 Place physical interconnect Preferences in menu File Preferences I O Import section DEF tab IV Place logical interconnect Reset All This dialog controls whether DEF reads physical Only resets USER Preferences and or logical information If a type of interconnect is Help tao not checked the DEF input reader ignores those arcs Cancel Using the Electric VLSI Design System version 8 11 197 Chapter 7 Technologies 7 3 6 CDL Control _ Categories C General F Display S ro B CDL Circuit Description Language is almost e identical to Spice format and is used as a netlist EDIF interchange method CDL options are controlled DEF with the CDL Preferences in menu File Preferences I O section CDL tab SUE o teary Include File This dialog controls the library name and path oo Copyright Cadence Library Name pooo information that is written when generating a Tools netlist You can specify an Include file which L Technology Cadence Library Path will be inserted at the top of the netlist Also I Convert brackets you can choose to convert square bracket characters if your CDL cannot handle indexed Export Import i
445. s shown Uncheck Use Perspective to see a parallel display Antialiasing can be turned on by checking Use Antialiasing Due to performance issues antialiasing is not on by default You can also control the display of cell bounds and axes The limit on the number of nodes prevents massively large circuits from swamping the 3D system The transparency option controls whether you can see through layers allowing finer control of the display The transparency factor ranges from 0 fully opaque not transparent at all to 1 completely transparent an invisible shape The transparency mode sets the rasterization technique to use during rendering Possible values are NONE BLENDED FASTEST NICEST or SCREEN DOOR The default setting of NONE indicates that all objects are opaque Due to rendering issues while setting more than 1 layer with the transparency mode NICEST the select layers are set with SCREEN_DOOR so they can be seen from any angle Refer to www j3d org for technical details Other controls are available in this dialog for example the initial zoom factor and rotation If the displayed layers are too thin along the Z axis compared to their X and Y values use the Z Scale field to make everything thicker Lights The 3D view uses one the ambient background light and two directional lights The ambient light is always on but the directional light can be enabled or disabled with the checkboxes The directional lights sit outsid
446. se the Clear Selected Stimuli command To remove all stimuli on a the selected waveforms use Clear All Stimuli on Selected Signals To remove all stimuli in the simulation use Clear All Stimuli Besides simple test vectors the ALS Clock Specification x simulator can also set clock patterns on the currently selected signal by using the Set C Frequency Clock on Selected Signal command Period fo cooocco1 There are two ways to specify a clock by frequency in cycles per second or period Cancel in seconds Note that the clock cycles infinitely but Electric generates simulation events to fill only the current waveform window If you want more clock events generated zoom out the waveform window before issuing the clock command Once a set of stimuli has been established you can save it to disk with the Save Stimuli to Disk command These stimuli can be restored later with the Restore Stimuli from Disk command Each built in simulator has its own format for saving stimuli The Simulators Preferences in menu File Preferences Tools section Simulators tab offers some controls for built in simulators e Auto advance time requests that the main time cursor advance after each stimulus is added This allows each stimulus added to occur at a new time e Resimulate each change requests that the simulator rerun the simulation after any change to the stimuli Because the process of simulating a circuit ca
447. sed in DRC a parameter to determine which points are off grid Example lt resolution value 2 0 gt e lt defaultFoundry gt is a name of the default foundry for this technology The name references one of the lt foundry gt elements found later in the Xml file Example lt defaultFoundry value MOSIS gt e lt minResistance gt global minimum resistance for parasitics Example lt minResistance value 4 0 gt e lt minCapacitance gt global minimum capacitance for parasitics Example lt minCapacitance value 0 1 gt e lt logicalEffort gt defines default project preferences for the Logical Effort tool Example lt logicalEffort gateCapacitance 0 167 wireRatio 0 16 diffAlpha 0 7 gt e lt transparentLayer gt defines the transparent layers in the technology All layers can be drawn in either a transparent or opaque style Transparent layers can overlap other transparent layers without obscuring each other they blend where they overlap Opaque layers cover all other layers without blending Because the system needs to store all combination of transparent layers it is not possible to make every layer transparent Instead less used layers should be opaque and use a stipple pattern so that they do not cover everything The exception is the Layer Display Algorithm which does not use the transparent opaque distinction see Section 4 3 for more on the display algorithms This element lists the number of transpar
448. side the lt primitiveNode gt subelements 2 The lt oldName gt lt lowVt gt lt highVt gt lt nativeBit gt lt od18 gt lt od25 gt and lt od33 gt subelements are also moved into the lt primitiveNode gt subelements 3 The lt nodeLayer gt elements inside of a lt primitiveNodeGroup gt may have an optional lt inNodes gt subelement This subelement defines a list of primitive nodes in the group where this lt nodeLayer gt can occur Example lt primitiveNodeGroup gt lt primitiveNode name P Transistor fun TRAPMOS gt lt primitiveNode name Thick P Transistor fun TRAPMOSHV1 gt lt od18 gt lt primitiveNode gt lt nodeBase gt lt box gt lt lambdaBox k1lx 1 5 khx 1 5 kly 1 0 khy 1 0 gt lt box gt lt nodeBase gt lt nodeLayer layer P Active style FILLED portNum 1 electrical true gt lt serpbox kly 1 0 1lWidth 4 0 rWidth 0 0 tExtent 0 0 bExtent 0 0 gt lt lambdaBox k1lx 1 5 khx 1 5 kly 1 0 khy 4 0 gt lt serpbox gt lt nodeLayer gt lt nodeLayer layer Thick Active style FILLED portNum 1 gt lt inNodes gt lt primitiveNode name Thick P Transistor gt lt inNodes gt lt serpbox 1lWidth 8 0 rWidth 8 0 tExtent 4 0 bExtent 4 0 gt lt lambdaBox k1lx 5 5 khx 5 5 kly 8 0 khy 8 0 gt lt serpbox gt lt nodeLayer gt lt primitivePort name poly left gt lt portAngle primary 180 range 90 gt lt portTopology gt 0 lt portT
449. sign System version 8 11 265 Chapter 9 Tools 9 2 4 Coverage Rules Some foundries request that each layer occupy a minimum percentage of the chip To enforce such rules additional pieces of geometry must be placed around the chip to fill that layer _ Categories Coverage USER Preferences E General fl Display Technology mocmos x To check for proper minimum layer coverage Yo Layers j use the Check Area Coverage command in El Tools ERIN menu Tools DRC To control the coverage sai Sa ean rules use the Coverage Preferences in menu File Preferences Tools section Coverage tab Each layer in the technology has a minimum percentage of coverage that is needed DRC Fast Henry Logical Effort NCC Network Parasitic gt Lan di a a E E 8 The coverage check proceeds in a tiled manner checking rectangular areas of the cell a E t I t For example to check each 100x100 unit area mo Coverage Area fio of the cell set Width and Height to 100 Reset Reset All and set DeltaX and DeltaY to 100 only resets USER Preferences Bounding Selection Help Apply Width 250 Deltax 250 Height 250 Delta 250 Cancel The List Layer Coverage on Cell command is another way to compute the percentage of the cell that is covered by each layer This command examines the entire cell without breaking it into tiled rectangles Use the Fill MoCMOS command in menu Tools
450. sign System version 8 11 35 Chapter 1 Introduction the letters SP in the toolbar You can use the Make Selected Easy command if you want to restore a node or arc to be easily selected Electric also provides the Coverage Implants Generator command in menu Tools Generation that automatically creates hard to select pure layer nodes for N and P wells This command is convenient for simple geometries inside of a cell Create exports for the cell When you use the cell in another design the exports define the locations that you can connect to the cell Click near the end of the short Metal 1 input line that you just drew on the left gate and select the Metal 1 Pin node If you accidentally select the Metal 1 arc instead click elsewhere in space to deselect the arc then try again to find the pin You may also try holding the Control key while clicking to cycle through everything that is under the cursor Add an input export called a type Ctrl E to get the export dialog Repeat for input b Export output y from the metal line connecting the nMOS and pMOS transistors You may have to place an extra pin and connect it to the output line to give yourself a pin to export as y Also export vdd and gnd from the Metal 2 arcs these should be of type power and ground respectively Electric recognizes vdd and gnd as special names so be sure to use them 1 12 4 Schematics and Layout Tutorial Hierarchical Design Now tha
451. sistor node P Transistor TECHNOLOGY SUPPORT Using the Electric VLSI Design System version 8 11 factors 217 Chapter 8 Creating New Technologies 8 2 Converting between Technologies and Libraries Converting Technologies to Libraries The best way to create a new technology is to change an existing one Use the Convert Technology to Library for Editing command in menu Edit Technology Editing and select a similar technology Unfortunately the Schematic and Artwork technologies are too complex to edit and cannot be converted Conversion of a technology to a library creates a library with the same name as the technology Note that technologies with settings such as MOSIS CMOS will be converted with their current settings only and the options will no longer be available Technology Editing Mode Once a technology library has been created editing of its cells is done in a special technology editing mode The system knows to use technology editing mode because the cells are marked as being Part of a technology editor library see the Cell Properties command of the Cells menu see Section 3 7 3 Converting Libraries to Technologies To convert a technology library into a technology use the Convert Library to Technology command gt E3 Convert Library to Technolo You are given the opportunity of naming the technology and e xl can also request that XML code be produced this code can Gre
452. sition 0 120 direction input port name leftl position 0 100 direction input port name left2 position 0 50 direction input port name left3 position 0 30 direction input port name bot0 position 40 0 direction bidir port name bot1l position 60 0 direction bidir nets net name iv0 segment port top0 component block0O outtopl net name ivl segment port topl component block0O outtop2 net name iv2 segment component block0O outbot1l component blockl outtopl1 net name iv3 segment component block0O outbot2 component blockl outtop2 net name iv4 segment component blockl outbotl port bot0 net name iv5 segment component blockl outbot2 port botl net name ih0 segment port left0 component r0 a net name ihl segment component r0 b component blockO inleftl net name ih2 segment port leftl component rl a net name ih3 segment component rl b component blockO inleft2 net name ih4 segment port left2 component r2 a net name ih5 segment component r2 b component blockl inleftl net name ih6 segment port left3 component r3 a net name ih7 segment component r3 b component blockl inleft2 214 Using the Electric VLSI Design System version 8 11 150 140 130 120 110 100 90 30 70 60 50 40 30 Chapter 7 Technologies Commands To read an architecture file use the Read Architecture And
453. slowly than other shapes when extents are increased The lt minSizeRule gt element defines the FullRectangle manually as a rectangle with its center at the origin The FullRectangle in the presence of lt minSizeRule gt is x 0 5 minSizeRule width y 0 5 minSizeRule height and x 0 5 minSizeRule width y 0 5 minSizeRule height This element defines FullRectangle of the Metal 1 Metal 2 Con as x 2 5 y 2 5 and x 2 5 y 2 5 Example lt minSizeRule width 5 0 height 5 0 rule 8 3 9 3 gt lt spiceTemplate gt optional spice template of this node Using the Electric VLSI Design System version 8 11 Chapter 8 Creating New Technologies Example lt primitiveNode name Metal 1 Metal 2 Con fun CONTACT gt lt diskOffset untilVersion 1 x 2 5 y 2 5 gt lt diskOffset untilVersion 2 x 2 0 y 2 0 gt lt sizeOffset 1x 0 5 hx 0 5 Lly 0 5 hy 0 5 gt lt nodeLayer layer Metal 1 style FILLED gt lt box gt lt lambdaBox k1lx 2 0 khx 2 0 kly 2 0 khy 2 0 gt lt box gt lt nodeLayer gt lt nodeLayer layer Metal 2 style FILLED gt lt box gt lt lambdaBox k1lx 2 0 khx 2 0 kly 2 0 khy 2 0 gt lt box gt lt nodeLayer gt lt nodeLayer layer Vial style FILLED gt lt multicutbox sizex 2 0 sizey 2 0 sepld 3 0 sep2d 3 0 gt lt lambdaBox k1lx 0 0 khx 0 0 kly 0 0 khy 0 0 gt lt multicutbox gt lt nodeLayer gt
454. stance is the number of degrees counterclockwise rotated about the center The attributes section of the instance assigns name value pairs this can be used to program the FPGA The nets section defines internal networks There can be multiple segment entries in a net each defining a straight wire that runs from the FROMPART to the TOPART These parts can be either component INSTNAME PORTNAME port PORTNAME or coord X Y depending on whether the net ends at a component port or at an arbitrary position inside of the block Using the Electric VLSI Design System version 8 11 213 Chapter 7 Technologies Here is an example of block definition code and its layout blockdef attributes name testblock size 80 150 components instance type sampleblock name block0 position 30 80 instance type sampleblock name block1 position 30 10 left repeater portb 20 120 repeater name r0 name r1 direction porta porta 10 120 10 100 portb 20 100 direction ino ing Sample Block ine ing leftt horizontal horizontal repeater name r2 porta 10 50 portb 20 50 direction horizontal repeater name r3 porta 10 30 portb 20 30 direction horizontal left2 Sample Block ine 8 ing left3 ports port name top0 position 40 150 direction bidir port name topl position 60 150 direction bidir port name left0 po
455. stor sizes and Hierarchical Comparison simultaneously then NCC restricts which cells it treats hierarchically to ensure a correct answer in the presence of automatically sized transistors For this case it compares a pair of cells hierarchically if and only if each cell is instantiated exactly once Series Parallel Combination When NCC builds the netlist it performs series parallel combination When NCC finds a number of transistors with the same channel length wired in parallel NCC substitutes a single transistor whose width is the sum of the widths of those transistors When NCC finds a number of transistors with the same channel width and channel length wired in series NCC substitutes a single multi gate transistor that represents all the series transistors NCC uses the Relative size tolerance and the Absolute size tolerance fields to determine how close transistor widths and lengths have to be before it will combine them in series or in parallel Body Checking Section The check box Check transistor body connections allows the user to select whether NCC checks connections to the body port of transistors By default body checking is disabled and NCC ignores connections to transistor body ports If the user wishes to check body connections then she must check this box Then the NCC will make sure that the schematics and layout have matching connections to all transistor body ports Note that only certain versions of schema
456. systems that use Xorg and Xinerama To disable the dimming and speed the display uncheck Dim upper levels of hierarchy when editing Down In Place See Section 3 5 for more on down in place editing Using the Electric VLSI Design System version 8 11 95 Chapter 4 Display Many commands cause cells to be displayed in a new window If you uncheck Show cell results in new window then the cells are shown in the current window instead When errors are highlighted the highlighting pulsates to make the error more visible To disable pulsating highlighting uncheck Make error highlighting pulsate When panning the window using menu commands the distance to pan can be controlled with the Panning distance selection see Section 4 4 2 for more on panning The Display style controls whether Electric uses the MDI Multiple Document Interface or the SDI Single Document Interface style of interaction MDI used typically on Windows systems uses a single large window that has all of the editing windows inside of it SDI used typically on Linux and Macintosh systems creates a window for every editing window in Electric You can leave the default style for your operating system or you can override that and force a style Display Algorithms Electric has three different display algorithms e The Pixel Display Algorithm is the older It was the only display algorithm prior to version 8 04 of Electric e The Vector Display
457. t Users are encouraged to examine the hierarchy to make sure that arbitrary hierarchical changes do not cause undetected damage to the layout Electric will warn you of any changes which affect undisplayed cells farther up the hierarchy Using the Electric VLSI Design System version 8 11 137 Chapter 5 Arcs 5 3 Setting Constraints The two most common constraints rigid and fixed angle see Section 5 2 1 can be controlled from the Edit Arc menu When the Rigid Non Rigid Fixed Angle and Not Fixed Angle commands are issued all of the currently highlighted arcs have those constraints set In order to set slidability see Section 5 2 2 select a single arc and issue the Object Properties command in menu Edit Properties Arc Properties Df x Type Metal 1 Network out Name Props Width Length 20 Angle 0 V Easy to Select At the bottom of the arc properties Head RotationLower lay Rotation 0 dialog when the More button has At 1 0 43 5 been pressed are check boxes that Tail Metal 1 Pin pin 13 control constraints This is the only At 21 0 43 5 i 0 43 way to affect the slidable constraint See See which is not very commonly Less Apply Cancel used Rigid End Extension Both ends V Fixed angle Directionality None V Slidable Negation None List Shows Attributes List Shows Bus Members Name vae Code Color and Pattern 138 Using t
458. t management functions are also available in context menus in the cell explorer 8 Browse The first step needed to use Import the project management Reset All system is to choose a location for the repository This must be a shared location that each user can access read and write User Name strubin Use the Project Management Preferences in menu File Preferences General section Project Management tab Only resets USER Preferences 178 Using the Electric VLSI Design System version 8 11 Chapter 6 Advanced Editing Each user must set the same location in their Project Management Preferences so that they can share the repository Also be sure that your user name is correct as this will be used when tagging file changes After the repository has been set libraries can be entered into it Use the Add Current Library To Repository command to place your library in the repository Use Add All Libraries To Repository to add all libraries in the system Note that a library that has been entered into the repository is also tagged with information about the repository location as well as the state of the cells checked in or checked out Therefore you should save your library after entering it into the repository Other users can obtain a copy of your library directly from the repository by using the Get Library From Repository command Checking Cells In and Out When a cell is not checked out
459. t da Nodes USER Preferences For New Primitive Nodes Technology mocmos x Metal 1 Pin Default X size E Default Y size E For Cells Primitive 7 Check cell dates during editing V Switch technology to match current cell L M Place Cell Center in new cells IV Reconstruct arcs and exports when deleting instances Always prompt For index when descending into array nodes For All Nodes I Disallow modification of complex nodes T Disallow modification of locked primitives IV Move after Duplicate I Duplicate In Place P Duplicate Array Paste copies exports IV Increment rightmost array index IV Extract copies exports te information be used to ensure a proper circuit building sequence When this box is checked warning messages will be issued when editing a cell that has more recent subcell instances Electric tracks cell creation and revision dates and this information can be displayed with the Describe this Cell command and others in menu Cell Cell Info see Section 3 7 1 144 Using the Electric VLSI Design System version 8 11 Chapter 6 Advanced Editing e Switch technology to match current cell requests that the current technology automatically change whenever the current cell changes so that the two match e Place Cell Center in new cells requests that all newly created cells have a Cell Center node placed at the origin see Section 3 3 for more on C
460. t extension e FILEPA TH The full path to the output file The bottom part of the dialog controls the reading back of Spice output for plotting in the waveform window e Output format The format to expect when reading Spice output The choices are Standard the default Raw raw format RawSmart SmartSpice raw format RawLT LTSpice raw format and Epic for Nanosim e Epic reader memory size Sets the amount of memory to allocate to the separate reader process which is only valid if the Output format is set to Epic e Extracted network delimiter character The character that separates automatically extracted networks in the Spice output Some Spice engines use and others use Using the Electric VLSI Design System version 8 11 279 Chapter 9 Tools Another set of controls can be used is the Spice Model Files Preferences in menu File Preferences Tools section Spice Model Files tab This dialog allows you to specify a disk file of Spice cards that will be used to describe any cell Instead of the cell subcircuit the specified disk file is included in the deck eeeeeeeeee eee 6 6 Export Reset Sy Yo Tools ik Antenna Rules Compaction Coverage DRC Fast Henry Logical Effort NCC Network Parasitic Placement Routing Silicon Compiler Simulators Spice Spice Model Files Yerilog Import Reset All Only resets USER Preferences Help Cancel gu
461. t is 8 units tall G8 Using the Electric VLSI Design System version 8 11 353 Chapter 10 The JELIB and DELIB File Format ART_degrees F 0 0 3 1415927 Adds a variable called ART_degrees with an array of 2 floating point values 0 0 and 3 1415927 EXPORTS E ccc gate 1l sch a ccc hate l sch b 0 4 Adds a variable called EXPORTS with an array of 2 exports export a of cell ccc gate sch and export b 0 4 from the cell ccc hate sch ATTR_z0 D5G0 5 NPY1 150 Adds an attribute called zO with the integer value 50 It is displayed anchored at the center D5 0 5 unit tall GO 5 written as name value N is a parameter P and is offset by 1 in Y Y1 10 4 2 Text Descriptors Text descriptors appear in every Variable and also in other places cell instances and exports All text descriptors have an anchor factor DO through D9 If the anchor starts with a lower case d the text is hidden but the descriptor information is remembered Here are the fields of a text descriptor A lt size gt B C lt color gt DO d0 D1 dl D2 d2 D3 d3 D4 d4 D5 d5 D6 d6 D7 d7 D8 d8 D9 d9 F lt font gt G lt size gt H I L N OJ OL 354 Text is absolute size in points Text is bold Text is drawn in the color index given Text is anchored at its center limited to the size of its owner Text is anchored at its lower left Text is anchored at it
462. t values You can select any of these pieces of text and edit their text or other information with the exception of the Units field which must match the defined parameter s units If you delete a parameter s text the parameter remains but with its default value Using the Electric VLSI Design System version 8 11 161 Chapter 6 Advanced Editing Parameters on instances of cells are placed at the same location as they appear inside of the icon cell To change the location on all subsequently created icon instances move the location in the icon If a parameter is added to a cell without checking Show new parameter on instances existing instances of that cell will not show the parameter To see the parameter at a later time use the Update Parameters on Node command in menu Edit Properties To do this everywhere use the Update Parameters all Libraries command It is sometimes desirable for each instance parameter to have a unique value When the default value of a parameter inside the schematic or icon cell has in it then the number before that will be incremented after each new icon instance is created Similarly a indicates that the number be decremented after instance is created This allows all instance parameters to be given unique values 162 Using the Electric VLSI Design System version 8 11 Chapter 6 Advanced Editing 6 9 Networks 6 9 1 Introduction A collection of electrically connected components d
463. t you have a 2 input NAND gate you can use it and an inverter to construct a 2 input AND gate Such hierarchical design is very important in the creation of complex systems You have found that the layout of an individual cell can be quite time consuming It is very helpful to reuse cells wherever possible to avoid unnecessary drawing Moreover hierarchical design makes fixing errors much easier For example if you had a chip with a thousand NAND gates and made an error in the NAND design you would prefer to have to fix only one NAND cell so that all thousand instances of it inherit the correction Each schematic has a corresponding symbol called an icon used to represent the cell in a higher level schematic For example open the inv sch and inv ic cells to see the inverter schematic and icon You will need to create an icon for your 2 input NAND gate When creating your icon it is a good idea to keep everything aligned to the 1 unit grid this will make connecting icons simpler and cleaner when you use it in another cell Edit your nand2 sch cell and use the Make Icon View command in menu View Electric will create a generic icon based on the exports as shown here It will drop the icon in the schematic for handy reference drag the icon away from the transistors so it leaves the schematic readable A schematic is easier to read when familiar icons are used instead of generic boxes Modify the icon to look like this Pay
464. tal epa Reset Reset All Pema are Be Routing feed through size fs Only resets USER Preferences Main power wire width Routing min port distance e Apply NEPESSEG metal E Routing min active distance 8 Cancel e The Layout section controls the number of rows of cells that will be created A one row circuit may be exceedingly wide and short so you may wish to experiment with this value For a square circuit the number of rows should be the square root of the number of instances in the circuit the number of instances appears as the sum of the unresolved references listed by the VHDL Compiler e The Arcs section lets you set the horizontal and vertical routing arcs as well as the power rails e The Well section gives you the option of placing blocks of P well and N well over the cell rows e The Design Rules section lets you control Via size metal spacing feed through size port distance and active distance prs TELE 340 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools 9 13 Placement Electric has a placement tool that can rearrange a circuit so that routing is easier The tool can handle schematic or layout cells To run placement use the Place Current Cell command in menu Tools Placement The Placement Preferences in menu File Preferences Tools section Placement tab let you control
465. tation on the schematic cell because it s more visible to the designer flattenInstances lt string or regular expression gt Hierarchical NCCs do not require a perfect match between the schematic and layout hierarchies Instead hierarchical NCC uses heuristics to determine which cell instances must be flattened and which can be compared hierarchically The heuristic sometimes make mistakes When that happens the flattenInstances annotation can guide the heuristic The list of strings and or regular expressions are used to match instance names within the cell Those cell instances that match are always flattened 308 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools notSubcircuit lt comment gt The designer should add the notSubcircuit annotation to a cell if e The schematic and layout will pass NCC when compared separately but e Hierarchical NCC of a parent of the cell should not treat the cell as a hierarchical element but should instead flatten it One reason for using this annotation is to correct errors made by the heuristic that determines which cells to flatten and which to compare hierarchically For example suppose that the schematic instantiates cell B sch 1000 times and the layout instantiates cell B lay 500 times In principle one could use the flattenInstances annotation to inform NCC which instances to keep and which to flatten However sometimes that s more work than it s worth and it s better
466. te MOS transistors e nMOS CN pMOS CN carbon nanotube MOS transistors 204 Using the Electric VLSI Design System version 8 11 Chapter 7 Technologies e nMOS VTL pMOS VTL low threshold MOS transistors e nMOS VTH pMOS VTH high threshold MOS transistors e nMOS HV1 pMOS HV1 high voltage 1 lowest voltage MOS transistors e nMOS HV2 pMOS HV2 high voltage 2 medium voltage MOS transistors e nMOS HV3 pMOS HV3 high voltage 3 highest voltage MOS transistors e nMOS NT HV1 pMOS NT HV1 native high voltage 1 lowest voltage MOS transistors e nMOS NT HV2 pMOS NT HV2 native high voltage 2 medium voltage MOS transistors e nMOS NT HV3 pMOS NT HV3 native high voltage 3 highest voltage MOS transistors o PNP PNP bipolar transistors o DMES EMES MESFET transistors e pJFET nJFET JFET transistors Other primitives that can appear in different forms e Capacitors can be normal or electrolytic e Diodes can be normal or zener e Resistors can be normal n Poly p Poly n Well or p Well e Off page connectors appear differently depending on their export s characteristics input output etc The Spice entry presents a popup menu of Spice parts More information about the use of these parts can be found in the Section 9 4 3 The Cell entry presents a popup menu of all cell instances The Global entry provides two nodes a Global Signal node defines a signal name that spans levels
467. ted the list shows the parameters on the node When Parameters is selected the entries in the list let you modify individual values Note that there is also an Edit Parameters button which brings up a full dialog for editing them See Section 6 8 5 for more on Parameters The last button Bus Members on Port lists all of the signals found on the currently selected bus port see Section 6 9 3 for more on busses In some situations the list may be too large to display easily for example a cell instance with hundreds of ports When the list contains more than 100 entries only the first 100 are shown and the Show All button is available to show the entire list If many objects are selected you can move them by a specific distance with the Move Objects By command in menu Edit Move If many nodes are selected the Object Properties command will list all of them and allow appropriate changes to be made depending on what is selected Multi Object Properties Ea 33 selections Node Metal 1 Metal 2 Con contact 36 Node Metal 1 P Active Con contact 10 Node Metal 1 P Active Con contact 16 Node Metal 1 Pin pin 23 Node Metal 1 Pin pin 32 Node Metal 1 Pin pin 33 Ease of Selection ESEME Node Metal 1 Pin pin 44 Node Metal 1 Pin pin 64 Node Metal 1 Pin pin 65 Node P Transistor pmos 1 Node P Transistor pmos 3 Node Polysilicon 1 Pin pin 0 x Remove Remove Others Ap
468. tents 346 Using the Electric VLSI Design System version 8 11 Chapter 10 The JELIB and DELIB File Format The syntax of an external export reference is F lt name gt lt centerX gt lt centerY gt the name of the external export lt centerX gt freserved for the X coordinate of the center of export polygon lt centerY gt _ reserved for the Y coordinate of the center of export polygon Examples Lspiceparts home strubin electric spiceparts jelib Rgate 1l sch 4 4 0 2 Fout 0 2 Declares that an external library called spiceparts will be used by the current library and that it can be found at home strubin electric spiceparts jelib In that library is a cell called gate 1 sch whose contents run from 4 to 4 in X and 0 to 2 in Y In that cell is an export called out with center at 0 2 10 2 3 Technologies All technologies used in the library must be in the header The other reason for a technology declaration to exist is if the technology has preferences stored on it If there are multiple technology lines they are sorted by technology name The syntax is T lt name gt lt variable gt lt name gt ithe name of the technology a list of preferences on the technology stored as variables see Section lt variable gt 10 4 1 Examples Tmocmos Declares that there should be a technology called mocmos Tmocmos ScaleFORmocmos D200 Declares the technology mocmos and also
469. ter 6 Advanced Editing electrolytic capacitor paste an electrolytic capacitor onto it Besides capacitors parameters can be found on diodes transistors sources and two ports the four connection primitives such as VCCS Another command for changing circuitry is Replace Cells from Library in menu Cell Merge Libraries This command replaces instances in the current cell with like names ones from another library It is useful when a new standard cell library is replacing an old one and all instances must be switched 152 Using the Electric VLSI Design System version 8 11 Chapter 6 Advanced Editing 6 7 Undo Control Electric has an undo mechanism that tracks all changes made during a session When a command is issued it and its side effects are stored The Undo command in menu Edit reverses the last change made this includes any changes that may have been made by other tools Multiple uses of the Undo command continue to undo further back The Redo command redoes changes up to the most recent change made a a You can also use the undo counterclockwise and redo clockwise icons from the tool bar Electric stores only the last 40 changes so anything older than that cannot be undone To increase the number of changes that are saved use the General Preferences in menu File Preferences General section General tab and change the Maximum undo history field To see a history of changes that were mad
470. tes schematic or netlist Semele f o5 ae views the default is netlist It also lets you set a scale factor for EDIF input The Cadence compatibility check affects both EDIF input and output When checked output of multidimensional and symbolic busses is converted to simpler all numeric busses and input of properties starting with def are added to cells as parameters Finally the Accepted Parameters Export ma area lets you list those EDIF parameters that will be read all Reset All Configuration Fle others are ignored Only resets USER Preferences The configuration file provides overrides For controlling Help Apply EDIF reading and writing Browse Cancel The bottom section of the panel lets you specify a configuration file that will control EDIF I O This file has conversions between coordinates and names inside of Electric and the EDIF file The file has these lines of text that control different aspects of conversion IV Cadence compatibility Accepted Parameters Type parameter names one per line that will be placed on nodes when reading EDIF SUE Library Copyright Tools Technology k a fal ik gu e Primitives A line starting with P controls how primitives are converted to EDIF The line has this format P ElTech ElPrim ElFunc ElRot ElPortOff EdTech EdPrim EdFunc EdPortOff Where ElTech is the Electric technology name e g schematic
471. th Electric version prior to electric attribute of that lt version gt element Attributes lt x gt and lt y gt are actually half of the values written to Jelib file So the Metal 1 Metal 2 Con node example shown below will be written 5 0 width height with Jelib prior to Electric version 8 05g 4 0 width height with Jelib prior to Electric version 8 050 0 0 width height with Jelib in Electric versions since 8 050 More formally let n extendX and n extendY be the internal values associated with the node instance in the Electric database The values written to library prior to diskOffset until Version were 2 n extendX diskOffset x and 2 n extendY diskOffset y The lt diskOffset gt element is necessary only with legacy technologies Example lt diskoffset untilVersion 1 x 2 5 y 2 5 gt lt defaultWidth gt and lt defaultHeight gt factory default values of the node size The subelement lt lambda gt contains the value of extendX extendY in display units Usually these elements are omitted because the default values of extendX and extendY are 0 So the factory defaults of extendX and extendY are defaultWidth lambda and defaultHeight lambda The factory defaults of BaseWidth and BaseHeight are BaseRectangle width 2 defaultWidth lambda and BaseRectangle height 2 defaultHeight lambda The factory defaults of FullWidth and FullHeight are FullRectangle width 2 defaultWidth lambda and FullRectangle h
472. that runs from the component to the location of the cursor Note that the wire is a fixed angle wire which means that it will be drawn along a horizontal vertical or 45 degree path from the originating node To see where the wire will end click but do not release the button and drag the outline of the wire s terminating node a pin until it is in the proper location It is highly recommended that you do all wiring operations this way because wiring is quite complex and can follow many different paths Once a wire has been created the other end is highlighted see above This is the highlighting of a pin node that was created to hold the other end of the arc Because it is a node the right button can be used again to continue the wire to a new location If while wiring the dragged location is over an existing component the wire will attach to that component To remove wires or nodes you can issue the Undo command in menu Edit to remove the last created object Alternatively you can select the component and use the Selected command in menu Edit Erase Using the Electric VLSI Design System version 8 11 27 Chapter 1 Introduction 1 11 5 Schematics Tutorial Multi Input gates and Negation One aspect of the And Or and Xor gates that you will notice is that their left side the input side can accept any number of wires To see this in action place one of these components in the cell Then repeatedly select its left side and us
473. the Edit Component Menu command in menu Edit Technology Editing This dialog works exactly the same as the Component Menu Preferences see Section 4 5 1 Special Using the Electric VLSI Design System version 8 11 231 Chapter 8 Creating New Technologies 8 8 How Technology Changes Affect Existing Libraries Once a technology is created the components are available for design Soon there will be many libraries of circuitry that makes use of this new technology What happens to these libraries when the technology description changes In most cases the change correctly affects the existing libraries However some changes are more difficult and might invalidate the existing libraries This section discusses the possible changes and shows workarounds for the difficult situations Technology information appears in four different places the layers the arcs the nodes and miscellaneous information on the technology the support cell and color tables Information in these areas can be added deleted or modified The rest of this section outlines all of these situations Adding layers arcs nodes and miscellaneous information Adding information has no effect on the existing circuitry All subsequent circuit design may make use of the new technology elements Deleting layers nodes arcs and miscellaneous information All references to a deleted layer in any nodes or arcs of the technology will become meaningless Th
474. the component menu and select schematics Multiplexor Buffer Inverter Switch Flip Flops 3 port Transistors n Transistor There are two arcs in the Schematic technology the wire blue and the bus green These arcs can be drawn at 45 degree angles One typically names Diodes busses with array names for example insig 0 7 and then names wires with scalar names for example insig 1 See Section 6 9 3 for more on bus naming 4 port Transistors p Transistor Inductor iis a ae To make a physical connection from a wire to a bus the bus pin can connect to either so it acts as a tap In addition the Wire Con node connects wires to Wire Con busses or connects busses of different width replicating the narrower side to make it as wide as the wider side Use the Rip Bus command in menu Edit Arc to automatically add taps to a bus Miscellaneous Functions There are four transistor entries in the menu The two on the right are the n and p transistors The two images on the left are actually popup menus that let you select any style of transistor The difference between the two on the left is that the top one is for 3 port transistors and the bottom one is for 4 port transistors The schematics technology understands these transistor types e nMOS pMOS n and p channel MOS transistors e nMOS D pMOS D depletion MOS transistors e nMOS NT pMOS NT native MOS transistors e nMOS FG pMOS FG floating ga
475. the List Cell Usage command in menu Cell Cell inv2iKnD sch Info For an explanation of the Evaluate Numbers when Sorting Inv knisch Names checkbox see Section 3 7 1 Because Electric is able to keep old versions of cells deleting the f inv2iLT sch latest version will cause an older version to become the most inv2i sch recent Old versions are those whose cell names include the inv2o sch VERSION clause indicating that there is a newer version of this inv3to1 sch view of the cell For example if you have cell Adder and an older version Adder 1 then deleting Adder will cause Adder 1 to be renamed to Adder This might make you think that the deletion failed because there is still a cell called Adder but this cell is actually the zj older but now most recent version JV Evaluate Numbers when Sorting Names I Confirm Deletions Cancel Apply Delete Done To clean up old and unused versions of cells use the Delete Unused Old Versions command in menu Cell Any such cells that are no longer used as instances in other cells will be deleted from the library You will get a list of deleted cells and it is possible to undo this command invLT sch mullerC sch Using the Electric VLSI Design System version 8 11 61 Chapter 3 Hierarchy 3 3 Creating Instances To place an instance of a cell in another cell use the Cell button in the component menu After choosing a cell fro
476. the arc can actually connect in any number of locations Original Structure Contact moved Contact moved nonslidable arc slidable arc Contact Transistor 136 Using the Electric VLSI Design System version 8 11 Chapter 5 Arcs Slidable arcs may adjust themselves within the port area rather than move For example if a node s motion is such that the arc can slide without moving then no change occurs to the arc or to the other node Without the slidable constraint the arc moves to stay connected at the same location within the port Slidability propagation works both ways because if an arc moves but can slide within the other node s port then that node does not move Note that slidability occurs only for complete motions and not for parts of a motion If the node moves by 10 and can slide by 1 then it pushes the arc by the full 10 and no sliding occurs In this case only motions of 1 or less will slide Because ports have area and because arcs end somewhere inside of that area the actual ending point can vary considerably If the arc is at the far side of the port it may protrude out of the far side of the node causing unwanted extra geometry You can shorten an arc so that its endpoint is at the closest side of the port with the Shorten Selected Arcs command in menu Edit Cleanup Cell 5 2 3 Constraint Propagation The last of Electric s constraints is the only one that is not actually programmable by the user Export Connection
477. the fixed angle constraint on this arc e lt angleIncrement gt default state of the angle increment amount on this arc grids placement angles e lt antennaRatio gt value used by the ERC tool e lt diskOffset gt tells how sizes were written in older library files The attribute until Version references the tech attribute of the lt version gt element above This disk offset is applied to Jelib libraries with Electric versions prior to the electric attribute of that lt version gt element Attribute lt width gt is actually half of the value written to Jelib file For example the P Active arc described above will be 15 0 wide with Jelib prior to Electric version 8 05g 3 0 wide with Jelib prior to Electric version 8 050 0 0 wide with Jelib in Electric versions since 8 050 More formally let a extend be the internal value associated with the arc instance in the Electric database The value written to libraries prior to diskOffset until Version was 2 a extend diskOffset width The lt diskOffset gt element is necessary only in legacy technologies Example lt diskOffset untilVersion 1 width 7 5 gt Using the Electric VLSI Design System version 8 11 Chapter 8 Creating New Technologies e lt defaultWidth gt factory default value of arc width This element is not used now and should be omitted e lt arcLayer gt a list of ArcLayers that comprise this Arc The attribute layer references the layer
478. the location of the newly created Wom Wo node To temporarily zoom type z zoom the display and then type z again to finish placing the node To temporarily pan type p pan the display and then type p again to finish placing the node For more on zooming and panning see Sections 4 4 1 and Sections 4 4 2 Besides basic components there are special entries in the component menu for creation of additional nodes e The Cell button displays a list of cell instances that can be created see Section 3 3 e The Pure button only available in layout technologies lets you place pure layer nodes see Section 6 10 1 e The Spice button only available in schematics lets you place Spice primitives see Section 9 4 3 46 Using the Electric VLSI Design System version 8 11 Chapter 2 Basic Editing e The Misc button has a collection of special objects that can be created Cell Instance Annotation Text Layout Text e Cell Instance brings up a dialog to select a cell instance to place Layout Image see Section 3 3 Annular Ring e Annotation Text places a node that contains only text see Section 6 8 1 This can also be accomplished with the Add Text Annotation command in menu Edit Text e Layout Text brings up a dialog to create text from layout nodes Cell Center Essential Bounds Spice Code see Section 6 10 3 Spice Declaration e Layout Image brings up a dialog to
479. the number keys for a valid layer switches to that layer If a node is highlighted it will route to that layer from the node creating contacts as necessary Using the Electric VLSI Design System version 8 11 49 Chapter 2 Basic Editing 2 2 3 Special Cases The default width is set by the Arcs Preferences in menu File Preferences General section Arcs tab If there are other arcs of this type already connected to the new one and they are wider than normal then the new arc will use that width Also if an arc connects to a node that is wider than normal it will grow to match the size of the node this can be disabled in the Arc Preferences see Section 5 5 Note that all arcs overlap their endpoint by half of their width so very wide arcs may overlap their destination with too much geometry You can turn off this overlap by using the Toggle End Extension of Head and Toggle End Extension of Tail commands in menu Edit Arc See Section 5 4 3 for more on end extension An unusual circuit creation command is the Insert Jog In Arc command in menu Edit Arc This command inserts a jog in the highlighted arc by replacing it with three new arcs Two of the new arcs run to the location of the cursor and the third arc is perpendicular to them connecting the ends at the cursor location initially it has zero length Before After Once the jog is inserted either half of the arc may be moved without affecting the other half
480. ther Note that the highlighted ports on the selected nodes are important arcs will run between them so they must be compatible in their wiring capabilities Two point wire creation first attempts to run a single arc Generally this can happen only if the ports are lined up accurately Failing single arc placement an attempt is made to connect with two arcs and an intermediate node These two arcs can bend in one of two directions determined by the location of the cursor 48 Using the Electric VLSI Design System version 8 11 Chapter 2 Basic Editing Special Considerations In addition to running an arc between two nodes you can also use arcs as the starting or ending point of arc creation SS Pin ig If it is sensible the creation command actually uses one of the nodes on an end of the selected arc However if the connection falls inside the arc it is split and a new node is created to make a T connection Electric will allow you to connect two nodes or arcs as long as there is some way in the current technology for those objects to be connected For example if connecting between metal 1 pin and a metal 3 pin in the MOSIS CMOS technology Electric will place metal 1 metal 2 and metal 2 metal 3 contact cuts down and wire between all four nodes When vias are inserted they are placed closest to the destination node or farthest from the original node As mentioned in Section 1 8 pressing
481. tic transistors have body ports The designer must use those schematic transistors In addition in this version of Electric layout transistors also have body ports The Using the Electric VLSI Design System version 8 11 305 Chapter 9 Tools designer must specify the connectivity of the body port of layout transistors using well arcs Note that the body port of the layout transistors are in the very center of the transistor and are hard to select If you wish to connect to the body port of a layout transistor you may need to push the Toggle Special Select button in the Electric tool bar see the Section 2 1 5 for more At the moment only the MoCMOS layout technology has been augmented to allow body connections This is because this implementation of body checking is experimental We d like to get some feedback from users before we go to the effort of generalizing all other technologies Checking All Cells Section In hierarchical mode NCC attempts to compare all cells in the design starting with those at the leaves and working it s way toward the root For that mode it is often best if NCC stops as soon as it finds an export or topology mismatch To get this behavior the user should check Halt after finding the first mismatched cell Note that size mismatches never cause NCC to stop It is occasionally useful to continue checking even after mismatches have been detected For example the designer might find that although a cell
482. ting the highlighted area a precise selection can be made with Area selection see Section 2 1 3 The Print resolution is the number of dots per inch DPI that the printer expects Higher resolutions use more memory for the print image There are many PostScript options available in the lower section e Encapsulated requests that the PostScript output to be insertable in other documents EPS Color offers four color choices Black amp White uses stipple patterns for the layers Color uses solid colors but does not handle overlap because PostScript does not handle transparency Color Stippled uses color stipple patterns for better overlap and Color Merged computes layer overlap and generates blended colors to recreate the appearance on the screen this takes time and memory Printer and Plotter let you specify the size of the page choose Printer for devices that print onto single pieces of paper and Plotter for devices that print onto continuous rolls of paper The Margin field is the amount of white space to leave on the sides All distances in the Height Width and Margin fields are in inches on some printers Line Width controls the width of PostScript lines Although they default to 1 this may be too thin Rotation controls rotation of the image by 90 degrees so that it fits better on the page The default is No Rotation but the popup can switch to Rotate plot 90 degrees
483. tion When X the More button is clicked it grows to full size as shown The full size Object Ports Parameters Bus Members on Port Properties dialog has many new input port cc connects to Metal 2 controls which vary according to the type Highlighted port f nod lected ground port gnd connects to Metal 2 OL NORE SEIE i input port in connects to Metal 2 output port out connects to Metal 1 power port vdd connects to Metal 2 I Locked See Color and Pattern Edit Parameters e Expanded and Unexpanded control how the node is drawn if it is a cell instance An expanded instance is one that shows its contents an unexpanded instance is drawn as a black box see Section 3 4 Shay AI 54 Using the Electric VLSI Design System version 8 11 Chapter 2 Basic Editing e Easy to Select sets whether this node is selectable with a simple click This feature allows you to eliminate pieces of circuitry from active editing see Section 2 1 5 e Invisible Outside Cell indicates that this node will not be drawn when the current cell is viewed from higher up the hierarchy e Locked nodes may not be changed moved deleted The bottom of the expanded Object Properties dialog has a scroll area that can view Ports Parameters or Bus Members on Port By default a list of the node s ports is shown including any exports connections and highlight details If the Parameters button is selec
484. tion they must also be present on the instantiated icon or instance of that definition By default this will be so Finally there must be at least one load that is driven by the gates in order for them to be sized A load is either a transistor or a capacitor Gates that do not drive loads or that do not drive gates that drive loads will not be assigned sizes Logical Effort Libraries Electric comes with a set of libraries that are specially designed for Logical Effort Use the Load Logical Effort Libraries Purple Red and Orange command in menu Tools Logical Effort to read these libraries e The Purple library is a set of logic gates that have been tailored for Logical Effort as described above Using the Electric VLSI Design System version 8 11 331 Chapter 9 Tools e The Red library is a similar set of gates but they are not setup for Logical Effort The Red gates can be used in places where Logical Effort is not to be done e The Orange library is a low level set of gates that is parameterized for a specific fabrication process Orange gates are used in the Purple and Red libraries but should not be used elsewhere The Orange library that comes with Electric is tailored for a generic 180 nanometer process Advanced Features There are several advanced features that may be added to the cell definition e Attribute LEKEEPER 1 This cell is defined as a keeper whose size will be the size of the smallest Logical Effort gat
485. tion can be NODSIZ the minimum size of a node or FORBIDDEN the node is not allowed Example 250 Using the Electric VLSI Design System version 8 11 Chapter 8 Creating New Technologies lt NodeRule ruleName 5 2 Mosis nodeName Metal 1 Polysilicon 1 Con when ALL type NODSIZ value 5 gt e NodeLayersRule gives rules for specific layers in a single node In addition to the standard attributes it has both layer names and a node name The type of information can be SURROUND for layers in anode or ASURROUND for layers in an arc Example lt NodeLayersRule ruleName 2 3 Mosis layerNames P Well N Active nodeName N Transistor when ALL type SURROUND value 5 gt Using the Electric VLSI Design System version 8 11 251 Chapter 8 Creating New Technologies 8 11 The Technology Creation Wizard The technology creation wizard generates a new technology from a few eT x simple parameters To start it E Technology Parameters This wizard creates a new technology from use the Technology numeric parameters provided by the Foundry Creation Wizard F Active Click on all of the panels listed on the left and command in menu Edit Poly filin the values Technology Editing The Gat wizard n s tof si Is Senin When done click Write XML to write ae ih i well Implant an z file that can be basse Electric with at describe various aspects Metal the Added Te
486. to add a single notSubcircuit annotation to cell B sch or B lay to tell NCC to never treat the cell as a hierarchical entity When hierarchical NCC encounters a notSubcircuit annotation it prints a message that includes the comment in a manner similar to skipNCC The notSubcircuit annotation only affects hierarchical NCC it is ignored by flat NCC The notSubcircuit annotation is created by the Not a Subcircuit command and may be placed on any schematic or layout cell in the cell group In general it is preferable to place the annotation on the schematic cell because it s more visible to the designer joinGroup lt cell name gt Memberships in cell groups is important when NCC performs hierarchical comparisons because NCC assumes that cells in the same cell group are supposed to be topologically equivalent Occasionally it is impractical to place the layout and schematic views of a cell in the same cell group For example when layout is automatically generated from hand drawn schematics it may be better to place the layout in a different library than the schematics The designer should use the Join Group command to add a joinGroup annotation to a cell if NCC should behave as if that cell belongs to a different cell group which may be in a different library The cell group to move the cell to is the cell group that contains the cell named in the annotation That specification should be fully qualified library cell view transistorTy
487. tory of This Cell command or use the Show History of This Cell context menu when clicking on a cell name in the cell explorer Besides showing the history of changes you can use this dialog to retrieve an earlier version of the cell Examine the History of cell test lay Ed version Date who Comments oo 8 Not In Repository Yet strubin CHECKED OUT 7 Wed May 18 2005 09 46 44 strubin Adjust export locations 6 Wed May 18 2005 09 44 20 _ strubin Adjusted aspect ratio 5 Tue May 17 2005 23 05 55 strubin Fixed DRC bugs 4 Tue May 17 2005 20 43 53 strubin Compaction 3 2 1 Tue May 17 2005 14 44 21 strubin Widened transistors Tue May 17 2005 12 42 32 strubin Added arcs Tue May 17 2005 12 40 09 strubin Initial checkin Retrieve Under the Hood The project management system makes use of version information on all cells to control cell changes When a cell is checked out a new version is made in your local library and the old version is deleted All instances of the old version are switched to the new version The old version remains in the repository When the cell is checked in that new version also goes into the repository When updates are done newer versions are obtained from the repository and appropriate substitutions are performed 180 Using the Electric VLSI Design System version 8 11 Chapter 6 Advanced Editing 6 13 CVS Project Management Electric imple
488. tric allows you to create multiple editing windows each of which can show a different cell You can also have the same cell in more than one window to see it at different scales and locations New windows are created by checking the appropriate checkbox in the New Cell or Edit Cell commands in menu Cell New windows can also be created from the cell explorer by using the context menu on a cell name All of the windows are listed at the bottom of the Window pulldown menu including the Messages Window To bring a window to the top for editing select its name from this list To cycle through the different Woo windows type q To delete a window click its close box or use the Close Window command in menu Window Note that you cannot delete the last window on systems where the pulldown menu is inside of each window because then the pulldown menus would become unavailable When there are many editing windows on the display you can arrange them neatly with the Window Adjust Position commands The Tile Horizontally command adjusts the windows so that they are full width but just tall enough to fill the screen one above the other The Tile Vertically command adjusts the windows so that they are full height but just wide enough to fill the screen one next to the other The Cascade command adjusts the windows so that they are all the same size and overlap each other uniformly from the upper left to the lower right Window Frame
489. ts like CF in an offpage symbol it is wired to something inside of the cell a global signal and it is also exported to the outside world In this example the schematic has power and ground signals but the power signal is also connected to a Global Partition node and exported as vddR The icon has an extra connection for this power tap In normal use the extra connections created by the Global Partition nodes are not wired up because they connect to globals and their connectivity is understood If however the extra exports are wired it means that the signal inside of the cell is disconnected from the global and connected instead to that wire In the example here two invR icons are placed but only one of them has its vddR connection wired to a different power source The subcircuit for the rightmost icon will not use the global power signal but will instead use the attached signal vddInv vddiny When writing a Spice netlist that makes use of Global Partitions you cannot use the GLOBAL block because it will prevent the overriding of signals You must set the Globals field in Spice Preferences to Create SUBCKT ports see Section 9 4 3 Using the Electric VLSI Design System version 8 11 169 Chapter 6 Advanced Editing 6 10 Outlines 6 10 1 Introduction Metal 1 Node For some primitive nodes it is not enough to rotate mirror and scale These eee primitives can to be au
490. ts that touch on the screen may or may not be truly connected Electric has many tools to ensure that the connectivity has been properly constructed The way that Electric handles all types of circuit design is by viewing it as a Nodes collection of nodes and arcs woven into a network The nodes are electrical components such as transistors contacts and logic gates Arcs are simply wires that connect two components Ports are the connection sites on nodes where the wires connect In the above example the transistor node on the left has three pieces of geometry on different layers polysilicon active and well This node can be scaled rotated and otherwise manipulated without concern for specific layer sizes This is because rules for drawing the node have been coded in a technology which describes nodes and arcs in terms of specific layers Ares Because Electric uses nodes and arcs for design it is important that they be used to make all of the relevant connections Although layout may appear to be connected when two components touch a wire must still be used to indicate the connectivity to Electric This requires a bit more effort when designing a circuit but that effort is paid back in the many ways that Electric understands your circuit Besides creating meaningful electrical networks arcs which form wires in Electric can also hold constraints A constraint helps to control geometric changes for example the rigid constraint
491. tter view however you can no longer change the circuit The 3D View is based on Java3D the Java interface for interactive 3D graphics Because not everyone has a full 3D capability on their computer the 3D facilities are dependent on these extra plugins e Java3D is the core 3D package and must be installed e 3D axes is an optional extra download from Static Free Software that shows a 3D axis e JMF is an optional package from Sun Microsystems that enables animation e Animation is an optional extra download from Static Free Software that does animation it needs JMF lc See Section 1 5 for details about getting these extensions To see the 3D view of a layout cell use the 3D View command in menu Window 3D Window The cell is displayed in 3D and mouse movements will rotate pan or zoom the circuit Use the left button to rotate the right button for panning and the middle one for zooming When zooming drag the middle button in one direction to zoom in and the other direction to zoom out Standard pan and zoom operations in menu Window are also available see Section 4 4 1 and Section 4 4 2 Each layer of a node or arc is drawn as a separate object in the 3D view If you click on a node or arc in a 2D view all of its layers will be highlighted in the 3D view Conversely clicking on any layer of a node or arc in the 3D view will show the entire component in the 2D view Using the Electric VLSI Desig
492. ursor makes the window shift so that the current cursor location is in the center of the window Note that this command is useful only when bound to a keystroke because you cannot issue the command and have a valid cursor location at the same time e Match Other Window in X redraws the current window so that it has the same horizontal pan as the other If there are more than two windows you will be asked to select the window to match e Match Other Window in Y redraws the current window so that it has the same vertical pan as the other If there are more than two windows you will be asked to select the window to match e Match Other Window in X Y and Scale redraws the current window so that it has the same zoom and pan as the other If there are more than two windows you will be asked to select the window to match One final command is useful if the display appears incorrect If this happens redraw the screen with the Redisplay Window command in menu Window 98 Using the Electric VLSI Design System version 8 11 Chapter 4 Display 4 4 3 Focus A particular scale and pan in a window is called a focus Each time you zoom in or out the focus is saved in a list You can move back through the list and show the last focus with the Go To Previous Focus command in menu Windows You can move forward in the list with the Go To Next Focus command JID Set Focus The Set Focus command in menu Window lets you type specific pan and
493. us Error commands in menu Edit Selection or type the gt and lt keys To force an error to be shown in the current window instead of popping up a new window for each cell use Show Next Error same Window and Show Previous Error same Window the and keys You can also force all errors to display in the same window by unchecking Show cell results in new window in the Display Preferences see Section 4 3 If an error involves multiple objects use Show Single Geometry the key to cycle through them individually Use Show Current Collection of Errors to highlight all errors A number of common tool _ Categories General USER Preferences controls are available from the General 1 0 General Preferences in menu MV Show file selection dialog before writing netlists File Preferences General Selection Current Directory by type section General tab si Bindings Type Database O gt A odes especially in the I O and Arcs Current C DevelE Electric TESTLIBS Jobs section Project Management New C DevelE Electric TESTLIBS CyS Most of the commands to Printing Reset generate an input deck for a 3 Jobs simulator a netlist prompt the Beep after long jobs verbose mode j a C Tools user for the desired file If Show C Technology Maximum errors to report lo 0 For infinite file selection dialog before Maximum undo history fso writing netlists is unchecked Logfile Options however
494. use it is not possible to parameterize layout cells X XX S 2x3 Transistor 2x10 Transistor 2x10 Transistor width attribute 8 Node Properties xi Type N Transistor Scalable Name nmos 0 Width f x position E The scalable transistor on the left is 3 Length E position E wide and the other two are 10 wide f poo However the scalable transistor on the keel Mirror R TT Mirror U D right has the width set to 8 so it has ies Cancel OK shrunk C Expanded Unexpanded V Easy to Select Invisible Outside Cell If you get Object Properties on a sii i scalable transistor there are extra controls that let you choose to have fewer contacts Contacts Top amp Bottom normal spacing X 1 or even none and you can tighten the Ports C Parameters Bus Members on Port contact spacing Port n trans sca poly left connects to Polysilicon 1 Port n trans sca diff top connects to N Active Metal 1 Port n trans sca poly right connects to Polysilicon 1 Port n trans sca diff bottom connects to N Active Metal 1 I Locked See Color and Pattern Edit Parameters Using the Electric VLSI Design System version 8 11 203 Chapter 7 Technologies 7 5 Schematics 7 5 1 Introduction Black Box And Nand Exclusive Or Or Nor The Schematic technology allows you to design using digital and analog schematic components To obtain this technology use the popup menu at the top of
495. ut t delta 3 0e 9 i inl H in2 H o output L t delta 1 0e 9 i inl L o output H i in2 L o output H This example shows that when both inputs are high the output will go low after a delay of 3 0 nanoseconds and that if either input is low the output will go high after a delay of 1 0 nanosecond The Delta Timing Distribution of the t Statement The Delta timing distribution is used to specify a fixed non random delay The format of a delta timing declaration is shown below Format delta value Example delta 1 0 delta 2 5e 9 The value associated with the delta declaration represents the fixed time delay in seconds 1 0 1 second 2 5e 9 2 5 nanoseconds etc 290 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools The Linear Timing Distribution of the t Statement The Linear timing distribution is used to specify a random delay period that has a uniform probability distribution The format of a linear timing declaration is shown below Format linear value Example linear 1 0 linear 2 0e 9 The value associated with the linear declaration represents the average delay time in seconds for the uniform distribution This means that there is an equally likely chance that the delay time will lie anywhere between the bounds of 0 and 2 times the value specified The Random Probability Function of the t Statement The random probability function enables the user to model things whic
496. vCTLnisch invCTLp ic invCTLp sch invHT ic invHT sch invK ic invK sch invLT ic invLT sch inv_passgate ic inv_passgate sch invidoc inv ic gt Copy gt Delete after copy Copy subcells V Use existing subcells Copy all related views By choosing one or more cells in the right hand library and clicking lt lt Copy those cells are copied into the left hand library The Copy gt gt button does the reverse If Delete after copy is checked the buttons change to lt lt Move and Move gt gt Using the Electric VLSI Design System version 8 11 85 Chapter 3 Hierarchy The system can be requested to copy additional cells that relate to the selected one By checking Copy subcells all subcells of the copied cell are also transferred By checking Copy all related views all related views icon schematic layout etc are also transferred Note that if Copy all related views is off but you want to Copy subcells it still copies related views in a limited fashion i e schematics and icons are copied together When there is a reference to an instance inside of a copied cell and that instance already exists in the destination library there are many ways to handle the transfer For example library Frank has cell A which has inside of it an instance of cell B B is also in library Frank You want to copy cell A to library Tom but there is already a cell called B in
497. ve Poly Gate Contact Well Implant Metal Via Antenna Load Parameters Write XML Save Parameters eeeeee ee Using the Electric VLSI Design System version 8 11 Normal Pin Text p b p roy gt pp NPlus fo p p Pus fo fo fo o Nwel PD pP fo Contacto po po Marking 0 fo fo Metal ifo pP fo viet fo of pP Meta 2f0 pP fo Load Parameters Write XML Save Parameters The GDS panel lets you specify GDS layer numbers for all layers Note that the Metal panel should be completed before filling in this panel so that the proper number of metal layers is shown 257 Chapter 8 Creating New Technologies 258 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools 9 1 Introduction There are many different tools available in Electric for doing both synthesis and analysis of circuitry Synthesis tools include routers compactors circuit generators and so on Analysis tools include design rule checkers network comparison and many simulators To see a list of tools including which ones are active use the List Tools command in menu Tools This chapter covers many of the tools available in Electric When a tool is running it may take a long time You can see it under the JOBS entry of the cell explorer see Section 4 5 2 After a tool has run it may report errors in the ERRORS section of the cell explorer To browse these errors use the Show Next Error and Show Previo
498. version 8 11 293 Chapter 9 Tools 9 5 5 ALS Functions The function entity is an alternate method of specifying behavior It makes reference to a Java method that has been compiled into Electric Because there are only a limited number of these methods and because the source code isn t always easy to update the function entity is of limited use However the facility is very powerful and can be used to efficiently model complex circuits It permits the designer to work at higher levels of abstraction so that the overall system can be conceived before the low level circuitry is designed Examples of this include arithmetic logic units RAM ROM and other circuitry which is easier to describe in terms of a software algorithm than a gate level hardware description To add a function to the simulator edit the module com sun electric tool simulation als UserCom java The function entity is headed by a function declaration statement that gives a name and a list of exports which are referenced in a higher level model description The format of this statement is shown below Format function name signall signal2 signal3 signalN Example function JK_FF ck j k out function DFFLOP data_in clk data_out function BUS_TO_STATE b7 b6 b5 b4 b3 b2 b1 b0 output function STATE_TO_BUS input b7 b6 b5 b4 b3 b2 b1 b0 The name refers to a Java method which will find the signal parameters in the same order that they appear in the argument list
499. w versions of cells when the names conflict producing a library that has both the previous and new contents in it 80 Using the Electric VLSI Design System version 8 11 Chapter 3 Hierarchy 3 9 3 Writing Libraries Writing libraries to disk is done with the Save Library command in menu File m The Save All Libraries command writes all libraries that have changed You can also use the fd save libraries icon from the tool bar To force all libraries to be saved use the Mark All Libraries for Saving command or use Save All Libraries in Format to specify how they are to be saved If a library was read from disk it is written back to the same file If however you wish to write the Categories Library USER Preferences library to a new file thus preserving the original General then use the Save Library As command Display 3 6 1 0 CIF GDS EDIF DEF CDL DXF The Library Preferences in menu File Preferences I O section Library tab offers options for writing libraries to disk By default saved libraries overwrite the previous files and no backup is created If you choose Backup of last library file then the former library is renamed so that it has a at the end If you choose Backup history of library files then the former library is renamed so that it has its creation date as part of its name C Backup history of library Files Export Import Reset Reset All Only resets USER Prefe
500. which has two controls I Use ASSIGN Construct Default wire is Trireg e Use ASSIGN Construct lets you choose whether or not to use the Verilog assign construct e Default wire is Trireg lets you control the type of Verilog declaration that will be used for wires wire by default trireg if checked Note that this can be overridden with the Set Verilog Wire command in menu Tools Simulation Verilog Another property that can be assigned to transistors is their strength The Weak command in menu Tools Simulation Verilog Transistor Strength sets the transistor to be weak The Normal command restores the transistor to be normal strength Using the Electric VLSI Design System version 8 11 271 Chapter 9 Tools Still more control of Verilog deck generation is accomplished with the Verilog User Preferences in the right side of the dialog e Run Placement after import requests that the Placement tool be used to organize components after reading Verilog see Section 9 13 for more on Placement e Do not netlist Standard Cells writes a netlist that excludes Standard Cells Any cell marked as a Standard Cell will be netlisted only as instances but no module definition will be written This allows Standard Cell based simulation or Static Timing Analysis to be performed on the netlist See Section 3 7 3 for more on marking cells as standard cells e Preserve Verilog formatting keeps the indent
501. which placement algorithm is being used These are the possible placement algorithms e Simulated Annealing 1 an experimental placer that uses Simulated Annealing to organized nodes e Simulated Annealing 2 an experimental placer that uses Simulated Annealing to organized nodes e Genetic 1 an experimental placer that uses a genetic algorithm to organized nodes e Genetic 2 an experimental placer that uses a genetic algorithm to organized nodes e Force Directed 1 an experimental placer that uses a force directed algorithm to organized nodes e Force Directed 2 an experimental placer that uses a force directed algorithm to organized nodes e Min Cut a simple placer that uses min cut to organize nodes e Random randomly places nodes in a line for test purposes only e Simple randomly places nodes in a square area for test purposes only Using the Electric VLSI Design System version 8 11 341 Chapter 9 Tools a Placement USER Preferences Antenna Rules Compaction Coverage DRC Fast Henry Logical Effort NCC Network Parasitic Placement Routing Silicon Compiler 342 Using the Electric VLSI Design System version 8 11 Chapter 10 The JELIB and DELIB File Format 10 1 Introduction This chapter describes Electric s native file format which ends in jelib These files contain an entire library of cells There are two earlier file formats which remain undocumented
502. with the node Thus when stretched horizontally or vertically there are two cuts and when stretched in both directions there are four cuts The technology editor will determine precise multicut rules from the cut spacing and the amount of stretch so that even more cuts will appear as the node grows larger The finished node definition is shown below All that is necessary is to convert this library back to a technology and the new technology will have this node cente f E Of course the newly created technology is valid only during the current session Therefore to preserve this technology write XML and add it to the Added Technologies Preferences cente Function contact Serpentine transistor No Square node No Invisible with 1 or 2 arcs No Lockable No Spice template 236 Using the Electric VLSI Design System version 8 11 Chapter 8 Creating New Technologies 8 10 Technology XML File Format Introduction Layout technologies in Electric can be described by Xml technology files These files are automatically generated by the technology editor and the technology creation wizard but some users may prefer to edit them by hand For these users the following is a description of the technology XML file format Electric currently has Xml technology files that are unparameterized all values are explicitly entered and there is no symbolic information Technology distances are specified as double precision numbers in disp
503. wn here illustrates some of these facilities This example is available in the Samples library as cell tool SimulateSpice you can read the library with the Load Sample Cells Library command in menu Help InitialVotage 0 Pulse altage 3V DelayTime Ons All input values to Spice are controlled with special nodes found in the Spice component menu entry Note that the first time any Spice node is placed the library yoigo X NY ER NA of Spice parts is loaded into Electric so there may be a delay My own SPICE cards That get stuffed into the deck The Spice nodes described here are Electric s default set However additional sets can and have been written To choose another set use the Spice Preferences in menu File Preferences Tools section Spice tab Under the setting Spice primitive set choose another set A second set of nodes called SpicePartsS3 is tailored towards special Spice3 274 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools ACCurrent ACVoltage Ammeter In this example there is a 5 volt supply on the left It was created by using the Amp DC Voltage entry under Spice entry of the component menu Once placed the AnalysisAC text that reads Voltage 0V can be selected and modified either with Object AnalysisDC Properties or by double clicking on it The Pulse input signal on the right is AnalysisTransient CECS created with the Pulse
504. xample when simulating The Invisible arc attaches any two components but makes no electrical connection It is useful for constraining otherwise unrelated components The Unrouted arc makes arbitrary electrical connections like the universal arc but routers know to replace them with real geometry None of these arcs produce any actual geometry in IC descriptions but they make important conceptual connections Any existing arc in a normal technology can be converted to one of these three special arcs by using the Change command in menu Edit Using the Electric VLSI Design System version 8 11 215 Chapter 7 Technologies Special Nodes There are also special nodes in the Generic technology They are all available from the Misc entry of the component menu A special primitive called Cell Center defines the origin of any cell Once the node is placed its location is at 0 0 for the cell Since instances of the current cell use the origin as the anchor point for cursor based references the location of this node defines the anchor For example if you place this node in the upper right corner of a cell then creation commands place instances such that their upper right corner is at the cursor See Section 3 3 for more information on cell centers A special primitive called Essential Bounds defines an alternate boundary of any cell At least two of them must be placed in opposite corners although 4 can be place to mak
505. xt makes use of the cell so save it to disk and use the Pad Frame Generator command in menu Tools Generation specify library with pads place the top edge of pads celllibrary pads4u txt place PAD_corner lay place PAD_gnd lay gnd_in gnd create cell padframe place PAD_vdd lay mlm2 vdd cell padframe place the right edge of pads place this cell as the core rotate c core tool PadFrame place PAD_corner lay place PAD_in lay out pulse set the alignment of the pads place PAD_spacer lay with input and output export align PAD_in lay dvddL dvddR place the bottom edge of pads align PAD_out lay dvddL dvddR rotate c align PAD_vdd lay dvddL dvddR place PAD_corner lay align PAD_gnd lay dvddL dvddR place PAD_out lay in outl align PAD_corner lay dvddL dvddR place PAD_out lay in out2 align PAD_spacer lay dvddL dvddR place the left edge of pads rotate c place PAD_corner lay place PAD_in lay out inl place PAD_in lay out in2 322 Using the Electric VLSI Design System version 8 11 Chapter 9 Tools This file places 8 pads in a ring 2 on each side and also places corner pads for making bends The input pads connect to the 2 input ports al and a2 The output pads connect to the 3 output ports outl out2 and out3 The power and ground pads connect to the vdd and gnd ports PAD_out PAD_out ZZZ EZZ PADBADD DDD DDD DDD DDD DD SD DDD PADDADD DPADMD PADDADD
506. xtension r z Three pins lined up vertically All arcs are drawn so that their geometry extends beyond their i endpoints by one half of their width This property can be set or reset with a Unconnected pin the Toggle End Extension of Head Toggle End Extension of Tail and Toggle End Extension of Both Head Tail commands in menu Edit Arc It may also be controlled by the Object Properties dialog in menu Edit Properties Using the Electric VLSI Design System version 8 11 139 Chapter 5 Arcs 5 4 4 Naming Another property of an arc is its name This is a character string that is displayed on the arc and used to name the electrical network connected to that arc The Name field in the Object Properties dialog allows you to specify this property which is then displayed on the arc See Section 6 8 4 for smart arc name control All arcs are named in Electric so if you don t give it a name one will be assigned These names which typically take the form object number are temporary names and are distinguished from the names given by the user Temporary names are not displayed on the arcs but user defined names are Note that creating exports is another way of naming a network See Section 6 9 2 for more on network naming Arc names can be quite complex when applied to busses The names can be indexed aggregated and otherwise be used to describe multiple signals See Section 6 9 3 for more on bus naming
507. y indicates that this cell helps to define a technology For more on the technology editor see Section 8 1 The check box Expand new instances of this cell indicates whether newly created instances of this cell are expanded contents visible or unexpanded drawn with a black outline See Section 3 4 for more on expansion For the first 5 checkboxes in this dialog there are buttons on the right which allow you to set or clear these flags for all cells in the library Each cell is tied to a specific technology The cell s technology is set when the cell is created You can change the technology that is associated with a cell by using the Technology popup The section labeled For Textual Cells lets you set the font and size of the text in that cell see Section 4 9 At the bottom is the cell frame control The frame is a border that is usually drawn around schematics You can set the frame size whether it is wider Landscape mode or taller Portrait mode and whether a title box is drawn in the corner Additionally you can set the designer name to be drawn for each cell Other information in the title box company name project name are set on a per user or per library basis with the Frame Preferences in menu File Preferences Display section Frame tab See Section 7 5 2 for more on frames 76 Using the Electric VLSI Design System version 8 11 Chapter 3 Hierarchy 3 8 Rearranging Cell Hierarchy In ord
508. y the technology editor translates the library back into a new technology REE LIBRARIES E cmos Current TECHNOLOGY LAYERS layer Metal layer Polysilicon layer Diffusion layer Contact Cut layer Transistor layer Pseudo Metal layer Pseudo Polysilicon layer Pseudo Diffusion 9 TECHNOLOGY ARCS arc Metal arc Polysilicon arc Diffusion amp y TECHNOLOGY NODES Libraries which describe a technology are called technology libraries They use elements from the Artwork technology to describe their information Special commands from the Edit Technology Editing menu aid in the manipulation of these libraries There are four types of cells in a technology library which describe the layers arcs nodes and support They are separated into these groups in the cell explorer The layer cells all begin with the name layer and each one defines a layer in the technology For example the cell called layer Metal defines the metal layer The node and arc cells correspond to the primitives in the technology Their names always begin with node and arc The support cell is always called factors Any other cell in the library is ignored e eee886 88068 6 node Metal Pin node Polysilicon Pin node Diffusion Pin node Metal Polysilicon Con node Metal Diffusion Con node Metal Node node Polysilicon Node node Diffusion Node node Cut Node node N Tran
509. y of the following letters sorted alphabetically with the numeric part at the end A if the arc instance is hard to select B if the arc instance has an arrow line on the body use X and Y for arrow heads F if the arc instance is NOT fixed angle fixed angle is more common G if the arc instance has its head connection negated I if the arc instance has its head NOT extended J if the arc instance has its tail NOT extended N if the arc instance has its tail connection negated R if the arc instance is rigid S if the arc instance is slidable X if the arc instance has an arrow on the head use B for an arrow body Y if the arc instance has an arrow on the tail use B for an arrow body Num Any digits at the end are the angle of the arc in tenths of a degree Examples AMetal 1 net 0 1 S1800 contact 0 10 10 pin 0 20 10 Places a metal 1 arc from the technology of the cell The arc is named net O is 1 wider than standard slidable and at a 180 degree angle The arc runs from 10 10 on node contact 0 to 20 10 on node pin 0 Aschematic bus net 161 IJ2700 busHat 4 s 1 8 42 14 conn 15 y 42 25 Places a bus arc from schematic named net 161 standard width not end extended on either end at 270 degrees angle The bus runs from 42 14 on node busHat 4 port s 1 8 to 42 25 on node conn 15 port y 10 3 4 Exports Inside of a cell definition exports are
510. yer types n For example you can double click the function entry many times selecting Diffusion p type and heavy to indicate a Diffusion layer that is heavily doped p type To clear the layer function set it to unknown A number of rules apply to the selection of layer functions There must be a pseudo layer for every layer used to build arcs This is because every arc needs a pin and pins are constructed from pseudo layers The pseudo layers are virtual geometry that do not appear in the fabrication output It is important that every pseudo layer have an associated real layer with similar descriptive fields The technology editor will issue a warning if pins are not constructed from pseudo layers Note that the layer functions must be treated carefully as they form the basis of subsequent arc and node definitions One consideration to note is the use of Wells and Substrates If the technology requires a separate contact to the well then it will typically contain a metal layer and a piece of heavily doped material under the metal to make ohmic contact to the well i e p in a P well This will have the same doping as the well unlike a device diffusion which is of opposite type to the well in which it is located Two rules apply here 1 There must be a separate diffusion layer for the p or n used as a contact in a P well or N well respectively it cannot be the same layer that is used for diffusions
511. you name an arc see Section 6 8 1 Arc names are only displayed on the arc if they less Apy o Cancel have been explicitly typed into this dialog You can also I Rigid E th ends E use the Props button to show a dialog that controls all aspects of a displayed arc name V Fixed angle Directionality None v V Slidable Negation None The Easy to Select checkbox enables selection of the arc F j i List Shows Attributes with a simple click see Section 2 1 5 PRESTON EDICT OTIOETE Many pieces of state can be changed here including Rigid and Fixed angle see Section 5 2 1 Slidable see Section 5 2 2 Directionality see Section 5 4 1 Ends extension see Section 5 4 3 and Negation see Section 5 4 2 When an Artwork arc has been selected see Section 7 6 1 the Color and Pattern button is available for setting its color Using the Electric VLSI Design System version 8 11 57 Chapter 2 Basic Editing 2 6 Changing Orientation There are two commands that can be used to change the orientation of circuitry The Rotate command in menu Edit has a submenu that allows the currently highlighted objects to rotate in any of three Manhattan directions or by an arbitrary amount The Mirror command in menu Edit has a submenu that allows you to flip the currently highlighted objects about their vertical centerline left right mirroring or their horizontal centerline up down mirroring
512. you select the desired via Note that the Metal panel should be completed before filling in this panel so that the proper number of via layers is shown The Rule Name fields let you describe the rule so that the Which via fi to2 design rule checker can report Distance Rule Name error names Via size A fo Via inline spacing B fo Via array spacing C fo Load Parameters Write XML Via inline overhang 0 0 Save Parameters Distances are in nanometers Il eee 8888 256 Using the Electric VLSI Design System version 8 11 The Antenna panel lets you specify antenna ratios for all layers Note that the Metal panel should be completed before filling in this panel so that the proper number of metal layers is shown The values here are the maximum ratio of polysilicon and metal layers to the area of connected transistors For example if the Metal 1 ratio is 200 then it is an error to have Metal 1 connected to transistors if the area of the Metal 1 is more than 200 times the area of the transistors Chapter 8 Creating New Technologies Technology Creation Wizard x Technology Parameters General Active Poly Gate Contact Antenna Ratios bd ee Poly ratio fo Meta Via Metal 1 ratio 0 0 Metal 2 ratio 0 0 See Section 9 3 2 for more on antenna ratio checking Technology Creation Wizard Eg Technology Parameters General Acti

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