ModelSim 6.4 Quick Guide
Contents
1. vopt automatically novopt Disables automatic vopt run voptargs lt args gt Arguments to pass to vopt view lt filename gt Log file for VSIM to view wlf lt filename gt Log file to create lt libname gt lt design_unit gt Configuration Module Entity Arch or optimized design to simulate Specify WLF reader cache size per WLF file Specify the number of Megabytes to be saved in event log file wlftlim lt duration gt Specify the duration of time to be saved in event log file wlfcachesize wlfslim lt size gt Code Coverage Key Arguments to vcom vlog cover bcefsx Specifies coverage type s Key Arguments to vsim coverage Enables statistics collection Key Arguments to vopt cover bcefsx Specifies coverage type s nocover Disable coverage on all source files Wave Window add wave lt item gt add wave add wave r add wave abus 31 15 Wave specific signals nets Wave signals nets in scope Wave all signals nets in design Wave a slice of a bus view wave Display wave window view wave new Display additional wave window write wave Print wave window to file lt left mouse button gt lt middle mouse button gt Zoom options lt right mouse button gt Context Menu lt ctrl f gt Find next item lt tab gt go right Search forward for next edge lt shift tab gt go left Search backward for next edge ior oor Zoom in Zoom out fl Zoom full Zoom Last Select signal Pl2. HTML report of code coverage from a ucdb file RED text ModelSim SE only www mentor com training_and_services TRAINING www model com products PRODUCTS ModelSim 6 4 Quick Guide Key Command Arguments Use lt commands help for a full list QVERILOG The qverilog command compiles optimizes and simulates Verilog and SystemVerilog designs in a single step akOoN automatic work library creation support for all standard vlog arguments support for C C files via the SystemVerilog DPI implicit run all quit unless using i gui do see R below vopt performance invoked see the vopt section of this guide Key arguments to qverilog lt filename gt required R lt sim_options gt SCCOM link CPP option g vv scv lt filename s gt VCOM 2002 93 87 check_synthesis debugVA explicit help f lt filename gt norangecheck nodebug novitalcheck nowarn lt gt quiet refresh version work lt libname gt lt filename s gt VLOG vlog95compat compat f lt filename gt hazards help nodebug quiet R lt simargs gt refresh sv version v lt library_file gt work lt libname gt lt filename s gt VOPT Verilog source code file to compile one is vsim command options applied to simulation Links source code required C compiler option Compile with debugging info Echo
3. Quick Guide ModelSim 6 4 www support model com SUPPORT ModelSim 6 4 Quick Guide Key Commands add memory opens the specified memory in the MDI frame of the Main window add testbrowser adds ucdb files to the Test Management Browser add watch adds signals or variables to the Watch window add wave adds VHDL signals and variables and Verilog nets and registers to the Wave window alias E a new Tcl procedure that evaluates the specified commands change modifies the value of a VHDL variable or Verilog register variable checkpoint saves the state of your simulation compare add compares signals in a reference design against signals in a test design configure invokes the List or Wave widget configure command for the current default List or Wave window COVERAGE coverage attribute displays attributes in the currently loaded database coverage clear clears all coverage data obtained during previous run commands coverage diff reports the coverage differences between two test runs coverage file sets the name of the coverage data file to be automatically saved at the end of simulation coverage goal Sets the value of UCDB wide goals coverage ranktest ranks coverage data according to user specified tests coverage report produces a textual output of the coverage statistics that have been gathered up to this point coverage summaryinfo prints coverage numbers of the specified coverage types without
4. ace cursor Key modelsim ini variables WLF Waveform management variables WLFCacheSize Change default or disable WLF file cache RED text ModelSim SE only Phone 503 685 0820 Toll free 877 744 6699 Fax 503 685 0910 Copyright 2008 Mentor Graphics Corporation 1026660 8005 SW Boeckman Road Wilsonville OR 97070
5. changes one or more properties of the specified signal net or register in the List Window property wave changes one or more properties of the specified signal net or register in the Wave Window pwd displays the current directory path in the Main window qverilog compiles optimizes and simulates a Verilog or SystemVerilog design in one step radix specifies the default radix to be used report displays the value of all simulator control variables or the value of any simulator state variables relevant to the current simulation restart reloads the design elements and resets the simulation time to zero restore restores the state of a simulation that was saved with a checkpoint command during the current invocation of vsim resume resumes execution of a macro file after a pause command or a breakpoint right searches right next for signal transitions or values in the specified Wave window run advances the simulation by the specified number of timesteps sccom compiles SystemC design units sdfcom compiles SDF files search searches the specified window for one or more objects matching the specified pattern s seetime scrolls the List or Wave window to make the specified time visible ucdb2html converts a ucdb file into HTML ved dumpports creates a VCD file that captures port driver data ved2wif translates VCD files into WLF files vcom compiles VHDL design units vcover attribute displays attributes in
6. el design unit acc lt spec gt lt module gt Enable design object visibility cover bcefsx Specifies coverage type s nocover Disable coverage on all source files g Assigns a value to generics and parameters with no value G Forces value assignment for generics and parameters Key arguments to vsim vopt Run vopt if not automatically invoked voptargs lt args gt Arguments passed to vopt use acc args for design visibility modelsim ini variable VoptFlow 1 Set vopt optimized flow as default VoptFlow 0 Set non optimized flow as default VSIM c Run in cmd line mode coverage Invoke Code Coverage do cmd lt file gt Run cmd or file at startup elab Create elaboration file f lt filename gt Pass in args from file g G lt name value gt Set VHDL Generic values hazards Enable hazard checking help Display vsim syntax help I lt logfile gt Save transcript to log file load_elab Simulate an elaboration file notimingchecks Disable timing checks quiet Disable loading messages restore lt filename gt Restore a simulation sdf min typ max lt region gt lt sdffile gt Apply SDF timing data e g sdfmin top MySDF txt sdfnowarn Disable SDF warnings t lt mult gt lt unit gt Time resolution vedstim lt instance gt lt filename gt Stimulate the top level design or instances from an Extended VCD file version Returns vsim version vopt Run
7. loading the entire database coverage tag adds or removes tags from specified objects coverage testnames displays test names in the current UCDB file loaded delete removes objects from either the List or Wave window do executes commands contained in a macro file drivers displays in the Main window the current value and scheduled future values for all the drivers of a specified VHDL signal or Verilog net dumplog64 dumps the contents of the vsim wlf file in a readable format echo displays a specified message in the Main window edit invokes the editor specified by the EDITOR environment variable environment displays or changes the current dataset and region environment examine examines one or more objects and displays current values or the values at a specified previous time in the Main window find displays the full pathnames of all objects in the design whose names maich the name specification you provide orce applies stimulus to VHDL signals and Verilog nets history lists the commands executed during the current session next continues a search see the search command noforce removes the effect of any active force commands on the selected object notepad opens a simple text editor printenv echoes to the Main window the current names and values of all environment variables profile on enables runtime profiling of where your simulation is spending its time and where memory is allocated property list
8. subprocess invocations on stdout Includes SystemC verification library SystemC files to be compiled Choose VHDL 2002 1993 or 1987 Turn on synthesis checker Print VITAL opt status Resolve ambiguous overloads Display vcom syntax help Pass in arguments from file Disable run time range checks Hide internal variables amp structure Disable VITAL95 checking Disable individual warning msg Disable loading messages Regenerate library image Returns vcom version Specify work library VHDL file s to be compiled Disable Verilog 2001 keywords Disable event order optimizations Pass in arguments from file Enable run time hazard checking Display vlog syntax help Hide internal variables amp structure Disable loading messages Invoke VSIM after compile Regenerate lib to current version Enables SystemVerilog keywords Returns vlog version Specify Verilog source library Specify work library Verilog file s to be compiled Design optimization options 1 The VoptFlow modelsim ini variable below sets the default design optimization on 1 or off 0 2 Optimized designs simulate faster while non optimized designs provide object visibility for debugging 3 Use acc with vopt or vsim voptargs with acc for selective design object visibility during debugging 4 Read Optimizing Designs with vopt in the User s Manual for additional information Key arguments to vopt o lt name gt Optimized design name lt design gt Top lev
9. the currently loaded database vcover merge merges multiple code coverage data files offline vcover ranktest ranks the specified input files according to their contribution to cumulative coverage vcover report reports on multiple code coverage data files offline vcover stats produces summary statistics from multiple coverage data files vcover testnames deplays test names in the current UCDB file loaded vde deletes a design unit from a specified library vdir lists the contents of a design library verror prints a detailed description of a message number vgencomp writes a Verilog module s equivalent VHDL component declaration to standard output view opens a QuestaSim window and brings it to the front of the display vli creates a design library vlog compiles Verilog design units and SystemVerilog extensions vmake creates a makefile that can be used to reconstruct the specified library vmap defines a mapping between a logical library name and a directory vopt produces an optimized version of your design vsim loads a new design into the simulator when instructs QuestaSim to perform actions when the specified conditions are met where displays information about the system environment wlf2log translates a QuestaSim WLF file to a QuickSim II logfile wlf2vcd translates a QuestaSim WLF file to a VCD file wlfman outputs information about or a new WLF file from an existing WLF file xml2ucdb creates an
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