VME Interface VC16 User Manual - W-IE-NE
Contents
1. void cam_irg void put_reg badr2 12 a AC spore spo k aa Ok ok kok kok kok 2 void cam noirq void put reg badr2 13 a ek e k AC k FAC k ohe k oh k ok ok FA FA FA ie oh le oh le ak Ok kok kok kok 2 ek K void cam nfa int n int f int a nfa a lt lt 5 nfa nfa l f lt lt 5 nfa nfa l n 0x8000 put reg badr2 0 put reg badr4 nfa b REOR So o oh o oh o oh o k ek o k ak En ok AC ok bek ek K gore goi spore spo spo spo spo spo eh FA K SK 3 K SK ok le ok 3K ok Sk ok he ok he ok he ok lek ek void cam nfa write int n int f int a unsigned int data nfa a lt lt 5 nfa nfa l f lt lt 5 nfa nfa n put reg badr2 0 put reg badr4 nfa put reg badr2 2 put reg badr4 data b REOR k sk o oh seo eh ek a ok ak ok e ok aK k bek ek ek oie gore spore spo spo spo spo spo FA eh K oh ie oh SK oh ie ok aK ok Sk ok FK ok lek e ok ek ek le void cam nfaqx write int n int f int a unsigned int data int q int x char j nfa a lt lt 5 nfa nfa l f lt lt 5 nfa nfa n put_reg badr2 0 put_reg badr4 nfa put reg badr2 2 16 VC 16 00211 A0 01 97 put reg badr4 data j get reg badr g j2. Z set SM9 BASE 2 set SM to enable Z set SM6 BASE 2 get SM to perform Z cycle Q and X response will be set to 1 as response of CC16 to the Z cycle CAMAC CLEAR C set SM8 BASE 2 set SM to enable C set SM6 BASE 2 set SM to perform C cycle Q and X response will be set to 1 as response of CC16 to the C cycle SET CAMAC INHIBIT I set SM10 BASE 2 set SM to enable I SET BACK CAMAC INHIBIT I set SM11 BASE 2 set SM to disable I The status of the inhibit line T is displayed at the CC16 front panel by the Inhibit LED 3 3 LAM servicing ENABLE IRQ ON LAM REQUEST set SM12 BASE 2 set SM to enable IRQ on LAM request DISABLE IRQ ON LAM REQUEST set SM13 BASE 2 set SM to disable IRQ on LAM request READ STATUS REGISTER SCB set SM7 BASE 2 set SM to CC16 status register read data BASE 6 read SCB bits see CC16 manual CC16 INITTALISATION The complete CC16 initialisation should include setting of crate branch and SCB as well as of giving Z cycle and checking for no setting of l line write Geo Addr register BASE 8 set crate branch set SM7 BASE 2 set SM to CC16 status register write SCB BASE4 4 write scb with bit2 0 switch crate on 3 4 Read and write data ACCESS AND DATA TRANSFER TO CAMAC MODULES The data transfer to or from modules of the CC16 controlled crate has to be done in two steps due to the 24 bit word length of the CAMAC bus First read or write the low
3. cam z FE o o o oh o oh eh eh ok ek ak ok he ok ek ek ek ek e k e k o e k ok k k ek ie oh FK oh eh ek le k 3K ok e ok he ok ek ek ek ek o e k o e k ohe k ohe kok K int getstatus void char j l 9 return j amp 7 h a ek AC k AS k FAS ak Ok kk kok kok kok K K void cam_z void put_reg badr2 11 put reg badr2 9 put reg badr2 6 y P P o o o oh o oh o k k ek ek be k bek ek ek ek ek e k e k ob k ok o ok o oh o oh ie oh eh le ok le ok K ok e ok he ok bek ek ek o e k o e k o e ok ohe ok ohe kok ke void cam c void put reg badr2 11 put reg badr2 8 put reg badr2 6 y a poe k AC spo spo spo spo aa Ok ok kok kok ok lek ole void cam i void put reg badr2 10 E P Pe o o o oh o oh eh o k ak ok ak ok ak ok ek ek ek ek e k e k obe k oh oh ek eh eh eh eh le k aK ok K ok he ok Sk aK ek ek ek o e k o e k ohe kok kok k void cam ci void put reg badr2 10 put reg badr2 8 put reg badr2 6 aa spo spo spo spo spo FA eh K oh ie oh Sk ok K ok 3K ok he ok K ok ek he ok lek ek ole int cam g void 15 VC 16 00211 A0 01 97 char j j get reg badr return gt gt 0 amp 1 REOR RE o oh o oh CF CH AG Ene k ek ek ek FAC spoke poe spo spo spo FA eh A int cam x void char j j get reg badr return j gt gt 5 amp 1
4. for VC16 rotary switches define cab delay 0x0 for VC16 cc16 link cable delay int main int nl fl al int q x long int data char inbuf 130 cam_controller_ini vc16_base nl 1 printf n W IE NE R CC16 VC16 DEMONSTRATION n printf n n n printf n NAF code operation demonstration N 0 to stop n printf n copyright Plein amp Baus GmbH Burscheid Germany VI 94 n n demonstration of clear inhibit and inizialise cam c cam 1 cam z set delay 0x0 demonstration of NAF read and write operations cam irq while nl l 0 printf n n printf n CAMAC station number N t gets inbuf sscanf inbuf t d amp n1 printf n CAMAC function number F X gets inbuf sscanf inbuf t d amp f1 printf n CAMAC subaddress A W gets inbuf sscanf inbuf t d kal printf n if f1 gt 8 printf data to write t gets inbuf sscanf inbuf t li amp data cam nfaqx write24 nl f1 al data amp q amp x printf t t t Q i X 96i q x 21 VC 16 00211 A0 01 97 else data cam_nfaqx_read24 nl fl al amp q amp x printf data li data printf t Q i X i n q x 22 VC 16 00211 A0 01 97 Software Licence Agreement Program VC16 libraries and test demonstration program OS 9 or
5. read data BASE S6 read data BASE S6 read data BASE S6 set SM to write NAF write NAF word with S bit 1 and start CAMAC cycle set SM to block read low word read low word 0 15 read low word 0 15 read low word 0 15 read low word 0 15 read low word 0 15 the last word has to be read again by the full sequence set SM3 BASE S2 read data BASE 6 set SM to read low word read low word 0 15 11 VC 16 00211 A0 01 97 3 5 CAMAC status bits Q and X The status bits Q and X are stored in the status register of the interface ISR in the first bits CSDO and CSD1 The O and X bits will be stable within 1 4us read ISR read ISR Q bit6 X bit 5 3 6 Cable delay correction The VC16 will serve for correct timing in case of cable lengths by strectching the VME bus cycles e g delaying the acknowledge time from the controllers connected The delay may be different for the 15 geographical addresses The several delay values are defined within bit 8 11 of the VC16 status register The following table gives examples for typical cable lengths delay times including CAMAC cycle xxxx 0000 xxxx xxxx xxxx 1001 xxxx xxxx Xxxx 0011 xxxx XXXX xxxx 0111 XXXX XXXX XXXX 1111 xxxx xxxx Table 9 Interface cable delay programming To fix the cable delay first select the geographical crate address Then the bits 8 11 of the statusregister has to be defined write Geo Addr reg BASE 8 set crate b
6. write D0 D7 BASE A Set Test Interrupt BASE C Table 3 VC16 address layout The Status register BASE 0 includes the VME interrupt levels the LAM and CP status as well as the cable delay information which is necessary for correct timing in a high speed data transfer with long distances between the CAMAC crates and the interface The bit assignment is given in the following table 10 1 1 cable delav 8 100m length Table 4 VC16 Status register bit assignment To test the correct connection between CAMAC crate and interface the VC16 is equipped with a read back mode register facility which can be red after a CP bus activity This feature can be used for troubleshooting in case of link fail functions The last called primary mode is stored in bit DO and D1 The next three bits show the type of the CP bus activity The detailed read back register pin assignment is given in the following table 7 VC 16 00211 A0 01 97 2 primary mode 2 Readbackvalue Table 5 CP bus read back bit description The primary modes of the CP bus protocol which are indicated by the first two bits are listed in the following table Table 6 CP bus primary modes 0 0 writeN E A and promptCAMAC cycle bit 6 6 je 9 9 enable CAMAC Z for next SM6 call O i B k l 3 D Table 7 CC16 Sub modes Via the 4 bits of the Mode register BASE 2 the different sub modes o
7. IBM PC version This software is copyrighted by W IE NE R Plein amp Baus GmbH All rights reserved Any duplication reproduction transfer or distribution of the software and the manual as well as of parts of them is not allowed without the express prior written consent of the publisher Disassembly of code is prohibited We do not make representations or warranties to the contents or use of the program and the software description Further we reserve the right to make changes to any and all parts of the software and the manual at any time without obligation to notify any person or entity of such changes W Ie Ne R Plein amp Baus GmbH M llersbaum 20 D 51399 Burscheid Germany Phone 49 0 2174 678 0 FAX 49 0 2174 678 555 E Mail info wiener d com URL http www wiener d com 23 VC 16 00211 A0 01 97
8. X cam lam get LAM source cam lamf any LAM request badr basic I O address copyright A Ruben W Ie Ne R PleinBaus GmbH 20 03 95 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLII CPU dependent register access has to be defined in unit reg acc h WA include reg_acc c unsigned int nfa unsigned long int badr unsigned long int badr2 unsigned long int badr4 unsigned long int badr6 unsigned long int badr8 unsigned long int badrA unsigned long int badrC 13 VC 16 00211 A0 01 97 void cam adr unsigned long int int cam cratecheck void void set crate int void set delay int void cam controller ini unsigned long int int getstatus void void cam z void void cam c void void cam i void void cam ci void void cam O void int cam q void int cam x void void cam irq void void cam noirq void void cam nfa int int int void cam nfa write int int int unsigned int void cam nfagx write int int int unsigned int int int void cam nfagx write24 int int int long int int int unsigned int cam nfa read int int int unsigned int cam nfaqx read int int int int int long int cam nfaqx read24 int int int int int P P o o o oh o oh o k ak ak ak ak ak ok bek bek ek ek ek e k e k be k ob k oh ek ek eh eh eh 3k K le k K ok le ok he ok ek ek ek o e k o e k o e k ohe ok ohe skok ke void cam ad
9. and middle byte as one 16 bit word The second cycle is for reading writing the high byte if 10 VC 16 00211 A0 01 97 required However a lot of CAMAC modules use only word length up to 16 bit In this case 16 bit data transfer is faster and more useful WRITE 24 BIT WORD set SM0 BASE S2 write NAFBASE S4 set SM1 BASE S2 write data BASE S4 set SM2 BASE S2 write data BASE S4 cycle WRITE 16 BIT WORD set SM0 BASE 2 write NAFBASE S4 set SM2 BASE S2 write data BASE S4 cycle READ 24 BIT WORD set SMO BASE S2 write NAFBASE S4 set SM3 BASE S2 read data BASE S6 set SM4 BASE S2 read data BASE S6 READ 16 BIT WORD set SMO BASE S2 write NAFBASE S4 set SM3 BASE 2 read data BASE 6 set SM to write NAF write NAF word with S bit 0 set SM to write high byte write high byte set SM to write low word write low word 0 15 and start CAMAC set SM to write NAF write NAF word with S bit 0 set SM to write low word write low word 0 15 and start CAMAC set SM to write NAF write NAF word with S bit 1 and start CAMAC cycle set SM to read low word read low word 0 15 set SM to read high byte read high byte set SM to write NAF write NAF word with S bit 1 and start CAMAC cycle set SM to read low word read low word 0 15 16 BIT FAST BLOCK TRANSFER READ set SMO BASE 2 write NAFBASE S4 set SM5 BASE S2 read data BASE S6 read data BASE S6
10. position Switch off the VME crate and insert the VC16 into an empty VME slot Connect the CC16 chain with the VC 16 by the 50 pin flat cable and switch on VME crate mains For correct operation the VC16 CC16 system has to be initialised first by setting the geographical address of the called controller Further the initial conditions for inhibit line I set off and IRO on LAM should be defined see next chapters At the end of initialisation a CAMAC initialise Z should be performed 6 VC 16 00211 A0 01 97 2 Register Lavout and operating modes The access to the CAMAC crate controller is performed according to the CP bus protocol via calls of several modes which are for selection of read write operation or special controller functions These modes are primarv modes PM defining the tvpe of operation and sub modes SM for the controller functions detailed description see CC16 Manual In opposite to the personal computer interface PC16 with the VME VC16 interface there is no more a direct access to the primarv modes The primarv mode selection is automaticallv done during sub mode write as well as write and read data bv using several registers Also for the geographical address load a single register is used The complete 14 byte register block is organised according to the following scheme DO DII BASE 0 Mode Register BASE 2 read write DO DI5 BASE 4 D0 D15 BASE 6 Geogr Address DO D7 BASE 8 read
11. request level IRQI IRQ7 is defined by the setting of the first three bits of the VC16 status register The 8 bit STATUS ID for the interrupt acknowledge cycle D08 O has to be load into the Vector register BASE A To test the interrupt function via the Test Interrupt register BASE C a software interrupt may be produced Note that for this operation the LAM enable bit in the status register must be set to true The interrupt reset is done by clearing the LAM enable bit 3 Programming and CAMAC operation The VC16 CC16 operation is performed on the basis of setting or reading the several VC16 registers which are described in chapter 2 The following instruction schemes are given in terms of setting these modes and registers and writing reading data Please consult the CC16 manual for the detailed CC16 functions 3 1 Call and set crate on off select crate write geographical address write Geo Addr register BASE4 8 setcrate branch Set crate on off set SM7 BASE 2 set SM to CC16 status register write SCB BASE 4 write scb with bit2 0 switch crate on bit2 1 switch crate off to test the setting read the SCB with read SCB BASE 8 read SCB with bit2 0 crate is on bit2 1 crate is off The crate ON OFF is displayed by a status LED at the front panel of the CC16 These ON OFF modes are only relevant for broadcast operations 9 VC 16 00211 A0 01 97 3 2 General CAMAC commands Z C I CAMAC INITIALISE
12. VME Interface VC16 User Manual 0 VC 16 00211 A0 01 97 CONTENT 1 VME CAMAC interface VC16 bn on entente enne nne 2 1 1 General description oem td en Leite eb Le eb 2 1 2 Front panel KE C 2 1 3 Interface description wer ee Rennen Rte pe tere eer eR ERR en End 3 1 4 VETO Installation i 22 3222 A herede DS tne eG sl 6 2 Register Layout and operating modes Nt 7 3 Programming and CAMAC operations Ne 9 3 1 Call and cr te 0n ft ax sit A ernennen 9 3 2 General CAMAC commands Z C Ne 10 3 3 LAM Servicing uite eR e ERR IRE ed Red A Nine 10 3 4 Read and Wte att nme en 10 3 5 CAMAE status bits Qand X ni nein en ent 11 3 6 Cable delay Corrections oett e ete e 12 3 7 Using Interrupts wi iksi re voe ere tee redet EE ne nte Ere qa eae tee ote 12 4 C Library and software examples ness nnsnens nases ns nst 13 APPENDIX Technical documentation De seen enne enne nennen A 14th January 1997 1 VC 16 00211 A0 01 97 1 VME CAMAC Interface VC16 1 1 General Description The VC16 is a single width 6U VME interface card for control of up to 15 CAMAC crates equipped with the W Ie Ne R CC16 CAMAC crate controller The link between the CAMAC crates and the interface is performed by a 16 bit parallel interface CP bus protocol with a high speed data transfer up to 1Mb s The cable length of the VC16 and CC16 link may be up to 200 metres twisted pair cable or up to 30m in case of standard f
13. ddress modifier for ATVME system jumper to AM 39 on VC16 board THHHHHHHHHHHHHHHE ELTEC 68X00 CPU System HH AM 39 by address offset ifdef ELTEC void put_reg unsigned long int regadr unsigned long int data regadr eltec_base short regadr data unsigned long int get_reg unsigned long int regadr regadr eltec_base return short regadr void vme init void endif THHEHHHHHHHHHHHHE CES FIC8232 CPU System HHHHHHHHHHHHHHT AM 39 by address offset ifdef CES void put_reg unsigned long int regadr unsigned long int data regadr cesfic_base short regadr data unsigned long int get_reg unsigned long int regadr regadr cesfic base 19 VC 16 00211 A0 01 97 return short regadr void vme init void endif THHHHHHHHHHHHHHHE PRO VME PC VME System THHHHHHBHHHHE ifdef ATVME include VMELIB C void put_reg unsigned long int regadr unsigned long int data WriteWordExt regadr data am unsigned long int get_reg unsigned long int regadr return ReadWordExt regadr am void vme_init void endif Init AT VMEO 20 VC 16 00211 A0 01 97 W Ie Ne R CC16 VC16 Test and Demonstration Version 1 1 revised 4 95 copyright WIENER Plein amp Baus GmbH 04 04 95 include lt stdio h gt include cam vc16 c define vcl6 base 0x800000
14. f the CAMAC crate controllers are called These sub modes SM which chooses the controller function for CAMAC access are defined as follows The Output Data register BASE 4 as well as the Input Data register BASE 6 with a length of 16 bit are for the data transfer from and to the connected CAMAC crate controllers for NAF code 16 bit word only output low data word 16 bit high data byte 8 bit 8 VC 16 00211 A0 01 97 As described in more detail in the CC16 Manual the NAF code includes the station number N of an addressed module the sub address A and the function number F It is decoded according to the following bit assignment ini v Ina Ins nis FI F2 ra rs to ar A2 At AS s Table 8 NAF code bits The last bit S corresponds to an immediate CAMAC cycle on a NAF load If this bit is 0 the NAF load in the CC16 will not cause a prompt CAMAC cycle S 0 is necessary write data to the dataway For read operations one has to set S 1 The Geographic Address register BASE 8 is for selecting the CAMAC crate for the following operations The chosen number defined by the first 4 bits 0 SE has to be equal to the value of the address switch on the CC16 front panel which has to be accessed The address F is used for broadcast operations to all connected controllers For test purposes the geographic address may be read back The VC16 is prepared for interrupt based LAM servicing The interrupt
15. gt gt 6 amp l x j gt gt 3 amp 1 y REOR k o oh k oh o oh o k ek ek ak ok le ok AC ok AE ok ek K goi poe spo spo spo spo spo spo FA eh oh ie oh Sk oh K ok 3K ok Sk ok K ok le ok lek ek lek void cam nfaqx write24 int n int f int a long int data int g int x char j int ih int il ih int data gt gt 16 amp 255 il int data nfa a lt lt 5 nfa nfa l f lt lt 5 nfa nfa n put reg badr2 0 put reg badr4 nfa put reg badr2 1 put reg badr4 ih put reg badr2 2 put reg badr4 il j get reg badr q j gt gt 6 amp l x j gt gt 5 amp 1 h REOR SE seo o oh o oh ak k k a AG ok AG ok 3K k ste egeret gore poe spo spo spo spo spore ak Ok kok kok kok 2 ole unsigned int cam nfa read int n int f int a nfa a lt lt 5 nfa nfa l f lt lt 5 nfa nfa l n 0x8000 put reg badr2 0 put reg badr4 nfa put reg badr2 3 return unsigned int get reg badr6 a aa Ok ok kok kok 2 KK ole unsigned int cam nfaqx read int n int f int a int q int x char j nfa a 5 nfa nfa f lt lt 5 nfa nfa n 0x8000 put reg badr2 0 put reg badr4 nfa put reg badr2 3 nfa unsigned int get reg badr6 put reg badr 3 nfa unsigned int get reg badr4 j get reg badr q j gt gt 6 amp 1 x j gt gt 5 amp 1 return nfa a ek bek ek AC k aa Ok ok kok kok kok 2 le 17 VC 16 00211 A0 01 97 long
16. int cam nfaqx read24 int n int f int a int q int x char j long int Ih nfa a lt lt 5 nfa nfa f lt lt 5 nfa nfa n 0x8000 put reg badr2 0 put reg badr4 nfa put reg badr2 4 Ih get reg badr6 amp 255 lh lh lt lt 16 put reg badr2 3 Ih get reg badr6 amp Oxffff j get reg badr g j gt gt 6 amp l x j gt gt 5 amp 1 return 1h nh REOR ro o oh o oh o oh eh o k ek ak oen tee ok ek ek ek ek ek ek AC spo spo spo spo spo FA FA K oh ie oh ek ek 3K ok Sk ok K ok he ok he ok ek ek ole int cam lam int station cam nfa station 8 0 return cam qO a AC k FAC k ohe k oh k ak Ok Ok kok kok kok 2 ole int cam_lamf void int j j get_reg badr return j amp 2 13 18 VC 16 00211 A0 01 97 reg acc c esee se eese se oe e ohe se see ohe se see oe K K K K K K K K K k K K oe K K K K ohe ohe K oe K K K K K K K K K K K K K K KK K K K K K K K K K K VME bus CPU register Access copyright W Ie Ne R PleinBaus GmbH A Ruben 20 12 94 LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLII void vme_init void void put reg unsigned long int unsigned long int unsigned long int get reg unsigned long int define vc16 base 0x800000 for VC16 rotary switches define eltec base Oxff000000 for ELTEC CPU AM 39 define cesfic base Oxf0000000 for CES FIC8232 CPU 16bit data AM 39 define am 0x39 A
17. lat cable The VME interface module VC16 will serve for correct timing in case of cable length gt 10 metres by stretching the VME cycles i e delaying the acknowledge time from the slave connected The VC16 is an A24 D16 VME bus slave The module supports the AM codes 39 and 3D The VC16 sub devices are addressed via 3 LSB address lines The basic address is complete decoded and switch selectable For LAM servicing one interrupt channel is installed The interrupt request level 1 7 may be software selected in the VC16 status register The VC16 interface supports the special features of the CC16 like broadcast and block mode operation with automatic CAMAC NAF code repeat Additional the VC16 is equipped with an internal CP bus cable delay correction and a CP bus test feature The data transfer from to the VME bus system has to be organised by an application program running on the VME CPU The different crates connected via the CC16 have 15 different geographic addresses and one broadcast address for parallel access For special applications every single crate may be enabled disabled for parallel download The VC 16 interface and the last CC16 controller in one chain have to be terminated to enable the correct function during the high speed data transfer 1 2 Front Panel Five status LED s are placed on the VC16 front panel to show ACCESS LAM pending LAM enable as well as write or mode operations of the CP bus protocol with the fo
18. llowing functions ACCESS lights if there is any access from the CPU LAM pending lights if there is a LAM request from the actual CAMAC crate LAM enable lights if the LAM interrupt line is enabled write CP lights if VC16 write to CP bus read mode CP lights if VC16 access to CP bus mode 2 VC 16 00211 A0 01 97 module access LAM pending IRQ on LAM enable write CP mode CP interface connetor CP bu Fig 1 CC16 front panel Below the status LED s the 50 pin connector for parallel link to the interface flat or twisted pair cable is mounted Please note that both interface VC16 and the last CC16 in a chain have to be terminated bv equal resistors see next chapter 1 3 Interface description For any operation the CAMAC crate controller CC16 has to be linked to an external interface which is driven bv a micro processor or computer The communication between the CC16 and the interface is performed according to the CP Communication bus Protocol RS422 developed by RWTH Aachen The CP bus consists of 16 bi directional data lines and 7 control lines used for geographical addressing of the installed CC16 as well as for control and data transfer strobes All signals are transferred as bipolar TTL signals Both the CC16 and the used interface have to be terminated to enable correct function during the high speed data transfer 3 VC 16 00211 A0 01 97 Fig 2 VC16 block diag
19. r unsigned long int bad badr bad badr2 badr 2 badr4 badr 4 badr6 badr 6 badr8 badr 8 badrA badr 10 badrC badr 12 int cam cratecheck void int j put reg badr8 0 put reg badr2 7 put reg badr4 0 j get reg badr6 J GRA 4 if j 0 j l return j nh P P o o o oh o oh eh k ak ok ak ok ak k ek ek ek ek e k be k he k o e k k k ok ek o oh eh eh ek le ok le ok le ok he ok ek ek ek ek o e k obe k ohe ok ohe kok K void set crate int crate put reg badr8 crate PE o o o oh o oh eh o k ek ak ok ak a ek ek ek ek ek e k o e k o e ok ek ek eh eh e oh e ok le ok K ok he ok he ok bek ek ek ek o e k o e k ohe kok skok ke 14 VC 16 00211 A0 01 97 void set delay int delay bits unsigned int i i get reg badr i i amp OxOff i i delay_bits lt lt 8 put_reg badr i P P o o o oh o oh k o k ok ek bek ek ek ek ek ek e k be k ob k k k ok o k o oh eh eh ek le k K ok le ok SK ok ek ek ek e k o e k o e k ohe ok ohe skok ke void cam controller ini unsigned long int bad vme_init cam_adr bad set crate 0
20. ram 4 VC 16 00211 A0 01 97 The crate controller termination is performed with resistor networks RN6 RN8 Two types of cable termination are provided DIL 220 Ohm 2 x SILS 1 x 1000hm Table 1 Termination resistor types factory prepared Both ends of the link i e CC16 and interface have to be terminated with equal resistors Note that in case of multi crate systems only the last CC16 in the chain has to be terminated Maximum tested distances between crate controller and interface are 30 metres in case of 50 pin flat cable or up to 200 metres using twisted pair cable The pin assignment of the 50 pin CP bus interface connector is given in the following table uy D0 jE DBS 00 D2 731 DIS O 08 1 33 GND 0 DH LAM Table 2 CP bus Interface connector pin assignment 5 VC 16 00211 A0 01 97 1 4 VC16 installation Prepare the VC16 before inserting into the 6U VME system i e check or select the register range by the hexadecimal switches S1 S5 according to the following scheme and example for BADR 800000 value 8 0 0 0 bin 0100 0000 0000 0000 0000 disableenable settling delay les AM 39 3D sie le s3 54 Further the address modifier 39 or 3D has to be chosen by jumper setting on the VC16 board The settling delay jumper should be in case of standard cable lengths up to 20 metres in the disabel
21. ranch write Status register BASE write status register 3 7 Using interrupts The VC16 is able to generate an interrupt on the VME bus after receiving a LAM request The interrupt level is defined within the VC16 status register i e bits 0 2 see table 4 The vector address is loaded into the VC16 vector register BASE A see table 3 For interrupt based LAM servicing first the VC16 has to be enabled for interrupt on LAM This is done by setting bit 3 of the VC16 status register to 1 To reset the LAM interrupt disable 1 e set bit 3 to O The interrupt servicing on the VME bus which is strongly CPU dependant has to be defined within the CAMAC control and read out software For testing the interrupt can be generated by writing any dummy value into the test interrupt register BASE C For interrupt programming see the VME CPU manual and programming language description 12 VC 16 00211 A0 01 97 4 C Librarv and software examples The following chapter describes the contents of the OS 9 software kit The included C code library for the VC16 CC16 is based on a general definition of the VME register access by the commands get reg address and put reg address data This access which depends on the chosen address modifier AM i e on the size of the address range 16bit 24bit 32bit as well as on the kind of operation supervisor data user is strongly CPU dependent Thus in the unit reg acc c the register access ope
22. rations get reg and put reg used in the cam vc16 c library has to be defined for the used VME bus master Programming examples are given for the ELTEC E7 E8 and the CES FIC8232 modules As an example for using the C library please find the test program vcl test c cam_vc16 c CC16 VC 16 C routines Unit contains cam_adr set I O address BADR getstatus get CC16 status cam cratecheck test crate available set crate set geographical crate address set delay set value for cable delay 4 bits cam controller ini controller initialization cam Z CAMAC Initialize Z cam c CAMAC Clear C cam i CAMAC Inhibit I cam ci CAMAC Clear Inhibit T setzen cam irq enable CAMAC LAM Interrupt cam noirq disable CAMAC LAM Interrupt cam q get CAMAC Q response cam x get CAMAC X response cam nfa set NE A start CAMAC cycle cam nfa read set N F A and read 2 byte cam nfaqx read set N F A and read 2 byte with Q and X cam nfaqx read24 set N F A and read 3 byte with Q and X cam nfa write set N E A and write 2 byte cam nfaqx write set N E A and write 2 byte with Q and X cam nfaqx write24 set N E A and write 2 byte with Q and
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