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Data Sheet - Mouser Electronics

1. CYPRESS PRELIMINARY Family Datasheet PERFORM The Field Values are listed in the following table Field Description Values Meaning CY8C Cypress Prefix 4 Architecture 4 PSoC 4 A Family within archi 1 4100 BLE Family tecture 2 4200 BLE Family B CPU Speed 2 24 MHz 4 48 MHz C Flash Capacity 7 128 KB DE Package Code FN WLCSP LQ QFN F Temperature Range Industrial XYZ Attributes Code 000 999 Code of feature set in specific family Packaging Table 55 Package Characteristics Parameter Description Conditions Min Typ Max Units Operating ambient temperature 40 25 00 85 Ty Operating junction temperature 40 100 Package 56 QFN 16 9 C watt Package 56 pin QFN 9 7 C watt TJA Package 0 4 68 ball WLCSP 16 6 C watt Package 68 ball WLCSP 0 19 C watt Table 56 Solder Reflow Peak Temperature Package IPSIS Maximum Time at Peak Temperature 56 pin QFN 260 C 30 seconds 68 ball WLCSP 260 C 30 seconds Table 57 Package Moisture Sensitivity Level MSL IPC JEDEC J STD 2 Package MSL 56 pin QFN MSL 3 68 ball WLCSP MSL 1 Table 58 Package Details Spec ID Package Description 001 58740 Rev A 56 pin QFN 7 0 mm x 7 0 mm x 0 6 mm 001 92343 Rev 68 ball WLCSP 3 52 mm x 3 91 mm x 0 55 mm Docume nt Number 001 90479
2. Details Spec ID Parameter Description Min Typ Max Units Conditions Power supply input voltage Vppa _ With regulator SID6 Vpp 1 8 5 5 V enabled Power supply input voltage unregulated Internally unregulated SID7 V 1 71 1 8 1 89 V pp Vppp Vpp Supply SID8 VDDR Radio supply voltage Radio ON 1 9 5 5 V SID8A VppR Radio supply voltage Radio OFF 1 71 5 5 V SID9 Digital regulator output voltage for core _ 18 V logic Digital regulator output bypass X5R ceramic or better SID10 Cvyccp capacitor 1 1 3 1 6 Active Mode Vpp 1 71 V to 5 5 V 1013 Execute from flash CPU at 3 MHz 1 7 mA 25 003 Vpp 3 3 V SID14 Ipp4 Execute from flash CPU at 3 MHz x mA T 40Cto 85 1015 1505 Execute from flash CPU at 6 MHz 2 5 mA 25 Vpp 3 3 V 1016 1506 Execute from flash CPU at 6 MHz mA T 40 C to 85 Notes 1 Usage above the absolute maximum conditions listed in Table 5 may cause permanent damage to the device Exposure to absolute maximum conditions for extended periods of time may affect device reliability The maximum storage temperature is 150 C in compliance with JEDEC Standard JESD22 A103 High Temperature Storage Life When used below absolute maximum conditions but above normal operating conditions the device may not operate to specification 2 This does not appl
3. CYPRESS PRELIMINARY Family Datasheet PERFORM Pulse Width Modulation PWM Table 25 PWM DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions 10211 lpwmM1 Block current consumption at 3 MHz 42 pA 16 bit PWM 10212 Ipwme2 Block current consumption at 12 MHz 130 pA 16 bit PWM 10213 IpwM3 Block current consumption at 48 MHz 535 pA 16 bit PWM Table 26 PWM AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions 10214 TPWMFREQ Operating frequency 48 MHz 10215 TPWMPWINT Pulse width internal 2 Tok ns SID216 TPWMEXT Pulse width external 2 Tek ns SID217 TPWMKILLINT Kill pulse width internal 2 x ns 10218 TpwMkKILLEXT _ Kill pulse width external 2 Tok ns SID219 TPWMEINT Enable pulse width internal 2 ns 10220 TPWMENEXT Enable pulse width external 2 x ns 10221 Tpwmreswint Reset pulse width internal 2x Tok ns SID222 Tpwmreswext Reset pulse width external 2 Toik ns FC Table 27 Fixed I C DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions 10223 loca Block current consumption at 100 kHz 50 10224 11262 Block current consumption at 400 kHz 155 10225 11263 Block current consumption at 1 Mbps 390 10226 11264 2 enabled in Deep Sleep mode 1 4
4. 4 Input Registers Output Registers Enables 7 6 ues 0 a x3 a a i Digital GlobalClocks af j Clock Selector 2 3 DSI Signals 4 Block from 11 0 Signal VpB 8 8 4 eset Selector m Sok rom 2 UDB To DSI From DSI From UDBs can generate interrupts one UDB at a time to the interrupt controller UDBs retain the ability to connect to any pin on the chip through the DSI Document Number 001 90479 Rev G Page 7 of 43 PERFORM Fixed Function Digital Timer Counter PWM Block The timer counter PWM block consists of four 16 bit counters with user programmable period length There is a capture register to record the count value at the time of an event which may be an I O event a period register which is used to either stop or auto reload the counter when its count is equal to the period register and compare registers to generate compare value signals which are used as PWM duty cycle outputs The block also provides true and complementary outputs with programmable offset between them to allow the use as deadband programmable complementary PWM outputs It also has a kill input to force outputs to a predetermined state for example this is used in motor drive systems when an overcurrent state is indicated and the PWMs driving the FETs need to be shut off immediately with no time for software inter vention Serial Communi
5. Spec ID Parameter Description Min Typ Max Units Details Conditions 10299 TSTARTILO4 ILO startup time 2 ms 10300 32 kHz trimmed frequency 15 32 50 kHz Document Number 001 90479 Rev G Page 31 of 43 PSoC 4 PSoC 4XX7_BLE CYPRESS PRELIMINARY Family Datasheet PERFORM Table 50 External Clock Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions 10301 ExtClkFreq External clock input frequency 0 48 MHz CMOS input level only SID302 ExtClkDuty Duty cycle Measured at Vpp 2 45 55 CMOS input level only Table 51 UDB AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions Data Path performance 10303 FMAX TIMER Max frequency of 16 bit timer in a 48 MHz UDB pair 10304 FMAX ADDER Max frequency of 16 bit adder in a 48 MHz UDB pair 10305 CRC Max frequency of 16 bit CRC PRS in 48 MHz i a UDB pair PLD Performance in UDB SID306 FMAX PLD Max frequency of 2 pass PLD function 48 MHz i in a UDB pair Clock to Output Performance SID307 OUT UDB4 Prop delay for clock in to data out at 15 ns un 25 C Typical 10308 OUT UDB2 Prop delay for clock in to data out 25 ns RARE Worst case Table 52 BLE Subsystem Spec ID Parameter Description Min Typ Max Units Details Con
6. PSoC 4 PSoC 4XX7_BLE Family Datasheet YPRESS PRELIMINARY PERFORM Programmable System on Chip PSoC LM General Description PSoC 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an ARM Cortex M0 CPU It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing The PSoC 4XX7 BLE product family based on this platform is a combination of a microcontroller with an integrated Bluetooth Low Energy BLE also known as Bluetooth Smart radio and subsystem BLESS The other features include digital programmable logic high performance analog to digital conversion ADC opamps with comparator mode and standard communication and timing peripherals The PSoC 4XX7_BLE products will be fully upward compatible with members of the PSoC 4 platform for new applications and design needs The programmable analog and digital subsystems allow flexibility and in field tuning of the design Features 32 bit MCU Subsystem m 48 MHz ARM Cortex MO CPU with single cycle multiply m Up to 128 KB of flash with Read Accelerator m Up to 16 KB of SRAM BLE Radio and Subsystem m 2 4 GHz RF transceiver with 50 O antenna drive m Digital PHY m Link Layer engine supporting master and slave modes m RF output power 18 dBm to 3 dBm m RX sensitivity 89 dBm m RX current 16 4 mA m TX current 15 6 mA at 0 dBm m Received Signal Str
7. 20 dB RF PHY Specification Wanted Signal at 67 dBm and Inter RCV LE CA 03 C at Image frequency Fimace SID349 CI3 Adjacent channel interference 30 dB RF PHY Specification Wanted signal at 67 dBm and Inter RCV LE CA 03 C at Image frequency Fimace 1 MHz 10350 OBB1 Out of band blocking 30 27 dBm RF PHY Specification Wanted signal at 67 dBm and Inter RCV LE CA 04 C ferer at F 30 2000 MHz 10351 OBB2 Out of band blocking 35 27 dBm RF PHY Specification Wanted signal at 67 dBm and Inter RCV LE CA 04 C ferer at F 2003 2399 MHz SID352 OBB3 Out of band blocking 35 27 dBm RF PHY Specification Wanted signal at 67 dBm and Inter RCV LE CA 04 C ferer at F 2484 2997 MHz SID353 OBB4 Out of band blocking 30 27 dBm RF PHY Specification Wanted signal a 67 dBm and Inter RCV LE CA 04 C ferer at F 3000 12750 MHz SID354 IMD Intermodulation performance 50 dBm RF PHY Specification Wanted signal at 64 dBm and 1 Mbps RCV LE CA 05 C BLE third fourth and fifth offset channel SID355 RXSE1 Receiver spurious emission 57 dBm 100 2 30 MHz to 1 0 GHz measurement bandwidth ETSI EN300 328 V1 8 1 SID356 RXSE2 Receiver spurious emission 47 dBm 1 MHz measurement 1 0 GHz to 12 75 GHz bandwidth ETSI EN300 328 V1 8 1 RF Transmitter Specifications SID357 TXP ACC RF power accuracy 4 dB 10358 TXP RANGE RF power control r
8. 200 mA current Table 9 GPIO AC Specifications Spec ID Parameter Description Min Typ Max Units C poa E SID78 TRISEF Rise time in Fast Strong mode 2 12 ns 3 3 V Vppp Ci oap 25 pF SID79 TFALLF Fall time in Fast Strong mode 2 12 ns 3 3 V Vppp Ci oap 25 pF SID80 TRISES Rise time in Slow Strong mode 10 60 ns 3 3 V Vppp Ci oap 25 pF SID81 TrFALLS Fall time in Slow Strong mode 10 60 ns 3 3 V Vppp Ci oap 25 pF SID82 FGPIOUT1 GPIO Fout 3 3 V lt Vpp lt 5 5 V 33 MHz 90 10 25 pF Fast Strong mode load 60 40 duty cycle Note 3 must not exceed Vppp 0 2 V Document Number 001 90479 Rev G Page 20 of 43 PSoC 4 PSoC 4XX7 BLE CYPRESS PRELIMINARY Family Datasheet PERFORM Table 9 GPIO AC Specifications continued inti Details Spec ID Parameter Description Min Typ Max Units Conditions SID83 Fepiout2 GPIO Fout 1 7 V lt Vpp x 3 3 V 16 7 MHz 90 10 25 Fast Strong mode load 60 40 duty cycle 1084 Fepiout3 GPIO Fout 3 3 V lt Vpp x 5 5 V 7 MHz 90 10 25 pF Slow Strong mode load 60 40 duty cycle SID85 GPIO Fout 1 7 V lt Vpp lt 3 3 V 3 5 MHz 90 10 25 pF Slow Strong mode load 60 40 duty cycle SID86 FGPIOIN GPIO input operating frequency 48 MHz 90 10 Vio 1 71 V lt Vpp lt 5 5V Table 10 OV
9. Deep Sleep Mode Vpp 1 71 V to 1 89 V Regulator Bypassed 1029 15049 WDT with WCO on 25 1030 15520 WDT with WCO on 40 C to 85 Deep Sleep Mode Vpp 2 5 V 3 6 V 1031 15021 25 Vpp 3 3 V 1032 15022 T 40 C to 85 C Deep Sleep Mode Vpp 3 6 V to 5 5 V 1033 15023 25 Vpp 5V 1034 15024 pA T 40 C to 85 C Hibernate Mode Vpp 1 8 V to 3 6 V 1037 15527 GPIO and reset active 150 nA T 25 C Vpp 3 3 V 1038 15028 GPIO and reset active nA T 40 C to 85 C Hibernate Mode Vpp 3 6 V to 5 5 V 1039 15029 GPIO and reset active nA T 25 C 5V 1040 15530 GPIO and reset active nA 40 C to 85 C Hibernate Vpp 1 71 to 1 89 V Regulator Bypassed Document Number 001 90479 Rev G Page 18 of 43 PSoC 4 PSoC 4XX7 BLE SSF CYPRESS PRELIMINARY Family Datasheet PERFORM Table 6 DC Specifications continued Spec ID Parameter Description Min Typ Max Units 51041 15031 GPIO and reset active nA T 25 C 1042 150532 GPIO and reset active nA T 40 C to 85 C Stop Mode Vpp 1 8 to 3 6 V 1043 15033 Stop mo
10. Spec ID Parameter Description Min Typ Max Units Details Conditions SID265 Vivi LVI A D SEL 3 0 0000b 1 71 1 75 1 79 V SID266 LVI A D SEL 3 0 00016 1 76 1 80 1 85 V SID267 Vivis LVI A D SEL 3 0 0010b 1 85 1 90 1 95 V SID268 LVI A D SEL 3 0 00116 1 95 2 00 2 05 V SID269 Vivis LVI A D SEL 3 0 0100b 2 05 2 10 2 15 V SID270 Vivie LVI A D SEL 3 0 0101b 2 15 2 20 2 26 V SID271 LVI A D SEL 3 0 01106 2 24 2 30 2 36 V SID272 Vivis LVI_A D_SEL 3 0 01116 2 34 2 40 2 46 V SID273 Vivig LVI A D SEL 3 0 1000b 2 44 2 50 2 56 V SID274 LVI A D SEL 3 0 10016 2 54 2 60 2 67 V SID275 Vivi LVI A D SEL 3 0 1010b 2 63 2 70 2 77 V SID276 2 LVI A D SEL 3 0 1011b 2 73 2 80 2 87 V SID277 LVI A D SEL 3 0 11006 2 83 2 90 2 97 V SID278 LVI A D SEL 3 0 11016 2 93 3 00 3 08 V SID279 Viyi45 LVI A D SEL 3 0 1110b 3 12 3 20 3 28 V SID280 Vivi46 LVI A D SEL 8 0 11116 4 39 4 50 4 61 V SID281 LVI IDD Block current 100 Table 44 Voltage Monitor AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions 10282 TMONTRIP Voltage monitor trip time 1 Hs Document Number 001 90479 Rev G Page 30 of 43 gt PSoC 4 PSoC 4XX7_BLE CYPRESS PRELIMINARY Family Datasheet PERFORM SWD Interface Table 45 SWD Interface Specifications Spec ID Parameter Description Min Typ Max Units Deta
11. 10248 TssELsCK SSEL valid to first SCK valid edge 100 ns Page 28 of 43 Document Number 001 90479 Rev G PSoC 4 PSoC 4XX7 BLE CYPRESS PRELIMINARY Family Datasheet PERFORM Memory Table 37 Flash DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions 10249 Erase and program voltage 1 71 5 5 V 10309 Tws48 Number of Wait states at 2 CPU execution from 32 48 MHz fign SID310 Tws32 Number of Wait states at 1 CPU execution from 16 32 MHz 197 510311 Tws16 Number of Wait states for 0 z CPU execution from 0 16 MHz pan Table 38 Flash AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID250 Row block write time erase 20 ms Row block 128 bytes program 10251 TroWERASE Row erase time 13 ms 10252 S Row program time after erase 7 ms SID253 Bulk erase time 128 35 ms 10254 TpeveroG Total device program time 25 seconds 10255 FEND Flash endurance 100 K cycles 10256 Fret Flash retention TA lt 55 C 100K 20 years P E cycles 10257 FnET2 Flash retention TA lt 85 10 10 years P E cycles System Resources Power on Reset POR Table 39 POR DC Specifications Spec ID Parameter Description Min T
12. E SID398 Fwco Crystal frequency 32 768 kHz SID399 FTOL Frequency tolerance 50 ppm SID400 ESR Equivalent series resistance 50 kQ 10401 PD Drive level 1 uW 510402 TSTART Startup time 500 ms 10403 CL Crystal load capacitance 6 12 5 pF SID404 CO Crystal shunt capacitance 1 35 pF 10405 lwco1 Operating current High Power 8 mode 510406 lwco2 Operating current Low Power 1 mode Document Number 001 90479 Rev G Page 35 of 43 gt PSoC 4 PSoC 4XX7_BLE CYPRESS PRELIMINARY Family Datasheet PERFORM Ordering Information The PSoC 4XX7_BLE part numbers and features are listed in the following table Features 22 a es ie B 2 gt 3 38 v 2g 8 2 3858 5 x 9 MPN gt S o c Sm o x l le lt 2 N 5 7 5 Q o E 2 o gt 8 Elo e micis ale CY8C4127LQI BL473 Y 24 128 16 2 806 2 4 2 36 QFN x CY8C4127LQI BL453 Y 24 v 128 16 2 Y 806 Ksps 2 4 2 2 36 QFN a a CY8C4127LQI BL483 Y Y 24 v 128 16 2 v 806 2 4 2 8 36 QFN CY8C4127LQI BL493 24 128 16 2 v v Y 806 2 4 2 z 36 QFN o 8 4127 483
13. lcd csd D4 2 1 Port 2 Pin 1 lcd csd D5 P2 5 GPIO Port 2 Pin 5 csd D6 VSSD GROUND Digital ground D7 4 1 GPIO Port 4 Pin 1 lcd csd D8 P5 0 GPIO Port 5 Pin 0 Icd csd E1 P1 2 GPIO Port 1 Pin 2 lcd csd E2 P1 3 GPIO Port 1 Pin 3 csd E3 P1 4 GPIO Port 1 Pin 4 lcd csd E4 P1 5 GPIO Port 1 Pin 5 Icd csd E5 P1 6 GPIO Port 1 Pin 6 Icd csd E6 P2 4 GPIO Port 2 Pin 4 Icd csd E7 P5 1 GPIO Port 5 Pin 1 lcd csd E8 VSSD GROUND Digital ground F1 VSSD GROUND Digital ground F2 0 7 GPIO Port 0 Pin 7 Icd csd F3 GPIO Port 0 Pin 3 Icd csd F4 P1 0 GPIO Port 1 Pin 0 Icd csd F5 P1 1 GPIO Port 1 Pin 1 lcd csd F6 VSSR GROUND Radio ground F7 VSSR GROUND Radio ground F8 VDDR POWER 1 9 V to 5 5 V radio supply G1 P0 6 GPIO Port 0 Pin 6 Icd csd G2 VDDD POWER 1 71 V to 5 5 V digital supply G3 P0 2 GPIO Port 0 Pin 2 lcd csd G4 VSSD GROUND Digital ground G5 VSSR GROUND Radio ground G6 VSSR GROUND Radio ground G7 GANT GROUND Antenna shielding ground G8 VSSR GROUND Radio ground H1 P0 5 GPIO Port 0 Pin 5 Icd csd H2 PO 1 GPIO Port 0 Pin 1 lcd csd XTAL240 CLOCK 24 MHz crystal H4 XTAL24I CLOCK 24 MHz crystal or external clock input H5 VSSR GROUND Radio ground H6 VSSR GROUND Radio ground H7 ANT ANTENNA Antenna pin J1 P0 4 GPIO Port 0 Pin 4 Icd csd Document Number 001 90479 Rev G Page 12 of 43 PSoC 4 PSoC 4 7 BLE CYPRESS PRELIMINAR
14. Family Datasheet PERFORM Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at Cypress Locations Products PSoC Solutions JAULtOITIOTIVO cypress com go automotive psoc cypress com solutions GIO CKS amp 2 cypress com go clocks PSoC 1 PSoC 3 PSoC 4 PSoC 5LP EEE eR cypress com go interface Cypress Developer Community Lighting amp Power Control cypress com go powerpsoc Community Forums Blogs Video Training MEMON TTE cypress com go memory cypress com go psoc Technical Support Touch Sensing s cypress com go touch cypress com go support USB Controllers cypress com go USB Wireless etie cypress com go wireless Cypress Semiconductor Corporation 2013 2014 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agre
15. P 0 SCB1 UART RX 0 EXTPA EN SCB1 I2C SDA 0 SCB1 SPI SSO 0 P5 1 GPIO TCPWMS3 0 SCB1 UART TX 0 EXT CLK 2 ECO OUT 2 SCB1 I2C SCL O SCB1 SPI SCLK 0 P6 0 XTAL320 GPIO P6 1 XTAL32I GPIO Document Number 001 90479 Rev G Page 14 of 43 PSoC 4 PSoC 4XX7_BLE CYPRESS PRELIMINARY Family Datasheet PERFORM The possible pin connections are shown for all analog and digital peripherals except the radio LCD and CSD blocks which were shown in Table 1 A typical system application connection diagram is shown in Figure 6 Figure 6 System Application Connection Diagram C1 1 0 uF 55 C2 1 0 uF L C3 C4 36 pF 18 pF 2 2 1 000 32 768 1 XTAL32 0 6 0 1 XTALS21 P6 1 XRES E ot PSoC 4x BLE 56 QFN VDDR s C6 ee C5 VOOR 51 010 Power of thumb and that for critical applications the PCB layout lead inductance and the bypass capacitor parasitic should be The PSoC 4XX7_BLE device can be supplied from batteries with simulated to design and obtain optimal bypassing a voltage range of 1 9 V to 5 5 V by directly connecting to the digital supply VDDD analog supply VDDA and radio supply Power Supply Bypass Capacitors VDDR pins Internal LDOs in the device regulate the supply voltage to the required levels for different blocks The device has VDDD 0 1 pF ceramic at each pin plus bulk one regulator for
16. Rev G Page 37 of 43 gt PSoC 4 PSoC 4XX7_BLE CYPRESS PRELIMINARY Family Datasheet PERFORM Figure 7 56 Pin QFN 7 mm x 7 mm x 0 6 mm TOP VIEW SIDE VIEW BOTTOM VIEW 7 00 0 10 piti 56 43 43 56 UUUUUUUUUUUUUU 42 x OX dt gt c by di 0 40 0 05 PIN 1 DOT FF gt o D 0 20 0 05 7 00 0 10 E di Cj gt ey gt gt c qu 56 05005054 a nnnnnnnnnnnnnn 15 28 0 05 MAX 28 19 1 1 1 0 40 0 10 0 55 0 05 L_ 5055 gg NOTES 1 HATCH AREA IS SOLDERABLE EXPOSED PAD 2 BASED ON REF JEDEC MO 248 3 ALL DIMENSIONS ARE IN MILLIMETERS 001 58740 A The center pad on the QFN package must be connected to ground Vss for the proper operation of the device Figure 8 68 Ball WLCSP Package Outline SIDE VIEW BOTTOM VIEW TOP VIEW H gt 123 45 67 8 x H 876543214 gt gt 1 REFERENCE JEDEC PUBLICATION 95 DESIGN GUIDE 4 18 2 ALL DIMENSIONS ARE IN MILLIMETERS 001 92343 Document Number 001 90479 Rev G Page 38 of 43 gt PSoC 4 PSoC 4XX7_BLE CYPRESS PRELIMINARY Family Datasheet PERFORM Acronyms Table 59 Acronyms Used in t
17. Table 28 Fixed I C AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID227 Fioc4 Bit rate 1 Mbps LCD Direct Drive Table 29 LCD Direct Drive DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID228 li cpLow Operating current in low power mode 17 5 16 x 4 small segment display at 50 Hz SID229 Ci cDCAP oo per segment common 500 5000 pF 10230 LCDorrset Long term segment offset 20 mV 10231 LCD system operating current 2 mA 32 x 4 segments Veias 5 V 50 Hz at 25 C 10232 2 LCD system operating current 2 mA 32 x 4 segments Veias 3 3 V 50 Hz at 25 C Table 30 LCD Direct Drive AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions 10233 LCD frame rate 10 50 150 Hz Document Number 001 90479 Rev G Page 27 of 43 PSoC 4 PSoC 4XX7 BLE CYPRESS PRELIMINARY Family Datasheet PERFORM Table 31 Fixed UART DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions 10234 lUART1 Block current consumption at 100 kbps 55 10235 luART2 Block current consumption at 312 1000 kbp
18. WDT watchdog timer an pulse width modulator WOL write once latch see also NVL random access memory WRES watchdog timer reset RISC reduced instruction set computing XRES external reset I O pin RMS root mean square XTAL crystal RTC real time clock RTL register transfer language RTR remote transmission request RX receive SAR successive approximation register SC CT switched capacitor continuous time SCL 2 serial clock SDA 2 serial data S H sample and hold SINAD signal to noise and distortion ratio 0 special input output GPIO with advanced features See GPIO SOC start of conversion SOF start of frame SPI Serial Peripheral Interface a communications protocol SR slew rate SRAM static random access memory Page 40 of 43 PERFORM Document Conventions Units of Measure Table 60 Units of Measure PRELIMINARY Symbol Unit of Measure degrees Celsius dB decibel dBm decibel milliwatts fF femtofarads Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohour kHz kilohertz kQ kilo ohm ksps kilosamples per second LSB least significant bit Mbps megabits per second MHz megahertz MQ mega ohm Msps megasamples per second microampere uF microfarad uH microhenry Hs microsecond uV microvolt uW microwatt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond nV nanovolt Q ohm pF pico
19. access time at 24 MHz The flash accelerator delivers 85 of single cycle SRAM access performance on average Part of the flash module can be used to emulate EEPROM operation if required During flash erase and programming operations the maximum erase and program time is 20 ms per row the Internal Main Oscillator IMO will be set to 48 MHz for the duration of the operation This also applies to the emulated EEPROM System design must take this into account because peripherals operating from different IMO frequencies will be affected If it is critical that peripherals continue to operate with no change during flash programming always set the IMO to 48 MHz and derive peripheral clocks by dividing down from this frequency SRAM SRAM memory is retained during Hibernate SROM The 8 KB supervisory ROM contains a library of executable functions for flash programming These functions are accessed through supervisory calls SVC and enable in system programming of the flash memory System Resources Power System The power system is described in detail in the Power section on page 15 It provides an assurance that the voltage levels are as required for the respective modes and can either delay the mode entry on power on reset POR for example until voltage Document Number 001 90479 Rev G PSoC 4 PSoC 4XX7_BLE Family Datasheet levels are as required or generate resets brownout detect BOD or interrupts when the
20. power supply reaches a particular programmable level between 1 8 V and 4 5V low voltage detect LVD PSoC 4XX7_BLE operates with a single external supply 1 71 V to 5 5 V without radio and 1 9 V to 5 5 V with radio The device has five different power modes transitions between these modes are managed by the power system PSoC 4XX7_BLE provides Sleep Deep Sleep Hibernate and Stop low power modes Refer to the Technical Reference Manual for more details Clock System The PSoC 4XX7_BLE clock system is responsible for providing clocks to all subsystems that require clocks and for switching between different clock sources without glitching In addition the clock system ensures that no metastable conditions occur The clock system for PSoC 4XX7_BLE consists of the internal main oscillator IMO the internal low speed oscillator ILO the 24 MHz external crystal oscillator ECO and the 32 kHz watch crystal oscillator WCO In addition an external clock may be supplied from a pin IMO Clock Source The IMO is the primary source of internal clocking in PSoC 4XX7 BLE It is trimmed during testing to achieve the specified accuracy Trim values are stored in nonvolatile latches NVL Additional trim settings from flash can be used to compensate for changes The IMO default frequency is 24 MHz and it can be adjusted between 3 MHz to 48 MHz in steps of 1 MHz The IMO tolerance with Cypress provided calibration settings is 2 ILO Cloc
21. the digital circuitry and separate regulators for capacitor 1 uF to 10 uF radio circuitry for noise isolation Analog circuits run directly from VDDA 0 1 ceramic at each pin plus bulk the analog supply VDDA input The device uses separate capacitor 1 uF to 10 pF regulators for Deep Sleep and Hibernate lowered power supply VDDR 0 1 uF ceramic at each pin plus bulk and retention modes to minimize the power consumption The capacitor 1 uF to 10 uF radio stops working below 1 9 V but the device continues to function down to 1 71 V without RF VCCD 1 uF ceramic capacitor at the VCCD pin Bypass capacitors must be used from VDDx x 7 A D or R to The internal bandgap may be bypassed ground The typical practice for systems in this frequency range VREF optional is to use a capacitor in the 1 uF range in parallel with a smaller capacitor for example 0 1 UF Note that these are simply rules with a 1 uF to 10 uF capacitor Document Number 001 90479 Rev G Page 15 of 43 PSoC 4 PSoC 4XX7_BLE CYPRESS PRELIMINARY Family Datasheet PERFORM Development Support The PSoC 4XX7_BLE family has a rich set of documentation development tools and online resources to assist you during your development process Visit www cypress com go psoc4 to find out more Documentation A suite of documentation supports the PSoC 4XX7 BLE family to ensure that you can find answers to your question
22. 1 GPIO Port 1 Pin 1 lcd csd 30 P1 2 GPIO Port 1 Pin 2 csd 31 P1 3 GPIO Port 1 Pin 3 Icd csd 32 P1 4 GPIO Port 1 Pin 4 csd 33 P1 5 GPIO Port 1 Pin 5 csd 34 P1 6 GPIO Port 1 Pin 6 Icd csd 35 P1 7 GPIO Port 1 Pin 7 lcd csd 36 VDDA POWER 1 71 V to 5 5 V analog supply 37 P2 0 GPIO Port 2 Pin 0 csd 38 P2 1 GPIO Port 2 Pin 1 lcd csd 39 P2 2 GPIO Port 2 Pin 2 Icd csd Document Number 001 90479 Rev G Page 10 of 43 PERFORM PSoC 4 PSoC 4XX7_BLE Family Datasheet Table 1 PSoC 4XX7_BLE Pin List QFN Package continued Pin Name Type Description 40 P2 3 GPIO Port 2 Pin 3 Icd csd 41 P2 4 GPIO Port 2 Pin 4 Icd csd 42 P2 5 GPIO Port 2 Pin 5 Icd csd 43 P2 6 GPIO Port 2 Pin 6 Icd csd 44 P2 7 GPIO Port 2 Pin 7 Icd csd 45 VREF REF 1 024 V reference 46 VDDA POWER 1 71 V to 5 5 V analog supply 47 P3 0 GPIO Port 3 Pin 0 Icd csd 48 P3 1 GPIO Port 3 Pin 1 Icd csd 49 P3 2 GPIO Port 3 Pin 2 Icd csd 50 P3 3 GPIO Port 3 Pin 3 Icd csd 51 P3 4 GPIO Port 3 Pin 4 Icd csd 52 P3 5 GPIO Port 3 Pin 5 Icd csd 53 P3 6 GPIO Port 3 Pin 6 Icd csd 54 P3 7 GPIO Port 3 Pin 7 Icd csd 55 VSSA GROUND Analog ground 56 VCCD POWER Regulated 1 8 V supply connect to 1 uF capacitor 57 EPAD GROUND Ground paddle for the QFN package Table 2 PSoC 4XX7
23. 3 Fsarintref SAR operating speed without external 100 Ksps 12 bit resolution ref bypass SID170 A snr Signal to noise ratio SNR 65 dB 10 kHz SID171 A bw Input bandwidth without aliasing A_samp 2 kHz 10172 A_inl Integral nonlinearity Vpp 1 71 V to 1 7 2 LSB Vref 2 1 V to Vpp 5 5 V 1 Msps SID173 A INL Integral nonlinearity Vppp 1 71 Vto 1 5 1 7 LSB Vref 1 71 V to Vpp 3 6 V 1 Msps 10174 A INL Integral nonlinearity Vpp 1 71 V to 1 5 1 7 LSB Vref 1 V to Vpp 5 5 V 500 Ksps SID175 A Differential nonlinearity Vpp 1 71 V to 1 2 2 LSB Vref 1 V to Vpp 5 5 V 1 Msps SID176 A DNL Differential nonlinearity Vpp 1 71 V to 1 2 LSB Vref 1 71 V to Vpp 3 6 V 1 Msps SID177 A DNL Differential nonlinearity Vpp 1 71 V to 1 2 2 LSB Vref 1 V to Vpp 5 5 V 500 Ksps SID178 A thd Total harmonic distortion 65 dB Fin 10 kHz CSD Table 20 CSD Block Specifications er Details Spec ID Parameter Description Min Typ Max Units Condidons SID179 Vesp Voltage range of operation 1 71 5 5 V SID180 IDAC1 DNL for 8 bit resolution 1 1 LSB 10181 IDAC1 INL for 8 bit resolution 3 3 LSB 10182 IDAC2 DNL for 7 bit resolution 1 1 LSB 10183 IDAC2 INL for 7 bit resolution 3 3 LSB SID184 SNR Ratio of counts of finger to noise 5 Ratio Capacitance range of 9 pF to 35 pF 0 1 pF sensitivity Radio is not operating during the scan 10185 1_ 1 O
24. 6 Programmable Digital 7 Fixed Function Digital 8 clo 8 Special Function Peripherals 9 dlc cg 10 ld i aaa 15 Development Support eene 16 Documentation 16 enl au c rere cers 16 He e 16 Electrical Specifications eere 17 Absolute Maximum Ratings 17 Device Level Specifications 17 Document Number 001 90479 Rev G Analog Peripherals 22 Digital Peripherals 26 Memon E 29 System 29 Ordering Information 36 Part Numbering Conventions 36 Packaging Acronyms Document Conventions eene 41 Units of Measure creer tete 41 Revision History Sales Solutions and Legal Information 43 Worldwide Sales and Design Support 43 ProdUCIS 43 PSoQO Sol tlOris 43 Cypress Devel
25. ADC The 12 bit 1 Msps SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks at that frequency to do a 12 bit conversion up to 806 Ksps for the PSoC 41X7_BLE derivatives The block functionality is augmented for the user by adding a reference buffer to it trimmable to 1 and by providing the choice of three internal voltage references Vpp Vpp 2 and Vrer nominally 1 024 V as well as an external reference through a REF pin The sample and hold S H aperture is programmable it allows the gain bandwidth requirements of the amplifier driving the SAR inputs which determine its settling time to be relaxed if required System performance will be 65 dB for true 12 bit precision if appropriate references are used and system noise levels permit it To improve the performance in noisy conditions it is possible to provide an external bypass through a fixed pin location for the internal reference amplifier PRELIMINARY PSoC 4 PSoC 4XX7 BLE Family Datasheet The SAR is connected to a fixed set of pins through an 8 input sequencer The sequencer cycles through the selected channels autonomously sequencer scan and does so with zero switching overhead that is the aggregate sampling bandwidth is equal to 1 Msps whether it is for a single channel or distributed over several channels The sequencer switching is effected through a state machine or through firmware driven switching A feature provid
26. BLE reference system generates all internally required references A one percent voltage reference spec is provided for the 12 bit ADC To allow better signal to noise ratios SNR and better absolute accuracy it is possible to bypass the internal reference using a REF pin or use an external reference for the SAR Refer to Table 19 SAR ADC AC Specifications on page 25 for details Document Number 001 90479 Rev G PSoC 4 PSoC 4XX7_BLE Family Datasheet Bluetooth Smart Radio and Subsystem PSoC 4XX7_BLE incorporates a BLESS that contains the Physical Layer PHY and Link Layer LL engines with an embedded AES 128 security engine The physical layer consists of the digital PHY and the RF transceiver that transmits and receives GFSK packets at 1 Mbps over a 2 4 GHz ISM band which is compliant with the Bluetooth Smart Bluetooth Specifi cation 4 1 The baseband controller is a composite hardware and firmware implementation that supports both master and slave modes Key protocol elements such as HCI and link control are implemented in firmware Time critical functional blocks such as encryption CRC data whitening and access code correlation are implemented in hardware in the LL engine The RF transceiver contains an integrated balun which provides a single ended RF port pin to drive a 50 Q antenna via a matching filtering network In the receive direction this block converts the RF signal from the antenna to a digital b
27. C 4 PSoC 4XX7_BLE Family Datasheet Digital HSIOM_PORT_SELx SELy x denotes port number and y denotes pin number Name Analog 0 8 9 10 14 15 GPIO Active 0 Active 1 Active 2 Deep Sleep 0 Deep Sleep 1 P1 5 CTBm1 OA1 INP GPIO TCPWM2 N 1 SCBO UART TX 0 SCBO I2C SCL 0 SCBO SPI MISO 1 P1 6 CTBm1 INP GPIO TCPWM3 P 1 SCBO UART RTS O0 SCBO SPI SSO 1 P1 7 CTBm1 OA1 INP GPIO TCPWM3 N 1 SCBO UART CTS 0 SCBO SPI SCLK 1 P2 0 CTBmO INP SCBO SPI SS1 2 1 CTBm0_OA0_INN SCBO_SPI_SS2 P2 2 CTBm0_OA0_OUT WAKEUP SCBO_SPI_SS3 P2 3 CTBm0 OA1 OUT GPIO WCO_OUT 1 P2 4 CTBmO OA1 INN P2 5 CTBmO0 OA1 INP GPIO P2 6 CTBmO INP P2 7 CTBm0 OA1 GPIO EXT CLK 1VECO OUT 1 P3 0 SARMUX 0 GPIO TCPWMO P 2 SCBO UART RX 2 SCBO I2C SDA 2 P3 1 SARMUX 1 GPIO TCPWMO NI2 SCBO UART TX 2 SCBO I2C SCL 2 P3 2 SARMUX 2 GPIO TCPWM1 P 2 SCBO UART RTS 2 P3 3 SARMUX 3 GPIO TCPWM1 N 2 SCBO UART CTS 2 P3 4 SARMUX 4 GPIO TCPWM2 P 2 SCB1 UART RX 2 SCB1 I2C SDA 2 P3 5 SARMUX 5 GPIO TCPWM2 NI2 SCB1 UART TX 2 SCB1 I2C SCL 2 P3 6 SARMUX 6 GPIO TCPWMS3 2 SCB1_UART_RTS 2 P3 7 SARMUX_7 GPIO TCPWMS3 NI2 SCB1 UART CTS 2 WCO OUT 0 P4 0 CMOD GPIO TCPWMO P 0 SCB1 UART RTS 0 SCB1 SPI MOSI 0 4 1 GPIO TCPWMO 0 SCB1 UART CTS 0 SCB1 SPI MISO 0 P5 0 GPIO TCPWMS3
28. MCU Clocking Architecture gt HFCLK SYSCLK PERO_CLK EXTCLK zl b Divider 9 5 16 I1 Fractional Divider 0 16 5 Fractional PER15_CLK Divider 1 16 5 gt LFCLK ILO The HFCLK signal can be divided down see Figure 2 to generate synchronous clocks for the UDBs and the analog and digital peripherals There are a total of 12 clock dividers for PSoC 4XX7_BLE ten with 16 bit divide capability and two with 16 5 bit divide capability This allows the generation of 16 divided clock signals which can be used by peripheral blocks The analog clock leads the digital clocks to allow analog events to occur before the digital clock related noise is generated The 16 bit and 16 5 bit dividers allow a lot of flexibility in generating fine grained frequency values and are fully supported in PSoC Creator Reset PSoC 4XX7_BLE can be reset from a variety of sources including a software reset Reset events are asynchronous and guarantee reversion to a known state The reset cause is recorded in a register which is sticky through resets and allows the software to determine the cause of the reset An XRES pin is reserved for an external reset to avoid complications with the configuration and multiple pin functions during power on or reconfiguration The XRES pin has an internal pull up resistor that is always enabled Voltage Reference The PSoC 4XX7_
29. MHz 30 dBm RF PHY Specification offset TRM LE CA 03 C 10371 TXSE1 Transmitter spurious emissions 55 5 dBm FCC 15 247 average 1 0 GHz SID372 TXSE2 Transmitter spurious emissions 41 5 dBm FCC 15 247 average gt 1 0 GHz RF Current Specifications 10373 IRX Receive current in normal mode 18 7 mA SID373A IRX_RF Radio receive current in normal mode 16 4 Measured at Vppr 10374 IRX HIGHGAIN Receive current high gain mode 21 5 mA 10375 ITX 3dBm TX current at 3 dBm setting PA10 20 mA 10376 ITX 0dBm TX current at 0 dBm setting PA7 16 5 mA SID376A ITX_RF 0dBm Radio TX current at 0 dBm setting 15 6 mA Measured at Vopr PA7 SID376B ITX RF 0dBm Radio TX current at 0 dBm excluding 14 2 mA Guaranteed by design Balun loss simulation 10377 ITX 3dBm TX current at 3 dBm setting PA4 15 5 mA 10378 ITX 6dBm TX current at 6 dBm setting 14 5 mA 10379 ITX 12dBm TX current at 12 dBm setting PA2 13 2 mA 10380 ITX 18dBm TX current at 18 setting PA1 12 5 mA SID380A lavg_1sec OdBm Average current at 1 second BLE 18 9 TXP 0 dBm 20 connection interval master and slave clock accuracy For empty PDU exchange SID380B lavg_4sec OdBm Average current at 4 second BLE 6 25 0 dBm 20 connection interval master and slave clock accuracy For empty PDU exchange General RF Sp
30. T GPIO DC Specifications P5_0 and P5_1 Only ae Details Spec ID Parameter Description Min Typ Max Units Conditions SID71A Input leakage current absolute value 10 25 gt Vpp 7 0 V 3 0V SID66A VoL Output voltage LOW level 0 4 V lo 20 mA Vpp 229V Table 11 OVT GPIO AC Specifications P5 0 and P5 1 Only E Details Spec ID Parameter Description Min Typ Max Units Conditions SID78A Output rise time Fast Strong mode 1 5 12 ns 25 pF load 10 90 Vpp 3 3 V SID79A TrFALL OVFS Output fall time in Fast Strong mode 1 5 12 ns 25 pF load 10 90 Vpp 3 3 V SID80A Trisss Output rise time in Slow Strong mode 10 60 ns 25 pF load 10 90 Vpp 3 3 V SID81A TFALLSS Output fall time in Slow Strong mode 10 60 ns 25 pF load 10 90 Vpp 3 3 V 1082 Fepiouti GPIO 3 3 V lt Vpp lt 5 5 V 24 MHz 90 1096 25 pF Fast Strong mode load 60 40 duty cycle SID83A Fepiout2 GPIO Foyt 1 71 V lt Vpp lt 3 3 V 16 MHz _ 90 10 25 pF Fast Strong mode load 60 40 duty cycle Document Number 001 90479 Rev G Page 21 of 43 gt PSoC 4 PSoC 4XX7_BLE CYPRESS PRELIMINARY Family Datasheet PERFORM XRES Table 12 XRES DC Specifications Spec ID Paramet
31. Table 59 Acronyms Used in this Document continued PRELIMINARY PSoC 4 PSoC 4XX7_BLE Family Datasheet Table 59 Acronyms Used in this Document continued Document Number 001 90479 Rev G Acronym Description Acronym Description opamp operational amplifier SRES software reset PAL programmable array logic see also PLD STN super twisted nematic PC program counter SWD serial wire debug a test protocol PCB printed circuit board SWV single wire viewer PGA programmable gain amplifier TD transaction descriptor see also DMA PHUB peripheral hub THD total harmonic distortion PHY physical layer TIA transimpedance amplifier PICU port interrupt control unit TN twisted nematic PLA programmable logic array TRM technical reference manual PLD programmable logic device see also PAL TTL transistor transistor logic PLL phase locked loop TX transmit PMDD package material declaration data sheet UART Universal Asynchronous Transmitter Receiver a POR power on reset communications protocol PRES precise power on reset UDB universal digital block PRS pseudo random sequence USB Universal Serial Bus PS port read data register USBIO n PSoC pins used to connect to Programmable System on Chip VDAC voltage DAC see also DAC IDAC PSRR power supply rejection ratio
32. XX7 BLE Family Datasheet GPIO Table 8 GPIO DC Specifications Spec ID Parameter Description Min Typ Max Units C Details onditions SID58 Vin Input voltage HIGH threshold 0 7 x Vpp _ CMOS input 1059 Vi Input voltage LOW threshold 0 3 Vpp V CMOS input 1060 LVTTL input Vpp lt 2 7 V 0 7 x Vpp V SID61 VIL LVTTL input Vpp lt 2 7 V 0 3 Voo V 1062 Vin LVTTL input Vpp gt 2 7 V 2 0 V SID63 Vi LVTTL input Vpp gt 2 7 V 0 8 V SID64 Vou Output voltage HIGH level Vpp 0 6 _ V loh 4 mA at 3 3 V Vpp SID65 Vou Output voltage HIGH level Vpp 0 5 _ V loh2 1 mAat 1 8 V Vpp SID66 VoL Output voltage LOW level 0 6 V 101 8 mAat3 3 V VDD 1067 VoL Output voltage LOW level 0 6 101 4 mAat1 8 V VDD 1068 VoL Output voltage LOW level 0 4 V Mol 23 mAat3 3 V VDD SID69 Rpullup Pull up resistor 3 5 5 6 8 5 kQ 1070 Rpulldown Pull down resistor 3 5 5 6 8 5 kQ SID71 lu Input leakage current absolute value 2 nA 25 3 3V 1072 liL CTBM Input leakage on CTBm input pins 4 nA 1073 Cin Input capacitance 7 pF SID74 Vhysttl Input hysteresis LVTTL 25 40 mV Vpp gt 2 7 V 1075 Vhyscmos Input hysteresis CMOS 0 05 x Vpp mV SID76 Idiode Current through protection diode to 100 Vpp Vss 1077 GPIO Maximum total source or sink chip
33. Y Family Datasheet PERFORM Table 2 PSoC 4XX7_BLE Pin List WLCSP Package continued Pin Name Type Pin Description J2 P0 0 GPIO Port 0 Pin 0 csd J3 VDDR POWER 1 9 V to 5 5 V radio supply J6 VDDR POWER 1 9 V to 5 5 V radio supply J7 No Connect High speed matrix HSIOM is a group of high speed Table 3 HSIOM Port Settings continued switches that routes GPIOs to the resources inside the device These resources include CapSense TCPWMs 2 SPI UART Value and LCD HSIOM PORT SELx are 32 bit wide registers that 11 control the routing of GPIOs Each register controls one port four 12 dedicated bits are assigned to each GPIO in the port This provides up to 16 different options for GPIO routing as shown in Description Reserved Pin is an LCD common pin 13 Pin is an LCD segment pin Table 3 14 Pin specific Deep Sleep function 0 Table 3 HSIOM Port Settings 15 Pin specific Deep Sleep function 1 Value Description 0 Firmware controlled GPIO 1 Output is firmware controlled but Output Enable OE is controlled from DSI 2 Both output and OE are controlled from DSI 3 Output is controlled from DSI but OE is firmware controlled 4 Pin is a CSD sense pin 5 Pin is a CSD shield pin 6 Pin is connected to AMUXA 7 Pin is connected to AMUXB 8 Pin specific Active function 0 9 Pin specific Active function 1 10 Pin s
34. Y Y 24 128 16 2 806 2 4 2 5 36 WLCSP CY8C4127FNI BL493 24 128 16 2 v v 806Ksps 2 4 2 36 WLCSP CY8C4247LQI BL473 Y 48 128 16 4 4 1 Msps 2 4 2 4 36 QFN CY8C4247LQI BL453 Y 48 128 16 4 4 Y 1 Msps 2 4 2 4 36 QFN amp CY8C4247LQI BL463 Y 48 128 16 4 4 1 Msps 2 4 2 4 36 QFN 39 CY8C4247LQI BL483 Y Y 48 128 16 4 4 1 Msps 2 4 2 4 36 QFN o o CY8C4247LQI BL493 48 v 128 16 4 4 1 Msps 2 4 2 4 36 QFN CY8C4247FNI BL483 Y Y 48 128 16 4 4 1 Msps 2 4 2 4 36 WLCSP CY8C4247FNI BL493 48 128 16 4 4 1 Msps 2 4 2 4 36 WLCSP Part Numbering Conventions PSoC 4 devices follow the part numbering convention described in the following table All fields are single character alphanumeric 0 1 2 9 AB Z unless stated otherwise part numbers are of the form CY8C4ABCDEF XYZ where the fields are defined as follows Example CC 4ABCDEF XYZ CY8C Cypress Prefix __ 4 PSoC4 Architecture 2 4200 Family Family within Architecture 4 48 MHz Speed Grade 7 128 KB Flash Capacity LQ QFN Package Code 1 Industrial Temperature Range B483 Attributes Attributes Code Document Number 001 90479 Rev G Page 36 of 43 PSoC 4 PSoC 4XX7 BLE
35. _BLE Pin List WLCSP Package Pin Name Type Pin Description Al VREF REF 1 024 V reference A2 VSSA GROUND Analog ground A3 P3 3 GPIO Port 3 Pin 3 Icd csd A4 P3 7 GPIO Port 3 Pin 7 Icd csd A5 VSSD GROUND Digital ground A6 VSSA GROUND Analog ground AT VCCD POWER Regulated 1 8 V supply connect to 1 uF capacitor A8 VDDD POWER 1 71 V to 5 5 V radio supply B1 P2 3 GPI Port 2 Pin 3 csd B2 VSSA GROUND Analog ground B3 P2 7 GPIO Port 2 Pin 7 lcd csd B4 P3 4 GPIO Port 3 Pin 4 csd B5 P3 5 GPIO Port 3 Pin 5 Icd csd B6 P3 6 GPIO Port 3 Pin 6 Icd csd B7 XTAL32I P6 1 CLOCK 32 768 kHz crystal or external clock input B8 XTAL320 P6 0 CLOCK 32 768 kHz crystal C1 VSSA GROUND Analog ground C2 P2 2 GPIO Port 2 Pin 2 lcd csd C3 P2 6 GPIO Port 2 Pin 6 Icd csd C4 P3 0 GPIO Port 3 Pin 0 Icd csd C5 P3 1 GPIO Port 3 Pin 1 csd Document Number 001 90479 Rev G Page 11 of 43 gt PSoC 4 PSoC 4XX7_BLE CYPRESS PRELIMINARY Family Datasheet PERFORM Table 2 PSoC 4XX7 BLE Pin List WLCSP Package continued Pin Name Type Pin Description C6 P3 2 GPIO Port 3 Pin 2 Icd csd C7 XRES RESET Reset active LOW C8 P4 0 GPIO Port 4 Pin 0 Icd csd D1 P1 7 GPIO Port 1 Pin 7 lcd csd D2 VDDA POWER 1 71 V to 5 5 V analog supply D3 P2 0 GPIO Port 2 Pin 0
36. and Table 2 shows the programmable pin multiplexing Port 2 consists of the high speed analog inputs for the SAR mux All pins support CSD CapSense and analog mux bus connections Table 1 PSoC 4XX7 BLE Pin List QFN Package Pin Name Type Description 1 VDDD POWER 1 71 V to 5 5 V digital supply 2 XTAL320 P6 0 CLOCK 32 768 kHz crystal 3 XTAL32I P6 1 CLOCK 32 768 kHz crystal or external clock input 4 XRES RESET Reset active LOW 5 P4 0 GPIO Port 4 Pin 0 Icd csd 6 P4 1 GPIO Port 4 Pin 1 lcd csd 7 P5 0 GPIO Port 5 Pin 0 lcd csd 8 P5 1 GPIO Port 5 Pin 1 Icd csd 9 VSSD GROUND Digital ground 10 VDDR POWER 1 9 V to 5 5 V radio supply 11 GANT1 GROUND Antenna shielding ground 12 ANT ANTENNA Antenna pin 13 GANT2 GROUND Antenna shielding ground 14 VDDR POWER 1 9 V to 5 5 V radio supply 15 VDDR POWER 1 9 V to 5 5 V radio supply 16 XTAL24I CLOCK 24 MHz crystal or external clock input 17 XTAL24O CLOCK 24 MHz crystal 18 VDDR POWER 1 9 V to 5 5 V radio supply 19 P0 0 GPIO Port 0 Pin 0 Icd csd 20 1 GPIO Port 0 Pin 1 Icd csd 21 2 Port 0 Pin 2 lcd csd 22 GPIO Port 0 Pin 3 Icd csd 23 VDDD POWER 1 71 V to 5 5 V digital supply 24 P0 4 GPIO Port 0 Pin 4 Icd csd 25 P0 5 GPIO Port 0 Pin 5 Icd csd 26 P0 6 GPIO Port 0 Pin 6 Icd csd 27 0 7 GPIO Port 0 Pin 7 Icd csd 28 P1 0 GPIO Port 1 Pin 0 Icd csd 29 P1
37. ange 20 dB 10359 9 Output power 0 Gain setting PA7 4 0 3 dBm 10360 TXP Output power maximum power setting 1 3 6 dBm PA10 10361 TXP MIN Output power minimum power setting 18 dBm PA1 10362 F2AVG Average frequency deviation for 185 kHz RF PHY Specification 10101010 pattern TRM LE CA 05 C 10363 F1AVG Average frequency deviation for 225 250 275 kHz RF PHY Specification 11110000 pattern TRM LE CA 05 C 10364 Eye opening AF2AVG AF1AVG 0 8 RF PHY Specification TRM LE CA 05 C Document Number 001 90479 Rev G Page 33 of 43 PSoC 4 PSoC 4XX7_BLE CYPRESS PRELIMINARY Family Datasheet PERFORM Table 52 BLE Subsystem continued ae Details Spec ID Parameter Description Min Typ Max Units Conditions SID365 FTX ACC Frequency accuracy 150 150 kHz RF PHY Specification TRM LE CA 06 C 10366 FTX MAXDR Maximum frequency drift 50 50 kHz RF PHY Specification TRM LE CA 06 C 10367 FTX INITDR Initial frequency drift 20 20 kHz RF PHY Specification TRM LE CA 06 C 10368 Maximum drift rate 20 20 kHz RF PHY Specification 50 us TRM LE CA 06 C 10369 IBSE1 In band spurious emission at 2 MHz 20 dBm RF PHY Specification offset TRM LE CA 03 C 10370 IBSE2 In band spurious emission at 23
38. cation Blocks SCB PSoC 4XX7_BLE has two SCBs each of which can implement an 2 UART or SPI interface IC Mode The hardware 12 block implements full multi master and slave interface it is capable of multimaster arbitration This block is capable of operating at speeds of up to 1 Mbps Fast Mode Plus and has flexible buffering options to reduce the interrupt overhead and latency for the CPU It also supports Ezl C that creates a mailbox address range in the memory of PSoC 4XX7_BLE and effectively reduces 12 communication to reading from and writing to an array in the memory In addition the block supports an 8 deep FIFO for receive and transmit which by increasing the time given for the CPU to read the data greatly reduces the need for clock stretching caused by the CPU not having read the data on time The FIFO mode is available in all channels and is very useful in the absence of DMA The 2 peripheral is compatible with 12 Standard mode Fast mode and Fast Mode Plus devices as defined in the NXP I C bus specification and user manual UM10204 The 12 bus I O is implemented with GPIOs in open drain modes SCB1 is fully compliant with Standard mode 100 kHz Fast mode 400 kHz and Fast Mode Plus 1 MHz signaling specifications when routed to GPIO pins P5 0 and P5 1 except for hot swap capability during I2C active communication The remaining GPIOs do not meet the hot swap specification Vpp off draw
39. d third party tools With the ability to disable debug features very robust flash protection and allowing customer proprietary functionality to be implemented in on chip programmable blocks the PSoC 4XX7_BLE family provides a level of security not Document Number 001 90479 Rev G Single Layer AHB Peripheral Interconnect Bluetooth Low Energy Subsystem BLE Baseband Peripheral 1KB SRAM GFSK Modem 4x TCPWM 2 SCB 2C SP VUART 2 4 GHz GFSK Radio IOSS 6x ports IO Antenna Pow er Crystal possible with multi chip application solutions or with microcon trollers Debug circuits are enabled by default and can only be disabled in firmware If not enabled the only way to re enable them is to erase the entire device clear flash protection and reprogram the device with the new firmware that enables debugging Additionally all device interfaces can be permanently disabled device security for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences Because all programming debug and test inter faces are disabled when maximum device security is enabled PSoC 4XX7 BLE with device security enabled may not be returned for failure analysis This is a trade off the PSoC 4XX7 BLE allows the customer to mak
40. de current Vpp 20 nA T 25 C Vpp 3 3 V 1044 15034 Stop mode current Vppg 40 nA 25 VDDR 3 3 V 1045 15035 Stop mode current Vpp nA T 40 C to 85 C SID46 Ipp36 Stop mode current Vppg nA T 40 to 85 VbppR 1 9Vto3 6V Stop Mode Vpp 3 6 to 5 5 V 1047 15037 Stop mode current Vpp nA 25 Vpp 5V 1048 15038 Stop mode current Vppg nA T 25 C Vppg 5 V 1049 15539 Stop mode current Vpp nA T 40 Cto 85 C SID50 15540 Stop mode current nA T 40 C to 85 Stop Mode Vpp 1 71 to 1 89 V Regulator Bypassed SID51 15044 Stop mode current Vpp nA T 25 C 1052 15042 Stop mode current Vpp nA T 40 to 85 Table 7 AC Specifications m 5 Details Spec ID Parameter Description Min Typ Max Units Conditions 1053 Fopy CPU frequency DC 48 MHz 1 71 lt lt 5 5 V 1054 TSLEEP Wakeup from Sleep mode 0 Hs Guaranteed by characterization SID55 TpEEPSLEEP Wakeup from Deep Sleep mode 25 Hs 24 MHz IMO Guaranteed by characterization SID56 THIBERNATE Wakeup from Hibernate mode 2 ms Guaranteed by characterization 1057 Tstop Wakeup from Stop mode 2 ms Guaranteed by characterization Document Number 001 90479 Rev G Page 19 of 43 PERFORM PSoC 4 PSoC 4
41. ditions RF Receiver Specification 510340 RXS IDLE RX sensitivity with idle transmitter 89 dBm SID340A RX sensitivity with idle transmitter 91 dBm Guaranteed by design excluding Balun loss simulation 10341 RXS DIRTY RX sensitivity with dirty transmitter 87 70 dBm RF PHY Specification RCV LE CA 01 C SID342 RXS HIGHGAIN RX sensitivity in high gain mode with 91 dBm idle transmitter 10343 PRXMAX Maximum input power 10 1 dBm RF PHY Specification RCV LE CA 06 C 10344 Cochannel interference 9 21 dB RF PHY Specification Wanted signal at 67 dBm and Inter RCV LE CA 03 C ferer at FRX 10345 CI2 Adjacent channel interference 3 15 dB RF PHY Specification Wanted signal at 67 dBm and Inter RCV LE CA 03 C ferer at FRX 1 MHz 10346 Adjacent channel interference 29 dB RF PHY Specification Wanted signal at 67 dBm and Inter RCV LE CA 03 C ferer at FRX 2 MHz Document Number 001 90479 Rev G Page 32 of 43 PSoC 4 PSoC 4XX7 BLE F CYPRESS PRELIMINARY Family Datasheet PERFORM Table 52 BLE Subsystem continued NT Details Spec ID Parameter Description Min Typ Max Units Conditions SID347 Cl4 Adjacent channel interference 39 dB RF PHY Specification Wanted signal at 67 dBm and Inter RCV LE CA 03 C ferer at 2FRX 3 MHz 10348 5 Adjacent channel interference
42. e Page 3 of 43 PERFORM Functional Definition CPU and Memory Subsystem PU The Cortex MO CPU the PSoC 4XX7_BLE is part of the 32 bit MCU subsystem which is optimized for low power operation with extensive clock gating It mostly uses 16 bit instructions and executes a subset of the Thumb 2 instruction set This enables fully compatible binary upward migration of the code to higher performance processors such as Cortex M3 and M4 The Cypress implementation includes a hardware multiplier that provides a 32 bit result one cycle It includes a nested vectored interrupt controller NVIC block with 32 interrupt inputs and a wakeup interrupt controller WIC The WIC can wake the processor up from the Deep Sleep mode allowing power to the main processor to be switched off when the chip is in the Deep Sleep mode The Cortex M0 CPU provides a nonmaskable interrupt NMI input which is made available to the user when it is not in use for system functions requested by the user The CPU also includes an SWD interface which is a 2 wire form of JTAG the debug configuration used for PSoC 4XX7_BLE has four break point address comparators and two watchpoint data comparators 9 Flash The PSoC 4XX7_BLE device has a 128 KB flash module with a flash accelerator tightly coupled to the CPU to improve average access times from the flash block The flash block is designed to deliver 1 wait state WS access time at 48 MHz and with 0 WS
43. ecifications 10381 FREQ RF operating frequency 2400 2482 MHz 10382 CHBW Channel spacing 2 MHz 10383 DR On air data rate 1000 kbps Document Number 001 90479 Rev G Page 34 of 43 PSoC 4 PSoC 4XX7 BLE F CYPRESS PRELIMINARY Family Datasheet PERFORM Table 52 BLE Subsystem continued Spec ID Parameter Description Min Typ Max Units C 510384 IDLE2TX BLE IDLE to BLE TX transition time 120 140 us 510385 IDLE2RX BLE IDLE to BLE RX transition time 75 120 Hs RSSI Specifications 510386 RSSI ACC RSSI accuracy 5 dB 510387 RSSI RES RSSI resolution 1 dB 10388 RSSI PER RSSI sample period 6 Us Table 53 ECO Specifications Spec ID Parameter Description Min Typ Max Units C DAS SID389 Feco Crystal frequency 24 2 10390 FroL Frequency tolerance 50 50 ppm 10391 ESR Equivalent series resistance 60 Q 10392 PD Drive level 100 uW 10393 TSTART1 Startup time Fast Charge on 850 HS 510394 TsranT2 Startup time Fast Charge off 3 ms SID395 CL Load capacitance 8 pF SID396 CO Shunt capacitance 1 1 pF 510397 140 pa ncudesLDO BG current Table 54 WCO Specifications Spec ID Parameter Description Min Typ Max Units C
44. ed by the sequencer is the buffering of each channel to reduce CPU interrupt service requirements To accommodate signals with varying source impedances and frequencies it is possible to have different sample times programmable for each channel Also the signal range specification through a pair of range registers low and high range values is implemented with a corresponding out of range interrupt if the digitized value exceeds the programmed range this allows fast detection of out of range values without having to wait for a sequencer scan to be completed and the CPU to read the values and check for out of range values in software The SAR is able to digitize the output of the on chip temperature sensor for calibration and other temperature dependent functions The SAR is not available in Deep Sleep and Hibernate modes as it requires a high speed clock up to 18 MHz The SAR operating range is 1 71 V to 5 5 V Figure 3 SAR ADC System Diagram System Bus and Programmable Logic Interconnec SAR Sequencer Sequencing VDD2 VDDD VREF and Control Data and 8 Status Flags gt g SAR ADC ig 9181 gt A t E Ref KA External a Reference Reference re Selection and D 4 s Bypass optiona Inputs from other Ports Opamps CTBm Block PSoC 42X7 BLE has four opamps two for PSoC 41X7 BLE with comparato
45. em interconnect DSI fabric that allows signals from peripherals and ports to be routed to and through the UDBs for communication and control Figure 4 UDB Array System CPU Interconnect Sub system 8 to 32 UDBIF BUS IF IRQ IF CLK IF gt 031 DSI 031 DSI Programmable Digital Subsystem Clocks 4 to8 Peads UBIH dyo sjeubis Sia 1940 Routing Channels PRELIMINARY PSoC 4 PSoC 4XX7_BLE Family Datasheet UDBs can be clocked from a clock divider block from a port interface required for peripherals such as SPI and from the DSI network directly or after synchronization A port interface is defined which acts as a register that can be clocked with the same source as the PLDs inside the UDB array This allows a faster operation because the inputs and outputs can be registered at the port interface close to the I O pins and at the edge of the array The port interface registers can be clocked by one of the I Os from the same port This allows inter faces such as SPI to operate at higher clock speeds by elimi nating the delay for the port input to be routed over DSI and used to register other inputs see Figure 5 Figure 5 Port Interface High Speed Matrix To Clock Tree
46. ement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves t
47. ength Indication RSSI 1 dB resolution Programmable Analog m Four opamps with reconfigurable high drive external and high bandwidth internal drive comparator modes and ADC input buffering capability can operate in Deep Sleep mode m 12 bit 1 Msps SAR ADC with differential and single ended modes channel sequencer with signal averaging m Two current DACs IDACs for general purpose or capacitive sensing applications on any pin m Two low power comparators that operate in Deep Sleep mode Programmable Digital m Four programmable logic blocks called universal digital blocks UDBs each with eight macrocells and datapath m Cypress provided peripheral Component library user defined state machines and Verilog input Power Management m Active mode 1 7 mA at 3 MHz flash program execution m Deep Sleep mode 1 3 pA with watch crystal oscillator WCO on m Hibernate mode 150 nA with RAM retention m Stop mode 60 nA Cypress Semiconductor Corporation Document Number 001 90479 Rev G 198 Champion Court Capacitive Sensing m Cypress CapSense Sigma Delta CSD provides best in class SNR 5 1 and liquid tolerance m Cypress supplied software component makes capacitive sensing design easy m Automatic hardware tuning algorithm SmartSense Segment LCD Drive m LCD drive supported on all pins common or segment m Operates in Deep Sleep mode with four bits per pin memory Serial Communication m Two inde
48. er Description Min Typ Max Units C DA 2 51087 Input voltage HIGH threshold 0 7 x Vooo V CMOS input SID88 Vy Input voltage LOW threshold 0 3 x Vppp V CMOS input SID89 Rpullup Pull up resistor 3 5 5 6 8 5 kQ SID90 Cin Input capacitance 3 pF SID91 VuvsxnES Input voltage hysteresis 100 mV 1092 IDIODE Current through protection diode to 100 Vppp Vss Table 13 XRES AC Specifications Spec ID Parameter Description Min Typ Max Units C vee 2 51093 TRESETWIDTH Reset pulse width 1 Hs Analog Peripherals Opamp Table 14 Opamp Specifications Spec ID Parameter Description Min Typ Max Units C eil Opamp Block Current Vpp 1 8 V No Load SID94 Ipp Hi Power high 1000 1300 1095 155 Power medium 500 1096 Ipp Low Power low 250 350 GBW Load 20 pF 0 1 mA Vppa 2 7 V SID97 GBW HI Power high 6 MHz SID98 GBW MED Power medium 4 MHz SID99 GBW_LO Power low 1 MHz lout_max VppA gt 2 7 V 500 mV From Rail SID100 loUT MAX HI Power high 10 mA SID101 lour Max mip Power medium 10 mA SID102 loUT MAX LO Power low 5 mA lout Vppa 1 71 V 500 mV From Rail 10103 loUT MAX HI Power high 4 10104 lout Max mip Power medium 4 mA 10105 louT MAX LO Power low 2 mA SID106 ViN Charge pump on Vppa 2 2 7 V 0 05 VppA 02 V SID107 Vem Charge pump on Vppa gt 2 7 0 05 Vp
49. farad ppm parts per million ps picosecond S second sps samples per second sqrtHz square root of hertz V volt Document Number 001 90479 Rev G PSoC 4 PSoC 4XX7 BLE Family Datasheet Page 41 of 43 CYPRESS PERFORM Revision History PRELIMINARY PSoC 4 PSoC 4XX7_BLE Family Datasheet Description Title PSoC 4 PSoC 4XX7_BLE Family Datasheet Programmable System on Chip PSoC Document Number 001 90479 Revision ECN crm ee Description of Change 4567076 WKA 11 11 2014 Initial release G 4600081 SKAR 12 19 2014 Change in LPCOMP block current SID148 149 in normal and low power mode Revision of I C UART block current consumption to align with CHAR data Revision of LCD Direct Drive operating current in low power mode to align with CHAR data Revision of BLE RF Average Current Spec for 4 sec BLE connection interval to 6 25 pA to align with CHAR data Revision of RXS with idle transmitter with balun loss and in high gain mode to align with CHAR data Clarified the operating current to reflect crystal current LDO and Bandgap current as well Revision of SID 141 Input Offset Voltage Custom Trim to align with CHAR data Revision of SID 118 CMRR to align with CHAR data Corrected Typo for SID 245 CPU gt SCB Corrected Typo for SID 275 Removed errata Document Number 001 90479 Rev G Page 42 of 43 PSoC 4 PSoC 4XX7_BLE CYPRESS PRELIMINARY
50. he right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 90479 Rev G Revised December 19 2014 Page 43 of 43 All products and company names mentioned in this document may be the trademarks of their respective holders Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information Cypress Semiconductor CY8C4247LQI BL483
51. high 15 nV rtHz SID124 Ci oAD Stable up to maximum load Perfor 125 pF mance specs at 50 pF 10125 Slew_rate Cload 50 pF Power High 6 V usec Vppa gt 2 7 V SID126 T op wake From disable to enable no external RC 300 usec dominating Comp mode Comparator Mode 50 mV Drive Trise Tfal Approx SID127 1 Response time power high 150 nsec SID128 Tpp2 Response time power medium 400 nsec SID129 Tpp3 Response time power low 2000 nsec 10130 Vhyst_op Hysteresis 10 mV Deep Sleep Mode Deep Sleep mode operation is only guaranteed for Vppa gt 2 5 V 10131 GBW DS Gain bandwidth product 50 kHz 10132 IDD_DS Current 15 10133 Vos_DS Offset voltage 5 mV SID134 Vos_dr_DS Offset voltage drift 20 uV C 510135 Vout_DS Output voltage 0 2 Vpp 0 2 V SID136 Vcm DS Common mode voltage 0 2 Vpp 1 8 V Table 15 Comparator DC Specifications Spec ID Parameter Description Min Typ Max Units Boe 10140 VoFFSET1 Input offset voltage Factory trim 10 mV SID141 VorrsET2 Input offset voltage Custom trim 6 mV SID141A VorrsETa Input offset voltage ultra low power 12 mV mode SID142 Vuyst Hysteresis when enabled 10 35 mV SID143 Input common mode voltage normal 0 Vbpp V Modes 1 and 2 mode 0 1 Document Number 001 90479 Rev Page 23 of 43 PSoC 4 PSoC 4XX7 BLE SSF CYPRESS PRELIMINARY Fa
52. his Document continued Table 59 Acronyms Used in this Document Acronym Description Acronym Description ETM embedded trace macrocell abus analog local bus field effect transistor ADC analog to digital converter FIR finite impulse response see also IIR AG analog global FPB flash patch and breakpoint AMBA advanced microcontroller bus archi tecture high performance bus an ARM data FS full speed transfer bus GPIO general purpose input output applies to a PSoC ALU arithmetic logic unit pin AMUXBUS _ analog multiplexer bus HCI host controller interface API application programming interface HVI high voltage interrupt see also LVI LVD APSR application program status register IC integrated circuit ARM advanced RISC machine a CPU architecture IDAC current DAC see also DAC VDAC ATM automatic thump mode IDE integrated development environment BW bandwidth or Inter Integrated Circuit communications protocol CAN Controller Area Network a communications protocol IIR infinite impulse response see also FIR CMRR common mode rejection ratio ILO internal low speed oscillator see also IMO CPU central processing unit IMO internal main oscillator see also ILO CRC cyclic redundancy check an error checking INL integra
53. ils Conditions 10283 F SWDCLK1 3 3V lt Vpp lt 5 5 V 14 MHz SWDCLK s 1 3 CPU clock frequency SID284 F SWDCLK2 1 71 V lt Vpp lt 3 3 V 7 MHz SWDCLK s 1 3 CPU clock frequency SID285 T SWDI SETUP T 1 f SWDCLK 0 25 x T ns 10286 T SWDI HOLD T 1 f SWDCLK 0 25 x T ns 10287 T SWDO VALID T 1 f SWDCLK 0 5 x T ns SID288 T SWDO HOLD T 1 f SWDCLK 1 ns Internal Main Oscillator Table 46 IMO DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions 10289 IMO operating current at 48 MHz 1000 10290 limo2 IMO operating current at 24 MHz ES 325 pA SID291 limo3 IMO operating current at 12 MHz 225 10292 limoa IMO operating current at 6 MHz 180 10293 limos IMO operating current at 3 MHz 150 Table 47 IMO AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions 10296 FIMOTOL3 Frequency variation from 3 to 2 With API called 48 MHz calibration 10297 FIMOTOL3 IMO startup time 12 Hs Internal Low Speed Oscillator Table 48 ILO DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID298 lit o2 ILO operating current at 32 kHz 0 3 1 05 Table 49 ILO AC Specifications
54. internal 2 ns 10197 TTENWIDEXT Enable pulse width external 2 ns 10198 Trimreswint pulse width internal 2 ns 10199 TTIMRESEXT Reset pulse width external 2 ns Counter Table 23 Counter DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions 10200 Block current consumption at 3 MHz 42 16 bit counter 10201 IcrR2 Block current consumption at 12 MHz 130 pA 16 bit counter SID202 IcrR3 Block current consumption at 48 MHz 535 pA 16 bit counter Table 24 Counter AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID203 TCTRFREQ Operating frequency 48 2 10204 Tetrpwint pulse width internal 2x Tok ns SID205 TerRPwExr Capture pulse width external 2 Tok ns SID206 TcTRES Counter Resolution ns 10207 TeENwipINT Enable pulse width internal 2 ns 10208 pulse width external 2x ns 10209 TerRRESWINT Reset pulse width internal 2 ns SID210 TcTRRESWEXT Reset pulse width external 2x _ x ns Document Number 001 90479 Rev G Page 26 of 43 PSoC 4 PSoC 4XX7 BLE
55. it stream after performing GFSK demodulation In the transmit direction this block performs GFSK modulation and then converts a digital baseband signal to a radio frequency before transmitting it to air through the antenna The Bluetooth Smart Radio and Subsystem requires a 1 9 V minimum supply the range varies from 1 9 V to 5 5 V Key features of BLESS are as follows m Master and slave single mode protocol stack with logical link control and adaptation protocol L2CAP attribute ATT and security manager SM protocols m API access to generic attribute profile GATT generic access profile GAP and L2CAP m L2CAP connection oriented channel Bluetooth 4 1 feature m GAP features Broadcaster Observer Peripheral and Central roles Security mode 1 Level 1 2 and 3 Security mode 2 Level 1 and 2 User defined advertising data Multiple bond support W GATT features GATT Client and Server Supports GATT sub procedures q universally unique identifier UUID Bluetooth 4 1 fea ure m SM features Pairing methods Just works Passkey Entry and Out of Band Authenticated man in the middle MITM protection and data signing mLL features Master and Slave roles 128 bit AES engine Encryption Low duty cycle advertising Bluetooth 4 1 feature n LE Ping Bluetooth 4 1 feature m Supports all SIG adopted BLE profiles Page 5 of 43 PERFORM Analog Blocks 12 bit SAR
56. k Source The ILO is a very low power oscillator which is primarily used to generate clocks for the peripheral operation in the Deep Sleep mode ILO driven counters can be calibrated to the IMO to improve accuracy Cypress provides a software component which does the calibration External Crystal Oscillator ECO The ECO is used as the active clock for the BLESS to meet the 50 ppm clock accuracy of the Bluetooth 4 1 Specification PSoC 4XX7_BLE includes a tunable load capacitor to tune the crystal clock frequency by measuring the actual clock frequency The high accuracy ECO clock can also be used as a system clock Watch Crystal Oscillator WCO The WCO is used as the sleep clock for the BLESS to meet the 500 ppm clock accuracy of the Bluetooth 4 1 Specification The sleep clock provides an accurate sleep timing and enables wakeup at the specified advertisement and connection intervals The WCO output can be used to realize the real time clock RTC function in firmware Watchdog Timer A watchdog timer is implemented in the clock block running from the ILO or from the WCO this allows the watchdog operation during Deep Sleep and generates a watchdog reset if not serviced before the timeout occurs The watchdog reset is recorded in the Reset Cause register With the WCO and Page 4 of 43 PERFORM firmware an accurate real time clock within the bounds of the 32 kHz crystal accuracy can be realized Figure 2 PSoC 4XX7_BLE
57. l nonlinearity see also DNL protocol I O input output see also GPIO DIO SIO USBIO DAC digital to analog converter see also IDAC VDAC IPOR initial power on reset DFB digital filter block IPSR interrupt program status register DIO digital input output GPIO with only digital IRQ interrupt request capabilities no analog See GPIO ITM instrumentation trace macrocell DMIPS Dhrystone million instructions per second LCD liquid crystal display DMA direct memory access see also TD mE LIN Local Interconnect Network a communications DNL differential nonlinearity see also INL protocol DNU do not use LR link register DR port write data registers LUT lookup table DSI digital system interconnect LVD low voltage detect see also LVI DWT data watchpoint and trace LVI low voltage interrupt see also HVI ECC error correcting code LVTTL low voltage transistor transistor logic ECO external crystal oscillator MAC multiply accumulate EEPROM electrically erasable programmable read only MCU microcontroller unit memory MISO master in slave out EMI electromagnetic interference NC no connect EMIF external memory interface NMI nonmaskable interrupt EOC end of conversion NRZ non return to zero EOF end of frame nested vectored interrupt controller EPSR execution program status register NVL nonvolatile latch see also WOL ESD electrostatic discharge Document Number 001 90479 Rev G Page 39 of 43 PERFORM
58. lt 10 A current for Fast mode and Fast Mode Plus loj spec 20 mA for Fast Mode Plus hysteresis spec 0 05 x Vpp for Fast mode and Fast Mode Plus and minimum fall time spec for Fast mode and Fast Mode Plus m GPIO cells including P5 0 and P5 1 cannot be hot swapped or powered up independent of the rest of the 2 system m The GPIO pins P5 0 and P5 1 are overvoltage tolerant but cannot be hot swapped or powered up independent of the rest of the I C system m Fast Mode Plus has an lo specification of 20 mA at a Vo of 0 4 V The GPIO cells can sink a maximum of 8 mA lo with a maximum of 0 6 V Document Number 001 90479 Rev G PRELIMINARY PSoC 4 PSoC 4XX7 BLE Family Datasheet m Fast mode and Fast Mode Plus specify minimum Fall times which are not met with the GPIO cell the Slow Strong mode can help meet this spec depending on the bus load UART Mode This is a full feature UART operating at up to 1 Mbps It supports automotive single wire interface LIN infrared interface IrDA and SmartCard 1507816 protocols all of which are minor variants of the basic UART protocol In addition it supports the 9 bit multiprocessor mode that allows the addressing of peripherals connected over common RX and TX lines Common UART functions such as parity error break detect and frame error are supported An 8 deep FIFO allows much greater CPU service latencies to be tolerated Note that hardware handshaking is not sup
59. meter Description Min Typ Max Units Details Conditions 10156 A_RES Resolution 12 bits 10157 A CHNIS S Number of channels single ended 8 8 full speed 10158 A CHNKS D Number of channels differential 4 Diff inputs use neighboring I O 10159 Monotonicity Yes 10160 A GAINERR Gain error 0 1 With external reference SID161 A OFFSET Input offset voltage 2 mV with 1 V VREF 10162 A_ISAR Current consumption 1 10163 A_VINS Input voltage range single ended Vss VDDA V SID164 A VIND Input voltage range differential Vss VDDA V SID165 A INRES Input resistance 2 2 kQ SID166 A_INCAP Input capacitance 10 pF Document Number 001 90479 Rev G Page 24 of 43 PERFORM PRELIMINARY PSoC 4 PSoC 4XX7 BLE Family Datasheet Table 18 SAR ADC DC Specifications 10312 VREFSAR Trimmed internal reference to SAR Percentage of Vbg 1 024 V Table 19 SAR ADC AC Specifications e Details Spec ID Parameter Description Min Typ Max Units Conditions SID167 A psrr Power supply rejection ratio 70 dB Measured at 1 V SID168 A cmrr Common mode rejection ratio 66 dB 10169 A_samp Sample rate 1 Msps 806 Ksps for PSoC 41X7 BLE devices SID31
60. mily Datasheet PERFORM Table 15 Comparator DC Specifications continued Spec ID Parameter Description Min Typ Max Units 510144 Vicm2 Input common mode voltage in 0 Vppp V low power mode SID145 Vicm3 Input common mode voltage in ultra 0 Vppp V low power mode 1 15 10146 CMRR Common mode rejection ratio 50 dB Vppp gt 2 7 V 10147 CMRR Common mode rejection ratio 42 dB Vppp lt 2 7 V SID148 lomp1 Block current normal mode 400 10149 lomp2 Block current low power mode 100 10150 Block current in ultra low power mode 6 10151 ZcMP DC input impedance of comparator 35 MQ Table 16 Comparator AC Specifications Spec ID Parameter Description Min Typ Max Units cole 510152 1 Response time normal mode 50 38 ns 50 mV overdrive overdrive 10153 Response time low power mode 70 ns 50 mV overdrive 50 mV overdrive 10154 Response time ultra low power mode 2 3 Hs 200 mV overdrive 50 mV overdrive Temperature Sensor Table 17 Temperature Sensor Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions 510155 TsENSACC Temperature sensor accuracy 5 1 5 40 to 85 C SAR ADC Table 18 SAR ADC DC Specifications Spec ID Para
61. oper Community 43 Technical Support enceinte 43 Page 2 of 43 SES 2 Cypress PRELIMINARY PERFORM PSoC 4 PSoC 4XX7_BLE Family Datasheet Figure 1 Block Diagram CPU amp Memory PSoC 4 BLE MOS8 Architecture SW D TC Cortex MO 48 MHz FASTMUL aM FLASH 128 kB System Resources Power Sleep Control WIC POR T CVD Peripherds System Interconnect REF BOD PWRSYS NVLatches PERI Boost Clock Contro WDT IMO LO Programmable Analog 2x LP Comparator Test DFT Logic DFT Analog Active Sleep DeepSleep Hibernate The PSoC 4XX7_BLE devices include extensive support for programming testing debugging and tracing both hardware and firmware The ARM SWD interface supports all programming and debug features of the device Complete debug on chip functionality enables full device debugging in the final system using the standard production device It does not require special interfaces debugging pods simulators or emulators Only the standard programming connections are required to fully support debugging The PSoC Creator IDE provides fully integrated programming and debugging support for the PSoC 4XX7_BLE devices The SWD interface is fully compatible with industry standar
62. pA 0 2 V Vout gt 2 7 V SID108 1 Power high 10 mA 0 5 0 5 V 10109 VouT 2 Power high 1 mA 0 2 Vppa 0 2 V SID110 Vour 3 Power medium 1 mA 0 2 VppA 0 2 V SID111 Vour 4 Power low 0 1 mA 0 2 Vppa 0 2 V SID112 Vos TR Offset voltage trimmed 1 0 5 1 mV High mode Document Number 001 90479 Rev G Page 22 of 43 gt PSoC 4 PSoC 4XX7_BLE CYPRESS PRELIMINARY Family Datasheet PERFORM Table 14 Opamp Specifications continued Spec ID Parameter Description Min Typ Max Units C pale 510113 Vos Offset voltage trimmed _ 1 _ mV Medium mode SID114 Vos TR Offset voltage trimmed 2 mV Low mode SID115 Vos DR TR Offset voltage drift trimmed 10 3 10 High mode 10116 Vos DR TR Offset voltage drift trimmed 10 Medium mode 10117 Vos DR TR Offset voltage drift trimmed 10 Low mode 10118 CMRR DC 65 70 dB Vppp 3 6 V High power mode SID119 PSRR At 1 kHz 100 mV ripple 70 85 dB Vppp 3 6 V Noise 10120 Input referred 1 Hz 1 GHz power 94 uVrms high 10121 VN2 Input referred 1 kHz power high 72 nV rtHz 10122 Input referred 10 kHz power high 28 nV rtHz 10123 Input referred 100 kHz power
63. pecific Active function 2 The selection of peripheral function for different GPIO pins is given in Table 4 Table 4 Port Pin Connections Document Number 001 90479 Rev G Digital HSIOM PORT SELx SELy x denotes port number and y denotes pin number Name Analog 0 8 9 10 14 15 GPIO Active 0 Active 1 Active 2 Deep Sleep 0 Deep Sleep 1 P0 0 COMPO INP GPIO TCPWMO P 3 SCB1 UART RX 1 SCB1 I2C SDA 1 SCB1 SPI MOSI 1 P0 1 COMPO INN GPIO TCPWMO N 3 SCB1 UART TX 1 SCB1 I2C SCL 1 SCB1 SPI MISO 1 P0 2 GPIO TCPWM1 P 3 SCB1 UART RTS 1 COMPO OUT 0 SCB1 SPI SSO 1 P0 3 GPIO TCPWM1_N 3 SCB1 UART CTS 1 COMP1 OUT 0 SCB1 SPI SCLK 1 P0 4 COMP1_INP GPIO TCPWM1_P 0 SCBO UART RX 1 EXT_CLK 0 SCBO I2C SDA 1 SCBO SPI MOSI 1 OUT 0 P0 5 COMP1_INN GPIO TCPWM1_N 0 SCBO UART TX 1 SCBO I2C SCL 1 SCBO SPI MISO 1 6 GPIO TCPWM2 0 SCBO UART RTS 1 SWDIO 0 SCBO SPI SSO 1 P0 7 GPIO TCPWM2 0 SCBO UART CTS 1 SWDCLK 0 SCBO SPI SCLK 1 P1 0 CTBm1 INP GPIO TCPWMO P 1 COMPO OUT 1 WCO_OUT 2 P1 1 CTBm1 INN GPIO TCPWMO N 1 COMP1_OUT 1 SCB1_SPI_SS1 P1 2 CTBm1_OA0_OUT GPIO TCPWM1_P 1 SCB1 SPI SS2 P1 3 CTBm1 OA1 OUT GPIO TCPWM 1 N 1 SCB1 SPI SS3 P14 CTBm1 OA1 INN GPIO TCPWM2 P 1 SCBO UART RX O0 SCBO I2C SDA 0 SCBO SPI MOSI 1 Page 13 of 43 PERFORM PRELIMINARY Table 4 Port Pin Connections continued PSo
64. pendentruntime reconfigurable serial communication blocks SCBs with reconfigurable 12C SPI or UART function ality Timing and Pulse Width Modulation m Four 16 bit timer counter pulse width modulator TCPWM blocks Center aligned Edge and Pseudo random modes Comparator based triggering of Kill signals for motor drive and other high reliability digital logic applications Up to 36 Programmable GPIOs mm x 7 mm 56 pin QFN package m 3 51 mm x 3 91 mm 68 ball CSP package m Any GPIO pin can be CapSense LCD analog or digital m Two overvoltage tolerant OVT pins drive modes strengths and slew rates are programmable PSoC Creator Design Environment m integrated design environment IDE provides schematic design entry and build with analog and digital automatic routing m API components for all fixed function and programmable peripherals Industry Standard Tool Compatibility m After schematic entry development can be done with ARM based industry standard development tools San Jose CA 95134 1709 408 943 2600 Revised December 19 2014 gt PSoC 4 PSoC 4XX7_BLE CYPRESS PRELIMINARY Family Datasheet Contents Functional Definition eee 4 CPU and Memory Subsystem 4 System 4 Bluetooth Smart Radio and Subsystem 5 Analog BIOCKS esc M
65. ported This is not commonly used and can be implemented with a UDB based UART in the system if required SPI Mode The SPI mode supports full Motorola SPI TI Secure Simple Pairing SSP essentially adds a start pulse that is used to synchronize SPI Codecs and National Microwire half duplex form of SPI The SPI block can use the FIFO and supports an EzSPI mode in which the data interchange is reduced to reading and writing an array in memory GPIO PSoC 4XX7 BLE has 36 GPIOs The GPIO block implements the following m Eight drive strength modes Analog input mode input and output buffers disabled Input only Weak pull up with strong pull down Strong pull up with weak pull down Open drain with strong pull down Open drain with strong pull up Strong pull up with strong pull down Weak pull up with weak pull down m Input threshold select CMOS or LVTTL m Pins 0 and 1 of Port 5 are overvoltage tolerant Pins m Individual control of input and output buffer enabling disabling in addition to drive strength modes m Hold mode for latching the previous state used for retaining the I O state in Deep Sleep and Hibernate modes m Selectable slew rates for dV dt related noise control to improve EMI The pins are organized in logical entities called ports which are 8 bit in width During power on and reset the blocks are forced to the disable state so as not to crowbar any inputs and or cause excess t
66. r modes which allow most common analog functions to be performed on chip eliminating external compo nents PGAs voltage buffers filters transimpedance amplifiers and other functions can be realized with external passives saving power cost and space The on chip opamps are designed with enough bandwidth to drive the sample and hold circuit of the ADC without requiring external buffering Document Number 001 90479 Rev G Temperature Sensor PSoC 4XX7_BLE has an on chip temperature sensor This consists of a diode which is biased by a current source that can be disabled to save power The temperature sensor is connected to the ADC which digitizes the reading and produces a temper ature value by using a Cypress supplied software that includes calibration and linearization Low Power Comparators PSoC 4XX7_BLE has a pair of low power comparators which can also operate in Deep Sleep and Hibernate modes This allows the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during low power modes The comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode Hibernate where the system wake up circuit is activated by a comparator switch event Page 6 of 43 PERFORM Programmable Digital Universal Digital Blocks UDBs and Port Interfaces The PSoC 42X7_BLE has four UDBs the UDB array also provides a switched digital syst
67. s Table 32 Fixed UART AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions 10236 FUART Bit rate 1 Mbps SPI Specifications Table 33 Fixed SPI DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions 10237 Ispi4 Block current consumption at 1 Mbps 360 10238 Igpio Block current consumption at 4 Mbps 560 10239 Ispi3 Block current consumption at 8 Mbps 600 Table 34 Fixed SPI AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions 10240 Fspi SPI operating frequency master 6X 8 MHz oversampling Table 35 Fixed SPI Master Mode AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions 10241 MOSI valid after Sclock driving edge 18 ns 10242 Tpsi MISO valid before Sclock capturing edge 20 ns Full clock late MISO Full clock late MISO sampling used sampling SID243 Previous MOSI data hold time 0 _ _ ns Referred to Slave capturing edge Table 36 Fixed SPI Slave Mode AC Specifications cate Details Spec ID Parameter Description Min Typ Max Units Conditions 10244 MOSI valid before Sclock capturing edge 40 ns SID245 Tpso MISO valid after Sclock driving edge 42 3 ns x TscB 10246 Tpso ext MISO valid after Sclock driving edge in 50 ns Vpp lt 3 0 V external clock mode 10247 Previous MISO data hold time 0 ns
68. s part of a development tool ecosystem Visit us at www cypress com go psoccreator for the latest information on the revolutionary easy to use PSoC Creator IDE supported third party compilers programmers debuggers and development kits Page 16 of 43 PSoC 4 PSoC 4XX7 BLE CYPRESS PRELIMINARY Family Datasheet PERFORM Electrical Specifications Absolute Maximum Ratings Table 5 Absolute Maximum Ratings Spec ID Parameter Description Min T Max Units Details yp Conditions 5101 Vppp ABS Analog digital or radio supply relative 0 5 6 V Absolute max to Vss Vssp Vssa 102 ABS Direct digital core voltage input relative 0 5 1 95 V Absolute max E to Vssp SID3 VGPIO_ABS GPIO voltage 0 5 Vpp 0 5 V Absolute max SIDA IcPio ABS Maximum current per GPIO 25 25 mA Absolute max SID5 IGPIO injection GPIO injection current Max for Vip gt 0 5 0 5 mA Absolute max i Vppp and Min for lt Vss current injected per pin BID57 ESD HBM Electrostatic discharge human body 220001 V model BID58 ESD CDM Electrostatic discharge charged device 500 V model BID61 LU Pin current for latch up 200 200 mA Device Level Specifications All specifications are valid for 40 lt lt 85 C and TJ lt 100 C except where noted Specifications are valid for 1 71 V to 5 5 V except where noted Table 6 DC Specifications
69. s quickly This section contains a list of some of the key documents Software User Guide A step by step guide for using PSoC Creator The software user guide shows you how the PSoC Creator build process works in detail how to use source control with PSoC Creator and much more Component Datasheets The flexibility of PSoC allows the creation of new peripherals Components long after the device has gone into production Component datasheets provide all of the information needed to select and use a particular Component including a functional description API documen tation example code and AC DC specifications Application Notes PSoC application notes discuss a particular application of PSoC in depth examples include creating Document Number 001 90479 Rev G standard and custom BLE profiles Application notes often include example projects in addition to the application note document Technical Reference Manual The Technical Reference Manual TRM contains all the technical detail you need to use a PSoC device including a complete description of all PSoC registers The TRM is available in the Documentation section at www cypress com psoc4 Online In addition to print documentation the Cypress PSoC forums connect you with fellow PSoC users and experts in PSoC from around the world 24 hours a day 7 days a week Tools With industry standard cores programming and debugging interfaces the PSoC 4XX7 BLE family i
70. urn on current A multiplexing network known as a high speed matrix HSIOM is used to multiplex between various signals that may connect to an I O pin Pin locations for fixed function peripherals are also fixed to reduce internal multi plexing complexity these signals do not go through the DSI network DSI signals are not affected by this and any pin may be routed to any UDB through the DSI network Data output and pin state registers store respectively the values to be driven on the pins and the states of the pins themselves Every I O pin can generate an interrupt if so enabled and each I O port has an interrupt request IRQ and interrupt service routine ISR vector associated with it 5 for PSoC 4XX7_BLE since it has 4 5 ports Page 8 of 43 PERFORM Special Function Peripherals LCD Segment Drive PSoC 4XX7_BLE has an LCD controller which can drive up to four commons and up to 32 segments It uses full digital methods to drive the LCD segments requiring no generation of internal LCD voltages The two methods used are referred to as digital correlation and PWM The digital correlation method modulates the frequency and levels of the common and segment signals to generate the highest RMS voltage across a segment to light it up or to keep the RMS signal zero This method is good for STN displays but may result in reduced contrast with TN cheaper displays The PWM method drives the panel with PWM signals to effec tivel
71. utput current of IDAC1 8 bits in 612 High range 10186 IpAC1 CRT2 Output current of IDAC1 8 bits in 306 Low range Document Number 001 90479 Rev G Page 25 of 43 PERFORM Table 20 CSD Block Specifications continued PRELIMINARY PSoC 4 PSoC 4XX7_BLE Family Datasheet Spec ID Parameter Description Min Typ Max Units C Ds SID187 Ipac2_ CRT1 Output current of IDAC2 7 bits in 305 High range 10188 Ipac2_CRT2 Output current of IDAC2 7 bits in 153 Low range Digital Peripherals Timer Table 21 Timer DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions 10189 1 Block current consumption at 3 MHz 42 pA 16 bit timer 10190 Block current consumption at 12 MHz 130 pA 16 bit timer SID191 Block current consumption at 48 MHz 535 pA 16 bit timer Table 22 Timer AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID192 TTIMFREQ Operating frequency 48 MHz 10193 TCAPWINT Capture pulse width internal 2 ns 10194 TCAPWEXT Capture pulse width external 2 ns 10195 TTIMRES Timer resolution ns 10196 TTENWIDINT Enable pulse width
72. y to the RF pins ANT XTALI and XTALO RF pins ANT XTALI and XTALO are tested for 500 V HBM Document Number 001 90479 Rev G Page 17 of 43 PSoC 4 PSoC 4XX7 BLE F CYPRESS PRELIMINARY Family Datasheet PERFORM Table 6 DC Specifications continued Spec ID Parameter Description Min Typ Max Units Serene 1017 1557 Execute from flash CPU at 12 MHz 4 mA T 25 C 3 3 V 1018 1508 Execute from flash CPU at 12 MHz mA T 40 to 85 51019 1509 Execute from flash CPU at 24 MHz 7 1 mA T 25 C Vpp 3 3 V SID20 15510 Execute from flash CPU at 24 MHz mA 40 to 85 51021 15041 Execute from flash CPU at 48 MHz 13 4 mA 25 Vpp 3 3V 1022 15042 Execute from flash CPU at 48 MHz mA T 40 to 85 Sleep Mode Vpp 1 8 V to 5 5 V 1023 15513 1 mA T 25 VDD 3 3 V SYSCLK 3 MHz Sleep Mode Vpp and Vppg 1 9 V to 5 5 V 1024 pem ECO on mA 25 VDD 3 3 V SYSCLK 3 MHz Deep Sleep Mode Vpp 1 8 V to 3 6 V 1025 15015 WDT with WCO on 1 3 25 3 3V 1026 15016 WDT with WCO on T 40 C to 85 C Deep Sleep Mode Vpp 3 6 V to 5 5 V 1027 15047 WDT with WCO on 25 Vbo 5 V 1028 15048 WDT with WCO on T 40 C to 85
73. y use the capacitance of the panel to provide the integration of the modulated pulse width to generate the desired LCD voltage This method results in higher power consumption but can result in better results when driving TN displays LCD operation is supported during Deep Sleep mode refreshing a small display buffer four bits one 32 bit register per port Document Number 001 90479 Rev G PSoC 4 PSoC 4XX7_BLE Family Datasheet CapSense CapSense is supported on all pins in PSoC 4XX7_BLE through a CapSense Sigma Delta CSD block that can be connected to any pin through an analog mux bus that any GPIO pin can be connected to via an Analog switch CapSense function can thus be provided on any pin or group of pins in a system under software control A component is provided for the CapSense block to make it easy for the user The shield voltage can be driven on another mux bus to provide liquid tolerance capability Liquid tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input The CapSense block has two IDACs which can be used for general purposes if CapSense is not being used both IDACs are available in that case or if CapSense is used without liquid tolerance one IDAC is available Page 9 of 43 gt PSoC 4 PSoC 4XX7_BLE CYPRESS PRELIMINARY Family Datasheet Table 1 shows the pin list for the PSoC 4XX7 BLE device
74. yp Max Units Details Conditions 10258 VRISEIPOR Rising trip voltage 0 80 1 45 V SID259 VFALLIPOR Falling trip voltage 0 75 1 40 V SID260 VIPORHYST Hysteresis 15 200 mV Table 40 POR AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID264 TPPOR TR PPOR response time in Active 1 HS and Sleep modes Note 4 tcan take as much as 20 milliseconds to write to flash During this time the device should not be reset or flash operations will be interrupted and cannot be relied onto have completed Reset sources include the XRES pin software resets CPU lockup states and privilege violations improper power supply levels and watchdogs Make certain that these are not inadvertently activated Document Number 001 90479 Rev G Page 29 of 43 PSoC 4 PSoC 4XX7 BLE CYPRESS PRELIMINARY Family Datasheet PERFORM Table 41 Brown Out Detect Spec ID Parameter Description Min Typ Max Units C S 10261 VEALLPPOR BOD trip voltage in Active and Sleep 1 64 V modes SID262 VEALLDPSLP BOD trip voltage in Deep Sleep mode 1 4 V Table 42 Hibernate Reset Spec ID Parameter Description Min Typ Max Units C pelle 2 510263 VHBRTRIP BOD trip voltage in Hibernate mode 1 1 V Voltage Monitors Table 43 Voltage Monitor DC Specifications

Data Sheet - Mouser Electronics

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