TPMC310 - TEWS TECHNOLOGIES
Contents
1. 9 3 2 2 CAN Status 10 3 2 3 CAN Controller Register 11 PCI9S030 TARGET CHIPA U 12 4 1 PCI Configuration Registers PCR J U u u uu u u u u 12 4 1 1 9030 PCI 12 4 1 2 PCI Base Address 13 4 2 Local Configuration Register LCR 14 4 3 Configuration EEPROM U U U u u u uu u u u 15 4 4 Local Software aannaaien Nendeni Naaien 16 PROGRAMMING HINTS 17 5 1 CAN Controller SJA1000 u u u u J 17 CONFIGURATION 19 6 1 VO Line Co fig rati ol u u 19 6 2 Solder Pad Location 20 PIN ASSIGNMENT n 21 TPMC310 User Manual Issue 12. 1 Note A CAN bus transceiver must only be set to operating mode when the CAN controller is also set to operating mode or already is in operating mode A CAN bus transceiver shall not be set to operating mode while the CAN controller is in Reset Mode Disabling interrupts in the CAN Control Register only affects the interrupt mapping to the PCI9030 LINTx local interrupt inputs It will not affect the interrupt source of the SJA1000 CAN controllers If enabled the CAN CH1 interrupt source is mapped to the PCI9030 LINT1 local interrupt input If enabled the CAN CH2 interrupt source is mapped to the PCI9030 LINT2 local interrupt input The PCI9030 LINTx local interrupt inputs are used in active low level sensitive mode The CAN interrupts must be acknowledged via SJA1000 registers CAN Controller Register Space Please see the SJA1000 CAN Controller Manual for more information TPMC310 User Manual Issue 1 1 6 Page 9 of 22 TEWS gt TECHNOLOGIES 3 2 2 CAN Status Register Bit Name Function Access Reset 7 2 Reserved Undefined for reads X 1 INT CAN 2 Controller Interrupt Request Status R X 0 CAN1 INT CAN CH1 Controller Interrupt Request Status R X Table 3 4 CAN Status Register The CAN CHx controller interrupt request status is 0 for no active interrupt request and 1 for active interrupt request Please see the SJA1000 CAN Controller Manual for more infor
3. Initial Issue CAN Oscillator Frequency corrected 16 MHz New address TEWS LLC Minor Version Step New PCB Added secondary thermal interface Added extra mounting holes preventing vibration value has changed Solder pad locations for termination options have changed New Notation for User Manual and Engineering Documentation 1 Corrected I O Line Configuration Table 2 Added note for the Bus End Option 3 Added note for supported baud rate range to Technical Specification Table 1 Added notes regarding the MTBF value in the technical specification table 2 Added note regarding setting the CAN bus transceivers to operating mode a CAN bus transceiver shall not be set to operating mode while the CAN controller is in Reset Mode TPMC310 User Manual Issue 1 1 6 TEWS E TECHNOLOGIES Date October 2003 June 2004 September 2006 April 2008 December 2008 January 2011 June 2014 Page 3 of 22 TEWS gt TECHNOLOGIES Table of Contents PRODUCT DESCRIPTION 6 TECHNICAL SPECIFICATION 7 LOCAL SPACE ADDRESSING U U IA u u uu DER ME 8 3 1 9030 Local Space Configuration U U u u u u u u 8 3 2 PLD Register Space u u cua ie inue 8 3 2 1 Control
4. TEWS 22 The Embedded I O Company TECHNOLOGIES TPMC310 Conduction Cooled PMC Isolated 2 x CAN Bus Version 1 1 User Manual Issue 1 1 6 June 2014 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 40580 Fax 49 0 4101 4058 19 e mail info tews com www tews com TPMC310 10R Conduction Cooled PMC isolated 2 x CAN Bus P14 back TPMC310 User Manual Issue 1 1 6 TEWS gt TECHNOLOGIES This document contains information which is proprietary to TEWS TECHNOLOGIES GmbH Any reproduction without written permission is forbidden TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein Style Conventions Hexadecimal characters are specified with prefix Ox i e 0 029 that means hexadecimal value 029E For signals on hardware products an Active Low is represented by the signal name with following i e IP RESET Access terms are described as W Write Only R Read Only RW Read Write R C Read Clear R S Read Set 2003 2014 by TEWS TECHNOLOGIES GmbH All trademarks mentioned are property of their respective owners Page 2 of 22 Issue 1 0 1 1 1 2 1 3 Description
5. 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C Ox0E 0x00 0x0136 0x1498 0x0280 0x0000 0x0280 0x0000 s b 0x1498 0x10 0x0000 0x0040 0x0000 0x0100 0x4801 0x0001 0x0000 0x0000 0x20 0x0000 0x0006 0x0000 0x0003 OxOFFF OxFFFO OxOFFF 0x30 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0001 0x40 0x0000 0x1001 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x50 0x1500 OxCOAO 0x1502 0x4120 0x0000 0x0000 0x0000 0x0000 0x60 0x0000 0x0000 0x0000 0x0009 0x0000 0x1081 0x0000 0x1181 0x70 0x0000 0x0000 0x0030 0x0049 0x0078 0x0000 0x0224 0x9252 0x80 0x0000 0x0000 0x0000 0x0000 OxFFFF OxFFFF OxFFFF OxFFFF 0x90 OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxAO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF 0xB0 OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF 0xCO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxDO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxEO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFO OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF OxFFFF Table 4 3 Configuration EEPROM Subsystem ID Value EEPROM Offset 0 0 10 108 0x000A TPMC310 User Manual Issue 1 1 6 Page 15 of 22 TEWS gt TECHNOLOGIES 4 4 Local Software Reset The PCI9030 Local Reset Output LRESETo is used to reset the on board local logic The 9030 local reset is active during PCI reset or if the PCI Adapter Software Reset bit is set in the
6. 1 6 Page 4 of 22 TEWS gt TECHNOLOGIES List of Figures FIGURE 1 1 DIAGRAM ente terree 6 FIGURE 6 1 SOLDER PAD L n eret nr sense trs tenete tenent 20 TABLE 2 1 TABLE 3 1 TABLE 3 2 TABLE 3 3 TABLE 3 4 TABLE 3 5 TABLE 4 1 TABLE 4 2 TABLE 4 3 TABLE 5 1 TABLE 5 2 TABLE 6 1 TABLE 6 2 TABLE 7 1 TPMC310 User Manual Issue 1 1 6 List of Tables TECHINICAL SPECIFICATION u uu uuu aasma pasqa 7 PCI9030 LOCAL SPACE CONFIGURATION 8 PLD REGISTER SPACE uuu tree est eder ede tva rase it ec bua aqha 8 CONTROL REGISTER u eere petet ie Eie esr e rhe 9 STATUS REGISTER aw icv ette ede spe reo Ete scr GL aspa 10 CAN CONTROLLER REGISTER SPAQCE eene eere rennen 11 PGI9030 POL HEADER ite E d tara 12 PCI9030 LOCAL CONFIGURATION REGISTER esee eene nennen 14 CONFIGURATION EEPROM iiie 15 OUTPUT CONTROL REGISTER ite ettet eret aaa 17 CLOCK DIVIDER REGISTER J aaa det eet 18 VO LINE CONFIGURATION s iriure etcetera 19 FACTORY DEFAULT I O LINE CONFIGURATION rennen menm 19 P14 I O PIN ASSIGNMENT nennen nnne 22 Page 5 of
7. 22 TEWS 2 gt TECHNOLOGIES Product Description The TPMC310 is a conduction cooled single width 32 bit PMC module providing a two channel high speed CAN bus interface The PLX Technology PCI9030 PCI Target Chip is used for the PCI bus interface Two Philips SJA1000 CAN Controllers CAN specification 2 0B supported are used for the CAN bus interface one for each channel The CAN bus I O interface provides two independent channels isolated from system logic and from each other CAN High Speed transceivers are used for the CAN bus I O interface An on board termination option solder pads is provided for each CAN bus channel allowing to configure on board termination and or pass through mode for the CAN bus The TPMC310 uses the P14 I O connector for the CAN bus I O interface CAN CH2 CAN CH2 CAN CH2 Power amp Signal Isolation Transceiver Term Opt CAN CH1 CAN CH1 CAN CH1 Power amp Signal Isolation Transceiver Term Opt SJA1000 CAN Controller Figure 1 1 Block Diagram TPMC310 User Manual Issue 1 1 6 Page 6 of 22 TEWS gt TECHNOLOGIES Technical Specification Mechanical Interface Logic Interface PCI Mezzanine Card PMC Interface Conduction Cooled Single Size Electrical Interface PCI Rev 2 1 compliant 33 MHz 32 bit PCI Universal PCI Signaling Voltage 3 3V PCI Signaling Voltage 5V PCI Signaling Voltage tolerant On board Devices PCI Target Chip PCI9030 PLX
8. PCI9030 local configuration register CNTRL offset 0x50 CNTRL 30 PCI Adapter Software Reset Value of 1 resets the PCI9030 and issues a reset to the Local Bus LRESETo asserted The PCI9030 remains in this reset condition until the PCI Host clears this bit The contents of the PCI9030 PCI and Local Configuration Registers are not reset The PCI9030 PCI Interface is also not reset TPMC310 User Manual Issue 1 1 6 Page 16 of 22 TEWS gt TECHNOLOGIES 5 Programming Hints 5 1 CAN Controller SJA1000 Clock Source The SJA1000 clock input frequency is 16 MHz for both SJA1000 CAN controllers Reset Mode After power up or board reset the SJA1000 CAN controllers are held in reset mode To bring the SJA1000 CAN controllers out of reset mode the CANx_RST bit s in the CAN Control Register PLD Register Space must be set Silent Mode After power up or board reset the CAN bus transceivers are held in silent mode To bring the CAN bus transceivers to operating mode the CANx SEL bit s in the CAN Control Register PLD Register Space must be set Note A CAN bus transceiver must only be set to operating mode when the CAN controller is also set to operating mode or already is in operating mode A CAN bus transceiver shall not be set to operating mode while the CAN controller is in Reset Mode Output Control Register The SJA1000 Output Control Register must be programmed as follows for both SJA1000 CAN controllers i
9. Technology CAN Controller CAN Bus Transceiver 2 x SJA1000 Philips 16 MHz 2 x TJA1050 Philips Interface Number of CAN Bus Channels 2 isolated from system logic and from each other CAN Bus Interface CAN High Speed The TJA1050 High Speed CAN Transceiver supports baud rates from 60 kbaud up to 1 Mbaud Connector PMC P14 I O 64pin Mezzanine Connector Physical Data Power Requirements 50mA typ 3 3V DC 150mA typ 5 0V DC Temperature Range Operating 40 C to 85 C Storage 55 to 125 C MTBF 372000 h MTBF values shown are based on calculation according to MIL HDBK 217F and MIL HDBK 217F Notice 2 Environment Gg 20 C The MTBF calculation is based on component FIT rates provided by the component suppliers If FIT rates are not available MIL HDBK 217F and MIL HDBK 217F Notice 2 formulas are used for FIT rate calculation Weight Humidity 759 5 95 non condensing TPMC310 User Manual Issue 1 1 6 Table 2 1 Technical Specification Page 7 of 22 TEWS gt TECHNOLOGIES 3 Local Space Addressing 3 1 PCI9030 Local Space Configuration The local on board addressable regions are accessed from the PCI side by using the PCI9030 local spaces PCI9030 PCI9030 PCI Size Port Endian Description Local PCI Address Space Byte Width Mode Space Offset in PCI Mapping Bit Configuration Space 0
10. 0001 0x18 Local Re map Register Space 1 0x0000_1001 0x1G Local Re map Register Space 2 0x0000_0000 0x20 Local Re map Register Space 3 0x0000_0000 0x24 Local Re map Register ROM 0x0000_0000 0x28 Local Address Space 0 Descriptor 0x1500_C0A0 0x2G Local Address Space 1 Descriptor 0x1502_4120 0x30 Local Address Space 2 Descriptor 0x0000_0000 0x34 Local Address Space 3 Descriptor 0x0000_0000 0x38 Local Exp ROM Descriptor 0x0000_0000 0x3G Chip Select 0 Base Address 0x0000_0009 0x40 Chip Select 1 Base Address 0x0000_1081 0x44 Chip Select 2 Base Address 0x0000_1181 0x48 Chip Select 3 Base Address 0x0000_0000 0x4G Interrupt Control Status 0x0049 0x4E EEPROM Write Protect Boundary 0x0030 0x50 Miscellaneous Control Register 0x0078_0000 0x54 General Purpose I O Control 0x0224_9252 0x70 Hidden1 Power Management 0x0000_0000 0x74 Hidden 2 Power Management 0x0000_0000 Table 4 2 PCI9030 Local Configuration Register TPMC310 User Manual Issue 1 1 6 Page 14 of 22 TEWS gt TECHNOLOGIES 4 3 Configuration EEPROM After power on or PCI reset the PCI9030 loads initial configuration register data from the on board configuration EEPROM The configuration EEPROM contains the following configuration data e Address 0x00 to 0x27 PCI9030 PCI Configuration Register Values e Address 0x28 to 0x87 PCI9030 Local Configuration Register Values e Address 0x88 to OxFF Reserved See the PCI9030 Manual for more information Address Offset
11. 1 1 6 Page 20 of 22 TEWS gt TECHNOLOGIES 7 Pin Assignment The complete TPMC310 I O interface is available on the 64 pin P14 mezzanine connector back I O Pin Signal Interface joe 1 Reserved 2 Reserved 3 Reserved I I I 4 NC 5 Reserved 6 Reserved 7 Reserved I i I 8 NC 9 Reserved 10 Reserved 11 Reserved I I I 12 NC 13 Reserved 14 Reserved 15 Reserved I I I 16 NC 17 NC 18 NC 19 NC 20 NC 21 CAN CH1 P 22 CAN CH1 N 23 GND errs 24 NC 25 CAN CH1 P 26 CAN CH1 CAN HS 27 GND Node Out 28 NC 29 NC 30 NC 31 NC 32 NC 33 CAN_CH2_P 34 35 GND SONS vn on 36 NC 37 CAN_CH2_P CAN HS N A CAN TPMC310 User Manual Issue 1 1 6 Page 21 of 22 TEWS gt TECHNOLOGIES Pin Signal Interface pomis i Mad 38 CAN CH2 N Nude ui 39 2 GND 40 NC 41 NC 64 Table 7 1 P14 I O Pin Assignment Be sure that the P14 connector signals used by the TPMC310 including the reserved pins are available and not otherwise used on the J14 connector of the PMC carrier board The Out Node for each CAN channel is only available if the on board I O line configuration is set accordingly pass through mode TPMC310 User Manual Issue 1 1 6 Page 22 of 22
12. 2 0x18 MEM 16 8 BIG PLD Register Space 1 3 0x1C MEM 512 8 BIG CAN Controller Register Space 2 4 0x20 Used 3 5 0x24 Not Used Table 3 1 PCI9030 Local Space Configuration 3 2 PLD Register Space PCI Base Address PCI9030 PCI Base Address 2 Offset 0x18 in PCI9030 PCI Configuration Register Space Offset to PCI Register Name Size Base Address Bit 0x00 CAN CONTROL REGISTER 8 0x01 CAN STATUS REGISTER 8 0x02 OxOF Reserved 8 Table 3 2 PLD Register Space TPMC310 User Manual Issue 1 1 6 Page 8 of 22 TEWS 2 TECHNOLOGIES 3 2 1 CAN Control Register Bit Name Function Access Reset 7 6 Reserved Undefined for reads write as 0 X CANBINTEN GAN CH2 Enabled a cane SEL 1 CAN CH2 Transceiver Operating Mode iudi K canz ST GAN CH2 Contoler Operating Mode iut M 2 CANLINTEN CAN CH1 Enabled 1 CANT_SEL 1 GAN CH1 Transosiver Operating Mode iu M o CAN CH1 Controler Operating Mode Table 3 3 CAN Control Register After power up or board reset the CAN controllers are set to reset mode To set the CAN controllers to operating mode the CANx_RST bit must be set to 1 After power up or board reset the CAN bus transceivers are set to silent mode To set the CAN bus transceivers to operating mode the CANx_SEL bit must be set to
13. ase address to the PCI9030 PCI Base Address Register For PCI Memory Space mapping the mapped address region must comply with the definition of bits 3 1 of the PCI9030 PCI Base Address Register After programming the PCI9030 PCI Base Address Registers the host software must enable the PCI9030 for PCI WO and or PCI Memory Space access in the PCI9030 PCI Command Register Offset 0x04 To enable PCI I O Space access to the PCI9030 bit 0 must be set to 1 To enable PCI Memory Space access to the PCI9030 bit 1 must be set to 1 TPMC310 User Manual Issue 1 1 6 Page 13 of 22 TEWS 2 TECHNOLOGIES 4 2 Local Configuration Register LCR After reset the PCI9030 Local Configuration Registers are loaded from the on board serial configuration EEPROM PCI Base Address PCI9030 PCI Base Address 0 PCI Memory Space Offset 0x10 in PCI9030 PCI Configuration Register Space or PCI9030 PCI Base Address 1 PCI Space Offset 0x14 in PCI9030 PCI Configuration Register Space Do not change hardware dependent bit settings in the PCI9030 Local Configuration Registers Offset to PCI Base Register Value Address 0x00 Local Address Space 0 Range OxOFFF FFFO 0x04 Local Address Space 1 Range OxOFFF 0x08 Local Address Space 2 Range 0x0000 0000 0x0G Local Address Space 3 Range 0x0000_0000 0x10 Local Exp ROM Range 0x0000_0000 0x14 Local Re map Register Space 0 0x0000_
14. er description TPMC310 User Manual Issue 1 1 6 Page 11 of 22 4 PCI9030 Target Chip 4 1 PCI Configuration Registers PCR 4 1 1 9030 PCI Header TEWS gt TECHNOLOGIES PCI CFG Write 0 to all unused Reserved bits PCI Initial Values Register writeable Hex Values Paares ee 24 23 16 15 8 7 0 0x00 Device ID Vendor ID N 0136 1498 0x04 Status Command Y 0280 0000 0x08 Class Code Revision ID N 028000 00 0x0C BIST Header Type PCI Latency Cache Line Y 7 0 00 00 00 00 Timer Size 0x10 PCI Base Address 0 for MEM Mapped Config Registers Y FFFFFF80 0x14 PCI Base Address 1 for I O Mapped Config Registers Y FFFFFF81 0x18 PCI Base Address 2 for Local Address Space 0 Y FFFFFFFO 0x1C PCI Base Address 3 for Local Address Space 1 Y 0x20 PCI Base Address 4 for Local Address Space 2 Y 00000000 0x24 PCI Base Address 5 for Local Address Space 3 Y 00000000 0x28 PCI CardBus Information Structure Pointer N 00000000 0x2C Subsystem ID Subsystem Vendor ID N s b 1498 0x30 PCI Base Address for Local Expansion ROM Y 00000000 0x34 Reserved New Cap Ptr N 000000 40 0x38 Reserved N 00000000 Lat Min Interrupt Pin Interrupt Line Y 7 0 00 00 01 00 0x40 PM Cap PM Nxt Cap PM Cap ID N 4801 00 01 0x44 PM Data PM CSR EXT PM CSR Y 00 00 0000 0x48 Reserved HS CSR HS Nxt Cap HS Cap ID Y 23 16 00 00 00 06 0x4C VPD Add
15. he TPMC310 is considered to be used in a vibration sensitive environment Possible line configuration options for each of the two I O channels CAN CH1 CAN CH2 are e On board Termination Mode on off e Bus Mode bus end pass through The on board termination option for a CAN I O channel node input see P14 I O pin assignment is a 120 ohm split termination network For the bus end option the I O lines are NOT passed through from the node input pins to the node output pins of the P14 I O connector The node input pins must be used to connect the CAN bus lines see P14 pin assignment For the pass through option the I O lines are passed through from the node input pins to the node output pins of the P14 I O connector see P14 I O pin assignment Termination Mode Bus Mode On board On board Termination On Termination Off zus oa CAN CH1 R42 R43 Closed R42 R43 Open R35 R45 Open R35 R45 Closed CAN CH2 R37 R38 Closed R37 R38 Open R33 R40 Open R33 R40 Closed Table 6 1 Line Configuration Termination Mode Bus Mode CAN CH1 On Bus End CAN CH2 On Bus End Table 6 2 Factory Default Line Configuration TPMC310 User Manual Issue 1 1 6 Page 19 of 22 TEWS E TECHNOLOGIES 6 2 Solder Pad Location TPMC310 PCB Top View Upper Right Corner 3 C5 5 318 C321 1 29 Figure 6 1 Solder Pad Location TPMC310 User Manual Issue
16. mation If enabled the CAN CH1 interrupt source is mapped to the PCI9030 LINT1 local interrupt input If enabled the CAN CH2 interrupt source is mapped to the PCI9030 LINT2 local interrupt input The PCI9030 LINTx local interrupt inputs are used in active low level sensitive mode The CAN interrupts must be acknowledged via SJA1000 registers CAN Controller Register Space Please see the SJA1000 CAN Controller Manual for more information TPMC310 User Manual Issue 1 1 6 Page 10 of 22 TEWS gt TECHNOLOGIES 3 2 3 CAN Controller Register Space PCI Base Address PCI9030 PCI Base Address 3 Offset 0x1C in PCI9030 PCI Configuration Register Space Offset to PCI Register Name Size Base Address Bit CAN Controller Channel 1 0 000 Controller CH1 Address 0 0x001 CAN Controller CH1 Address 1 0x002 CAN Controller CH1 Address 2 8 0x07F CAN Controller CH1 Address 127 dec 8 0x080 OXOFF Reserved CAN Controller Channel 2 0x100 CAN Controller CH2 Address 0 0x101 CAN Controller CH2 Address 1 0x102 CAN Controller CH2 Address 2 Oxi7F CAN Controller CH2 Address 127 dec 8 0x180 OX1FF Reserved Table 3 5 CAN Controller Register Space The CAN controllers must be set to operating mode CAN Control Register in PLD Register Space before CAN controller register access Please see the SJA1000 CAN Controller Manual for a detailed regist
17. n the SJA1000 controller internal reset mode see SJA1000 Control Register in the SJA1000 CAN Controller Manual Bit Symbol Description 7 OCTP 1 11 Push Pull output stage 6 OCTN1 5 OCPOL1 0 Normal polarity 4 OCTPO 11 Push Pull output stage 3 OCTNO 2 OCPOLO 0 Normal polarity 1 OCMODE 1 01 Test Output Mode 0 OCMODEO 10 Normal Output Mode Table 5 1 Output Control Register TPMC310 User Manual Issue 1 1 6 Page 17 of 22 TEWS gt TECHNOLOGIES Clock Divider Register The SJA1000 Clock Divider Register must be programmed as follows for both SJA1000 CAN controllers in the SJA1000 controller internal reset mode see SJA1000 Control Register in the SJA1000 CAN Controller Manual Bit Symbol Description 0 BasiCAN Mode CANMODE 1 PeliCAN Mode 6 CBP 1 Bypass input comparator use only 5 RXINTEN 0 Disable Interrupts on TX1 output 4 0 3 CLOCK OFF 1 Disable Clock Output not used 2 CD2 0 1 CD1 0 0 CDO 0 Table 5 2 Clock Divider Register Baud Rate Range The TPMC310 uses the TJA1050 High Speed CAN transceiver The TJA1050 High Speed CAN Transceiver supports baud rates from 60 kbaud up to 1 Mbaud TPMC310 User Manual Issue 1 1 6 Page 18 of 22 TEWS gt TECHNOLOGIES 6 Configuration Hints 6 1 Line Configuration The line configuration is configured by on board solder pads there is no jumper solution because t
18. ress VPD Nxt Cap VPD Y 31 16 0000 00 03 0x50 VPD Data Y 00000000 Subsystem ID Table 4 1 PCI9030 PCI Header TPMC310 10R 0x000A TPMC310 User Manual Issue 1 1 6 Page 12 of 22 TEWS gt TECHNOLOGIES 4 1 2 PCI Base Address Initialization PCI Base Address Initialization is scope of the PCI host software PCI9030 PCI Base Address Initialization 1 Write OxFFFF_FFFF to the PCI9030 PCI Base Address Register 2 Read back the PCI9030 PCI Base Address Register 3 For PCI Base Address Registers 0 5 check bit 0 for PCI Address Space Bit 0 0 requires PCI Memory Space mapping Bit 0 1 requires PCI I O Space mapping For the PCI Expansion ROM Base Address Register check bit 0 for usage Bit 0 0 Expansion ROM not used Bit 0 1 Expansion ROM used 4 For PCI I O Space mapping starting at bit location 2 the first bit set determines the size of the required PCI I O Space size For PCI Memory Space mapping starting at bit location 4 the first bit set to 1 determines the size of the required PCI Memory Space size For PCI Expansion ROM mapping starting at bit location 11 the first bit set to 1 determines the required PCI Expansion ROM size For example if bit 5 of a PCI Base Address Register is detected as the first bit set to 1 the PCI9030 is requesting a 32 byte space address bits 4 0 are not part of base address decoding 5 Determine the base address and write the b
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