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SIS3400 CDMS II VME TDC/Time Stamper User Manual

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1. Bit Function 31 clear reserved 15 30 disable IRQ source 2 29 disable IRQ source 1 28 disable IRQ source 0 27 clear reserved 11 26 clear reserved 10 25 clear reserved 9 24 clear reserved 8 23 set reserved 15 22 enable IRQ source 2 test 21 enable IRQ source input counter IRQ Counter overflow toggle bit 20 20 enable IRQ source 0 formatter 19 set reserved 11 18 set reserved 10 17 set reserved 9 16 set reserved 8 15 Disable input test 14 Enable clock master 13 Disable control input inversion 12 Disable front panel control inputs 11 Disable 1 MHz CLOCK 10 Disable 10 MHz CLOCK 9 clear IRQ test source 2 8 switch off user LED 7 Enable input test 6 Disable clock master 5 Enable control input inversion 4 Enable front panel control inputs 3 Enable 1 MHz CLOCK 2 Enable 10 MHz CLOCK 1 set IRQ test source 2 0 switch on user LED denotes the default power up or key reset state Page 17 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 8 3 Module Identification and IRQ control register 0x4 This register has two basic functions The first is to give information on the active firmware design This function is implemented via the read only upper 20 bits of the register Bits 16 31 hold t
2. RNI7A 17B 18A 18B 49 50 51 52 53 54 55 56 RN19A 19B 20A 20B 57 58 59 60 61 62 63 64 12 Connector Specification The two different types of front panel and VME connectors used on the SIS3400 CDMS II are Connector Purpose Part Number 160 pin zabcd VME P1 P2 Harting 02 01 160 2101 LEMOOO Control in output LEMO EPB 00 250 N TN 68 pin Input Thomas amp Betts HFRO68RA29JSI Page 34 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 13 Signal Specification 13 1 Control Signals The width of the start and stop pulse has to be greater or equal 15 ns the maximum external clock shall not exceed 10 MHz the wave form has to be symmetric 13 2 Inputs The SIS3400 control section is designed for high active TTL inputs by default the module is shipped with 50 Ohm input termination Logic Level Level in V 0 0 8 1 gt 2 4 The forbidden range between the high and low level can result in undefined states If 1K input termination is chosen open inputs will be seen as 1 control input inversion can be used to redefine them as 0 SIS3400 CDMS II inputs are designed for RS485 levels the receiver input sensitivity is 200 mV refer to www rs485 com for details 14 Operating Conditions 14 1 Power Consumption Voltage requirement To allow for the use of the SIS3400 independent of the users VME crate
3. 7 read only No function read 0 6 read only No function read 0 5 read only No function read 0 4 read write Module Address Bit 4 used in data stream 3 read write Module Address Bit 3 used in data stream 2 read write Module Address Bit 2 used in data stream 1 read write Module Address Bit 1 used in data stream 0 read write Module Address Bit 0 used in data stream The power up value of the register is 0x00000000 8 6 FIFO Flag Register 0x108 read only The status of the input FIFO group and the output FIFO group can be retrieved from this read only register In most cases the evaluation of the FIFO flag register of all frontend modules will be a good way to control overall readout As an alternative the FIFO flags can be used to generate interrupts with the interrupt service routine handling readout Bit Read Function 31 0 16 0 15 0 14 0 13 0 12 Input FIFO flag full 11 Input FIFO flag almost full 10 Input FIFO flag half full 9 Input FIFO flag almost empty 8 Input FIFO flag empty 7 0 6 0 5 0 4 Output FIFO flag full 3 Output FIFO flag almost full 2 Output FIFO flag half full 1 Output FIFO flag almost empty 0 Output FIFO flag empty The reading of the status register after power up or key reset is 0x303 Page 21 of 47 SIS Documentation SIS3400 CDMSII TDC Time Stamper 8
4. SIS Documentation SIS3400 CDMSII SIS GmbH A TDC Time Stamper VME 9 VME Interrupts Three VME interrupt sources are implemented in the SIS3400 firmware design e output FIFO flag e 20 bit counter roll over e test For compatibility with the LINUX Universe driver the interrupts were implemented in release on acknowledge ROAK style Interrupt generation has to be enabled by setting bit 11 in the IRQ and version register The internal VME interrupt flag can be used to check on an IRQ condition without actually making use of interrupts on the bus The VME interrupt level 1 7 are defined by bits 8 through 10 and the VME interrupt vector 0 255 by bits O through 7 of the VME IRQ and version register Find a diagram with the overall interrupt mechanism of the SIS3400 below Internal IRQ Test Enable 2 Sl 20 bit toggle gt clear Enable 1 VME IRQ clear FIFO enable Flags register Enable 0 Ni IRQ ACK Enable IRQ Page 32 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 10 Data Format At present two formatter data formats are implemented the so called single wire mode and the so called event mode In single wire mode two 32 bit words per hit i e bit change 01 are written to the output FIFO The new status of all 64 input bits is written to the output FIFO in multi wir
5. TDC Time Stamper VME 17 6 Row d and z Pin Assignments The SIS3400 is ready for the use with VME64x and VME64xP backplanes Features include geographical addressing and live insertion hot swap The prepared used pins on the d and z rows of the P1 and P2 connectors are listed below Position P1 J1 P2 J2 Row z Row d Row z Row d 1 VPC 1 2 GND GND 1 GND 3 4 GND GND 5 6 GND GND 7 8 GND GND 9 GAP 10 GND GAO GND 11 RESP GAI 12 GND GND 13 GA2 14 GND GND 15 GA3 16 GND GND 17 GA4 18 GND GND 19 20 GND GND 21 22 GND GND 23 24 GND GND 25 26 GND GND 27 28 GND GND 29 30 GND GND 31 GND 1 GND 1 32 GND VPC 1 GND VPC 1 Note Pins designated with 1 are so called MFBL mate first break last pins on the installed 160 pin connectors VPC 1 pins are connected via inductors Page 44 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 17 7 Geographical Address Pin Assignments The SIS3400 board can be used with geographical addressing via the geographical address pins GAO GA1 GA2 GA3 GA4 and GAP The address pins are left open or tied to grou
6. 64K FIFO chips as long as the availability of sufficient space for the event is insured Event processing pauses as long as the FIFO almost full condition if flagged by the output FIFOs If the VME CPU side can not cope with the output data rate the input FIFO stage will finally reach the almost full condition as well and the Veto output will be set Note the sustained input data rate of the input FPGAs of a SIS3400 which is clocked at 10 MHz 100 ns time bins is 80 Mbyte s 8 byte x 10 MHz Page 6 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 3 2 SIS3400 CDMS II input stage firmware The SIS3400 CDMS II input stage firmware is edge sensitive Input channels with a leading edge within the time slice clock cycle will have their corresponding bit set in the input data word To allow for maximum flexibility the inputs can be inverted in the input stage FPGAs via the two input stage inversion registers Data words with one or more leading edges will be stored in the input FIFO stage with the corresponding counter value written to the time stamp FIFO upon the next leading edge of the clock While single wire and event mode are still available as formatter data handling options it is obvious that no leading trailing edge recognition is available The formatter processing time depends on the selected mode of operation In multi wire mode it is in the order of 1 us in single wire it is in the order of 5 us T
7. 8 read only No function read as O JA read write reserved read as O 6 read write reserved read as O 5 read write reserved read as O 4 read write reserved read as O 3 read write reserved read as O 2 read write reserved read as O 1 read write reserved read as O 0 read write TIME Shadow Register freeze bit The power up reading is 0x00000000 8 11 Input inversion group 1 register 0x204 After power up the SIS3400 CDMS II latches leading edge transitions as 1 Trailing edges can be selected for input channels 64 to 33 by setting bit O of this register Bit Read Write access Function 31 read only No function read as O 8 read only No function read as O 7 read write reserved read as O 6 read write reserved read as O 5 read write reserved read as O 4 read write reserved read as O 3 read write reserved read as O 2 read write reserved read as O 1 read write reserved read as O 0 read write Input group 1 channels 64 33 inversion mode The power up reading is 0x00000000 Page 24 of 47 SIS Documentation SIS3400 CDMSII TDC Time Stamper SIS GmbH VME 8 12 Input Group 1 FIFO test registers 0x210 0x214 0x218 0x21C Data can be written to the input FIFO through the four input groupl FIFO test registers and the four input group 2 FIFO test registers The data are copied to the input FIFO with a key address 0x38 acce
8. Test register 6 for Input FIFO Test 0x314 sse nennen Re ee ee ee ene 29 8 16 3 Test register 7 for Input FIFO Test 0x318 ee se se se Ge GR ee Gee ee ee Ge Se Ge eene nennen 29 8 16 4 Test register 8 for Input FIFO Test 0XB1C ese see se see ee Ge ee ee ee ee Ge Se Ge eene enne 29 8 17 Input Buffer Group 2 registers 0x320 0x324 0x328 UN 30 8 17 1 Input Buffer 0X320 eben ere re REI E EE A ee eer RES 30 8 17 2 Input Buffer 6 OX324 iier ert rete ER RE ER GED SR Ee GREG REG ER ER Ee GR ne Ee ER Ge eee Peoria s 30 8 L73 Input Buffer 7 OX328 sce EE ER EE EE EI EO ET N 30 SATA Input B ffer 8 HI SUS ER RE ER EE OE EE WO ER 30 8 18 Output FIFO 0x8000 0xFFFC or 0x10000 to Ox IPC 31 H VME Interrupts deeem dete eee OE ario ita 32 10 Data Format ioc e AE SEE EE ER EE RE EE Eee Fern 33 Page 3 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH I TDC Time Stamper VME 10 1 Single Wire mode eee eerte eni et ert tege eoe d ente eI erre Seg 33 10 2 Multiwire mod e itte eit EE iaa 33 11 Input Config ration eic etie eem led tete EE eb eset ic eden 34 12 Connector Specific itunes 34 13 Signal Specification ie EE RE EE RE EE EG 35 131 tree oett iet top tet EE RR EE OE 35 13 2 Inputs eee eletti P OE ee atate EG 35 14 Operating Conditions i ee EE etii bett dilatada 35 14 1 Power Consumption Voltage requirement ee ee Se ee nennen tren nennen rennen ee erret 35 ES Us REK EE IE EE EE EE EE t
9. external or VME key select input inversion inputs 64 33 and 32 1 1f required select control input inversion if required see section 6 enable front panel control inputs select formatter mode single wire e g set formatter module address if desired enable input control logic starts counter arms for start stop A good way of checking first time communication with the SIS3400 consists of switching on the user LED by a write to the control register at offset address 0x0 with data word 0x1 the LED can be switched back off by writing 0x100 to the control register Getting started address bit table Function Address offset Datum to write Key reset 0x20 arbitrary Define clock receiver 0x0 0x40 omit for first module in chain Define clock source 0x0 0x8 1 MHz omit for front panel clock or VME key 0x4 10 MHz Select input inversion inputs 64 33 0x204 0x1 if required Select input inversion inputs 32 0x304 0x1 if required Select control input inversion 0x0 0x50 if required Enable front panel control inputs 0x0 0x10 ored with VME control Select formatter mode select single wire 0x100 0x1 mode omit for multi wire mode Set formatter module address 0x104 0x0 0x1F omit if O is fine with you Enable input control logic 0x28 arbitrary Page 10 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME b Front Panel LEDs The
10. interrupter type input buffer 3 introduction input buffer 4 TRO SOURCES aere ee bent eie tenes input buffer 5 J1 10 13 40 input buffer 6 EE RT TN 10 input buffer 7 AE E OR OR OE ERS 40 input buffer 8 LU te 40 input buffer group 1 Jumper input buffer group 2 OVeIMIE Wxi EE EE 40 input group 1 FIFO test key address iia eiii 14 input group 1 inversion key reset bes input group 2 FIFO test input group 2 inversion input group Control MBETOE 2 isole re rne oe es EE ss 6 33 THetri6 etse De EE ER EE di 5 mode Ai EE RE EE 7 33 A OE ee N 10 single WITS EE EE dre Ee Geet 7 20 33 Module Identification and IRQ control register 14 18 module number a PEE RENS 18 Operating Conditions iese see se see 35 output oe diie sdanevees power consumption HA Power Consumption eee register vod 36 fifo lag OR EE AA 21 FIFO flag IRQ enable eee 22 formatter control m formatter module address 21 inp t buffer T eie RE eere 26 ele dE He input group control status input inversion group le input inversion group 7 ouput FIFO test ein id die ok trt terere ia EN AA EX a aR Signal Specification Control Software Support Status Register SE EE Eg bee RE Ee nee Midi EE ER Pap teabgs 10 13 40 LO 13 40 Technical Properties Features eese 6 termination Tundra Un
11. no non standard voltage is used by the board In especial the card is a single supply 4 5 V design The 43 3 V supply voltage for the on board FPGAs is generated by linear regulators The actual power consumption of the module will vary with input data rate and may also depend on the actual firmware Operating conditions Voltage in V Current in A SIS3400 Idle 5 2 2 SIS3400 Clock 20 MHz t5 SIS3400 CDMSII Idle 5 2 4 14 2 Cooling Forced air flow is required for the operation of the SIS3400 board 14 3 Insertion Removal Please note that the VME standard does not support live insertion hot swap Hence crate power has to be turned off for installation and removal of SIS3400s in standard VME crates The leading pins on the SIS3400 VME64x VME connectors and connected on board circuitry are designed for hot swap in conjunction with a VME64x backplane a VME64x backplane can be recognised by the 5 row VME connectors while the standard VME backplane has three row connectors only Page 35 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH I TDC Time Stamper VME 15 Test The SIS3400 provides a number of test features which allow for debugging of the unit as well as for overall system setup tests 15 1 LED selftest During power up self test and LCA configuration all LEDs except the Ready R LED are on After the initialisation phase is completed all LEDs except the Ready R Power P and Disab
12. 28 Status VME IRQ source 0 Overflow 27 VME IRQ 26 internal VME IRQ 23 0 24 0 23 Status reserved 15 22 Status VME IRQ Enable Bit Source 2 21 Status VME IRQ Enable Bit Source 1 20 Status VME IRQ Enable Bit Source 0 19 Status reserved 11 18 Status reserved 10 17 Status reserved 9 16 Status reserved 8 15 Global INPUT Control Logic Enable bit 14 Gate reflects current gate status 13 0 12 0 11 0 10 0 9 0 8 0 7 Status input test 6 Status clock synchroniser 5 Status front panel input inversion 4 Status front panel control input 3 Status Enable 1 MHz CLOCK 2 Status Enable 10 MHz CLOCK 1 Status IRQ source 2 for software IRQ testing 0 Status user LED The power up or key reset content is 0x0 see default settings of control register Page 16 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 8 2 Control Register 0x0 The control register is in charge of the control of most of the basic properties of the SIS3400 board in write access It is implemented via a selective J K register a specific function is enabled by writing a 1 into the set enable bit the function is disabled by writing a 1 into the clear disable bit which has a different location within the register An undefined toggle status will result from setting both the enable and disable bits for a specific function at the same time On read access the same register represents the status register
13. 400 can be loaded off a FLASHPROM or via JTAG In FLASHPROM boot mode up to four different boot files can be selected with the possible combinations of jumpers M3 and M4 J34 Jumper Function Factory default e e MI Reserved closed alo m3 Mi Boot mode selection closed FLASH open JTAG closed ala M M3 Boot file BitO closed 0 open 1 closed M4 Boot file Bitl closed 0 open 1 closed Note The factory default setting M2 M3 and M4 closed boots file O from the FLASHPROM For the SIS3400 clock distribution firmware the setting is M2 closed M3 open M4 closed boot file 1 from FLASH Page 40 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH I TDC Time Stamper VME 17 3 3 SW1 and SW2 Base Address Selection The two hexadecimal rotary switches SW1 and SW2 are used to define the VME base address in systems without geographical addressing capabilities i e if standard VME crates are used The two switches are labelled ADR LO SW1 and ADR UP SW2 as they define the lower and upper address nibble of the eight leading address bits A31 to A24 with A32 enabled and addressed A23 to A16 with A24 enabled and addressed The setting of the two switches is ignored if a geographical addressing mode GEO or VIPA is enabled Page 41 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 17 4 Board Layout RESDIBIT e IT MNN PAS gri aL 08 U33 al i WUU L
14. 64 57 0x234 R D32 Time Shadow Register 2 Bits 56 49 0x238 R D32 Time Shadow Register 3 Bits 48 41 0x23C R D32 Time Shadow Register 4 Bits 40 33 Input2 32 1 0x304 R W D32 Input inversion channel 32 1 Bit0 0 non inverting Bit0 1 inverting 0x310 R W D32 Test register 5 for Input FIFO Test input data 32 25 0x314 R W D32 Test register 6 for Input FIFO Test input data 24 17 0x318 R W D32 Test register 7 for Input FIFO Test input data 16 9 0x31C R W D32 Test register 8 for Input FIFO Test input data 8 1 0x320 R D32 Input Buffer 5 input data 32 25 0x324 R D32 Input Buffer 6 input data 24 17 0x328 R D32 Input Buffer 7 input data 16 9 0x32C R D32 Input Buffer 8 input data 8 1 0x8000 to R D32 Output FIFO on A24 access OxFFFC BLT32 MBLT64 Us 10000 R D32 Output FIFO on A32 access to BLT32 Ox1FFFC MBLT64 Note DOS and D16 are not supported by the SIS3400 board Page 15 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH 4 TDC Time Stamper VME 8 Register Description 8 1 Status Register 0x0 The status register reflects the current settings of most of the SIS3400 parameters in read access in write access it functions as the control register Bit Function 31 0 30 Status VME IRQ source 2 test IRQ 29 Status VME IRO source 1 ext clock shadow
15. 7 FIFO Flag IRQ Enable register 0x10C This read write register defines which condition s of the output FIFO will generate an interrupt for interrupt driven readout applications The optimum setting will depend on application data rate and performance of the VME master Bit Read Write access Function 31 read only No function read 0 16 read only No function read 0 15 read write reserved 14 read write reserved 13 read write reserved 12 read write reserved 11 read write reserved 10 read write reserved 9 read write reserved 8 Read write reserved 7 Read write reserved 6 Read write reserved 5 Read write reserved 4 Read write Enable IRQ if Output FIFO is full 3 Read write Enable IRQ if Output FIFO is almost full 2 Read write Enable IRQ if Output FIFO is half full 1 Read write Enable IRO if Output FIFO is NOT almost empty 0 Read write Enable IRO if Output FIFO is NOT empty Power up default value 0x00000000 Page 22 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 8 8 Output FIFO test registers 0x110 and 0x114 Data can be written to the 32 bit wide output FIFO through the upper and lower test register if output FIFO test mode is enabled To transfer the data of the two test registers to the FIFO a key address cycle to address 0x120 is required 8 8 1
16. EEDSs ise en OE KI OE EO OE KO ea eee ee EE AO EG 11 6 Front Panel Control In Outputs essent Re GRA RA Gee Gee Ge ee none cone Ge neon neon non neon nee enne ene 12 T SS OER EE EO ee OER OE OO EE EE OT 13 7 1 RR RE OR ER RR EK ER ER ENEE 13 7 2 Base Address soe eee ead ec s o eor HO ER we EE ET 13 7 2 1 VASE ER ihn ER ER oo ordei ee ait decies 13 7 3 Address Map EER ER OER EE EA OE AA OT OE EE OER e 14 8 Register Ps OER ER EN 16 8 1 Status Register 0x0 dci etre EE EO OER ER EE OE EE 16 8 2 Control Register OKO 4 EN tee n RT t esa eee dtr eite a dentada ve Re Qe cue did 17 8 3 Module Identification and IRQ control register USA 18 8 4 Formatter Control Status Register OslO0 ee se ee ee ee RA AR ee enne en nnne entre entere 20 8 5 Formatter Module Address register Ox104 ee se ee SR ee RA AR ee ee Re ee GR nnne ee ge ee ee 21 8 6 FIFO Flag Register 0x108 read only 21 8 7 FIFO Flag IRQ Enable register OX10CO see esse ee r ee GR ee Ge GR ee GR ee GR ee Ge AR ee Se enne 22 8 8 Output FIFO test registers 0x 110 and Ox1 14 se see ee ee ee Ge Se Ge ee Re nenne 23 8 8 1 Upper Test register for Output FIFO Test 0x1 IO 23 8 8 2 Lower Test register for Output FIFO Test 0x114 ee se se ee ee se ee ee ee ee ee Ge eene 23 8 9 Output FIFO word counter Ox118 eere eco ee ee eter eer ee ee idee geen 23 8 10 Input group 1 Control Status register 0x200 ee ee se GR RA Gee Ge ee ee Se Se Re Ge RA Re R
17. ILILI a Su2 SHL i l J34 Ji J Mi rata M2 RnB 7 M3 RACC J M4 RDC TO3T NA LEDB4LEDB3LEDB2LEDB1 u95 ces j ES Ml U74 J E ora ar A 7 pzz8 a L eeu SEED EJ El LC luss 4ESY ef SS dal N c27AC JE Jc4oo U40 WI e caca fgg sl ae 53 E Crue E ins Dous rg Ej Coca ES E3 BE CI TE ES em e sis GmbH 9 2000 eC A el nk bal ma L U54 LIG zeo J C nen gri x O red Dn DIO EJE JL er L2 Page 42 of 47 SIS Documentation SIS3400 CDMSII TDC Time Stamper SIS GmbH VME 17 5 FLASHPROM Versions A list of available FLASHPROMS can be obtained from http www struck de sis3400firm htm Please note that a special hardware configuration may be necessary for the firmware design of interest The table on the web is of the format shown below SIS3400 FLASHPROM table Design Name Design Boot File s SIS3400 020300 0 SIS3400 Version 1 SIS3400_200400 10 SIS3400 Version 2 clock module SIS3400_271000 0 SIS3400 Version 9 CDMS ID SIS3400_070501 O SIS3400 Version OxA CDMS ID SIS3400 200302 0 SIS3400 Version OxB CDMS ID Page 43 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH A
18. O Level Bit 1 8 read write VME IRO Level Bit 0 7 read write IRO Vector Bit 7 placed on D7 during VME IRQ ACK cycle 6 read write IRO Vector Bit 6 placed on D6 during VME IRQ ACK cycle 5 read write IRQ Vector Bit 5 placed on D5 during VME IRQ ACK cycle 4 read write IRQ Vector Bit 4 placed on D4 during VME IRQ ACK cycle 3 read write IRQ Vector Bit 3 placed on D3 during VME IRQ ACK cycle 2 read write IRQ Vector Bit 2 placed on D2 during VME IRQ ACK cycle 1 read write IRQ Vector Bit 1 placed on D1 during VME IRO ACK cycle 0 read write IRO Vector Bit 0 placed on DO during VME IRO ACK cycle Page 18 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH I TDC Time Stamper VME The second function of the register is interrupt control The interrupter type of the SIS3400 is D08 O ROAK Via bits 0 7 of the module identifier and interrupt control register you can define the interrupt vector which is placed on the VME bus during the interrupt acknowledge cycle Bits 8 through 10 define the VME interrupt level bit 11 is used to enable bit set to 1 or disable bit set to 0 interrupting Module identification and version example The register for a SIS3400 CDMSII reads 0x3400Bnnn the status of the lower 3 nibbles is denoted with n in the example Page 19 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 8 4 Formatter Control Status Register 0x100 The behaviour of the event formatter can be c
19. O OO 212 xu X X not decoded notdecoded S o o SISIS sls X not implemented in current firmware Shorthand Explanation SWI SW2 Setting of rotary switch SW1 or SW2 respective GAO GA4 _ Geographical address bit as defined by the VME64x P backplane The factory default setting for the SIS3400 CDMSII is shipped with SW2 set to 3 and SWI set to 4 and A32 and A24 enabled hence the module will respond to A32 0x34000000 and A24 0x340000 Page 13 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 7 3 Address Map The SIS3400 board is operated via VME registers and VME key address cycles output data are read from the FIFO The following table gives an overview on all SIS3400 addresses and their offset from the base address a closer description of the registers and their function is given in the following subsections Note Write access to a key address KA with arbitrary data invokes the respective action Offset Key Access Type Function 0x000 R W D32 Control and Status register 0x004 R W D32 Module Identification and IRQ control register 0x020 KA W D32 Global Reset like Power On clear time counter also from firmware rev OxA on 0x028 KA W D32 Enable INPUT Control Logic 0x02C KA W D32 Disable INPUT Control Logic 0x030 KA W D32 Start start of gate 0x034 KA W D32 Stop end of gate 0x038 KA W D32 INPUT Control CLOCK p
20. SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME SIS3400 CDMS II VME TDC Time Stamper User Manual SIS GmbH Harksheider Str 102A 22399 Hamburg Germany Phone 4449 0 40 60 87 305 0 Fax 49 0 40 60 87 305 20 email info Ostruck de http www struck de Version 1 20 as of 20 03 02 Page 1 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME Revision Table Revision Date Modification 0 1 26 10 00 Generation from 8183400 1 0 31 10 00 First official release 1 01 07 11 00 Missing registers added several additions 1 02 12 01 01 Experiment name fix gt CDMSII 1 03 15 01 01 Add missing control bits add getting started table 1 10 22 05 01 Firmware version Ox A FIFO word counter time counter reset upon global reset 1 20 20 03 02 Firmware version OxB TIME STAMP expanded to 32 bits Page 2 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 1 Table of contents Tableof e EE 3 2 el ete A OE aes 5 3 Technical Properties Ee tures ok Bie kt es e OE EE ces eG ee Be aac Bee RERO IEEE 6 3 1 Board DeSigm d DEE A EE ee 6 3 2 SIS3400 CDMS II input stage firmware se see se ss Gee Ge ee ee Ge Ge Re Ge RA Ge Gee ee be ee ee RR ee 7 3 2 1 Clock Synchroniser Clock receiver eese ene cnn conc ee nine cone GR RA Re ee 8 A Getting Started EE 10 gt Front Panel
21. SIS3400 CDMS II latches leading edge transitions as 1 Trailing edges can be selected for input channels 32 to 1 by setting bit O of this register Bit Read Write access Function 31 read only No function read as 0 8 read only No function read as O 7 read write reserved read as O 6 read write reserved read as O 5 read write reserved read as O 4 read write reserved read as O 3 read write reserved read as O 2 read write reserved read as O 1 read write reserved read as O 0 read write Input group 1 channels 32 1 inversion mode The power up reading is 0x00000000 Page 28 of 47 SIS Documentation SIS3400 CDMSII TDC Time Stamper SIS GmbH VME 8 16 Input Group 2 FIFO test registers 0x310 0x314 0x318 0x31C 8 16 1 Test register 5 for Input FIFO Test 0x310 8 16 3 Test register 7 for Input FIFO Test 0x318 Bit Read Write access Function Bit Read Write access Function 31 Read only No function read 0 31 Read only No function read 0 8 Read only No function read 0 8 Read only No function read 0 7 Read write Input Fifo Test Data Bit 31 7 Read write Input Fifo Test Data Bit 15 0 Read write Input Fifo Test Data Bit 24 0 Read write Input Fifo Test Data Bit 8 after power up 0x00000000 8 16 2 Test register 6 for Input FIFO Test 0
22. SIS3400 has 8 front panel LEDs to visualise part of the units status Three LEDs according to the VME64xP standard Power Access and Ready plus 5 additional LEDs VME user LED EVT DIS OVI and OVO LED Designation LED Color Function A Access yellow Signals VME access to the unit P Power red Flags presence of VME power R Ready green Signals configured logic U VME user LED green To be switched on off under user program control EVT Event yellow Signals one or more leading edges in time slice i e data word is copied to input FIFO DIS Disable red Signals disabled or no gate present state OVI Overflow Input green Signals input FIFO overflow OVO Overflow Output green Signals output FIFO overflow The LED locations are shown in the portion of the front panel drawing below AO OEVT PO ODIS RO Oov U O Qovo SIS GmbH CONTROL In Out The VME Access and the EVT LED are monostable i e the duration of the on phase is stretched for better visibility the other LEDs reflect the current status An LED test cycle is performed upon power up refer to chapter 15 1 Page 11 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH I TDC Time Stamper VME 6 Front Panel Control In Outputs Six control signals are implemented in the SIS3400 CDMSII design three inputs and three outputs Their location can be seen on the drawing above Input Output Clock Clock 1 Start Start S
23. Upper Test register for Output FIFO Test 0x110 Bit Read Write access Function 31 Read only No function read 0 16 Read only No function read 0 15 Read write Output Fifo Test Data Bit 31 0 Read write Output Fifo Test Data Bit 16 Power up default value 0x00000000 8 8 2 Lower Test register for Output FIFO Test 0x114 Bit Read Write access Function 31 read only No function read 0 16 read only No function read 0 15 read write Output Fifo Test Data Bit 15 0 read write Output Fifo Test Data Bit 0 after power up 0x00000000 8 9 Output FIFO word counter 0x118 The read only 16 bit wide output FIFO word counter is incremented with every word stored in the output FIFO It is reset upon global reset KA 0x20 or the clear all FIFO KA 0x130 command Page 23 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 8 10 Input group 1 Control Status register 0x200 The contents of the time shadow register can be frozen for readout by setting bit O of the input group control register to ensure that no changes occur while the actual time value is read from time shadow registers 1 through 4 Note there is no equivalent group 2 register Bit Read Write access Function 31 read only No function read as O
24. ata on the clock receiver modules to guarantee for synchronisation of all modules in the chain Starts and stops by front panel as well as by VME are synchronised to the clock as shown in the scope shot below the outgoing start stop pulse has a width of one clock period Note The user has to make sure to provide a symmetric external clock the internal 1 MHz clock is symmetric Page 8 of 47 SIS GmbH VME SIS Documentation SIS3400 CDMSII TDC Time Stamper Vp CEDE N seed 5ns 408 2 00Ve Chi 2 00 VO M 250ns Ch2 1 36 Y Source Coupling Slope TYPE e Edge che DC F The scope shot above shows the clock on the upper trace and the Edge Source chi AC X AC Line Auxiliary Rear Panel ode amp Holdoff synchronised start stop pulse on the lower trace Page 9 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH A TDC Time Stamper VME 4 Getting Started The minimum setup to operate the SIS3400 CDMSII requires the following steps Select the proper boot mode and firmware design with jumper J34 Select the VME addressing mode with jumper J1 Set the base address if a non geographical addressing mode is used with SW1 and SW2 turn VME crate power off install the module in the VME crate turn crate power back on issue a key reset define clock receiver 1f not first module in the chain define clock source 1 MHz internal 20 MHz internal
25. d incorrect reading caused by toggling bits it is recommended to freeze the time shadow register by setting bit O of the input group control register to read the time from the four time shadow registers and to unfreeze the time shadow register by clearing bit O of the input group control register again The time shadow register is updated with every clock tick as long as bit O of the input group control register is cleared 8 14 1 Time Shadow Register 1 8 14 3 Time Shadow Register 3 0x230 0x238 Bit Function Bit Function 31 No function read 0 31 No function read 0 8 No function read 0 8 No function read 0 7 Time Shadow Register Bit 31 7 Time Shadow Register Bit 15 0 Time Shadow Register Bit 24 0 Time Shadow Register Bit 8 8 14 2 Time Shadow Register 2 8 14 4 Time Shadow Register 4 0x234 0x23C Bit Function Bit Function 31 No function read 0 31 No function read 0 8 No function read 0 8 No function read 0 7 Time Shadow Register Bit 23 7 Time Shadow Register Bit 7 0 Time Shadow Register Bit 16 0 Time Shadow Register Bit 0 Page 27 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 8 15 Input inversion group 2 register 0x204 After power up the
26. e access Function Bit Read Write access Function 31 Read only No function read 0 31 Read only No function read 0 8 Read only No function read 0 8 Read only No function read 0 7 Read only Input Buffer Data Bit 23 7 Read only Input Buffer Data Bit 7 0 Read only Input Buffer Data Bit 16 0 Read only Input Buffer Data Bit 0 Page 30 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 8 18 Output FIFO 0x8000 0xFFFC or 0x10000 to Ox1FFFC The address range of the output FIFO First In First Out depends on the addressing mode Mode FIFO Address range A24 0x8000 0x8FFFC A32 0x 10000 0x 1FFFC The output FIFO consists of two 64Kx18 bit FIFO chips which are used in parallel to hold the formatted 32 bit wide output word Normally one address to read from would be sufficient for the FIFO but as most VME masters use address auto increment on block transfers a contiguous address block allows for more efficient readout The address range was chosen in a fashion that allows for the readout of half of the FIFO in one block read which typically consists of many 256 Byte reads on the VME bus if A32 addressing is used Hence A32 is the preferred addressing mode in high speed readout applications The data format of the output FIFO data is described in section 10 Note read access to the empty output FIFO results in a bus error BERR Page 31 of 47
27. e ee ee ee 24 8 11 Input inversion group 1 register OX204 esses GR RA Ge ee ee ee Se Se Re Ge RA Re ee ee ee 24 8 12 Input Group FIFO test registers 0x210 0x214 0x218 OI 25 8 12 1 Test register 1 for Input FIFO Test UNION 25 8 12 2 Test register 2 for Input FIFO Test UNI 25 8 12 3 Test register 3 for Input FIFO Test O0X218 eee se ee Ge Re Re ee ee ee Ge Se Ge Re ee ee Re ee 25 8 12 4 Test register 4 for Input FIFO Test 0X21C ese se ee ee ee ee ee ee ee Ge Se Ge ee ee Rd ee 25 8 13 Input Buffer Group 1 registers 0x220 0x224 0x228 UN 26 Sach Input Butter 0X220 ienne EED erro HERE dE ENER E Be I A eg 26 8 13 2 Tnput Bufier 2 ORD a eene or e ee Bee E ERN REDE ER ERE E EE e 26 8 13 3 Input Buffer 3 0X228 Jonah RUP IHRER ER RN ERE EP ie Eit 26 8 13 4 Input Buffer 4 0x22 E 26 8 14 Time Shadow Registers 0x230 0x234 0x238 NC 27 8 14 1 Time Shadow Register 1 0x230 reserare ee ee ee ee ee ee AR ee EE ra AR ee ee Ge ee ee 27 8 14 2 Time Shadow Register 2 UNI 27 8 14 3 Time Shadow Register 3 0x238 ee ee ee ee ee ee Ge RE E EATE GR R Re ee ee ge ee ee 27 8 14 4 Time Shadow Register 4 UNC 27 8 15 Input inversion group 2 register OX204 ee ee ee Se Se SR GR Re ee ee ee Ge ee Se RA ee ee ene 28 8 16 Input Group 2 FIFO test registers 0x310 0x314 0x318 NIC 29 8 16 1 Test register 5 for Input FIFO Test O0X310 ee ee se se se Ge GR Re Ge ee ee Se Se Ge ee ee Rd ee 29 8 16 2
28. e mode Two more 32 bit words are needed to hold time and module Id information Note The output FIFO can be read in D32 BLT32 and MBLT32 10 1 Single Wire mode 32 bit word bit 31 bits 30 26 bits 25 20 bits 19 0 1 Trailing always 1 Module Id Channel 0 2 Time Stamp 31 0 10 2 Multiwire mode 32 bit word bit 31 bits 30 26 bits 25 20 bits 19 0 1 0 Module Id 0 0 2 Time Stamp bits 31 0 3 Input Bits 63 32 channels 64 33 bits 31 0 4 Input Bits 31 0 channels 32 1 bits 31 0 Page 33 of 47 SIS3400 CDMSII TDC Time Stamper SIS Documentation SIS GmbH VME 11 Input Configuration SIS3400 CDMS II boards can be configured for TTL control levels with 50 Ohm or high impedance input termination and 100 Ohm or high impedance resistor networks removed recommended for daisy chaining only RS485 inputs The resistor networks are in sockets For low active input levels the signals can be connected to Vcc through RN1B to RN18B with 1 KO Network Channels RNIA Control Input 1 RNIB Control Input 2 RNIC Control Input 3 RNSA 5B 6A 6B 1 2 3 4 5 6 7 8 RN7A 7B 8A 8B 9 10 11 12 13 14 15 16 RN9A 9B 10A 10B 17 18 19 20 21 22 23 24 RNI1A 11B 12A 12B 25 26 27 28 29 30 31 32 RN13A 13B 14A 14B 33 34 35 36 37 38 39 40 RN15A 15B 16A 16B 41 42 43 44 45 46 47 48
29. fitted by the user if he wants to change to a VME64x VIPA crate at a later point in time In the drawing below you can find the front panel layout Note Only the aluminium portion without the extractor handle mounting fixtures is shown SIS GmbH CONTROL In Out SIS 3400 Page 39 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 17 3 List of Jumpers and Switches Find below a list of jumpers and switches Name Type Function Jl Array Addressing mode selection J34 Array Boot mode selection SWI Rotary Base address setting SW2 Rotary Base address setting 17 3 1 J1 Addressing Mode Selection As described in section 7 2 the SIS3400 supports several addressing modes the actual mode is selected by jumper array J1 The given mode is selected if ist corresponding jumper is in place The four jumper positions are described in the table below OE Jumper Function Factory default ula A24 A32 enable A32 addressing closed ajo ceo A24 enable A32 addressing closed als VIPA GEO enable geographical addressing open VIPA not implemented yet open Note It is possible to have A32 and A24 set in parallel If an A32 cycle is detected in this case the setting of SW and SW2 is compared with A31 A24 if an A24 cycle is detected SW1 and SW2 are compared with A23 A16 17 3 2 J34 Boot Mode and File Selection The firmware of the SIS3
30. he board comprise standard multi event latch self triggering latch trigger time stamp generator and TDC for low speed applications Initially the development of the card was driven by the requirements of users from the Neutron Scattering community in the context of the readout of a large scale Time Of Hlight TOF spectrometer at the Garching FRM II research reactor As in the order of 14 front end modules will be in use over a long time scale design aspects like ease of maintenance and minimum overhead system integration played an important role The result are features like hot swap and geographical addressing To follow VMES tradition of downward compatibility cstandard VME addressing is implemented as well This manual describes the SIS3400 version which was developed for the CDMS II experiment the main changes are SCSI style 68 pin input connectors in conjunction with LEMO control connectors and RS485 level compatible receivers TTL in the control case and a dedicated firmware design As we are aware that no manual is perfect we appreciate your feedback and will try to incorporate proposed changes and corrections as quickly as possible The most recent version of this manual can be obtained by email from info Gstruck de the revision dates are online under http www struck de manuals htm A list of available firmware designs can be retrieved from http www struck de sis3400firm htm Page 5 of 47 SIS Documentation SIS3400 CDMSII SIS G
31. he four digits of the SIS module number like 3400 e g bits 12 15 hold the version number The version number allows a distinction between different implementations of the same module number the SIS3400 for example has the frontend module mode and the clock module mode as versions Control register bit assignment table Bit Read Write access Function 31 read only Module Identification Bit 15 30 read only Module Identification Bit 14 Module Id Digit 3 29 read only Module Identification Bit 13 28 read only Module Identification Bit 12 27 Read only Module Identification Bit 11 26 read only Module Identification Bit 10 Module Id Digit 2 25 read only Module Identification Bit 9 24 read only Module Identification Bit 8 23 read only Module Identification Bit 7 22 read only Module Identification Bit 6 Module Id Digit 1 21 read only Module Identification Bit 5 20 read only Module Identification Bit 4 19 read only Module Identification Bit 3 18 read only Module Identification Bit 2 Module Id Digit O 17 read only Module Identification Bit 1 16 read only Module Identification Bit 0 15 read only Version Bit 3 14 read only Version Bit 2 13 read only Version Bit 1 12 read only Version Bit 0 11 read write VME IRQ Enable 0 IRQ disabled 1 IRQ enabled 10 read write VME IRO Level Bit 2 9 read write VME IR
32. his value can be regarded as conversion time in combination with the clock period A module operated in event mode at a clock period of 1 us will have the event data stored in the output FIFO after some 2 us Note Set Bits in the input stage Xilinx chips are cleared with the leading edge of the next clock tick During this process which takes approximately 25 ns a new leading edge may not be detected i e the safe double pulse resolution is clock 4 25 ns Page 7 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH 4 TDC Time Stamper VME S e uu Boot o VME a Control Interface ul E S 8 TS Timestamp FIFO 64K x 20 bit O 2 E 3 o Det 5 E E A alle EX o SC 2 5 6 LL ax m Ee HE E EE 9 so o 00 ra i a SIS3400 Block Diagram 3 2 1 Clock Synchroniser Clock receiver The first SIS3400 CDMSII in a multi module setup acts as the clock synchroniser following modules in the clock chain act as clock receiver modules The power up default setting is implemented in a fashion that the unit will power up as clock synchroniser what is the proper setting for a single board The clock synchroniser will synchronise start and stop signals via front panel or VME to the negative edge of the clock and the positive clock edge will be used to latch the d
33. iverse U N 37 Universe Universe UE st edet EE 37 MASA ies VME addressing VME Interrupt nora sesse esse esse see ee Ge ee iE VME IRQ and version register see see see se ee ee 32 VMEORS AE AE A E E VIMEGAXP isis teta ites GR Voltage requirement Windows 2000 word counter zd rd re TNS HIN e 55 COM s Lis iter iere esee Page 47 of 47
34. le DIS LED have to go off Differing behaviour indicates either a problem with the download of the firmware boot file or one or more LCA and or the download logic 15 2 FIFO tests 15 2 1 Input FIFO test Defined input data can be written to the input FIFO chips from VME when input mode 3 is selected via the control register The data have to be written to the 8 input group 1 group 2 FIFO test registers and are transferred to the input FIFO chips upon a key address access to 0x38 input control clock pulse 15 2 2 Output FIFO test The output FIFO chips can be tested in the same fashion as the input FIFO Data are clocked into the output FIFO chips with a key address cycle to address 0x120 from the upper and lower output FIFO test registers The test mode is enabled when input control mode 3 is activated Page 36 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 16 Software Support The first application of the SIS3400 was the FRM II TOF spectrometer readout system A readout program with external configuration was developed for Dr J rgen Hannappels Universe II driver The SBS OR VP7 VME PC was used as platform the driver has been tested with other Tundra Universe II based VME PC s also The latest CDMS II firmware version was tested with a PC and the SIS1100 3100 PCI to VME interface under LINUX The software for both systems will be provided on request by email or on disk In addition the LINUX PCI
35. mbH 4 TDC Time Stamper VME 3 Technical Properties Features Find below a list of key features of the SIS3400 CDMSII 64 channels 3 control in and 3 control outputs 32 bit time bin counter with wrap around counter TTL level for control signals RS485 input level SCSI style 68 pin input connectors Derandomiser FIFO Output FIFO Leading Edge input inversion through control register FIFO and wrap around interrupts external internal clock external internal software inhibit software time reset zero Up to four firmware files A24 32 D32 BLT32 MBLT64Geographical addressing mode in conjunction with VME64x backplane VME64x extractor handles on request single supply 45 V e Hot swap in conjunction with VME64x backplane e VME64x Connectors e VME64x Side Shielding e VME64x Front panel e e 3 1 Board Design As can be seen in the block diagram below the SIS3400 is implemented as a two stage FPGA FIFO Field Programmable Gate Array First In First Out memory design The 64 input channels are connected to the three first stage FPGAs through input drivers Depending on the decision of the input stage FPGAs the 64 bit word and possibly additional information like the event time stamp is stored in the input FIFO group which consists of 5 18 bit x 64K FIFO chips The so called event formatter FPGA processes data from the input FIFOs and stores the result in the output FIFOs the output FIFO group consists of 2 18 bit x
36. nd by the backplane as listed in the following table Slot GAP GA4 GA3 GA2 GAI GAO Number Pin Pin Pin Pin Pin Pin 1 Open Open Open Open Open GND 2 Open Open Open Open GND Open 3 GND Open Open Open GND GND 4 Open Open Open GND Open Open 5 GND Open Open GND Open GND 6 7 8 GND Open Open GND GND Open Open Open Open GND GND GND Open Open GND Open Open Open 9 GND Open GND Open Open GND 10 GND Open GND Open GND Open 11 Open Open GND Open GND GND 12 GND Open GND GND Open Open 13 Open Open GND GND Open GND 14 Open Open GND GND GND Open 15 GND Open GND GND GND GND 16 Open GND Open Open Open Open 17 GND GND Open Open Open GND 18 GND GND Open Open GND Open 19 Open GND Open Open GND GND 20 GND GND Open GND Open Open 21 Open GND Open GND Open GND 17 8 Additional Information on VME The VME bus has become a popular platform for many realtime applications over the last decade Information on VME can be obtained in printed form via the web or from newsgroups Among the sources are the VMEbus handbook http www vita com the home page of the VME international trade association VITA and comp bus arch vmebus In addition you will find u
37. nputs can be read in groups of 8 bit through the four input buffer group 1 and the four input buffer group 2 read only registers for test purposes 8 13 1 Input Buffer 1 0x220 8 13 3 Input Buffer 3 0x228 Bit Read Write access Function Bit Read Write access Function 31 Read only No function read 0 31 Read only No function read 0 8 Read only No function read 0 8 Read only No function read 0 7 Read only Input Buffer Data Bit 63 7 Read only Input Buffer Data Bit 47 0 Read only Input Buffer Data Bit 56 0 Read only Input Buffer Data Bit 40 8 13 2 Input Buffer 2 0x224 8 13 4 Input Buffer 4 0x22C Bit Read Write access Function Bit Read Write access Function 31 Read only No function read 0 31 Read only No function read 0 8 Read only No function read 0 8 Read only No function read 0 7 Read only Input Buffer Data Bit 55 7 Read only Input Buffer Data Bit 39 0 Read only Input Buffer Data Bit 48 0 Read only Input Buffer Data Bit 32 Page 26 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 8 14 Time Shadow Registers 0x230 0x234 0x238 0x23C The 32 bit wide time stamp can be read trough the four read only time shadow registers To avoi
38. oes 35 14 3 Insertion Removal is EERS Eed eene Se beer ee KEE 35 15 ES AE EE HR EE EE OE EE OER 36 KA PEL RE EE EE aid 36 15 2 io RE EE adds 36 I5 23 N Input FIFO RE EE OE OE DP RE opere er 36 15 2 2 Output diL es IE RE EE EUER n aet deeper 36 16 Software SUppott ceto o ER E EE EE e a BED 37 17 Appendix rot teg EE RE EE OE RE HE EE EE tae 38 rt Address Modifier Overview iaceo A Een Ee 38 17 2 front Panel RE ME ER EE EE EE OE RE EN 39 17 3 ist Of e 40 17 31 JH Addressine Mode S election eege GI e DERE BER RERO RED Ee See De Pa 40 17 3 2 J34 Boot Mode and File Selection ses see see bees see n ee Be ee ee Bee Be EE E E T ES ese ee ee ee 40 1733 SWI and SW2 Base Address Selection ooocnoncnonnnocnnoncnonconnconoconocononn nono nonnnnnnn E EES RA S Eeo ee 41 VTA Board Layout iecit etre av eae HG IA e ere RE GR DOE EG 42 TES FLASHPROM VerstonS oe Ee EE ates GR R IRONIA Ree ers 43 17 6 Row d and z Pin Assignments onina aer are eene on ne roce non ee ee nace ee anne GR neon neon nena E 44 17 7 Geographical Address Pin Assignments nennen nennen een rennen ee ge ee 45 17 8 Additional Information on NM 45 18 Index NS 46 Page 4 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 2 Introduction The SIS3400 is a versatile 64 channel TTL or RS485 CDMS II version input module The card is a single width 6U VME board with hard metric coaxial input connectors Possible applications of t
39. ontrolled through this register On read access the register represents the formatter status register Bit Read Write access Function 31 read only No function read 0 16 read only No function read 0 15 read write reserved 14 read write reserved 13 read write reserved 12 read write reserved 11 read write reserved 10 read write reserved 9 read write reserved 8 read write reserved 7 read write reserved 6 read write reserved 5 read write reserved A Read write OUTPUT FIFO TEST Mode 3 read write reserved 2 read write reserved 1 Read write reserved 0 Read write single wire mode else multi wire mode if 0 Power up default reading 0x00000000 Page 20 of 47 SIS Documentation SIS3400 CDMSII TDC Time Stamper SIS GmbH VME 8 5 Formatter Module Address register 0x104 This read write register defines the address which is copied into the output FIFO data stream of the SIS3400 In a multi module setup a detector channel is identified by its channel number 0 63 and its formatter module address 0 15 i e up to 1024 detector channels can be identified in a unique fashion without additional data to be added by the VME CPU Bit Read Write access Function 31 read only No function read 0 8 read only No function read 0
40. seful links on many high energy physics labs web pages like CERN or FNAL Page 45 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 18 Index D 13 31 40 EE RE EE EN 6 13 31 40 address f rmatt r EP Giese nen Haan nee 10 Address Map EE 14 Address Modifier Overview cooooocccononcccoonnnononanononanacono 38 address modifiers Zei Vee EE red addressing geographical sabato ded 5 6 13 O ee ee eere LA OE OE 40 addressing mode sese 38 back A ec ee RS A ee 6 13 base address factory default setting sse 13 Base Address x3 BERR 31 BET desee tei dete rhe D MUS deg 38 BLT32 6 33 Board Layout Ee chides eter de ee ge eg es eg 42 boot MS A Ee N e eer ie boot mode DU EE Ee OE OU HI eee BUS GLK s GENI EE IET ES BUS CLR BUS INH BUS VETO E 44 CDMS II extemal iss Ee ee Rate eae alate as 12 1 terndl de Se EE EECH 12 receiver 8 10 Ge EE 10 SYNCHTOMISET E 8 clock master disable as 17 CO EE 5 compatibility si Ee SERE ee 5 NERO ea 6 Connector Specification 34 Control and Status register see se se se ee ee 14 control input disable front panel sesse ee ee Re ee ee 17 disable inversion eese 17 enable front panel sse 17 enable inversion a front panel iie hes EE IDVef SIOIL it Con
41. ss if input control mode 3 is avtive 8 12 1 Test register 1 for Input FIFO Test 0x210 8 12 3 Test register 3 for Input FIFO Test 0x218 Bit Read Write access Function Bit Read Write access Function 31 Read only No function read 0 31 Read only No function read 0 8 Read only No function read 0 8 Read only No function read 0 7 Read write Input Fifo Test Data Bit 63 7 Read write Input Fifo Test Data Bit 47 0 Read write Input Fifo Test Data Bit 56 0 Read write Input Fifo Test Data Bit 40 after power up 0x00000000 8 12 2 Test register 2 for Input FIFO Test 0x214 after power up 0x00000000 8 12 4 Test register 4 for Input FIFO Test 0x21C Bit Read Write access Function Bit Read Write access Function 31 Read only No function read 0 31 Read only No function read 0 8 Read only No function read 0 8 Read only No function read 0 7 Read write Input Fifo Test Data Bit 55 7 Read write Input Fifo Test Data Bit 39 0 Read write Input Fifo Test Data Bit 48 0 Read write Input Fifo Test Data Bit 32 after power up 0x00000000 after power up 0x00000000 Page 25 of 47 SIS Documentation SIS3400 CDMSII TDC Time Stamper SIS GmbH VME 8 13 Input Buffer Group 1 registers 0x220 0x224 0x228 0x22C The status of the 64 i
42. to VME interface code will work with minimum modifications with the Windows 2000 driver for the SIS1100 3100 interface also Page 37 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 17 Appendix 17 1 Address Modifier Overview Find below the table of address modifiers which can be used with the SIS3400 with the corresponding addressing mode enabled AM code Mode 0X3 F A24 supervisory block transfer BLT 0x3D A24 supervisory data access 0x3C A24 supervisory 64 bit block transfer MBLT 0x3B A24 non privileged block transfer BLT 0x39 A24 non privileged data access 0x38 A24 non privileged 64 bit block transfer MBLT OxOF A32 supervisory block transfer BLT OxOD A32 supervisory data access OxOC A32 supervisory 64 bit block transfer MBLT OxOB A232 non privileged block transfer BLT 0x09 A232 non privileged data access 0x08 A32 non privileged 64 bit block transfer MBLT Page 38 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 17 2 Front Panel Layout The front panel of the SIS3400 CDMS II is equipped with 8 LEDs 6 control in and outputs and 64 inputs The control connectors are of LEMOOO style the two input connectors are of 68 pin SCSI style The units are 4 TE one VME slot wide the front panel is of EMC shielding type VME64x VIPA extractor handles are available on request or can be retro
43. top Stop 3 The input to output delay is approx 15 ns Note The internal clock will not be seen by the module if front panel input is enabled and the external clock input is high open and terminated with 4 7 KQ to Vcc e g Le the internal and external clock signals are ored See section 8 2 for control input inversion Page 12 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME 7 VME addressing 7 1 Address Space Depending on the selected addressing mode the module occupies 16 bits A24 mode or 24 bits A32 mode of the VME addressing space 7 2 Base Address 7 2 1 VME Besides standard A24 and A32 addressing the SIS3400 offers a pragmatic geographical addressing mode VIPA geographical addressing is foreseen as a possible future option but was considered too complex for the Neutron TOF application The base address is defined by the selected addressing mode which is defined by jumper array J1 and possibly SW1 and SW2 in non geographical mode The table below summarises the possible base address settings set jumper s of J1 Address Bits A32 A24 GEO VIPA 31 30 29 28 27 26 25 24 23 22 21 2019 18 17 16 X Sw2 SWI 0 0 X X notdecoded not decoded Sw2 SWI st lei eil co e X X ex Ec em Eil en oe emm e em ECO QO
44. trol Register conversion time COON SA ier t ri DO08 O edge leading isa ese ree acte Ue esee s event formatter FIFO flag almost empty ie ortos tercio eg coetde cutee 21 22 almosttull steet ee 21 22 einpty Ee AE RE AE EE 21 22 full o 2221 22 half full 21 22 unu EE 40 firmware design LO 18 FILASHPROMb iiss t ere ees Ete ed 40 FLASHPROM Version 43 ENAE zx dee ee E 45 formatter address 10 FPGA eh ern ERROR ER ee RE 6 FRM IE nes Ie 5 37 front panel ehe RO eR tereti 6 Front Panel EED at e ere EE PER UNI IE 11 Front Panel Layout 39 GAO GA1 GA2 GA3 GA4 GAP Gear chin RE eid intem deese 5 geographical address pills dosh BERE eens 45 Geographical Address 45 geographical addressing sss 44 Getting Started EE eod bene 10 global TES ia ERR Ye HR seen 23 h t EE 5 35 44 http IWWW MA COM 45 inhibit oret ove dee gis 6 12 input COMTOL AR NE EE ont inversion A PERO Input Configuration esee input group 1 FIFO test input group 2 FIFO test input IDVerSIOIn tonos creer deer ete EE RU input ouput delay Insertion Removal esee Interruption P er N seeds interrupt acknowledge cycle Interrupt Control ese et e per teet ertet interrupt level eite teeth interrupt vecina Page 46 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME
45. ulse 0x03C KA W D32 INPUT Control CLEAR pulse clears time counter Formatter 0x100 R W D32 Formatter Control Status register 0x104 R W D32 Formatter Module Address register module number 0x108 R D32 FIFO Flag Status register Ox10C R W D32 FIFO Flag IRQ Enable control register 0x110 R W D32 Upper Test register for Output FIFO Test data bits 31 16 0x114 R W D32 Lower Test register for Output FIFO Test data bits 15 0 0x118 R D32 Output FIFO word counter 0x120 KA W D32 Write test data into Output FIFO if Test is enabled 0x130 KA W D32 Clear all FIFOs and FIFO word counter Page 14 of 47 SIS Documentation SIS3400 CDMSII SIS GmbH TDC Time Stamper VME Input1 64 33 0x200 R W D32 Input group 1 Control Status register 0x204 R W D32 Input inversion channel 63 32 Bit0 0 non inverting Bit0 1 inverting 0x210 R W D32 Test register 1 for Input FIFO Test input data 64 57 0x214 R W D32 Test register 2 for Input FIFO Test input data 56 49 0x218 R W D32 Test register 3 for Input FIFO Test input data 48 41 0x21C R W D32 Test register 4 for Input FIFO Test input data 40 33 0x220 R D32 Input Buffer 1 input data 64 57 0x224 R D32 Input Buffer 2 input data 56 49 0x228 R D32 Input Buffer 3 input data 48 41 0x22C R D32 Input Buffer 4 input data 40 33 0x230 R D32 Time Shadow Register 1 Bits
46. x314 after power up 0x00000000 8 16 4 Test register 8 for Input FIFO Test 0x31C Bit Read Write access Function Bit Read Write access Function 31 Read only No function read 0 31 Read only No function read 0 8 Read only No function read 0 8 Read only No function read 0 7 Read write Input Fifo Test Data Bit 23 7 Read write Input Fifo Test Data Bit 7 0 Read write Input Fifo Test Data Bit 16 0 Read write Input Fifo Test Data Bit 0 after power up 0x00000000 after power up 0x00000000 Page 29 of 47 SIS Documentation SIS3400 CDMSII TDC Time Stamper SIS GmbH VME 8 17 Input Buffer Group 2 registers 0x320 0x324 0x328 0x32C 8 17 1 Input Buffer 5 0x320 8 17 3 Input Buffer 7 0x328 Bit Read Write access Function Bit Read Write access Function 31 Readonly No function read 0 31 Read only No function read 0 8 Read only No function read 0 8 Read only No function read 0 H Read only Input Buffer Data Bit 31 7 Read only Input Buffer Data Bit 15 0 Read only Input Buffer Data Bit 24 0 Read only Input Buffer Data Bit 8 8 17 2 Input Buffer 6 0x324 8 17 4 Input Buffer 8 0x32C Bit Read Writ

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