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1. Y BRK B 0 18 0 007 T 116 r U 0 18 0 007 0 IN G PO L MO 1 zi bs L d L m M V 3 es poc 52 Gi NOTE 1 10 25 0 010 N L MO gt X x gt V VIEW D D lt A 4 0 18 0 007 T L PO lt z R 0 18 0 007 T L N P 6 _ 048 0 007 T H 0 18 0 0079 T NS P O L6 0 10 0 004 Y T SEATING PLANE K BETAS 018 0007 TLS MO NS PS gt lt r 048 0 007 9 6 16 DETAIL S 0 25 0 010 T 116 NOTES MILLIMETERS INCHES 1 DUE TO SPACE LIMITATION CASE 778 02 SHALL BE REPRESENTED DIM MAX MIN MAX BY A GENERAL SMALLER CASE OUTLINE DRAWING RATHER THAN 1994 2019 0785 0 795 SHOWING ALL 52 LEADS B 19 94 2019 0 785 0 795 2 DATUMS L M N DETERMINED WHERE TOP OF LEAD C 420 457 0165 0 180 SHOULDER EXIT PLASTIC BODY AT MOLD PARTING LINE E 229 279 0 090 0 110 3 DIM G1 TRUE POSITION TO BE MEASURED AT DATUM F 033 048 0013 0 019 SEATING PLANE G 127 BSC 0 050 BSC 4 DIM R AND U DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE H oes 081 0 026 00 MOLD PROTRUSION IS 0 25 0 010 PER SIDE j 051 T 0000 5 DIME
2. DS Width High 2 R W RS1 RS5 Valid to Falling CS Setup Time 0 ns 3 Data Valid Prior to Falling CLK Setup Time Write Cycle Only 0 ns 41 CS IACK Valid to Falling CLK Setup Time 50 ns 5 CLK Low to DTACK Low 220 ns 6 CS or DS or TACK High to DTACK High 60 ns 7 5 DS IACK High to DTACK High Impedance 100 ns 8 DTACK Low to Data Invalid Hold Time Write 0 ns 9 CS or DS or High to Data High Impedance Read 50 ns 10 CSorDS High to RS1 RS5 RAN Invalid Hold Time 0 ns 115 Data Valid from CS Low Read 310 ns 12 Data Valid to DTACK Low Setup Time Read 50 ns 13 DTACK Low to DS or CS or High Hold Time 0 ns 14 TEI Low to Falling CLK Setup Time 50 ns 15 IEO Valid from CLK Low Delay Time 180 ns 16 Data Valid from CLK Low Delay Time 300 ns 17 IEO Invalid from TACK High Delay Time 150 ns 18 DTACK Low from CLK High Delay Time 180 ns 19 IEO Valid from TEI Low Delay Time 100 ns 20 Data Valid from Low Delay Time 220 ns 21 CLK Cycle Time 250 1000 ns 22 CLK Width Low 110 ns 23 CLK Width High 110 ns 2424 Inactive to Rising CLK Setup Time 100 ns 25 Minimum Active Pulse Width 100 ns 263 TACK Width High 2 m 27 Data Valid from Falling Write 450 ns 8 5 MC68HC901 USER S MANUAL MOTOROLA Electrical Char
3. 1 2 Section 2 Signal Description 2 1 Power Supply Vec and GND ndm len ets 2 1 2 2 Glock we asp e a cea D c oi eL 2 2 2 3 Data Bus D7 D0 RR 2 2 2 4 Asynchronous Bus Control 2 2 2 4 1 Chip Select GS uuu sasanqua ni y naa rebos 2 2 2 4 2 Data Strobe DS ben Deb baeo ta 2 2 2 4 3 Read Write RAN sectionis LUE eth 2 2 2 4 4 Data Transfer Acknowledge 2 2 2 5 Register Select Bus 51 55 42 2 11 2 2 2 6 Heset HESET Suida an cep l y aaa 2 2 2 7 Interrupt Control 2 3 2 7 4 Interrupt Request IRQ cota etc rU aee e aec eir beta c 2 3 2 7 2 Interrupt Acknowledge 4 40 2 3 2 7 3 Interrupt Enable In 2 3 2 7 4 Interrupt Enable Out IEO a 2 3 2 8 General Purpose I O Interrupt Lines 17 10 2 3 2 9 2 4 2 9 1 Timer Inputs TAI and TBI 2 4 2 9 2 Timer Outputs TAO TCO and TDO 2 4 2 9 3 Timer Clock XTAL1 and XTAL2
4. 2 4 Signal Summary 2 5 Software End O f Interrupt Mode 4 12 Special Receive Conditions 7 7 Synchronous Format 7 2 MOTOROLA MC68HC901 USER S MANUAL T Thermal Characteristics 8 1 Timer AC Characteristics 8 7 Timer Control Registers TxCR 6 4 Timer Control Signals 2 4 Timer Data Registers 6 4 Timer Registers Timer A Control Register 6 4 Timer A Data Register TADR 6 4 Timer Control Register TBCR 6 4 Timer B Data Register oo uuu 6 4 Timer C and D Control Register TODOR co 6 4 Timer C Data Register ICDR 6 4 Timer D Data Register CLD DA 6 4 Timer Timing 8 12 TIMENS u kaa 6 1 Transmitter 7 7 Transmitter Interrupt Channels 7 8 Transmitter Timing 8 11 register 7 8 U UCR register 7 3 UDR register 7 4 Universal Synchronous Asynchronous Receiver Transmitter 7
5. 3 3 Reset Signal 2 2 Reset Timing 8 11 RSR register 7 5 5 SCR register 7 2 Section s Bus Operation 3 1 Electrical Characteristics 8 1 General Purpose Input Output 21002 5 1 Interrupt Structure 4 1 Introduction 1 1 Mechanical Data and Ordering Information 9 1 Signal Description 2 1 aa 6 1 Universal Synchronous Asynchronous Receiver Transmitter 7 1 Selecting the End Of Interrupt 4 11 Serial Control Signals 2 4 Signal Description 2 1 Signal Groups Asynchronous Bus Control 2 2 Clock CLK 2 2 Data Bus 07 00 2 2 DMA Control 2 5 GPIP Interrupts 17 10 2 3 Interrupt Control 2 3 Power Supply Vcc and GND 2 1 Register Select Bus RS1 RS5 2 2 Reset RESET 2 2 Serial Control 2 4 Timer Control
6. Minimum Pulse 4 tci k Event Counter Mode Minimum Active Time of and 4 tci k Minimum Inactive Time of Al and 4 tci k NOTES 1 Error may be cumulative if repetitively performed 8 7 2 Error with respect to tout or IRQ if note 3 is true 3 Assuming it is possible for the timer to make an interrupt request immediately MC68HC901 USER S MANUAL MOTOROLA Electrical Characteristics gt 4 Figure 8 4 Write Cycle Timing 8 8 MC68HC901 USER S MANUAL MOTOROLA Electrical Characteristics NOTE IEO only goes low if no acknowledgeable interrupt is pending If IEO goes low DTACK and the data bus remain in the high impendance state Figure 8 5 Interrupt Acknowledge Cycle IEI Low 8 9 MC68HC901 USER S MANUAL MOTOROLA Electrical Characteristics NOTES 1 IEO only goes low if no acknowledgable interrupt is pending If IEO goes low DTACK and the data bus remain in the high impedance state 2 DTACK will go low at A if specification number is met Otherwise DTACK will go low at 8 Figure 8 6 Interrupt Acknowledge Cycle IEI High IRQ NOTE Active edge is assumed to be the rising edge Figure 8 7 Interrupt Timing CLK 17 10 Figure 8 8 P
7. 8 4 G Conceptual Circuit of Interrupt General Purpose I O Data Register Source Selection 6 2 GPDH oett ee of an Interrupt ie General Purpose Interrupt ANNEI E A Pd D General Purpose Input Output Daisy Chained Interrupt Structure 4 3 GPDR register TURAE EUM Daisy Chaining MFPs 43 GPIP Control Registers Data Bus Signals 2 2 GP IP Port MOTOROLA INDEX Data Direction Register DDR Data Transfer Operations DC Electrical Characteristics MC68HC901 USER S MANUAL INDEX 1 Index GPIP Registers Active Edge Register AER 5 2 Data Direction Register DDR 5 2 General Purpose Data Register GPDR 5 1 Cycle Timing Diagram 3 3 IERA register 4 4 IERB register 4 5 IMRA register 4 8 register 4 9 Input and Output Signals 2 1 Interrupt Acknowledge Cycle TET High 8 10 Interrupt Acknowledge Cycle Low 8 9 Interrupt Acknowledge Operation 3 2 Interrupt Channel Prioriti
8. 2 Although sections of the device contain circuitry to protect against damage from high static voltages or electrical fields take normal precautions to avoid exposure to voltages higher than maximum rated voltages 8 2 THERMAL CHARACTERISTICS CHARACTERISTIC SYMBOL VALUE SYMBOL VALUE RATING Thermal Resistance C W Plastic Dual In Line 40 20 PLCC 60 30 Estimated MOTOROLA MC68HC901 USER S MANUAL 8 1 Electrical Characteristics 8 3 POWER CONSIDERATIONS The average chip junction temperature in C can be obtained from TA Pp DAE A M RESTE EAR EPA EN 1 where TA Ambient Temperature Package Thermal Resistance Junction to Ambient C W Pp Pint Vcc Watts Chip Internal Power Power Dissipation on Input and Output Pins Watts User Determined For most applications lt and can be neglected An appropriate relationship between Pp and Tj if is neglected is PS 270 C assit stu nels Perd aa qa e Beta oit 2 Solving equations 1 and 2 for K gives KP HOO Py anco ea bec ea 3 where K is a constant pertaining to the particular part K can be determined from equation 3 by measuring at equilibrium for a known T4 Using this value of K the values of Pp and can be obtained by solving equations 1 and
9. ADDRESS HEX BINARY ABBREVIATION REGISTER NAME RS5 RS4 RS3 RS2 RS1 17 0 1 0 1 1 VR Vector Register 19 0 1 1 0 0 TACR Timer A Control Register 1B 0 1 1 0 1 TBCR Timer B Control Register 1D 0 1 1 1 0 TCDCR Timers C and D Control Register 1F 0 1 1 1 1 TADR Timer A Data Register 21 1 0 0 0 0 TBDR Timer B Data Register 23 1 0 0 0 1 TCDR Timer C Data Register 25 1 0 0 1 0 TDCR Timer D Data Register 27 1 0 0 1 1 SCR Synchronous Character Register 29 1 0 1 0 0 UCR USART Control Register 2B 1 0 1 0 1 RSR Receiver Status Register 2D 1 0 1 1 0 TSR Transmitter Status Register 2F 1 0 1 1 1 UDR USART Data Register NOTE Hex addresses assume that RS1 connects with A1 RS2 connects with A2 etc and that DSis connected to LDS on the MC68000 or DS is connected to DS on the MC68008 MOTOROLA MC68HC901 USER S MANUAL 1 3 SECTION 2 SIGNAL DESCRIPTION This section contains descriptions of the input and output signals The input and output signals can be functionally organized into groups as shown in Figure 2 1 The following paragraphs provide a brief description of the signal and a reference if applicable to other sections that contain more detail about its function NOTE Assertion and negation are used to specify forcing a signal to a particular state Assertion and assert refer to a signal that is active or true Negation and negate refer to a signal that is inactive or false These terms are us
10. RS5 Input Data Bus D7 Input Yes Output Reset RESET Input Interrupt Request TRQ Output No Interrupt Acknowledge TACK Input Interrupt Enable In TEI Input Interrupt Enable Out Output No General Purpose Input Yes Output Timer Clock XTAL1 Input N A XTAL2 Output N A No Timer Inputs TAI TBI Input N A Timer Outputs TAO TBO Output N A No Low TCO TDO Serial Input SI Input N A Serial Output SO Output N A Yes Hi Z Receiver Clock RC Input N A Transmitter Clock TC Input N A Receiver Ready RR Output Low No High Transmitter Ready TR Output Low No Low Open Drain 2 6 MC68HC901 USER S MANUAL MOTOROLA SECTION 3 BUS OPERATION The following paragraphs describe control signals and the bus operation during data transfer interrupt acknowledge and reset operations 3 1 DATA TRANSFER OPERATIONS Transfer of data between devices involves the following pins Register Select Bus RS1 through RS5 Data Bus DO through D7 Control Signals The address and data buses are separate parallel buses used to transfer data using an asynchronous bus structure In all cases the bus master assumes responsibility for deskewing all signals it issues at both the start and end of a cycle Additionally the bus master is responsible for deskewing the acknowledge and data signals from the peripheral devices 3 1 1 Read Cycle To read an MFP register CS and DS must be asserted and R W must be high The MFP will place the contents
11. is hereafter referred to as the MFP in this document Many features of the MFP make reference to the MC68000 Family of 16 and 32 bit microprocessors which includes the 68 000 68 001 and the MC68ECOO00 These microprocessors are referred to as the MC68000 within this document The MFP directly interfaces to the MC68000 via the asynchronous bus structure Both vectored and polled interrupt schemes are supported with the MFP providing unique vector number generation for each of its 16 interrupt sources Additionally handshake lines are provided to facilitate direct memory access controller DMAC interfacing Refer to Figure 1 1 for a block diagram of the MFP CLK RESET Vec GND INTERNAL CONTROL LOGIC TIMERS TCO C amp D TDO XTAL1 00 07 dm XTAL2 TAO TIMERS TAI 51 55 p CPU A amp B TBO lt TBI BUS Cs 1 0 RR R W SI DS USART DTACK 80 GENERAL PURPOSE 1 0 INTERRUPTS 0 17 INTERRUPT CONTROL IRQ IEI IEO IACK Figure 1 1 MFP Block Diagram MOTOROLA MC68HC901 USER S MANUAL 1 1 Introduction 1 1 KEY FEATURES The MFP performs many of the functions common to most microprocessor based systems The resources available to the user include Eight individually programmable pins with interrupt capability 16 source interrupt controller with individual source enable and masking Four timers two of which are multi mode timers Single channel full duplex universal
12. 2 iteratively for any value of TA The total thermal resistance of a package can be separated into two components and representing the barrier to heat flow from the semiconductor junction to the package case surface and from the case to the outside ambient These terms are related by the equation 4 is device related and cannot be influenced by the user However is user dependent and can be minimized by such thermal management techniques as heat sinks ambient air cooling and thermal convection Thus good thermal management on the part of the user can significantly reduce so that approximately equals Substitution of for in equation 1 will result in a lower semiconductor junction temperature 8 2 MC68HC901 USER S MANUAL MOTOROLA Electrical Characteristics 8 4 DC ELECTRICAL CHARACTERISTICS Ta 0 C to 70 Vec 5 0 55 GND 0 Vdc unless otherwise noted CHARACTERISTIC SYMBOL SS UNIT Input High Voltage except XTAL1 Input Low Voltage except XTAL1 Vit 0 3 0 8 V XTAL1 Input High Voltage 3 15 Voc V XTAL1 Input Low Voltage 0 3 1 35 V Output High Voltage Except IRQ DTACK 120 Vou 2 4 V Output Low Voltage Except DTACK lo 2 0 mA VoL 0 5 V Power Supply Current lu 40 mA
13. 2 4 2 10 Serial Control ren deque nt bed 2 4 2 10 1 Serial pe T 2 4 2 10 2 Serial Output SO 2 5 2 10 3 Receiver Clock e eo RERUM sura 2 5 2 10 4 Transmitter Clock Gb eb 2 5 2 11 Direct Memory Access Control 2 5 2 11 1 Receiver Ready 2 5 2 11 2 Transmitter Ready TR a ated 2 5 2 12 Signal Sumteiaty a 2 5 MOTOROLA MC68HC901 USER S MANUAL vii TABLE OF CONTENTS Continued Paragraph Page Number Title Number Section 3 Bus Operation 3 1 Data Transfer Operations 00 3 1 3 1 1 Read 19 don ho Lt aT E ADI DAT 3 1 3 1 2 Write i uu eb tu e v deus 3 2 3 2 Interrupt Acknowledge Operation 3 2 3 3 Reset Operation 3 3 Section 4 Interrupt Structure 4 1 Interrupt Processirtt u roi E EE RERO Mus 4 1 4 1 1 Interrupt Channel Prioritization 4 1 4 1 2 Interrupt Vector Number eet ae 4 1 4 1 3 Vector Register VR 4 2 4 2 Daisy Chaining MERS eme t 4 3 4 3 Interrupt Control Registers 4 4 4 3 1 Interrupt
14. DR EN EUR 8 8 84 Write G ycle TIMIN uisi root xr bed ute p T E 8 8 8 5 Interrupt Acknowledge Cycle Low 8 9 8 6 Interrupt Acknowledge Cycle High 8 10 B 7 Interrupt Timing ebbe oes 8 10 8 8 POR TIMING eost to eye aqa 8 10 B 9 Reset TIMING soo oe Ae e AL SL RE E 8 11 8410 Receiver TIMING eee tree Diese ca Re Dre Diet cbe Dues 8 11 8 11 Transmitter TIMING iuo tecta usa Ron Ele pt ER REUS 8 11 8 12 imer THING etc Sc Eds 8 12 9 1 48 Dual In Line Package Plastic 9 1 9 2 52 Lead QUAD Package uictor nene 9 2 9 3 Case 767 02 P Suffix Ree bin neni 9 2 9 4 778 02 FN SUK Aidei ee eco Re alc eiu Len 9 3 MOTOROLA MC68HC901 USER S MANUAL xi LIST OF TABLES Table Page Number Title Number 1 1 MPP Register aus 1 2 23e Signal 2 5 MC68HC901 USER S MANUAL xiii SECTION 1 INTRODUCTION The MC68HC901 Multi Function Peripheral is a member of the M68000 Family of peripherals Unless otherwise specified the MC68HC901 multi function peripheral
15. General Purpose Interrupt Pending 1 Pending 0 Timer A Timer A Interrupt Pending 1 Pending 0 Cleared Receiver Buffer Full Receiver Buffer Full Interrupt Pending 1 Pending 0 Cleared Receiver Error Receiver Buffer Full Interrupt Pending 1 Pending 0 Cleared Transmitter Buffer Empty Transmitter Buffer Interrupt Pending 1 Pending 0 Cleared Transmitter Error Transmitter Error Interrupt Pending 1 Pending 0 Cleared Timer B Timer B Interrupt Pending 1 Pending 0 Cleared 4 6 MC68HC901 USER S MANUAL MOTOROLA Interrupt Structure IPRB REGISTER BIT 7 6 5 4 3 2 1 0 FIELD GPIP5 4 TIMERC TIMERD GPIP3 GPIP2 GPIP1 GPIPO RESET 0 0 0 0 0 0 0 0 ADDR 0D GPIP5 GPIP4 General Purpose Interrupt Pending 1 Pending 0 Cleared Timer C Timer C Interrupt Pending 1 Pending 0 Cleared Timer D Timer D Interrupt Pending 1 Pending 0 Cleared GPIP3 GPIPO General Purpose Interrupt Pending 1 Pending 0 Cleared 4 7 MC68HC901 USER S MANUAL MOTOROLA Interrupt Structure 4 3 3 Interrupt Mask Registers IMRA IMRB Interrupts are masked for a channel by clearing the appropriate bit in interrupt mask register A or B IMRA or IMRB Even though an enabled channel is masked the channel will recognize subsequent interrupts and set its interrupt pending bit However the channel is prevented
16. character has been received 1 Character transferred to the receive buffer matches the synchronous character 0 Character transferred to the receive buffer does not match the synchronous character The CIP bit is used in the asynchronous character format and indicates that a character is being assembled 1 Start bit is detected 0 Final stop bit has been received SS Synchronous Strip Enable 1 Characters that match the synchronous character will not be loaded into the receiver buffer and no buffer full condition will be produced 0 Characters that match the synchronous character will be transferred to the receive buffer and a buffer full condition will be produced 7 6 MC68HC901 USER S MANUAL MOTOROLA Universal Synchronous Asynchronous Receiver Transmitter RE Receiver Enable This bit should not be set until the receiver clock is active When the transmitter is disabled in auto turnaround mode this bit is set 1 Receiver operation is enabled 0 Receiver is disabled 7 2 3 Special Receive Conditions Certain receive conditions relating to the overrun error flag and the break detect flag require further explanation Consider the following examples 1 A break is received while the receive buffer is full This does not produce an overrun condition Only the B flag will be set after the receiver buffer is read 2 new word is received and the receive buffer is full A break is received before the
17. number which corresponds to the highest priority channel that has a pending interrupt is presented to the processor during an interrupt acknowledge cycle This unique vector number allows the processor to immediately begin execution of the interrupt handler for the interrupting source decreasing interrupt latency 4 1 1 Interrupt Channel Prioritization The 16 interrupt channels are prioritized from highest to lowest with General Purpose Interrupt 7 I7 being the highest and 10 the lowest The priority of the interrupt is determined by the least significant four bits in the interrupt vector number which are internally generated by the MFP Pending interrupts are presented to the processor in order of priority unless they have been masked By selectively masking interrupts the channels are in effect re prioritized 4 1 2 Interrupt Vector Number During an interrupt acknowledge cycle a unique 8 bit interrupt vector number is presented to the system which corresponds to the specific interrupt source that is requesting service BIT 7 6 5 4 3 2 1 0 FIELD V7 V6 V5 V4 IV3 IV2 IV1 IVO V7 V4 Vector The four most significant bits are copied from the vector register MOTOROLA MC68HC901 USER S MANUAL 4 1 Interrupt Structure IV3 IVO Interrupt Vector These bits are supplied by the MFP They are the binary channel number of the highest priority channel that is requesting interrupt service
18. the timer clock pins XTAL1 and XTAL2 or XTAL1 can be driven with a CMOS level clock while XTAL2 is not connected The following crystal parameters are suggested 1 Parallel resonance fundamental mode AT cut HC6 or HC33 holder 2 Frequency tolerance measured with 18 picofarads load 0 1 accuracy drive level 10 microwatts 3 Shunt capacitance equals 7 picofarads 4 Series resistance 2 0 f 2 7 MHz Rs 300 ohms 2 8 lt f lt 4 0 MHz Rs 150 ohms 2 10 SERIAL CONTROL The full duplex serial channel is implemented by a serial input line The independent receive and transmit sections may be clocked by separate timing signals on the receive clock input and the transmitter clock input 2 10 1 Serial Input SI This input line is the USART receiver data input This input is not used in the USART loopback mode Refer to Section 7 3 2 Transmitter Status Register for additional information 2 4 MC68HC901 USER S MANUAL MOTOROLA Signal Description 2 10 2 Serial Output SO This output line is the USART transmitter data output This output is in a high impedance state after a device reset 2 10 3 Receiver Clock RC This input controls the serial bit rate of the receiver The signal may be supplied by the timer output lines or by an external TTL level clock which meets the minimum and maximum cycle times This clock is not used in the USART loopback mode Refer to Section 7 3 2 Transmitter Status Regist
19. 8 2 8 4 DC Electrical Characteristics teg 8 3 8 5 EE 8 3 8 6 Glock KMING oii nunus uuu ER PIS D e Ei 8 4 8 7 AG Electrical Characteristics nitet ve dt rere odios 8 5 8 8 Timer AC Characteristics ostia oti eden den dede 8 7 Section 9 Mechanical Data and Ordering Information 9 1 Pim ASSIGUEIGEIS 9 1 9 2 Package Dimensions hr 9 2 9 3 Ordering a etna d e tdeo hc itd es 9 4 MOTOROLA MC68HC901 USER S MANUAL ix LIST OF ILLUSTRATIONS Figure Page Number Title Number 1 1 Block eoe 1 1 2 1 np tand Output 2 1 3 1 Read Cycle Timing Diagram wae 3 2 3 2 Write Cycle Timing Diagram sioe dre noe D xe 3 2 3 3 Cycle Timing Diagram 3 3 4 1 Daisy Chained Interrupt Structure 2204444 4 3 4 2 Conceptual Circuits of an Interrupt 4 9 6 1 Conceptual Circuit of Interrupt Source Selection 6 2 8 1 Clock Input Timing Diagram 8 4 8 2 External Oscillator Components 440 8 4 8 3 Read Cycle Timing oui
20. For Dial Up Phone 1 512 891 3650 Phone US or Canada 1 800 843 3451 Connection Settings N 8 1 F Data Rate 14 400 bps Terminal Emulation VT100 Login pirs For AESOP Questions FAX 41 512 891 8775 EMAIL aesop_sysop pirs aus sps mot com For Hotline Questions FAX US or Canada 1 800 248 8567 EMAIL aesop_support pirs aus sps mot com MOTOROLA MC68HC901 USER S MANUAL iii Applications and Technical Information For questions or comments pertaining to technical information questions and applications please contact one of the following sales offices nearest you Sales Offices Field Applications Engineering Available Through All Sales Offices UNITED STATES PASSI HE Dude ARIZONA Tempe CALIFORNIA Agoura Hills CALIFORNIA 5 CALIFORNIA Irvine CALIFORNIA Roseville CALIFORNIA San Diego CALIFORNIA Sunnyvale CO OA Colorado Springs COLORADO D CONNECTICUT Wallingford FLORIDA Maitland FLORIDA pompano Beach Fort Lauderdale FLORIDA Clearwater GEORGIA Atlanta IDAHO Boise ILLINOIS Chicago Hoffman Estates INDIANA Fort Wayne INDIANA Indianapolis INDIANA Kokomo ANS Cedar Rapids NSAS Kansas City Mission MARYLAND Columbia MASSACHUSETTS MASSACHUSETTS Woburn MICHIGAN perot BOTA PUNE Tons MISSOURI St Louis NEW JERSEY Fairfield NEW YORK Fairport NEW YORK Haup ppaug NEW YORK Pou keepsie Fishkil NORTH CAROLINA Raleigh OHIO Cleveland OHIO po
21. GPIP6 GPIP5 GPIP4 GPIP3 GPIP2 GPIP1 GPIPO RESET 0 0 0 0 0 0 0 0 ADDR 03 GPIP7 GPIPO General Purpose I O Port 0 Interrupts will be generated on the falling edge of the associated input signal 1 Interrupts will be generated on the rising edge of the associated input signal NOTE The inputs to the exclusive OR of the transition detector are the edge bit and the input buffer As a result writing the AER may cause an interrupt producing transition depending upon the state of the input So the AER should be configured before enabling interrupts via the interrupt enable registers IERA and IERB Also changing the edge bit while interrupts are enabled may cause an interrupt on the corresponding channel 5 1 3 Data Direction Register DDR The data direction register DDR allows the programmer to define IO through I7 as inputs or outputs by writing the corresponding bit When a bit of the data direction register is written as a zero the corresponding interrupt I O pin will be a high impedance input Writing a one to any bit of the data direction register will cause the corresponding pin to be configured as a push pull output DDR REGISTER BIT 7 6 5 4 3 2 1 0 FIELD GPIP7 GPIP6 GPIP5 GPIP4 GPIP3 GPIP2 GPIP1 GPIPO RESET 0 0 0 0 0 0 0 0 ADDR 05 GPIP7 GPIPO General Purpose I O Port 0 Associated I O line is defined to be an input 1 Associated line is defined t
22. Input Leakage Current Vi 0 to Vcc lu 10 uA Hi Z Output Leakage Current in Float Vout 2 4 to ILoH 10 Hi Z Output Leakage Current in Float Vout 0 5 V lio 10 DTACK Output Source Current Vout 2 4 V lou 400 DTACK Output Sink Current Voy 0 5 V loL 5 3 mA 8 5 CAPACITANCE TA 25 C f 1 MHz unmeasured pins returned to ground Input Capacitance Hi Z Output Capacitance Cout 10 pF Load DTACK C 100 pF All Other Outputs 130 MOTOROLA MC68HC901 USER S MANUAL 8 3 Electrical Characteristics 8 6 CLOCK TIMING See Figure 8 1 1 t 250 ns Cycle Time 1000 2 3 Clock Pulse Width 110 485 4 5 Rise and Fall Times tcr 15 ns Figure 8 1 Clock Input Timing Diagram 10 pF e XTAL1 Crystal Parameters Parallel resonance fundamental mode AT cut Rg lt 150 f 2 8 4 0 MHz MC68HC901 YI Rg lt 300 Q f 2 0 2 7 MHz CL 18 pF Cy 0 02 pF 5 pF Ly 96 MHz F f typical 2 4576 MHz e XTAL2 Figure 8 2 MFP External Oscillator Components 8 4 MC68HC901 USER S MANUAL MOTOROLA Electrical Characteristics 8 7 AC ELECTRICAL CHARACTERISTICS Vec 5 0 5 GND 0 Vdc T4 0 C to 70 C unless otherwise noted see Figures 8 3 through 8 12
23. Interrupt Enable 1 Enable 0 Disable Timer B Timer B Interrupt Enable 1 Enable 0 Disable IERB REGISTER BIT 7 6 5 4 3 2 1 0 FIELD GPIP5 4 TIMERC TIMERD GPIP3 GPIP2 GPIP1 GPIPO RESET 0 0 0 0 0 0 0 0 ADDR 09 GPIP5 GPIP4 General Purpose Interrupt Enable 1 Enable 0 Disable Timer C Timer C Interrupt Enable 1 Enable 0 Disable Timer D Timer D Interrupt Enable 1 Enable 0 Disable GPIP3 GPIPO General Purpose Interrupt Enable 1 Enable 0 Disable 4 5 MC68HC901 USER S MANUAL MOTOROLA Interrupt Structure 4 3 2 Interrupt Pending Registers IPRA IPRB When an interrupt is received on an enabled channel the corresponding interrupt pending bit is set in interrupt pending register A or B IPRA or IPRB In a vectored interrupt scheme this bit will be cleared when the processor acknowledges the interrupting channel and the MFP responds with a vector number In a polled interrupt system the interrupt pending registers must be read to determine the interrupting channel and then the interrupt pending bit is cleared by the interrupt handling routine without performing an interrupt acknowledge sequence IPRA REGISTER BIT 7 6 5 4 3 2 1 0 RCV XMIT RCV XMIT FIELD GPIP7 GPIP6 BUFFER BUFFER TIMER B FULL ERROR ERROR RESET 0 0 0 0 0 0 0 0 ADDR 0B GPIP7 GPIP6
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25. My MOTOROLA MC68HC901 Multi Function Peripheral User s Manual Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal
26. Pulse Width Measurement Operation Besides the delay mode timers A and B may be programmed to operate in the pulse width measurement mode In this mode an auxiliary control input is required timers A and B auxiliary input lines are TAI and TBI Also in the pulse width measurement mode interrupt channels normally associated with I4 and 13 will instead respond to transitions on TAI and TBI respectively General purpose lines and 14 may still be used for I O but may not be used as interrupt generating inputs A conceptual circuit of the selection of the interrupt source is shown in Figure 6 1 TAI TIMER A PULSE WIDTH MODE INTERRUPT CHANNEL ERES TIMER B PULSE WIDTH MODE INTERRUPT CHANNEL 0011 TBI Figure 6 1 Conceptual Circuit of Interrupt Source Selection The pulse width measurement mode functions similarly to the delay mode with the auxiliary control signal acting as an enable to the timer When the control signal is active the prescaler and main counter are allowed to operate When the control signal is negated the timer is stopped So the width of the active pulse on TAI is measured by the number of timer counts which occur while the timer is allowed to operate The active state of the auxiliary input line is defined by the associated interrupt channel s edge bit in the active edge register AER GPIP4 of the AER is the edge bit associated with TAI
27. When the divide by one clock mode is selected synchronization must be accomplished externally The receiver will sample serial data on the rising edge of the receiver clock In the divide by 16 clock mode the data is sampled at mid bit time to increase transient noise rejection Also when the divide by 16 clock mode is selected the USART re synchronization logic is enabled This logic increases the channels clock skew tolerance Refer to Section 7 1 1 Asynchronous Format for more information on the re synchronization logic MOTOROLA MC68HC901 USER S MANUAL 7 1 Universal Synchronous Asynchronous Receiver Transmitter 7 1 1 Asynchronous Format Variable character length and start stop bit configurations are available under software control for asynchronous operation The user can choose a character length from five to eight bits and a stop bit length of one one and one half or two bits The user can also select odd even or no parity In the asynchronous format start bit detection is always enabled New data is not shifted into the receive shift register until a zero bit is received When the divide by 16 clock mode is selected the false start bit logic is also active Any transition must be stable for three positive receive clock edges to be considered valid For a start bit to be good a valid zero to one transition must not occur for eight positive receiver clock transitions after the initial one to zero transition After a valid
28. all zeros with not stop bit this bit cannot be set until transmitter is enabled and internal reset and initialization is complete 1 Break transmitted and transmission stops 0 Break ceases and normal transmission resumes H L High and Low These bits configure the transmitter output SO when the transmitter is disabled Changing these bits after the transmitter is enabled will not alter the output state until END is cleared 0 1 Low 1 0 High 1 1 Loopback Mode TE Transmitter Enable The serial output will be driven according to H and L bits until transmission begins A one bit is transmitted before character transmission in the TSR begins 1 Transmitter enabled 0 2 Transmitter disabled The UE bit is cleared and the END bit is set 7 4 DMA OPERATION USART error conditions are valid only for each character boundary When the USART performs block data transfers by using the DMA handshake lines receiver ready RR and transmitter ready TR errors must be saved and checked at the end of a block This is accomplished by enabling the error channel for the receiver or transmitter and by masking 7 9 MC68HC901 USER S MANUAL MOTOROLA Universal Synchronous Asynchronous Receiver Transmitter interrupts for this channel Once the transfer is complete interrupt pending register A is read Any pending receiver or transmitter error indicates an error in the data transfer RR is asserted when the buffer full b
29. and is associated with TBI When the edge bit is a one the auxiliary input will be active high enabling the timer while the input signal is at a high level If the edge bit is zero the auxiliary input will be active low and the timer will operate while the input signal is at a low level 6 2 MC68HC901 USER S MANUAL MOTOROLA Timers The state of the active edge bit also specifies whether a zero to one transition or a one to zero transition of the auxiliary input pin will produce an interrupt when the interrupt channel is enabled In normal operation programming the active edge bit to a one will produce an interrupt on the zero to one transition of the associated input signal Alternately programming the edge bit to a zero will produce an interrupt on the one to zero transition of the input signal However in the pulse width measurement mode the interrupt generated by atransition on TAI or TBI will occur on the opposite transition as that normally defined by the edge bit For example in the pulse width measurement mode if the edge bit is a one the timer will be allowed to run while the auxiliary input is high When the input transitions from high to low the timer will stop and if the interrupt channel is enabled an interrupt will occur By having the interrupt occur on the one to zero transition instead of the zero to one transition the processor will be interrupted when the pulse being measured has been terminated and the
30. assembled until the RSR is read 7 5 MC68HC901 USER S MANUAL MOTOROLA Universal Synchronous Asynchronous Receiver Transmitter 1 Receiver buffer full and incoming word received 0 Read by RSR PE Parity Error 1 Parity error detected on character transfer to receiver buffer 0 No parity error detected on character transfer to receiver buffer FE Frame Error A frame error exists when a non zero data character is not followed by a stop bit in the asynchronous character format 1 Frame error detected on character transfer to receiver buffer 0 No frame error detected on character transfer to receiver buffer F S or B Found Search or Break Detect The F S bit is used in the synchronous character format When set to zero the USART receiver is placed in the search mode F S is cleared when the incoming character does not match the synchronous character 1 Match found Character length counter enabled 0 Incoming data compared to SCR Character length counter disabled The B bit is used in the asynchronous character format this flag indicates a break condition which continues until a non zero data bit is received 1 Character transferred to the receive buffer is a break condition 0 Non zero data bit received and break condition was acknowledged by reading the RSR at least once M or CIP Match Character in Progress The M bit is used in the synchronous character format and indicates a synchronous
31. from requesting interrupt service IRQ to the processor as long as the mask bit for that channel is cleared If a channel is requesting interrupt service at the time that its corresponding bit in IMRA or IMRB is cleared the request will cease and IRQ will be negated unless another channel is requesting interrupt service Later when the mask bit is set any pending interrupt on the channel will be processed according to the channel s assigned priority IMRA and IMRB may be read at any time Figure 4 2 provides a conceptual circuit of an MFP interrupt channel IMRA REGISTER BIT 7 6 5 4 3 2 1 0 RCV XMIT FIELD GPIP7 GPIP6 TIMER A BUFFER EROR BUFFER ERA TIMER B FULL EMPTY RESET 0 0 0 0 0 0 0 0 ADDR 13 GPIP7 GPIP6 General Purpose Interrupt Mask 1 Unmask 0 Mask Timer A Timer A Interrupt Mask 1 Unmask 0 Mask Receiver Buffer Full Receiver Buffer Full Interrupt Mask 1 Unmask 0 Mask Receiver Error Receiver Buffer Full Interrupt Mask 1 Unmask 0 Mask Transmitter Buffer Empty Transmitter Buffer Interrupt Mask 1 Unmask 0 Mask Transmitter Error Transmitter Error Interrupt Mask 1 Unmask 0 Mask 4 8 MC68HC901 USER S MANUAL MOTOROLA Interrupt Structure Timer B Timer B Interrupt Mask 1 Unmask 0 Mask IMRB REGISTER BIT 7 6 5 4 3 2 1 0 FIELD GPIP5 4 TIMERC TIMERD G
32. of the register which is selected by the register select bus RS1 through RS5 on the data bus DO through D7 and then assert DTACK The register addresses are shown in Table 1 1 After the processor has latched the data it negates DS The negation of either CS or DS will terminate the read operation The MFP will drive DTACK high and place it and the data bus in the high impedance state The timing for a read cycle is shown in Figure 3 1 Refer to Section 8 7 AC Electrical Characteristics for actual timing numbers MOTOROLA MC68HC901 USER S MANUAL 3 1 Bus Operation DTACK Figure 3 1 Read Cycle Timing Diagram 3 1 2 Write Cycle To write a register CS and DS must be asserted and R W must be low The MFP will decode the address bus to determine which register is selected Then the register will be loaded with the contents of the data bus on the next valid falling edge of CLK and DTACK will be asserted When the processor recognizes DTACK it will negate DS The write cycle is terminated when either CS or DS is negated The MFP will drive DTACK high and place itin the high impedance state The timing for a write cycle is shown in Figure 3 2 Refer to Section 8 7 AC Electrical Characteristics for actual timing numbers DTACK N Figure 3 2 Write Cycle Timing Diagram 3 2 INTERRUPT ACKNOWLEDGE OPERATION The MFP has 16 interrupt sources eight internal and eight external When an interrupt request is pending
33. the MFP will assert IRQ In a vectored interrupt scheme the processor will acknowledge the interrupt request by performing an interrupt acknowledge cycle and DS will be asserted The responds to the signal by placing a vector number on the data bus This vector number corresponds to the particular interrupt channel requesting service The format of this vector number is further discussed in Section 4 1 2 Interrupt Vector Number 3 2 MC68HC901 USER S MANUAL MOTOROLA Bus Operation When the MFP asserts DTACK to indicate that valid data is on the bus the processor will latch the data and terminate the bus cycle by negating DS When either DS or is negated the MFP will terminate the interrupt acknowledge operation by driving DTACK high and placing it in the high impedance state IRQ will be negated as a result of the IACK cycle unless additional interrupts are pending The MFP can be part of a daisy chain interrupt structure which allows multiple MFPs to be placed at the same interrupt level by sharing a common IACK signal A daisy chain priority scheme is implemented with signals IEI and IEO IEI indicates that no higher priority device is requesting interrupt service IEO signals lower priority devices that neither this device nor any higher priority MFP is requesting service To daisy chain MFPs the highest priority MFP has its IEI tied low and successive MFPs have their connected to the nex
34. width of the pulse from the timer is available After reading the contents of the timer the processor must re initialize the main counter by writing to the timer data register to allow consecutive pulses to be measured If the data register is written after the auxiliary input signal becomes active the timer will count from the previous contents of the timer data register until it counts through 01 hexadecimal At that time the main counter is loaded with the new value from the timer data register a time out pulse is generated which will toggle the timer output and an interrupt may be optionally generated on the timer interrupt channel Note that the pulse width measured includes counts from before the main counter was reloaded If the timer data register is written while the pulse is transitioning to the active state an indeterminate value may be written into the main counter Once the timer is reprogrammed for another mode interrupts will again occur as normally defined by the edge bit Note that an interrupt may be generated as the result of placing the timer into the pulse width measurement mode or by reprogramming the timer for another mode Also an interrupt may be generated by changing the state of the edge bit while in the pulse width measurement mode 6 1 3 Event Count Mode Operation In addition to the delay mode and the pulse width measurement mode timers A and B may be programmed to operate in the event count mode Like the pul
35. 1 USART Registers Receiver Status Register RSR 7 5 Synchronous Character Register SCR 7 2 Transmitter Status Register seeded PR 7 8 USART Control Register EPA Eo ab tS UR 7 3 USART Data Register UDR 7 4 Vector Register VR 4 2 INDEX 3 Index VR registar 4 2 W Write Cycle Timing 8 8 Write Cycle Timing Diagram 3 2 INDEX 4 MC68HC901 USER S MANUAL MOTOROLA
36. 2 505 2 Ye YS HYBRID COMPONENTS RESELLERS Elmo Semiconductor Minco Technology Labs Inc Semi Dice Inc MC68HC901 USER S MANUAL 818 768 7400 512 834 2022 310 594 4631 MOTOROLA The complete documentation package for the MC68HC901 consists of the MC68HC901UM AD and the M68000 Family Programmer s Reference Manual which contains the complete instruction set for the M68000 Family The MC68HC901 Multi Function Peripheral User s Manual describes the programming capabilities registers and operation of the MC68HC901 This device is the HCMOS version of the older MC68901 device and provides enhanced performance in several areas The MC68HC901 provides full function single channel USART an eight source interrupt controller four 8 bit timers and eight parallel I O lines The organization of this manual is as follows Section 1 Section 2 Section 3 Section 4 Section 5 Section 6 Section 7 Section 8 Section 9 Introduction Signal Description Bus Operation Interrupt Structure General Purpose Input Output Port Timers Universal Synchronous Asynchronous Receiver Transmitter Electrical Characteristics Mechanical Data and Ordering Information MC68HC901 USER S MANUAL MOTOROLA TABLE OF CONTENTS Paragraph Page Number Title Number Section 1 Introduction 1 1 once iene eeu dte aum Hs u aaa 1 2 1 2 Register Programming
37. CR The bits in the control register select the operation mode prescaler value and disable the timers Both control registers have bits which allow the programmer to reset output lines TAO and TBO 6 4 MC68HC901 USER S MANUAL MOTOROLA Timers TACR REGISTER BIT 7 6 5 4 3 2 1 0 RESET FIELD TAG 2 AC1 ACO RESET 0 0 0 0 0 0 0 0 ADDR 19 TBCR REGISTER BIT 7 6 5 4 3 2 1 0 N RESET FIELD ERR BC3 BC2 BC1 BCO RESET 0 0 0 0 0 0 0 0 ADDR 1B Bits 7 5 Unused Unused bits read as zero Reset TAO TBO Reset Timer A and B Output TAO and TBO may be forced low at any time by writing a one to the reset location in TACR and TBCR Output is held low during the write operation and at the end of the bus cycle the output is allowed to toggle in response to a time out pulse When resetting TAO and TBO the other bits in the TCR must be written with their previous value to avoid altering the operating mode ACS3 ACO BC3 BCO Select Timer A and B Operation Mode When the timer is stopped counting is inhibited The contents of the timer s main counter are not affected although any residual count in the prescaler is lost Delay Mode 4 Prescaler Delay Mode 10 Prescaler Delay Mode 16 Prescaler Delay Mode 50 Prescaler Delay Mode 64 Prescaler Delay Mode 100 Prescaler Delay Mode 200 Presca
38. Enable Registers IERB 4 4 4 3 2 Interrupt Pending Registers IPRA IPRB 4 6 4 3 3 Interrupt Mask Registers IMRA 4 8 4 3 4 Interrupt In Service Registers ISRA ISRB 4 10 4 4 Nesting 22 toe be 4 11 4 4 1 Selecting the End Of Interrupt Mode 4 11 4 4 2 Automatic End Of Interrupt Mode 4 12 4 4 3 Software End Of Interrupt Mode 4 12 Section 5 General Purpose Input Output Port 5 1 GPIP Control Registers ie deni 5 1 5 1 1 General Purpose I O Data Register 5 1 5 1 2 Active Edge Register AER 5 1 5 1 3 Data Direction Register DDR 244222 02 5 2 Section 6 Timers 6 1 Operation Modes ots ha debut a Me eMe c dcm ue 6 1 6 1 1 Delay Mode Operation 08 6 1 6 1 2 Pulse Width Measurement Operation 2 6 2 6 1 3 Event Count Mode Operation 6 3 6 2 Mimer itecto funt a
39. GISTERS The four timers are programmed via three control registers and four data registers The following paragraphs describe the different registers 6 2 1 Timer Data Registers TxDR The four timer data registers TDRs are designated as Timer A data register TADR Timer B data register TBDR Timer C data register TCDR and Timer D data register TDDR Each timer s main counter is an 8 bit binary down counter The timer data registers contain the value of their respective main counter This value was captured on the last low to high transition of the data strobe pin The main counter is initialized by writing to the TDR If the timer is stopped data is loaded simultaneously into both the TDR and main counter If the TDR is written to while the timer is enabled the value is not loaded into the timer until the timer counts through 01 hexadecimal If a write is performed while the timer is counting through 01 then an indeterminate value will be loaded into the timer s main counter TxDR REGISTER BIT 7 6 5 4 3 2 1 0 FIELD D7 D6 D5 D4 D3 D2 D1 DO RESET 0 0 0 0 0 0 0 0 ADDR 1F 21 23 25 7 Data 0 Cleared 1 Set 6 2 2 Timer Control Registers TxCR Timer A control register TACR and timer B control register TBCR are associated with timers A and B respectively Timers C and D are programmed using one control register the timer C and D control register TCD
40. General Purpose Interrupt 7 I7 1 1 1 0 General Purpose Interrupt 6 16 1 1 0 1 Timer A 1 1 0 0 Receiver Buffer Full 1 0 1 1 Receive Error 1 0 1 0 Transmit Buffer Empty 1 0 0 1 Transmit Error 1 0 0 0 Timer B 0 1 1 1 General Purpose Interrupt 5 15 0 1 1 0 General Purpose Interrupt 4 14 0 1 0 1 Timer C 0 1 0 0 Timer D 0 0 1 1 General Purpose Interrupt 3 I3 0 0 1 0 General Purpose Interrupt 2 I2 0 0 0 1 General Purpose Interrupt 1 11 0 0 0 0 General Purpose Interrupt O 10 4 1 3 Vector Register VR This 8 bit register determines the four most significant bits in the interrupt vector format and which end of interrupt mode is used in a vectored interrupt scheme The vector register should be written to before writing to the interrupt mask or enable registers to ensure that the MFP responds to an interrupt acknowledge cycle with a vector number not in the range of allowable user vectors For information refer to Section 4 4 1 Selecting the End Of Interrupt Mode VR REGISTER BIT 7 6 5 4 3 2 1 0 FIELD V7 V6 V5 V4 S RESET 0 0 0 0 0 0 0 0 ADDR 17 4 2 MC68HC901 USER S MANUAL MOTOROLA Interrupt Structure V7 V4 Vector These upper four bits of the vector register are written by the user These bits become the most significant four bits of the interrupt vector number S In Service Register Enable 1 Sof
41. NSIONING AND TOLERANCING PER ANSI 14 5 1982 HN 6 CONTROLLING DIMENSION INCH SET CMTE ECE BIEL 7 THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 012 300 DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST U 11905 1920 0 750 0 756 EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH TIE BAR V 1 07 121 0 042 0 048 BURRS GATE BURRS AND INTERLEAD FLASH BUT INCLUDING ANY MISMATCH w 107 1 21 0042 0 048 BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY X 107 142 0 042 0 056 8 DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION THE Y 050 0020 DAMBAR PROTRUSION S SHALL NOT CAUSE THE H DIMENSION TO BE GREATER 2 109 29 102 THAN 037 940 THE DAMBAR INSTRUSION S SHALL NOT CAUSE THE Gi 1804 1854 0710 0 730 DIMEMSION TO BE SMALLER THAN 025 635 Ki 1 02 0 040 MOTOROLA Figure 9 4 Case 778 02 Suffix MC68HC901 USER S MANUAL 9 3 Mechanical Data and Ordering Information 9 3 ORDERING INFORMATION PACKAGE TYPE MAXIMUM CLOCK TEMPERATURE RANGE ORDER NUMBER FREQUENCY Plastic P Suffix 4 0 MHz 0 70 C MC68HC901P Quad Pack FN Suffix 4 0 MHz 0 70 C MC68HC901FN 9 4 MC68HC901 USER S MANUAL MOTOROLA Numerics 48 Pin Dual In Line Package 9 1 DDR a 52 Lead QUAD Package 9 2 Delay Mode Operationens A Diagram s Clock In
42. PIP3 GPIP2 GPIP1 GPIPO RESET 0 0 0 0 0 0 0 0 ADDR 15 GPIP5 GPIP4 General Purpose Interrupt Mask 1 Unmask 0 Mask Timer C Timer C Interrupt Mask 1 Unmask 0 Mask Timer D Timer D Interrupt Mask 1 Unmask 0 Mask GPIP3 GPIPO General Purpose Interrupt Mask 1 Unmask 0 Mask INTERRUPT IN SERVICE INTERRUPT REQUEST e PASS VECTOR Figure 4 2 Conceptual Circuits of an Interrupt Channel 4 9 MC68HC901 USER S MANUAL MOTOROLA Interrupt Structure 4 3 4 Interrupt In Service Registers ISRA ISRB These registers indicate whether interrupt processing is in progress for a certain channel A bit is set whenever an interrupt vector number is passed for a interrupt channel during an IACK cycle and the S bit of the vector register is a one The bit is cleared whenever interrupt service is complete for an associated interrupt channel the S bit of the vector register is cleared or the processor writes a zero to the bit ISRA REGISTER BIT 7 6 5 4 3 2 1 0 RCV XMIT FIELD GPIP7 GPIP6 TIMERA BUFFER BUFFER EROR TIMER B FULL EMPTY RESET 0 0 0 0 0 0 0 0 ADDR 0F GPIP7 GPIP6 General Purpose Interrupt Servicing 1 In service 0 No service in progress Timer A Timer A Interrupt Servicing 1 In service 0 No service in progress Receiver Buffer Full Receiver Buffer Full Interrupt Servicing 1 In service 0 No service in
43. SRA or ISRB and ones to all other bit positions Since bits in the in service registers can only be cleared in software and not set writing ones to the registers does not alter their contents ISRA and ISRB may be read at any time 4 12 MC68HC901 USER S MANUAL MOTOROLA SECTION 5 GENERAL PURPOSE INPUT OUTPUT PORT The general purpose input output I O port GPIP provides eight I O lines 10 through 17 that may be operated as either inputs or outputs under software control In addition these lines may optionally generate an interrupt on either a positive transition or a negative transition of the input signal The flexibility of the GPIP allows it to be configured as an 8 bit I O port or for bit I O Since interrupts are enabled on bit by bit basis a subset of the GPIP could be programmed as handshake lines or the port could be connected to as many as eight external interrupt sources which would be prioritized by the MFP interrupt controller for the interrupt service 5 1 GPIP CONTROL REGISTERS The GPIP is programmed via three control registers These registers control the data direction provide user access to the port and specify the active edge for each bit of the GPIP which will produce an interrupt These registers are described in detail in the following paragraphs 5 1 1 General Purpose Data Register GPDR The general purpose l O data register is used to input data from or output data to the port When data is written t
44. SRB register 4 11 K Key Features 1 2 M Maximum Ratings 8 1 MC68000 Family 1 1 MC68HC901 Multi Function Peripheral 1 4 Mechanical Data and Ordering Information 9 1 MEP Block Diagram 1 1 MFP External Oscillator Components 8 4 Register 1 2 Operation Modes 6 1 Ordering Information 9 4 P Package Dimensions 9 2 Pin Assignments 9 1 Port HEP 8 10 Power Considerations 8 2 Power Supply Signals 2 1 programming registers 1 2 Pulse Width Measurement Operation 6 2 R Read Cycle Timing 8 8 Read Cycle Timing Diagram 3 2 HOGOlVOl a 7 4 Receiver Interrupt Channels 7 5 MOTOROLA Index Receiver Timing 8 11 register programming 1 2 Register Select Bus Signals 2 2 Reset Operation
45. acteristics ES Receiver Ready RR Delay from Rising RC Transmitter Ready TR Delay from Rising TC 600 ns 30 TxO A or B Low from Rising Edge of CS or DS Reset Time 450 ns 313 Timer Output TxO Valid from Falling t k that Causes Timeout 2 tox 300 ns 32 Timer Clock Low Time 110 ns 33 Timer Clock tg High Time 110 ns 34 Timer Clock Cycle Time 250 1000 ns 35 RESET Low Time 2 us 36 Delay to Falling from Ix Active Transition 380 ns 37 Transmitter Interrupt Delay from Falling Edge of TC 550 ns 38 Receiver Interrupt Delay from Rising Edge of RC Buffer Full 800 ns 39 Receiver Interrupt Delay from Falling Edge of RC Error 800 ns 40 SI Setup Time from Rising Edge of RC Divide by 1 Only 80 ns 41 SI Hold Time from Rising Edge of RC Divide by 1 Only 350 ns 42 SO Data Valid from Falling Edge of TC Divide by 1 Only 440 ns 43 TC Low Time 500 ns 44 TC High Time 500 ns 45 TC Cycle Time 1 05 oo us 46 RC Low Time 500 ns 47 RC High Time 500 ns 48 RC Cycle Time 1 05 oo us 493 CS IACK DS Width Low 80 50 SO Data Valid from Falling Edge of TC Divide by 16 Only 490 ns NOTES 1 If the setup time is not met CS will not be recognized until the next falling clock 2 If this setup time is met for consecutive cycles the minimum hold off time of one clock cycle will be obtained If not m
46. ared In addition the general purpose interrupt MOTOROLA MC68HC901 USER S MANUAL 3 3 Bus Operation I O lines are placed in the high impedance input mode and the timer outputs are driven low External MFP signals are negated Since the vector register VR is initialized to a 00 an uninitialized MFP may not respond to an interrupt acknowledge cycle with the uninitialized interrupt vector 0F Refer to Section 4 1 2 Interrupt Vector Number for more information 3 4 MC68HC901 USER S MANUAL MOTOROLA SECTION 4 INTERRUPT STRUCTURE In an M68000 system the MFP will be assigned to one of the seven possible interrupt levels All interrupt service requests from the MFP 16 interrupt channels will be presented at this level As an interrupt controller the MFP will internally prioritize its 16 interrupt sources Additional interrupt sources may be placed at the same interrupt level by daisy chaining multiple MFPs The MFPs will be prioritized by their position in the chain 4 1 INTERRUPT PROCESSING Each MFP provides individual interrupt capability for its various functions When an interrupt is received on one of the external interrupt channels or from one of the eight internal sources the MFP will request interrupt service The 16 interrupt channels are assigned a fixed priority so that multiple pending interrupts are serviced according to their relative importance Since the MFP can internally generate 16 vector numbers the unique vector
47. astic Yes 52 Lead QUAD Yes NOTES 1 DIMENSIONS AND TOLERANCING PER ANSI 14 5 1982 CONTROLLING DIMENSION INCH m TIP TAPER 3 DIMENSION L TO CENTER OF LEAD WHEN DETAIL X FORMED PARALLEL 4 DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH MAXIMUM MOLD FLASH 0 25 0 010 INCHES MILLIMETERS DIM MIN MAX MIN MAX cC L A 2415 2445 61 34 62 10 B 0540 0560 1372 1422 PEE EEEE a C 0455 0200 394 508 T a d i D 001 036 055 F 0440 0460 102 152 G 0100856 254 BSC SEATING P M 48 PL H 0070BSC 179 BSC PLANE DETAIL X N z le J 0 008 0015 020 0 38 F G K o5 0150 292 J 48 PL L 0 600 BSC 15 24 BSC 155 0 15 0 25 0 010 T B N 020 0040 08171101 0 51 0 020 T Figure 9 3 Case 767 02 P Suffix 9 2 MC68HC901 USER S MANUAL MOTOROLA Mechanical Data and Ordering Information
48. d also separate receive and transmit status and data bytes The receive and transmit sections are also assigned separate interrupt channels Each section has two interrupt channels one for normal conditions another for error conditions All interrupt channels are edge triggered Generally it is the output of a flag bit or bits which is coupled to the interrupt channel Thus if an interrupt producing event occurs while the associated interrupt channel is disabled no interrupt would be produced even if the channel was subsequently enabled because a transition did not occur while the channel was enabled That particular event would have to occur again generating another edge before an interrupt would be generated The interrupt channels may be disabled and instead a DMA device can be used to transfer the data via the control signals receiver ready RR and transmitter ready TR Refer to Section 7 4 DMA Operation for more information 7 1 CHARACTER PROTOCOLS The MFP USART supports asynchronous and with the help of a polynomial generator checker byte synchronous character formats These formats are selected independently of the divide by one and divide by 16 clock modes It is possible to clock data synchronously into the MFP but still use start and stop bits After a start bit is detected data will be shifted in and a stop bit will be checked to determine proper framing In this mode all normal asynchronous format features apply
49. ed independently of the voltage level high or low that they represent POWER SUPPLY GND 0 17 0 07 TAG cs MC68HC901 TCO CONTROL ASYNCHRONOUS DS MULTI FUNCTION TDO BUS CONTROL R W PERIPHERAL XTAL1 DTACK MFP XTAL2 RS1 Rss SI RESET SO SERIAL 1 0 pur RC CONTROL _IRQ TC INTERRUPT CONTROL RR DMA IEO TR CONTROL Figure 2 1 Input and Output Signals 2 1 POWER SUPPLY Vcc and GND Power is supplied to the MFP using these connections The pin is powered at 5 volts and ground is connected to the GND pins MOTOROLA MC68HC901 USER S MANUAL 2 1 Signal Description 2 2 CLOCK CLK The clock input is a single phase TTL compatible signal used for internal timing This input must conform to minimum pulse width times The clock is not necessarily the system clock in frequency or phase 2 3 DATA BUS D7 DO This three state bidirectional bus is used to transmit data to or receive data from the MFP internal registers during a processor read or write cycle respectively During an interrupt acknowledge cycle the data bus is used to pass a vector number to the processor The MFP must be located on data bus lines D7 DO when used with either the MC68000 series of microprocessors and on data lines D31 D24 when used with the MC68020 microprocessor if vectored interrupts are to be used 2 4 ASYNCHRONOUS BUS CONTROL Asynchronous data transfers are contr
50. er for additional information 2 10 4 Transmitter Clock TC This input controls the serial bit rate of the transmitter This signal may be supplied by the timer output lines or by an external TTL level clock which meets the minimum and maximum cycle times 2 11 DIRECT MEMORY ACCESS CONTROL The USART section of the MFP supports direct memory access transfers through its receiver ready and transmitter ready status lines 2 11 1 Receiver Ready RR This active low output reflects the receiver buffer full status bit 7 in the Receiver Status Register for DMA operations 2 11 2 Transmitter Ready TR This active low output reflects the transmitter buffer empty bit 7 in the Transmitter Status Register for DMA operations 2 12 SIGNAL SUMMARY The following table is a summary of all the signals discussed in the previous paragraphs Table 2 1 Signal Summary INPUT ACTIVE THREE RESET PINE MNEMONIG OUTPUT STATE STATE STATE Power Input Voc Input High Ground GND Input Low Clock CLK Input N A Chip Select cs Input Low DS Low Data Strobe DS Input Read Write R W Input Read High Write Low 2 5 MC68HC901 USER S MANUAL MOTOROLA Signal Description Table 2 1 Signal Summary Continued INPUT ACTIVE THREE RESET SIGNAL NAME STATE STATE STATE Data Transfer Acknowledge DTACK Output Register Select Bus RS1
51. eria cO pae Dur ERE qud 6 4 viii MC68HC901 USER S MANUAL MOTOROLA TABLE OF CONTENTS Continued Paragraph Page Number Title Number 6 2 1 Timer Data Registers 6 4 6 2 2 Timer Control Registers TxCR 1 6 4 Section 7 Universal Synchronous Asynchronous Receiver Transmitter 7 1 CharactemPEDIGODIS ita 7 1 7 1 1 Asynchronous Format I 7 2 7 1 2 Synchronous eiie 7 2 7 1 3 USART Control Register UCR ete ee 7 3 7 1 4 USART Data Register UDR 7 4 7 2 p D RI REMINDED RAE 7 4 7 2 1 Receiver Interrupt Channels 7 5 7 2 2 Receiver Status Register RSR 7 5 7 2 3 Special Receive Conditions 2 7 7 7 3 Loretta b 7 7 7 3 1 Transmitter Interrupt Channels bx hte eee 7 8 7 9 2 Transmitter Status Register TSR 7 8 7 4 tcI 7 9 Section 8 Electrical Characteristics 8 1 Maxim m ETE 8 1 8 2 Thermal 8 1 8 3 Power Considerations
52. escription 2 7 INTERRUPT CONTROL The interrupt request and interrupt acknowledge signals are handshake lines for a vectored interrupt scheme Interrupt enable in and interrupt enable out implement a daisy chained interrupt structure 2 7 1 Interrupt Request IRQ This active low open drain output signals to the processor that an interrupt is pending from the MFP There are 16 interrupt channels that can generate an interrupt request Clearing the interrupt pending registers IPRA and IPRB or clearing the interrupt mask registers IMRA and IMRB will cause the IRQ to be negated IRQ will also be negated as the result of an interrupt acknowledge cycle unless additional interrupts are pending in the MFP Refer to Section 4 Interrupt Structure for further information 2 7 2 Interrupt Acknowledge If both IRQ and are asserted the MFP will begin an interrupt acknowledge cycle when IACK and DS are asserted The MFP will supply a unique vector number to the processor which corresponds to the particular channel requesting interrupt service In a daisy chained interrupt structure all devices in the chain must have a common IACK Refer to Section 3 2 Interrupt Acknowledge Operation and Section 4 1 2 Interrupt Vector Number for additional information CS and IACK must not be asserted at the same time 2 7 3 Interrupt Enable In IEI This active low input together with the IEO signal provides a daisy chained interrupt
53. et the hold off time will be two clock cycles refers to the clock signal applied to the MFP CLK input pin tuk refers to the timer clock signal regardless of whether that signal comes from the XTAL1 XTAL2 crystal clock inputs or the TAI or TBI timer inputs 4 CS is latched internally therefore if specifications 1 and 24 are met then CS may be negated before the falling clock and still initiate a bus cycle 5 Although CS and DTACK are synchronized with the clock the data out during a read cycle is asynchronous to the clock relying only on CS for timing 8 6 MC68HC901 USER S MANUAL MOTOROLA Electrical Characteristics 8 8 TIMER AC CHARACTERISTICS Definitions Error Indicated time value actual time value tose x Prescale Value Internal Timer Mode Single Interval Error Free Running See Note 2 below 100 ns Cumulative Internal Error ea e one Ere eta ENS 0 Error Between Two Timer Reads tpsc 4 Start Timer to Stop Timer Error 2 tcLk 100 ns to 6 100 ns Start Timer to Read Timer Error 0 to 6 tci 400 ns Start Timer to Interrupt Request Error See Note 2 tck to 4 800 ns Pulse Width Measurement Mode Measurement Accuracy See Note 1 below 2 to tpsc 4
54. hen the timer has decremented down to 01 hexadecimal the next count pulse will cause the main counter to be reloaded from the timer data register and a time out pulse will be produced This time out pulse is coupled to the timer s interrupt channel and if the channel is enabled an interrupt will occur The time out pulse also causes the timer output pin to toggle The output will remain in this new state until the next time out pulse occurs For example if delay mode with a divide by 10 prescaler is selected and the timer data register is loaded with 100 decimal the main counter will decrement once every 10 timer clock cycles After 1000 timer clocks a time out pulse will be produced This time out pulse will generate an interrupt if the channel is enabled IERA IERB and in addition the timer s output line will toggle The output line will complete one full period every 2000 cycles of the timer clock If the prescaler value is changed while the timer is enabled the first time out pulse will occur at an indeterminate time no less than one or more than 200 timer clock cycles Subsequent time out pulses will then occur at the correct interval MOTOROLA MC68HC901 USER S MANUAL 6 1 Timers If the main counter is loaded with 01 hexadecimal a time out pulse will occur every time the prescaler presents a count pulse to the main counter If the main counter is loaded with 00 a time out pulse will occur every 256 count pulses 6 1 2
55. hould always be read before the receive buffer UDR to maintain the correct correspondence between data and flags Otherwise it is possible that after reading the UDR and prior to reading the RSR a new word could be received and transferred to the receive buffer Its associated flags would be latched into the RSR writing over the flags for the previous data word Thus when 7 4 MC68HC901 USER S MANUAL MOTOROLA Universal Synchronous Asynchronous Receiver Transmitter the RSR was read to access the status information for the first data word the flags for the new word would be retrieved 7 2 1 Receiver Interrupt Channels The USART receiver section is assigned two interrupt channels One indicates the buffer full condition while the other channel indicates an error condition Error conditions include overrun parity error frame error synchronous found and break These interrupting conditions correspond to the OE PE FE and F S or B bits of the receiver status register These flags will function as described in Section 7 2 2 Receiver Status Register whether the receiver interrupt channels are enabled or disabled While only one interrupt is generated per character received two dedicated interrupt channels allow separate vector numbers to be assigned for normal and abnormal receiver conditions When a received word has an error associated with it and the error interrupt channel is enabled an interrupt will be generated on the error chan
56. injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer 1995 Motorola Inc All Rights Reserved Trademarks Motorola and the Motorola symbol are registered trademark s of Motorola Inc ii MC68HC901 USER S MANUAL MOTOROLA 68K FAX IT Documentation Comments FAX 512 891 8593 Documentation Comments Only The Motorola High Performance Embedded Systems Technical Communications Department provides a fax number for you to submit any questions or comments about this document or how to order other documents We welcome your suggestions for improving our documentation Please do not fax technical questions Please provide the part number and revision number located in upper right hand corner of the cover and the title of the document When referring to items in the manual please reference by the page number paragraph number figure number table number and line number if needed When sending a fax please provide your name company fax number and phone number including area code For Internet Access Telnet pirs aus sps mot com Login pirs WWW http pirs aus sps mot com aesop hmpg html Query By Email aesop_query pirs aus sps mot com Type HELP in text body
57. it is set in the RSR unless a parity error or frame error is detected by the receiver TR is asserted when the buffer empty bit is set in the TSR unless a break is currently being transmitted 7 10 MC68HC901 USER S MANUAL MOTOROLA SECTION 8 ELECTRICAL CHARACTERISTICS This section contains the electrical specifications and associated timing information for the MC68HC901 multi function peripheral Refer to Section 9 Ordering Information and Mechanical Data for specific part numbers corresponding to voltage frequency and temperature rating 8 1 MAXIMUM RATINGS RATING SYMBOL VALUE UNIT This device contains circuitry to protect the inputs against damage Supply Voltage 0 3 to 7 0 due to high static voltages or electric fields however it is Input Voltage V 0 3 to 7 0 V advised that normal precautions i be taken to avoid application of Operating Temperature Range TA 0 to 70 any voltage higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level e g either Voc or GND Storage Temperature Range Tstg 65 to 150 C Power Dissipation Pp 0 21 NOTES 1 Permanent damage can occur if maximum ratings are exceeded Exposure to voltages or currents in excess of recommended values affects device reliability Device modules may not operate normally while being exposed to electrical extremes
58. ler Event Count Mode 6 5 MC68HC901 USER S MANUAL MOTOROLA Timers OPERATION MODE 1 0 0 1 Pulse Width Mode 4 Prescaler 1 0 1 0 Pulse Width Mode 10 Prescaler 1 0 1 1 Pulse Width Mode 16 Prescaler 1 1 0 0 Pulse Width Mode 50 Prescaler 1 1 0 1 Pulse Width Mode 64 Prescaler 1 1 1 0 Pulse Width Mode 100 Prescaler 1 1 1 1 Pulse Width Mode 200 Prescaler TCDCR REGISTER BIT 7 6 5 4 3 2 1 0 FIELD 2 CC1 CCO DC2 DC1 DCO RESET 0 0 0 0 0 0 0 0 ADDR 1D Bit 7 Bit 3 Unused Unused bits read as zero CC2 CCO DC2 DCO Select Timer C and D Operation Mode When the timer is stopped counting is inhibited The contents of the timer s main counter are not affected although any residual count in the prescaler is lost OPERATION MODE 0 0 0 Timer Stopped 0 0 1 Delay Mode 4 Prescaler 0 1 0 Delay Mode 10 Prescaler 0 1 1 Delay Mode 16 Prescaler 1 0 0 Delay Mode 50 Prescaler 1 0 1 Delay Mode 64 Prescaler 1 1 0 Delay Mode 100 Prescaler 1 1 1 Delay Mode 200 Prescaler 6 6 MC68HC901 USER S MANUAL MOTOROLA SECTION 7 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER The universal synchronous asynchronous receiver transmitter USART is a single full duplex serial channel with a double buffered receiver and transmitter There are separate receive and transmit clocks an
59. nel only However if the error channel is disabled an interrupt for an error condition will be generated on the buffer full interrupt channel along with interrupts produced by the buffer full condition The receiver status register must always be read to determine which error condition produced the interrupt 7 2 2 Receiver Status Register RSR The RSR contains the receiver buffer full flag the synchronous strip enable the various status information associated with the data word in the receive buffer The RSR is latched each time a data word is transferred to the receive buffer RSR flags cannot change again until the new data word has been read However the M CIP bit is allowed to change RSR REGISTER BIT 7 6 5 4 3 2 1 0 FIELD BF OE PE FE FSORB MORCIP 55 RESET 0 0 0 0 0 0 0 0 ADDR 2B BF Buffer Full Receiver word is transferred to the receive buffer Receiver buffer is read by accessing the USART data register 1 Receiver word transferred to buffer 0 Read by RSR Overrun Error Overrun error occurs when a received word is to be transferred to the receive buffer but the buffer is full Neither the receiver buffer nor the RSR is overwritten The OE bit is set after the receive buffer full condition is satisfied by reading the UDR This error condition will generate an interrupt to the processor The OE bit is cleared by reading the RSR New data words will not be
60. nsmission E O Even Odd Parity 1 Even parity is selected 0 Odd parity is selected Bit 0 Reserved by Motorola This bit is reserved and returns a zero when read 7 1 4 USART Data Register UDR This register is used to either provide the current data word in the receiver buffer or to provide data to the transmitter buffer UDR REGISTER D7 DO Data 0 Cleared 1 Set 7 2 RECEIVER As data is received on the serial input line SI it is clocked into an internal 8 bit shift register until the specified number of data bits have been assembled The character will then be transferred to the receive buffer assuming that the last word in the receive buffer has been read This transfer will set the buffer full bit in the receiver status register RSR and produce a buffer full interrupt to the processor assuming this interrupt has been enabled Reading the receive buffer satisfies the buffer full condition and allows a new data word to be transferred to the receive buffer when it is assembled The receive buffer is accessed by reading the USART data register UDR The UDR is simply an 8 bit data register used when transferring data between the MFP and the CPU Each time a word is transferred to the receive buffer its status information is latched into the receiver status register RSR The RSR is not updated again until the data word in the receive buffer has been read When a buffer full condition exists the RSR s
61. o Section 5 General Purpose Input Output Port for further information MOTOROLA MC68HC901 USER S MANUAL 2 3 Signal Description 2 9 TIMER CONTROL These lines provide internal timing and auxiliary timer control inputs required for certain operating modes Additionally the timer outputs are included in this group 2 9 1 Timer Inputs TAI and TBI These input lines are control signals for timers A and B in the pulse width measurement mode and the event count mode These signals generate interrupts at the same priority level as the general purpose interrupt lines 14 and respectively when in the pulse width measurement mode While 14 and do not have interrupt capability when timers A and are operated in this mode they may still be used for I O Refer to Section 6 1 2 Pulse Width Measurement Mode Operation and Section 6 1 3 Event Count Mode Operation for further information 2 9 2 Timer Outputs TAO TBO TCO and TDO Each timer has an associated output which toggles when its main counter counts through 01 hexadecimal regardless of which operational mode is selected When in the delay mode the timer output will be a square wave with a period equal to two timer cycles This output may be used to supply the universal synchronous asynchronous receiver transmitter USART baud rate clocks 2 9 3 Timer Clock XTAL1 and XTAL2 These pins provide the timing signal for the four timers A crystal can be connected between
62. o be an output 5 2 MC68HC901 USER S MANUAL MOTOROLA SECTION 6 TIMERS The MFP contains four 8 bit timers which provide many functions typically required in microprocessor systems The timers can supply the baud rate clocks for the on chip serial channel generate periodic interrupts measure elapsed time and count signal transitions In addition two timers have waveform generation capability All timers are prescaler counter timers with a common independent clock input XTAL1 and XTAL2 Each timer s output signal toggles when the timer s main counter times out Additionally timers A and B have auxiliary control signals TAI TBI which are used in two of the operation modes An interrupt channel is assigned to each timer and when the auxiliary control signals are used in the pulse width measurement mode a separate interrupt channel will respond to transitions on these inputs 6 1 OPERATION MODES Timers A and B are full function timers which in addition to the delay mode operate in the pulse width measurements mode and the event count mode Timers C and D are delay timers only A brief discussion of each of the timer modes follows 6 1 1 Delay Mode Operation All timers may operate in the delay mode In this mode the prescaler is always active The prescaler specifies the number of timer clock cycles which must elapse before a count pulse is applied to the main counter A count pulse causes the main counter to decrement by one W
63. o the GPDR those pins which are defined as inputs will remain in the high impedance state Pins which are defined as outputs will assume the state high or low of their corresponding bit in the data register When the GPDR is read data will be passed directly from the bits of the data register for pins which are defined as outputs Data from pins defined as inputs will come from the input buffers GPDR REGISTER BIT 7 6 5 4 3 2 1 0 FIELD GPIP7 GPIP6 GPIP5 GPIP4 GPIP3 GPIP2 GPIP1 GPIPO RESET 0 0 0 0 0 0 0 0 ADDR 01 GPIP7 GPIPO General Purpose I O Port 0 Cleared 1 Set 5 1 2 Active Edge Register AER The active edge register AER allows each of the GPIP lines to produce an interrupt on either a one to zero or a zero to one transition Writing a zero to the appropriate edge bit of MOTOROLA MC68HC901 USER S MANUAL 5 1 General Purpose Input Output Port the active edge register will cause the associated input to generate an interrupt on the one to zero transition Writing a one to the edge bit will produce an interrupt on the zero to one transition of the corresponding line When the processor sets a bit interrupts will be generated on the rising edge of the associated input signal When the processor clears a bit interrupts will be generated on the falling edge of the associated input signal AER REGISTER BIT 7 6 5 4 3 2 1 0 FIELD GPIP7
64. olled by chip select data strobe read write and data transfer acknowledge The register select lines RS5 RS1 select an internal MFP register for a read or write operation The reset line initializes the MFP registers and the internal control signals 2 4 1 Chip Select CS This active low input activates the for internal register access CS and must not be asserted at the same time 2 4 2 Data Strobe DS This active low input is part of the internal chip select and interrupt acknowledge functions 2 4 3 Read Write R W This input defines the current bus cycle as a read high or a write low cycle 2 4 4 Data Transfer Acknowledge DTACK This active low three state output signals the completion of the operation phase of a bus cycle to the processor If the bus cycle is a process read the MFP asserts DTACK to indicate that the information on the data bus is valid If the bus cycle is a processor write to the MFP DTACK acknowledges the acceptance of the data by the MFP DTACK will be asserted only by MFP that has CS or IACK and IEI asserted 2 5 REGISTER SELECT BUS RS1 RS5 The register select bus selects an internal MFP register during a read or write operation 2 6 RESET RESET This active low input will initialize the MFP during powerup or in response to a total system reset Refer to Section 3 3 Reset Operation for further information 2 2 MC68HC901 USER S MANUAL MOTOROLA Signal D
65. ort Timing 8 10 MC68HC901 USER S MANUAL MOTOROLA Electrical Characteristics 2 i RESET Figure 8 9 Reset Timing IRQ lt BUFFER FULL CONDITION _ _ IRQ ERROR CONDITION S DIVIDE BY 1 MODE ONLY _ Figure 8 10 Receiver Timing 44 DIVIDE BY 16 MODE _ i 50 DIVIDE BY 1 MODE _ RO Figure 8 11 Transmitter Timing 8 11 MC68HC901 USER S MANUAL MOTOROLA Electrical Characteristics XTAL1 XTAL2 CS DS INTERNAL TIMEOUT TAO TBO TCO TDO NOTE Specification 30 applies to timer outputs TAO and TBO only Figure 8 12 Timer Timing 8 12 MC68HC901 USER S MANUAL MOTOROLA SECTION 9 MECHANICAL DATA AND ORDERING INFORMATION This section contains the pin assignments package dimensions and ordering information for the MC68HC901 multi function peripheral 9 1 PIN ASSIGNMENTS PACKAGE MC68HC901 Yes 52 Lead QUAD Yes R W CS RS1 DS RS2 DTACK RS3 TACK RS4 D7 RS5 D6 TC D5 so D4 SI D3 RC D2 Vcc D1 NC DO TAO GND TBO CLK TCO IEO XTAL1 IRQ XTAL2 RR TAI TR TBI 7 RESET l6 Figure 9 1 48 Pin Dual In Line Package Plastic MOTOROLA MC68HC901 USER S MANUAL 9 1 Mechanical Data and Ordering Information D5 D3 D2 D1 GND CLK IEO RR TR Figure 9 2 52 Lead QUAD Package 9 2 PACKAGE DIMENSIONS 48 Pin Dual In Line Pl
66. progress Receiver Error Receiver Buffer Full Interrupt Servicing 1 In service 0 No service in progress Transmitter Buffer Empty Transmitter Buffer Interrupt Servicing 1 In service 0 No service in progress Transmitter Error Transmitter Error Interrupt Servicing 1 In service 0 No service in progress Timer B Timer B Interrupt Servicing 1 In service 0 No service in progress 4 10 MC68HC901 USER S MANUAL MOTOROLA Interrupt Structure ISRB REGISTER BIT 7 6 5 4 3 2 1 0 FIELD GPIP5 GPIP4 TIMERC D GPIP3 GPIP2 GPIP1 GPIPO RESET 0 0 0 0 0 0 0 0 ADDR 11 GPIP5 GPIP4 General Purpose Interrupt Servicing 1 In service 0 No service in progress Timer C Timer C Interrupt Servicing 1 In service 0 No service progress Timer D Timer D Interrupt Servicing 1 In service 0 No service in progress GPIP3 GPIPO General Purpose Interrupt Servicing 1 In service 0 No service in progress 4 4 NESTING MFP INTERRUPTS In an M68000 vectored interrupt system the MFP is assigned to one of seven possible interrupt levels When an interrupt is received from the MFP an interrupt acknowledge for that level is initiated Once an interrupt is recognized at a particular level interrupts at the same level or below are masked by the processor As long as the processor s interrupt mask is unchanged the M68000 interrup
67. put Timing AC Electrical Characteristics 8 5 IACK Cycle Timing poe Register AER Exec da Te B Interrupt Acknowledge Cycle Timina TEI High Asynchronous Bus Control 2 2 Interrupt S Asynchronous Format 7 2 Timing Low Automatic End Of Interrupt Interrupt Timing Node suu u HM E 4 12 Block 22222222222 Port Timing B Read Cycle Timing Bus Operation 3 1 Receiver Timing Reset Timing C Timer Timing Transmitter Timing Capacitance 8 3 Write Cycle Timing MNA Macer Drawings Direct Memory Access Control Case 767 02 Suffix 9 2 Signale Case 778 02 Suffix 9 3 DMA Operation QUU E SEATS A NET RUNS Character Formats 77772 DMA Operation Asynchronous 7 2 E Synchronous 7 2 Character Protocols 7 1 Electrical Characteristics Clock Input Timing Diagram 8 4 Event Count Mode Operation Clock Signal 2 2 Clock
68. r is passed to the processor during an interrupt acknowledge cycle the corresponding channel s interrupt pending bit is cleared In the automatic end of interrupt mode no further history of the interrupt remains in the MFP The in service bits of the interrupt in service registers ISRA and ISRB are forced low Subsequent interrupts which are received on any MFP channel will generate an interrupt request to the processor even if the current interrupt s service routine has not been completed 4 4 3 Software End Of Interrupt Mode In the software end of interrupt mode the channel s associated interrupt pending bit is cleared In addition the channel s in service bit of in service register A or B is set when its vector number is passed to the processor during the interrupt acknowledge cycle A higher priority channel may subsequently request interrupt service and be acknowledged but as long as the channel s in service bit is set no lower priority channel may request interrupt service nor pass its vector during an interrupt acknowledge sequence While only higher priority channels may request interrupt service any channel can receive an interrupt and set its interrupt pending bit Even the channel with its in service bit is set can receive a second interrupt However no interrupt service request is made until its in service bit is cleared The in service bit for a particular channel can be cleared by writing a zero to its corresponding bit in I
69. receive buffer is read Both the B and OE flags will be set when the buffer full condition is satisfied 7 3 TRANSMITTER The transmit buffer is loaded by writing to the USART data register UDR The data character will be transferred to an internal 8 bit shift register when the last character in the shift register has been transmitted This transfer will produce a buffer empty condition If the transmitter completes the transmission of the character in the shift register before a new character is written to the transmit buffer an underrun error will occur In the asynchronous character format the transmitter will send a mark until the transmit buffer is written In the synchronous character format the transmitter will continuously send the synchronous character until the transmit buffer is written The transmit buffer can be loaded prior to enabling the transmitter After the transmitter is enabled there is a delay before the first bit is output The serial output line SO should be programmed to be high low or high impedance by setting the appropriate bits in the transmitter status register TSR before the transmitter is enabled forcing the output line to the desired state until the first bit of the first character is shifted out The state of the H and L bits in the TSR determine the state of the first transmitted bit after the transmitter is enabled If the high impedance mode is selected prior to the transmitter being enabled the firs
70. rupt channel is enabled or disabled 7 3 2 Transmitter Status Register TSR The TSR contains various transmitter error flags and transmitter control bits for selecting auto turnaround and loopback mode TSR REGISTER BIT 7 6 5 4 3 2 1 0 FIELD BE UE AT END B H L TE RESET 0 0 0 0 0 0 0 0 ADDR 2D BE Buffer Empty 1 Character in the transmit buffer transferred to TSR 0 Transmit buffer reloaded by writing to the USR U Underrun Error One full transmitter clock cycle is required after UE bit is set before it can be cleared This bit does not require clearing before writing to the UDR 7 8 MC68HC901 USER S MANUAL MOTOROLA Universal Synchronous Asynchronous Receiver Transmitter 1 Character in the TSR was transmitted before a new word was loaded into the transmit buffer 0 Transmitter disabled or read performed on TSR AT Auto Turnaround When set the receiver will be enabled automatically after the transmitter has been disabled and the last character being transmitted is complete END End of Transmission If the transmitter is disabled while a character is being transmitted this bit is set after transmission is complete if no character was being transmitted then this bit is set immediately Re enabling the transmitter clears this bit B Break This bit only functions in the asynchronous format When B is set BE cannot be set A break consists of
71. se width measurement mode the event count mode requires an auxiliary input signal TAI or General purpose lines and 14 can be used for I O or as interrupt producing inputs In the event count mode the prescaler is disabled allowing each active transition on TAI and TBI to produce a count pulse The count pulse causes the main counter to decrement by one When the timer counts through 01 hexadecimal a time out pulse is generated which will cause the output signal to toggle and may optionally produce an interrupt via the associated timer interrupt channel The timer s main counter is also reloaded from the timer data register To count transitions reliably the input signal may only transition once every four timer clock periods For this reason the input signal must have a maximum frequency of one fourth that of the timer clock MOTOROLA MC68HC901 USER S MANUAL 6 3 Timers The active edge of the auxiliary input signal is defined by the associated channel s edge bit GPIP4 of the AER specifies the active edge for TAI and GPIP3 defines the active edge for TBI When the edge bit is programmed to a one a count pulse will be generated on the zero to one transition of the auxiliary input signal When the edge bit is programmed to a zero a count pulse will be generated on the one to zero transition Also note that changing the state of the edge bit while the timer is in the event count mode may produce a count pulse 6 2 TIMER RE
72. start bit has been detected the data is checked continuously for valid transitions When a valid transition is detected an internal counter is forced to state zero and no further transition checking is initiated until state four At state eight the previous state of the transition checking logic is clocked into the receiver As a result of this re synchronization logic it is possible to run with asynchronous clocks without start and stop bits if there are sufficient valid transitions in the data streams 7 1 2 Synchronous Format When the synchronous character format is selected the 8 bit synchronous character loaded into the synchronous character register SCR is compared to received serial data until a match is found Once synchronization is established incoming data is clocked into the receiver The synchronous word will be continuously transmitted during an underrun condition All synchronous characters can be optionally stripped from the receive buffer i e taken out of the data stream and thrown away by clearing the appropriate bit in the receive status register RSR SCR REGISTER BIT 7 6 5 4 3 2 1 0 FIELD D7 D6 D5 D4 D3 D2 D1 DO RESET 0 0 0 0 0 0 0 0 ADDR 27 7 Data 0 Cleared 1 Set The synchronous character should be written after the character length is selected since unused bits in the synchronous character register are zeroed out When parity is enabled s
73. ster must be cleared of pending transmitter errors at the beginning of the break transmission or no interrupts will be generated at the character boundary time The break B bit cannot be set until the transmitter has been enabled and has had sufficient time one transmitter clock cycle to perform internal reset and initialization functions Any character in the transmit buffer at the start of a break will be transmitted when the break is terminated assuming the transmitter is still enabled If the transmit buffer is empty at the start of a break it may be written at any time during the break If the buffer is still empty at the end of the break an underrun condition will exist Disabling the transmitter during a break condition causes the transmitter to cease transmission of the break character at the end of the current character No end of break stop bit will be transmitted Even if the transmit buffer is empty no buffer empty condition will occur nor will an underrun condition occur Also any word in the transmit buffer will remain 7 3 1 Transmitter Interrupt Channels The USART transmit section is assigned two interrupt channels The normal channel indicates a buffer empty condition and the error channel indicates an underrun or end condition These interrupting conditions correspond to the BE UE and END flags in the TSR The flag bits will function as described in Section 7 3 2 Transmitter Status Register whether their associated inter
74. structure for a vectored interrupt scheme indicates that no higher priority device is requesting interrupt service So the highest priority MFP in the chain should have its IEI pin tied low During an interrupt acknowledge cycle a MFP with a pending interrupt is not allowed to pass a vector number to the processor until its pin is asserted When the daisy chain option is not implemented all MFPs should have their IEI pin tied low Refer to Section 4 2 Daisy Chaining MFPs for additional information 2 7 4 Interrupt Enable Out IEO This active low output together with the signal provides a daisy chained interrupt structure for a vectored interrupt scheme The IEO of a particular MFP signals lower priority devices that neither it nor any other higher priority device is requesting interrupt service When a daisy chain is implemented IEO is tied to the next lower priority MFP IEI input The lowest priority MFP is not connected When the daisy chain option is not implemented IEO is not connected Refer to Section 4 2 Daisy Chaining MFPs for additional information 2 8 GENERAL PURPOSE I O INTERRUPT LINES 17 10 These lines constitute an 8 bit pin programmable port with interrupt capability The data direction register DDR individually defines each line as either a high impedance input or a TTL compatible output As an input each line can generate an interrupt on the user selected transition of the input signal Refer t
75. synchronous asynchronous receiver transmitter USART which supports asynchronous formats byte synchronous formats with the addition of a polynomial generator checker By incorporating multiple functions within the MFP the system designer retains flexibility while minimizing device count 1 2 REGISTER PROGRAMMING From a programmer s point of view the versatility of the MFP may be attributed to its register set The registers are well organized and allow the MFP to be easily tailored to a variety of applications All of the 24 registers are also directly addressable which simplifies programming The register map is shown in Table 1 1 Table 1 1 MFP Register Map ADDRESS HEX BINARY ABBREVIATION REGISTER NAME RS5 854 RS3 52 RS1 01 0 0 0 0 0 GPDR General Purpose O Data Register 03 0 0 0 0 1 AER Active Edge Register 05 0 0 0 1 0 DDR Data Direction Register 07 0 0 0 1 1 IERA Interrupt Enable Register A 09 0 0 1 0 0 IERB Interrupt Enable Register B 0B 0 0 1 0 1 IPRA Interrupt Pending Register A 00 0 0 1 1 0 IPRB Interrupt Pending Register B OF 0 0 1 1 1 ISRA Interrupt In service Register A 11 0 1 0 0 0 ISRB Interrupt In service Register B 13 0 1 0 0 1 IMRA Interrupt Mask Register A 15 0 1 0 1 0 IMRB Interrupt Mask Register B 1 2 MC68HC901 USER S MANUAL MOTOROLA Introduction Table 1 1 MFP Register Map Continued
76. t bit transmitted is indeterminate Note that the SO line will always be driven high for one bit time prior to the character in the transmit shift register being transmitted when the transmitter is first enabled When the transmitter is disabled any character currently being transmitted will continue to completion However any character in the transmit buffer will not be transmitted and will remain in the buffer Thus no buffer empty condition will occur If the buffer is empty when the transmitter is disabled the buffer empty condition will remain but no underrun condition will be generated when the character in transmission is completed If no character is being transmitted when the transmitter is disabled the transmitter will stop at the next rising edge of the internal shift clock 7 7 MC68HC901 USER S MANUAL MOTOROLA Universal Synchronous Asynchronous Receiver Transmitter In the asynchronous character format the transmitter can be programmed to send a break The break will be transmitted once the word currently in the shift register has been sent If the shift register is empty the break command will be effective immediately A transmit error interrupt will be generated at every normal character boundary to aid in timing the break transmission The contents of the TSR are not affected however The break will continue until the break bit is cleared The underrun error UE must be cleared from the TSR Also the interrupt pending regi
77. t higher priority MFPs When the daisy chain interrupt structure is not implemented the IEls of all MFPs must be tied low and the IEOs left unconnected Refer to Section 4 2 Daisy Chaining MFPs for additional information When the processor initiates an interrupt acknowledge cycle by driving and DS the MFP whose is low may respond with a vector number if an interrupt is pending If this device does not have a pending interrupt is asserted which allows the next lower priority device to respond to the interrupt acknowledge When an MFP propagates IEO it will not drive the data bus nor DTACK during the interrupt acknowledge cycle The timing for an IACK cycle is shown in Figure 3 3 Refer to Section 8 7 AC Electrical Characteristics and Figures 7 7 and 7 8 for further information Figure 3 3 IACK Cycle Timing Diagram 3 3 RESET OPERATION The reset operation will initialize the MFP to a known state The reset operation requires that the RESET input be asserted for a minimum of two microseconds During a device reset condition all internal MFP registers are cleared except for the timer data registers TADR TBDR TCDR and TDDR the USART data register UDR and the transmitter status register TSR timers are stopped the USART receiver and transmitter are disabled and the serial output SO line is placed in high impedance The interrupt channels are also disabled and any pending interrupts are cle
78. t structure will prohibit nesting the interrupts at the same interrupt level However additional interrupt requests from the MFP can be recognized before a previous channel s interrupt service routine is finished by lowering the processor s interrupt mask to the next lower interrupt level within the interrupt handler When nesting MFP interrupts it may be desirable to permit interrupts on any MFP channel regardless of its priority to pre empt or delay interrupt processing of an earlier channel s interrupt service request Or it may be desirable to only allow subsequent higher priority channel interrupt requests to supercede previously recognized lower priority interrupt requests The MFP interrupt structure provides the flexibility by offering two end of interrupt options for vectored interrupt schemes The end of interrupt modes are not active in a polled interrupt scheme 4 4 1 Selecting the End Of Interrupt Mode In a vectored interrupt scheme the MFP may be programmed to operate in either the automatic end of interrupt mode or the software end of interrupt mode The mode is selected by writing the S bit of the vector register When the S bit is programmed to a one 4 11 MC68HC901 USER S MANUAL MOTOROLA Interrupt Structure the MFP is placed in the software end of interrupt mode and when the S bit is a zero all channels operate in the automatic end of interrupt mode 4 4 2 Automatic End Of Interrupt Mode When an interrupt vecto
79. the next lower priority device Thus priority is passed down the chain via IEI and IEO until a part which has a pending interrupt is reached The part with the pending interrupt passes a vector number to the processor and does not propagate IEO HIGHEST LOWEST PRIORITY PRIORITY MC68HC901 MC68HC901 MC68HC901 IEO IE IEO IEl Figure 4 1 Daisy Chained Interrupt Structure MOTOROLA MC68HC901 USER S MANUAL 4 3 Interrupt Structure 4 3 INTERRUPT CONTROL REGISTERS MFP interrupt processing is managed by the enable registers A and B interrupt pending registers A and B and interrupt mask registers A and B These registers allow the programmer to enable or disable individual interrupt channels mask individual interrupt channels and access pending interrupt status information In service registers A and B allow interrupts to be nested as described in Section 4 4 Nesting MFP Interrupts The interrupt control registers are shown in the following paragraphs 4 3 1 Interrupt Enable Registers IERA IERB The interrupt channels are individually enabled or disabled by writing a one or a zero respectively to the appropriate bit of interrupt enable register A or B IERA or IERB The processor may read these registers at any time When a channel is enabled interrupts received on the channel will be recognized by the MFP and IRQ will be asserted to the processor indicating that interrupt service is required On
80. the other hand a disabled channel is completely inactive interrupts received on the channel are ignored by the MFP Writing a zero to a bit of interrupt enable register A or B will cause the corresponding bit of the interrupt pending register to be cleared This will terminate all interrupt service requests for the channel and also negate IRQ unless interrupts are pending from other sources Disabling a channel however does not affect the corresponding bit in interrupt in service registers A or B So if the MFP is in the software end of interrupt mode refer to Section 4 4 3 Software End Of Interrupt Mode and an interrupt is in service when a channel is disabled the in service bit of that channel will remain set until cleared by software IERA REGISTER BIT 7 6 5 4 3 2 1 0 RCV XMIT FIELD GPIP7 GPIP6 TIMERA BUFFER ERROR TIMER B FULL EMPTY RESET 0 0 0 0 0 0 0 0 ADDR 07 GPIP7 GPIP6 General Purpose Interrupt Enable 1 Enable 0 Disable Timer A Timer A Interrupt Enable 1 Enable 0 Disable Receiver Buffer Full Receiver Buffer Full Interrupt Enable 1 Enable 0 Disable 4 4 MC68HC901 USER S MANUAL MOTOROLA Interrupt Structure Receiver Error Receiver Buffer Full Interrupt Enable 1 Enable 0 Disable Transmitter Buffer Empty Transmitter Buffer Interrupt Enable 1 Enable 0 Disable Transmitter Error Transmitter Error
81. tware end of interrupt mode and in service register bits enabled 0 Automatic end of interrupt mode and in service register bits forced low Bits 2 0 Unused Unused bits read as zero 4 2 DAISY CHAINING MFPs As an interrupt controller the MFP will support eight external interrupt sources in addition to its eight internal interrupt sources When a system requires more than eight external interrupt sources to be placed at the same interrupt level sources may be added to the prioritized structure by daisy chaining MFPs Interrupt sources are prioritized internally within each MFP and the MFPs are prioritized by their position in the chain Unique vector numbers are provided for each interrupt source The IEI and IEO signals implement the daisy chained structure The IEI of the highest priority MFP is tied low and the IEO output of this device is tied to the next highest priority IEI The IEI and signals are daisy chained in this manner for all the MFPs in the chain with the lowest priority MFP IEO left unconnected Figure 4 1 shows a diagram of the interrupt daisy chain Daisy chaining requires that all parts in the chain have a common IACK When the common is asserted during an interrupt acknowledge cycle all parts will prioritize interrupts in parallel When the IEI signal to an is asserted the part may respond to the cycle if it requires interrupt service Otherwise the part will assert to
82. ur bus Worthington OHIO Da OKLAHO in Tulsa OREGON Portland PENNSYLVANIA Colmar Philadelphia Horsham TENNESSEE Knoxville TEXAS Austin TEXAS Houston TEXAS Plano VIRGINIA Richmond WASH INGTON Bellevue Seattle Acc WISCONSIN Milwaukee Brookfield CANADA BRITISH COLUMBIA Vancouver ONTARIO Toronto ONTARIO Ottawa QUEBEC Montreal INTERNATIONAL AUSTRALIA Melbourne AUSTRALIA Sydney BRAZIL Sao Paulo CHINA Beijing FINLAND Helsinki Car Phone FRANCE Paris Vanves 205 464 6800 602 897 5056 818 706 1929 310 417 8848 714 753 7360 916 922 7152 408 749 0510 719 599 7497 303 337 3434 203 949 4100 407 628 2636 305 486 9776 813 538 7750 404 729 7100 208 323 9413 708 490 9500 9 317 571 0400 CO C2 CO SBS OSB SO O gt O gt N GO 4 00 m En 614 431 8492 3 800 544 9496 503 641 3681 215 997 1020 215 957 4100 615 584 4841 512 873 2000 800 343 2692 214 516 5100 804 285 2100 604 293 7605 416 497 8181 613 226 3491 514 731 6881 61 3 6 1 2 906 3855 55 11 815 4200 86 505 2180 358 0 35161191 358 49 211501 33 1 40 955 900 GERMANY Langenhagen Hanover GERMANY Munich GERMANY Nuremberg GERMANY Sindelfingen GERMANY Wiesbaden HONG KONG Kwai Fong Tai Po INDIA Bangalore ISRAEL Tel Aviv ITALY Milan JAPAN Aizu JAPAN Atsugi JAPAN Kumagaya JAPAN Kyushu
83. ynchronous word length is the character length plus one The MFP will compute and append the parity bit for the synchronous character 7 2 MC68HC901 USER S MANUAL MOTOROLA Universal Synchronous Asynchronous Receiver Transmitter 7 1 3 USART Control Register UCR This register selects the clock mode and the character format for the receive and transmit sections UCR REGISTER BIT 7 6 5 4 3 2 1 0 FIELD CLK CL1 CLO ST1 STO PE E O RESET 0 0 0 0 0 0 0 U ADDR 29 CLK Clock Mode 1 Dataclocked into and out of receiver and transmitter at one sixteenth the frequency of their respective clocks 0 Data clocked into and out of receiver and transmitter at the frequency of their respective clocks CL1 CLO Character Length These bits specify the length of the character exclusive of start bits and parity 0 0 8 Bits 0 1 7 Bits 1 0 6 Bits 1 1 5 Bits ST1 STO Start Stop Bit and Format Control These bits select the number of start and stop bits and specify the character format Synchronous Asynchronous Asynchronous See note Asynchronous NOTE Used with divide by 16 mode only MOTOROLA MC68HC901 USER S MANUAL 7 3 Universal Synchronous Asynchronous Receiver Transmitter PE Parity Enable 1 Parity checked by receiver and parity calculated and inserted during data transmission 0 No parity check and no parity bit computed for tra
84. zation 4 1 Interrupt Control Registers 4 4 Interrupt Control Signals 2 3 Interrupt Enable Registers IERA IERB 4 4 Interrupt In Service Registers ISRA ISRB 4 10 Interrupt Mask Registers IMRA 4 8 Interrupt Pending Registers IPRA IPRB 4 6 Interrupt Processing 4 1 Interrupt Registers Interrupt Enable Register A loqui 4 4 Interrupt Enable Register B IERB ir rt 4 5 Interrupt Mask Register A IMRA 4 8 Interrupt Mask Register B IMRB 4 9 Interrupt Pending Register IPRA 4 6 Interrupt Pending Register PRB 4 7 Interrupt Service Register A ISRA 4 10 Interrupt Service Register B etia u ratore 4 11 INDEX 2 MC68HC901 USER S MANUAL Vector Register VR 4 2 Interrupt Structure 4 1 Interrupt Timing 8 10 Interrupt Vector Number 4 1 Introduction 1 1 IPRA register 4 6 IPRB register 4 7 ISRA register 4 10 I

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