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1. UART IO_INTERFACE IO_IF RS232_Uart_1 IO_TYPE xilinx com bsb_lib rtl_busdefs uart 1 0 PORT RS232_Uart_l_sout DIR O IQ_IF RS232_Uart_1 IO_IS sout PORT RS232_Uart_l_sin DIR I IO_IF RS232_Uart_1 IO_IS sin GPIO IO_INTERFACE IO_IF DIP_Switches_8Bits IO_TYPE xilinx com bsb_lib rtl_busdefs gpio 1 0 PARAMETER DIP_Switches_8Bits_GPIO_WIDTH_ID 8 DT STRING ASSIGNMENT CONSTANT IO_IF DIP_Switches_8Bits IO_IS C_GPIO_WIDTH PARAMETER DIP_Switches_4Bits_ALL_INPUTS_ID 1 DT STRING ASSIGNMENT CONSTANT IO_IF DIP_Switches_8Bits IO_IS C_ALL_INPUTS PARAMETER DIP_Switches_4Bits_IS_DUAL_ID 0 DT STRING IO_IF DIP_Switches_4Bits IO_IS C_IS_DUAL PORT DIP_Switches_8Bits_TRI_T DIR I VEC 7 0 IO_IF DIP_Switches_8Bits IO_IS TRI_I DDR2 SDRAM IO_INTERFACE IO_IF MCB_DDR2 IO_TYPE xilinx com bsb_lib rtl_busdefs ddr2_sdram 1 0 PARAMETER C_MEM_ PARTNO_ID EDE1116AXXX 8E DT STRING ASSIGNMENT CONSTANT IO_IF MCB_DDR2 IO_IS C_MEM_PARTNO PARAMETER C_BYPASS_CORE_UCF_ID 0 DT STRING ASSIGNMENT CONSTANT IO_IF MCB_DDR2 IO_IS C_BYPASS_CORE_UCF PARAMETER C_MEM_TRAS_ID 45000 DT STRING ASSIGNMENT CONSTANT IO_
2. Tips for Writing or Customizing Linker Scripts The following points must be kept in mind when writing or customizing your own linker script e Ensure that the different vector sections are assigned to the appropriate memories as defined by the MicroBlaze hardware e Allocate space in the bss section for stack and heap Set the _stack variable to the location after _STACK_SIZE locations of this area and the _heap_start variable to the next location after the _STACK_SIZE location Because the stack and heap need not be initialized for hardware as well as simulation define the _bss_end variable after the bss and COMMON definitions Note however that the bss section boundary does not include either stack or heap Embedded System Tools Reference Manual www xilinx com 107 UG111 July 6 2011 Chapter 9 GNU Compiler Tools XILINX e Ensure that the variables SDATA_START__ _SDATA_END__ SDATA2_ START _SDATA2_ END __ _SBSS2_START__ _SBSS2_END__ _bss_start _bss_end _sbss_start and _sbss_end are defined to the beginning and end of the sections sdata sdata2 sbss2 bss and sbss respectively e ANSIC requires that all uninitialized memory be initialized to startup not required for stack and heap The standard CRT that is provided assumes a single bss section that is initialized to zero If there are multiple bss sections this CRT will not work You should write your own CRT that initializes all the
3. Buslf f gt _MASTERS Buslf gt _IS_ACLK ASYNC Buslf gt _ACLK_ RATIO Bus I f gt _SECURI GA Buslf gt _AW_REGISTER Buslf gt _AR_ REGISTER Embedded System Tools Reference Manual UG111 July 06 2011 www xilinx com 255 Appendix D Interconnect Settings and Parameter Automations for AXI Designs XILINX TERCONNECT_ lt BusIlf gt _W_REGISTER TERCONNECT_ lt BusIf gt _R_ REGISTER TERCONNECT_ lt BusIf gt _B REGISTER TERCONNECT_ lt BusIf gt _WRITE_FIFO_DEPTH TERCONNECT_ lt BusIf gt _READ_FIFO_DEPTH TERCONNECT_ lt BusIf gt _WRITE_ACCEPTANCE 2 2 2 2 222 e C_INTERCONNECT_ lt BusIf gt _READ_ACCEPTANCE These parameters are e NON_HDL parameters meaning that they do not affect the behavior of the end point IP e Not present in the MPD of the IPs However XPS tools allow these parameters to be specified as parameters in the MHS instances of the peripherals connected to the AXI Interconnect end point IPs in the MHS file In the context of the system as a whole the AXI Interconnect needs to know about certain properties of the IP interfaces to which that are connected It is simpler to capture these values on the end point IPs The main advantages to this approach are e
4. 0 0 00 cece teen eens Additional Resources 0 00 ccc ccc teen eee eens Chapter 12 Bitstream Initializer BitInit Oyervi eW 600g ato Shteegatkse eee athe eee etd ace ee ae SE Tool Usage i o i2i0k ire vexietor tier aneri eked anre eA e Tool OPHONS eiio eaei haiie Ee EE E EE AR KR aa ENE Ea ESS Chapter 13 System ACE File Generator GenACE ASSUMPUONS ee e aa E e E E a E N T EEE EEY Tool Requirements 0 00 00 0 cece cence ee GenACkE Featutes o iccvrccnteerartgeateoduegesnted kerane pi akaa a GenACE Model ccrerceri diries ridar TE eE EEE EIT RS The Genace tcl Script icsiiisicieei cis ceri twenie bene bee eee en hee Generating ACE Piles epre nsp iea e t n p gees Related Information n u usssauunesanu rrr nnrr rran r arrn Chapter 14 Flash Memory Programming OVEIVICW crceseierirtesr eian eiie tiaia EENE Ap E E EE EERE DERGE Supported Flash Hardware 155 5icgi0 ieyidinhdviavinse nie siedokee exe Flash Programmer Performance 00 00 e cece eee eee Customizing Flash Programming 00 0000 eee Chapter 15 Version Management Tools revup OCVOEVICW 8 sire 6b Hirer Nae a eect it ae be ecw Sia eee oe wR aS Embedded System Tools Reference Manual www xilinx com UG111 EDK v 13 2 July 6 2011 XILINX Format Revision Tool Backup and Update Processes 197 Command Line Option for the Format Revision Tool 200 The Vers
5. Appendix C EDK Tel Interface XILINX xadd_hw_ipinst lt mhs_handle gt lt inst_name gt lt ip_name gt lt hw_ver gt Description Adds a new MHS instance to the MHS specified by lt mhs_hand1e gt Returns a handle to the newly created instance if successful and NULL otherwise Arguments lt mhs_hand1e gt is the handle to the MHS in which this mhs instance has to be added lt inst_name gt is the instance name of the IP instance that needs to be added lt ip_name gt is the name of the IP that needs to be added lt hw_ver gt is the version of the IP that needs to be added Example Add a MicroBlaze v7 00 a IP with the instance name mblaze to the MHS xadd_hw_ipinst mhs_handle mblaze microblaze 7 00 a xadd_hw_ipinst_port lt ipinst_handle gt lt port_name gt lt connector_name gt Description Creates and adds a port specified by lt port_name gt and lt connector_name gt to the IP instance specified by the lt ipinst_handle gt This API returns a handle to the newly created port if successful and NULL otherwise Arguments lt inst_hand1e gt is the handle to the IP instance to which the port has to be added lt port_name gt is the name of the port lt connector_name gt is the name of the connector Example Add a clock port on a MicroBlaze instance and connect it to the sys_c1lk_s signal xadd_hw_ipinst_port mb_handle Clk sys_clk_s xadd_hw_ipinst_parameter lt ipinst_handle gt lt param_name gt l
6. RTL Core Generator System Generator Create Identify a Workspace Automatic Export to SDK xml file only Create a New Project Board Support Package 1 Synthesis 2 Translate 3 MAP 4 PAR 5 Timing 6 Bitstream Generation 7 Data2MEM Implementation to Bitstream Application Development elf Netlist Generation with Platgen Download to FPGA Debug Export to SDK xml bit bmm files Board X10254 Figure 1 1 Embedded Design Process Flow Hardware Development Xilinx FPGA technology allows you to customize the hardware logic in your processor subsystem Such customization is not possible using standard off the shelf microprocessor or controller chips The term Hardware platform describes the flexible embedded processing subsystem you are creating with Xilinx technology for your application needs The hardware platform consists of one or more processors and peripherals connected to the processor buses XPS captures the hardware platform description in the Microprocessor Hardware Specification MHS file The MHS file is the principal source file that maintains the hardware platform description and represents in ASCII text the hardware components of your embedded system When the hardware platform description is complete the hardware platform can be exp
7. The following text displays Loading section text Loading section rodata Loading section data Loading section fixup Loading section got2 Loading section sdata Loading section boot0 Loading section boot Start address Oxfffffffc Transfer rate 41344 bits sec gdb c Continuing size Oxfcc lma Oxfff 8000 size 0x118 lma O0Oxffff8fd0 size 0x2f8 lma O0Oxffff90e8 size 0x14 lma Oxfff 93e0 size 0x20 lma Oxffff93f4 size 0xc lma Oxffff9414 size 0x10 lma Oxffffa430 size 0x4 lma Oxfffffffc load size 5168 323 bytes write For the console mode these two commands can also be placed in the GDB startup file gdb ini in the current working directory 172 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX GDB Command Reference GDB Command Reference For help on using mb gdb select Help gt Help Topics in the XPS main dialog box or type help in the console mode To open a console window from the GBD main dialog box select View gt Console For comprehensive online documentation on using GDB refer to the GNU web site For information about the mb gdb Insight GUI refer to the Red Hat Insight webpage Links to these documents are provided in the Additional Resources page 173 Table 11 1 describes the commonly used mb gdb console commands The equivalent GUI versions can be identified in the mb gdb GUI window icons Some of the commands such as info target and
8. 2 Using the merged_mhs_hand_le get a list of all IPs Iterate over this list and for each IP get the value of the OPTION IPTYPE and compare it with the given IP type The following code snippet illustrates how to get the IPTYPE of specific IPs Procedure to get a list of IPs of a particular IPTYPE proc xget_ipinst_handle_list_for_iptype merged_mhs_handle iptype Get a list of all IPs set ipinst_list xget_hw_ipinst_handle merged_mhs_handle set ret_list foreach ipinst Sipinst_list Get the value of the IPTYPE Option set curiptype xget_hw_option_value Sipinst IPTYPE i1 curiptype matches the given iptype then add it to the list that this proc returns if string compare nocase S curiptype Siptype O f lappend ret_list Sipinst return S ret_list www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 g XILINX Tcl Example Procedures Example 2 The following procedure explains how to get the list of cores that are memory controllers in a design Memory controller cores have the tag ADDR_TYPE MEMORY in their address parameter Procedure to get a list of memory controllers in a design proc xget_hw_memory_controller_handles merged_mhs set ret_list Gets all MhsInsts in the system set mhsinsts xget_hw_ipinst_handle S merged_mhs Loop through each MhsInst and determine if it has ADDR_TYPE MEMO
9. 2 Modify pg crtinit s to remove the following lines brlid r15 __init Invoke language initialization functions nop and brlid r15 _ fini Invoke language cleanup functions nop This avoids referencing the extra code usually pulled in for constructor and destructor handling reducing code size 3 Compile these files into o files and place them in a directory of your choice or include them as a part of your application sources 4 Add the nostartfiles switch to the compiler Add the B directory switch if you have chosen to assemble the files in a particular folder 5 Compile your application If your application is executing in a different mode then you must pick the appropriate CRT files based on the description in Startup Files page 108 Embedded System Tools Reference Manual www xilinx com 111 UG111 July 6 2011 112 Chapter 9 GNU Compiler Tools XILINX Compiler Libraries The mb gcc compiler requires the GNU C standard library and the GNU math library Precompiled versions of these libraries are shipped with EDK The CPU driver for MicroBlaze copies over the correct version based on the hardware configuration of MicroBlaze during the execution of Libgen To manually select the library version that you would like to use look in the following folder XILINX_EDK gnu microblaze lt platform gt microblaze xilinx elf lib The filenames are encoded based on the compiler flags and co
10. Embedded System Tools Reference Manual www xilinx com 99 UG111 July 6 2011 100 Chapter 9 GNU Compiler Tools XILINX mno x1 soft mul This option permits use of hardware multiply instructions for 32 bit multiplications The MicroBlaze processor has an option to turn the use of hardware multiplier resources on or off This option should be used when the hardware multiplier option is enabled on MicroBlaze Using the hardware multiplier can improve the performance of your application The compiler automatically defines the C pre processor definition HAVE_HwW_MUL when this switch is used This allows you to write C or assembly code tailored to the hardware based on whether this feature is specified as available or not Refer to the MicroBlaze Processor Reference Guide for more details about the usage of the multiplier option in MicroBlaze A link to the document is provided in Additional Resources page 122 mxl multiply high MicroBlaze has an option to enable instructions that can compute the higher 32 bits of a 32x32 bit multiplication This option tells the compiler to use these multiply high instructions The compiler automatically defines the C pre processor definition HAVE_HW_MUL_HIGH when this switch is used This allows you to write C or assembly code tailored to the hardware based on whether this feature is available or not Refer to the MicroBlaze Processor Reference Guide for more details about the usage of the multiply high
11. Option Description ppc Connects to PowerPC processor mb Connects to MicroBlaze processor mdm Connects to MDM peripheral lt Connection_Type gt Connection method target dependent Options Connection options The following sections describe connect options for different targets 140 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Connect Command Options PowerPC Processor Targets Xilinx Virtex series devices can contain one or two PowerPC 405 and 440 processor cores XMD can connect to these PowerPC processor targets over a JTAG connection on the board XMD also communicates over a TCP socket interface to an IBM PowerPC 405 Processor Instruction Set Simulator ISS Use the connect ppc command to connect to the PowerPC processor target and start a remote GDB server When XMD is connected to the PowerPC processor target powerpc eabi gdb or SDK can connect to the processor target through XMD and debugging can proceed Note XMD does not support Virtual Addressing Debugging is only supported for Programs running in Real Mode PowerPC Processor Hardware Connection When connecting to a PowerPC processor hardware target XMD detects the JTAG chain automatically and the PowerPC processor type and processors in the system and connects to the first processor You can override or provide information using the following options Usage connect ppc hw cable lt JTAG Cable options gt
12. The psf2Edward is a command line program that converts a Xilinx Embedded Development Kit EDK project into Edward an internal XML format for use in external programs such as the Software Development Kit SDK The DTD for the Edward Format can be found in lt EDK installation directory gt data xml DTD Xilinx Edward Program Usage You can use Psf2Edward to e Convert PSF project to XML format To do this use the following command psf2Edward inp lt psf input source gt xml lt xml output file gt lt options gt e Synchronize an existing XML file with a PSF project psf2Edward inp lt psf input source gt sync lt XML file to sync gt lt options gt Program Options Psf2Edward has the following options Option inp Description Input PSF source This can be either a Microprocessor Hardware Specification MHS file or a Xilinx Microprocessor Project XMP file xml Output XML file sync Input sync XML file This outputs to the same file Part Name This must be used if the PSF source is an MHS file edwver Set schema version of Edward to write For example 1 1 and 1 2 dont_run_checkhwsys Do not run full set of system drc checks exit_on_error Exit on first dre error By default non fatal errors are ignored Embedded System Tools Reference Manual UG111 July 6 2011 www xilinx com 39 Chapter 3 Psf2Edward Program 40 www xili
13. This chapter describes the GNU compiler tools Overview EDK includes the GNU compiler collection GCC for both the PowerPC 405 and 440 processors and the MicroBlaze processor e The EDK GNU tools support both the C and C languages e The MicroBlaze GNU tools include mb gcc and mb g compilers mb as assembler and mb 1d_ linker e The PowerPC processor tools include powerpc eabi gcc and powerpc eabi g compilers powerpc eabi as assembler and the powerpc eabi 1d linker e The toolchains also include the C Math GCC and C standard libraries The compiler also uses the common binary utilities referred to as binutils such as an assembler a linker and object dump The PowerPC and MicroBlaze compiler tools use the GNU binutils based on GNU version 2 16 of the sources The concepts options usage and exceptions to language and library support are described Appendix A GNU Utilities Embedded System Tools Reference Manual www xilinx com 83 UG111 July 6 2011 Chapter 9 GNU Compiler Tools XILINX Compiler Framework This section discusses the common features of both the MicroBlaze and PowerPC processor compilers Figure 9 1 displays the GNU tool flow Input C C Files as mb as or powerpc eabi as Libraries 5 mb Id or powerpc eabi ld Output ELF File UG111_05_101905 Figure 9 1 GNU Tool Flow 84 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g
14. configdevice lt JTAG chain options gt debugdevice lt PowerPC options gt JTAG Cable Options The options listed in Table 10 8 let you specify the Xilinx JTAG cable used to connect to a target Table 10 8 JTAG Cable Options Option esn lt USB cable ESN gt Specify the Electronic Serial Number ESN of the USB cable connected to the host Description machine Use this option to uniquely identify a USB cable when multiple cables are connected to the host machine To read the ESN of the USB cable connect the cable and use the xrcableesn command fname lt filename svf gt Filename for creating the Serial Vector Format SVF file frequency lt cable speed in Hz gt Specify the cable clock speed in Hertz Valid Cables speeds are e For Parallel 4 5000000 default 2500000 200000 e For Platform USB 24000000 12000000 6000000 default 3000000 1500000 750000 port lt port name gt Specify the port Valid arguments for port are Ipt1 lpt2 usb21 usb22 type lt cable_type gt Specify the cable type Valid cable types are e xilinx_parallel3 e xilinx_parallel4 e xilinx_platformusb e xilinx_svffile In the case of xilinx_svffile the JTAG commands are written into a file specified by the fname option Embedded System Tools Reference Manual www xilinx com 141 UG111 July 6 2011 Chapter 10 Xilinx Microprocessor Debugger XMD XILINX JTAG C
15. configdevice devicenr 2 idcode 0x22a96093 irlength 10 partname xc5v1lx50t configdevice devicenr 3 idcode 0x22a96093 irlength 10 partname xc5v1lx50t debugdevice devicenr 1 cpunr 1 target mdm elf executablel elf This generates the SVF file fpga1_sw svf 3 Generate an SVF file for the software on the second FPGA device The options file contains the following jprog ace fpga2_sw ace board user configdevice devicenr 1 idcode 0x22a96093 irlength 10 partname xc5v1lx50t configdevice devicenr 2 idcode 0x22a96093 irlength 10 partname xc5v1lx50t configdevice devicenr 3 idcode 0x22a96093 irlength 10 partname xc5v1lx50t debugdevice devicenr 2 cpunr 1 target mdm elf executable2 elf This generates the SVF file fpga2_sw svf 186 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Related Information 4 Generate an SVF file for the software on the third FPGA device The options file contains the following jprog ace fpga3_sw ace board user configdevice devicenr 1 idcode 0x22a96093 irlength 10 partname xc5vlx50t configdevice devicenr 2 idcode 0x22a96093 irlength 10 partname xc5v1x50t configdevice devicenr 3 idcode 0x22a96093 irlength 10 partname xc5v1x50t debugdevice devicenr 3 cpunr 1 target mdm elf executable3 elf This generates the SVF file fpga3_sw svf 5 Concatenate the files in the following order config0 svf fpgal_sw svf fpga2
16. isim none Where mgm Mentor Graphics ModelSim questa Mentor Graphics QuestaSim ies Cadence Incisive Enterprise Simulator IES isim ISE Simulator ISIM Specify the path to the Xilinx and EDK precompiled libraries using the following commands XPS xset sim x lib lt path gt XPS xset sim_edk_lib lt path gt Select the Simulation Model using the following command XPS xset sim model behavioral structural timing Enable or disable external memory simulation using following command xset external_mem sim 0 1 Optionally before setting external memory simulation flag you might need to check if a DDRx memory controller for Virtex 6 is present in the system Use the following command xget is _external_mem_present Check for more detail in External Memory Simulation page 72 To generate the simulation model type XPS run simmodel When the process finishes HDL models are saved in the simulation directory To open the simulator type XPS run sim At the prompt run Simgen with the MHS file and appropriate options as inputs Requirements simgen lt system_name gt mhs options Verify that your system is properly configured to run the Xilinx ISE tools Consult the release notes and installation notes that came with your software package for more information 66 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Simgen Syntax Optio
17. r13 SDA_BASE SDA_BASE is the read write small data anchor address Other Undefined Other registers do not have defined values registers The following subsection describes the initialization files This information is for advanced users who want to change or understand the startup code of their application Initialization File Description The PowerPC processor compiler uses four different CRT files xil crt0 o xil pgert0 o xil sim crt0 o and xil sim pgcrt0 o The various CRT files perform the following steps with exceptions as described 1 Invoke the function _cpu_init This function is provided by the board support package library and contains processor architecture specific initialization 2 Clear the bss memory regions to zero 3 Set up registers Refer to Table 9 12 for details 4 Initialize the timer base register to zero 5 Optionally enable the floating point unit bit in the MSR 6 Invoke the C language and constructor initialization function _init 7 Invoke main 8 Invoke C language destructors _fini 9 Transfer control to exit 118 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX PowerPC Compiler Usage and Options Start up File Descriptions xil crt0 o This is the default initialization file used for programs that are to be executed in standalone mode with no other special requirements This performs all the common actions described above xil pgcrt0 o Th
18. read addr f 8031 be 0100_0000 read addr f 8032 be 0010_0000 read addr f 8033 be 0001_0000 58 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Using the Platform Studio BFM Package read addr ffff 8034 be 0000_1000 read addr fff f 8035 be 0000_0100 read addr fff 8036 be 0000_0010 read addr fff f 8037 be 0000_0001 Write and read a 16 word line mem_update addr ffff8080 data 01010101_01010101 mem_update addr ffff8088 data 02020202_ 02020202 mem_update addr ffff 8090 data 03030303_03030303 mem_update addr ffff8098 data 04040404_ 04040404 mem_update addr ffff80a0 data 05050505_05050505 mem_update addr ffff80b0 data 07070707_07070707 mem_update addr ffff80b8 data 08080808_08080808 write addr fff 8080 size 0011 be 1111_1111 read addr fff 8080 size 0011 be 1111_1111 More information about the PLB Bus Functional Language is in the PlbToolkit pdf document in the X mem_update addr ffff80a8 data 06060606_06060606 L NX_EDK third_party doc directory Bus Functional Compiler Usage Running BFM Simulations The Bus Functional Compiler provided in the CoreConnect toolkit is a Perl script called BFC The script uses a bfcrc configuration file that specifies to the script which simulator is used and the paths to the BFMs Xilinx EDK includes a helper executable called xilbfc that ena
19. specified it is used jprog false Clear the existing FPGA configuration Do not specify this option if performing runtime configuration start_address Start Address Specify the address at which to start processor lt processor run address gt of the last ELF execution This is useful when a data file is being file if ELF file loaded and processor should execute from load is specified address else none target lt target type gt ppc_hw Target to use in the system for downloading ELF Data file Target types are ppc_hw to connect to a PowerPC 405 or 440 processor system mdm to connect to a MicroBlaze system This assumes the presence of mdm in the system Usage xmd tcl genace tcl jprog target mdm hw lt implementation download bit gt elf executablel elf executable2 svf data image bin O0xfe000000 board m1507 ace system ace Preferred genace opt file jprog hw implementation download bit ace system ace board m1507 target mdm elf executablel elf executable2 svf data image bin 0xfe000000 Embedded System Tools Reference Manual www xilinx com 181 UG111 July 6 2011 Chapter 13 System ACE File Generator GenACE XILINX Supported Target Boards in Genace tcl Script Table 13 3 lists the boards supported in the genace tcl script Table 13 3 Supported Target Boards Board name Board type Devices in the JTAG Chain ML401
20. 2 Issue reset signal system reset or processor reset The processor starts running 3 After processor is stopped at reset location remove the breakpoint www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX XMD User Commands Recommended XMD Flows The following are the recommended steps in XMD for debugging a program and debugging programs in a multi processor environment and running a program ina debug session Debugging a Program To debug a program 1 a a i ONO Connect to the processor Download the ELF file Set the required breakpoints and watchpoints Start the processor execution using the con command or step through the program using the stp command Use the state command to check the processor status Use stop command to stop the processor if needed When the processor is stopped read and write registers and memory To re run the program use the run command Debugging Programs in a Multi Processor Environment For debugging programs in a multi processor environment 1 Connect to processor 2 Use the debugconfig command to configure the reset behavior which depends on your system architecture Refer to the Configure Debug Session on page 160 3 Download the ELF file Set the required breakpoints and watchpoints 5 Start the processor execution using the con command or step through the program using the stp command Connect to processor2 Use the
21. 8 When the programming is done the flash programmer Tcl sends an exit command to the flash programmer and terminates the XMD session The following is an example set of steps to perform for a custom flow XPS stores the flash settings and temporary files in the hardware platform project directory If multiple hardware projects exist in the workspace the flash programmer dialog box prompts you to select the hardware platform In the following procedure lt XPS project gt refers to this hardware platform project 1 Create a new subdirectory called tmp under the lt xPS project gt directory Note f this folder already exists skip this step 2 Copy flashwriter tcl from lt edk_install1 gt data xmd flashwriter tcl to your lt XPS project gt tmp directory 3 Create a sw_services directory within your project Copy the lt edk_instal1 gt data xmd flashwriter directory to the sw_services directory 5 Change the following line in the flashwriter tcl file copy set flashwriter_sre file join xilinx_edk data xmd flashwriter sro to set flashwriter_srce file join sw_services flashwriter src From this point when you use the Program Flash Memory dialog box in XPS the flash programming tools use the script and the sources you copied into the sw_services directory You can customize these as required If you prefer to not have the GUI overwrite the lt xPS project gt settings flash tcl file run th
22. Data Structure Creation EDK tools provide access to two basic types of run time information e The original design and library datafile data structure The original data structure provides access only to the information present in various data files You can get a handle to such files as the MHS MPD MDD and MLD These handles allow you to query the contents of the files with which they are associated e The merged data structure When EDK tools run the information in the design files MHS is combined with the corresponding information from library files MPD to create merged data structures hardware merged datastructure also referred to as the hardware merged object During the process of creating the merged data structure the tools also analyze various design characteristics such as connectivity or address mapping and that information is also stored in the merged data structures A merged data structure provides an easy way to access this analyzed information For example an instance of an IP in the MHS file is merged with its corresponding MPD Using the merged instances complete information can be obtained from one handle it is not necessary to access the IP instance and MPD handles separately Figure C 1 shows a marged hardware data structure creation MHS c Merged DataStructure X10582 Figure C 1 Merged Hardware Data Structure Creation 230 www xilinx com Embedded System Tools Reference Manual UG111 July
23. Device Control Register Bus DCR V2 9 for differences in the DCR bus IBM CoreConnect Toolkit The IBM CoreConnect Toolkit is a collection of toolkits Each toolkit includes a collection of HDL files that represents predefined systems including a bus bus masters bus slaves and bus monitors You can modify the predefined systems included in the toolkits manually to connect the hardware components you want to test This is a labor intensive process because you must describe all the connections to the bus and ensure there are no errors in setting up the test environment Refer to the CoreConnect Toolkit documentation for more information on how to verify your hardware module Platform Studio BFM Package The Platform Studio BFM package includes a set of CoreConnect BFMs the Bus Functional Compiler and CoreConnect documents tailored for use within Platform Studio The BFM package lets you specify bus connections from a high level description such as an MHS file By allowing the Platform Studio tools to write the HDL files that describe the connections the time and effort required to set up the test environment are reduced www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Getting and Installing the Platform Studio BFM Package AXI BFM Package The AXI BFM solution was created for Xilinx by Cadence Design Systems AXI BFMs enable Xilinx customers to verify and simulate communication with AX
24. Initialization File Search Procedures The compilers search initialization files in the following order 1 2 92 Directories are passed to the compiler with the B lt dir_name gt option The compilers search XILINX_EDK gnu processor platform processor lib 1lib The compilers search the following libraries a SXILINX_EDK gnu lt processor gt platform lt processor lib gt lib b SXILINX_EDK 1ib processor Where e lt processor gt is powerpc eabi for PowerPC processors and microblaze for MicroBlaze processors e lt processor lib gt is powerpc eabi for PowerPC processors and microblaze xilinx elf for MicroBlaze processors Note plat form indicates lin for Linux lin64 for Linux 64 bit and nt for Windows Cygwin www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Common Compiler Usage and Options Linker Options defsym STACK SIZE value The total memory allocated for the stack can be modified using this linker option The variable _STACK_SIZEis the total space allocated for the stack The _STACK_SIZE variable is given the default value of 100 words or 400 bytes If your program is expected to need more than 400 bytes for stack and heap combined it is recommended that you increase the value of _STACK_SIZE using this option The value is in bytes In certain cases a program might need a bigger stack If the stack size required by the program
25. To have the PsfUtility infer this information automatically all specified conventions must be followed for reserved generics as well This can help prevent errors when your peripheral requires information on the platform that is generated Reserved Generic Names Table 2 3 lists the reserved generic names Table 2 3 Automatically Expanded Reserved Generics Parameter Description C_ lt BI gt AXI_ADDR_WIDTH AXI address width C_ lt BI gt AXI_DATA_WIDTH AXI data width C_ lt BI gt AXI_ID_WIDTH AXI master ID width C_ lt BI gt AXI_NUM_MASTERS Number of AXI masters C_ lt BI gt AXI_NUM_SLAVES Number of AXI slaves C_FAMILY FPGA device family C_INSTANCE Instance name of component C_ lt BI gt DCR_AWIDTH DCR address width C_ lt BI gt DCR_DWIDTH DCR data width C_ lt BI gt DCR_NUM_SLAVES Number of DCR slaves C_ lt BI gt FSL_DWIDTH FSL data width C_ lt BI gt LMB_AWIDTH LMB address width C_ lt BI gt LMB_DWIDTH LMB data width C_ lt BI gt LMB_NUM_SLAVES Number of LMB slaves Reserved Parameters Table 2 4 lists the parameters that Platgen populates automatically Table 2 4 Reserved Parameters Parameter BUS_CONFIG Description Defines the bus configuration of the MicroBlaze processor FAMILY Defines the FPGA device family INSTANCE Defines the instance name of the component DCR_AWIDTH Defines the DCR address
26. Where nCHand1e ls the instance pointer of ConstraintManager bsb readPinData strCsvPinFile Where strCsvPinFile ls the file that defines the CSV used for pins bsb registerPinData nCHandle nComIdXbd nDesignid strCsvFilePath nCHandle Is the instance pointer of ConstraintManager nComIdxbd Is the board MPD in memory nDesignID Is the HURRI design constructed by BSB strCsvFilePath ls the path to the CSV file bsb registerRawUcfFile nCHandle strUcfFilePath nCHand1e ls the instance pointer of ConstraintManager strUcfFilePath ls the path to the UCF bsb registerRawUcfFileForBusI f nCHandle nDesignId vecBusIf nCHandle Is the instance pointer of ConstraintManager nDesignID Is the HURRI design constructed by BSB Embedded System Tools Reference Manual www xilinx com 207 UG111 July 6 2011 Chapter 16 Microprocessor Peripheral Definition Translation tool MPDX XILINX Example The following example shows how to use the CSV pin file in a script nCHandle is instance pointer of ConstraintManager nComIdXbd is the SP605 nDesignID is the HURRI design proc RunUcfConstraintGen nCHandle nComIdXbd nDesignId set nResult 0 if nCHandle eq return SnResult if nComIdXbd eq return SnResult if nDesignId eq return S nResult set bApiStatus tgi init 1 0 fail Client connected if SbApiStatus 0 return 1 Reposit
27. You can change the default name using o output_file_name The output file is created in ELF format Wp option Wa option W1 option The compiler mb gcc or powerpc eabi gcc is a wrapper around other executables such as the preprocessor compiler cc1 assembler and the linker You can run these components of the compiler individually or through the top level compiler There are certain options that are required by tools but might not be necessary for the top level compiler To run these commands use the options listed in the following table Table 9 4 Tool Specific Options Passed to the Top Level GCC Compiler Option Tool Example Wp option Preprocessor mb gcc Wp D Wp MYDEFINE Signal the pre processor to define the symbol MYDEF INE with the D MYDEFINE option Wa option Assembler powerpc eabi gcc Wa m405 Signal the assembler to target the PowerPC 405 processor with the m405 option W1 option Linker mb gcec Wl M Signal the linker to produce a map file with the M option help Use this option with any GNU compiler to get more information about the available options You can also consult the GCC manual A link to the manual is supplied in the Additional Resources on page 122 B directory Add directory to the C run time library search paths 90 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Common Compiler Usage
28. are merged handles and not the original handles Hardware Read Access APIs The following sections contain a summary table and descriptions of defined hardware read access APIs To go to the API descriptions which are provided in the following section click on a summary link www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 g XILINX EDK Hardware Tcl Commands API Summary xget_hw_busif_value lt handle gt lt busif_name gt xget_hw_bus_slave_addrpairs lt merged_bus_handle gt xget_hw_busif_handle lt handle gt lt busif_name gt xget_hw_connected_busifs_handle lt merged_mhs_handle gt lt businst_name gt lt busif_type gt xget_hw_connected_ports_handle lt merged_mhs_handle gt lt connector_name gt lt port_type gt xget_hw_ioif_handle lt handle gt lt ioif_name gt xget_hw_ioif_value lt handle gt lt ioif_name gt xget_hw_ipinst_handle lt mhs_handle gt lt ipinst_name gt xget_hw_mpd_handle lt ipinst_handle gt xget_hw_name lt handle gt xget_hw_option_handle lt handle gt lt option_name gt xget_hw_option_value lt handle gt lt option_name gt xget_hw_parameter_handle lt handle gt lt parameter_name gt xget_hw_parameter_value lt handle gt lt parameter_name gt xget_hw_pcore_dir_from_mpd lt mpd_handle gt xget_hw_pcore_dir lt ipinst_handle gt xget_hw_port_connectors_list lt ipinst_handle gt lt portName gt xget_hw_parent_handle lt handle gt xget_hw_port_connectors
29. block RAMs in the FPGA This utility reads an Microprocessor Hardware Specification MHS file and invokes the Data2MEM utility provided in Xilinx ISE to initialize the FPGA block RAMs To invoke the BitInit tool type the following bitinit lt mhsfile gt options Note You must specify lt mhsfile gt before specifying other tool options Table 12 1 lists the supported options in BitInit Table 12 1 BitInit Syntax Options Option Command Description Input BMM file bm Specifies the input BMM file which contains the address map and the location of the instruction memory of the processor Default implementation lt sysname gt _bd bmm Bitstream file bt Specifies the input bitstream file that does not have its memory initialized Default implementation lt sysname gt bit Display Help h Displays the usage menu and then quits Log file name log Specifies the name of the log file to capture the log Default bitinit log Libraries path 1p Specifies the path to repository libraries This option can be repeated to specify multiple libraries Output bitstream file o Specifies the name of the output file to generate the bitstream with initialized memory Default implementation download bit Part name p lt partname gt Uses the specified part type to implement the design Embedded System Tools Reference Manual UG111 July 6 2011 www xilinx com 175 Chapter 12 Bitstream In
30. bss sections Startup Files The compiler includes pre compiled startup and end files in the final link command when forming an executable Startup files set up the language and the platform environment before your application code executes Start up files typically do the following e Set up any reset interrupt and exception vectors as required e Set up stack pointer small data anchors and other registers Refer to Table 9 8 page 108 for details e Clear the BSS memory regions to zero e Invoke language initialization functions such as C constructors e Initialize the hardware sub system For example if the program is to be profiled initialize the profiling timers e Set up arguments for the main procedure and invoke it Similarly end files are used to include code that must execute after your program ends The following actions are typically performed by end files e Invoke language cleanup functions such as C destructors e De initialize the hardware sub system For example if the program is being profiled clean up the profiling sub system Table 9 8 lists the register names values and descriptions in the C Runtime files Table 9 8 Register Initialization in C Runtime Files Register Value Description r1 _stack 16 The stack pointer register is initialized to point to the bottom of the stack area with an initial negative offset of 16 bytes The 16 bytes can be used for passing in argume
31. data after programming is done If your flash hardware has a different configuration when using the Program Flash Memory dialog box then the programming could fail Refer to your flash hardware datasheet for information about how to reset the configuration so that DQ7 has the appropriate outputs upon erasure and ending Embedded System Tools Reference Manual www xilinx com 195 UG111 July 6 2011 Chapter 14 Flash Memory Programming XILINX 196 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Chapter 15 Version Management Tools revup This chapter introduces the version management tools in XPS Overview When you open an older project with the current version of EDK the Format Revision Tool automatically performs format changes to an existing EDK project and makes that project compatible with the current version Backups of existing files such as Xilinx Microprocessor Project XMP and Microprocessor Hardware Specification MHS are performed before the format changes are applied These backup files are stored in the revup folder in the project directory Updates to IP and drivers if any are handled by the Version Management wizard which launches after the format revision tool runs The format revision tool does not modify the IPs used in the MHS design it only updates the syntax so the project can be opened with the new tools Format Revision Tool Backup and Update Proc
32. directory e The make file must have the targets include and libs e Each driver must also contain an MDD file and a Tcl file in the data subdirectory Open the existing EDK driver files to get an understanding of the required structure Refer to the Microprocessor Driver Definition MDD chapter in the Platform Specification Format Reference Manual for details on how to write an MDD and its corresponding Tcl file A link to the document is supplied in Appendix E Additional Resources The MSS file includes a library block for each library The library block contains a reference to the library name LIBRARY_NAME parameter and the library version LIBRARY_VER There is no default value for these parameters Each library is associated with a processor instance specified using the PROCESSOR_INSTANCE parameter The library directory contains C source and header files and a make file for the library The MLD file for each library specifies all configurable options for the libraries and each MLD file has a corresponding Tcl file You can write your own libraries These libraries must be in a specific directory under lt YOUR_PROJECT gt sw_services or lt library_name gt sw_services as shown in Figure 8 1 on page 76 e The LIBRARY_NAME attribute lets you specify any name for your libraries which is also the name of the library directory e The source files and make file for the library must be in the src subdirectory under the
33. instructions in MicroBlaze A link to the document is provided in Additional Resources page 122 mno xl multiply high Do not use multiply high instructions This option is the default mxl soft mul This option tells the compiler that there is no hardware multiplier unit on MicroBlaze so every 32 bit multiply operation is replaced by a call to the software emulation routine__mu1si3 This option is the default mno x1 soft div You can instantiate a hardware divide unit in MicroBlaze When the divide unit is present this option tells the compiler that hardware divide instructions can be used in the program being compiled This option can improve the performance of your program if it has a significant amount of division operations The compiler automatically defines the C pre processor definition HAVE_HwW_DIv when this switch is used This allows you to write C or assembly code tailored to the hardware based on whether this feature is specified as available or not Refer to the MicroBlaze Processor Reference Guide for more details about the usage of the hardware divide option in MicroBlaze A link to the document is provided in the Additional Resources section of this chapter mxl1 soft div This option tells the compiler that there is no hardware divide unit on the target MicroBlaze hardware This option is the default The compiler replaces all 32 bit divisions with a call to the corresponding software emulation routines __divsi3
34. is the name of the port to be deleted Example Delete a top level port called sys_clk_pin xdel_hw_toplevel_port mhs_handle sys_clk_pin Modify Commands xset_hw_parameter_ value lt busif_handle gt lt busif_value gt Description Sets the value of the parameter to the given value Arguments lt port_hand1le gt is the handle to the port whose value must be set lt port_value gt is the value to be set Example Set the value of a parameter to 2 xset_hw_ parameter value param_handle 2 xset_hw_port_value lt port_handle gt lt port_value gt Description Sets the value of the port to the given value Arguments lt port_hand1e gt is the handle to the port whose value must be set lt port_value gt is the value to be set Example Set the value of a port to my_connection xset_hw_port_value port_handle my _ connection xset hw _busif value lt busif_handle gt lt busif_value gt Description Sets the value of the bus interface to the given value Arguments lt busif_hand1e gt is the handle to the bus interface whose value must be set lt busif_value gt is the value to be set Example Set the value of a bus interface to my_bus xset_hw_busif value busif_handle my_bus Embedded System Tools Reference Manual www xilinx com 247 UG111 July 06 2011 Appendix C EDK Tel Interface XILINX Tcl Flow During Hardware Platform Generation 248 Input Files Platgen Simgen Libgen and o
35. lt connector_name gt lt direction gt Description Arguments Example Adds a new top level port to the MHS specified by lt mhs_handle gt Returns a handle to the newly created port if successful and NULL otherwise lt mhs_hand1e gt is the handle to the MHS in which this top level port has to be added lt port_name gt is the name of the port that needs to be added lt connector_name gt is the name of the connector lt direction gt is the direction of the port I 0 or IO Add a top level input port sys_clk_pin with connector dcm_clk_s xadd_hw_toplevel_port mhs_handle sys_clk_ pin dem_clk_s I Delete Commands xdel_hw_ipinst lt mhs_handle gt lt inst_name gt Description deletes the IP instance with a specified instance name Arguments lt mhs_hand1e gt is the handle to the original MHS lt inst_name gt is the name of the instance to be deleted Example Delete an instance called mymb xdel_hw_ipinst mhs_handle mymb Embedded System Tools Reference Manual www xilinx com 245 UG111 July 06 2011 Appendix C EDK Tcl Interface XILINX xdel_ hw_ipinst_busif lt ipinst_handle gt lt busif_name gt Description Deletes a specified bus interface on an IP instance handle Arguments lt ipinst_hand1le gt is the handle of the IP instance lt busif_name gt is the name of the bus interface that is to be deleted Example Delete the ILMB bus interface from a MicroBlaze instance xdel_hw_ipinst_b
36. lt library_name gt directory e The make file must have the targets include and libs www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX OS Block OS Block e Each library must also contain an MLD file and a Tel file in the data subdirectory Refer to the existing EDK libraries for more information about the structure of the libraries Refer to the Microprocessor Library Definition MLD chapter in the Platform Specification Format Reference Manual for details on how to write an MLD and its corresponding Tcl file A link to the document is supplied in Appendix E Additional Resources The MSS file includes an OS block for each processor instance The OS block contains a reference to the OS name OS_NAME parameter and the OS version OS_VER There is no default value for these parameters The bsp directory contains C source and header files and a make file for the OS The MLD file for each OS specifies all configurable options for the OS Each MLD file has a corresponding Tcl file associated with it Refer to the Microprocessor Library Definition MLD and Microprocessor Software Specification MSS chapters in the Platform Specification Format Reference Manual A link to the document is supplied in Appendix E Additional Resources You can write your own OSs These OSs must be in a specific directory under lt YOUR_PROJECT gt bsp or lt library_name gt bsp as shown in F
37. lt nFSL_S gt _Clk lt BI gt lt nFSL_S gt _Read Examples FSL_S_Read Busl_FSL_S_ Read in in in in in n n std_logic std_logic std_logic std_logic td_logic td_logic Embedded System Tools Reference Manual UG111 July 6 2011 www xilinx com 33 Chapter 2 Platform Specification Utility PsfUtility XILINX Master FSL Ports Table 2 11 lists the required Master FSL ports naming conventions Table 2 11 Master FSL Port Naming Conventions lt nFSL gt or A meaningful name or acronym for the master I O The last five characters of lt nFSL_M gt lt nFSL_M gt must contain the string FSL_M upper lower or mixed case lt BI gt A bus identifier Optional for peripherals with a single master FSL port and required for peripherals with multiple master FSL ports lt BI gt must not con tain the string FSL_M upper lower or mixed case For peripherals with mul tiple master FSL ports the lt BI gt strings must be unique for each bus interface FSL Master Outputs For interconnection to the FSL masters must provide the following outputs lt BI gt lt nFSL_M gt _Full out std_logic Examples FSL_M Full out std_logic Memcon_FSL_M_Full out std_logic FSL Master Inputs For interconnection to the FSL masters must provide the following inputs lt BI gt lt nFSL gt _C1lk in std_logic lt BI gt lt nFSL gt _Rst in std_logic lt BI g
38. lt number of bytes gt of memory locations from the specified memory address Defaults to byte b read Returns a list of data values The data type depends on the data width of memory access xwmem lt target id gt lt address gt lt number of bytes gt half word b h w lt value list gt xwmem lt target id gt var lt Global Variable Name gt lt value list gt Writes lt number of bytes gt data value from the specified memory address Defaults to byte b write xrreg lt target id gt reg Reads all registers or only register number lt reg gt xwreg lt target id gt reg value Writes a 32 bit value into register number lt reg gt xstack_check lt target id gt Gives the stack usage information of the program running on the current target The most recent ELF file downloaded on the target is taken into account for stack check Embedded System Tools Reference Manual UG111 July 6 2011 www xilinx com 165 Chapter 10 Xilinx Microprocessor Debugger XMD XILINX Program Control Options Table 10 18 Program Control Options Option xbreakpoint lt target id gt addr function name sw hw Description Sets a breakpoint at the given address or start of function Note Breakpoints on instructions immediately following an IMM instruction can lead to undefined results for an XMDStub target xcontinue lt target id gt lt Execute Start Addres
39. t std_logic_vector C_M_AXI_ LITE DATA WIDTH 8 1 t std_logic std_logic std_logic std_logic_vector C_ lt BI gt _DATA_WIDTH 1 downto 0 std_logic_vector 1 downto 0 std_logic std_logic std_logic std_logic_vector 1 downto 0 in std_logic_vector C_M_AXI LITE DATA _WIDTH 1 in std_logic_vector 1 downto 0 in std_logic 30 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Conventions for Defining HDL Peripherals Slave AXI4LITE ports Slave AXI4LITE ports must use the naming conventions shown in Table 2 8 Table 2 8 Slave AXI4LITE Port Naming Conventions lt BI gt A bus identifier For peripherals with multiple AXI4 ports the lt BI gt strings must be unique for each bus interface Trailing underline characters such as _ in the lt BI gt string are ignored AXI4LITE Slave Outputs lt BI gt _AWREADY out std_logic lt BI gt _WREADY out std_logic lt BI gt _BRESP out std_logic_vector 1 downto 0 lt BI gt _BVALID out std_logic lt BI gt _ARREADY out std_logic lt BI gt _RDATA out std_logic_vector C_ lt BI gt _DATA_WIDTH 1 downto 0 lt BI gt _RRESP out std_logic_vector 1 downto 0 lt BI gt _RVALID out std_logic Examples lt BI gt _RDATA out std_logic_vector C_S_AXTI_ DATA WIDTH 1 downto 0 lt BI gt _RRESP out std_logic_vector 1 downto 0 lt BI gt _RVALID out std_logic A
40. xget_hw_port_handle lt handle gt lt port_name gt Description Arguments Returns the handle to a port associated with the handle If a handle is of type MHS the returned handle points to a global port of the given name lt handle gt is the handle to the MPD original IP instance merged IP instance original MHS or merged MHS lt port_name gt is the name of the port whose handle is required If lt port_name gt is specified as an asterisk a list of port handles is returned To access an individual port handle you can iterate over the list in Tel If a handle is of type MHS original or merged the returned handle points to a global port with the given name xget_hw_port_value lt handle gt lt port_name gt Description Arguments Returns the value of the specified port The value of a port is the signal name connected to that port lt handle gt is the handle to the MPD original IP instance merged IP instance original MHS or merged MHS lt port_name gt is the name of the port whose value is required xget_hw_proj_setting lt prop name gt Description Arguments Returns the value of the property specified by prop_name lt prop_name gt is the name of the property whose value is needed Options are fpga_family fpga_subfamily fpga_partname fpga_device fpga_package fpga_speedgrade xget_hw_proc_slave_periphs lt merged_proc_handle gt Description Arguments 238 Returns a list o
41. 0 std_logic Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Conventions for Defining HDL Peripherals Slave AXI4 Ports Slave AXI4 ports must use the naming conventions shown in Table 2 6 Table 2 6 Slave AXI4 Port Naming Conventions lt BI gt A bus identifier For peripherals with multiple AXI4 ports the lt BI gt strings must be unique for each bus interface Trailing underline characters such as _ in the lt BI gt string are ignored AXI4 Slave Outputs lt BI gt _awready out std_logic lt BI gt _wready out std_logic lt BI gt _bid out std_logic_vector C_ lt BI gt _ID_WIDTH 1 downto 0 lt BI gt _bresp out std_logic_vector 1 downto 0 lt BI gt _bvalid out std_logic lt BI gt _arready out std_logic lt BI gt _rid out std_logic_vector C_ lt BI gt _ID_WIDTH 1 downto 0 lt BI gt _rdata out std_logic_vector C_ lt BI gt _DATA_WIDTH 1 downto 0 lt BI gt _rresp out std_logic_vector 1 downto 0 lt BI gt _rlast out std_logic lt BI gt _rvalid out std_logic Examples s_axi_bid out std_logic_vector C_S_AXI_ID_WIDTH 1 downto 0 s_axi_bresp out std_logic_vector 1 downto 0 s_axi_bvalid out std_logic AXI4 Slave Inputs lt BI gt _awid in std_logic_vector C_ lt BI gt _ID_WIDTH 1 downto 0 lt BI gt _awaddr in std_logic_vector C_ lt BI gt _ADDR_WIDTH 1 downto 0 lt BI gt _awlen in std_logic_vector 7 downto 0
42. 11 GNU Debugger Embedded System Tools Reference Manual www xilinx com 103 UG111 July 6 2011 104 Chapter 9 GNU Compiler Tools XILINX xl mode bootstrap This option is used for applications that are loaded using a bootloader Typically the bootloader resides in non volatile memory mapped to the processor reset vector If a normal executable is loaded by this bootloader the application reset vector overwrites the reset vector of the bootloader In such a scenario on a processor reset the bootloader does not execute first it is typically required to do so to reload this application and do other initialization as necessary To prevent this you must compile the bootloaded application with this compiler flag On a processor reset control then reaches the bootloader instead of the application Using this switch on an application that is deployed in a scenario different from the one described above will not work This mode uses crt2 o asa startup file x1l mode novectors This option is used for applications that do not require any of the MicroBlaze vectors This is typically used in standalone applications that do not use any of the processor s reset interrupt or exception features Using this switch leads to smaller code size due to the elimination of the instructions for the vectors This mode uses crt3 o as a startup file Caution Do not use more than one mode of execution on the command line You will receive lin
43. 11 Input Sections Assigned by the PowerPC Processor Linker Scripts Section Description boot Processor reset vector code with initial branch to boot0 boot0 Boot code heap Section of memory defined for the heap stack Section of memory defined for the stack bss Static and global variables without initial values Initialized to 0 by the boot code sbss Small static and global variables without initial values Initialized to 0 by the boot code sbss2 Small read only static and global variables with initial values Initialized to zero by the boot code sdata Small static and global variables with initial values data Static and global variables with initial values These variables are initialized to zero by the boot code sdata2 Small read only static and global variables with initial values rodata Read only variables text Program instructions from code in functions and global assembly statements got2 Global Offset Table GOT The GOT is to define a place where position independent code can access global data goti Global Offset Table GOT The GOT defines a place where position independent code can access global data fixup Fixup information such as fixup record table jer Compiler specific Used by compiler initialization functions 116 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX PowerPC C
44. ANY LOSS OF DATA OR LOST PROFITS ARISING FROM YOUR USE OF THE DOCUMENTATION Copyright 2011 Xilinx Inc XILINX the Xilinx logo Virtex Spartan ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries All other trademarks are the property of their respective owners Revision History The following table shows the revision history for this document Date Version Revision 03 01 2011 13 1 EDK 13 1 release Revision numbering format change to match release number 07 06 2011 13 2 EDK 13 2 release Changes in this release are e Obsoleted OPB and PLB IP e Added support for external simulation model for Micron Memory Models used with XPS MIG e Added option for instyle instantiation and a new simulation option to support Mentor Graphics QuestaSim e Added command line options to discover and to enable external memory e Changed the EDK diagram to match new flow 07 06 2011 13 2_web EDK 13 2 web release has the following changes e Removed the obsolete OPB and PLB interface references e Added information on Questa simulation in command line mode Chapter 5 Command Line Mode e Added AXI BFM information in Chapter 6 Bus Functional Model Simulation e Added information regarding Revup actions when updating project from 12 x and below to 13 x project Chapter 15 Version Management Tools revup Embedded System Tools Reference Manual www xilinx
45. Compiler Usage and Options dp_lite Produces code targeted to the Double precision Lite FPU coprocessor This version supports both single and double precision hardware floating point and does not use hardware divide and square root instructions The compiler automatically defines the C preprocessor definition HAVE_XFPU_DP_LITE when this option is given dp_full Produces code targeted to the Double precision Full FPU coprocessor This version supports both single and double precision hardware floating point and uses hardware divide and square root instructions The compiler automatically defines the C preprocessor definition HAVE_XFPU_DP_FULL when this option is given Caution Do not link code compiled with one variant of the mfpu switch with code compiled with other variants or without the mfpu switch You must use the switch even when you are only linking object files together This allows the compiler to use the correct set of libraries and prevent incompatibilities none This option tells the compiler to use software emulation for floating point arithmetic This option is the default Refer to the latest APU FPU user guide for detailed information on how to optimize use of the hardware floating point co processor A link to the guide is provided in Additional Resources page 261 mppcperflib Use PowerPC processor performance libraries for low level integer and floating emulation and some simple string routines These l
46. D Interconnect Settings and Parameter Automations for AXI Designs XILINX 258 C_ lt Buslf gt _AXI_ID_WIDTH The AXI Interconnect appends the BASE ID bits to transactions The slaves must know how many bits are appended by the AXI Interconnect which is specified in the C_ lt BusIf gt _AXI_ID_WIDTH parameter Regardless of whether the tools computed the BASE ID values or you specified them the tools compute the maximum number of bits necessary to make the masters unique and set that value as the AXI_ID_WIDTH on the AXI Interconnect and the connected slaves C_INTERCONNECT_ lt Buslf gt _ACLK_RATIO This parameter determines whether the frequency of the clock port of the master slave interface is at an integer ratio with respect to the frequency of the clock port of the interconnect The tools trace the IP clocks in the design to identify the value of the frequency of the clock port They do this based on the CLK_FREQ_HZ sub property on the clock port identified by SIGIS CLK tag in the MPD If this sub property does not exist the tools create the sub property by tracing the clock port connection through bus interfaces clock generator external ports etc Once the clock frequencies are determined the tools then compute the values of C_INTERCONNECT_ lt BusIf gt _ACLK_RATIO parameters To compute this parameter the tools look at each interconnect in the design and iden
47. E Wp option libraryname S Wa option L Lib Directory C WI option g help Header File Search Option gstabs B directory I Directory Name On L directory ay I directory Linker Options save temps I library defsym _STACK_SIZE value o filename defsym _HEAP_SIZE value www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Common Compiler Usage and Options General Options E Preprocess only do not compile assemble and link The preprocessed output displays on the standard out device S Compile only do not assemble and link Generates a s file C Compile and Assemble only do not link Generates a o file g This option adds DWARF2 based debugging information to the output file The debugging information is required by the GNU debugger mb gdb or powerpc eabi gdb The debugger provides debugging at the source and the assembly level This option adds debugging information only when the input is a C C source file gstabs Use this option for adding STABS based debugging information on assembly files and assembly file symbols at the source level This is an assembler option that is provided directly to the GNU assembler mb as or powerpc eabi as If an assembly file is compiled using the compiler mb gcc or powerpc eabi gec prefix the option with Wa On The GNU compiler provides optimizations at different levels The optimization levels in the foll
48. To compile memory model into the user library Simgen also generates simulator specific compilation elaboration commands into respective helper setup scripts Refer to Chapter 7 Simulation Model Generator Simgen for more information Embedded System Tools Reference Manual www xilinx com 15 UG111 July 6 2011 Chapter 1 Embedded System and Tools Architecture Overview XILINX Software Development Kit The Software Development Kit SDK provides a development environment for software application projects SDK is based on the Eclipse open source standard SDK has the following features e Can be installed independent of ISE and XPS with a small disk footprint e Supports development of software applications on single or multi processor systems e Imports the XPS generated hardware platform definition e Supports development of software applications in a team environment e Ability to create and configure board support packages BSPs for third party OS e Provides off the shelf sample software projects to test the hardware and software functionality e Hasan easy GUI interface to generate linker scripts for software applications program FPGA devices and program parallel flash memory e Has feature rich C C code editor and compilation environment e Provides project management e Configures application builds and automates the make file generation e Supplies error navigation e Provides a well integrated environment f
49. To create a new project use the command xload mhs lt basename gt mhs XPS reads in the MHS file and creates the new project The project name is the same as the MHS base name All of the files generated have the same name as MHS After reading in the MHS file XPS also assigns various default drivers to each of the peripheral instances if a driver is known and available to XPS Opening an Existing Project If you already have an XMP project file you can load that file using the command xload xmp lt basename gt xmp XPS reads in the XMP file Saving Your Project Files To save XMP and make files for your project use the command save xmp make proj Command save proj saves the XMP MHS and make files To save the make file use the save make command explicitly Setting Project Options You can set project options and other fields in XPS using the xset command You can also display the current value of those fields by using xget commands The xget command also returns the result as a Tcl string result which can be saved into a Tcl variable Table 5 1 shows the options you can use with the xget and xset commands xset option lt value gt xget option Table 5 1 xset and xget Command Options Option Name Description arch Set the target device architecture dev Set the target part name enable par_timing_error 0 1 When set to 1 enables PAR timing error external_mem_sim 0 1 When set to 1 enables
50. XILINX Format Revision Tool Backup and Update Processes 10 1 Changes Tools are updated to reflect revision 10 1 The following tags were removed from the XMP file in 10 1 UseProjNav PnimportBitFile PnImportBmmFile 9 2i Changes e Updates XMP The XMP tag EnableResetOptimization was added and its value is set to 0 false If it is set to true it will improve timing on the reset signal e Updates XMP The XMP tag EnableParTimingError was added and its value is set to 0 false If it set to 1 true the tools will error out if timing conditions are not met after Place and Route Changes in 9 1i e Updates XMP Simulation libraries path are removed from the project Simulation library paths are now applied across all the XPS projects for the machine e Updates XMP Stack and Heap size for custom linker scripts can no longer be provided in the compiler settings dialog These have to be specified in the custom linker script Stack and Heap size can be provided through the compiler settings dialog for default linker scripts Changes in 8 2i e Updates MHS For submodule designs the Format Revision Tool expands any I O ports into individual _I _O and _T ports This aligns with changes to Platgen any buffers in the generated stub HDL are not instantiated and the interface of the generated HDL stays the same as that in the MHS file e Updates MHS The Format Revision Tool changes the value of SIGIS for top level ports fr
51. ___udivsi3 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX MicroBlaze Compiler Usage and Options mxl barrel shift The MicroBlaze processor can be configured to be built with a barrel shifter In order to use the barrel shift feature of the processor use the option mxl barrel shift The default option assumes that no barrel shifter is present and the compiler uses add and multiply operations to shift the operands Enabling barrel shifts can speed up your application significantly especially while using a floating point library The compiler automatically defines the C pre processor definition HAVE_HW_BSHIFT when this switch is used This allows you to write C or assembly code tailored to the hardware based on whether or not this feature is specified as available Refer to the MicroBlaze Processor Reference Guide for more details about the use of the barrel shifter option in MicroBlaze A link to the document is provided in Additional Resources page 261 mno xl barrel shift This option tells the compiler not to use hardware barrel shift instructions This option is the default mxl pattern compare This option activates the use of pattern compare instructions in the compiler Using pattern compare instructions can speed up boolean operations in your program Pattern compare operations also permit operating on word length data as opposed to byte length data on string manipulation routin
52. __stack_overflow_error tol You can override the standard stack overflow handler by providing the function _stack_overflow_exit in the source code which acts as the stack overflow handler Application Execution Modes xl mode executable This is the default mode used for compiling programs with mb gcc This option need not be provided on the command line for mb gcc This uses the startup file crto o x1 mode xmdstub The Xilinx Microprocessor Debugger XMD allows debugging of applications in a software intrusive manner known as XMDSTUB mode Compile programs being debugged in such a manner with this switch In such programs the address locations 0x0 to 0x800 are reserved for use by XMDSTUB Using x1 mode xmdstub has two effects e The start address of your program is set to 0x800 You can change this address by overriding the _TEXT_START_ADDR in the linker script or through linker options For more details about linker options refer to Linker Options page 93 If the start address is defined to be less than 0x800 XMD issues an address overlap error e crt1 ois used as the initialization file The crt1 o file returns the control back to the XMDStub when your program execution is complete Note Use x1 mode xmdstub for designs when XMDStub is part of the bitstream Do not use this mode when the system is complied for No Debug or when Hardware Debugging is turned ON For more details on debugging with XMD refer to Chapter
53. a Virtex device with multiple PowerPC processors It starts from 1 dcachestartadr lt D Cache start address gt Start address for reading or writing the data cache contents derstartadr Start address for reading and writing the Device Control Registers DCR lt DCR start address gt Using this option the entire DCR address space 210 addresses can be mapped to addresses starting from the lt DCR start address gt for debugging from XMD and GDB devicenr Position in the JTAG chain of the Virtex device containing the PowerPC lt PowerPC device position gt processor The device position number starts from 1 dtagstartadr Start address for reading or writing the data cache tags lt D Cache start address gt fputype sp dp XMD does not automatically look for a Floating Point Unit FPU in the PowerPC processor system To force XMD to detect a FPU specify this option with the FPU type in the system Options sp Single Precision dp Double Precision icachestartadr lt I Cache start address gt Start address for reading or writing the instruction cache contents 142 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Connect Command Options Table 10 10 PowerPC Processor Options Cont d Option isocmdcrstartadr lt ISOCM in Bytes DCR address gt Description DCR address corresponding to the ISOCM interface specified using the
54. ace Generate the System ACE technology file after the BIT file is updat ed with block RAM information bits Run the Xilinx implementation tools flow and generate the bitstream bitsclean Delete the BIT NCD and BMM files in the implementation directory clean Delete all tool generated files and directories download Download the bitstream onto the FPGA hwclean Delete the implementation directory init_bram Update the bitstream with block RAM initialization information makeiplocal Make an IP and all its dependent libraries local to the project netlist Generate the netlist netlistclean Delete the NGC or EDN netlist resync Update any MHS file changes into the memory and rewrites the XMP and makefile if required sim Generate the simulation models and run the simulator simmodel Generate the simulation models without running the simulator simclean Delete the simulation directory Reloading an MHS File All EDK design files refer to MHS files Any changes in MHS files have impact on other design files If there are any changes in the MHS file after you loaded the design use the the following command to re read MHS and XMP files run resync Embedded System Tools Reference Manual UG111 July 6 2011 48 www xilinx com g XILINX Adding or Updating an ELF File Adding or Updating an ELF File You can add or update the ELF files associated with a processor instance using this command xadd_elf lt proc
55. are exclusive interfaces For example an OPB Slave bus interface and a DCR Slave bus interface are exclusive because they can be connected simultaneously On a peripheral containing exclusive bus interfaces a port can be connected to only one of the exclusive bus interfaces Non exclusive bus interfaces cannot be connected simultaneously Peripherals with non exclusive bus interfaces have ports that can be connected to multiple non exclusive interfaces Non exclusive interfaces have the same bus interface standard Non Exclusive and Exclusive Bus Interfaces Signal Naming Conventions Signal names must adhere to the conventions specified in Conventions for Defining HDL Peripherals on page 23 e For non exclusive bus interfaces bus identifiers need not be specified e For exclusive bus interfaces identifiers must be specified only when the peripheral has more than one bus interface of the same bus standard and type Invoking the PsfUtility With Buses Specified in the Command Line You can specify buses on the command line when the bus signals do not have bus identifier prefixes The command line for invoking the PsfUtility is as follows psfutil hdl2mpd lt hdlfile gt lang vhdl ver top lt top_entity gt bus lt busstd gt lt bustype gt o lt mpdfile gt Exclusive and Non exclusive Bus Interface Command Line Examples For an example of a non exclusive bus interface to create an MPD specification for a peripheral
56. because it is the value the timer counter is loaded with when it is started define RESET_VALUE 0xF0000000 ERER k k k k k k kk k k k kk k k k k Function Prototypes kkk kk kk kk kk kk k k kk kkk kkk kk int TmrCtrIntrExample XIntc IntcInstancePtr XTmrCtr InstancePtr ul6 Deviceld ul6 Intrid u8 TmrCtrNumber void TimerCounterHandler void CallBackRef u8 TmrCtrNumber RRREKRKRKRKEKRKRKREKEKKKREEEK Variable Definitions kkkkkkkkkkkkkkkkkkkkkkkk XIntc InterruptController The instance of the Interrupt Controller z7 XTmrCtr TimerCounterInst The instance of the Timer Counter The following variables are shared between non interrupt processing and interrupt processing such that they must be global EJ volatile int TimerExpired EEEk k kkk kkk kkk kkk kkk kkk kk k k k k k k k kk k k k k k k k k k kk k k k k k k k k kk kk kk kk kk kk kkk This function is the main function of the Tmrctr example using Interrupts paramNone returnXST_SUCCESS to indicate success else XST_FATLURE to indicate a Failure noteNone kkkkkkkkkkk kkkk kkk k k kkkkkkkkkkkk kkk kk kk kkkkkkkkkkkkkkkkkkkkkkkkkkkkk int main void int Status Run the Timer Counter Interrupt example a7 Status TmrCtrIntrExample amp InterruptController amp TimerCounterInst TMRCTR_DEVICE_ID Embedded System Tools Reference Manual www xilinx co
57. com UG111 July 6 2011 EDK v13 2 Table of Contents Revision History a tsi a heed ee ee ee ee ee wie aw ee weeds 2 Chapter 1 Embedded System and Tools Architecture Overview Ut 0 eee ee ae ee eS ee ee ee E ee ey ee eee ee nes Oe Te ree 7 About EDK icici dict cit ee hii teneire nen inii ep tenia teks Hebe E E 7 Design Process OvervieW icrssosisssskencsrgd esbyd anegusuehessaGucaeee steeds 8 EDK OveryieW iceri perre ciri eis raaa EE EET E EEA E EE hE plese a 10 Chapter 2 Platform Specification Utility PsfUtility T ol OPONSE E ee r eke E hes EDA 19 MPD Creation Process Overview 0 6 000 c cece eee teens 20 Use Models for Automatic MPD Creation 0 0 000 n cee eee 21 DRC Checks in PsfUtility i025 cass tetssieteder ish ceieseiah ee eeenas 23 Conventions for Defining HDL Peripherals 0 23 Chapter 3 Psf2Edward Program Programi Usage ick iccexeioxeedoraeewegvi segue E RAE AAEE AE AAE EAA kee 39 Program OPHONS cc 540355 46s 3 5e0esidessqensh eE i Ee AE E EE 39 Chapter 4 Platform Generator Platgen Feat teS 4 210i ante giiawsnedieaeetenics e a a E e a i E E sean aes x 41 Tool Requirements c 4 ciiscisis intieiecbiie iets dente deed bobbed vend ates 41 Tool Usf iii ene eh tendena ida e ea e e ee hee p es ia 42 Tool Options cis 41335 ss iena haul EEE ates EEE eee eee EE EAE EE 42 Load Path seretii ee Ao te ied Eee ed 43 Output Files scepte eine duck kya e t
58. debugconfig command to configure the reset behavior which depends on your system architecture Refer to the Configure Debug Session on page 160 Download the ELF file Set the required Breakpoints and Watchpoints 10 Start the processor execution using the con command or step through the program using the stp command 11 Use the targets command to list the targets in the system Each target is associated witha lt target id gt an asterisk marks the active target 12 Use targets lt target id gt to switch between targets 13 Use the state command to check the processor status 14 Use the stop command to stop the processor 15 When the processor is stopped read and write the registers and memory 16 To re run the program use the run command Embedded System Tools Reference Manual www xilinx com 137 UG111 July 6 2011 Chapter 10 Xilinx Microprocessor Debugger XMD XILINX Running a Program in a Debug Session Connect to the processor Download the ELF file Set the Breakpoint at the lt exit gt function Start the processor execution using the con command Use the state command to check the processor status Use the stop command to stop the processor When the processor is stopped read and write the registers and memory So NOY OT oR Ge Nes To re run the program use the run command Using Safemode for Automatic Exception Trapping XMD allows you to trap exceptions in your program when errors oc
59. drivers pcores sw_services X10133 Figure 8 1 Directory Structure of Peripherals Drivers Libraries and OSs 76 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Output Files Default Repositories By default Libgen scans the following repositories for software components e S XILINX_EDK sw 1lib XilinxProcessorIPLib e XILINX_EDK sw 1lib e SXILINX_EDK sw ThirdParty It also treats the directory from which Libgen is invoked as a repository and therefore scans for cores under sub directories with standard directory names such as drivers bsp and sw_services Figure 8 2 shows the repository directory structure lt Library Name gt pcores lt my_driver gt drivers lt my_driver gt lt my_library gt C files X10134 Figure 8 2 Repository Directory Structure Search Priority Mechanism Libgen uses a search priority mechanism to locate drivers and libraries as follows 1 Search the current working directory 2 Search the repositories under the library path directory specified using the 1p option 3 Search the default repositories as described in Default Repositories Output Files Libgen generates directories and files in the lt YOUR_PROJECT gt directory For every processor instance in the MSS file Libgen generates a directory with the name of the processor instance Within each processor instanc
60. ec cceeeeeeeee ee 54 Getting and Installing the Platform Studio BFM Package 55 Using the Platform Studio BFM Package 0 0 0 e cee eee 55 Chapter 7 Simulation Model Generator Simgen Simgen OVERVIEW ss candied s tir oitir eis pete darn E EEE EEEE EEEE cee ees 61 Simulation Libraries ps vsi4e Sews Ween ce Ries ea ee eee e A pp eE pai 61 Compxlhib Utility eeen iire pe a REE EEEE EEE E EE EEEE EEEE 63 Simulation Models nunnu auauna a urrunen r anunn rurun serben bean 63 Simgen Syntax 9235 bres eens dwkseresedek NR perked ea n RGE REER a 66 Output Files 0 35 3h 5 nsdn death cue SGEE EEEE EEEF E ET ERR 68 Memory Initialization anaana bored duces dee bey chad nev bsvavhan eres 69 External Memory Simulation 0 000 0 c cece eee ee 72 Simulating Your Designs iios20 s4eyeiaeed lene es citeg ey ence pes 74 Chapter 8 Library Generator Libgen OVERVIEW EEEE EEE E E wa Ad win E E E aoe ad E 75 Tool Usages ic vis tans yeu ids ie p eed EA EEEE EE 75 T ob Options esac kr ii ennir tane inor EEEE EE EE EE EREE EEEE ERGE 75 Load Paths einser i eck be back aea Le E EE eee EOE O e aria 76 Qutp t Files G8 bene a EE TEERAA AE aae dwt tesenieed 77 Generating Libraries and Drivers 0 00 0c cece cece eee ee 78 MSS Parameters ersun ob0 a Seed edn NENIAE ae oak ee a bee ie eld 79 Diren eee A ANY E E E 80 Librari O82 cenre eos E a a a see a a E E Ges 80 OS BlOC
61. exception ID The stub handler is then registered for this exception ID Id contains the ID of the exception source It should be XIL_EXCEPTION_INT or in the range of 0 to XIL_EXCEPTION_LAST Refer to the xil_exception h file for further information Interrupt Setup Example EAk kkk kkk k kkk kkk kk kk kk k kkk kkk Include Files KEKEKEKKERKREKREKEREREKEKER include xparameters h include xtmrctr h include xintc h include xil_exception h RRR Rk k k k k k kk k k k k k k k k k k Constant Definitions kkk kkk kkk kkk kkk kkk kkk kk The following constants map to the XPAR parameters created in the xparameters h file They are only defined here such that a user can easily change all the needed parameters in one place define TMRCTR_DEVICE_IDXPAR_TMRCTR_0_DEVICE_ID define INTC_DEVICE_IDXPAR_INTC_0_DEVICE_ID define TMRCTR_INTERRUPT_IDXPAR_INTC_0_TMRCTR_0O_VEC_ID The following constant determines which timer counter of the device that is used for this example there are currently 2 timer counters in a device and this example uses the first one 0 the timer numbers are 0 based 222 www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 g XILINX Software APIs define TIMER _CNTR_O 0 The following constant is used to set the reset value of the timer counter making this number larger reduces the amount of time this example consumes
62. external memory simulation Default 0 gen_sim_tb true false Generate test bench for simulation models hdl vhdl verilog Set the HDL language to be used hier top sub Set the design hierarchy intstyle ise sysgen default Set the instantiation style e intstyle ise the project is instantiated in Project Navigator e intstyle sysgen the project is instantiated in System Generator Default default 46 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Setting Project Options Table 5 1 xset and xget Command Options Cont d Option Name is external _mem_ present Description xget command only Returns 1 if AXI DDRx memory controller Virtex 6 and 7 series is present otherwise returns 0 mix_lang_sim true false Specify if the available simulator tool can support both VHDL and Verilog package Set the package of the target device parallel_xst yes no Set the parallel synthesis option Default no sdk_export_bmm_bit 0 1 When set to 1 export BMM and BIT files for SDK sdk_export_dir lt directory path gt Directory to which to export SDK files Default project_directory sdk searchpath lt directories gt Set the search path as a semicolon separated list of directories speedgrade Set the speedgrade of the target device sim model structural behavioral timing Set the current simulation mod
63. follow MicroBlaze Simulator Target You can use mb gdb and XMD to debug programs on the cycle accurate simulator built in to XMD Usage connect mb sim memsize lt size gt Embedded System Tools Reference Manual www xilinx com 159 UG111 July 6 2011 Chapter 10 Xilinx Microprocessor Debugger XMD XILINX MicroBlaze Simulator Option Option Description memsize lt size gt The width of the memory address bus allocated in the simulator Programs can access the memory range from 0 to 2 7 1 The default memory size is 64 KB Simulator Target Requirements To debug programs on the Cycle Accurate Instruction Set Simulator using XMD you must compile programs for debugging and link them with the startup code in crt0 o The mb gcc can compile programs with debugging information when it is run with the option g and by default mb gcc links crt0 o with all programs The option is x1 mode executable The program memory size must not exceed 64 K and must begin at address 0 The program must be stored in the first 64KB of memory Note XMD with a simulator target does not support the simulation of OPB peripherals MDM Peripheral Target You can connect to the mdm peripheral and use the UART interface for debugging and collecting information from the system Usage connect mdm uart MDM Target Requirements To use the UART functionality in the MDM target you must set the C_USE_UART para
64. for each bus interface Note If lt BI gt is present lt Sin gt is optional LMB Slave Outputs For interconnection to the LMB slaves must provide the following outputs lt BI gt lt Sin gt _DBus out std_logic_vector 0 to C_ lt BI gt LMB_DWIDTH 1 lt BI gt lt Sl1n gt _Ready out std_logic Examples D_Ready out std_logic I_Ready out std_logic LMB Slave Inputs For interconnection to the LMB slaves must provide the following inputs lt BI gt lt nLMB gt _ABus in std_logic_vector 0 to C_ lt BI gt LMB_AWIDTH 1 lt BI gt lt nLMB gt _AddrStrobe in std_logic lt BI gt lt nLMB gt _BE in std_logic_vector 0 to C_ lt BI gt LMB_DWIDTH 8 1 7 lt BI gt lt nLMB gt _Clk in std_logic lt BI gt lt nLMB gt _ReadStrobe in std_logic lt BI gt lt nLMB gt _Rst in std_logic lt BI gt lt nLMB gt _WriteDBus in std_logic_vector 0 to C_ lt BI gt LMB_DWIDTH 1 lt BI gt lt nLMB gt _WriteStrobe in std_logic Examples LMB_ABus in std_logic_vector 0 to C_LMB_ AWIDTH 1 DLMB_ABus in std_logic_vector 0 to C_DLMB_ AWIDTH 1 Embedded System Tools Reference Manual www xilinx com 35 UG111 July 6 2011 Chapter 2 Platform Specification Utility PsfUtility XILINX Master PLBV4 6 Ports Master PLBV4 6 ports must use the naming conventions shown inTable 2 13 Table 2 13 Master PLBV4 6 Port Naming Conventions lt M gt Prefix for the master output lt PLB_
65. have vectored values The tools capture these values on the end point IPs and at run time and gather these values and build the necessary vectors that can be set as the value of the parameters on the AXI Interconnect The tools also make some type conversions such as string to hex to make it easier for you and the AXI Interconnect to understand the values For example you can specify the value of the AXI protocol of the peripherals that are connected to the interconnect as AXI4 AXI3 or AXI4LITE These values are encoded as 0 1 and 2 respectively In a design that has four slaves connected to the interconnect with protocol values and positions as shown below the value of the protocol parameter is constructed and set by the tools Slave at position 0 protocol axi4 Slave at position 1 protocol axi3 Slave at position 2 protocol axi4lite Slave at position 3 protocol axi4lite Value 256 bit set on the interconnect is C_M_AXI_ PROTOCOL 0Ox0000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000002000000020000000100000000 Parameter Automations The EDK tool automatically compute certain parameters in AXI designs to enable ease of use and to optimize the designs The following subsections list the auto computed parameters C_INTERCONNECT_ lt Buslf gt _BASE_ID This parameter is used to specify the unique Base ID for each master interface that is connected to the
66. in their distribution and tools Other Switches and Features Other switches and features might not be supported by the Xilinx EDK compilers and or platform such as fprofile arcs Some features might also be experimental in nature as defined by open source GCC and could produce incorrect code if used inappropriately Refer to the GCC manual for more information on specific features A link to the document is provided in Additional Resources page 261 Additional Resources 122 GNU Information e GCC Feature Reference http gcec gnu org onlinedocs gcc 4 1 2 gcc e Invoking the compiler for different languages http gcc gnu org onlinedocs gcc 4 1 2 gcc Invoking G_002b_002b html Invoking G_002b_002b e GCC online manual http www gnu org manual manual html e GNU C standard library http gcc gnu org onlinedocs libstdc manual spine html e GNU linker scripts http www gnu org software binutils PowerPC Information e IBM Book E http www ibm com e IBM PowerPC performance library http sourceforge net projects ppcperflib e APU FPU documentation http www xilinx com support documentation ip_documentation apu_fpu_virtex5 pdf MicroBlaze Information e The MicroBlaze Processor Reference Guide http www xilinx com support documentation sw_manuals xilinx13_2 mb_ref_guide pdf www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Chapter 1
67. is greater than the stack size available the program tries to write in other incorrect sections of the program leading to incorrect execution of the code Note A minimum stack size of 16 bytes 0x0010 is required for programs linked with the Xilinx provided C runtime CRT files defsym _HEAP SIZE value The total memory allocated for the heap can be controlled by the value given to the variable HEAP_SIZE The default value of _HEAP_SIZE is zero Dynamic memory allocation routines use the heap If your program uses the heap in this fashion then you must provide a reasonable value for _HEAP_SIZE For advanced users you can generate linker scripts directly from XPS Memory Layout The MicroBlaze and PowerPC processors use 32 bit logical addresses and can address any memory in the system in the range 0x0 to OxFFFFFFFF This address range can be categorized into reserved memory and I O memory Reserved Memory Reserved memory has been defined by the hardware and software programming environment for privileged use This is typically true for memory containing interrupt vector locations and operating system level routines Table 9 5 lists the reserved memory locations for MicroBlaze and PowerPC processors as defined by the processor hardware For more information on these memory locations refer to the corresponding processor reference manuals Note In addition to these memories that are reserved for hardware use your software en
68. level component T The high level IP XACT component files reside in XILINX_ ipxact hurri xilinx com components DK data wizards Board Options The VLNV reference is used as follows V is the name of the vendor Tools use this element to sort various board files based on vendor name Lis the library catalog of the vendor N is the name of the board This is the name the tools display for you when a board is selected V is the board revision number An example is OPTION VLNV xilinx com bsb_lib boards sp605 C Reference Clock IO_INTERFACE IO_IF gclk IO_TYPE xilinx com bsb_lib rtl_busdefs clock 1 0 PARAMETER refclk_frequency_0 200000000 DT LONG ASSIGNMENT CONSTANT IO_IF clock_0 IO_IS frequency PORT GCLK DIR I IO_IF gclk IO_IS CLK SIGIS CLK ASSIGNMENT REQUIRE Reference Reset IO_INTERFACE IO_IF rst_1 IO_TYPE xilinx com bsb_lib rtl_busdefs reset 1 0 PARAMETER reset_polarity 1 DT STRING ASSIGNMENT CONSTANT IO_IF reset_0 IO_IS RST_POLARITY PORT RESET_N DIR I IO IF rst_1 IO_IS RESET SIGIS RST ASSIGNMENT REQUIRE Embedded System Tools Reference Manual www xilinx com 203 UG111 July 6 2011 Chapter 16 Microprocessor Peripheral Definition Translation tool MPDX XILINX
69. level interrupt handling happens here Vectoring of individual interrupts to final handlers happens here Acknowledges to the interrupt controller and statistics collection are also options Save and restore of register context happens here Located at an address that is either fixed statically or fixed at run time Usually just a branch to the next level vectoring code X11018 Interrupt Flow Embedded System Tools Reference Manual UG111 July 06 2011 XILINX Software Setup and Interrupt Flow Interrupt Flow for MicroBlaze Systems MicroBlaze interrupts go through the following flow 1 Interrupts have to be enabled on MicroBlaze by setting appropriate bits in the Machine Status Registers MSR Upon an external interrupt signal being raised the processor first disables further interrupts Then the processor jumps to an absolute fixed address 0x0000_0010 The software platform or OS provides vectoring code at this address which transfers control to the main platform interrupt handler The platform interrupt handler saves all of the processor registers that could be clobbered further down onto the current application stack The handler then transfers control to the next level handler Because the next level handler can be dependent on whether there is an interrupt controller in the system or not the handler consults an internal interrupt vectoring table to determine the function ad
70. library directories Simulation Model m beh str tim Allows you to select the type of simulation models to be used Type The supported simulation model types are behavioral beh structural str and timing tim Default beh Mixed Language N A This option is depreciated The tool assumes mixed yes Output Directory od lt output_dir gt Specifies the project directory path The default is the current directory Target Part or Family p lt partname gt Allows you to target a specific part or family This option must be specified Processor ELF Files pe lt proc_instance gt elf file lt elf_file gt Specifies a list of ELF files to be associated with the processor with instance name as defined in the MHS Simulator s mgm questa ies isim Generates compile script and helper scripts for vendor simulators The options are mgm Mentor Graphics ModelSim questa Mentor Graphics QuestaSim ies Cadence Incisive Enterprise Simulator IES isim ISE Simulator ISIM Embedded System Tools Reference Manual UG111 July 6 2011 www xilinx com 67 Chapter 7 Simulation Model Generator Simgen XILINX Table 7 1 Simgen Syntax Options Cont d Option Command Description Source Directory sd lt source_dir gt Specifies the source directory to search for netlist files Testbench Template tb Creates a testbench template file Use ti a
71. location where the interrupt occurred The return instruction also enables interrupts again on the MicroBlaze processor The application resumes normal execution at this point Xilinx recommends that interrupt handlers be kept to a short duration and the bulk of the work be left to the application to handle This prevents long lockouts of other possibly higher priority interrupts and is considered good system design Figure B 3 page 216 shows a MicroBlaze interrupt flow without an interrupt controller and Figure B 4 page 216 shows a MicroBlaze interrupt flow with an interrupt controller Embedded System Tools Reference Manual www xilinx com 215 UG111 July 06 2011 Appendix B Interrupt Management XILINX INTR User Program microblaze_interrupt_handler c __interrupt_handler 0x000_0008 Branch to OS INTR handler user or peripheral interrupt handler function 0x000_00 10 Lookup the interrupt handler registered with the OS and jump to it 0x000_00 18 0x000_00 20 MB_InterruptVector Table User or peripheral interrupt handler registered directly with the OS layer X11019 Figure B 3 MicroBlaze Interrupt Flow without Interrupt Controller User Program microblaze_interrupt_handler c 0x000_0008 __interrupt_handler INTR Branch to OS xintc c 0x000_00 10 INTR handler N XIntc_DevicelnterruptHandler user or peripheral Lookup the J 0
72. mdm to connects to a MicroBlaze processor system This assumes the presence of mdm in the system The options can be specified in an options file and passed to the GenACE script The options syntax is described in Table 13 2 Table 13 2 Genace File Options Options Default Description lt Some Text gt none The line starting with is treated as a comment ace lt ACE_file gt none The output ACE file The file prefix should not match any input file bitstream elf data files prefix board lt board_type gt none This identifies the JTAG chain on the board Devices lt user gt lt supported_board_list gt IR length Debug device and so on The options are given with respect to the System ACE controller The script contains the options for some pre defined boards Board type options are user for user specific board You must also specify the configdevice and debugdevice option in the OPT file Refer to the genace opt file for details For a list of supported board types refer to Supported Target Boards in Genace tcl Script on page 182 configdevice none Configuration parameters for the device on the JTAG only for user board type chain devicenr Device position on the JTAG chain idcode ID code irlength Instruction Register IR length partname Name of the device The device position is relative to the System ACE device and these JTAG devices must be specified in the order i
73. monitor info might be available only in the console mode Table 11 1 Commonly Used GDB Console Commands Command load lt program gt Description Load the program into the target b main Set a breakpoint in function main c Continue after a breakpoint Note Do not use the run command 1 View a listing of the program at the current point n Steps one line stepping over function calls Step one line stepping into function calls stepi Step one assembly line info reg View register values info target View the number of instructions and cycles executed for the built in simulator only p lt xyz gt Print the value of xyz data hbreak main Set hardware breakpoint in function main watch lt gvar1 gt Set Watchpoint on Global Variable gvar1 rwatch lt gvarl gt Set Read Watchpoint on Global Variable gvar1 Additional Resources e GNU website http www gnu org e Red Hat Insight webpage http sources redhat com insight Embedded System Tools Reference Manual UG111 July 6 2011 www xilinx com 173 Chapter 11 GNU Debugger XILINX 174 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Chapter 12 Bitstream Initializer BitInit Overview Tool Usage Tool Options BitInit initializes the instruction memory of processors on the FPGA which is stored in
74. o final_system ace quit On some boards for example the ML561 the FPGA 1 DONI E pins are all connected together For these boards the FPGAs on the board must be configured with the hardware bitstream at the same time followed by software configuration The following are the steps to generate the ACE file for such an configuration This procedure uses an ML561 board as an example only Embedded System Tools Reference Manual www xilinx com UG111 July 6 2011 185 Chapter 13 System ACE File Generator GenACE XILINX To generate an SVF file for hardware configuration for all FPGAs 1 Create a SCR file impact_download scr with the following contents and invoke the impact batch impact_download scr command setMode cf setPreference pref KeepSVF True addCollection name Temp addDesign version 0 name config0O addDeviceChain index 0 setCurrentDeviceChain index 0 setCurrentCollection collection Temp setCurrentDesign version 0 addDevice position 1 file ML561_FPGA1_Download bit addDevice position 2 file ML561_FPGA2_ Download bit addDevice position 3 file ML561_FPGA3_Download bit generate quit This generates the SVF file config0 svf 2 Generate an SVF file for the software on the first FPGA device The options file contains the following jprog ace fpgal_sw ace board user configdevice devicenr 1 idcode 0x22a96093 irlength 10 partname xc5v1lx50t
75. on The options are given with respect to the System ACE controller The script contains the options for some pre defined boards You must specify the configdevice and debugdevice option in the OPT file Refer to the genace opt file for details For Supported board type refer to Supported Target Boards in Genace tcl Script on page 182 data lt data_file gt lt load_address gt none List of data binary file and its load address The load address can be in decimal or hex format 0x prefix needed If an SVF file is specified it is used elf lt list_of_Elf_Files gt none List of ELF files to download If an SVF file is specified it is used hw lt bitstream_file gt none The bitstream file for the system If an SVF file is specified it is used jprog true false false Clear the existing FPGA configuration This option should not be specified if performing runtime configuration Embedded System Tools Reference Manual www xilinx com 179 UG111 July 6 2011 Chapter 13 System ACE File Generator GenACE XILINX Table 13 1 genace tcl Script Command Options Cont d Options Default Description opt lt genace_options_file gt none GenACE options are read from the options file target lt target_type gt ppc_hw mdn ppc_hw Target to use in the system for downloading ELF or Data file Target types are ppc_hw to connect to a PowerPC 405 and 440 processor system
76. page 153 illustrates the MicroBlaze MDM target www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Connect Command Options Multiple MicroBlaze _ Processors OPB PLBv46 Bus 4q4 7 pr X10843 Figure 10 3 MicroBlaze MDM Target When no option is specified to the connect mb mdm XMD detects the JTAG cable automatically and chains the FPGA device containing the MicroBlaze MDM system If XMD is unable to detect the JTAG chain or the FPGA device automatically you can explicitly specify them using the following options Usage connect mb hw cable lt JTAG Cable options gt configdevice lt JTAG chain options gt debugdevice lt MicroBlaze options gt JTAG Cable Options and JTAG Chain Options For JTAG cable and chain option descriptions refer to Table 10 8 JTAG Cable Options on page 141 and Table 10 9 JTAG Chain Options on page 142 respectively Embedded System Tools Reference Manual www xilinx com 153 UG111 July 6 2011 Chapter 10 Xilinx Microprocessor Debugger XMD 154 MicroBlaze Options XILINX Table 10 13 describes the MicroBlaze options Table 10 13 MicroBlaze Options Option cpunr lt CPU Number gt Description Specific MicroBlaze processor number to be debugged in an FPGA containing multiple MicroBlaze processors connected to MDM The processor number starts from 1 devicenr lt MicroBlaze device positi
77. particular processor can access For more information about the libraries refer to the introductory section of the OS and Libraries Document Collection A link to the document is supplied in Appendix E Additional Resources lipsrc Directory The libsrc directory contains intermediate files and make files needed to compile the OSs libraries and drivers The directory contains peripheral specific driver files BSP files for the OS and library files that are copied from the EDK and your driver OS and library directories Refer to the Drivers page 80 OS Block page 81 and Libraries page 80 sections of this chapter for more information code Directory The code directory is a repository for EDK executables Libgen creates an xmdstub elf file for MicroBlaze on board debug in this directory Note Libgen removes these directories every time you run the tool You must put your sources executables and any other files in an area that you create Generating Libraries and Drivers 78 This section provides an overview of generating libraries and drivers The hardware specification file and the MSS files define a system For each processor in the system Libgen finds the list of addressable peripherals For each processor a unique list of drivers and libraries are built Libgen does the following for each processor e Builds the directory structure as defined in the Output Files page 77 e Copies the necessary source files for th
78. processors and ACE file is generated for processor number two The options file for this configuration is jprog hw implementation download bit ace system ace board user configdevice devicenr 1 idcode 0x1266093 irlength 14 partname XC2VP20 debugdevice devicenr 1 cpunr 2 lt Note The cpunr is 2 target ppc_hw elf executablel elf executable2 elf Multi Processor System Configuration The assumed configuration is with two PowerPC processors and a MicroBlaze processor each loaded with a single ELF file The board configuration is specified in the options file jprog hw implementation download bit ace system ace board user configdevice devicenr 1 idcode 0x1266093 irlength 14 partname XC2VP20 Options for PowerPC Processor 1 Target Type ELF files amp Data files debugdevice devicenr 1 cpunr 1 target ppc_hw elf executablel elf Options for PowerPC Processor 2 Target Type ELF files amp Data files debugdevice devicenr 1 cpunr 2 target ppc_hw elf executable2 elf Options for MicroBlaze Processor Target Type ELF files amp Data files debugdevice devicenr 1 cpunr 1 target mdm elf executable3 elf Note When multi processors are specified in an OPT file processor specific options such as target type ELF data files should follow debugdevice option for that processor The cpunr of the processor is inferred from debugdevice option 184 www xilinx com Embedded System Too
79. return 0 250 www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 XILINX Tcl Flow During Hardware Platform Generation UPDATE Procedure for a Parameter After System Level Analysis You can use the parameter subproperty SYSLEVEL_UPDATE_VALUE_PROC to specify the Tel procedure that computes the parameter value based on other parameters of the same IP The input handle is a handle to the parameter object of a particular instance of that IP Note that when this procedure is called system level parameters computed by Platgen for example C_NUM_MASTERS on a bus are already updated with the correct values MPD snippet PARAMETER C_PARAM1 5 SYSLEVEL_UPDATE_VALUE_PROC sysupdate_param1 Tcl snippet proc sysupdate_paraml param_handle set retval somehow_compute_param1 return S reetval UPDATE Procedure for the IP Instance After System Level Analysis You can use the OPTION SYSLEVEL_UPDATE_PROC to perform certain actions associated with a specific IP This procedure is associated with the complete IP and not with a specific parameter so it cannot be used to update the value of a specific parameter For example you can use this procedure to copy certain files associated with the IP ina particular directory The input handle is a handle to an instance of the IP MPD Snippet OPTION SYSLEVEL_UPDATE_PROC syslevel_update_proc Tcl snippet P
80. same flags as data and it must be mapped to initialized RAM got2 got This section contains pointers to program data the same flags as data and it must be mapped to initialized RAM eh frame This section contains frame unwind information for exception handling It contains the same flags as rodata and can be mapped to initialized ROM tbss This section holds uninitialized thread local data that contribute to the program memory image This section has the same flags as bss and it must be mapped to RAM tdata This section holds initialized thread local data that contribute to the program memory image This section must be mapped to initialized RAM gcc_except_ table This section holds language specific data This section must be mapped to initialized RAM ejer This section contains information necessary for registering compiled Java classes The contents are compiler specific and used by compiler initialization functions This section must be mapped to initialized RAM fixup This section contains information necessary for doing fixup such as the fixup page table and the fixup record table This section must be mapped to initialized RAM Linker Scripts The linker utility uses commands specified in linker scripts to divide your program on different blocks of memories It describes the mapping between all of the sections in all of the input object files to output sections in the executable file The output
81. shifter and multiplier Customizing Flash Programming Hardware incompatibilities flash command set incompatibilities or memory size constraints are considerations when programming flash This section briefly describes the flash programming algorithm so that if necessary you can plug in and replace elements of the flow to customize it for your particular setup When you click the Program Flash button and select a hardware platform project the following sequence of events occurs 1 A flash tcl file is written out to the lt hardware platform project gt settings folder This contains parameters that describe the flash programming session and is used by the flash programmer Tcl file 2 XPS launches XMD with the flash programmer Tel script executing it with a command suchas xmd nx hw lt hardware platform project gt system xml tcl flashwriter tcl lt hardware platform project gt settings flash tcl This flash programmer host Tcl comes from the installation You can replace the default lashwriter tcl with your own driver Tcl to run when you click the Program Flash button by placing a copy of the flashwriter tcl file in your lt hardware platform project gt tmp directory XMD searches for the specified file in your project directory before looking for it in the installation 3 The flash programmer Tel script copies the flash programmer application source files from the installation to the lt hardware platform project gt tmp fol
82. sys_clk reg sys_reset reg tx system dut sys_clk sys_clk sys_reset sys_reset rx exe stx A Ez J leds leds Embedded System Tools Reference Manual www xilinx com 71 UG111 July 6 2011 Chapter 7 Simulation Model Generator Simgen XILINX Clock generator for sys_clk initial begin sys_clk 1 b0 sys_clk_PHASE forever sys_clk_PERIOD 2 sys_clk sys_clk end Reset Generator for sys_reset initial begin sys_reset 1 b0 sys_clk_LENGTH sys_reset sys_reset end START USER CODE Do not remove this line User Put your stimulus here Code in this section will be not be overwritten END USER CODE Do not remove this line endmodule You can add your own Verilog code between the lines tagged BEGIN USER CODE and END USER CODE The code between these lines is maintained if simulation files are created again Any code outside these lines is lost if you create a new test bench External Memory Simulation Simgen provides simulation models for external memory and has automated support to instantiate memory models in the simulation testbench and performs connection with the design under test To compile memory model into the user library Simgen also generates simulator specific compilation elaboration commands into respective helper setup scripts Restrictions The restrictions on external memory simulation models are Supp
83. the Additional Resources page 261 16 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX EDK Overview GNU Compiler Tools GNU compiler tools GCC are called for compiling and linking application executables for each processor in the system Processor specific compilers are e The mb gcc compiler for the MicroBlaze processor e The powerpc eabi gcec compiler for the PowerPC processor As shown in the embedded tools architectural overview Figure 1 2 page 10 e The compiler reads a set of C code source and header files or assembler source files for the targeted processor e The linker combines the compiled applications with selected libraries and produces the executable file in ELF format The linker also reads a linker script which is either the default linker script generated by the tools or one that you have provided Refer to Chapter 9 GNU Compiler Tools Chapter 11 GNU Debugger and Appendix A GNU Utilities for more information about GNU compiler tools and utilities Xilinx Microprocessor Debugger You can debug your program in software using an Instruction Set Simulator ISS or ona board that has a Xilinx FPGA loaded with your hardware bitstream As shown in Figure 1 2 page 10 the Xilinx Microprocessor Debugger XMD utility reads the application executable ELF file For debugging on a physical FPGA XMD communicates over the same download cable as used to configure the F
84. the wrapper that invokes the main procedure Before invoking the main procedure it may invoke other initialization functions The _crtinit routine is supplied by the startup files described below ecrtinit o This is the default second stage C startup file This startup file performs the following steps 1 Clears the bss section to zero 2 Invokes _program_init 3 Invokes constructor functions _init 4 Sets up the arguments for main and invokes main Embedded System Tools Reference Manual www xilinx com 109 UG111 July 6 2011 Chapter 9 GNU Compiler Tools XILINX 5 6 Invokes destructor functions _ fini Invokes _program_clean and returns pgcrtinit o This second stage startup file is used during profiling This startup files performs the following steps Sn aT WYN a Clears the bss section to zero Invokes _program_init Invokes _profile_init to initialize the profiling library Invokes constructor functions _init Sets up the arguments for main and invokes main Invokes destructor functions _fini Invokes _profile_clean to cleanup the profiling library Invokes _program_clean and then returns sim crtinit o This second stage startup file is used when the mno clearbss switch is used in the compiler This startup file performs the following steps 1 2 3 4 5 Invokes _program_init Invokes constructor functions _init Sets up the arguments f
85. there is any error status returned by a DRC procedure Platgen captures the error and stops execution at an appropriate time UPDATE These procedures assume the system to be in a correct state and query the design data structure using Tcl APIs to compute the values of certain parameters The tool uses the string these procedures return to update the design with the Tcl computed value e The stage during hardware platform creation at which they are invoked IPLEVEL These procedures are invoked early in processing performed within the tools These procedures assume that no design analysis has been performed and therefore none of the system level information is available e SYSLEVEL These procedures are invoked later in processing when the tool has performed some system level analysis of the design and has updated certain parameters For a list of such parameters refer to the Reserved Parameters section of Chapter 2 Platform Specification Utility PsfUtility Also note that some parameters may be updated by Tcl procedures of IPs Such parameters are governed solely by IP Tcl and are therefore not listed in the MPD documentation Each Tcl procedure takes one argument The argument is a handle of a certain type in the data structure The handle type depends on the object type with which the Tcl procedure is associated Tcl procedures associated with parameters are provided with a handle to that par
86. to be stored in a compact flash device in a production system Flash Memory Programmer Allows you to use your target processor to program on board Common Flash Interface CFI compliant parallel flash devices with software and data Format Revision Tool and Version Management Wizard Updates the project files to the latest format The Version Management wizard helps migrate IPs and drivers created with an earlier EDK release to the latest version Platform Specification Utility PsfUtility and PSFZEDWARD The PsfUtility enables automatic generation of Microprocessor Peripheral Definition MPD files Program required to create an IP core compliant with EDK The psf2Edward is a command line program that converts a Xilinx Embedded Development Kit EDK project into Edward an internal XML format for use in programs such as the Software Development Kit SDK Microprocessor Peripheral Definition Translation tool MPDX The MPDxX is a translation tool that generates the IP XACT files on disk for the BSB repository Xilinx Platform Studio Xilinx Platform Studio XPS offers the following features e Ability to add processor and peripheral cores edit core parameters and make bus and signal connections to generate an MHS file e Support for tools described in Table 1 1 page 11 e Ability to generate and view a system block diagram and or design report e Project management support e Process and to
87. width Defines the DCR data width DCR_NUM_SLAVES Defines the number of DCR slaves on the bus LMB_AWIDTH Defines the LMB address width LMB_DWIDTH Defines the LMB data width C_ C C_ C C_DCR_DWIDTH C C_ cC C_ LMB_NUM_SLAVES Defines the number of LMB slaves on the bus Embedded System Tools Reference Manual UG111 July 6 2011 www xilinx com 25 26 Chapter 2 Platform Specification Utility PsfUtility XILINX Naming Conventions for Bus Interface Signals This section provides naming conventions for bus interface signal names The conventions are flexible to accommodate embedded processor systems that have more than one bus interface and more than one bus interface port per component When peripherals with more than one bus interface port are included in a design it is important to understand how to use a bus identifier As explained previously a bus identifier must be used for peripherals that contain more than one of the same bus interface The bus identifier must be attached to all associated signals and generics The names must be HDL compliant Additional conventions for IP peripherals are e The first character in the name must be alphabetic and uppercase e The fixed part of the identifier for each signal must appear exactly as shown in the applicable section below Each section describes the required signal set for one bus interface type e I
88. with a PLB slave interface and a PLB Master Slave interface such as gemac the command is psfutil hdl2mpd gemac prj lang vhdl top gemac bus plb s bus plb ms 0o gemac mpd For an example of an exclusive bus identifier to create an MPD specification for a peripheral with a PLB slave interface and a DCR Slave interface the command is psfutil hdl2mpd mem prj lang vhdl top mem bus plb s bus dcr s o mem prj Peripherals with Point to Point Connections Some peripherals such as multi channel memory controllers might have point to point connections BUS_STD XIL_ MEMORY CHANNEL BUS_TYPE TARGET Signal Naming Conventions The signal names must follow conventions such that all signals belonging to the point to point connection start with the same bus interface name prefix such as MCHO_ www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX DRC Checks in PsfUtility Invoking the PsfUtility with Point to Point Connections from Command Line You can specify point to point connections in the command line using the bus interface name as a prefix to the bus signals The command line for invoking PsfUtil is psfutil hdl2mpd lt hdlifile gt lang vhdl ver top lt top_entity gt p2pbus lt busif_name gt lt bus_std gt target initiator o lt mpdfile gt For example to create an MPD specification for a peripheral with an MCHO connection the command is psfutil hdl2mpd mch_m
89. 0 Xilinx Microprocessor Debugger XMD The Xilinx Microprocessor Debugger XMD is a tool that facilitates debugging programs and verifying systems using the PowerPC 405 or 440 processor or the MicroBlaze processor You can use it to debug programs on MicroBlaze or PowerPC 405 processors running on a hardware board cycle accurate Instruction Set Simulator ISS XMD provides a Tool Command Language Tcl interface This interface can be used for command line control and debugging of the target as well as for running complex verification test scripts to test a complete system XMD supports GNU Debugger GDB remote TCP protocol to control debugging of a target Some graphical debuggers use this interface for debugging including the PowerPC processor GDB and the MicroBlaze GDB powerpc eabi gdb and mb gdb and the Software Development Kit SDK the EDK Eclipse based software tool In either case the debugger connects to XMD running on the same computer or on a remote computer on the network XMD reads Xilinx Microprocessor Project the XMP system file to gather information about the hardware system on which the program is debugged The information is used to perform memory range tests determine MicroBlaze to Microprocessor Debug Module MDM connectivity for faster download speeds and perform other system actions Figure 10 1 page 124 shows the XMD targets Embedded System Tools Reference Manual www xilinx com 123 UG111
90. 00 r4 00000000 r12 00000000 r20 00000000 r28 00000000 r5 00000000 r13 00000140 r21 00000000 r29 00000000 r6 00000000 r14 00000000 r22 00000000 r30 00000000 r7 00000000 r15 00000064 r23 00000000 r31 00000000 pc 00000070 msr 00000004 lt Launching GDB from XMD console gt XMD start mb gdb microblaze_0 code executable elf XMD lt From GDB a connection is made to XMD and debugging is done from the GDB GUI gt XMD Accepted a new GDB connection from 127 0 0 1 on port 3791 XMD XMD GDB Closed connection XMD stp Embedded System Tools Reference Manual www xilinx com 155 UG111 July 6 2011 Chapter 10 Xilinx Microprocessor Debugger XMD XILINX BREAKPOINT at 114 F1440003 sbi rio r4 3 XMD dis 0x114 10 114 F1440003 sbi r10 r4 3 118 EOE30004 Ilbui r7 x3 4 11e E1030005 lbui r8 3 5 120 F0E40004 sbi ET Ta 4 124 F1040005 sbi r8 r4 5 128 B800FFCC bri 52 12C B6110000 rtsd riz 0 130 80000000 Or r0 r0 x0 134 B62E0000 rtid rid 0 138 80000000 Or r0 r ro XMD dow microblaze_0 code executable elf XMD con Info Processor started Type stop to stop processor RUNNING gt stop XMD Info User Interrupt Processor Stopped at 0x0000010c XMD con Info Processor started Type stop to stop processor RUNNING gt rrd pc pe 0x000000f4 lt With the MDM the current PC of MicroBlaze can be read while the program is running RUNNING gt rrd p
91. 06 2011 g XILINX Tcl Command Usage Tcl Command Usage General Conventions There are two kinds of Tcl APIs which differ based on the type of data they return Tcl APIs return either e Ahandle or a list of handles to some objects e A value or a list of values The common rules followed in all Tcl APIs are e AnAPI returns a NULL handle when an expected handle to another object is not found e An API returns an empty string when a value is either empty or that value cannot be determined Before You Begin When you use XPS in non GUI mode xps nw you must first initialize the internal tool database the runtime datastructure by loading the project with the xload command xload lt filetype gt lt filename gt MHS XMP Refer to Chapter 5 Command Line Mode for more detail regarding xload To gain access to either the MHS Handle or the merged MHS Handle use one of the following commands after loading the project XPS set original_mhs_ handle xget_handle mhs or XPS set merged_mhs_handle xget_handle merged_mhs The following section provides the nomenclature of the EDK Hardware Tcl commands in more detail Embedded System Tools Reference Manual www xilinx com 231 UG111 July 06 2011 Appendix C EDK Tcl Interface XILINX EDK Hardware Tcl Commands 232 Overview This section provides a list of Tcl APIs available in the EDK hardware data structure The description of these commands uses certa
92. 1 00000003 pe fffffffc msr 00000000 XMD mrd OxFFFFFFFC FFFFFFFC 4BFFFC74 XMD stp fffffc70 XMD stp fffffc74 XMD mrd 0xFFFFC000 5 FFFFCOOO 00000000 FFFFCOO4 00000000 FFFFCOO8 00000000 FFFFCOOC 00000000 FFFFCO1O 00000000 XMD mwr OxXFFFFCO04 Oxabcd1234 2 XMD mwr OxFFFFC0O10 0xa5a50000 XMD mrd OxFFFFCO0O00 5 FFFFCOOO 00000000 Embedded System Tools Reference Manual www xilinx com 145 UG111 July 6 2011 Chapter 10 Xilinx Microprocessor Debugger XMD XILINX FFFFC004 ABCD1234 FFFFC008 ABCD1234 FFFFCOOC 00000000 FFFFCO10 A5A50000 XMD XMD Example Connecting to PowerPC440 Processor Target To connect to the PowerPC 440 processor target use the connect ppc hw command XMD automatically detects the processor type and connects to the PowerPC 440 processor Use powerpc eabi gdb to debug software program remotely Refer to Chapter 11 GNU Debugger for more information about connecting the GNU Debugger to XMD XMD connect ppc hw JTAG chain configuration Device ID Code IR Length Part Name 1 5059093 16 XCF32P 2 5059093 16 XCF32P 3 59608093 8 xc95144x1 4 0a001093 8 System_ACE 5 032c6093 10 XCSVFX70T_U PowerPC440 Processor Configuration VELS LOM ye ia a EE oie eS Beles eee 0x7 21910 User ED 22 s428 5 obs we ak ee bee he bes 0x00 00000 No of PC Breakpoints 4 No of Read Addr Data Watchpoints 1 No of Write Addr Data Watchpoints 1 User Defined Address Map to acce
93. 13 a2c94315 r21 0080040e r29 fd0009f0 r6 51c6832a r14 45401007 r22 c1200004 r30 00000003 r7 a2c94315 r15 8a80200b r23 c2100008 r31 00000003 pc ffff0700 msr 00000000 XMD srrd pc ffff0700 msr 00000000 cr 00000000 lr ef0009f8 ctr ffffffff xer c000007f pvr 20010820 sprg0 ffffe204 sprg1 ffffe204 sprg2 ffffe204 sprg3 ffffe204 srr0 ffff0700 srr1l 00000000 tbl a06ea671 tbu 00000010 icdbdr 55000000 esr 88000000 dear 00000000 evpr ffff0000 tsr fc000000 tcr 00000000 pit 00000000 srr2 00000000 srr3 00000000 dbsr 00000300 dbcr0 81000000 iacl ffffe204 iac2 ffffe204 daci ffffe204 dac2 ffffe204 dcecr 00000000 iccr 00000000 zpr 00000000 pid 00000000 sgr ffffffff dewr 00000000 ccer0 00700000 dbcri 00000000 dvc1 ffffe204 dvc2 ffffe204 iac3 ffffe204 iac4 ffffe204 sler 00000000 sprg4 ffffe204 sprg5 ffffe204 sprg6 ffffe204 sprg7 ffffe204 su0r 00000000 usprg0 ffffe204 XMD rst Sending System Reset Target reset successfully XMD rwr 0 OxAAAAAAAA XMD rwr 1 0x0 XMD rwr 2 0x0 XMD rrd r0 aaaaaaaa r8 51 c6832a r16 00000804 r24 32a08800 rl 00000000 r9 a2c94315 r17 00000408 r25 31504400 r2 00000000 r10 00000003 r18 7c7dfcd r26 82020922 r3 d004340 r11 00000003 r19 fbcbefce r27 41010611 r4 0007a120 r12 51c6832a r20 0040080d r28 fe0006f0 r5 000b5210 r13 a2c94315 r21 0080040e r29 fd0009f0 r6 51c6832a r14 45401007 r22 c1200004 r30 00000003 r7 a2c94315 r15 8a80200b r23 c2100008 r3
94. 16 K e Non deterministic multiply cycles e Processor clock period and timer clock period of 5 ns 200 MHz www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Connect Command Options Table 10 11 lists the Local Memory Banks Table 10 11 Local Memory Banks Name Start Address Length Speed Mem0O 0x0 0x80000 0 Mem1 Oxfff80000 0x80000 0 Figure 10 3 illustrates a PowerPC processor ISS target TCP IP Socket Connection PowerPC Cycle_Accurate ISS405 icf ISS X10885 Figure 10 3 PowerPC Processor ISS Target Usage connect ppc sim icf lt Configuration File gt ipcport IP lt port gt Option Description icf Uses the given ISS configuration file instead of the default lt configuration file gt configuration file You can customize the PowerPC ISS features such as cache size memory address map and memory latency ipeport IP lt port gt Specifies the IP address and debug port of a PowerPC processor ISS that you have started XMD does not spawn a ISS you must start the ISS Embedded System Tools Reference Manual www xilinx com 149 UG111 July 6 2011 Chapter 10 Xilinx Microprocessor Debugger XMD XILINX Example Debug Session for PowerPC Processor ISS Target XMD connect ppc sim Instruction Set Simulator ISS PPC405 Version 1 9 1 76 c 1998 2005 IBM Corporation Waiting to connect to controlling in
95. 8 xc95144x1 PowerPC405 Processor Configuration VELSTON yc waik dae ave feat ete chine ae 0x20011430 USER Dorre ka tnia emna a ee ete ie desis ava aa a Se 0x00000000 No of PC Breakpoints 4 No of Read Addr Data Watchpoints 1 No of Write Addr Data Watchpoints 1 TSOCM sata Bente idea ceeded ede ve ays le Oxffffe000 Oxffffffff User Defined Address Map to access Special PowerPC Features using XMD I Cache Data 0x70000000 Ox70003fff I Cache TAG 0x70004000 0x70007fff D Cache Data 0x78000000 Ox78003fff D Cache TAG 0x78004000 0x78007fff DCR aoii ge eee bh eck ub he aus Oxab000000 OxabOOO0fff NIMS oe eared vad gto eae aa E 0x70004000 0x70007fff XMD stp ffffe2lic XMD stp ffffe220 XMD bps OxFFFFE218 Setting breakpoint at Oxffffe218 XMD con Processor started Type stop to stop processor RUNNING gt 8 Processor stopped at PC Oxffffe218 XMD XMD mrd 0xab000060 8 AB000060 00000000 AB000064 00000000 AB000068 FF000000 lt DCR register ISARC AB00006c 81000000 lt DCR register ISCNTL AB000070 00000000 AB000074 00000000 AB000078 FE000000 lt DCR register DSARC AB00007c 81000000 lt DCR register DSCNTL XMD Example Showing Special JTAG Chain Setup for Non Xilinx Devices This example demonstrates the use of the configdevice option to specify the JTAG chain on the board in the event that XMD is u
96. B BFM components are used to connect to their respective bus For each bus there are different model types For example the PLB bus has PLB Master PLB Slave and PLB Monitor BFM components The same set of components and more could exist for other busses or the functionality of BFM components could be combined into a single model Embedded System Tools Reference Manual www xilinx com 51 UG111 July 6 2011 Chapter 6 Bus Functional Model Simulation XILINX Bus Functional Language BFL The BFL describes the behavior of the BFM components You can specify how to initiate or respond to bus transactions using commands in a BFL file Bus Functional Compiler BFC The BFC translates a BFL file into the commands that actually program the selected Bus Functional Model Bus Functional Model Use Cases There are two main use cases for Bus Functional Models e IP verification e Speed Up simulation IP Verification When verifying a single piece of IP that includes a bus interface you concern yourself with the internal details of the IP design and the bus interactions It is inefficient to attach the IP to a large system only to verify that it is functioning properly Figure 6 1 shows an example in which a master BFM generates bus transactions to which the device under test responds The monitor BFM reports any errors regarding the bus compliance of the device under test Monitor BFM Slave Device Master BFM Under T
97. C_ISOCM_DCR_BASEADDR parameter on PowerPC 405 processors isocmstartadr lt ISOCM start address gt Start address for the Instruction Side On Chip Memory ISOCM Only for PowerPC 405 processor isocmsize lt ISOCM size in Bytes gt Size of the ISBRAM memory connected to the ISOCM interface Only for PowerPC 405 processor itagstartadr lt I Cache start address gt Start address for reading or writing the instruction cache tags romemstartadr lt ROM start address gt Start address of Read Only Memory This can be used to specify flash memory range XMD sets hardware breakpoints instead of software breakpoints romemsize lt ROM size in bytes gt Size of Read Only Memory ROM tlbstartadr lt TLB start address gt Start address for reading and writing the Translation Look aside Buffer TLB PowerPC Processor Target Requirements There are two possible methods for XMD to connect to the PowerPC processors over a JTAG connection The requirements for each of these methods are described in the following subsections Debug connection using the JTAG port of a Virtex FPGA If the JTAG ports of the PowerPC processors are connected to the JTAG port of the FPGA internally using the JTAGPPC primitive then XMD can connect to any of the PowerPC processors inside the FPGA as shown in the following figure Refer to the PowerPC 405 Processor Block Reference Guide and the PowerPC 440 Processor Blo
98. DR PORT mcbx_dram_clk DIR I IO_IF MCB_DDR2 IO_IS clk PORT mcbx_dram_clk_n DIR I IO_IF MCB_DDR2 IO_IS clk_n PORT mcbx_dram_cke DIR I IO_IF MCB_DDR2 IO_IS cke 204 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX XBD2 PORT mcbx_dram_odt DIR I IO_IF MCB_DDR2 IO_IS odt PORT mcbx_dram_ras_n DIR I IO_IF MCB _DDR2 IO_IS ras_n PORT mcbx_dram_cas_n DIR I IO_IF MCB_DDR2 IO_IS cas_n PORT mcbx_dram_we_n DIR I IO_IF MCB_DDR2 IO_IS we_n PORT mcbx_dram_ldm DIR I IO_IF MCB _DDR2 IO_IS ldm PORT mcbx_dram_udm DIR I IO_IF MCB _DDR2 IO_IS udm PORT mcbx_dram_ba DIR I VEC 2 0 IO_IF MCB_DDR2 IO_IS ba PORT mcbx_dram_addr DIR I VEC 12 0 IO_IF MCB _DDR2 IO_IS addr PORT mcbx_dram_dq DIR IO VEC 15 0 IO_IF MCB_DDR2 IO_IS dq PORT mcbx_dram_dqs DIR IO IO_IF MCB_DDR2 IO_IS dqs PORT mcbx_dram_dqs_n DIR IO IO_IF MCB_DDR2 IO_IS dqs_n PORT mcbx_dram_udqs DIR IO IO_IF MCB_DDR2 IO_IS udqs PORT mcbx_dram_udqs_n DIR IO IO_IF MCB_DDR2 IO_IS udqs_n PORT rzq DIR IO IO_IF MCB_DDR2 IO_IS rzq PORT zio DIR IO IO IF MCB_DDR2 IO_IS zio NOR FLASH IO_INTERFACE IO_IF Linear_Flash IO_TYPE xilinx com bsb_lib rt1l_busdefs flash_nor 1 0 PARAMETER Linea
99. Embedded System Tools Reference Manual EDK v13 2 UG111 July 6 2011 XILINX amp XILINX Xilinx is disclosing this user guide manual release note and or specification the Documentation to you solely for use in the development of designs to operate with Xilinx hardware devices You may not reproduce distribute republish download display post or transmit the Documentation in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Xilinx expressly disclaims any liability arising out of your use of the Documentation Xilinx reserves the right at its sole discretion to change the Documentation without notice at any time Xilinx assumes no obligation to correct any errors contained in the Documentation or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DOCUMENTATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING
100. I based IP that is in development Complete verification of these interfaces and protocol compliance is outside the scope of the AXI BFM solution for compliance testing and complete system level verification of AXI interfaces the Cadence AXI UVC can be used The AXI BFM solution is an optional product that is purchased separate from the ISE software Licensing is handled through the standard Xilinx licensing scheme A newlicense feature XILINX_AXI_BFM is needed in addition to the standard ISE license features A license is checked out at simulation run time While the Xilinx ISE software does not need to be running while the AXI BFM solution is in use the AXI BFM only operates on a computer that has the Xilinx software installed and licensed The BFM solution is encrypted using either the Verilog P1735 IEEE standard or a vendor specific encryption scheme To use the AXI BFM with Cadence IUS IES simulator products an export control regulation license feature is required Contact your Cadence sales office for more information See the AXI BFM User Guide UG783 and the AXI Bus Functional Model Data Sheet DS824 for more information The Appendix E Additional Resources contains a link to these documents Getting and Installing the Platform Studio BFM Package The use of the CoreConnect BFM components requires the acceptance of a license agreement For this reason the BFM components are not installed along with EDK Xilinx p
101. I gt SPLB_Rst in std_logic lt BI gt PLB_ABus in std_logic_vector 0 to C_ lt BI SPLB gt _AWIDTH 1 lt BI gt PLB_UABus in std_logic_vector 0 to C_ lt BI SPLB gt _AWIDTH 1 lt BI gt PLB_BE in std_logic_vector 0 to C_ lt BI gt PLB_DWIDTH 8 1 lt BI gt PLB_busLock in std_logic lt BI gt PLB_lockErr in std_logic lt BI gt PLB_masterID in std_logic_vector 0 to C_ lt BI SPLB gt _MID_WIDTH 1 lt BI gt PLB_PAValid in std_logic lt BI gt PLB_rdPendPri in std_logic_vector 0 to 1 lt BI gt PLB_wrPendPri in std_logic_vector 0 to 1 lt BI gt PLB_rdPendReq in std_logic lt BI gt PLB_wrPendReq in std_logic lt BI gt PLB_rdBurst in std_logic lt BI gt PLB_rdPrim in std_logic lt BI gt PLB_reqPri in std_logic_vector 0 to 1 lt BI gt PLB_RNW in std_logic lt BI gt PLB_SAValid in std_logic lt BI gt PLB_MSize in std_logic_vector 0 to 1 lt BI gt PLB_size in std_logic_vector 0 to 3 lt BI gt PLB_TAttribute in std_logic_vector 0 to 15 lt BI gt PLB_type in std_logic_vector 0 to 2 lt BI gt PLB_wrBurst in std_logic lt BI gt PLB_wrDBus in std_logic_vector 0 to C_ lt BI SPLB gt _DWIDTH 1 lt BI gt PLB_wrPrim in std_logic Examples PLB size in std_logic_vector 0 to 3 IPLB_size in std_logic_vector 0 to 3 DPORTO_PLB_ size in std_logic_vector 0 to 3 38 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Chapter 3 Psf2Edward Program
102. IF MCB_DDR2 IO_IS C_MEM_TRAS PARAMETER C_MEM_TRCD_ID 12500 DT STRING ASSIGNMENT CONSTANT IO_IF MCB_DDR2 IO_IS C_MEM_TRCD PARAMETER C_MEM_TRFC_ID 127500 DT STRING ASSIGNMENT CONSTANT IO_IF MCB_DDR2 IO_IS C_MEM_TRFC PARAMETER C_MEM_TRP_ID 12500 DT STRING ASSIGNMENT CONSTANT IO_IF MCB_DDR2 IO_IS C_MEM_TRP PARAMETER C_MEM_TRP_ID 12500 DT STRING ASSIGNMENT CONSTANT IO_IF MCB_DDR2 IO_IS C_MEM_TRP PARAMETER C_MEM_TYPE_ID DDR2 DT STRING ASSIGNMENT CONSTANT IO_IF MCB_DDR2 IO_IS C_MEM_TYPE PARAMETER C_MEM_BURST_LEN_ID 4 DT STRING ASSIGNMENT CONSTANT IO_IF MCB_DDR2 IO_IS C_MEM_ BURST_LEN PARAMETER C_MEM_CAS_LATENCY_ID 5 DT STRING ASSIGNMENT CONSTANT IO_IF MCB_DDR2 IO_IS C_MEM_CAS LATENCY PARAMETER C_MEM_ DDR2_RTT_ID 500HMS DT STRING ASSIGNMENT CONSTANT IO_IF MCB_DDR2 IO_IS C_MEM _DDR2_RTT PARAMETER C_MEM _DDR2_DIFF_DQS_EN_ID YES DT STRING ASSIGNMENT CONSTANT IO_IF MCB_DDR2 IO_IS C_MEM_DDR2_DIFF_DQS_EN PARAMETER C_MCB_RZQ_LOC_ID L6 DT STRING ASSIGNMENT CONSTANT IO_IF MCB_DDR2 IO_IS C_MCB_RZQ_ LOCPARAMETER C_MCB_ZIO_LOC_ID C2 DT STRING ASSIGNMENT CONSTANT IO_IF MCB_DDR2 IO_IS C_MCB_ZIO_LOCPARAMETER MEMORY_0_BASEADDR_ID 0x00000000 DT STRING ASSIGNMENT CONSTANT IO_IF MCB_DDR2 IO_IS MEMORY_0_BASEADDR PARAMETER MEMORY_0O_HIGHADDR_ID Ox07ffffff DT STRING ASSIGNMENT CONSTANT IO_IF MCB _DDR2 IO_IS MEMORY_0_HIGHAD
103. IP MPD snippet PARAMETER C_PARAM1 0 IPLEVEL_DRC_PROC drc_param1 Tcl snippet Argument param_handle points to C_PARAM1 since the Tcl is associated with C_PARAM1 proc drc_paraml param_handle set paramival xget_hw_value Sparam_handle if Sparamlval gt 5 error C_PARAM1 value should be less 5 return 1 else return 0 DRC Procedure for the IP Before System Level Analysis You can use the OPTION IPLEVEL_DRC_PROC to specify the Tcl procedure that performs this DRC The procedure should be used to perform DRCs at IPLEVEL for example consistency between two parameter values The DRCs performed here should be independent of how that IP has been used in the system MHS and should only use parameter bus interface and port settings used on that IP The input handle is a handle to an instance of the IP MPD Snippet OPTION IPLEVEL_DRC_PROC iplevel_drc BUS_INTERFACE BUS SPLB BUS_STD PLB BUS_TYPE SLAVE PORT MYPORT DIR I Tcl snippet proc iplevel_dre ipinst_handle set splb_handle xget_hw_busif_handle Sipinst_handle SPLB set splb_conn xget_hw_value splb_handle set myport_handle xget_hw_port_handle MYPORT set myport_conn xget_hw_value S myport_handle if splb_conn S myport_conn error Either busif SPLB or port MYPORT must be connected in the design return 1 else
104. July 6 2011 Chapter 10 Xilinx Microprocessor Debugger XMD XILINX GDB and Platform Studio SDK Manual debugger TCL Scripts External debugger GDB Remote XMD Socket protocol Interface GDB Remote Protocol Interface XMD Tcl Interface XMD Socket Interface Xilinx Microprocessor Debug XMD MicroBlaze ISS TCP Socket e ee ee eee Interface l l l l l R MicroBlaze XMDSTUB using PowerPC MicroBlaze on board Serial Interface PowerPC ISS MicroBlaze UP l l l l Hardware on board T a eee UG111_13_01_091905 Figure 10 1 XMD Targets XMD Usage xmd h help hw lt hardware_specification_file gt ipeport lt port_number gt nx opt lt optfile gt v xmp lt xmpfile gt tel lt tcl_file gt lt tcl_args gt Table 10 1 XMD Options Option Command Description Help h help Displays the usage menu and then quits Hardware Specification hw lt hw_spec_file gt Specifies the XML file that describes the hardware File components Port Number ipecport lt port_number gt Starts the XMD server at lt portnum gt Internal XMD commands can be issued over this TCP Port If lt port_number gt is not specified a default val ue 2345 is used No Initialization file nx Does not source xmd ini file on startup Option File opt lt connect_option_file gt Specifies the option file to use to connect to target The option file contains the XMD connect command to target 124 www xili
105. K es 9 0 5 E E E aus cae E ne biian bee aie 81 Additional Resources 0 0 t ent e eee eee aes 81 Chapter 9 GNU Compiler Tools OVEIVIEW sxiten Wiener rials a bread ta eee ees ee eke nad 83 Compiler Framework 0 506666 65 ced inek betas donb da eid be bedded debe 84 Common Compiler Usage and Options 00 e cee eee 85 MicroBlaze Compiler Usage and Options 0 0 0 cee eee 98 PowerPC Compiler Usage and Options 00 c cece eee eee 114 Other Notesin ae me rar rary eee wr eae mT aes ee 121 www xilinx com Embedded System Tools Reference Manual UG111 EDK v 13 2 July 6 2011 g XILINX Additional Resources 0 cece cece eee e nee e eee enneee Chapter 10 Xilinx Microprocessor Debugger XMD XMD US AGC sco xiaia tere ede dapd hice he nehe ds ik ede te eieatieeies XMD Console 0 0 nce tenn nee e eee eens XMD Command Reference 00 ccc cece eee etna XMD User Commands 00000 c ccc cette eens Connect Command Options 0 0 c cece eee eee XMD Internal Tcl Commands 000000 c cece eens Chapter 11 GNU Debugger MicroBlaze GDB Targets 0 0 0 0 cece cece ee eee PowerPC 405 Vareets lt iis0dsscssecvy ha iapid crete ceed akerit nie POwerr 44 Wate lS ps didnt apuh i a a a tenet EEES Console Mode 0 0 00 c ccc tenet e een e eee aes GDB Command Reference
106. M gt Prefix for the master input lt BI gt A bus identifier Optional for peripherals with a single master PLBV46 port and required for peripherals with multiple master PLBV46 ports For peripherals with multiple master PLBV46 ports the lt BI gt strings must be unique for each bus interface Trailing underline character _ in the lt BI gt string are ig nored PLB v4 6 Master Outputs For interconnection to the PLB v4 6 masters must provide the following outputs lt BI gt M_abort out std_logic lt BI gt M_ABus out std_logic_vector 0 to C_ lt BI MPLB gt _AWIDTH 1 lt BI gt M_UABus out std_logic_vector 0 to C_ lt BI MPLB gt _AWIDTH 1 lt BI gt M_BE out std_logic_vector 0 to C_ lt BI MPLB gt _DWIDTH 8 1 lt BI gt M_busLock out std_logic lt BI gt M_lockErr out std_logic lt BI gt M_MSize out std_logic lt BI gt M_priority out std_logic_vector 0 to 1 lt BI gt M_rdBurst out std_logic lt BI gt M_request out std_logic lt BI gt M_RNW out std_logic lt BI gt M_size out std_logic_vector 0 to 3 lt BI gt M_TAttribute out std_logic_vector 0 to 15 lt BI gt M_type out std_logic_vector 0 to 2 lt BI gt M_wrBurst out std_logic lt BI gt M_wrDBus out std_logic_vector 0 to C_ lt BI MPLB gt _DWIDTH 1 Examples IPLBM_request out std_logic Bridge_M_request out std_logic O020b_M_ request out std_logic PLB v4 6 Master Inputs Fo
107. PGA with a bitstream Refer to Chapter 10 Xilinx Microprocessor Debugger XMD for more information GNU Debugger The GNU Debugger GDB is a powerful yet flexible tool that provides a unified interface for debugging and verifying MicroBlaze and PowerPC processor systems during various development phases GDB uses Xilinx Microprocessor Debugger XMD as the underlying engine to communicate to processor targets Refer to Chapter 11 GNU Debugger for more information Simulation Library Compiler Compxlib The Compxlib utility compiles the EDK HDL based simulation libraries using the tools provided by various simulator vendors The Compxlib operates in both the GUI and batch modes In the GUI mode it allows you to compile the Xilinx libraries in your ISE installation using the libraries available in EDK For more information about Compxlib see Simulation Models in Chapter 7 and the ISE Command Line Tools User Guide For instructions on compiling simulation libraries refer to the Xilinx Platform Studio Help Embedded System Tools Reference Manual www xilinx com 17 UG111 July 6 2011 Chapter 1 Embedded System and Tools Architecture Overview XILINX 18 Bitstream Initializer Bitinit The Bitinit tool initializes the on chip block RAM memory connected to a processor with its software information This utility reads hardware only bitstream produced by the ISE tools system bit and outputs a new bitstream dow
108. PI_V1 xilinx com bsb_lib rtl_busdefs spi 1 0 XIL_SYSACE_V1 xilinx com bsb_lib rtl_busdefs sysace 1 0 XIL_TFT_V1 N A XIL_UART_V1 xilinx com bsb_lib rtl_busdefs uart 1 0 UART MPDX Given a Board MPD input file MPDX generates the IP XACT equivalent repository files for BSB BSB requires two IP XACT files to capture the design requirements One file is the RTL description of the IO interfaces that capture the port direction port width and port names The RTL filename is lt board gt xml Use the following command to generate the file mpdx mpd_data board ipx_data rtl board mpd The other file is BSB_Component xm1 which captures a high level representation of the system Use the following command to generate the file mpdx mpd_data board ipx data hurri board mpd 202 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX XBD2 Board MPD The following are detailed descriptions and examples of each element in the Board MPD On parameters and ports a logical to physical mapping is defined with the IO_IS and O_ F tags The mapping names are listed in the IP XACT description of the high level components Some naming conventions are listed here Parameter names lt interfaceName gt _paramName Port names lt interfaceName gt _portName IO_IF tag lt interfaceName gt The IO_IS is taken from the spirit id defined for the parameter within the high
109. PowerPC 405 and 440 processors Modifying Startup Files The initialization files are distributed in both pre compiled and source form with EDK The pre compiled object files are found in the compiler library directory Sources for the initialization files for the PowerPC compiler can be found in the lt XILINX_EDK gt sw 1ib ppc405 src directory where lt XILINX_EDK gt is the EDK installation area Any time you need a custom startup file requirement you can take the files from the source area and include them as a part of your application sources Alternatively they can be assembled into o files and placed in a common area To refer to the newly created object files instead of the standard files use the B directory name command line option while invoking powerpc eabi gcc To prevent the default startup files being used add nostartfiles on final compile line Note that the compiler standard CRT files for C support suchas ecrti oand crtbegin o are not provided with source code They are available in the installation to be used as is You might need to bring them in on your final link command if your code uses constructors and destructors Embedded System Tools Reference Manual www xilinx com 119 UG111 July 6 2011 Chapter 9 GNU Compiler Tools XILINX Reducing the Startup Code Size for C Programs If your application has stringent requirements on code size for C programs you can eliminate all sources of overhead This secti
110. Procedure for a Parameter Before System Level Analysis You can use the parameter subproperty IPLEVEL_UPDATE_VALUE_PROC to specify the Tel procedure that computes the parameter value based on other parameters on the same IP The input handle associates with the parameter object of a particular instance of that IP MPD snippet PARAMETER C_PARAM1 PARAMETER C_PARAM2 ll A Il oO H J EVEL_UPDATE_VALUE_PROC update_param2 Tcl computes value based on other parameters on the IP Argument param_handle points to C_PARAM2 because the Tcl is associated with C_PARAM2 proc update_param2 param_handle set retval 0 set mhsinst xget_hw_parent_handle S param_handle set paramlval xget_hw_param_value S mhsinst C_PARAM1 if Sparamlval gt 4 set retval 1 return Sretval Embedded System Tools Reference Manual www xilinx com 249 UG111 July 06 2011 Appendix C EDK Tel Interface XILINX DRC Procedure for a Parameter Before System Level Analysis You can use the parameter subproperty IPLEVEL_DRC_PROC to specify the Tcl procedure that performs DRCs specific to that parameter These DRCs should be independent of other PARAMETER values on that IP For example this DRC can be used to ensure that only valid values are specified for that parameter The input handle is a handle to the parameter object for a particular instance of that
111. R INSTANCE my_synch PARAMETER HW_VER 1 00 a PARAMETER C_NUM_SYNCH 3 PORT FROM_SYNCH_OUT synch0 amp synchl amp synch2 PORT TO_SYNCH_IN synch BFM Synchronization Bus Usage The BFM synchronization bus collects the SYNCH_OUT outputs of each BFM component in the design The bus output is then connected to the SYNCH_IN of each BFM component Figure 6 4 depicts an example for three BFMs and the MHS example above shows its instantiation for PLB v4 6 BFMs SYNCH_OUT SYNCH IN SYNCH_OUT SYNCH IN SYNCH_OUT SYNCH_IN FROM_SYNCH_OUT C_NUM_SYNCH 3 BFM Synch TO_SYNCH_IN X10850 Figure 6 4 BFM Synchronization Bus Usage Embedded System Tools Reference Manual www xilinx com 57 UG111 July 6 2011 Chapter 6 Bus Functional Model Simulation XILINX PLB Bus Functional Language Usage FILE sample bfl This test case initializes a PLB master Initialize my_master The following is a sample BFL file written for the PLB v4 6 BFM Component Instantiation page 56 which instantiate the PLB v4 6 BFM components Note The instance name for plb_master is duplicated in the path due to the wrapper level inserted by the tools set_device path system my_master my_master master device_type plb_master Configure as 64 bit master configure msize 01 Write and read 64 bit data using byte enable architecture mem_update addr ffff8000 data 00112233_ 44556677 me
112. RAMETER C_DCR_INTFCE 0 PORT PLB Clk sys_clk PORT SYS_Rst sys_reset END By i By BEGIN plb_bram_if_cntlr PARAMETER INSTANCE myplbbram_cntlr PARAMETER HW_VER 1 00 a PARAMETER C_BASEADDR OxFFFF8000 PARAMETER C_HIGHADDR OxXFFFFFFFF BUS_INTERFACE PORTA porta BUS_INTERFACE SPLB myplb END BEGIN bram_block PARAMETER INSTANCE bram1 PARAMETER HW_VER 1 00 a BUS_INTERFACE PORTA porta END 56 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Using the Platform Studio BFM Package BEGIN plbv46_master_bfm PARAMETER INSTANCE my_master PARAMETER HW_VER 1 00 a PARAMETER PLB MASTER _ADDR_LO_O OxFFFFO0O000 PARAMETER PLB MASTER _ADDR_HT_0O OxFFFFFFFF US_INTERFACE MPLB myplb ORT SYNCH_OUT synch0O ORT SYNCH_IN synch ND H u W wW BEGIN plbv46_slave_bfm PARAMETER INSTANCE my_slave PARAMETER HW_VER 1 00 a PARAMETER PLB_SLAVE_ADDR_LO_0 0xFFFF0000 PARAMETER PLB_SLAVE_ADDR_HI_0 OxXFFFF7FFF BUS_INTERFACE SPLB myplb PORT SYNCH_OUT synchl PORT SYNCH_IN synch END BEGIN plbv46_monitor_bfm PARAMETER INSTANCE my_monitor PARAMETER HW_VER 1 00 a BUS_INTERFACE MON_PLB myplb P P E D By By ORT SYNCH_OUT synch2 ORT SYNCH_IN synch ND BEGIN bfm_synch PARAMETE
113. RY in the parameters foreach mhsinst S mhsinsts Gets all parameters of the IP set params xget_hw_parameter_handle mhsinst Loop through each param and find tag ADDR_TYPE MEMORY foreach param params if Sparam 0 continue elseif Sparam continue set addrTypeValue xget_hw_subproperty_value Sparam ADDR_TYPE Found tag Add MhsInst to list and break to go to next MhsInst if string compare nocase SaddrTypeValue MEMORY 0 lappend ret_list mhsinst break return S ret_list Embedded System Tools Reference Manual www xilinx com 241 UG111 July 06 2011 242 Appendix C EDK Tcl Interface XILINX Advanced Write Access APIs Advance Write Access APIs modify the MHS object in memory These commands operate on the original MHS handle and handles obtained from the MHS handle The Write Access APIs can be used to create the project only They are disabled during the Platgen flow Advance Write Access Hardware API Summary The following table provides a summary of the Advance Write Access APIs To go to the API descriptions which are provided in the following section click on a summary link Table C 1 Hardware Advanced Write Access APIs Add Commands xadd_hw_hdl_srcfile lt ipinst_handle gt lt fileuse gt lt filename gt lt hdllang gt xadd_hw_ipinst_busif lt ipinst_handle gt lt busif_name gt lt busif_value gt xadd_hw_ipin
114. The AXI Interconnect has vectored parameters to capture the values of parameters Because the interconnect allows up to 16 masters and 16 slaves to be connected to it the value of each forms part of a vectored value Although it is possible to design a smart interface to capture the values of these parameters in a non vectored fashion it is inefficient to enter vectored values in the MHS by hand e IP information resides in a single location so you can view core details including some system level settings at one place in the MHS e When you need to move a core from one AXI Interconnect to another you need only to change the bus interface name on the core All AXI Interconnect related settings are preserved by the tools As long as the other AXI Interconnect is an AXI Interconnect with the same version you do not need to specify the settings again The IP Configuration dialog boxes of the end point IPs include the Interconnect Settings for BUSIF tab which captures the values of these parameters At runtime the XPS tools gather the values of these parameters from all the end point IPs and transfer them onto the AXI Interconnect 256 www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 g XILINX Building Vectors Building Vectors The AXI Interconnect allows a connection maximum of 16 masters and 16 slaves Additionally parameters on the interconnect that capture the values of the masters slaves connected to it
115. The mb as assembler generates imm instructions when large immediate values are used The assembly language programmer is never required to write code with imm instructions For more information on the MicroBlaze instruction set refer to the MicroBlaze Processor Reference Guide A link to the document is provided in Additional Resources page 261 The mb as assembler requires all MicroBlaze instructions with an immediate operand to be specified as a constant or a label If the instruction requires a PC relative operand then the mb as assembler computes it and includes an imm instruction if necessary www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX MicroBlaze Compiler Usage and Options For example the Branch Immediate if Equal beqi instruction requires a PC relative operand The assembly programmer should use this instruction as follows beqi r3 mytargetlabel where mytargetlabel is the label of the target instruction The mb as assembler computes the immediate value of the instruction as mytargetlabel PC If this immediate value is greater than 16 bits the mb as assembler automatically inserts an imm instruction If the value of mytargetlabel is not known at the time of compilation the mb as assembler always inserts an imm instruction Use the relax option of the linker remove any unnecessary imm instructions Similarly if an instruction needs a large constant as an operand the assembly
116. Usage watch watch r 0x400 0x1234 watch r w lt address gt lt data gt watch r 0x40X 0x12x4 watch r 0b01000000xXxxx 0b00010010XxXxx0100 watch r 0x40X Description Sets a read or write watchpoint at address If the value compares to data stop the processor Address and Data can be specified in hex 0x format or binary 0b format Don t care values are specified using X Addresses can be of contiguous range only Default value of data is OxXXXXXXXxX That is it matches any value For the PowerPC processor only absolute values are supported xload xload hw system xml xloadhw lt hw_spec_file gt Loads hardware specification XML file XMD reads the XML file to gather instruction and data memory address maps of the processor This information is used to verify the program and data downloaded to processor memory XPS generates the hardware specification file during the Export to SDK process Special Purpose Register Names MicroBlaze Special Purpose Register Names The following special register names are valid for MicroBlaze processors pe msr ear fsr btr pvr0 pvr2 pvr3 pvr4 pvr6 pvr7 pvr8 pvr10 pvril edr esr zpr pvrl zpr pvr5 zpr pvr9 pid For additional information descriptions and usage of MicroBlaze special register names refer to the Special Purpose Registers section of the MicroBlaze Architecture chapter in the MicroBlaze Processor Reference Guide A link to th
117. X Chapter 2 Platform Specification Utility Ps tility Tool Options Table 2 1 PsfUtility Syntax Options This chapter describes the features and the usage of the Platform Specification Utility PsfUtility tool that enables automatic generation of Microprocessor Peripheral Definition MPD files MPD files are required to create IP peripherals that are compliant with the Embedded Development Kit EDK The Create and Import Peripheral CIP wizard in the Xilinx Platform Studio XPS interface supports features provided by the PsfUtility for MPD file creation recommended Table 2 1 lists the PsfUtility Syntax options and their descriptions Option Command Description Single IP MHS template deploy_core Generate MHS Template that instantiates a single lt corename gt peripheral Suboptions are lt coreversion gt lp lt Library_Path gt Add one or more additional IP library search paths o lt outfile gt Specify output filename default is stdout Help h help Displays the usage menu and then exits HDL file to MPD hdl2mpd lt hdlfile gt Generate MPD from the VHDL Ver src prj file Suboptions are lang ver vhdl Specify language top lt design gt Specify top level entity or module name bus plbv46 axi4 axi4lite der 1mb fs1 m s ms mb lt busif_name gt Specify one or more bus interfaces for the peripheral p2pbus lt busif_name gt lt bus_std gt target initiat
118. XI4LITE Slave Inputs lt BI gt _AWADDR in std_logic_vector C_ lt BI gt _ADDR_WIDTH 1 downto 0 lt BI gt _AWVALID in std_logic lt BI gt _WDATA in std_logic_vector C_ lt BI gt _DATA_WIDTH 1 downto 0 lt BI gt _WSTRB in std_logic_vector C_ lt BI gt _DATA_WIDTH 8 1 downto 0 lt BI gt _WVALID in std_logic lt BI gt _BREADY in std_logic lt BI gt _ARADDR in std_logic_vector C_ lt BI gt _ADDR_WIDTH 1 downto 0 lt BI gt _ARVALID in std_logic lt BI gt _RREADY in std_logic Examples S_AXT_ARADDR in std_logic_vector C_S_AXT_ADDR_WIDTH 1 downto 0 S_AXI_ARVALID in std_logic S_AXI_RREADY in std_logic Embedded System Tools Reference Manual www xilinx com 31 UG111 July 6 2011 Chapter 2 Platform Specification Utility PsfUtility XILINX Slave DCR Ports Slave DCR ports must follow the naming conventions shown in Table 2 9 Note lf lt BrI gt is present lt S1n gt is optional Table 2 9 Slave DCR Port Naming Conventions lt Sin gt A meaningful name or acronym for the slave output lt S1n gt must not contain the string DCR upper lower or mixed case so that slave outputs are not confused with bus outputs lt nDCR gt A meaningful name or acronym for the slave input The last three characters of lt nDCR gt must contain the string DCR upper lower or mixed case lt BI gt A bus identifier Optional for peripherals with a single slave DCR por
119. XILINX Common Compiler Usage and Options The GNU compiler is named mb gcc for MicroBlaze and powerpc eabi gec for PowerPC The GNU compiler is a wrapper that calls the following executables Pre processor cpp0 This is the first pass invoked by the compiler The pre processor replaces all macros with definitions as defined in the source and header files Machine and language specific compiler This compiler works on the pre processed code which is the output of the first stage The language specific compiler is one of the following e C Compiler cc1 The compiler responsible for most of the optimizations done on the input C code and for generating assembly code e C Compiler cc1plus The compiler responsible for most of the optimizations done on the input C code and for generating assembly code Assembler mb as for MicroBlaze and powerpc eabi as for PowerPC processors The assembly code has mnemonics in assembly language The assembler converts these to machine language The assembler also resolves some of the labels generated by the compiler It creates an object file which is passed on to the linker Linker mb 1d for MicroBlaze and powerpc eabi 1d for PowerPC processors Links all the object files generated by the assembler If libraries are provided on the command line the linker resolves some of the undefined references in the code by linking in some of the functions from the assembler Executable options are described i
120. _TEXT_START_ADDR for MicroBlaze and _START_ADDR for PowerPC processors In special cases you might want to partition the various sections of your ELF file across different memories This is done using the linker command language refer to the Linker Scripts page 97 for details The following are some situations in which you might want to change the memory map of your executable e When partitioning large code segments across multiple smaller memories e Remapping frequently executed sections to fast memories e Mapping read only segments to non volatile flash memories No restrictions apply to how you can partition your executable The partitioning can be done at the output section level or even at the individual function and data level The resulting ELF can be non contiguous that is there can be holes in the memory map Ensure that you do not use documented reserved locations Alternatively if you are an advanced user and want to modify the default binary data provided by the tools for the reserved memory locations you can do so In this case you must replace the default startup files and the memory mappings provided by the linker Object File Sections An executable file is created by concatenating input sections from the object files o files being linked together The compiler by default creates code across standard and well defined sections Each section is named based on its associated meaning and purpose The vari
121. _list lt ipinst_handle gt lt portName gt xget_hw_port_handle lt handle gt lt port_name gt xget_hw_port_value lt handle gt lt port_name gt xget_hw_proj_setting lt prop_name gt xget_hw_proc_slave_periphs lt merged_proc_handle gt xget_hw_subproperty_handle lt property_handle gt lt subprop_name gt xget_hw_subproperty_value lt property_handle gt lt subprop_name gt xget_hw_value lt handle gt Hardware API Descriptions xget_hw_busif handle lt handle gt lt busif_name gt Description Returns a handle to the associated bus interface Arguments lt handle gt is the handle to the MPD original IP instance or merged IP instance lt busif_name gt is the name of the bus interface whose handle is required If lt busif_name gt is specified as an asterisk the API returns a list of bus interface handles To access an individual bus interface handle you can iterate over the list in Tcl Embedded System Tools Reference Manual www xilinx com 233 UG111 July 06 2011 Appendix C EDK Tel Interface XILINX xget_hw_ _busif value lt handle gt lt busif_name gt Description Returns the value of the specified bus interface The value is typically the instance name of the bus to which the bus interface is connected For a transparent bus interface the value is the connector which is not a bus instance name Arguments lt hand1le gt the handle to the MPD original IP instance or merged IP instance lt
122. _sw svf and fpga3_sw svf to final_system svef 6 Generate the ACE file by calling impact batch svf2ace scr Use the following SCR file svfi2ace wtck d i final_system svf o final_system ace quit Related Information CF Device Format To have the System ACE controller read the CF device do the following 1 Format the CF device as FAT16 2 Create a Xilinx sys file in the root directory This file contains the directory structure to use by the ACE controller Copy the generated ACE file to the appropriate directory For more information refer to the iMPACT section of the ISE Help Embedded System Tools Reference Manual www xilinx com 187 UG111 July 6 2011 Chapter 13 System ACE File Generator GenACE XILINX 188 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Chapter 14 Flash Memory Programming Overview You can program the following in flash e Executable or bootable images of applications e Hardware bitstreams for your FPGA e File system images data files such as sample data and algorithmic tables The executable or bootable images of applications is the most common use case When the processor in your design comes out of reset it starts executing code stored in block RAM at the processor reset location Typically block RAM size is only a few kilobytes or so and is too small to accommodate your entire software application image You can store your so
123. a bitstream is generated to configure the FPGA This bitstream includes initialization information for block RAM memories on the FPGA chip If your code or data must be placed on these memories at startup the Data2MEM tool in the ISE tool set updates the bitstream with code and data information obtained from your executable files which are generated at the end of the software application creation and verification flow Tool Requirements Set up your system to use the Xilinx Integrated Development System Verify that your system is properly configured Consult the release notes and installation notes for more information Embedded System Tools Reference Manual www xilinx com 41 UG111 July 6 2011 Chapter 4 Platform Generator Platgen Tool Usage Run Platgen as follows XILINX platgen p lt partname gt system mhs where platgen is the executable name p is the option to specify a part lt partname gt is the partname system mhs is the output file Tool Options Table 4 1 lists the supported Platgen syntax options Table 4 1 Platgen Syntax Options Option Command Description Help h help Displays the usage menu and then exits without running the Platgen flow Filename f lt filename gt Reads command line arguments and options from file Integration intstyle Indicates contextual information when invoking Xilinx applications Style ise default within a flow or project environ
124. a unit delay to avoid race conditions The clock to out delay for these synchronous components is 100 ps SIMPRIM Library The SIMPRIM Library is used for timing simulation It includes all the Xilinx primitives library components used by Xilinx implementation tools Timing simulation models generated by Simgen instantiate SIMPRIM library components XilinxCoreLib Library The Xilinx CORE Generator software is a graphical Intellectual Property IP design tool for creating high level modules like FIR Filters FIFOs CAMs and other advanced IP You can customize and pre optimize modules to take advantage of the inherent architectural features of Xilinx FPGA devices such as block multipliers SRLs fast carry logic and on chip single or dual port RAM The CORE Generator software HDL library models are used for behavioral simulation You can select the appropriate HDL model to integrate into your HDL design The models do not use library components for global signals Xilinx EDK Library The EDK library is used for behavioral simulation It contains all the EDK IP components precompiled for ModelSim SE and PE or Cadence Incisive Enterprise Simulator IES This library eliminates the need to recompile EDK components on a per project basis minimizing overall compile time The EDK IP components library is provided for VHDL only and can be encrypted The Xilinx Compxlib utility deploys compiled models for EDK IP components into a common
125. able instruction workarounds and usage of libraries targeted for the 440 processor mfpu sp lite sp full dp_lite dp full none Generate hardware floating point instructions to use with the Xilinx PowerPC processor APU FPU coprocessor hardware The instructions and code output follow the floating point specification in the PowerPC Book E with some exceptions tailored to the APU FPU hardware Book E is available from the IBM web page Refer to the FPU hardware documentation for more information on the architecture Links to Book E and to the FPU documentation are available in Additional Resources page 261 The option given to mfpu determines which variant of the FPU hardware to target The variants are as follows sp_lite Produces code targeted to the Single precision Lite FPU coprocessor This version supports only single precision hardware floating point and does not use hardware divide and square root instructions The compiler automatically defines the C preprocessor definition HAVE_XFPU_SP_LITE when this option is given sp_full Produces code targeted to the Single precision Full FPU coprocessor This version supports only single precision hardware floating point and uses hardware divide and square root instructions The compiler automatically defines the C preprocessor definition HAVE_XFPU_SP_FULL when this option is given 114 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX PowerPC
126. aints The BSB reads IP XACT natively when targeting Advanced eXtensible Interface AXI designs The IP XACT based board file set is referenced as XBD2 XBD2 models the FPGA device in IP XACT as a component XML description which defines the interfaces available on the board This allows designers familiar with IP XACT to define a data driven mechanism leveraging the BSB system data to assemble designs For board designers not familiar with IP XACT the board description can be captured in an ASCII text file similar to the Microprocessor Peripheral Definition MPD format defined to capture a pcore description This MPD file is known as the Board MPD It includes a translation tool MPDX which generates the IP XACT files on disk for the BSB repository Constraints are captured in a Comma Separated Value CSV file and a Tcl file that you provide EDK provides the CSV file to capture pin constraints and the Tcl file to capture more complex constraints such as timing constraints Note Throughout the document any reference to Board MPD is the input to MPDxX translation tool and reference to XBD2 IP XACT is the output of MPDX The XBD2 file contains a number of spirit busInterface elements each corresponding to a hardware module on the board The type of the module is specified using the VLNV reference of the spirit busDefinition The VLNV string is used to match an IP that can communicate with this module Table 16 1 page 202 defines th
127. al structural and timing simulation methods refer to the Platform Studio Online Help Simulation Libraries EDK simulation netlists use low level hardware primitives available in Xilinx FPGAs Xilinx provides simulation models for these primitives in the libraries listed in this section The libraries described in the following sections are available for the Xilinx simulation flow The HDL code must refer to the appropriate compiled library The HDL simulator must map the logical library to the physical location of the compiled library Xilinx ISE Libraries ISE provides the following libraries for simulation e UNISIM Library e SIMPRIM Library e XilinxCoreLib Library Embedded System Tools Reference Manual www xilinx com 61 UG111 July 6 2011 Chapter 7 Simulation Model Generator Simgen XILINX UNISIM Library The UNISIM Library is a library of functional models used for behavioral and structural simulation It includes all of the Xilinx Unified Library components that are inferred by most popular synthesis tools The UNISIM library also includes components that are commonly instantiated such as I Os and memory cells You can instantiate the UNISIM library components in your design VHDL or Verilog and simulate them during behavioral simulation Structural simulation models generated by Simgen instantiate UNISIM library components Asynchronous components in the UNISIM library have zero delay Synchronous components have
128. al documents are linked below e EDK Concepts Tools and Techniques UG683 http www xilinx com support documentation sw_manuals xilinx13_2 edk_ctt pdf Note The accompanying design files are in edk_ctt zip e Embedded System Tools Reference Manual UG111 http www xilinx com support documentation sw_manuals xilinx13_2 est_rm pdf e Platform Specification Format Reference Manual UG642 http www xilinx com support documentation sw_manuals xilinx13_2 psf_rm pdf e EDK Profiling Guide UG448 http www xilinx com support documentation sw_manuals xilinx13_2 edk_prof pdf e PowerPC 405 Processor Block Reference Guide UGO018 http www xilinx com support documentation user_guides ug018 pdf Embedded System Tools Reference Manual www xilinx com 261 UG111 July 06 2011 Appendix E Additional Resources XILINX PowerPC 405 Processor Reference Guide UGO011 http www xilinx com support documentation user_guides ug011 pdf PowerPC 440 Embedded Processor Block in Virtex 5 FPGAs UG200 http www xilinx com support documentation user_guides ug200 pdf MicroBlaze Processor User Guide UG081 http www xilinx com support documentation sw_manuals xilinx13_2 mb_ref_guide pdf SDK Help XPS Help EDK Additional Resources 262 Xilinx Platform Studio and EDK website http www xilinx com ise embedded_design_prod platform_studio htm Xilinx Platform Studio and EDK Document website http www xil
129. ame gt ppc ormicroblaze lt processor_name gt powerpc eabi or microblaze and lt platform gt linornt To use a linker script provide it on the GCC command line Use the command line option T lt script gt for the compiler as described below compiler T lt linker_script gt lt Other Options and Input Files gt If the linker is executed on its own include the linker script as follows linker T lt linker_script gt lt Other Options and Input Files gt This tells GCC to use your linker script in the place of the default built in linker script Linker scripts can be generated for your program from within XPS and SDK In XPS or SDK select Tools gt Generate Linker Script This opens up the linker script generator utility Mapping sections to memory is done here Stack and Heap size can be set as well as the memory mapping for Stack and Heap When the linker script is generated it is given as input to GCC automatically when the corresponding application is compiled within XPS or SDK Linker scripts can be used to assign specific variables or functions to specific memories This is done through section attributes in the C code Linker scripts can also be used to assign specific object files to sections in memory These and other features of GNU linker scripts are explained in the GNU linker documentation which is a part of the online binutils manual A link to the GNU manuals is supplied in the Additional Resources o
130. ameter as an argument www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 g XILINX Tcl Flow During Hardware Platform Generation Tcl procedures associated with the IP itself are provided with a handle toa particular instance of the IP used in the design as an argument The following is a list of the Tcl procedures that can be called for an IP instance Note The MPD tag name that specifies the Tcl procedure name indicates the category to which the Tcl procedure belongs Each of the following tags is a name value pair in the MPD file where the value specifies the Tcl procedure associated with that tag You must ensure that sucha Tcl procedure exists in the Tcl file for that IP e Tool specific Tel calls e You can specify calls specific to either Platgen or Simgen Order of Execution for Tcl Procedures in the MPD The Tcl procedures specified in the MPD are executed in the following order during hardware platform generation IPLEVEL_UPDATE_VALUE_PROC on parameters IPLEVEL_DRC_PROC on parameters IPLEVEL_DRC_PROC on the IP specified on options SYSLEVEL_UPDATE_VALUE_PROC on parameters SYSLEVEL_UPDATE_PROC on the IP specified on options SYSLEVEL_DRC_PROC on parameters ports SYSLEVEL_DRC_PROC on the IP specified on options FORMAT_PROC on parameters Cen aor YN a Helper core Tcl Procedures UPDATE
131. and Options L directory Add directory to library search path I directory Add directory to header search path 1 library Search library for undefined symbols Note The compiler prefixes lib to the library name indicated in this command line switch Library Search Options 1 libraryname By default the compiler searches only the standard libraries such as libc libm and libxil You can also create your own libraries You can specify the name of the library and where the compiler can find the definition of these functions The compiler prefixes 1ib to the library name that you provide The compiler is sensitive to the order in which you provide options particularly the 1 command line switch Provide this switch only after all of the sources in the command line For example if you create your own library called libproject a you can include functions from this library using the following command Compiler Source Files L LIBDIR 1 project Caution If you supply the library flag 1 1ibrary_name before the source files the compiler does not find the functions called from any of the sources This is because the compiler search is only done in one direction and it does not keep a list of available libraries L Lib Directory This option indicates the directories in which to search for the libraries The compiler has a default library search path where it looks for the standard library Using the L option you can in
132. and Software Configuration The options file for hardware and software configuration is jprog hw implementation download bit ace system ace board m1501 target mdm elf executablel elf executable2 elf Hardware and Software Partial Reconfiguration The options file for hardware and software partial reconfiguration is hw implementation download bit ace system ace board m1501 target mdm elf executablel elf executable2 elf Hardware Only Configuration The options file for hardware only configuration is jprog hw implementation download bit ace system ace board m1401 Hardware Only Partial Reconfiguration The options file for hardware only partial reconfiguration is hw implementation download bit ace system ace board m1501 Software Only Configuration The options file for software only configuration is jprog ace system ace board m1501 target mdm elf executablel elf Embedded System Tools Reference Manual www xilinx com 183 UG111 July 6 2011 Chapter 13 System ACE File Generator GenACE XILINX Generating ACE for a Single Processor in Multi Processor System Many of the Virtex family designs contain two PowerPC processors 405 and 440 or the system might contain multiple MicroBlaze processors To generate an ACE file for a single processor use debugdevice option Use cpunr to specify the processor instance In the example we assume a configuration with two PowerPC
133. arget using the connect mb mdm command At the end of the session mb gdb connects to XMD using the GDB remote target Refer to Chapter 11 GNU Debugger for more information about connecting GDB to XMD XMD connect mb mdm JTAG chain configuration Device ID Code IR Length Part Name 1 0a001093 8 System_ACE 2 5059093 16 XCF32P 3 01e58093 10 XC4VFX12 4 49608093 8 xc95144x1 MicroBlaze Processor Configuration VOLS LOM s gara ai aeaa Bodh ae anaes oats wks 7 00 a Opt Satlon ec sesse bk ee oe ee E i Performance TINCSKRCONNE CE sinks secsndcsasadeduseed a aoe sacs eeane PLBv46 No of PC Breakpoints 3 No of Read Addr Data Watchpoints 1 No of Write Addr Data Watchpoints 1 Exceptions Support off FPU Supports s ceneg caked Gee E ae oS off Hard Divider Support off Hard Multiplier Support on Mul32 Barrel Shifter Support off MSR clr set Instruction Support on Compare Instruction Support on PVR SUPPOLE SOS secese eed arate 4 eaae on PVR Configuration Type Base Connected to MDM UART Target Connected to mb target id 0 Starting GDB server for mb target id 0 at TCP port no 1234 XMD rrd rO 00000000 r8 00000000 r16 00000000 r24 00000000 r1 00000510 r9 00000000 r17 00000000 r25 00000000 r2 00000140 r10 00000000 r18 00000000 r26 00000000 r3 a5a5a5a5 r11 00000000 r19 00000000 r27 000000
134. arting address 150 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Connect Command Options Cache Word Access The cache entries are mapped to the address space in a way by way manner Using the provided example if the cache line size is 32 byte and each way has 16 sets then 0x70000000 0x700001FF is mapped to I Cache way 0 and 0x70000200 0x700003FF is mapped to I Cache way 1 Cache Tag and Parity Access The cache tag address space contains the tag status and parity information of the cache entries for the corresponding cache address space In the provided example the tag information for I Cache entry at 0x70000100 is available at 0x70008100 and the tag information for the D Cache entry at 0x78000600 is available at 0x78008600 The PowerPC 405 processor uses one word to store the tag and status of one cache line and one word to store parities The PowerPC 440 processor also uses two words first word is tag low and second word is tag high to store the tag of one cache line For more information on how to translate the tag bits refer to the icread and dcread instructions in the respective PowerPC405 User Manual or PowerPC440 User Manual A link to these documents can be found in Appendix E Additional Resources Because the cacheline size is 32 bytes the tag values repeat within the same cacheline DCR Address Spaces Although the DCR bus is not in the same address domain as the PLB bus y
135. ble different reset types specify debugconfig reset_on_data_dow processor enable debugconfig reset_on_data_dow system enable To disable reset specify debugconfig reset_on_data_dow disable run_poll_interval lt time in millisec gt When the processor is run using either the run or con command XMD monitors the processor state at regular intervals 100 ms If you want XMD to poll less frequently use this option to specify the poll interval Embedded System Tools Reference Manual UG111 July 6 2011 www xilinx com 161 Chapter 10 Xilinx Microprocessor Debugger XMD XILINX Configuring Instruction Step Modes XMD supports two instruction step modes You can use the debugconfig command to select between the modes The two modes are e Instruction step with interrupts disabled This is the default mode In this mode the interrupts are disabled e Instruction step with interrupts enabled In this mode the interrupts are enabled during step operation XMD sets a hardware breakpoint at the next instruction and executes the processor If an interrupt occurs it is handled by the registered interrupt handler The program stops at the next instruction Note The instruction memory of the program should be connected to the processor d side interface XMD debugconfig Debug Configuration for Target 0 Step Mode cs ts e is arasi Rae See bel Interrupt Disabled Memory Data Width Matching Disa
136. bled XMD debugconfig step_mode enable interrupt XMD debugconfig Debug Configuration for Target 0 Step MOdEG 5 sa db cae Bn Be as Interrupt Enabled Memory Data Width Matching Disabled Configuring Memory Access XMD supports handling different memory data width accesses The supported data widths are word 32 bits half word 16 bits and Byte 8 bits By default XMD uses appropriate data width accesses when performing memory read and write operations You can use the debugconfig command for configuring XMD to match the data width of the memory operation This is usually necessary for accessing flash devices of different data widths XMD debugconfig Debug Configuration for Target 0 Step Mod s siesena enia a e Interrupt Disabled Memory Data Width Matching Enabled XMD debugconfig memory_datawidth_matching disable XMD debugconfig Debug Configuration for Target 0 Step MOG 2c dis es soe be sra i p ener na Interrupt Disabled Memory Data Width Matching Disabled Configuring Reset for Multiprocessing Systems By default XMD performs a system reset upon download of a program to a processor This behavior ensures a clean processor state before running the program However in multiprocessing systems downloading and running programs to the various processors happens in sequence 162 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX XMD Internal Tcl Commands Depending up
137. bles this configuration To compile a BFL file type the following at a command prompt For ModelSim xilbfc s mti sample bfl For ISim xilbfc s isim sample bfl This creates a script targeted for the selected simulator that initializes the BFM devices In the case of ModelSim it creates a file called sample do In the case of ISim it creates a file called sample tcl To run the BFM simulation you must Sy Oo BS Compile the simulation HDL files Load the system into the simulator Initialize the Bus Functional Models Optionally create a waveform list or load a previously created one Provide the clock and reset stimulus to the system Run the simulation Embedded System Tools Reference Manual UG111 July 6 2011 www xilinx com 59 Chapter 6 Bus Functional Model Simulation XILINX ModelSim Example The following is an example ModelSim script called run do that you can write to perform the BFM simulation steps do system do vsim system do sample do do wave do force freeze sim system sys_clk 1 0 0 10 ns r 20 ns force freeze sim system sys_reset 0 1 200 ns run 2 us Note If your design has an input reset that is active high replace the reset line with force freeze sim system sys_reset 1 0 200 ns At the ModelSim prompt type do run do Questa Example The following is an example Questa script called that you can write to perform the BFM simulation steps Need exam
138. build a runtime data structure of your design The data structure contains information about user design files such as Microprocessor Hardware Specification MHS or library data files such as Microprocessor Peripheral Definition MPD Microprocessor Driver Definition MDD and Microprocessor library Definition MLD Access to the data structure is given as Tcl APIs Based on design requirements IP driver library and OS writers that provide the corresponding data files can access the data structure information to add some extra steps in the tools processing EDK tools also use Tool Command Language Tcl to perform various Design Rule Checks DRCs and to update the design data structure in a limited manner Understanding Handles The tools provide access points into the data structure through a set of API functions Each API function requires an argument in the form of system information which is called a handle For example an IP defined in the Microprocessor Hardware Specification MHS file could serve as a handle Handles can be of various types based on the kind of data to which they are providing access Data types include instance names driver names hardware parameters or hardware ports From a given handle you can get information associated with that handle or you can get other associated handles Embedded System Tools Reference Manual www xilinx com 229 UG111 July 06 2011 Appendix C EDK Tcl Interface XILINX
139. busif_name gt is the name of the bus interface whose value is required xget_hw_bus_ slave_addrpairs lt merged_bus_handle gt Description Returns a list of slave addresses associated with the specified bus handle The returned value is a list of integers where The first value is the base address of any connected peripherals The second value is the associated high address The following values are paired base and high addresses of other peripherals Arguments lt merged_bus_handle gt is a handle to a merged IP instance pointing to a bus instance xget_hw_connected_busifs_ handle lt merged_mhs_handle gt lt businst_name gt lt busif_type gt Description Returns a list of handles to bus interfaces that are connected to a specified bus Arguments lt merged_mhs_handle gt is a handle to the merged MHS lt businst_name gt is the name of the connected bus instance lt busif_type gt is one of the following MASTER SLAVE TARGET INITIATOR ALL xget_hw_ connected _ports_ handle lt merged_mhs_handle gt lt connector_name gt lt port_type gt Description Returns a list of handles to ports associated with a specified connector The valid handle type is the merged MHS Arguments lt merged_mhs_hand1e gt is the handle to the merged MHS lt connector_name gt is the name of the connector lt port_type gt is source sink or all This API returns a list of handles to ports based on the lt port_type gt w
140. c pe 0x00000110 lt Note the PC is constantly changing as the program is running RUNNING gt stop Info Processor started Type stop to stop processor XMD rrd rO 00000000 r8 00000065 r16 00000000 r24 00000000 r1 00000548 r9 0000006c r17 00000000 r25 00000000 r2 00000190 r10 0000006c r18 00000000 r26 00000000 r3 0000014c r11 00000000 r19 00000000 r27 00000000 r4 00000500 r12 00000000 r20 00000000 r28 00000000 r5 24242424 r13 00000190 r21 00000000 r29 00000000 r6 0000c204 r14 00000000 r22 00000000 r30 00000000 r7 00000068 r15 0000005c r23 00000000 r31 00000000 pe 0000010c msr 00000000 XMD bps 0x100 Setting breakpoint at 0x00000100 XMD bps 0x11c hw Setting breakpoint at 0x0000011c XMD bpl SW BP addr 0x00000100 instr 0xe1230002 lt Software Breakpoint HW BP BP_ID 0 addr 0x0000011c lt Hardware Breakpoint XMD con Info Processor started Type stop to stop processor RUNNING gt Processor stopped at PC 0x00000100 Info Processor stopped Type start to start processor XMD con Info Processor started Type stop to stop processor RUNNING gt Info Processor started Type stop to stop processor 156 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Connect Command Options MicroBlaze Stub Hardware Target To connect to a MicroBlaze target use the XMDStub a ROM monitor running on the targ
141. ch simgen will create a test bench which will instantiate the top level design and will create default stimulus for clock and reset signals Clock stimulus is inferred from any global port which is tagged SIGIS CLK in the MHS file The frequency of the clock is given by the CLK_FREQ tag The phase of the clock is given by the CLK_PHASE tag which takes values from 0 to 360 Embedded System Tools Reference Manual www xilinx com 69 UG111 July 6 2011 Chapter 7 Simulation Model Generator Simgen XILINX Reset stimulus is inferred for all global ports tagged SIGIS RST in the MHS file The polarity of the reset signal is given by the RST_POLARITY tag The length of the reset is given by the RST_LENGTH tag For more information about the clock and reset tags refer to the Platform Studio Online Help library IEEE VHDL Test Bench Example use IEEE STD_LOGIC_1164 ALL library UNISIM use UNISIM VCOMPONENTS ALL entity system_tb is end system_tb architecture STRUCT constant sys_clk_PERIOD time constant sys_reset_LENGTH time URE of system_tb is 10 ns 160 ns constant sys_clk_PHASE time 2 5 ns component system is port sys_clk sys_reset in std_logic in std_logic rx in std_logic tx out std_logic leds inout std_logic_vector 0 to 3 i end component Internal signals signal leds begin dut system port
142. ck Reference Guide for more information A link to the document is supplied in Appendix E Additional Resources Debug connection using I O pins connected to the JTAG port of the PowerPC Processor If the JTAG ports of the PowerPC processors are brought out of the FPGA using I O pins then XMD can directly connect to the PowerPC processor for debugging In this mode XMD can only communicate with one PowerPC processor If there are two PowerPC processors in your system you cannot chain them and the JTAG ports to each processor should be brought out to use FPGA I O pins Refer to the PowerPC 405 Processor Block Reference Guide and the PowerPC 440 Processor Block Reference Guide for more information about this debug setup A link to the document is supplied in Appendix E Additional Resources Figure 10 2 page 144 illustrates the PowerPC processor target Embedded System Tools Reference Manual UG111 July 6 2011 www xilinx com 143 Chapter 10 Xilinx Microprocessor Debugger XMD XILINX XMD JTAG FPGA PowerPC JTAG signals UG111_13_02_072407 Figure 10 2 PowerPC Processor Target Example Debug Sessions Example Using a PowerPC 405 Processor Target The following example demonstrates a simple debug session with a PowerPC 405 processor target Basic XMD based commands are used after connecting to the PowerPC processor target using the connect ppc hw command At the end of the session powerpc eabi gdb is connect
143. cl This file uses the parameters configured in the MSS file for a driver OS or library to generate data Data generated includes but is not limited to generation of header files C files running DRCs for the driver OS or library and generating executables The Tel file includes procedures that Libgen calls at various stages of its execution Various procedures in a Tcl file include e DRC The name of DRC given in the MDD or MLD file generate A Libgen defined procedure that is called after files are copied e post_generate A Libgen defined procedure that is called after generate has been called on all drivers OSs and libraries e execs generate A Libgen defined procedure that is called after the BSPs libraries and drivers have been generated Note The data generation Tcl file is not necessary for a driver OS or library For more information about the Tcl procedures and MDD MLD related parameters refer to the Microprocessor Driver Definition MDD and Microprocessor Library Definition MLD chapters in the Platform Specification Format Reference Manual A link to the document is supplied in Appendix E Additional Resources MSS Parameters For a complete description of the MSS format and all the parameters that MSS supports refer to the Microprocessor Software Specification MSS chapter in the Platform Specification Format Reference Manual A link to the document is supplied in Appendix E Additio
144. clude some additional directories in the compiler search path Header File Search Option I Directory Name This option searches for header files in the lt dir_name gt directory before searching the header files in the standard path Embedded System Tools Reference Manual www xilinx com 91 UG111 July 6 2011 Chapter 9 GNU Compiler Tools XILINX Default Search Paths The compilers mb gcc and powerpc eabi gcc search certain paths for libraries and header files The search paths on the various platforms are described below Library Search Procedures The compilers search libraries in the following order 1 2 3 Directories are passed to the compiler with the L lt dir_name gt option Directories are passed to the compiler with the B lt dir_name gt option The compilers search the following libraries a XILINX_EDK gnu processor platform processor lib lib b XILINX_EDK lib processor Note Processor indicates powerpc eabi for the PowerPC processor and microblaze for MicroBlaze Header File Search Procedures The compilers search header files in the following order 1 2 Directories are passed to the compiler with the I lt dir_name gt option The compilers search the following header files a XILINX_EDK gnu processor platform lib gcc processor gcc version include b S XILINX_EDK gnu processor platform processor lib include
145. cur Such errors include the execution of illegal instructions and bus errors Use the following steps 1 Download the program 2 Run the safemode on command 3 Start the program with the con command The program stops when an exception occurs This feature is more useful when working with the GUI debugger either Insight GDB or SDK e When using SDK check the Enable Safemode checkbox box in the Initialization tab before running the program e When using GDB download the program and run the safemode on command in XMD console before running the program in GDB When the exception occurs the program stops and the GUI shows the line of code that triggered the exception Processor Default Exception Settings Table 10 5 and Table 10 6 page 139 show the factory default settings for exception trapping settings by processor types Table 10 5 PowerPC Processor Exception Settings Exception_id Trap Exception_Name 0 No External critical interrupt exception 1 Yes External bus error exception 2 Yes Data storage exception 3 Yes Instruction storage exception 4 No External noncritical interrupt exception 5 No Unaligned data access exception 6 Yes Illegal op code exception 7 Yes FPU non available exception 8 No System call instruction 138 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX XMD User Commands Table 10 5 PowerPC Processor Exception S
146. d for the EDK tools libc a Standard C libraries including functions like strcmp and strlen libgec a GCC low level library containing emulation routines for floating point and 64 bit arithmetic libm a Math Library containing functions like cos and sine libsupctt a C support library with routines for exception handling RTTI and others libstdct a C standard platform library Contains standard language classes such as those for stream I O file I O string manipulation and others Libraries are linked in automatically by both compilers If the standard libraries are overridden the search path for these libraries must be given to the compiler The 1ibxil a is modified by the Library Generator tool Libgen to add driver and library routines Language Dialect The GCC compiler recognizes both C and C dialects and generates code accordingly By GCC convention it is possible to use either the GCC or the G compilers equivalently on a source file The compiler that you use and the extension of your source file determines the dialect used on the input and output files When using the GCC compiler the dialect of a program is always determined by the file extension as listed in Table 9 1 page 86 If a file extension shows that it is a C source file the language is set to C This means that if you have compile C code contained in a CC file even if you use the GCC compiler it automatically
147. d redirects the output from the mdm UART interface to an optionally specified TCL channel TCL Channel ID The read_uart stop command stops redirection A TCL channel represents an open file or a socket connection The TCL channel should be opened prior to using the read_uart command using appropriate TCL commands rrd rrd lt reg_num gt rrd rrd r1 or rrd R1 Reads all registers or reads lt reg_num gt register rwr lt register_number gt register_name gt lt Hex_value gt rrd 1 rst rst Resets the system If the processor option is specified the rst processor rst processor current processor target is reset If the processor is not in a Running state use the state command then the processor will be stopped at the processor reset location on reset rwr rwr pe 0x400 Registers writes from a lt register_number gt lt register_name gt or lt hex_value gt 130 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Table 10 2 XMD User Commands Cont d XMD User Commands command options run Example Usage run Description Runs program from the program start address The command does a reset stops the processor at the reset location by using breakpoints and loads the ELF program data sections to the memory Loading the ELF program data sections ensures that the static variables are properly i
148. dded System Tools Reference Manual www xilinx com 23 UG111 July 6 2011 24 Chapter 2 Platform Specification Utility PsfUtility XILINX When the signal naming conventions are correctly specified the following interface types are recognized automatically and the MPD file contains the bus interface label shown in Table 2 2 Table 2 2 Recognized Bus Interfaces Description Bus Label in MPD Slave AXI interface S_AXI Master AXI interface M_AXI Slave DCR interface SDCR Master FSL interface MFSL Slave FSL interface SFSL Slave LMB interface SLMB Master PLBV4 6 interface MPLB Slave PLBV4 6 interface SPLB Naming Conventions for VHDL Generics For peripherals that contain more than one of the same bus interface a bus identifier must be used The bus identifier must be attached to all associated signals and generics Generic names must be VHDL compliant Additional conventions for IP peripherals are The generic must start with c_ If more than one instance of a particular bus interface type is used on a peripheral a bus identifier lt BI gt must be used in the signal If a bus identifier is used for the signals associated with a port the generics associated with that port can optionally use lt BI gt If no lt BI gt string is used in the name the generics associated with bus parameters are assumed to be global For example c_DOPB_DWIDTH has a bus identifier of D and is associated with th
149. der It compiles the application locally to execute from the scratch memory address you specified in the dialog box You can compile your own flash writer sources by modifying your local copy of the flashwriter tcl script to compile your own sources instead of those from the installation Embedded System Tools Reference Manual www xilinx com 191 UG111 July 6 2011 Chapter 14 Flash Memory Programming XILINX 4 The script downloads the flash programmer to the processor and communicates with the flash programmer through mailboxes in memory In other words it writes parameters to the memory locations corresponding to variables in the flash programmer address space and lets the flash programmer execute 5 The script waits for the flash programmer to invoke a callback function at the end of each operation and stops the application at the callback function by setting a breakpoint at the beginning of the function When the flash programmer stops the host Tcl processes the results and continues with more commands as required 6 While running the flash programmer erases only as many flash blocks as required in which to store the image 7 The flashwriter allocates a streaming buffer based on the amount of scratch pad memory available and iteratively stream programs the image file The stream buffer is allocated within the flashwriter If there is enough scratch memory to hold the entire image the programming can be completed quickly
150. ditional Resources page 261 msoft float This option tells the compiler to use software emulation for floating point arithmetic This option is the default Embedded System Tools Reference Manual www xilinx com 101 UG111 July 6 2011 Chapter 9 GNU Compiler Tools XILINX mx1l float convert This option turns on the usage of single precision floating point conversion instructions fint and 1t in the compiler These instructions are natively decoded and executed by MicroBlaze when the FPU is enabled in hardware and these optional instructions are enabled Refer to the MicroBlaze Processor Reference Guide for more details about the use of the hardware floating point unit option in MicroBlaze A link to the document is provided in the Additional Resources page 261 mxl1 float sqrt This option turns on the usage of single precision floating point square root instructions sqrt in the compiler These instructions are natively decoded and executed by MicroBlaze when the FPU is enabled in hardware and these optional instructions are enabled Refer to the MicroBlaze Processor Reference Guide for more details about the use of the hardware floating point unit option in MicroBlaze A link to the document is provided in the Additional Resources page 261 General Program Options msmall1 divides This option generates code optimized for small divides when no hardware divider exists For signed integer divisions where the
151. dress of the next level handler It also consults the vectoring table for a callback value that it must pass to the next level handler Finally the actual call is made e Onsystems with an interrupt controller the next level handler is the handler provided by the interrupt controller driver This handler queries the interrupt controller for all active interrupts in the system For each active interrupt it consults its internal vector table which contains the user registered handler for each interrupt line If the user has not registered any handler a default do nothing handler is registered The registered handler for each interrupt gets invoked in turn in interrupt priority order e Onsystems without an interrupt controller the next handler is the final interrupt handler that the application wishes to execute The final interrupt handler for a particular interrupt typically queries the interrupting peripheral and determines the cause for the interrupt It does a series of actions that are appropriate for the given peripheral and the cause for the interrupt The handler is also responsible for acknowledging the interrupt at the interrupting peripheral After the interrupt handler is finished it returns back and the interrupt stack gets unwound all the way back to the software platform level interrupt handler The platform level interrupt handler restores the registers it saved on the stack and returns control back to the Program Counter PC
152. e simulator mgm ies isim questa none Set the simulator for which you want simulation scripts generated mgm Mentor Graphics ModelSim ies Cadence Incisive Enterprise Simulator isim ISE Simulator Sim questa Mentor Graphics QuestaSim none No simulator specified sim x lib Set the simulation library For details refer to Chapter 7 Simulation Model Generator Simgen sim_elf imp_elf Read Simulation Implementation ELF files associated with the processors Instead of the xset command use add_elf help elf ucf_file Specify a path to the User Constraints File UCF to be used for implementation tools usercmd1 Set the user command 1 usercmd2 Set the user command 2 user_make_file lt directory path gt Specify a path to the make file This file should not be same as the make file generated by XPS Embedded System Tools Reference Manual UG111 July 6 2011 www xilinx com 47 Chapter 5 Command Line Mode XILINX Executing Flow Commands You can run various flow tools using the run command with appropriate options XPS creates a make file for the project and runs that make file with the appropriate target XPS generates the make file every time the run command is executed Table 5 2 lists the valid options for the run command run lt option gt Table 5 2 run Command Options Option Name Description
153. e generated for PowerPC 405 and 440 processors and the MicroBlaze processor with Microprocessor Debug Module MDM systems Assumptions This chapter assumes that you e Are familiar with debugging programs using XMD and with using XMD commands e Are familiar with general hardware and software system models in EDK e Have a basic understanding of Tcl scripts Tool Requirements Generating an ACE file requires the following tools e agenace tcl file e XMD e iMPACT from ISE Embedded System Tools Reference Manual www xilinx com 177 UG111 July 6 2011 Chapter 13 System ACE File Generator GenACE XILINX GenACE Features GenACE e Supports PowerPC 405 and 440 processor and the MicroBlaze processor with MDM targets e Generates ACE files from hardware Bitstream and software ELF and data files e Initializes external memories on PowerPC 405 and 440 processors and MicroBlaze systems e Supports multi processor systems e Supports single and multiple FPGA device systems GenACE Model 178 System ACE CF is a two chip solution that requires the System ACE CF controller and either a CompactFlash card or one inch Microdrive disk drive technology as the storage medium System ACE CF configures devices using Boundary Scan JTAG instructions and a Boundary Scan Chain The generated System ACE files support the System ACE CF family of configuration solutions The System ACE file is generated from a S
154. e CLK_FREQ_HZ The frequency of every clock port in the merged hardware datastructure if available is stored in a sub property called CLK_FREQ_HZ on that port This is an internal sub property and the frequency value is always in Hz RESOLVED_ISVALID If a parameter port or bus interface has the sub property ISVALID defined in the MPD then the tools evaluate the expression to true 1 or false 0 and store the value in an internal sub property called RESOLVED_ISVALID on that property RESOLVED_BUS If a port or parameter in an IP has a colon separated list of buses specified in the Bus tag that it can be associated with in the MPD file the tools analyze the connectivity of that IP and determine to which of those buses the IP is connected and store the name of that bus interface in the RESOLVED_BUS tag Embedded System Tools Reference Manual www xilinx com 253 UG111 July 06 2011 Appendix C EDK Tcl Interface XILINX 254 www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 XILINX Appendix D Interconnect Settings and Parameter Automations for AXI Designs The MPD and MHS Chapters of the Platform Specification Format Reference Manual UG642 describe the INTERCONNECT related parameters that are captured on the end point master and slave bus interfaces These parameters usually contain the C_INTERCONNECT_ lt Bus f g
155. e bus signals that also have a bus identifier of D If only C_OPB_DWIDTH is present it is associated with all OPB buses regardless of the bus identifier on the port signals Note For the PLBV4 6 bus interface the bus identifier lt BI gt is treated as the bus tag bus interface name For example C_SPLBO_DWIDTH has a bus identifier tag SPLBO and is associated with the bus signals that also have a bus identifier of SPLBO as the prefix For peripherals that have only a single bus interface which is the case for most peripherals the use of the bus identifier string in the signal and generic names is optional and the bus identifier is typically not included All generics that specify a base address must end with _BASEADDR and all generics that specify a high address must end with _HIGHADDR Further to tie these addresses with buses they must also follow the conventions for parameters as listed above For peripherals with more than one bus interface type the parameters must have the bus standard type specified in the name For example parameters for an address on the PLB bus must be specified as C_PLB_BASEADDR and C_PLB_HIGHADDR The Platform Generator Platgen expands and populates certain reserved generics automatically For correct operation a bus tag must be associated with these parameters www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Conventions for Defining HDL Peripherals
156. e command xmd nx hw system xml tcl tmp flashwriter tcl settings flash tcl on the command line to use only the values that you specify in the flash tcl file 192 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Customizing Flash Programming Table 14 3 lists the available parameters in the lt XPS project gt directory Table 14 3 Flash Programming Parameters Variable Function EXTRA_COMPILER_FLAGS For MicroBlaze specify any compiler flags required to turn on support for hardware features For example if you have the hardware multiplier enabled add mno x1 soft mul here Do not set this variable for the PowerPC processors FLASH BASEADDR The base address of the flash memory bank FLASH BOOT CONFIG Refer to Handling Flash Devices with Conflicting Sector Layouts on page 194 FLASH_FILE A string containing the full path of the file to be programmed FLASH PROG OFFSET The offset within the flash memory bank at which the programming should be done PROC_INSTANCE The instance name of the processor used for programming SCRATCH_BASEADDR The base address of the scratch memory used during programming SCRATCH_LEN The length of the scratch memory in bytes TARGET_TYPE The type of the processor instance used for programming MicroBlaze or PowerPC 405 or 440 processor XILINX PLATFORM FLASH To enable use of the Xilinx Platform Flash XL flash dev
157. e directory Libgen generates the following directories and files which are described in the following subsections e The include Directory e lib Directory e libsrc Directory e code Directory Embedded System Tools Reference Manual www xilinx com 77 UG111 July 6 2011 Chapter 8 Library Generator Libgen XILINX The include Directory The include directory contains C header files needed by drivers The include file xparameters h is also created through Libgen in this directory This file defines base addresses of the peripherals in the system defines needed by drivers OSs libraries and user programs as well as function prototypes The Microprocessor Driver Definition MDD file for each driver specifies the definitions that must be customized for each peripheral that uses the driver Refer to the Microprocessor Driver Definition MDD chapter in the Platform Specification Format Reference Manual for more information The Microprocessor Library Definition MLD file for each OS and library specifies the definitions that you must customize Refer to the Microprocessor Library Definition MLD chapter in the Platform Specification Format Reference Manual for more information A link to the Platform Specification Format Reference Manual is supplied in Appendix E Additional Resources lib Directory The 1ib directory contains libc a libm a and libxil a libraries The 1ibxil library contains driver functions that the
158. e document is supplied in Appendix E Additional Resources Note When MicroBlaze is debugged in xMDSTUB mode only PC and MSR registers are accessible Embedded System Tools Reference Manual www xilinx com UG111 July 6 2011 133 Chapter 10 Xilinx Microprocessor Debugger XMD XILINX PowerPC 405 Processor Special Purpose Register Names Table 10 3 lists the special register names that are valid for PowerPC 405 processors Table 10 3 Special Register Names for PowerPC 405 Processors ccr0 f0 f11 f22 iac1 pvr su0r cr fl f12 23 iac2 sgr tbl ctr f2 f13 f24 iac4 sler tbu dac1 f3 f14 f25 iccr sprg0 tcr dac2 f4 f15 26 icdbdr sprg1 tsr dbcr0 f5 f16 f27 lr sprg2 usprg0 dbcr1 f6 f17 28 msr sprg3 xer dbsr f7 f18 29 pe sprg4 zpr dcer f8 f19 f30 pid sprg5 su0r dewr f9 f20 pit sprg6 tbl dear f10 f21 iacl sprg7 tbu dvcl iac2 srr0 dvc2 srrl esr srr2 evpr srr3 Note XMD always uses 64 bit notation to represent the Floating Point Registers f0 f31 In the case of a Single Precision floating point unit the 32 bit Single Precision value is extended to a 64 bit value For additional information about PowerPC 405 processor special register names refer to the PowerPC 405 Processor Block Reference Guide A link to the document is supplied in Appendix E Additional Resources 134 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX XMD User Commands PowerPC 440 Processor Special Pu
159. e drivers OSs and libraries into the processor instance specific area OUTPUT_DIR processor_instance_name libsrc e Calls the Design Rule Check DRC procedure which is defined as an option in the MDD or MLD file for each of the drivers OSs and libraries visible to the processor www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX MSS Parameters Calls the generate Tcl procedure if defined in the Tel file associated with an MDD or MLD file for each of the drivers OSs and libraries visible to the processor This generates the necessary configuration files for each of the drivers OSs and libraries in the include directory of the processor Calls the post_generate Tcl procedure if defined in the Tcl file associated with an MDD or MLD file for each of the drivers OSs and libraries visible to the processor Runs make with targets include and libs for the OSs drivers and libraries specific to the processor On the Linux platform the gmake utility is used while on NT platforms make is used for compilation Calls the execs_generate Tcl procedure if defined in the Tcl file associated with an MDD or MLD file for each of the drivers OSs and libraries visible to the processor MDD MLD and Tcl A driver or library has two associated data files Data Definition File MDD or MLD file This file defines the configurable parameters for the driver OS or library Data Generation File T
160. e migration of XBD IO_INTERFACE definitions to IP XACT bus definition XML equivalents All XBD2 component XML files reference the bus definitions outlined in this table A V L N V VLNV reference is provided where e V is the vendor e Lis the library catalog of the vendor e Nis the name of the board e Vis the board revision number Embedded System Tools Reference Manual www xilinx com 201 UG111 July 6 2011 Chapter 16 Microprocessor Peripheral Definition Translation tool MPDX XILINX Table 16 1 1O_INTERFACE Details XBD Feature IOTYPEXBD2 IP XACT Equivalent Comments XIL_CLOCK_V1 xilinx com bsb_lib rtl_busdefs clock 1 0 Clock XIL_RESET_V1 xilinx com bsb_lib rtl_busdefs reset 1 0 Reset XIL_TEMAC V1 xilinx com bsb_lib rtl_busdefs gmii 1 0 GMII XIL_IIC_V1 xilinx com bsb_lib rtl_busdefs i2c 1 0 IC XIL_MEMORY_V1 xilinx com bsb_lib rtl_busdefs ddr3_sdram1 0 DDR3 SDRAM XIL_MEMORY_V1 xilinx com bsb_lib rtl_busdefs ddr2_sdram 1 0 DDR2 SDRAM XIL_PCI_ARBITER_V1 Not supported PCI arbitration_group XIL_PCIE_V1 Not supported PCI Express XIL_CPUDEBUG_V1 Not supported JTAG XIL_TRACE_V1 N A XIL_ETHERNET_V1 xilinx com bsb_lib rtl_busdefs mii 1 0 MII XIL_GPIO_V1 xilinx com bsb_lib rtl_busdefs gpio 1 0 GPIO XIL_EMC_V1 xilinx com bsb_lib rtl_busdefs flash_nor 1 0 NOR flash XIL_PS2_V1 N A XIL_S
161. e of the IP instance whose handle is required If lt ipinst _name gt is specified as an asterisk the API returns a list of IP instance handles To access an individual IP instance handle you can iterate over the list in Tcl xget_hw_mpd_ handle lt ipinst_handie gt Description Arguments Returns a handle to the MPD object associated with the specified IP instance lt ipinst_handle gt is a handle to the merged IP instance xget_hw_ name Description Arguments lt handle gt Returns the name of the specified handle lt handle gt is of specified type If lt handle gt is of type IP instance its name is the instance name of that IP For example if the handle refers to an instance of MicroBlaze called mymb in the MHS file the value the API returns is mymb Similarly to get the name of a parameter from a parameter handle you can use the same command Embedded System Tools Reference Manual www xilinx com 235 UG111 July 06 2011 Appendix C EDK Tel Interface XILINX xget_hw_ option handle lt handle gt lt option_name gt Description Returns a handle to the associated option Arguments lt hand1le gt is the associated option lt option_name gt is the name of the option whose value is required If specified as an asterisk the API returns a list of option handles To access an individual option handle you can iterate over the list in Tcl xget_hw_option_ value lt handle g
162. e verification e You can load your design on a supported development board and use a debugging tool to control the target processor e You can gauge the performance of your system by profiling the execution of your code Device Configuration When your hardware and software platforms are complete you then create a configuration bitstream for the target FPGA device e For prototyping download the bitstream along with any software you require to run on your embedded platform while connected to your host computer e For production store your configuration bitstream and software in a non volatile memory connected to the FPGA Embedded System Tools Reference Manual www xilinx com 9 UG111 July 6 2011 Chapter 1 Embedded System and Tools Architecture Overview XILINX EDK Overview An embedded hardware platform typically consists of one or more processors peripherals and memory blocks interconnected via processor buses It also has port connections to the outside world Each of the processor cores also referred to as pcores or processor IPs has a number of parameters that you can adjust to customize its behavior These parameters also define the address map of your peripherals and memories XPS lets you select from various optional features consequently the FPGA needs only implement the subset of functionality required by your application Figure 1 2 provides an overview of the EDK architecture structure of how the tools
163. eStep and Green Hills Multi Xilinx recommends that you bring the JTAG signals of the PowerPC processor TCK TMS TDI and TDO out of the FPGA as User IO to appropriate debug connectors on the hardware board You must also bring the DBGC405DEBUGHALT and C405JTGTDOEN signals out of the FPGA as User IO In the case of multiple PowerPC processors Xilinx recommends that you chain the PowerPC processor JTAG signals inside the FPGA For more information about connecting the PowerPC processor JTAG port to FPGA User IO refer to the JTAG port sections of the PowerPC 405 Processor Block Reference Guide and the PowerPC 440 Processor Block Reference Guide A link to the document is supplied in Appendix E Additional Resources Note DO NOT use the JTAGPowerPC module while bringing the PowerPC processor JTAG signals out as User IO MicroBlaze Processor Target XMD can connect through JTAG to one or more MicroBlaze processors using the MDM peripheral XMD can communicate with a ROM monitor such as XMDStub through a JTAG or serial interface You can also debug programs using built in cycle accurate MicroBlaze ISS The following sections describe the options for these targets MicroBlaze MDM Hardware Target Use the command connect mb mdm to connect to the MDM target and start the remote GDB server The MDM target supports non intrusive debugging using hardware breakpoints and hardware single step without the need for a ROM monitor Figure 10 3
164. eck for lt data value gt If lt data value gt is not specified watchpoints match any value The address and value can be specified in hex or binary format a This command is for Simulator targets only 166 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX XMD Internal Tcl Commands XMD MicroBlaze Hardware Target Signals Table 10 19 XMD MicroBlaze Hardware Target Signals Signal Name Value Non maskable Break 0x10 Description Similar to the Break signal but works even while the BIP flag is already set Refer the MicroBlaze Processor Reference Guide for more information about the BIP flag A link to the document is supplied in Appendix E Additional Resources Processor Break 0x20 Raises the Brk signal on MicroBlaze using the JTAG UART Ext_Brk signal It sets the Break in Progress BIP flag on MicroBlaze and jumps to address 0x18 Processor Reset 0x80 Resets MicroBlaze using the JTAG UART Debug_Rst signal System Reset 0x40 Resets the entire system by sending an OPB Rst using the JTAG UART Debug_SYS_Rst signal Program Trace and Profile Options Table 10 20 Program Trace Profile Options Option Output File gt xprofile lt target id gt xprofile lt target id gt o lt GMON Generates profile output that can be read by config sampling_freq_hw lt value gt frequency in Hz Histogram binary size Descriptio
165. ed to XMD using the GDB remote target Refer to Chapter 11 GNU Debugger for more information about connecting GDB to XMD XMD connect ppc hw JTAG chain configuration Device ID Code IR Length Part Name 1 0a001093 8 System_ACE 2 5059093 16 XCF32P 3 01e58093 10 XC4VFX12 4 49608093 8 xc95144x1 PowerPC405 Processor Configuration WEES TON ck ghd dre iiaa na wee ee eee Gees 0x20011430 User TED soe died ay oral Gate Mw ede wee Roce es BS 0x00000000 No of PC Breakpoints 4 No of Read Addr Data Watchpoints 1 No of Write Addr Data Watchpoints 1 User Defined Address Map to access Special PowerPC Features using XMD I Cache Data 0x70000000 Ox70003ffF I Cache TAG 0x70004000 Ox70007ffF D Cache Data 0x78000000 Ox78003ffFf D Cache TAG 0x78004000 0x78007fff DER siipra Seacoast 0x78004000 0x78004fff 144 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Connect Command Options Connected to ppc target id 0 0x70004000 0x70007fff Starting GDB server for ppc target id 0 at TCP port no 1234 XMD rrd r0 ef0009f8 r8 51c6832a r16 00000804 r24 32a08800 r1 00000003 r9 a2c94315 r17 00000408 r25 31504400 r2 fe008380 r10 00000003 r18 7c7dfcd r26 82020922 r3 d004340 r11 00000003 r19 fbcbefce r27 41010611 r4 0007a120 r12 51c6832a r20 0040080d r28 fe0006f0 r5 000b5210 r
166. eing the highest priority interrupt 220 www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 XILINX Software APIs int XIntc_Start XIntc InstancePtr u8 Mode Description Starts the interrupt controller by enabling the output from the controller to the processor Interrupts can be generated by the interrupt controller after this function is called Parameters InstancePtr isa pointer to the XIntc instance Mode determines if software is allowed to simulate interrupts or if real interrupts are allowed to occur Modes are mutually exclusive The interrupt controller hardware resets in a mode that allows software to simulate interrupts until this mode is exited It cannot be re entered after it has been exited Mode is one of the following valued XIN_SIMULATION_MODE enables simulation of interrupts only XIN_REAL_MODE enables hardware interrupts only This function must be called after Xintc initialization is completed void XIntc_Stop XIntc InstancePtr Description Stops the interrupt controller by disabling the output from the controller so that no interrupts are caused by the interrupt controller Parameters InstancePtr isa pointer to the XIntc instance Hardware Abstraction Layer APIs The following is a summary of exception functions which can run on MicroBlaze PowerPC 405 and PowerPC 440 processors Header File include xil_exception h Typedef typedef void Xil_ExceptionHa
167. em prj lang vhdl top mch_mem p2pbus MCHO XIL_MEMORY_ CHANNEL TARGET o mch_mem mpd DRC Checks in PsfUtility To enable generation of correct and complete MPD files from HDL sources the PsfUtility reports DRC errors The DRC checks are listed in the following subsections in the order they are performed HDL Source Errors The PsfUtility returns a failure status if errors are found in the HDL source files Bus Interface Checks For every specified bus interface the PsfUtility checks and reports any missing or repeated bus signals It generates an MPD file when all bus interface checks are completed Conventions for Defining HDL Peripherals The top level HDL source file for an IP peripheral defines the interface for the design and has the following characteristics e Lists ports and default connectivity for bus interfaces e Lists parameters generics and default values e Parameters defined in the MHS overwrite corresponding HDL source parameters Individual peripheral documentation contains information on source file options For components that have more than one bus interface of the same type naming conventions must be followed so the automation tools can group the bus interfaces Naming Conventions for Bus Interfaces A bus interface is a grouping of related interface signals For the automation tools to function properly you must adhere to the signal naming conventions and parameters associated with a bus interface Embe
168. en reads the MSS file and generates the software components configuring them as specified in the MSS For further description on generating the XML hardware specification file refer to the Software Development Kit SDK documentation in the SDK Online Help For further description of the MSS file format refer to the Microprocessor Software Specification MSS chapter in the Platform Specification Format Reference Manual A link to the document is supplied in Appendix E Additional Resources Note EDK includes a Format Revision tool to convert older MSS file formats to a new MSS format Refer to Chapter 15 Version Management Tools revup for more information Tool Usage To run Libgen type the following libgen options lt filename gt mss Tool Options Table 8 1 list the supported Libgen command options Table 8 1 Libgen Syntax Options Option Command Description Help h help Displays the usage menu and quits Version v Displays the version number of Libgen and quits Log output log lt logfile log gt Specifies the log file Default Libgen log Embedded System Tools Reference Manual www xilinx com 75 UG111 July 6 2011 Chapter 8 Library Generator Libgen XILINX Table 8 1 Libgen Syntax Options Cont d Option Command Description Output directory od lt output_dir gt Specifies the output directory output_dir The default is the current directory All output f
169. ename Description peripheral_wrapper vhd v Modular simulation files for each component Not applicable for timing models system_name vhd v The top level HDL file of the design system_name sdf The SDF file with the appropriate block and net delays from the place and route process used only for timing simulation xilinxsim ini Initialization file for the ISim system prj Project file specifying HDL source files and libraries to compile for the ISim 68 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Memory Initialization Table 7 2 Simgen Output Files Cont d Filename Description lt system_name gt _fuse sh Helper script to create a simulation executable ISim only when Simgen does not create a test harness lt system_name gt _setup do sh tc1 Script to compile the HDL files and load the compiled simulation models in the simulator lt test_harness_name gt prj Project file specifying HDL source and libraries to compile for the ISim when Simgen creates a test harness lt test_harness_fuse gt sh Helper script to create a simulation executable ISim only when Simgen creates a test harness lt test_harness gt _setup do sh tc1 Helper script to set up the simulator and specify signals to display in a waveform window or tabular list window ModelSim only lt test_harness gt _wave do sv tc1 Helper script to set up simulation waveform d
170. ename elf gt mrd_var global_varl1 executable elf Reads memory corresponding to global variable in the lt filename e1f gt or ina previously downloaded ELF file Embedded System Tools Reference Manual UG111 July 6 2011 www xilinx com 129 Chapter 10 Xilinx Microprocessor Debugger XMD XILINX Table 10 2 XMD User Commands Cont d command options mwr lt address gt lt values gt lt number of words half words bytes gt w h b mwr mwr lt Global Variable Name gt lt values gt lt number of words half words bytes gt w h b Example Usage mwr 0x400 0x12345678 mwr 0x400 0x1234 1h mwr 0x400 0x12345678 0x87654321 2 Description Writes to num memory locations starting at lt address gt or lt Global Variable Name gt Defaults to a word w write profile profile o lt GMON Output filename gt profile o gproff out Writes a Profile output file which can be interpreted by mb gprof or powerpc eabi gprof to generate profiling information Specify the profile configuration sampling frequency in Hz histogram bin size and memory address for collecting profile data For details about Profiling using XPS search on Profiling in the Platform Studio Online Help read_uart read_uart start stop lt TCL Channel ID gt read_uart start read_uart stop read_uart start channel_id The read_uart start comman
171. entation updated to include information regarding new flash devices that require that the cfi c file be modified Updates configdevice option The configdevice option documentation changed to reflect that the option is available in the OPT file only configdevice is not available as a command line option 11 1 Changes Tools are updated to reflect revision 11 1 Updates XMP The following tags were removed from the XMP in 11 1 FpgaImpMode Used to select between Xplorer and xflow flows Beginning with release 11 1 Xplorer is no longer supported in EDK Instead instantiate the project in the ISE Project Navigator to use Xplorer flow e EnableResetOptimization ISE tools no longer require this setting to improve timing e InsertNoPads TopInst NPL File These settings are removed from the XMP e tLockAddr ICacheAddr DCacheAddr These settings for Address Generator in the GUI were removed e Simulator MixLangSim Simulator settings are now applied across all XPS projects The simulator settings can be set in Edit gt Preferences in the XPS GUI Updates Simgen e The CompEDKLib was removed and replaced by Compx1lib e E switch was deprecated Updates Command Line The enable_reset_optimization option is obsoleted Updates PsfUtility e The tbus suboption was obsoleted e the KIND_OF_ reserved generics were obsoleted www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g
172. erial Vector Format SVF file which is a text file that contains both programming instructions and configuration data to perform JTAG operations XMD and iMPACT generate SVF files for software and hardware system files respectively The set of JTAG instructions and data used to communicate with the JTAG chain on board is an SVF file It includes the instructions and data to perform operations such as e Configuring an FPGA using iMPACT e Connecting to the processor target e Downloading the program and running the program from XMD These actions are captured in an SVF file format The SVF file is then converted to an ACE file and written to the storage medium These operations are performed by the System ACE controller to achieve the determined operation The following is the sequence of operations using iMPACT and XMD for a simple hardware and software configuration that gets translated into an ACE file 1 Download the bitstream using iMPACT The bitstream download bit contains system configuration and bootloop code 2 Bring the device out of reset causing the Done pin to go high This starts the processor system Connect to the processor using XMD Download multiple data files to block RAM or external memory Download multiple executable files to block RAM or external memory The PC points to the start location of the last downloaded ELF file 6 Continue execution from the PC instruction address The flow for generating Sys
173. es such as strcpy strlen and strcmp On a program heavily dependent on string manipulation routines the speed increase obtained will be significant The compiler automatically defines the C pre processor definition HAVE_Hw_PcMP when this switch is used This allows you to write C or assembly code tailored to the hardware based on whether this feature is specified as available or not Refer to the MicroBlaze Processor Reference Guide for more details about the use of the pattern compare option in MicroBlaze A link to the document is provided in Additional Resources page 261 mno xl pattern compare This option tells the compiler not to use pattern compare instructions This is the default mhard float This option turns on the usage of single precision floating point instructions fadd frsub fmul1 and fdiv in the compiler It also uses femp p instructions where p is a predicate condition such as 1e ge 1t gt eq ne These instructions are natively decoded and executed by MicroBlaze when the FPU is enabled in hardware The compiler automatically defines the C pre processor definition HAVE_HwW_FPU when this switch is used This allows you to write C or assembly code tailored to the hardware based on whether this feature is specified as available or not Refer to the MicroBlaze Processor Reference Guide for more details about the use of the hardware floating point unit option in MicroBlaze A link to the document is provided in the Ad
174. esses The Format Revision tool creates a backup of your files and a file name extension that specifies the EDK release number For example EDK 11 1 files are saved with a 111 extension and then modified for EDK 12 x tools 13 2 Changes Tools are updated to reflect revision 13 2 13 1 Changes Tools are updated to reflect revision 13 1 12 1 Changes Tools are updated to reflect revision 12 1 11 4 Changes Tools are updated to reflect revision 11 4 Embedded System Tools Reference Manual www xilinx com 197 UG111 July 6 2011 198 Chapter 15 Version Management Tools revup XILINX 11 3 Changes Tools are updated to reflect revision 11 3 Updates GenACE A microblaze_v72 option was added to the cpu_version XMD debug device command in the Genace File Options in Table 13 2 page 180 Updates XMD e An option to specify the FPGA device was added to the Program Control Options in Table 10 18 page 166 e Anote was added to the dow command to clarify that only those segments of an ELF file that are marked as LOAD are executed e References to ppc440 mode for ISS were removed Update BFM The Bus Functional Model was added as a chapter of this document Update Flash Programmer A work around was added to allow the user to change a flash program from synchronous to asynchronous in the TCL file 11 2 Changes Tools are updated to reflect revision 11 2 Updates Flash Memory The set reset command docum
175. est Arbiter X10847 Figure 6 1 Slave IP Verification Use Case 52 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Bus Functional Model Use Cases Figure 6 2 shows an example in which a slave BFM responds to bus transactions that the device under test generates The monitor BFM reports any errors regarding the bus compliance of the device under test Monitor BFM Master Device Slave BEM Arbiter X10848 Figure 6 2 Master IP Verification Use Case Under Test Speed Up Simulation When verifying a large system design it can be time consuming to simulate the internal details of each IP component that attaches to a bus There are certain complex pieces of IP that take a long time to simulate and could be replaced by a Bus Functional Model especially when the internal details of the IP are not of interest Additionally some IP components are not easy to program to generate the desired bus transactions Figure 6 3 shows how two different IP components that are bus masters have been replaced by BFM master modules These modules are simple to program and can provide a shorter simulation time because no internal details are modeled Monitor BFM Master BFM Master ee BFM Figure 6 3 Speed Up Simulation Use Case Component 1 gt Component 2 X10849 Embedded System Tools Reference Manual www xilinx com 53 UG111 July 6 2011 Chapter 6 Bus Functional Model S
176. et and start a GDB server for the target XMD connects to XMDStub through a JTAG or serial interface The default option connects using a JTAG interface MicroBlaze Stub JTAG Target Options Usage connect mb stub comm jtag cable lt JTAG Cable options gt configdevice lt JTAG chain options gt debugdevice lt MicroBlaze options gt JTAG Cable Options and JTAG Chain Options For JTAG cable and chain option descriptions refer to Table 10 8 JTAG Cable Options on page 141 and Table 10 9 JTAG Chain Options on page 142 respectively MicroBlaze Option Option Description devicenr The position in the JTAG chain of the FPGA lt MicroBlaze device position gt device containing MicroBlaze MicroBlaze Stub Serial Target Options Usage connect mb stub comm serial lt Serial Communication options gt Serial Communication Options Table 10 14 lists the options that specify the MicroBlaze stub serial target Table 10 14 MicroBlaze Stub Serial Target Options Option Description baud Specifies the serial port baud rate in bits per second lt serial port baud rate gt bps The default value is 19200 bps port lt serial port gt Specifies the serial port to which the remote hardware is connected when XMD communication is over the serial cable The default serial ports are dev ttyso on Linux Com1 on Windows timeout Timeout period while waiting for a reply from lt timeo
177. ettings Cont d Exception_id Trap Exception_Name 9 Yes APU non available exception 10 No Time out exception on programmable interval timer 11 No Time out exception on fixed interval timer 12 No Time out exception on watchdog timer 13 No Data TLB miss exception 14 No Instruction TLB miss exception 15 No Debug event exception 16 Yes Assertion failure 17 Yes Program exit Table 10 6 MicroBlaze Exception Settings Exception_id Trap Exception_Name 0 Yes Fast Simplex Link exception 1 No Unaligned data access exception 2 Yes Illegal op code exception 3 Yes Instruction bus error exception 4 Yes Data bus error exception 5 Yes Divide by zero exception 6 Yes Floating point unit exception 7 Yes Privileged instruction exception 8 Yes Data storage exception 9 Yes Instruction storage exception 10 Yes Data TLB miss exception 11 Yes Instruction TLB miss exception 12 Yes Assertion failure 13 Yes Program exit Embedded System Tools Reference Manual UG111 July 6 2011 www xilinx com 139 Chapter 10 Xilinx Microprocessor Debugger XMD XILINX Overwriting Exception Settings There are two methods to overwrite the default exception settings 1 Use the command xmdconfig mb_trap_mask ppc_trap_mask MASK This sets the mask for all targets in the current XMD session To define your own default setting fo
178. exclusion mechanisms when using the EDK libraries in a multi threaded environment Command Line Arguments PowerPC processor programs cannot take in command line arguments The command line arguments argc and argv are initialized to zero by the C runtime routines Other Notes C Code Size The GCC toolchain combined with the latest open source C standard library libstdc v3 might be found to generate large code and data fragments as compared to an equivalent C program A significant portion of this overhead comes from code and data for exception handling and runtime type information Some C applications do not require these features To remove the overhead and optimize for size use the f no exceptions and or the fno rtti switches This is recommended only for advanced users who know the requirements of their application and understand these language features Refer to the GCC manual for more specific information on available compiler options and their impact C programs might have more intensive dynamic memory requirements stack and heap size due to more complex language features and library routines Many of the C library routines can request memory to be allocated from the heap Review your heap and stack size requirements for C programs to ensure that they are satisfied C Standard Library The C standard defines the C standard library A few of these platform features are unavailable on the default Xilin
179. f handles to slaves that can be addressed by the specified processor lt merged_proc_hand1le gt is a handle to the merged IP instance pointing to a processor instance This returned list includes slaves that are not directly connected to the processor but are accessed across a bus to bus bridge for example opb2p1b_bridge The input handle must be an IP instance handle to a processor instance obtained from the merged MHS only not from the original MHS www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 XILINX EDK Hardware Tcl Commands xget_hw subproperty handle lt property_handle gt lt subprop_name gt Description Arguments Returns the handle to a subproperty associated with the specified lt property_handle gt lt property_handle gt is a handle to one of the following PARAMETER PORT BUS_INTERFACI IO_INTERFACE or OPTION aa S lt subprop_name gt is the name of the subproperty whose handle is required For a list of sub properties please refer to Microprocessor Peripheral Definition Microprocessor Peripheral Definition MPD in the Platform Specification Format Reference Manual and Additional Keywords in the Merged Hardware Datastructure on page 253 xget_hw subproperty value lt property_handle gt lt subprop_name gt Description Arguments Returns the value of a specified subproperty lt property_hand1e gt is one of the fo
180. f more than one instance of a particular bus interface type is used on a peripheral the bus identifier lt BI gt must be included in the signal identifier The bus identifier can be as simple as a single letter or as complex as a descriptive string with a trailing underscore _ peripheral lt BI gt must be included in the port signal identifiers in the following cases The peripheral has more than one slave AXI port The peripheral has more than one master AXI port The peripheral has more than one slave LMB port The peripheral has more than one slave DCR port The peripheral has more than one master DCR port The peripheral has more than one slave FSL port The peripheral has more than one master FSL port The peripheral has more than one slave PLBV4 6 port The peripheral has more than one master PLBV4 6 port The peripheral has more than one port of any type and the choice of lt mn gt or lt Sin gt causes ambiguity in the signal names For peripherals that have only a single bus interface which is the case for most peripherals the use of the bus identifier string in the signal names is optional and the bus identifier is typically not included www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Conventions for Defining HDL Peripherals Global Ports The names for the global ports of a peripheral such as clock and reset signals are standardized You can use any name for other global ports
181. files from archives An archive is a file that contains one or more other files typically object files for libraries mb as This is the assembler program Embedded System Tools Reference Manual www xilinx com 209 UG111 July 06 2011 Appendix A GNU Utilities XILINX mb c This is the same cross compiler as mb gcc invoked with the programming language set to C This is the same as mb g mb c filt This program performs name demangling for C and Java function names in assembly listings mb g This is the same cross compiler as mb gcc invoked with the programming language set to C This is the same as mb c mb gasp This is the macro preprocessor for the assembler program mb gcc This is the cross compiler for C and C programs It automatically identifies the programming language used based on the file extension mb gdb This is the debugger for programs mb gprof This is a profiling program that allows you to analyze how much time is spent in each part of your program It is useful for optimizing run time mb ld This is the linker program It combines library and object files performing any relocation necessary and generates an executable file mb nm This program lists the symbols in an object file mb objcopy This program translates the contents of an object file from one format to another mb objdump This program displays information about an object file This is very useful in deb
182. for stack and heap Set the _stack variable to the location after _STACK_S1IZE locations of this area and the _heap_start variable to the next location after the _STACK_SIZE location Because the stack and heap need not be initialized for hardware as well as simulation define the _bss_end variable after the bss and COMMON definitions Note that the bss section boundary does not include either stack or heap Ensure that the variables _SDATA_START__ _SDATA_END__ _SDATA2_ START SDATA2_ END_ SBSS2_START__ _SBSS2_END__ _bss_start _bss_end _sbss_start and _sbss_end are defined to the beginning and end of the sections sdata sdata2 sbss2 bss and sbss respectively For the PowerPC 405 processor ensure that the vectors section is aligned ona 64K boundary The PowerPC 440 processor does not require any special alignment on the vectors section Include this section definition only when your program uses interrupts and or exceptions Each physical region of memory must use a separate program header Two discontinuous regions of memory cannot share a program header ANSI C requires that all uninitialized memory be initialized to startup not required for stack and heap The standard CRT provided assumes a single bss section that is initialized to zero If there are multiple bss sections this CRT will not work You must write your own CRT that initializes the bss_ sections Embedded System Tools Reference Manual www x
183. ftware application image typically a few megabytes worth of data in flash memory A small bootloader is then designed to fit in block RAM The processor executes the bootloader on reset which then copies the software application image from flash into external memory The bootloader then transfers control to the software application to continue execution The software application you build from your project is in Executable Linked Format ELF When bootloading a software application from flash ELF images should be converted to one of the common bootloadable image formats such as Motorola S record SREC This keeps the bootloader smaller and more simple EDK provides interface and command line options for creating bootloaders in SREC format See the Xilinx Platform Studio Help for instructions on creating a flash bootloader and on converting ELF images to SREC The Appendix E Additional Resources contains a link the help Flash Programming from XPS The Xilinx Platform Studio XPS interface includes dialog boxes from which you can program external Common Flash Interface CFI compliant parallel flash devices on your board connected through the external memory controller EMC IP cores The programming solution is designed to be generic and targets a wide variety of flash hardware and layouts The programming is achieved through the debugger connection to a processor in your design XPS downloads and executes a small in system flash program
184. ger XMD as the underlying engine to communicate to processor targets Tool Overview Tool Usage MicroBlaze GDB usage mb gdb lt options gt executable file PowerPC GDB usage powerpc eabi gdb lt options gt executable file Tool Options The following options are the most common in the GNU debugger command FILE Execute GDB commands from the specified file Used for debugging in batch and script mode batch Exit after processing options Used for debugging in batch and script mode Embedded System Tools Reference Manual www xilinx com 169 UG111 July 6 2011 Chapter 11 GNU Debugger XILINX nx Do not read initialization file gdbinit If you have issues connecting to XMD GDB connects and disconnects from XMD target launch GDB with this option or remove the gdbinit file nw Do not use a GUI interface W Use a GUI interface Default Debug Flow using GDB Start XMD from XPS Connect to the Processor target This action opens a GDB server for the target Start GDB from XPS Connect to Remote GDB Server on XMD Oo PF ONY PP Download the Program and Debug application MicroBlaze GDB Targets The MicroBlaze GNU Debugger and XMD tools support remote targets Remote debugging is done through XMD The XMD server program can be started on a host computer with the Simulator target or the Hardware target The Cycle Accurate Instruction Set Simulator ISS and the hardware interface provide powe
185. gistered a default do nothing handler is registered The registered handler for each interrupt gets invoked in turn in interrupt priority order e On systems without an interrupt controller the next handler is the final interrupt handler that is executed by the application The final interrupt handler for a particular interrupt typically queries the interrupting peripheral and determines the cause for the interrupt It usually does a series of actions that are appropriate for the given peripheral and the cause for the interrupt The handler is also responsible for acknowledging the interrupt at the interrupting peripheral When the interrupt handler completes its activity it returns back and the interrupt stack gets unwound back to the software platform level interrupt handler The platform level interrupt handler restores the registers that it saved on the stack and returns control back to the Program Counter PC location where the interrupt occurred Embedded System Tools Reference Manual www xilinx com 217 UG111 July 06 2011 Appendix B Interrupt Management XILINX The return instruction also enables interrupts again on the PowerPC processor The application resumes normal execution at this point It is recommended that interrupt handlers be of a short duration and that the bulk of the interrupt work be done by application This prevents long lockouts of other possibly higher priority interrupts and is considered good sy
186. hain Options Table 10 9 lists the options that let you specify device information of non Xilinx devices in the JTAG chain Refer to Example Showing Special JTAG Chain Setup for Non Xilinx Devices on page 147 Table 10 9 JTAG Chain Options Option Description devicenr lt device position gt The position of the device in the JTAG chain The device position number starts from 1 irlength lt length of the JTAG The length of the IR register of the device This information can be found in the Instruction Register gt device BSDL file idcode lt device idcode gt JTAG ID code of the device If the PowerPC processor JTAG pins are connected directly to FPGA user IO pins the irlength should be 4 partname lt device name gt The name of the device PowerPC Processor Options The following options allow you to specify the FPGA device to debug and the processor number in the device You can also map special PowerPC processor features such as ISOCM Caches TLB and DCR registers to unused memory addresses and then access them from the debugger as memory addresses This is helpful for reading and writing to these registers and memory from GDB or XMD Table 10 10 lists the PowerPC processor options Note These options do not create any real memory mapping in hardware Table 10 10 PowerPC Processor Options Option cpunr lt CPU Number gt Description PowerPC processor number to be debugged in
187. he jtag_uart_server option is specified a TCP server is opened at lt port_no gt Use any hyperterminal utility to communicate with opb_mdm UART interface over TCP sockets The lt port_number gt default value is 4321 The lt baudrate gt determines the rate at which the JTAG UART port reads the data This option can have the values low med or high The default setting is med Increasing the baud rate might affect other debug operations because XMD is busy polling for data on the JTAG UART port tracestart tracestart lt pc_trace_filename gt function_name lt func_trace_filename gt tracestart pcetrace txt tracestart pcetrace txt function_name fntrace txt Starts collecting instruction and function trace information to lt filename gt Trace collection can be stopped and started any time the program runs lt filename gt is specified on first tracestart only lt pc_trace_filename gt defaults to isstrace out lt func_trace_filename gt defaults to tracestop done tracestop done tracestart fntrace out This is supported on ISS targets only tracestop tracestop Stops collecting trace information The done option signifies the end of tracing Supported on ISS targets only 132 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Table 10 2 XMD User Commands Cont d XMD User Commands command options Example
188. he JTAF Chain options or by specifying it in the GUI See Connect Command Options page 140 and JTAG Chain Options page 142 and for more information PowerPC Processor Simulator Target XMD can connect to one or more PowerPC 405 processor ISS targets through socket connection Use the connect ppe sim command to start the PowerPC 405 processor ISS on a local host connect to that host and start a remote GDB server You can also use connect ppc sim to connect to a PowerPC 405 processor ISS running on localhost or other machine When XMD is connected to the PowerPC 405 processor target powerpc eabi gdb can connect to the target through XMD and debugging can proceed Note XMD does not support PowerPC 440 processor ISS targets Running PowerPC Processor ISS XMD starts the ISS with a default configuration e The ISS executable file is located in the XILINX_EDK third_party bin lt platform gt directory e The PowerPC 405 processor configuration file used is XILINX_EDK third_party data iss405 icf You can run ISS with different configuration options and XMD can connect to the ISS target Refer to the IBM Instruction Set Simulator User Guide for more details A link to the document is supplied in Appendix E Additional Resources The following are the default configurations for ISS e Two local memory banks e Connect to XMD Debugger e Debugger port at 6470 6490 e Data cache size of 16 K e Instruction cache size of
189. he current version The revup tool performs format changes only it does not update your design Backups of existing files such as the project file XMP the MHS and MSS files are performed before the format changes are applied The Version Management wizard appears automatically when an older project is opened in a newer version of EDK for example when a project created in EDK 10 1 is opened in version 11 3 The Version Management wizard is invoked after format revision has been performed The wizard provides information about any changes in Xilinx Processor IPs used in the design If anew compatible version of an IP is available then the wizard also prompts you to update to the new version For instructions on using the Version Management wizard see Chapter 15 Version Management Tools revup and the Xilinx Platform Studio Help Microprocessor Peripheral Definition Translation tool MPDX For board designers not familiar with the IP XACT tool a board description can be captured in an ASCII text file similar to the Microprocessor Peripheral Definition MPD format that captures a pcore description This MPD file is known as the Board MPD It includes a translation tool MPDX which generates the IP XACT files on disk for the BSB repository Chapter 16 Microprocessor Peripheral Definition Translation tool MPDX describes how to use this tool www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILIN
190. he handler for that interrupt CallBackRef is the callback reference usually the instance pointer of the connecting driver The handler provided as an argument overwrites any handler that was previously connected void XIntc_Disconnect XIntc InstancePtr u8 Id Description Disconnects the XIntc instance Parameters InstancePtrisa pointer to the XIntc instance Id contains the ID of the interrupt source and should be in the range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS 1 with 0 being the highest priority interrupt Void XIntc_Enable XIntc InstancePtr u8 Id Description Enables the interrupt source provided as the argument Id Any pending interrupt condition for the specified Id occurs after this function is called Parameters InstancePtr isa pointer to the XIntc instance Id contains the ID of the interrupt source and should be in the range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS 1 with 0 being the highest priority interrupt void XIntc_Disable Xintc InstancePtr u8 Id Description Disables the interrupt source provided as the argument Id such that the interrupt controller does not cause interrupts for the specified Id The interrupt controller continues to hold an interrupt condition for the Id but does not cause an interrupt Parameters InstancePtr is a pointer to the XIntc instance Id contains the ID of the interrupt source and should be in the range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS 1 with 0 b
191. here source is a list of ports that are driving the given signal sink is a list of ports that are being driven by the given signal all is a list of all ports connected to the given signal 234 www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 XILINX EDK Hardware Tcl Commands xget_hw_ioif handle lt handle gt lt ioif_name gt Description Arguments Returns the handle to an I O interface associated with the handle lt hand1le gt is the handle to an MPD or a merged IP instance If an original IP instance handle is provided this API returns a NULL lt ioif_name gt is the name of the I O interface whose handle is required If lt ioi f_name gt is specified as an asterisk the API returns a list of I O interface handles To access an individual I O interface handle you can iterate over the list in Tcl xget_hw_ioif value lt handle gt lt ioif_name gt Description Arguments Returns the value of the I O interface The value is specified in the MPD file and cannot be overwritten in MHS lt handle gt is the handle to an MPD or a merged IP instance lt ioif_name gt is the name of the I O interface whose value is required xget_hw_ipinst_ handle lt mhs_handle gt lt ipinst_name gt Description Arguments Returns the handle of the specified IP instance lt mhs_hand1e gt is the handle to either an original MHS or a merged MHS lt ipinst_name gt is the nam
192. ibraries are used in the place of the default emulation routines provided by GCC and simple string routines provided by Newlib The performance libraries show an average of three times increase in speed on applications that heavily use these routines The SourceForge project web page contains more information and detailed documentation A link to that page is provided in the Additional Resources section of this chapter Caution You cannot use the performance libraries in conjunction with the mfpu switch They are incompatible mno clearbss This option is useful for compiling programs used in simulation According to the C language standard uninitialized global variables are allocated in the bss section and are guaranteed to have the value 0 when the program starts execution Typically this is achieved by the C startup files running a loop to fill the bss section with zero when the program starts execution Additionally optimizing compilers will also allocate global variables that are assigned zero in C code to the bss section Ina simulation environment the two language features above can be unwanted overhead Some simulators automatically zero the whole memory Even in a normal environment you can write C code that does not rely on global variables being zero initially This switch is useful for these scenarios It causes the C startup files to not initialize the bss section with zeroes It also internally forces the compiler not to all
193. ibrary_Path gt lt Library_Name gt pcores as specified by the lp option 3 The XILINX_EDK hw lt Library_Name gt pcores Note Directory path names are case sensitive in Linux Ensure that you use pcore and not Pcore Ip lt library_path gt lt Library Name gt drivers sw_services X10066 pcores Figure 4 1 Peripheral Directory Structure From the pcores directory the root directory is the lt peripheral_name gt From the root directory the underlying directory structure is as follows data hdl netlist Output Files Platgen produces directories and files from the project directory in the following underlying directory structure hdl implementation synthesis HDL Directory The hd1 directory contains the following files e system vhd v is the HDL file of the embedded processor system as defined in the MHS and the toplevel file for your project e system_stub vhd v is the toplevel template HDL file of the instantiation of the system Use this file as a starting point for your own toplevel HDL file e lt inst gt _wrapper vhd v is the HDL wrapper file for the of individual IP components defined in the MHS Embedded System Tools Reference Manual www xilinx com 43 UG111 July 6 2011 Chapter 4 Platform Generator Platgen XILINX Implementation Directory The implementation directory contains implementation netlist files with the naming convention lt instance_na
194. ibutes Functions interrupt_handler This attribute saves the machine status register and all the volatiles in addition to the non volatile registers rtid returns from the interrupt handler If the interrupt handler function is a leaf function only those volatiles which are used by the function are saved save_volatiles This attribute is similar to interrupt_handler but it uses rtsd to return to the interrupted function instead of rtid Embedded System Tools Reference Manual www xilinx com 113 UG111 July 6 2011 Chapter 9 GNU Compiler Tools XILINX PowerPC Compiler Usage and Options PowerPC Compiler Options Quick Reference PowerPC Compiler Options mcpu 440 mfpu sp_lite sp_full dp_lite dp_full none mppcperflib mno clearbss Linker Options defsym _START_ADDR value PowerPC Compiler Options The PowerPC processor GNU compiler powerpc eabi gcc is built out of the sources for the PowerPC processor port as distributed by GNU foundation The compiler is customized for Xilinx purposes The features and options that are unique to the version distributed with EDK are described in the following sections When compiling with the PowerPC processor compiler the pre processor automatically provides the definition __PPc__ You can use this definition in any conditional code that you have mcpu 440 Target code for the 440 processor This includes instruction scheduling optimizations enable or dis
195. ice XMD_CONNECT The connect command used in XMD to connect to the processor Manual Conversion of ELF Files to SREC for Bootloader Applications If you want to create SREC images of your ELF file manually instead of using the auto convert feature in XPS you can use the command line tools For example to create a final software application image named myexecutable elf navigate in the console of your operating system Cygwin on Windows platforms to the folder containing this ELF file and type the following lt platform gt objcopy O srec myexecutable elf myexecutable srec where lt plat form gt is powerpc eabi if your processor is a PowerPC 405 or 440 processor or mb if your processor is a MicroBlaze This creates an SREC file that you can then use as appropriate The utilities mb obj copy and powerpc eabi obj copy are GNU binaries that ship with EDK For information about creating a bootloader from within a GUI see the Xilinx Platform Studio Help Appendix E Additional Resources contains links to the help Embedded System Tools Reference Manual www xilinx com 193 UG111 July 6 2011 Chapter 14 Flash Memory Programming XILINX Operational Characteristics and Workarounds Handling Xilinx Platform Flash Modes Xilinx Platform Flash memory devices initialize in synchronous mode You must set these devices to asynchronous mode before performing device operations When using the Xilinx Software Development Kit you can se
196. ided in Additional Resources page 261 The MicroBlaze linker uses linker scripts to assign sections to memory These are listed in the following section www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX MicroBlaze Compiler Usage and Options MicroBlaze Linker Script Sections Table 9 7 lists the input sections that are assigned by MicroBlaze linker scripts Table 9 7 Section Names and Descriptions Section Description vectors reset Reset vector code vectors sw_exception Software exception vector code vectors interrupt Hardware Interrupt vector code vectors hw_exception Hardware exception vector code text Program instructions from code in functions and global assembly statements rodata Read only variables sdata2 Small read only static and global variables with initial values data Static and global variables with initial values Initialized to zero by the boot code sdata Small static and global variables with initial values sbss2 Small read only static and global variables without initial values Initialized to zero by boot code sbss Small static and global variable without initial values Initialized to zero by the boot code bss Static and global variables without initial values Initialized to zero by the boot code heap Section of memory defined for the heap stack Section of memory defined for the stack
197. if Status XST_SUCCESS return XST_FAILURE Enable the interrupt for the timer counter z7 XIntc_Enable IntcInstancePtr IntrId Initialize the exception table z Xil_ExceptionInit Register the interrupt controller handler with the exception table aay Xil_ExceptionRegisterHandler XIL_EXCEPTION_ID_INT Xil_ExceptionHandler XIntc_InterruptHandler IntcInstancePtr Enable exceptions z Xil_ExceptionEnable if Status XST_SUCCESS return XST_FAILURE Setup the handler for the timer counter that will be called from the interrupt context when the timer expires specify a pointer to the Embedded System Tools Reference Manual www xilinx com 225 UG111 July 06 2011 Appendix B Interrupt Management XILINX timer counter driver instance as the callback reference so the handler is able to access the instance data XTmrCtr_SetHandler TmrCtriInstancePtr TimerCounterHandler TmrCtriInstancePtr Enable the interrupt of the timer counter so interrupts will occur and use auto reload mode such that the timer counter will reload itself automatically and continue repeatedly without this option it would expire once only 7 XTmrCtr_SetOptions TmrCtrInstancePtr TmrCtrNumber XTC_INT_MODE_OPTION XTC_AUTO_RELOAD_OPTION Set a reset value for the timer counter such that it will expire ear
198. igure 8 1 on page 76 e The OS_NAME attribute allows you to specify any name for your OS which is also the name of the OS directory e The source files and make file for the OS must be in the src subdirectory under the lt os_name gt directory e The make file should have the targets include and libs e Each OS must contain an MLD file and a Tel file in the data subdirectory Look at the existing EDK OSs to understand the structures Refer to the Microprocessor Library Definition MLD chapter in the Platform Specification Format Reference Manual for details on how to write an MLD and its corresponding Tcl file A link to the document is supplied in Appendix E Additional Resources Additional Resources For more information refer to the following documents Links to these documents are provided in Appendix E Additional Resources e Platform Specification Format Reference Manual http www xilinx com ise embedded edk_docs htm e OS and Libraries Document Collection http www xilinx com ise embedded edk_docs htm e Device Driver Programmer Guide is located in the doc usenglish folder of your EDK installation file name xilinx drivers _guide pdf Embedded System Tools Reference Manual www xilinx com 81 UG111 July 6 2011 Chapter 8 Library Generator Libgen 82 www xilinx com XILINX Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Chapter 9 GNU Compiler Tools
199. ilar to the rodata section It contains small read only data of size less than 8 bytes All data in this section is accessed with reference to the read only small data anchor This ensures that all the contents of this section are accessed using a single instruction You can change the size of the data going into this section with the G option to the compiler This section has the r read only and the i initialized flags Embedded System Tools Reference Manual www xilinx com 95 UG111 July 6 2011 96 Chapter 9 GNU Compiler Tools XILINX data This section contains read write data and has the w read write and the i initialized flags It must be mapped to initialized random access memory RAM It cannot be mapped to a ROM sdata This section contains small read write data of a size less than 8 bytes You can change the size of the data going into this section with the G option All data in this section is accessed with reference to the read write small data anchor This ensures that all contents of the section can be accessed using a single instruction This section has the w read write and the i initialized flags and must be mapped to initialized RAM sbss2 This section contains small read only un initialized data of a size less than 8 bytes You can change the size of the data going into this section with the G option This section has the r read flag and can be mapped to ROM sbss This section contains
200. iles and directories are generated in the output directory The input file filename mss is taken from the current working directory This output directory is also called OUTPUT_DIR and the directory from which Libgen is invoked is called YOUR_PROJECT for convenience in the documentation Source directory s d lt source_dir gt Specifies the source directory lt source_dir gt for searching the input files The default is the current working directory Pathtoasoftware lp lt Repository_Path gt Specifies a library containing repositories of user component peripherals drivers OSs and libraries Libgen looks for the repository following Drivers in the directory lt Library_Path gt drivers Libraries in the directory lt Library_Path gt sw_services OSs in the directory lt Library_Path gt bsp Hardware hw lt hwspecfile xml gt Specifies the hardware specification file XML to be used Specification File for Libgen The hardware specification file describes the complete hardware system to LibGen Libraries lib Use this option to copy libraries and drivers but not to compile them Processor pe This command runs Libgen for a specific processor instance instance specific lt processor_instance_name gt Libgen run Load Paths Figure 8 1 shows the directory structure of peripherals drivers libraries and operating systems lp lt library_path gt lt Library Name gt boards
201. ilinx com 117 UG111 July 6 2011 Chapter 9 GNU Compiler Tools XILINX Startup Files When the compiler forms an executable it includes pre compiled startup and end files in the final link command Startup files set up the language and the platform environment before your application code can execute Startup files typically do the following e Set up any reset interrupt and exception vectors as required e Set up stack pointer small data anchors and other registers as required e Clear the BSS memory regions to zero e Invoke language initialization functions such as C constructors e Initialize the hardware sub system For example if the program is to be profiled initialize the profiling timers e Set up arguments for and invoke the main procedure End files include code that must execute after your program is finished End files typically e Invoke language cleanup functions such as C destructors e Clean up the hardware subsystem For example if the program is being profiled clean up the profiling subsystem Table 9 12 lists the register initialization in the C runtime files Table 9 12 Register Initialization in C Runtime Files Register Value Description ri _stack 8 Stack pointer register initializes the bottom of the allocated stack offset by 16 bytes The 16 bytes can be used for passing in arguments r2 _SDA2_BASE _SDA2_BASE_ is the read only small data anchor address
202. imulation XILINX Bus Functional Simulation Methods 54 There are two software packages that allow you to perform Bus Functional Simulation and each applies its own methodology e IBM CoreConnect Toolkit e Xilinx EDK BFM Package e AXIBFM These software packages are not included with EDK but they are required if you intend to perform bus functional simulation You can download IBM CoreConnect Toolkit free of charge after you obtain a license for the IBM CoreConnect Bus Architecture Licensing CoreConnect provides access to a wealth of documentation Bus Functional Models and the Bus Functional Compiler Xilinx provides a Web based licensing mechanism that lets you obtain CoreConnect from the Xilinx web site To license CoreConnect use an internet browser to access http www xilinx com products ipcenter dr_pcentral_coreconnect htm After the request is approved typically within 24 hours you receive an E mail granting you access to the protected web site from which to download the toolkit For further documentation on the CoreConnect Bus Architecture refer to the IBM CoreConnect web site http www 01 ibm com chips techlib techlib nsf products CoreConnect_Bus_Architecture Note There are some differences between IBM CoreConnect and the Xilinx implementation of CoreConnect These are described in the Processor IP Reference Guide available in your XILINX_EDK doc usenglish directory Refer to the following section
203. in terms which are defined in the following subsections Original MHS Handle original _mhs_ handle The handle that points to the MHS information only This handle does not contain any MPD information If an IP parameter has not been specified in the MHS this handle does not contain that parameter Merged MHS Handle merged_mhs_handle The handle that points to both the MHS and MPD information A hardware datastructure merged object is formed when the tools merge the MHS and MPD information Note Various Tcl procedures are also called within batch tools such as Platgen Libgen and Simgen Handles provided through batch tools always refer to the merged MHS handle You do not have access to the original MHS handle from the batch tools The original MHS handle is needed only when you must modify the design using the provided APIs so that the generated MHS design file can be updated Original IP Instance Handle original_1P_handle A handle to an IP instance obtained from the original MHS handle that contains information present only in the MHS file Merged IP Instance Handle merged_IP_handle Refers to the IP handle obtained from the merged MHS handle The merged IP instance handle contains both MHS and MPD information Note Batch tools such as Platgen provide access to the merged IP instance handle only and not the original IP instance handle Consequently the various property handles the parameter and port handles for example
204. inear_Flash_address DIR O VEC 0 23 IO_IF Linear_Flash IO_IS address PORT Linear_Flash_data DIR IO VEC 0 15 IO_IF Linear_Flash IO_IS data PORT Linear_Flash_ce_n DIR O IO_IF Linear _Flash IO_IS ce_n PORT Linear_Flash_oe_n DIR O IO_IF Linear _Flash IO_IS oe_n PORT Linear_Flash_we_n DIR O IO_IF Linear_Flash IO_IS we_n PORT Linear_Flash_reset DIR O IO_IF Linear_Flash IO_IS reset PORT Linear_Flash_adv_n DIR O IO_IF Linear_Flash IO_IS adv_n Embedded System Tools Reference Manual www xilinx com 205 UG111 July 6 2011 Chapter 16 Microprocessor Peripheral Definition Translation tool MPDX g XILINX Define Constraints 206 Constraints are captured in a user provided CSV file and a Tcl file The CSV file contains pin constraints and the Tcl file contains more complex constraints like timing constraints The file names are e CSV file lt board gt _pins csv e Tel file lt board gt tcl XBD2 constraint specification is done with TGI calls to IP XACT data model that explores the topology of the design Pin location constraints are associated with the port element within the model capture of component XML Constraints are in UCF format Figure 16 1 illustrates the constraint delivery model START X12096 Figure 16 1 Constraint Delivery Model CSV Pin File Designers often use a CSV file during FPGA design to capture pin locati
205. inst gt lt elf type sim imp both gt lt elf file gt Option Name Description procinst The processor instance elf type The type of ELF file s to add or update sim simulation ELF file imp implementation ELF file both both simulation and implementation ELF files lt elf file gt The file name to add update Deleting an ELF File You can delete the ELF file associated with a processor instance using this command xdel_elf lt procinst gt lt elf type sim imp both gt Option Name Description procinst The processor instance elf type The type of ELF file s to delete sim simulation ELF file imp implementation ELF file both both simulation and implementation ELF files Archiving Your Project Files To archive a project use the command xps_archiver The xps_archiver tool compacts the files into a zip file Refer to the XPS Online Help for the list of files that are archived Restrictions XMP Changes Xilinx recommends that you do not edit the XMP file manually The XPS batch mode supports changing project options through commands Any other changes must be done from XPS Embedded System Tools Reference Manual www xilinx com 49 UG111 July 6 2011 Chapter 5 Command Line Mode 50 www xilinx com XILINX Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Chapter 6 Bus Functional Model Simulation This chapter describes B
206. int the output of most of these commands and provide more options While the Tcl wrappers are backward compatible the x lt name gt commands will be deprecated The following Tcl command subsections are e Program Initialization Options e Register Memory Options e Program Control Options e Program Trace and Profile Options e Miscellaneous Commands Embedded System Tools Reference Manual www xilinx com 163 UG111 July 6 2011 Chapter 10 Xilinx Microprocessor Debugger XMD Program Initialization Options Table 10 16 Program Initialization Option XILINX Option xconnect lt target gt mb ppc mdm lt connect type gt options Description Connects to a processor or a peripheral target Valid target types are mb ppc and mdm Refer to Connect Command Options page 140 for more information on options xdebugconfig lt target id gt step mode lt Step Type gt memory datawidth_matching disable enable reset_on_run system enable processor enable disable reset_on_data_dow system enable processor enable disable run_poll_interval lt time in millisec gt Configures the debug session for the target For additional information refer to the Configure Debug Session page 160 xdisconnect lt target id gt cable Disconnects from the target Use the cable option command to disconnect from cable and all targets xdownload lt target_id gt lt filename gt
207. interconnect The master interfaces specify the number of variable low order ID bits using the C_ lt BusI gt _THREAD_ID_WIDTH parameter The tools then take into account the value of THREAD_ID_WIDTH of all the interfaces and generate unique Base IDs for each interface The interconnect does some bookkeeping to enable the master interfaces connected to it to issue multiple transactions at once and ensures that they are returned in order It appends the Base ID value to all the transactions that the master issues and it informs the slave about the number of bits that it appended The slave then ignores those bits in processing the transaction When the response from the slave reaches the interconnect it strips off those bits that it appended before sending the response to the master Ideally the number of bits that the interconnect appends to make the master interfaces unique should be as low as possible to minimize the packet size The tools follow a general algorithm to generate the BASE ID values and the values that the tools generate may not always be optimal To optimize it further you can override the values generated by the tools by specifying the BASE IDs in the MHS However if you chooses to override even a single BASE ID you must specify the BASE ID values for all the master interfaces in the design Embedded System Tools Reference Manual www xilinx com 257 UG111 July 06 2011 Appendix
208. inx com ise embedded edk_docs htm Xilinx XPS EDK Supported IP website http www xilinx com ise embedded edk_ip htm Xilinx EDK Example website http www xilinx com ise embedded edk_examples htm Xilinx Tutorial website http www xilinx com support documentation dt_edk_edk13 2_tutorials htm Xilinx Data Sheets http www xilinx com support documentation data_sheets htm Xilinx Problem Solvers http www xilinx com support troubleshoot psolvers htm Xilinx ISE Manuals http www xilinx com support software_manuals htm Additional Xilinx Documentation http www xilinx com support library htm GNU Manuals http www gnu org manual IBM CoreConnect Technology http www xilinx com products intellectual property dr_pcentral_coreconnect htm AXI BFM User Guide UG783 http www xilinx com support documentation sw_manuals xilinx13_2 ug783_axi_bfm pdf www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011
209. ion Design Guide to learn more about compiling and using Xilinx ISE simulation libraries A link to the documentation website is provided in Appendix E Additional Resources Simulation Models This section describes how and when each of three FPGA simulation models are implemented and provides instructions for creating simulation models using XPS batch mode At specific points in the design process Simgen creates an appropriate simulation model as shown in the following figure Figure 7 1 illustrates the FPGA design simulation stages Design Design Implemented Netlist Implementation Design Netlist Design Synthesis Design Entry 2 Behavioral Structural Simulation Simulation Timing Simulation Functional Simulation UG111_01_111903 Figure 7 1 FPGA Design Simulation Stages Embedded System Tools Reference Manual www xilinx com 63 UG111 July 6 2011 64 Chapter 7 Simulation Model Generator Simgen XILINX Behavioral Models To create a behavioral simulation model as displayed in the following figure Simgen requires an MHS file as input Simgen creates a set of HDL files that model the functionality of the design Optionally Simgen can generate a compile script for a specified vendor simulator If specified Simgen can generate HDL files with data to initialize block RAMs associated with any processor that exists in the design This data is obtained from an existing Executable Lin
210. ion Management Wizard 00000 ec cece cece 200 Chapter 16 Microprocessor Peripheral Definition Translation tool MPDX DO De 201 Define Constraints 0 0 ccc ccc cece cee cece nee e ee en ene enenns 206 Appendix A GNU Utilities General Purpose Utility for MicroBlaze and PowerPC 209 Utilities Specific to MicroBlaze and PowerPC 00 00005 209 Other Programs and Files 3 25 cc460 ce de unnan unran edi panda be elemendG Ra aides 211 Appendix B Interrupt Management HardWare SCtUps ciinsde bese tdeawnen tah inde Pawnee eden tee aera uous 213 Software Setup and Interrupt Flow 000 c cece cece eee 214 Software APIS eiee eenden esee ee e e e aa EE 219 Appendix C EDK Tcl Interface Introduction 5 134 oe tages ne cha te ne a ie E a oere Eat 229 Understanding Handles 15 2 5243 orien tw caaw dn naw ey naw adain heed entire tn Man 229 Data Structure Creation c2 iia sed cesdin edi ciidnineieniedene ied tiedeakd 230 Tel Command Usagers cc iv ise nwiieseenkeeereguanegeersGperseanivdavidis es 231 EDK Hardware Tcl Commands 0 0 c cece cence eee eee 232 Tcl Example Procedures i scnieeawi eka ri east d eeeti arene i hina b ides 240 Tcl Flow During Hardware Platform Generation 248 Additional Keywords in the Merged Hardware Datastructure 253 Appendix D Interconnect Settings and Parameter Automa
211. is chapter describes the XPS command line no window mode Invoking XPS Command Line Mode To invoke the XPS command line or no window mode type the command xps nw at the LINUX Shell or Windows command prompt XPS performs the specified operation then presents a command prompt From the command line you can e Generate the make files e Run the complete project flow in batch mode e Create an XMP project file e Load a Xilinx Microprocessor Project XMP file created by the XPS GUI e Read and reload project files e Execute flow commands e Archive your project XPS batch provides the ability to query the EDK design database Tcl commands are available for this purpose In batch mode for XPS you can specify a Tcl script by using the scr option You can also provide an existing XMP file as input to XPS Creating a New Empty Project To create a new project with no components use the command xload new lt basename gt xmp XPS creates a project with an empty Microprocessor Hardware Specification MHS file All of the files have same base name as the XMP file If XPS finds an existing project in the directory with same base name then the XMP file is overwritten However if an MHS file with same name is found then they are read in as part of the new project Embedded System Tools Reference Manual www xilinx com 45 UG111 July 6 2011 Chapter 5 Command Line Mode XILINX Creating a New Project With an Existing MHS
212. is initialization file is used when the application is to be profiled in a software intrusive manner In addition to all the common CRT actions described it also invokes the _profile_init routine before invoking main This initializes the software profiling library before your code executes Similarly upon exit from main it invokes the _profile_clean routine which cleans up the profiling library xil sim crt0 o This initialization file is used when the application is compiled with the mno clearbss switch It performs all the common CRT setup actions except that it does not clear the bss section to Zero xil sim pgcrt0 o This initialization file is used when the application is compiled with the mno clearbss switch It performs all the common CRT setup actions except that it does not clear the bss section to zero It also invokes the _profile_init routine before invoking main This initializes the software profiling library before your code executes Similarly upon exit from main it invokes the _profile_clean routine which cleans up the profiling library Other files The compiler also uses standard start and end files for C language support ecrti o crtbegin o crtend o and crtn o These files are standard compiler files that provide the content for the init fini ctors and dtors sections The PowerPC default and generated linker scripts also make boot o a startup file This file is present in the standalone package for
213. is parameter is present on the AXI slave interfaces the tools automatically update it to optimize the design The tools analyze the design at run time When there are no masters connected to the interconnect that can generate narrow bursts they set this parameter on the slave to 0 to disable narrow burst support logic and save resources C_ lt Buslf gt _SUPPORTS_READ If this parameter is present on the AXI slave interfaces the tools automatically update it to optimize the design The tools analyze the design at run time If there are no masters connected to the interconnect that use the AR and R channels they set this parameter on the slave to 0 to disable AR and R channels and save resources C_ lt Buslf gt _SUPPORTS_WRITE If this parameter is present on the AXI slave interfaces it is automatically updated by the tools to optimize the design The tools analyze the design at run time If there are no masters connected to the interconnect that use the AW and W channels they set this parameter on the slave to 0 to disable AW and W channels and save resources User Signal Width parameters on the AXI interconnect The tools analyze the design at runtime and check the value of the user signal widths of all masters and slaves connected to the interconnect They then compute the maximum value of the channel width for the AW AR and W channels between all the masters and set those values on the interconnect Similarly they compute the ma
214. isplay lt test_harness gt _list do Helper script to set up simulation tabular list display ModelSim only lt instance gt _wave do sv tcl Helper script to set up simulation waveform display for the specified instance lt instance gt _list do Helper script to set up simulation tabular list display for the specified instance ModelSim only Memory Initialization If a design contains banks of memory for a system the corresponding memory simulation models can be initialized with data You can specify a list of ELF files to associate to a given processor instance using the pe switch The compiled executable files are generated with the appropriate GNU Compiler Collection GCC compiler or assembler from corresponding C or assembly source code Note Memory initialization of structural simulation models is only supported when the netlist file has hierarchy preserved For VHDL Verilog simulation models run Simgen with the pe option to generate mem files These mem files contain a configuration for the system with all initialization values For example simgen system mhs pe mblaze executable elf 1 vhdl simgen system mhs pe mblaze executable elf 1 verilog These mem files are used along with your system to initialize memory The BRAM blocks connected to the mblaze processor contain the data in executable elf Test Benches Simgen is capable of creating test bench templates If you use the tb swit
215. ith Interrupt Controller 218 www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 XILINX Software APIs Software APIs This section provides an overview of the software APIs involved in handling and managing interrupts lists the available Software APIs by processor type and provides examples of interrupt management code Note This chapter is not meant to cover the APIs comprehensively Refer to the interrupt controller device driver documentation as well as the reference documentation for the Standalone platform to for all the details of the APIs Interrupt Controller Driver The Xilinx interrupt controller supports the following features Enabling and disabling specific individual interrupts Acknowledging specific individual interrupts Attaching specific callback function to handle interrupt source Enabling and disabling the master Sending a single callback per interrupt or handling all pending interrupts for each interrupt of the processor The acknowledgement of the interrupt within the interrupt controller is selectable either prior to calling the device handler or after the handler is called Interrupt signal inputs are either edge or level signal consequently support for those inputs is required Edge driven interrupt signals require that the interrupt is acknowledged prior to the interrupt being serviced to prevent the loss of interrupts which are occurring close together Level driven i
216. itialization functions and displays usage instructions for creating waveform and list ModelSim only windows using the waveform and list scripts The top level scripts invoke instance specific scripts You might need to edit hierarchical path names in the helper scripts for test harnesses not created by Simgen Commands in the scripts are commented or not commented to define the displayed set of signals Editing the top level waveform or list scripts allows you to include or exclude signals for an instance editing the instance level scripts allows you to include or exclude individual port signals For timing simulations only top level ports are displayed www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Chapter 8 Library Generator Libgen This chapter describes the Library Generator utility Libgen which is required for the generation of libraries and drivers for embedded processors Overview Libgen is the first Embedded Design Kit EDK tool that you run to configure libraries and device drivers Libgen takes an XML hardware specification file and a Microprocessor Software Specification MSS file that you create The hardware specification file defines the hardware system to Libgen and the MSS file describes the content and configuration of the software platform for a particular processor Components are instantiated as blocks in the MSS file and configuration is specified using parameters Libg
217. itializer BitInit XILINX Table 12 1 BitInit Syntax Options Cont d Option Command Description Specify the Processor pe Specifies the name of the processor instance in associated ELF file that Instance name and list forms its instruction memory This option can be repeated once for each of ELF files processor instance in the design Only one ELF per processor can be initialized into block RAM Quiet mode quiet Runs the tool in quiet mode In this mode it does not print status warning or informational messages while running It prints only error messages on the console Display version v Displays the version and then quits BitInit also produces a file named data2mem dmr which is the log file generated during invocation of the Data2MEM utility 176 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Chapter 13 System ACE File Generator GenACE This chapter describes the steps to generate Xilinx System ACE technology configuration files from an FPGA bitstream and Executable Linked Format ELF data files The generated ACE file can be used to e Configure the FPGA e Initialize block RAM e Initialize external memory with valid program or data e Bootup the processor in a production system EDK provides a Tool Command Language Tcl script genace tcl which uses Xilinx Microprocessor Debug XMD commands to generate ACE files ACE files can b
218. ize m_axi_sg_awburst AXI4 Master Inputs lt BI gt _awready lt BI gt _wready lt BI gt _bresp lt BI gt _bvalid lt BI gt _arready lt BI gt _rdata lt BI gt _rresp lt BI gt _rlast lt BI gt _rvalid Examples m_axi_sg_awready m_axi_sg_bresp m_axi_sg_bvalid ou ou ou ou ou ou ou ou ou ou ou ou OU ou ou ou ou ou ou ou ou ou ou in in in in in in in in in in in in www xilinx com taogata EE EE OPE ET EF EF OPE EE ET EE OER ORE EF OPE CF ET F Cr Aa std_logic_vector C_ lt BI gt _ADDR_WIDTH 1 downto 0 std_logic_vector 7 downto 0 std_logic_vector 2 downto 0 std_logic_vector 1 downto 0 std_logic_vector 2 downto 0 std_logic_vector 3 downto 0 std_logic std_logic_vector C_ lt BI gt _DATA WIDTH 1 downto 0 std_logic_vector C_ lt BI gt _DATA_WIDTH 9 1downto std_logic std_logic std_logic std_logic_vector C_ lt BI gt _ADDR_WIDTH 1 downto 0 std_logic_vector 7 downto 0 std_logic_vector 2 downto 0 std_logic_vector 1 downto 0 std_logic_vector 2 downto 0 std_logic_vector 3 downto 0 std_logic std_logic std_logic_vector 7 downto 0 std_logic_vector 2 downto 0 std_logic_vector 1 downto 0 std_logic std_logic std_logic_vector 1 downto 0 std_logic std_logic std_logic_vector C_ lt BI gt _DATA_WIDTH 1 downto 0 std_logic_vector 1 downto 0 std_logic std_logic std_logic std_logic_vector 1 downto
219. k errors due to multiple definition of symbols if you do so Position Independent Code The GNU compiler for MicroBlaze supports the fPIC and fpic switches These switches enable Position Independent Code PIC generation in the compiler This feature is used by the Linux operating system only for MicroBlaze to implement shared libraries and relocatable executables The scheme uses a Global Offset Table GOT to relocate all data accesses in the generated code and a Procedure Linkage Table PLT for making function calls into shared libraries This is the standard convention in GNU based platforms for generating relocatable code and for dynamically linking against shared libraries MicroBlaze Application Binary Interface The GNU compiler for MicroBlaze uses the Application Binary Interface ABI defined in the MicroBlaze Processor Reference Guide Refer to the ABI documentation for register and stack usage conventions as well as a description of the standard memory model used by the compiler A link to the document is provided in Additional Resources page 261 MicroBlaze Assembler The mb as assembler for the Xilinx MicroBlaze soft processor supports the same set of options supported by the standard GNU compiler tools It also supports the same set of assembler directives supported by the standard GNU assembler The mb as assembler supports all the opcodes in the MicroBlaze machine instruction set with the exception of the imm instruction
220. ked Format ELF file Figure 7 2 illustrates the behavioral simulation model generation ELF Sa UG111_02_101705 Figure 7 2 Behavioral Simulation Model Generation Structural Models To create a structural simulation model as shown in the following figure Simgen requires an MHS file as input and associated synthesized netlist files From these netlist files Simgen creates a set of HDL files that structurally model the functionality of the design Optionally Simgen can generate a compile script for a specified vendor simulator If specified Simgen can generate HDL files with data to initialize block RAMs associated with any processor that exists in the design This data is obtained from an existing ELF file Figure 7 3 illustrates the structural simulation model simulation generation sero UG111_03_101705 Figure 7 3 Structural Simulation Model Generation Note The EDK design flow is modular Platgen generates a set of netlist files that are used by Simgen to generate structural simulation models www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Simulation Models Timing Models To create a timing simulation model as displayed in Figure 7 4 Simgen requires an MHS file as input and an associated implemented netlist file From this netlist file Simgen creates an HDL file that models the design and a Standard Data Format SDF file with the appropriate timing inf
221. kk kkk kkk kk kk kk kkk int TmrCtrIntrExample XIntc IntcInstancePtr XTmrCtr TmrCtrInstancePtr ul6 Deviceld ul6 Intrid u8 TmrCtrNumber int Status int LastTimerExpired 0 Initialize the timer counter so that it s ready to use specify the device ID that is generated in xparameters h cf Status XTmrCtr_Initialize TmrCtrinstancePtr Deviceld if Status XST_SUCCESS return XST_FAILURE Initialize the interrupt controller driver so that it s ready to use specify the device ID that is generated in xparameters h 224 www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 g XILINX Software APIs Ry Status XIntc_Initialize IntcInstancePtr INTC_DEVICE_ID if Status XST_SUCCESS return XST_FAILURE Connect a device driver handler that will be called when an interrupt for the device occurs the device driver handler performs the specific interrupt processing for the device z7 Status XIntc_Connect IntcInstancePtr IntrId XInterruptHandler XTmrCtr_InterruptHandler void TmrCtriInstancePtr if Status XST_SUCCESS return XST_FAILURE Start the interrupt controller such that interrupts are enabled for all devices that cause interrupts specific real mode so that the timer counter can cause interrupts thru the interrupt controller Status XIntc_Start IntcInstancePtr XIN_REAL_MODE
222. l_archsupport_proc mhsinst print_deprecated_helper_core_message S mhsinst proc_common_v1_00_a The PRINT_DEPRECATED_HELPER_CORE_MESSAGE procedure is provided by EDK tools to generate a standard message for deprecated cores It takes the handle to the top level core and the name of deprecated helper core as arguments Additional Keywords in the Merged Hardware Datastructure Some keywords sub properties that are created optionally on parameters ports and bus interfaces in the merged hardware datastructure These are used internally by tools and can also be used by Tcl for DRCs These additional keywords are MHS_VALUE When the merged object is created it combines information from both MHS and MPD The default value is present in the MPD However these properties can be overridden in the MHS The tools have conditions when some values are auto computed and that auto computed value will override the values in MHS also The original value specified in MHS is then stored in the MHS_VALUE sub property e MPD_VALUE When the merged object is created it combines information from both MHS and MPD The default value is present in the MPD However these properties can be overridden in the MHS The tools have conditions when some values are auto computed and that auto computed value will override the values in MHS also The value specified in MPD is consequently stored in the MPD_VALUE sub property
223. language programmer should use the operand as is without using an imm instruction For example the following code adds the constant 200 000 to the contents of register r3 and stores the results in register r4 addi r4 r3 200000 The mb as assembler recognizes that this operand needs an imm instruction and inserts one automatically In addition to the standard MicroBlaze instruction set the mb as assembler also supports some pseudo op codes to ease the task of assembly programming Table 9 6 lists the supported pseudo opcodes Table 9 6 Pseudo Opcodes Supported by the GNU Assembler Pseudo Opcodes Explanation nop No operation Replaced by instruction or RO RO RO la Rd Ra Imm Replaced by instruction addik Rd Ra imm Rd Ra Imm not Rd Ra Replace by instruction xori Rd Ra 1 neg Rd Ra Replace by instruction rsub Rd Ra RO sub Rd Ra Rb Replace by instruction rsub Rd Rb Ra Embedded System Tools Reference Manual www xilinx com 105 UG111 July 6 2011 106 Chapter 9 GNU Compiler Tools XILINX MicroBlaze Linker Options The mb 1d linker for the MicroBlaze soft processor provides additional options to those supported by the GNU compiler tools The options are summarized in this section defsym _TEXT START ADDR value By default the text section of the output code starts with the base address 0x28 0x800 in XMDStub mode This can be overridden by using the def
224. lect a check box to inform the Flash programming interface to treat the target device as Xilinx Platform Flash This setting enables an internal workaround in the programmer that sets the device to asynchronous mode before programming Handling Flash Devices with OxFO as the Read Reset Command The CFI specification defines the read reset command as 0xFF 0xF0 By default the flash programmer uses the 0xFF read reset command Certain devices require 0xF0 as the read reset command however the flash programmer is unable to determine this automatically Consequently you might encounter issues when programming newer devices In that event of an error occurring follow the documented steps inCustomizing Flash Programming page 191 then modify the define FRR_CMD 0xFF in the cfi c file to define FRR_CMD OxFO Handling Flash Devices with Conflicting Sector Layouts Some flash vendors store a different sector map in the CFI table and another based on the boot topology of the flash device in hardware Because the boot topology information is not standardized in CFI the flash programmer cannot determine the layout of your particular flash device If your flash hardware has a sector layout that is different from the one specified in the CFI table for the device then you must create a custom flash programming flow You must determine whether the device is a top boot or a bottom boot flash device In a top boot flash device the smallest sector
225. lier than letting it roll over from 0 the reset value is loaded into the timer counter when it is started 7 XTmrCtr_SetResetValue TmrCtrInstancePtr TmrCtrNumber RESET_VALUE Start the timer counter such that it s incrementing by default then wait for it to timeout a number of times ay XTmrCtr_Start TmrCtriInstancePtr TmrCtrNumber while 1 Wait for the first timer counter to expire as indicated by the shared variable which the handler will increment Xy while TimerExpired LastTimerExpired LastTimerExpired TimerExpired Tf it has expired a number of times then stop the timer counter and stop this example sf if TimerExpired 3 XTmrCtr_Stop TmrCtriInstancePtr TmrCtrNumber break Disable the interrupt for the timer counter ays XIntc_Disable IntcInstancePtr DevicelId return XST_SUCCESS EEEk kkk kk kkk kkk kkk EKER ERE RE KERR EKER ERE k k k k k k k k k k k RRR k k kk k kk kkk kkk kkk f 226 www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 XILINX Software APIs This function is the handler which performs processing for the timer counter It is called from an interrupt context such that the amount of processing performed should be minimized It is called when the timer counter expires if interrupts are enabled This handler provide
226. llowing PARAMETER PORT BUS_INTERFACI IO_INTERFACE or OPTION Le lt lt subprop_name gt is the name of the subproperty whose value is required For a list of sub properties refer to Microprocessor Peripheral Definition MPD in the Platform Specification Format Reference Manual and Additional Keywords in the Merged Hardware Datastructure page 253 xget_hw_ value lt handle gt Description Arguments Gets the value associated with the specified handle lt handle gt is of specified type If lt handle gt is of type IP instance its value is the IP module name For example if the handle refers to the MicroBlaze instance in the MHS file the value the API returns is the name of the IP that is microblaze Similarly to get the value of a parameter from a parameter handle you can use the same command Embedded System Tools Reference Manual www xilinx com 239 UG111 July 06 2011 Appendix C EDK Tel Interface XILINX Tcl Example Procedures The following are example Tcl procedures that use some of the hardware API Tel commands 240 Example 1 This procedure explains how to get a list of IPs of a particular IPTYPE Each IP provided in the EDK repository has a corresponding IP type specified by the IpTyPE option in the MPD file The merged_mhs_instance has the information from both the MHS file and the MPD file The process for getting a list of IPs of a particular 1PTYPE is 1
227. load address xdownload lt target_id gt data lt filename gt lt load_address gt Downloads the given ELF or data file using the data option onto the memory of the current target If no address is provided along with ELF file the download address is determined from the ELF file headers Otherwise it is treated as Position Independent Code PIC code and downloaded at the specified address and Register R20 is set to the start address according to the PIC code semantics XMD does not perform bounds checking with the exception of preventing writes into the XMDSTUB area address 0x0 to 0x800 xrcableesn Returns the ESN values of USB cables connected to the host machine xrjtagchain cable lt cable_options gt Returns the Jtag Device Chain information of the board connected to the host machine xfpga f lt bitstream gt cable lt cable_options gt configdevice lt configuration_options gt debugdevice lt device_name gt Loads the FPGA device bitstream and optionally the cable configuration and debug device options xload_sysfile hw lt hw_spec_file gt Loads the hardware specification file 164 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX XMD Internal Tcl Commands Table 10 16 Program Initialization Option Cont d Option xrut Session ID Description Authenticates the XMD session when comm
228. location Unencrypted EDK IP components can be compiled using Compxlib Precompiled libraries are provided for encrypted components 62 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Compxlib Utility Compxlib Utility Xilinx provides the Compxlib utility to compile the HDL libraries for Xilinx supported simulators Compxlib compiles the UNISIM SIMPRIM and XilinxCoreLib libraries for supported device architectures using the tools provided by the simulator vendor You must have an installation of the Xilinx implementation tools to compile your HDL libraries using Compxlib Run Compxlib with the help option if you need to display a brief description for the available options compxlib help Each simulator uses certain environment variables that you must set before invoking Compxlib Consult your simulator documentation to ensure that the environment is properly set up to run your simulator Note Make sure you use the p lt simulator_path gt option to point to the directory where the ModelSim executable is if it is not in your path The following is an example of a command for compiling Xilinx libraries for MTI_SE Compxlib s mti_se arch all 1 vhdl w dir This command compiles the necessary Xilinx libraries into the current working directory Refer to the Command Line Tools User Guide for information Compxlib Refer to the Simulating Your Design chapter of the Synthesis and Simulat
229. ls library When you create or import a peripheral XPS generates the Microprocessor Peripheral Definition MPD and Peripheral Analyze Order PAO files automatically e The MPD file defines the interface for the peripheral e The PAO file specifies to Platgen and Simgen what HDL files are required for compilation synthesis or simulation for the peripheral and in the order of those files For more information about MPD and PAO files see the Platform Specification Format Reference Manual A link to the document is available in Additional Resources page 261 For detailed information on using the features provided in the CIP wizard see the Xilinx Platform Studio Help Embedded System Tools Reference Manual www xilinx com 13 UG111 July 6 2011 14 Chapter 1 Embedded System and Tools Architecture Overview XILINX Platform Specification Utility PsfUtility and PSF2EDWARD Program The PsfUtility enables automatic generation of Microprocessor Peripheral Definition MPD files required to create an IP core compliant with EDK Features provided by this tool can be used with the help of the CIP wizard See Chapter 2 Platform Specification Utility PsfUtility The psf2Edward is a command line program that converts a Xilinx Embedded Development Kit EDK project into Edward an internal XML format for use in external programs such as the Software Development Kit SDK See Chapter 3 Psf2Edward Program Coprocesso
230. ls Reference Manual UG111 July 6 2011 XILINX Generating ACE Files Multiple FPGA Devices The assumed configuration is with two FPGA devices each with a single processor and a single ELF file The configuration of the board is specified in the options file This configuration requires multiple steps to generate the ACE file 1 Generate an SVF file for the first FPGA device The options file contains the following jprog target ppc_hw hw implementation download bit elf executablel elf ace fpgal ace board user configdevice devicenr 1 idcode 0x123e093 irlength 10 partname XC2VP4 configdevice devicenr 2 idcode 0x123e093 irlength 10 partname XC2VP4 debugdevice devicenr 1 cpunr 1 This generates the file fpga1 svf 2 Generate an SVF file for the second FPGA device The options file contains the following jprog target ppc_hw hw implementation download bit elf executable2 elf ace fpga2 ace board user configdevice devicenr 1 idcode 0x123e093 irlength 10 partname XC2VP4 configdevice devicenr 2 idcode 0x123e093 irlength 10 partname XC2VP4 debugdevice devicenr 2 cpunr 1 lt Note This generates the file fpga2 svf The change in Devicenr 3 Concatenate the files in the following order fpgal svf and fpga2 svf to final_system svf 4 Generate the ACE file by calling impact batch svf2ace scr Use the following SCR file svfi2ace wtck d m 16776192 i final_system svf
231. lt BI gt _awsize in std_logic_vector 2 downto 0 lt BI gt _awburst in std_logic_vector 1 downto 0 lt BI gt _awlock in std_logic lt BI gt _awcache in std_logic_vector 3 downto 0 lt BI gt _awprot in std_logic_vector 2 downto 0 lt BI gt _awqos in std_logic_vector 3 downto 0 lt BI gt _awvalid in std_logic lt BI gt _wdata in std_logic_vector C_ lt BI gt _DATA_WIDTH 1 downto 0 lt BI gt _wstrb in std_logic_vector C_ lt BI gt _DATA_WIDTH 8 1 downto 0 lt BI gt _wlast in std_logic lt BI gt _wvalid in std_logic lt BI gt _bready in std_logic lt BI gt _arid in std_logic_vector C_ lt BI gt _ID_WIDTH 1 downto 0 lt BI gt _araddr in std_logic_vector C_ lt BI gt _ADDR_WIDTH 1 downto 0 lt BI gt _arlen in std_logic_vector 7 downto 0 lt BI gt _arsize in std_logic_vector 2 downto 0 lt BI gt _arburst in std_logic_vector 1 downto 0 lt BI gt _arlock in std_logic lt BI gt _arcache in std_logic_vector 3 downto 0 lt BI gt _arprot in std_logic_vector 2 downto 0 lt BI gt _arqos in std_logic_vector 3 downto 0 lt BI gt _arvalid in std_logic lt BI gt _rready in std_logic Embedded System Tools Reference Manual www xilinx com 29 UG111 July 6 2011 Chapter 2 Platform Specification Utility PsfUtility XILINX Examples s_axi_arburst s_axi_arlock s_axi_arcache Master AXI4LITE Ports in in in std_logic std_logic std_logic Master AXI4LITE ports mus
232. m 223 UG111 July 06 2011 Appendix B Interrupt Management XILINX F F F F F F F F F F F TMRCTR_INTERRUPT_ID TIMER_CNTR_0O if Status XST_SUCCESS return XST_FAILURE return XST_SUCCESS KERR RKKEKKEKER KEKE RE RARE KK KEE KER EKER KERR KEK EKER KERR EKER KERR KERR RRR REEREREKERKEE EK Kk This function does a minimal test on the timer counter device and driver as a design example The purpose of this function is to illustrate how to use the XTmrCtr component It initializes a timer counter and then sets it up in compare mode with auto reload such that a periodic interrupt is generated This function uses interrupt driven mode of the timer counter paramIntcInstancePtr is a pointer to the Interrupt Controller driver Instance paramTmrCtrinstancePtr is a pointer to the XTmrCtr driver Instance paramDevicelId is the XPAR_ lt TmrCtr_instance gt _DEVICE_ID value from xparameters h paramIntriId is XPAR_ lt INTC_instance gt _ lt TmrCtr_instance gt _INTERRUPT_INTR o F F F F F F HF F value from xparameters h paramTmrCtrNumber is the number of the timer to which this handler is associated with returnXST_SUCCESS if the Test is successful otherwise XST_FAILURE noteThis function contains an infinite loop such that if interrupts are not working it may never return Kk kk kk k k k k k k KKK RK RAK KEK KEKE KEE KEK RK KEKE KEKE k k k k k kkk k k k
233. m a sub routine mb gcc looks for an attribute interrupt_handler in the declaration of the code This attribute is defined as follows void function_name __attribute__ interrupt_handler Note The attribute for the interrupt handler is to be given only in the prototype and not in the definition Interrupt handlers might also call other functions which might use volatile registers To maintain the correct values in the volatile registers the interrupt handler saves all the volatiles if the handler is a non leaf function Note Functions that have calls to other sub routines are called non eaf functions Interrupt handlers are defined in the MicroBlaze Hardware Specification MHS and the MicroBlaze Software Specification MSS files These definitions automatically add the attributes to the interrupt handler functions For more information refer to Appendix B Interrupt Management The interrupt handler uses the instruction rtid for returning to the interrupted function save_volatiles attribute The MicroBlaze compiler provides the attribute save_volatiles which is similar to the interrupt_handler attribute but returns using rtsd instead of rtid This attribute saves all the volatiles for non leaf functions and only the used volatiles in the case of leaf functions void function_name __attribute__ save_volatiles Table 9 10 lists the attributes with their functions Table 9 10 Use of Attributes Attr
234. m_update addr ffff8008 data 8899aabb_ccddeef Ff write addr ff 8000 size 0000 be 11111111 write addr f f 8008 size 0000 be 11111111 read addr f 8000 size 0000 be 11111111 read addr ff 8008 size 0000 be 11111111 Write and read 32 bit data using byte enable architecture mem_update addr fff 8010 data 11111111_22222222 write addr ffff 8010 size 0000 be 11110000 write addr ffff 8014 size 0000 be 00001111 read addr ff 8010 size 0000 be 11110000 read addr ff 8014 size 0000 be 00001111 Write and read 16 bit data using byte enable architecture mem_update addr ffff8020 data 33334444 55556666 write addr ff 8020 be 1100_0000 write addr ff 8022 be 0011_0000 write addr ff 8024 be 0000_1100 write addr ff 8026 be 0000_0011 read addr ff 8020 be 1100_0000 read addr ff 8022 be 0011_0000 read addr ff 8024 be 0000_1100 read addr ff 8026 be 0000_0011 Write and read 8 bit data using byte enable architecture mem_update addr ffff8030 data 778899aa_bbccddee write addr f 8030 be 1000_0000 write addr f 8031 be 0100_0000 write addr f 8032 be 0010_0000 write addr f 8033 be 0001_0000 write addr f 8034 be 0000_1000 write addr f 8035 be 0000_0100 write addr f 8036 be 0000_0010 write addr f 8037 be 0000_0001 read addr f 8030 be 1000_0000
235. mangles function names The primary difference between GCC and G is that G automatically sets the default language dialect to C irrespective of the file extension and if linking automatically pulls in the C support libraries This means that even if you compile C code ina c file with the G compiler it will mangle names Name mangling is a concept unique to C and other languages that support overloading of symbols A function is said to be overloaded if the same function can perform different actions based on the arguments passed in and can return different return values To support this C compilers encode the type of the function to be invoked in the function name avoiding multiple definitions of a function with the same name Embedded System Tools Reference Manual www xilinx com 87 UG111 July 6 2011 Chapter 9 GNU Compiler Tools XILINX 88 Be careful about name mangling if you decide to follow a mixed compilation mode with some source files containing C code and some others containing C code or using GCC for compiling certain files and G for compiling others To prevent name mangling of a C symbol you can use the following construct in the symbol declaration ifdef _ cplusplus extern C endif int foo int morefoo ifdef _ cplusplus endif Make these declarations available in a header file and use them in all source files This causes the compiler to use the C dialect when c
236. map std_logic_vector 0 to 3 Signal rx std_logic signal sys_clk std_logic signal sys_reset std_logic signal tx std_logic sys_clk gt sys_clk sys_reset gt sys_reset EX gt IX tx gt tx leds gt leds Clock generator for sys_clk process begin sys_clk lt wait for sys_clk_PHAS O Gl 70 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Memory Initialization loop wait for sys_clk_PERIOD 2 sys_clk lt not sys_clk end loop end process Reset Generator for sys_reset process begin sys_reset lt 0 wait for sys_reset_LENGTH sys_reset lt not sys_reset wait end process START USER CODE Do not remove this line User Put your stimulus here Code in this section will not be overwritten END USER CODE Do not remove this line end architecture STRUCTURE You can add your own VHDL code between the lines tagged BEGIN USER CODE and END USER CODE The code between these lines is maintained if simulation files are created again Any code outside these lines will be lost if a new test bench is created Verilog Test Bench Example timescale 1 ns 10 ps uselib lib unisims_ver module system_tb Li real sys_clk_PERIOD 10 real sys_clk_PHASE 2 5 real sys_reset_LENGTH 160 Internal signals reg 0 3 leds reg rx reg
237. me gt _wrapper ngc Synthesis Directory The synthesis directory contains the system prj scr synthesis project file BMM Flow Platgen generates the lt system gt bmm and the lt system gt _stub bmm in the lt Project_Name gt implementation directory The lt system gt bmm is used by the implementation tools when EDK is the top level system The lt system gt _stub is used by the implementation when EDK is a sub module of the top level system The EDK tools implementation tools flow using Data2MEM is as follows ngdbuild bm lt system gt bmm lt system gt ngc map par bitgen bd lt system gt elf Bitgen outputs lt system gt _bd bmm which contains the physical location of block RAMs A block RAM Memory Map BMM file contains a syntactic description of how individual block RAMs constitute a contiguous logical data space The lt system gt _bd bmm and lt system gt bit files are input to Data2MEM Data2MEM translates contiguous fragments of data into the proper initialization records for the Virtex series block RAMs Synthesis Netlist Cache An IP rebuild is triggered when one of the following changes occur 44 Instance name change Parameter value change Core version change Core is specified with the MPD CORE_STATE DEVELOPMENT option Core license change www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Chapter 5 Command Line Mode Th
238. ment Language lang verilog vhd1l Specifies the HDL language output Default vhd1 Log output log lt logfile log gt Specifies the log file Default platgen log Library path for lp lt Library_Path gt Adds lt Library_Path gt to the list of IP search directories A library user peripherals is a collection of repository areas and driver repositories Output od lt output_dir gt Specifies the output directory path directory Default The current directory Part name p lt partname gt Uses the specified part type to implement the design Instance name ti lt instname gt Specifies the top level instance name Top level tm lt top_module gt Specifies the top level module name module Top level toplevel yes no Specifies if the input design represents a whole design or a level of hierarchy Default yes Version v Displays the version number of Platgen and then exits without running the Platgen flow 42 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Load Path Load Path Figure 4 1 shows the peripheral directory structure To specify additional directories use one of the following options e Use the current directory from which Platgen was launched e Set the EDK tool lp option Platgen uses a search priority mechanism to locate peripherals in the following order 1 The pcores directory in the project directory 2 The lt L
239. meter while instantiating the mdm in a system UART input can also be provided from the host to the program running on MicroBlaze using the xuart w lt byte gt command You can use the terminal command to opena hyperterminal like interface to read and write from the UART interface The read_uart command provides interface to write to STDIO or to file Configure Debug Session Configure the debug session for a target using the debugconfig command You can configure the behavior of instruction stepping and memory access method of the debugger Usage debugconfig step_mode disable_interrupt enable_interrupt memory_datawidth_matching disable enable reset_on_run system enable processor enable disable reset_on_data_dow system enable processor enable disable Table 10 15 page 161 lists the debug configuration options 160 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Connect Command Options Table 10 15 Debug Configuration Options Option No Option Description Lists the current debug configuration for the current session step_mode disable interrupt enable_interrupt Configures how XMD handles instruction stepping disable_interrupt is the default mode The interrupts are disabled during step enable_interrupt enables interrupts during step If an interrupt occurs during step the interrupt is handled by the registered interrupt ha
240. ming stub on the target processor The in system programming stub requires a minimum of 8 KB of memory to operate A host Tcl script drives the in system flash programming stub with commands and data and completes the flash programming The flash programming tools do not process or interpret the image file to be programmed and the tools routinely program the file as is onto flash memory Your software and hardware application setup must infer the contents of the file being programmed Embedded System Tools Reference Manual www xilinx com 189 UG111 July 6 2011 Chapter 14 Flash Memory Programming XILINX Supported Flash Hardware 190 The flash programmer uses the Common Flash Interface CFI to query the flash devices so it requires that the flash device be CFI compliant The layout of the flash devices to form the total memory interface width is also important The following table lists the supported flash layouts and configurations If your flash layout does not match a configuration in Table 14 1 you must then customize the flash programming session Refer to Customizing Flash Programming on page 191 Table 14 1 Supported Flash Configurations x8 only capable device forming an 8 bit data bus x16 x8 capable device in x8 mode forming an 8 bit data bus x32 x8 capable device in x8 mode forming an 8 bit data bus x16 x8 capable device in x16 mode forming a 16 bit data bus Paired x8 only capable devices formi
241. ml401 XCF32P gt XC4VLX25 gt XC95144XL ML401 with ml401_es XCF32P gt XC4VLX25 ES gt XC95144XL V4LX25 ES ML402 ml402 XCF32P gt XC4VSX35 gt XC95144XL ML403 m1403 XCF32P gt XC4VFX12 gt XC95144XL ML405 m1405 XCF32P gt XC4VFX20 gt XC95144XL ML410 m1410 XC4FX60 ML411 m1411 XC4FX100 ML501 m1501 XC5vLX50 ML505 m1505 XC5vLX50T ML506 m1506 XC5vSX50T ML507 m1507 XC5VFX70T ML510 m1510 XC5VFX130T For a custom board use the configdevice option to specify the JTAG chain and use an OPT file Generating ACE Files System ACE files can be generated for the scenarios in the following subsections An example OPT file is given for each Specify the use of the OPT file as follows xmd tcl genace tcl opt genace opt For Custom Boards If your board is not listed in the Supported Target Boards in Genace tcl Script page 182 the JTAG Chain configuration of the board can be specified using the configdevice option The options file in this case would be jprog hw implementation download bit ace system ace board user lt Note The Board type is user configdevice devicenr 1 idcode 0x1266093 irlength 14 partname XC2VP20 devicenr 2 idcode 0x1266093 irlength 14 partname XC2VP20 lt Note The JTAG Chain is specified here target ppc_hw elf executable elf 182 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Generating ACE Files Single FPGA Device Hardware
242. n Commonly Used Compiler Options Quick Reference page 88 Linker Options page 93 MicroBlaze Compiler Options Quick Reference page 99 MicroBlaze Linker Options page 106 PowerPC Compiler Options Quick Reference page 114 Note From this point forward the references to GCC in this chapter refer to both the MicroBlaze compiler mb gcc and the PowerPC processor compiler powerpc eabi gcc and references to G refer to both the MicroBlaze C compiler mb g and the PowerPC processor C compiler powerpc eabi g Common Compiler Usage and Options Usage To use the GNU compiler type lt Compiler_Name gt options files where lt Compiler_Name gt is powerpc eabi gcec or mb gcc To compile C programs you can use either the powerpc eabi g or the mb g command Embedded System Tools Reference Manual www xilinx com 85 UG111 July 6 2011 Chapter 9 GNU Compiler Tools XILINX Input Files The compilers take one or more of the following files as input e C source files e C source files e Assembly files e Object files e Linker scripts Note These files are optional If they are not specified the default linker script embedded in the linker mb 1d or powerpc eabi 14d is used The default extensions for each of these types are listed in Table 9 1 In addition to the files mentioned above the compiler implicitly refers to the libraries files libc a libgcec a libm a and 1libxil a The default location for the
243. n mb gprof or powerpc eabi gprof Specify the profile configuration sampling binsize lt value gt profile_mem and memory address for collecting profile lt start addr gt data xstats lt target id gt options Displays the simulation statistics for the current session Use the reset option to reset the simulation statistics xtracestart lt target id gt Starts collecting trace information xtracestop lt target id gt Stops collecting trace information a This command is for ISS targets only Miscellaneous Commands Table 10 21 Miscellaneous Commands Command Description xclean Cleans up any Xilinx resources that are using the cable xhelp Lists the XMD commands xverbose Toggles verbose mode on and off Dumps debugging information from XMD Embedded System Tools Reference Manual www xilinx com 167 UG111 July 6 2011 Chapter 10 Xilinx Microprocessor Debugger XMD XILINX 168 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Chapter 11 GNU Debugger This chapter describes the general usage of the Xilinx GNU debugger GDB for the MicroBlaze processor and the PowerPC 405 and 440 processors Overview GDB is a powerful and flexible tool that provides a unified interface for debugging and verifying MicroBlaze and PowerPC 405 and 440 systems during various development phases It uses Xilinx Microprocessor Debug
244. n an address decode operation The model maintains an internal memory that can be initialized through the Bus Functional Language and may be dynamically checked during simulation or when all bus transactions have completed e PLB v4 6 Monitor plbv46_monitor_bfm The PLB v4 6 monitor is a model that connects to the PLB v4 6 and continuously samples the bus signals It checks for bus compliance or violations of the PLB v4 6 architectural specifications and reports warnings and errors e BFM Synchronization Bus bfm_synch The BFM Synchronization Bus is not a bus BFM but a simple bus that connects BFMs in a design and allows communication between them The BFM Synchronization Bus is required whenever BFM devices are used These components may be instantiated in an MHS design file for the Platform Studio tools to create the simulation HDL files Note Xilinx has written an adaptation layer to connect the IBM CoreConnect Bus Functional Models to the Xilinx implementation of CoreConnect Some of these BFM devices have different data instruction bus widths PLB v4 6 BFM Component Instantiation The following is an example MHS file that instantiates PLB v4 6 BFM components and the BFM synchronization bus Parameters PARAMETER VERSION 2 1 0 Ports PORT sys_clk sys_clk DIR I SIGIS CLK PORT sys_reset sys_reset DIR IN Components BEGIN plb_v46 PARAMETER INSTANCE myplb PARAMETER HW_VER 1 01 a PA
245. n page 122 For a specific list of input sections that are assigned by MicroBlaze and PowerPC processor linker scripts see MicroBlaze Linker Script Sections on page 107 and PowerPC Processor Linker Script Sections on page 116 MicroBlaze Compiler Usage and Options The MicroBlaze GNU compiler is derived from the standard GNU sources as the Xilinx port of the compiler The features and options that are unique to the MicroBlaze compiler are described in the sections that follow When compiling with the MicroBlaze compiler the pre processor provides the definition __MICROBLAZE__ automatically You can use this definition in any conditional code MicroBlaze Compiler The mb gcc compiler for the Xilinx MicroBlaze soft processor introduces new options as well as modifications to certain options supported by the GNU compiler tools The new and modified options are summarized in this chapter 98 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX MicroBlaze Compiler Usage and Options MicroBlaze Compiler Options Quick Reference Click an option name below to view its description Processor Feature Selection Options mcpu vX YY Z General Program Options mno xl soft mul msmall divides mxl multiply high mxl gp opt mno xl multiply high mno clearbss mxl soft mul mxl stack check mno xl soft div Application Execution Modes mxl soft div xl mode executable mxl barrel shift xl mode
246. n select the Custom Board option instead of selecting a target board Using this option you can specify the individual hardware devices that you expect to have on your custom board To run the generated system on a custom board you enter the FPGA pin location constraints into the User Constraints File UCF If a supported target board is selected the BSB wizard inserts these constraints into the UCF automatically For detailed information on using the features provided in the BSB wizard see the Xilinx Platform Studio Help The Create and Import Peripheral Wizard The Create and Import Peripheral CIP wizard helps you create your own peripherals and import them into XPS compliant repositories or projects In the Create mode the CIP wizard creates templates that help you implement your peripheral without requiring detailed understanding of the bus protocols naming conventions or the formats of special interface files required by XPS By referring to the examples in the template file and using various auxiliary design support files that are output by the wizard you can start quickly on designing your custom logic In the Import mode this tool creates the interface files and directory structures that are necessary to make your peripheral visible to the various tools in XPS For the Import operation mode it is assumed that you have followed the required XPS naming conventions Once imported your peripheral is available in the XPS periphera
247. n the board uses the MDM or UART to communicate with the host computer therefore it must be configured to use the MDM or UART in the MicroBlaze system The Library Generator Libgen can configure the xMDStub to use the XMDSTUB_PERIPHERAL in the system Libgen generates an XMDStub configured for the XMDSTUB_PERIPHERAL and puts it in code xmdstub elf as specified by the xMDStub attribute in the MSS file For more information refer to Chapter 8 Library Generator Libgen The xmpStub executable must be included in the MicroBlaze local memory at system startup Data2MEM can populate the MicroBlaze memory with XMDStub Libgen generates a Data2MEM script file that can be used to populate the block RAM contents of a bitstream containing a MicroBlaze system It uses the executable specified in DEFAULT_INIT For any program that must be downloaded on the board for debugging the program start address must be higher than 0x800 and the program must be linked with the startup code in crt1 o mb gcc can compile programs satisfying the above two conditions when it is run with the option x1 mode xmdstub Note For source level debugging programs should also be compiled with the g option While initially verifying the functional correctness of a C program it is advisable to not use any mb gcc optimization option such as 02 or 03 as mb gcc performs aggressive code motion optimizations which might make debugging difficult to
248. n which they are connected in the JTAG chain on the board This option is not available on the command line Use in OPT file only data lt data_file gt lt load_address gt none List of data binary file and its load address The load address can be in decimal or hex format 0x prefix needed If an SVF file is specified it is used 180 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX The Genace tcl Script Table 13 2 Genace File Options Cont d Options Default Description debugdevice lt XMD debug device MB v7 The device containing either PowerPC 405 or 440 options gt cpu_version lt version gt MDM v1 processor or MicroBlaze to debug or configure in the mdm_version lt version gt JTAG chain Specify the lt xMD debug device options gt suchas position on the chain devicenr number of processors cpunr processor options such as OCM Cache addresses For a MicroBlaze system the script assumes the MicroBlaze v7 processor and MDM v1 versions The additional options for MicroBlaze versions are cpu_version microblaze_v5 microblaze_v microblaze_v7 microblaze_v72 The additional MDM versions are mdm version mdm_v1 mdm_v2 mdm_v3 elf lt list of Elf or SVF files gt none List of ELF files to download If an SVF file is specified it is used hw lt bitstream file gt none The bitstream file for the system If an SVF file is
249. nable to detect the JTAG chain automatically Automatic detection in XMD can fail for non Xilinx devices on the board for which the JTAG IRLengths are not known The JTAG Boundary Scan RLength information is usually available in Boundary Scan Description Language BSDL files provided by device vendors For these unknown devices IRLength is the only critical information the other fields such as partname and idcode are optional Embedded System Tools Reference Manual www xilinx com 147 UG111 July 6 2011 Chapter 10 Xilinx Microprocessor Debugger XMD XILINX 148 The options used in the following example are e Xilinx Parallel cable III or IV connection is done over the LPT1 parallel port e The two devices in the JTAG chain are explicitly specified e The IRLength partname and idcode of the PROM are specified e The debugdevice option explicitly specifies to XMD that the FPGA device of interest is the second device in the JTAG chain In Virtex devices it is also explicitly specified that the connection is for the first PowerPC processor if there is more than one XMD connect ppc hw cable type xilinx parallel port LPT1 configdevice devicenr 1 partname PROM_XC18V04 irlength 8 idcode 0x05026093 configdevice devicenr 2 partname XC2VP4 irlength 10 idcode 0x0123e093 debugdevice devicenr 2 cpunr 1 Adding Non Xilinx Devices You can add a non Xilinx device either on the command line using the connect command using t
250. nal Resources Embedded System Tools Reference Manual www xilinx com 79 UG111 July 6 2011 Chapter 8 Library Generator Libgen XILINX Drivers Libraries 80 Most peripherals require software drivers The EDK peripherals are shipped with associated drivers libraries and BSPs Refer to the Device Driver Programmer Guide for more information on driver functions A link to the guide is supplied in Appendix E Additional Resources The MSS file includes a driver block for each peripheral instance The block contains a reference to the driver by name DRIVER_NAME parameter and the driver version DRIVER_VER There is no default value for these parameters A driver has an associated MDD file and a Tel file e The driver MDD file is the data definition file and specifies all configurable parameters for the drivers e Each MDD file has a corresponding Tel file which generates data that includes generation of header files generation of C files running DRCs for the driver and generating executables You can write your own drivers These drivers must be in a specific directory under lt YOUR_PROJECT gt lt driver_name gt or lt library_name gt drivers as shown in Figure 8 1 on page 76 e The DRIVER_NAME attribute allows you to specify any name for your drivers which is also the name of the driver directory e The source files and make file for the driver must be in the src subdirectory under the lt driver_name gt
251. nd tm to define the design under test name and the testbench name respectively Top Level Instance ti lt top_instance gt When a testbench template is requested use lt top_instance gt to define the instance name of the design under test When design represents a sub module use lt top_instance gt for the top level instance name Top Level Module tm lt top_module gt When a testbench template is requested use top_module to define the name of the testbench When the design represents a sub module use lt top_module gt for the top level entity module name Top Level toplevel yes no yes Design represents a whole design no Design represents a level of hierarchy sub module Default yes Version v Displays the version then quits Xilinx Library X lt xlib_directory gt Path to the Xilinx simulation libraries unisim simprim Directory XilinxCoreLib directory This is the output directory of the Compxlib tool Output Files Simgen produces all simulation files in the simulation directory which is located inside the output_directory In the simulation directory there is a subdirectory for each simulation model such as output_directory simulation lt sim_model gt Where lt sim_mode1 gt is one of behavioral structural or timing After a successful Simgen execution the simulation directory contains files listed in Table 7 2 Table 7 2 Simgen Output Files Fil
252. ndler void Data This typedef is the exception handler function pointer void Xil_ExceptionDisable Description Disable Exceptions On PowerPC 405 and PowerPC 440 processors this function only disables non critical exceptions void Xil_ExceptionEnable Description Enable Exceptions On PowerPC 405 and PowerPC 440 processors this function only enables non critical exceptions Embedded System Tools Reference Manual www xilinx com 221 UG111 July 06 2011 Appendix B Interrupt Management XILINX void Xil_ExceptionInit Description Initialize exception handling for the processor The exception vector table is set up with the stub handler for all exceptions void Xil_ExceptionRegisterHandler u32 Id Xil_ExceptionHandler Han dler void Data Description Parameters Make the connection between the ID of the exception source and the associated handler that runs when the exception is recognized Data is used as the argument when the handler is called Parameters Id contains the identifier ID of the exception source This should be XIL_EXCEPTION_INT or be in the range of 0 to XIL_EXCEPTION_LAST Refer to the xil_exception h file for further information Handler is the handler for that exception Data is a reference to data that is passed to the handler when it is called void Xil_ExceptionRemoveHandler u32 Id Description Parameters Remove the handler for a specific
253. ndler of the program memory_datawidth_matching disable enable Configures how XMD handles memory read and write By default the data width matching is set to enable All data width byte half and word accesses are handled using the appropriate data width access method This method is especially useful for memory controllers and flash memory where the datawidth access should be strictly followed When data width matching is set to disable XMD uses the best possible method such as word access reset_on_run system enable processor enable disable Configures how XMD handles reset on program execution A reset brings the system to a known consistent state for program execution This ensures correct program execution without any side effects from a previous program run By default XMD performs system reset on run on program download or program run To enable different reset types specify debugconfig reset_on_run processor enable debugconfig reset_on_run system enable To disable reset specify debugconfig reset_on_run disable reset_on_data_dow system enable processor enable disable Changes how XMD handles reset on data download A reset brings the system to a known consistent state for program execution This ensures correct program execution without any side effects from a previous program run By default XMD performs system reset on run on program download or program run To ena
254. nfigurations used to compile the library For example 1ibc_m_bs a is the C library compiled with hardware multiplier and barrel shifter enabled in the compiler Table 9 9 shows the current encodings used and the configuration of the library specified by the encodings Table 9 9 Encoded Library Filenames on Compiler Flags Encoding Description _bs Configured for barrel shifter _m Configured for hardware multiplier _p Configured for pattern comparator _mh Configured for extended hardware multiplier Of special interest are the math library files 1ibm a The C standard requires the common math library functions sin and cos for example to use double precision floating point arithmetic However double precision floating point arithmetic may not be able to make full use of the optional single precision floating point capabilities in available for MicroBlaze The Newlib math libraries have alternate versions that implement these math functions using single precision arithmetic These single precision libraries might be able to make direct use of the MicroBlaze hardware floating point unit and could therefore perform better If you are sure that your application does not require standard precision and you would like to implement enhanced performance you can change the version of the linked in library manually By default the CPU driver copies the double precision version libm_ _fpd a of the library into y
255. ng GDB server and reverts to the previous processor target if any dow dow executable elf dow lt filename elf gt dow lt PIC filename elf gt lt load_address gt dow executable elf 0x400 Downloads the given ELF or data file with the data option onto the memory of the current target If no address is provided along with the ELF file the download address is determined from the ELF file by reading its headers Only those segments of the ELF file that are marked LOAD are written to memory 128 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX XMD User Commands Table 10 2 XMD User Commands Cont d command options dow data lt binary_filename gt lt load_address gt Example Usage dow data system dat 0x400 Description If an address is provided with the ELF file on MicroBlaze targets only it is treated as Position Independent Code PIC code and downloaded at the specified address Also the R20 Register is set to the start address according to the PIC code semantics The R20 Register is reserved for storing a pointer to the Global Offset Table GOT in Position Independent Code PIC It is non volatile in non PIC code and must be saved across function calls When an ELF file is downloaded the command does a reset stops the processor at the reset location by using software breakpoints and loads the ELF pr
256. ng a 16 bit data bus Quad x8 only capable devices forming a 32 bit data bus Paired x16 only capable devices in x16 mode forming a 32 bit data bus x32 x8 capable device in x32 mode forming a 32 bit data bus x32 only capable device forming a 32 bit data bus The physical layout geometry information and other logical information such as command sets are determined using the CFI The flash programmer can be used on flash devices that use the CFI defined command sets only The CFl defined command sets are listed in Table 14 2 Table 14 2 CFI Defined Command Sets nde ID OEM Sponsor Interface Name 1 Intel Sharp Intel Sharp Extended Command Set 2 AMD Fujitsu AMD Fujitsu Standard Command Set 3 Intel Intel Standard Command Set 4 AMD Fujitsu AMD Fujitsu Extended Command Set By default the flash programmer supports only flash devices which have a sector map that matches what is stored in the CFI table Some flash vendors have top boot and bottom boot flash devices the same common CFI table is used for both The field that identifies the boot topology of the current device is not part of the CFI standard Consequently the flash programmer encounters issues with such flash devices Refer to Customizing Flash Programming on page 191 for more information about how to work around the boot topology identification field The following assumptions and behaviors apply to programming fla
257. ng at source assembly and mixed source and assembly Note While initially verifying the functional correctness of a C program do not use any mb gcc optimization option like 02 or 03 as mb gcc does aggressive code motion optimizations which might make debugging difficult to follow Note For debugging with XMD in hardware mode using XMDSTUB specify the mb gcc option x1 mode xmdstub Refer to Chapter 10 Xilinx Microprocessor Debugger XMD for more information about compiling for specific targets PowerPC 405 Targets Debugging for the PowerPC 405 processor is supported by powerpc eabi gdb and XMD through the GDB Remote TCP protocol XMD supports two remote targets PowerPC 405 Hardware and Cycle Accurate PowerPC Instruction Set Simulator ISS To connect to a PowerPC 405 target 1 Start XMD and connect to the board using the connect ppc command as described in Chapter 10 Xilinx Microprocessor Debugger XMD 2 Select Run gt Connect to target from GDB 3 Inthe GDB target selection dialog box specify the following e Target Remote TCP e Hostname localhost e Port 1234 4 Click OK The debugger powerpc eabi gdb attempts to make a connection to XMD If successful a message is printed in the shell window where XMD started At this point the debugger is connected to XMD and controls the debugging The GUI can be used to debug the program and read and write memory and registers Embedded System Tools Reference Manual
258. nitialized and reset is done so the system is in a known good state The reset behavior can be configured using the following commands debugconfig reset_on_run system enable l processor enable disable debugconfig reset_on_data_dow system enable l processor enable disable Refer to Configure Debug Session on page 160 safemode options safemode config lt mode gt lt exception_mask gt safemode on of f safemode config lt exception_id gt lt exception_addr gt safemode info safemode elf lt elf_file gt safemode config lt mode gt lt exception_mask gt safemode on safemode off safemode config lt exception_id gt safemode info safemode elf Enables disables configures and specifies files to be read in safemode Changes the current safemode configuration Enables and disables safemode Changes exception handler ID and or addresses Displays the safemode information Specifies the ELF file to be debugged lt elf_file gt srrd srrd Reads special purpose registers or reads lt reg_name gt register srrd lt register_name gt srrd pe stackcheck stackcheck Gives the stack usage information of the program running on the current target The most recent ELF file downloaded on the target is taken into account for stack check state state When no target id is specified the command state lt target_id g
259. nload bit which includes the embedded application executable ELF for each processor The utility uses the BMM file originally generated by Platgen and updated by the ISE tools with physical placement information on each block RAM in the FPGA Internally the Bitstream Initializer tool uses the Data2MEM utility to update the bitstream file See Figure 1 2 page 10 to see how the Bitinit tool fits into the overall system architecture Refer to Chapter 12 Bitstream Initializer BitInit for more information System ACE File Generator GenACE XPS generates Xilinx System ACE configuration files from an FPGA bitstream ELF and data files The generated ACE file can be used to configure the FPGA initialize block RAM initialize external memory with valid program or data and bootup the processor in a production system EDK provides a Tool Command Language Tcl script genace tcl that uses XMD commands to generate ACE files ACE files can be generated for PowerPC processors and MicroBlaze processors with Microprocessor Debug Module MDM systems For more information see Chapter 13 System ACE File Generator GenACE Flash Memory Programmer The Flash Memory Programming solution is designed to be generic and targets a wide variety of flash hardware and layouts See Chapter 14 Flash Memory Programming Format Revision Tool and Version Management Wizard The Format Revision Tool revup updates an existing EDK project to t
260. ns Table 7 1 list the supported Simgen options Table 7 1 Simgen Syntax Options Option Command Description EDK Library E lt edklib_dir gt Path to EDK simulation libraries directory Directory This switch is not required if the X switch is used The default location of the EDK libraries is inferred from the X switch External Memory Simulation external_mem_sim yes no yes Instantiate external memory model into testbench no Generate testbench without external memory model instances Default no External Memory Model Entity Module name external_ mem module lt mem_module gt Simgen searches for an external memory model file with name lt mem_module gt v vhd in the the XPS project directory Inside the model file a module declaration should exist with the name lt mem_module gt The default value of the lt mem_module gt is e ddr3 if DDR3 is present in the system MHS e ddr2 if DDR2 is present in the system MHS Help h help Displays the usage menu and then quits Options File lt filename gt Reads command line arguments and options from file HDL Language lang vhdl verilog Specifies the HDL language VHDL or Verilog Default vhd1 Log Output log lt logfile log gt Specifies the log file Default simgen log Library Directories lp lt Library_Path gt Allows you to specify library directory paths This option can be specified more than once for multiple
261. nt This appendix describes how to set up interrupts in a Xilinx embedded hardware system Also this appendix describes the software flow of control during interrupts and the software APIs for managing interrupts To benefit from this description you need to have an understanding of hardware interrupts and their usefulness Hardware Setup You must first wire the interrupts in your hardware so the processor receives interrupts The MicroBlaze processor has a single external interrupt port called Interrupt The PowerPC 405 processor and the PowerPC 440 processor each have two ports for handling interrupts One port generates a critical category external interrupt and the other port generates a non critical category external interrupt the difference between the two categories being the priority level over other competing interrupts and exceptions in the system The critical category has the highest priority e On the PowerPC 405 processor the critical and non critical interrupt ports are named EICC405CRITINPUTIRQ and EICC405EXTINPUTIRQ respectively e On the PowerPC 440 processor the critical and non critical interrupt ports are named EICC440CRITIRQ and EICC440EXTIRQ respectively There are two ways to wire interrupts to a processor e The interrupt signal from the interrupting peripheral is directly connected to the processor interrupt port In this configuration
262. nt Wizard When an older project is opened for the first time with the new version of EDK the Format Revision Tool runs and the Version Management Wizard opens Some IP cores might have been obsoleted or updated in the repository since the project was last processed so the wizard outlines the modifications provides the option to automatically upgrade to the latest backward compatible revision or provides more information on how to upgrade to the latest version of the core The wizard also gives you the option to make similar updates for drivers if required Backup copies of the MHS and MSS files are created before the project is modified You may choose to cancel the wizard at any time without modifying the files but as a result it may not be possible to run the project with the current version 200 of XPS www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Chapter 16 Microprocessor Peripheral Definition Translation tool MPDX XBD2 The Xilinx Base Description XBD file defines the supported interfaces of a given board system or sub system XBD enables you to create a system level design through the Base System Builder BSB in Xilinx Platform Studio XPS without the requirement of reading a board schematic or making pin constraint assignments The following information is included for a given board FPGA architecture family speed grade I O list 1 O configuration and peripheral constr
263. nterrupt input signals require the interrupt to be acknowledged after servicing the interrupt to ensure that the interrupt only generates a single interrupt condition API Descriptions int XIntc_Initialize XIntc InstancePtr ul6 Deviceld Description Parameters Initializes a specific interrupt controller instance or driver All the fields of the XIntc structure and the internal vectoring tables are initialized All interrupt sources are disabled InstancePtr is a pointer to the XIntc instance Deviceldis the unique id of the device controlled by this XIntc instance obtained from xparameters h Passing ina DeviceId associates the generic XIntc instance to a specific device as chosen by the caller or application developer Embedded System Tools Reference Manual www xilinx com 219 UG111 July 06 2011 Appendix B Interrupt Management XILINX int XIntc_Connect XIntc InstancePtr u8 Id XInterruptHandler Handler void CallBackRef Description Makes the connection between the Id of the interrupt source and the associated handler that is to be run when the interrupt occurs The argument provided in this call as the CallBackRef is used as the argument for the handler when it is called Parameters InstancePtr is a pointer to the XIntc instance Id contains the ID of the interrupt source and should be in the range of 0 to XPAR_INTC_MAX_NUM_INTR_INPUTS 1 with 0 being the highest priority interrupt Handler is t
264. nts r2 _SDA2_ BASE _SDA2_BASE_ is the read only small data anchor address r13 _SDA_BASE_ _SDA_BASE is the read write small data anchor address Other Undefined Other registers do not have defined values registers The following subsections describe the initialization files used for various application modes This information is for advanced users who want to change or understand the startup code of their application 108 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX MicroBlaze Compiler Usage and Options For MicroBlaze there are two distinct stages of C runtime initialization The first stage is primarily responsible for setting up vectors after which it invokes the second stage initialization It also provides exit stubs based on the different application modes First Stage Initialization Files crt0 o This initialization file is used for programs which are to be executed in standalone mode without the use of any bootloader or debugging stub such as xmdstub This CRT populates the reset interrupt exception and hardware exception vectors and invokes the second stage startup routine _crtinit On returning from _crtinit it ends the program by infinitely looping in the _exit label crt1 o This initialization file is used when the application is debugged in a software intrusive manner It populates all the vectors except the breakpoint and reset vectors and transfers cont
265. numerator and denominator are between 0 and 15 inclusive this switch provides very fast table lookup based divisions This switch has no effect when the hardware divider is enabled mxl gp opt If your program contains addresses that have non zero bits in the most significant half top 16 bits then load or store operations to that address require two instructions MicroBlaze ABI offers two global small data areas that can each contain up to 64 K bytes of data Any memory location within these areas can be accessed using the small data area anchors and a 16 bit immediate value needing only one instruction for a load or store to the small data area This optimization can be turned on with the mx1 gp opt command line parameter Variables of size lesser than a certain threshold value are stored in these areas and can be addressed with fewer instructions The addresses are calculated during the linking stage Caution If this option is being used it must be provided to both the compile and the link commands of the build process for your program Using the switch inconsistently can lead to compile link or run time errors 102 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX MicroBlaze Compiler Usage and Options mno clearbss This option is useful for compiling programs used in simulation According to the C language standard uninitialized global variables are allocated in the bss section and a
266. nx com XILINX Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Chapter 4 Platform Generator Platgen The Hardware Platform Generation tool Platgen customizes and generates the embedded processor system in the form of hardware netlists files By default Platgen synthesizes each processor IP core instance found in your embedded hardware design using the XST compiler Platgen also generates the system level HDL file that interconnects all the IP cores to be synthesized later as part of the overall Xilinx Integrated Software Environment ISE implementation flow For more information refer to the Platform Specification Format Reference Manual A link to this document is provided in Appendix E Additional Resources Features The features of Platgen includes the creation of e The programmable system on a chip in the form of hardware netlists HDL and implementation netlist files e A hardware platform using the Microprocessor Hardware Specification MHS file as input e Netlist files in various formats such as NGC and EDIF e Support files for downstream tools and top level HDL wrappers to allow you to add other components to the automatically generated hardware platform After running Platgen XPS spawns the Project Navigator interface for the FPGA implementation tools to complete the hardware implementation allowing you full control over the implementation At the end of the ISE flow
267. nx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX XMD Console Table 10 1 XMD Options Contd Option Command Description Tcl File tcl lt tclfile gt lt tclarg gt Specifies the XMD Tel script to run The lt tclargs gt are arguments to the Tcl script This Tcl file is sourced from XMD XMD quits after executing the script No other option can follow tc1 Version v Displays the version then quits XMP File xmp lt xmpfile gt Specifies the XMP file to load XMD Console Embedded System Tools Reference Manual UG111 July 6 2011 Upon startup XMD does the following e Ifan XMD Tcl script is specified XMD executes the script then quits e Ifan XMD Tel script is not specified XMD starts in interactive mode In this case XMD does the following 1 Creates source HOME xmdrc file You can use this configuration file to form custom Tcl commands using XMD commands e hw option loads the XML file e When nx option is not given sources the xmd ini file if present in the current directory e opt option uses Connect option file to connect to processor target e ipcport option opens XMD socket server p p e xmp option loads system XMP file 2 Displays the XMD prompt From the XMD Tc1 prompt you can use XMD commands for debugging as described in the next section XMD Command Reference page 126 The XMD console is a standard Tcl cons
268. nx com Embedded System Tools Reference Manual UG111 July 06 2011 g XILINX Parameter Automations C_INTERCONNECT_ lt Buslf gt _IS_ACLK_ASYNC This parameter is used to specify whether the frequency of the clock port of the bus interface master slave is asynchronous with respect to the frequency of the clock port of the interconnect Whenever the interface is asynchronous with respect to the interconnect the interconnect inserts some additional logic to handle that situation As mentioned in the MHS Chapter of the Platform Specification Format Reference Manual UG642 tools require that all IPs in the design be connected to a clock port So when tools identify the clock frequencies of different interfaces they compute the ratio parameters If the ratio is a non integer ratio the IS_ACLK_ASYNC parameter is set to 1 Otherwise if the ratio is an integer ratio the tools set the value of that parameter to 0 To make a particular clock asynchronous with respect to the interconnect you can override the value of this parameter in the MHS The tools will not update that parameter Note f you override the C_INTERCONNECT_ lt BusI gt _IS_ACLK_ASYNC parameter for any interface the tools ignore that frequency when trying to identify the lowest clock for determining clock ratios Also tools do not compute the ratio for that particular interface as it is marked asynchronous C_ lt Buslf gt _SUPPORTS_NARROW_BURST If th
269. o achieve this your application must not bring in boot o as a startup file Unlike other compiler startup files boot o is not explicitly linked in by the compiler Instead the default linker scripts and the tools for generating the linker scripts specify boot o as a startup file You must remove the STARTUP directive in such linker scripts You must also modify the ENTRY directive to be__start instead of _boot Compiler Libraries The powerpc eabi gcc compiler requires the GNU C standard library and the GNU math library Precompiled versions of these libraries are shipped with EDK These libraries are located in SXILINX_EDK gnu powerpc eabi platform powerpc eabi lib Various subdirectories under this top level library directory contain customized versions of the libraries for a particular configuration For instance the double directory contains the version of libraries for use with a double precision FPU whereas the 440 subdirectory contains the version of libraries suited for use with PowerPC 440 processor 120 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Other Notes Thread Safety The C and math libraries for the PowerPC processor distributed with EDK are not built to be used in a multi threaded environment Common C library functions such as printf scanf malloc and free are not thread safe and will cause unrecoverable errors in the system at run time Use appropriate mutual
270. ocate zero initialized global variables in the bss and instead move them to the data section This option may improve startup times for your application Use this option with care Do not use code that relies on global variables being initialized to zero or ensure that your simulation platform performs the zeroing of memory Embedded System Tools Reference Manual www xilinx com 115 UG111 July 6 2011 Chapter 9 GNU Compiler Tools XILINX PowerPC Processor Linker The powerpc eabi 1d linker for the PowerPC processor introduces a new option in addition to those supported by the GNU compiler tools The option is described below defsym _START ADDR value By default the text section of the output code starts with the base address 0xff 0000 because this is the start address listed in the default linker script This can be overridden by using the above option or providing a linker script that lists the value for the start address You are not required to use defsym _START_ADDR if you want to use the default start address set by the compiler This is a linker option Use this option when you invoke the linker separately If the linker is being invoked as a part of the powerpc eabi gcec flow use the option W1 defsym W1 _START_ADDR value The PowerPC linker uses linker scripts to assign sections to memory Table 9 11 and the following subsection lists the script sections PowerPC Processor Linker Script Sections Table 9
271. ocess it resolves the high level bus connections in the MHS into the actual signals required to interconnect the processors peripherals and on chip memories The system level HDL netlist produced by Platgen is used as part of the FPGA implementation process e Invokes the XST Xilinx Synthesis Technology compiler to synthesize each of the instantiated pcores e Generates the block RAM Memory Map BMM file which contains addresses and configuration of on chip block RAM memories This file is used later for initializing the block RAMs with software Chapter 4 Platform Generator Platgen provides a detailed description of the Platgen tool www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX EDK Overview XPS Command Line or No Window Mode XPS includes a no window mode that lets you run from an operating system command line Chapter 5 Command Line Mode provides information on the command line feature in XPS Bus Functional Model Bus Functional Model BFM simulation simplifies the verification of hardware components that attach to a bus Chapter 6 Bus Functional Model Simulation provides information about BFM simulation Debug Configuration Wizard The Debug Configuration wizard automates hardware and software platform debug configuration tasks common to most designs You can instantiate a ChipScope analyzer core to monitor the AMBA AXI4 interface Proce
272. ogram to the memory The reset is done to ensure that the system is ina known good state The reset behavior can be configured using the following commands debugconfig reset_on_run system enable l processor enable disable debugconfig reset_on_data_dow system enable processor enable disable Refer to the Configure Debug Session on page 160 elf verify lt filename elf gt elf verify executable elf Verify if the executable elf is downloaded correctly to the target If ELF file is not specified it uses the most recent ELF file downloaded on the target fpga lt bitstream gt cable lt cable_options gt configdevice lt configuration_options gt fpga f download bit fpga f download bit Loads the FPGA device bitstream Optionally specify the cable JTAG configuration and debug device options For additional information refer to Connect lt number of words half words bytes gt w h b mrd lt Global Variable Name gt cable type debugdevice lt device_name gt xilinx parallel Command Options on page 140 mrd lt address gt mrd 0x400 Reads lt num gt memory locations starting at mrd 0x400 10 mrd 0x400 10 h address Defaults to a word w read If lt Global Variable Name gt name is specified reads memory corresponding to global variable in the previously downloaded ELF file mrd_var mrd_var lt Global Variable Name gt lt fil
273. ol flow dependency management e Ability to export hardware specification files for import into SDK For more information on files and their formats see the Platform Specification Format Reference Manual which is linked in Additional Resources page 261 Refer to the Xilinx Platform Studio Help for details on using the XPS GUI The following subsections describe the tool and utility components of XPS www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX EDK Overview The Base System Builder Wizard The Base System Builder BSB wizard helps you quickly build a working system Some embedded design projects can be completed using the BSB wizard alone For more complex projects the BSB wizard provides a baseline system that you can then customize to complete your embedded design BSB wizard can generate a single processor design for the supported processor types and dual processor designs for MicroBlaze For efficiency in project creation Xilinx recommends using the BSB wizard in every scenario Based on the board you choose the BSB wizard allows you to select and configure basic system elements such as processor type debug interface cache configuration memory type and size and peripheral selection BSB provides functional default values pre selected in the wizard that can be modified as desired If your target development board is not available or not currently supported by the BSB wizard you ca
274. ole where you can run any available Tel commands Additionally the XMD console provides command editing convenience such as file and command name auto fill and command history The available Tcl commands on which you can use auto fill are defined in the lt EDK_Install_Area gt data xmd cmdlist file The command history is stored in SHOME xmdcmdhistory To use different files for available command names and command history you can use environment variables XILINX_XMD_CMD_LIST and XILINX_XMD_CMD_HISTORY to overwrite the defaults www xilinx com 125 Chapter 10 Xilinx Microprocessor Debugger XMD XILINX XMD Command Reference XMD User Command Summary The following is a summary of XMD commands To go to a description for a given command click on its name bpl rst bpr rwr bps run con safemode options connect state cstp srrd data_verify stackcheck debugconfig state dis stats disconnect stop dow stp elf verify targets lt filename elf gt fpga f lt bit terminal stream gt mrd lt address gt tracestart lt number of words half words bytes gt w h b mwr tracestop profile watch read_uart xload rrd www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX XMD User Commands XMD User Commands Table 10 2 displays XMD user commands and options For a list of special register names for MicroBlaze and PowerPC processors refer to Special Purp
275. om DCMCLK to CLK The value DCMCLK has been deprecated e The preprocessor assembler and linker specific options for a software application are moved and included among the Advanced Compiler Options settings individual options have been eliminated e Updates XMP The synthesis tool setting is removed Changes in 8 1i e Update MSS The PROCINST PARAMETER is added to LIBRARY blocks which ensures that a given library can be configured differently across different processor instances in the system e Updates Linkerscript MicroBlaze based application linker script updates are provided to allow the addition of new vector sections that support CRT changes e Updates Linkerscript MicroBlaze based application linker script updates are provided to allow the addition of new sections that support C e Updates Linkerscript PowerPC processor based application linker script updates are provided to allow the addition of new sections that support C e No Project Updates For MicroBlaze applications the program start address is changed from 0x0 to 0x50 to accommodate the change in size of xmdstub elf e No Project Updates For projects that use the Spartan 3 FPGA architecture there is a change to bitgen ut Embedded System Tools Reference Manual www xilinx com 199 UG111 July 6 2011 Chapter 15 Version Management Tools revup XILINX Changes in 7 1i Updates Linkerscript PowerPC processor based application linker sc
276. ompiler Usage and Options Table 9 11 Input Sections Assigned by the PowerPC Processor Linker Scripts Section Description gcc_except_table Language specific data tdata Initialized thread local data tbss Unititialized thread local data Tips for Writing or Customizing Linker Scripts The following points must be kept in mind when writing or customizing your own linker script e The PowerPC processor linker is built with default linker scripts This script assumes a contiguous memory starting at address 0xFFFF0000 The script defines boot o as the first file to be linked The boot o file is present in the 1ibxil a library which is created by the Libgen tool The script defines the start address to be 0xFFFF0000 To specify a different start address you can convey it to the linker using either a command line assignment or an adjustment to the linker script e When writing or customizing your own linker script Ensure that the boot section starts at OxFFFFFFFC Upon power up the PowerPC processor starts execution from the location 0xFFFFFFFC The _end variable is defined after the boot0 section definition This section is a jump to the start of the boot0 section The jump is defined to be 24 bits hence the boot and boot0 sections should not be more than 24 bits apart On the PowerPC 440 processor the boot0 section has a fixed location of 0xFFFFFF00 Allocate space in the bss section
277. ompiling definitions or references to these symbols Note All EDK drivers and libraries follow these conventions in all the header files they provide You must include the necessary headers as documented in each driver and library when you compile with G This ensures that the compiler recognizes library symbols as belonging to C type When compiling with either variant of the compiler to force a file to a particular dialect use the x lang switch Refer to the GCC manual on the GNU website for more information on this switch A link to the document is provided in the Additional Resources on page 122 When using the GCC compiler libstdc a and libsupc aare not automatically linked in When compiling C programs use the G variant of the compiler to make sure all the required support libraries are linked in automatically Adding 1stdc and lsupc to the GCC command are also possible options For more information about how to invoke the compiler for different languages refer to the GNU online documentation A link to the documentation is provided in the Additional Resources on page 261 Commonly Used Compiler Options Quick Reference The summary below lists compiler options that are common to the compilers for MicroBlaze and PowerPC processors Note The compiler options are case sensitive To jump to a detailed description for a given option click on its name General Options Library Search Options
278. on documents how to remove the overhead of invoking the C constructor or destructor code in a C program that does not need them You might be able to save approximately 500 bytes of code space by making these modifications 1 Follow the instructions for creating a custom copy of the startup files from the installation area as described in the preceding sections Specifically you need to copy over the particular version of xil crt s that suits your application For example if your application is being profiled copy xil pgcrt0 s from the installation area Modify the CRT file to remove the following lines Call _init bl _init and Invoke the language cleanup functions bl _fini This avoids referencing the extra code that is usually pulled in for constructor and destructor handling and reducing code size 2 Either compile these files into 0 files and place them in a directory of your choice or include them as a part of your application sources 3 Add the nostart files switch to the compiler Add the B directory switch if you have chosen to assemble the files in a particular folder 4 Compile your application Modifying Startup Files for Bootstrapping an Application If your application is going to be loaded from a bootloader you might not want to overwrite the processor reset vector of the bootloader with that of your application This re executes the bootloader on a processor reset instead of your application T
279. on gt Position in the JTAG chain of the FPGA device containing the MicroBlaze processor The device position number starts from 1 romemstartadr lt ROM start address gt Start address of Read Only Memory Use this to specify flash memory range XMD sets hardware breakpoints instead of software breakpoints romemsize lt ROM Size in Bytes gt Size of Read Only Memory tlbstartadr lt TLB start address gt Start address for reading and writing the Translation Look aside Buffer TLB MicroBlaze MDM Target Requirements 1 To use the hardware debug features on MicroBlaze such as hardware breakpoints and hardware debug control functions like stopping and stepping the hardware debug port must be connected to the MDM 2 To use the UART functionality in the MDM target you must set the C_USE_UART parameter while instantiating the MDM core in a system Note Unlike the MicroBlaze stub target programs should be compiled in executable mode and NOT in XMDSTUB mode while using the MDM target Consequently you do not need to specify an XMDSTUB_PERIPHERAL for compiling the XMDStub www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Connect Command Options Example Debug Sessions Example Using a MicroBlaze MDM Target This example demonstrates a simple debug session with a MicroBlaze MDM target Basic XMD based commands are used after connecting to the MDM t
280. on the system architecture a system reset performed during download of a program could cause programs downloaded to other processors earlier in the sequence to get reset This may or may not be desirable consequently use the debugconfig command to disable system reset and or enable processor reset only on the various processors The following are example use cases Example 1 One Master Processor and Multiple Slave Processors In this scenario the program on the master processor gets downloaded and run first followed by the other processors In this case the user wants to enable system reset on download to the master processor and only a processor reset or no reset on the other processors Example 2 Peer Processors In this case the download sequence could be arbitrary and the user wants to enable only processor reset or no reset at both the processors This will ensure that downloading a program to one of the peer processors does not affect the system state for the other peers Refer the proc_sys_reset IP module documentation for more information on how the reset connectivity and sequencing works through this module XMD Internal Tcl Commands In the Tcl interface mode XMD starts a Tcl shell augmented with XMD commands All XMD Tcl commands start with x and you can list them from XMD by typing x Xilinx recommends using the Tcl wrappers for these internal commands as described in Table 10 1 on page 124 The Tcl wrappers pr
281. only one peripheral can interrupt the processor e The interrupt signal from the interrupting peripheral is connected to an interrupt controller core which in turn generates an interrupt on a signal connected to the interrupt port on the processor This allows multiple peripherals to send interrupt signals to a processor This is the more common method as there are usually more than one peripheral on embedded systems that require access to the interrupt function Figure B 1 page 214 illustrates the interrupt configurations Embedded System Tools Reference Manual www xilinx com 213 UG111 July 06 2011 Appendix B Interrupt Management Processor Interrupt Port Programmable Timer Interrupts without an Interrupt Controller Figure B 1 Software Setup and Interrupt Flow XILINX Processor Programmable Timer Interrupt Port Interrupt Controller Interrupts with an Interrupt Controller Ethernet MAC X11017 Interrupt Configurations Interrupts are typically vectored through multiple levels in the software platform before the application interrupt handlers are executed The Xilinx software platforms Standalone and Xilkernel follow the interrupt flow shown in Figure B 2 Application Interrupt Handler Software Platform OS Level Interrupt Vector Lowest Level Interrupt Vector Figure B 2 214 www xilinx com Final peripheral level or application
282. ons The BSB framework uses the following as a standard e The CVS defines two mandatory columns Pin Name and Pin Index e Other columns such as LOC are optional e You can add or remove additional pin properties by adding or removing a column The Pin Name must be present and the field must match the name used in the Board MPD file The Pin Index column must be present and can have an empty field Pin Name Pin Index LOC DRIVE IOSTANDARD SLEW TIG CUR Py K115 CLK_N K16 RESET N4 TIG RS232_Uart_1_sout L12 RS232 Uart_1_sin K14 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Define Constraints RS232_Uart_1_ctsN U10 RS232_Uart_l_rtsN T5 DIP_Switches_4Bits_TRI_I 0 D14 LVCMOS25 DIP_Switches_4Bits_TRI_I 1 E12 LVCMOS25 DIP_Switches_4Bits_TRI_1I 2 F12 LVCMOS25 DIP_Switches_4Bits_TRI_1I 3 V13 LVCMOS25 TCL The BSB framework supports TGI calls through Tcl TGI calls are defined in IP XACT documentation Tcl and ConstraintMan bsb definePinAttribute nCHandle strPinName strAttName strAttValue Where nCHand1e ls the instance pointer of ConstraintManager strPinName lIs a concatenation of Pin Name and Pin Index fields defined in the CSV For example DIP_Switches_4Bits_TRI_I 0 strAttName ls the attribute name For example LOC strAttValue ls the attribute value bsb getRepoDirPath nCHandle
283. operate together to create an embedded system CompXLib Processor Software Processor Hardware Platform MSS Platform MHS IP Models Cs wed IP Library or User Repository BSP MLD Generator MDD Generator Generator Behavioral HDL Model Libraries Ca OS MLD Sysienvand Wrapper HDL aysiem EN E Synthesis XST NGCBuild Simulation NepBuNg Structural HDL Model MAP PAR NCD Simulation Generator Timing HDL SDF Model Application Source iG hs Implementation Constraint File UCF Compiler GCC Linker GCC system_BD BMM ii Bitstream Generator ELF Bitstream Initializer a system BIT download BIT Debugger iMPACT XMD GDB JTAG Cable FPGA Device X10310 Simulation download CMD Figure 1 2 Embedded Development Kit EDK Tools Architecture 10 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 Embedded System Tools Reference Manual UG111 July 6 2011 EDK Tools and Utilities EDK Overview The following table describes the tools and utilities supported in EDK and the subsections that follow provide an overview of each tool with references to the chapters that contain additional information Table 1 1 EDK Tools and Utilities Hardware Development and Verification Xilinx Platform Studio An integrated design environment GUI in which you can create your embedded hardware design The Base S
284. or Specify one or more point to point connections for the peripheral o lt outfile gt Specify output filename default is stdout 1 Bus type mb master that generates burst transactions is valid for bus standard PLBv4 6 only Embedded System Tools Reference Manual UG111 July 6 2011 www xilinx com 19 XILINX Chapter 2 Platform Specification Utility PsfUtility Table 2 1 PsfUtility Syntax Options Cont d Option Command PAO file to MPD pao2mpd lt paofile gt Description Generate MPD from Peripheral Analyze Order PAO file Suboptions are lang ver vhd1 Specify language top lt design gt Specify top level entity or module name bus plbv46 axi4 axi4lite dcr 1mb fsl m s ms mb lt busif_name gt Specify one or more peripherals and optional interface name s p2pbus lt busif_name gt lt bus_std gt target initiator Specify one or more point to point connections of the peripheral o lt outfile gt Specify output filename default is stdout Display version v information Displays the version number 1 Bus type mb master that generates burst transactions is valid for bus standard PLBv4 6 only MPD Creation Process Overview You can use the PsfUtility to create MPD specifications from the HDL specification of the core automatically To create a peripheral and deliver it through EDK 1 Code the IP in VHDL or Verilog using the req
285. or code is placed e The PowerPC 440 processor has independent offset registers for each interrupt type labeled IVORO IVOR15 Each offset register contains a value that is appended to the Interrupt Vector Prefix register IVPR to obtain the final physical address of the interrupt vector code The processor jumps to the calculated interrupt vector code address Each interrupt vector location contains a platform interrupt handler that is appropriate for the interrupt type e For external critical and non critical interrupts the handler saves all of the processor registers that could be clobbered further down onto the current application stack e The handler then transfers control to the next level handler Because this can be dependent on whether there is an interrupt controller in the system the handler consults an internal interrupt vectoring table to determine the function address of the next level handler e The handler also consults the vectoring table for a callback value that it must pass to the next level handler Then the handler makes the actual call e On systems with an interrupt controller the next level handler is the handler provided by the interrupt controller driver This handler queries the interrupt controller for all active interrupts in the system For each active interrupt it consults its internal vector table which contains the user registered handler for each interrupt line If no handler is re
286. or each bus interface Trailing underline character _ in the lt BI gt string are ignored PLBV46 Slave Outputs For interconnection to the PLBV4 6 slaves must provide the following outputs lt BI gt S1_addrAck lt BI gt S1_MBusy lt BI gt S1_MRdErr lt BI gt S1_MWrErr lt BI gt S1_MIRO lt BI gt S1_rdBTerm lt BI gt S1_rdComp lt BI gt S1_rdDAck lt BI gt S1_rdDBus lt BI gt S1_rdwdAddr lt BI gt Sl_rearbitrate lt BI gt S1_SSize lt BI gt Sl_wait lt BI gt S1_wrBTerm lt BI gt S1_wrComp lt BI gt S1_wrDAck Examples Tmr_Sl_addrAck Uart_Sl_addrAck IntcSl_addrAck out std_logic out std_logic_vector 0 to C_ lt BI SPLB gt _NUM_MASTERS 1 out std_logic_vector 0 to C_ lt BI SPLB gt _NUM_MASTERS 1 out std_logic_vector 0 to C_ lt BI SPLB gt _NUM_MASTERS 1 out std_logic out std_logic out std_logic out std_logic out std_logic_vector 0 to C_ lt BI SPLB gt _DWIDTH 1 out std_logic_vector 0 to 3 out std_logic out std_logic 0 to 1 out std_logic out std_logic out std_logic out std_logic out std_logic out std_logic out std_logic Embedded System Tools Reference Manual UG111 July 6 2011 www xilinx com 37 Chapter 2 Platform Specification Utility PsfUtility XILINX PLBV4 6 Slave Inputs For interconnection to the PLBV4 6 slaves must provide the following inputs lt BI gt SPLB_Clk in std_logic lt B
287. or main and invokes main Invokes destructor functions _fini Invokes _program_clean and then returns sim pgcrtinit o This second stage startup file is used during profiling in conjunction with the mno clearbss switch This startup files performs the following steps in order NAO PF WN a Invokes _program_init Invokes _profile_init to initialize the profiling library Invokes constructor functions _init Sets up the arguments for main and invokes main Invokes destructor functions _ fini Invokes _profile_clean to cleanup the profiling library Invokes _program_clean and then returns Other files The compiler also uses certain standard start and end files for C language support These are crti o crtbegin o crtend o and crtn o These files are standard compiler files that provide the content for the init fini ctors and dtors sections 110 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX MicroBlaze Compiler Usage and Options Modifying Startup Files The initialization files are distributed in both pre compiled and source form with EDK The pre compiled object files are found in the compiler library directory Sources for the initialization files for the MicroBlaze GNU compiler can be found in the lt XILINX_EDK gt sw lib microblaze src directory where lt XILINX_EDK gt is the EDK installation area To fulfill a custom startup file requirement
288. or seamless debugging and profiling of embedded targets For more information about SDK see the Software Development ToolKit SDK Help Library Generator Libgen Libgen configures libraries device drivers file systems and interrupt handlers for the embedded processor system creating a board support package BSP The BSP defines for each processor the drivers associated with the peripherals you include in your hardware platform selected libraries standard input and output devices interrupt handler routines and other related software features Your SDK projects further define software applications to run on each processor which are based on the BSP Taking libraries and drivers from the installation along with any custom libraries and drivers for custom peripherals you provide SDK is able to compile your applications including libraries and drivers into Executable Linked Format ELF files that are ready to run on your processor hardware platform Libgen reads selected libraries and processor core pcore software description files Microprocessor Driver Definition MDD and driver code from the EDK library and any user IP repository Refer to Chapter 8 Library Generator Libgen and the Xilinx Platform Studio Help for more information For more information on libraries and device drivers refer to the Xilinx software components documented in the OS and Libraries Document Collection Links to the documentation are supplied in
289. ormation Optionally Simgen can generate a compile script for a specified vendor simulator If specified Simgen can generate HDL files with data to initialize block RAMs associated with any processor that exists in the design This data is obtained from an existing ELF file ELF sorp UG111_04_101705 Figure 7 4 Timing Simulation Model Generation Single and Mixed Language Models Simgen allows the use of mixed language components in behavioral files for simulation By default Simgen takes the native language in which each component is written Individual components cannot be mixed language To use this feature a mixed language simulator is required Xilinx IP components are written in VHDL If a mixed language simulator is not available Simgen can generate single language models by translating the HDL files that are not in the HDL language The resulting translated HDL files are structural files Structural and Timing simulation models are always single language Embedded System Tools Reference Manual www xilinx com 65 UG111 July 6 2011 Chapter 7 Simulation Model Generator Simgen XILINX Creating Simulation Models Using XPS Batch Mode 1 Simgen Syntax Open your project by loading your XMP file XPS load xmp lt filename gt xmp Set the following simulation values at the XPS prompt a Select the simulator of your choice using the following command XPS xset simulator mgm questa ies
290. orted for DDR2 and DDR3 Virtex 6 only Supported for Behavioral simulation only 3 When you select external memory simulation the memory model is instantiated only if an AXI DDRx memory controller is present in the system The IP nomenclature is axi_ lt device family gt _ddrx If the AXI memory controller is not present Simgen continues to generate the testbench without the external memory model 4 The following are not supported in this release e 72 bit wide memory interface for example with ECC e RDIMM memory types e 7 series DDRx 72 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX External Memory Simulation Enabling External Memory Simulation To enable external memory simulation pass the following flag to Simgen external_mem_sim yes no You can specify a memory model to Simgen by placing the file with the name ddr2 v vhd or ddr3 v vhd in the project directory The file can be downloaded from memory vendor web sites provided that it is renamed accordingly See Considerations and Use Restrictions page 73 An additional Simgen command line option lets you specify the external simulation file external_mem_module lt external memory entity module name gt This option is not supported in the XPS GUI or XPS no window mode If amemory model is not found in the XPS project directory Simgen continues to generate the testbench with a warning message The following a
291. orted for use by SDK www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Design Process Overview Software Development A board support package BSP is a collection of software drivers and optionally the operating system on which to build your application The created software image contains only the portions of the Xilinx library you use in your embedded design You can create multiple applications to run on the BSP The hardware platform must be imported into SDK prior to creation of software applications and BSP Verification EDK provides both hardware and software verification tools The following subsections describe the verification tools available for hardware and software Hardware Verification Using Simulation To verify the correct functionality of your hardware platform you can create a simulation model and run it on an Hardware Design Language HDL simulator When simulating your system the processor s execute your software programs You can choose to create a behavioral structural or timing accurate simulation model Sim the ISE simulator now supports simulation of embedded designs When you create a project in ISE and add an embedded project source you can launch ISim from within ISE When no ISE project is used you can launch the ISim software directly from within Platform Studio Software Verification Using Debugging The following options are available for softwar
292. ory path set strRepoDirPath bsb getRepoDirPath nCHandle Pin Constraints set strCsvFilePath file join strRepoDirPath sp605_pins csv set nResult bsb registerPinData nCHandle nComIdXbd nDesigniId SstrCsvFilePath if nResult 0 return SnResult return nResult 208 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Appendix A GNU Utilities This appendix describes the GNU utilities available for use with EDK General Purpose Utility for MicroBlaze and PowerPC cpp Pre processor for C and C utilities The preprocessor is invoked automatically by GNU Compiler Collection GCC and implements directives such as file include and define gcov This is a program used in conjunction with GCC to profile and analyze test coverage of programs It can also be used with the gprof profiling program Note The gcov utility is not supported by XPS or SDK but is provided as is for use if you want to roll your own coverage flows Utilities Specific to MicroBlaze and PowerPC Utilities specific to MicroBlaze have the prefix mb as shown in the following program names The PowerPC processor versions of the programs are prefixed with yowerpc eabi mb addr2line This program uses debugging information in the executable to translate a program address into a corresponding line number and file name mb ar This program creates modifies and extracts
293. ose Register Names on page 133 For connect command options refer to Connect Command Options on page 140 Table 10 2 XMD User Commands command options Example Usage Description bpl bp1 Lists breakpoints and watchpoints bpr bpr 0x400 Removes breakpoints and watchpoints bpr all lt bp id gt bpr main lt address gt lt function gt bpr all bps bps 0x400 Sets a software or hardware breakpoint at lt address gt or start of lt function name gt The s last downloaded ELF file is used for function bps lt address gt bps main hw f lookup Defaults to software breakpoint lt function_name gt sw hw close_terminal close_terminal Closes the terminal server opened by the terminal command and the MDM Uart target connection con con Continues from current PC or optionally specified lt Execute Start Address gt con lt Execute Start Address gt con 0x400 If block option is specified the command block timeout lt Seconds gt returns when the Processor stops on breakpoint or watchpoint A timeout value can be specified to prevent indefinite blocking of the command The block option is useful in scripting connect connect mb mdm Connects to lt target_type gt Valid target types are mb ppc and mdm For additional ee ee ae ee connect a information refer to Connect Command SEFERE Pp Options on page 140 cstp cstp Steps through the specified numbe
294. ou can access the DCR bus in XMD through the PLB address map Each DCR address corresponds to one DCR register which has 4 bytes When it is mapped to the PLB address it needs 4 bytes of address range In the example shown in Example Debug Session for PowerPC Processor ISS Target page 150 the address mappings are DCR Address Mapped Address 0x0 0x78020000 0x1 0x78020004 0x2 0x78020008 0x10 0x78020040 Advanced PowerPC Processor Debugging Tips Support for Running Programs from ISOCM and ICACHE There are restrictions on debugging programs from PowerPC 405 processor ISOCM memory and instruction caches ICACHEs One such restriction is that you cannot use software breakpoints In such cases XMD can set hardware breakpoints automatically if the address ranges for the ISOCM or ICACHEs are provided as options to the connect command in XMD In this case of ICACHE this is only necessary if you try to run programs completely from the ICACHE by locking its contents in ICACHE For more information refer to the Xilinx Platform Studio Help The special features of the PowerPC processor can be accessed from XMD by specifying the appropriate options to the connect command in the XMD console Embedded System Tools Reference Manual www xilinx com 151 UG111 July 6 2011 152 Chapter 10 Xilinx Microprocessor Debugger XMD XILINX Debugging Setup for Third Party Debug Tools To use third party debug tools such as Wind River Singl
295. our XPS project To get the single precision version you can create a custom CPU driver that copies the corresponding 1ibm_ _fps a library instead Simply copy the corresponding 1ibm_ _fps a file into your processor library folder such as microblaze_0 1lib as libm a When you have copied the library that you want to use rebuild your application software project Thread Safety The MicroBlaze C and math libraries distributed with EDK are not built to be used in a multi threaded environment Common C library functions such as printf scanf malloc and free are not thread safe and will cause unrecoverable errors in the system at run time Use appropriate mutual exclusion mechanisms when using the EDK libraries in a multi threaded environment www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX MicroBlaze Compiler Usage and Options Command Line Arguments MicroBlaze programs cannot take command line arguments The command line arguments argc and argv are initialized to 0 by the C runtime routines Interrupt Handlers Interrupt handlers must be compiled in a different manner than normal sub routine calls In addition to saving non volatiles interrupt handlers must save the volatile registers that are being used Interrupt handlers should also store the value of the machine status register RMSR when an interrupt occurs interrupt handler attribute To distinguish an interrupt handler fro
296. ous standard sections of the object file are displayed in the following figure In addition to these sections you can also create your own custom sections and assign them to memories of your choice 94 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Common Compiler Usage and Options Sectional Layout of an object or an Executable File Text Section Read Only Data Section Small Read Only Data Section Small Read Only Uninitialized Data Section Read Write Data Section Small Read Write Data Section Small Uninitialized Data Section Uninitialized Data Section Program Heap Memory Section Program Stack Memory Section Figure 9 2 Sectional Layout of an Object or Executable File X11005 The reserved sections that you would not typically modify include init fini ctors dtors got got2 and eh_frame text This section of the object file contains executable program instructions This section has the x executable r read only and i initialized flags This means that this section can be assigned to an initialized read only memory ROM that is addressable from the processor instruction bus rodata This section contains read only data This section has the r read only and the i initialized flags Like the text section this section can also be assigned to an initialized read only memory that is addressable from the processor data bus sdata2 This section is sim
297. owing table apply only to the C and C source files Table 9 3 Optimizations for Values of n n Optimization 0 No optimization 1 Medium optimization 2 Full optimization 3 Full optimization Attempt automatic inlining of small subprograms S Optimize for size Note Optimization levels 1 and above cause code re arrangement While debugging your code use of no optimization level is recommended When an optimized program is debugged through gdb the displayed results might seem inconsistent V This option executes the compiler and all the tools underneath the compiler in verbose mode This option gives complete description of the options passed to all the tools This description is helpful in discovering the default options for each tool Embedded System Tools Reference Manual www xilinx com 89 UG111 July 6 2011 Chapter 9 GNU Compiler Tools XILINX save temps The GNU compiler provides a mechanism to save the intermediate files generated during the compilation process The compiler stores the following files e Preprocessor output input_file_name i for C code and input_file_name ii for C code e Compiler cc1 output in assembly format input_file_name s e Assembler output in ELF format input_file_name s The compiler saves the default output of the entire compilation as a out o filename The compiler stores the default output of the compilation process in an ELF file named a out
298. ple ISim Example The following is an example ISim script called run tc1 that you can write to perform the BFM simulation steps isim force add system sys_clk 1 time 0 ns value 0 time 10 ns repeat 20 ns isim force add system sys_reset 1 time 100 ns value 0 time 200 ns do sample tcl do wave do run 2 us At the ISim prompt type source run tcl 60 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Chapter 7 Simulation Model Generator Simgen This chapter introduces the basics of Hardware Description Language HDL simulation and describes the Simulation Model Generator tool Simgen and usage of the Compxlib utility tool Simgen Overview Simgen creates and configures various VHDL and Verilog simulation models for a specified hardware Simgen takes as the input file the Microprocessor Hardware Specification MHS file which describes the instantiations and connections of hardware components Simgen is also capable of creating scripts for a specified vendor simulation tool The scripts compile the generated simulation models The hardware component is defined by the MHS file Refer to the Microprocessor Hardware Specification MHS chapter in the Platform Specification Format Reference Manual for more information Appendix E Additional Resources contains a link to the document web site For more information about simulation basics and for discussions of behavior
299. r Wizard The Configure Coprocessor wizard helps add and connect a coprocessor to a CPU A coprocessor is a hardware module that implements a user defined function and connects to the processor through an auxiliary bus The coprocessor has a Fast Simplex Link FSL interface For MicroBlaze processor systems the coprocessor connects to the FSL interface For PowerPC processor systems the coprocessor connects to the Auxiliary Processor Unit APU interface of the PowerPC processor through the fcb2fs1 bridge For details on the Fast Simplex Link refer to its data sheet and the MicroBlaze Processor Reference Guide UG For information about the APU bus refer to the PowerPC reference guides For information on the fcb2fsl bridge refer to its data sheet Links to document locations are available in the Additional Resources page 261 For instructions on using the Coprocessor wizard refer to the Xilinx Platform Studio Help Platform Generator Platgen Platgen compiles the high level description of your embedded processor system into HDL netlists that can be implemented in a target FPGA device Platgen e Reads the MHS file as its primary design input e Reads various processor core pcore hardware description files MPD PAO from the XPS project and any user IP repository e Produces the top level HDL design file for the embedded system that stitches together all the instances of parameterized pcores contained in the system In the pr
300. r _Flash_PHY_TYPE_0 Linear Flash DT STRING ASSIGNMENT CONSTANT IO_IF Linear_Flash IO_IS PHY_TYPE PARAMETER Linear_Flash_MEM WIDTH_0O 16 DT STRING ASSIGNMENT CONSTANT IO_IF Linear_Flash IO_IS MEM_WIDTH PARAMETER Linear_Flash_MEM _STZE_0 33554432 DT STRING ASSIGNMENT CONSTANT IO_IF Linear_Flash IO_IS MEM_SIZE PARAMETER Linear_Flash_TCEDV_PS_0 130000 DT STRING ASSIGNMENT CONSTANT IO_IF Linear_Flash IO_IS TCEDV_PS PARAMETER Linear_Flash_TAVDV_PS_0 130000 DT STRING ASSIGNMENT CONSTANT IO_IF Linear_Flash IO_IS TAVDV_PS PARAMETER Linear_Flash_THZCE_PS_0 35000 DT STRING ASSIGNMENT CONSTANT IO_IF Linear_Flash IO_IS THZCE_PS PARAMETER Linear_Flash_THZOE_PS_0 7000 DT STRING ASSIGNMENT CONSTANT IO_IF Linear_Flash IO_IS THZOE_PS PARAMETER Linear _Flash_TWC_PS_0 13000 DT STRING ASSIGNMENT CONSTANT IO_IF Linear_Flash IO_IS TWC_PS PARAMETER Linear_Flash_TWP_PS_0 70000 DT STRING ASSIGNMENT CONSTANT IO_IF Linear_Flash IO_IS TWP_PS PARAMETER Linear_Flash_TLZWE_PS_0 35000 DT STRING ASSIGNMENT CONSTANT IO_IF Linear_Flash IO_IS TLZWE_PS PARAMETER Linear _Flash_ EXCLUSIVE SPI_FLASH DT STRING ASSIGNMENT CONSTANT IO_IF Linear_Flash IO_IS EXCLUSIVE PORT L
301. r all XMD sessions you can write that command in the xmdrc file which is located at your home directory 2 Use the command safemode config mode MASK This sets the mask for current target only While debugging a program this is a convenient way to change the trap settings Note The current target is destroyed when you disconnect from the target Viewing Safemode Settings You can view the current safemode setting with the safemode info command In safe mode XMD sets the breakpoint at the exception handlers that you want to trap e For MicroBlaze processors all exceptions take PC to 0x20 e For PowerPC processors XMD detects the exception handler locations from the ELF file The detection works on most Standalone or Xilkernel projects If another software platform is used the detection might fail In such cases set the exception handler address with the safemode config lt exception_id gt lt exception_handler_addr gt command Connect Command Options XMD can debug programs on different targets processor or peripheral e When communicating with a target XMD connects to the target and a unique target ID is assigned to each target after connection e When connecting to a processor the gdbserver starts enabling communication with GDB or SDK Usage connect mb ppc mdm lt Connection_Type gt Options Table 10 7 lists the connect command options Table 10 7 Connect Command Options
302. r interconnection to the PLBV4 6 masters must provide the following inputs lt BI gt MPLB_Clk in std_logic lt BI gt MPLB_Rst in std_logic lt BI gt PLB_MBusy in std_logic lt BI gt PLB_MRdErr in std_logic lt BI gt PLB_MWrErr in std_logic lt BI gt PLB_MIRQ in std_logic lt BI gt PLB_MWrBTerm in std_logic lt BI gt PLB_MWrDAck in std_logic lt BI gt PLB_MAddrAck in std_logic lt BI gt PLB_MRdBTerm in std_logic lt BI gt PLB_MRdGDAck in std_logic 36 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Conventions for Defining HDL Peripherals lt BI gt PLB_MRdDBus lt BI gt PLB_MRdWdAddr in std_logic_vector 0 to C_ lt BI MPLB gt _DWIDTH 1 in std_logic_vector 0 to 3 lt BI gt PLB_MRearbitrate in std_logic lt BI gt PLB_MSSize lt BI gt PLB_MTimeout Examples IPLBO_PLB_ MBusy Bus1_PLB_MBusy Slave PLBV46 Ports in std_logic_vector 0 to 1 in std_logic in std_logic in std_logic Table 2 14 shows the required naming conventions for Slave PLBV4 6 ports Table 2 14 Slave PLBV46 Port Naming Conventions lt S1 gt Prefix for the slave output lt PLB gt Prefix for the slave input lt BI gt A bus identifier Optional for peripherals with a single slave PLBV46 port and required for peripherals with multiple slave PLBV46 ports For peripherals with multiple PLBV46 ports the lt BI gt strings must be unique f
303. r of cycles This is supported only on ISS targets cstp lt number of cycles gt cstp 10 data_verify data_verify Verify if the lt Binary filename gt is downloaded correctly at lt Load Address gt to the target data_verify lt binary_filename gt system dat 0x400 r8 lt load_address gt Embedded System Tools Reference Manual www xilinx com 127 UG111 July 6 2011 Chapter 10 Xilinx Microprocessor Debugger XMD XILINX Table 10 2 XMD User Commands Cont d command options debugconfig debugconfig step_mode disable_interrupt enable_interrupt debugconfig memory_datawidth_matching disable enable debugconfig reset_on_run system enable processor enable disable debugconfig reset_on_data_dow system enable processor enable disable Example Usage debugconfig debugconfig step_ mode enable interrupt debugconfig memory datawidth_ma tching enable debugconfig reset_on_run system enable debugconfig reset_on_data_dow processor enable Description Configures the debug session for the target For additional information refer to Configure Debug Session on page 160 dis dis lt address in hex gt lt number of words gt dis 0x400 10 Disassemble instruction Supported on the MicroBlaze target only disconnect disconnect lt target id gt disconnect 0 Disconnects from the current processor target closes the correspondi
304. re guaranteed to have the value 0 when the program starts execution Typically this is achieved by the C startup files running a loop to fill the bss section with zero when the program starts execution Optimizing compilers also allocates global variables that are assigned zero in C code to the bss section Ina simulation environment the above two language features can be unwanted overhead Some simulators automatically zero the entire memory Even in a normal environment you can write C code that does not rely on global variables being zero initially This switch is useful for these scenarios It causes the C startup files to not initialize the bss section with zeroes It also internally forces the compiler to not allocate zero initialized global variables in the bss and instead move them to the data section This option might improve startup times for your application Use this option with care and ensure either that you do not use code that relies on global variables being initialized to zero or that your simulation platform performs the zeroing of memory mxl stack check With this option you can check whether the stack overflows when the program runs The compiler inserts code in the prologue of the every function comparing the stack pointer value with the available memory If the stack pointer exceeds the available free memory the program jumps to a the subroutine _stack_overflow_exit This subroutine sets the value of the variable
305. re optional recommended steps while working with XPS 1 For better tracking of initialization of models on the simulator waveforms expose the phy_init_done pin on the top level To make port external a Goto XPS gt System Assembly View b Select the Port tab and expand the DDRx_SDRAM IP instance c Select the phy_init_done pin d In the net drop down select Make External 2 To speed simulation set the init_call manually to FAST in the MHS to speed simulation this feature is not available in the GUI IP configuration To do so add the following parameter to the MHS under the axi_ddrx IP instance as follows PARAMETER C_BYPASS_INIT_CAL FAST 3 The current flow was developed with version 1 60 of micron memory models If you are using a version of Micron memory model higher than 1 62 the model files must have density defined before compilation Add the following construct into model file define lt density gt Note lt density gt values are one of the following den1024Mb den2048Mb or den4096Mb in the downloaded memory model file Considerations and Use Restrictions 1 The memory model is always instantiated with x8 configuration consequently if the DQ_WIDTH parameter is 64 then eight instances are generated in the testbench and other parameters are modified accordingly 2 External memory simulation with multiple instances of DDRx memory controller in XPS is not supported 3 External memory simulation is
306. rful debugging tools for verifying a complete MicroBlaze system The debugger mb gdb connects to XMD using the GDB remote protocol over TCP IP socket connection Simulator Target The XMD simulator is a cycle accurate ISS of the MicroBlaze system which presents the simulated MicroBlaze system state to GDB Hardware Target 170 With the hardware target XMD communicates with Microprocessor Debug Module mdm debug core or an xmpstTus program running on a hardware board through the serial cable or JTAG cable and presents the running MicroBlaze system state to GDB For more information about XMD refer to Chapter 10 Xilinx Microprocessor Debugger XMD www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX PowerPC 405 Targets Compiling for Debugging on MicroBlaze Targets To debug a program you must generate debugging information when you compile the program This debugging information is stored in the object file it describes the data type of each variable or function and the correspondence between source line numbers and addresses in the executable code The mb gcc compiler for the Xilinx MicroBlaze soft processor includes this information when the appropriate modifier is specified The g option in mb gcc allows you to perform debugging at the source level The debugger mb gcc adds appropriate information to the executable file which helps in debugging the code The debugger mb gdb provides debuggi
307. ript updates are provided to allow for the addition of new sections that support GCC 3 4 1 changes Changes in 6 3i Updates MHS The EDGE and LEVEL subproperties on top level interrupt ports are consolidated into the SENSITIVITY subproperty in the MHS file Changes in 6 2i No Project Updates The mb gcc compiler option related to the hard multiplier is removed This is based only on FPGA architecture Updates MSS In the MSS file the PROCESSOR block is split into two blocks PROCESSOR and OS In conjunction with this change The Linux and VxWorks LIBRARY blocks are renamed to reflect their new status as OS blocks With the introduction of the OS block all peripherals used with Linux and VxWorks operating systems are specified using a CONNECTED_PERIPHS parameter which replaces the CONNECT_TO parameter used in earlier versions When the Format Revision Tool runs it collects old CONNECT_TO driver parameter peripherals and collates them in the CONNECTED_PERIPHS parameter of the OS block In the MSS file PROCESSOR block the following parameters are removed LEVEL EXECUTABLE SHIFTER and DEFAULT _ INIT In the PROCESSOR block the DEBUG_PERIPHERAL is renamed XMDSTUB_PERIPHERAL Command Line Option for the Format Revision Tool Run the Format Revision tool from the command line as follows revup system xmp The following option is supported h Help Displays the usage menu and then quits The Version Manageme
308. rm Specification Format Reference Manual for further details and examples Appendix E Additional Resources contains a link to the document 252 www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 XILINX Additional Keywords in the Merged Hardware Datastructure Helper Core Tcl Procedures All the illustrated Tcl procedures must be specified in the top level cores If a top level core is using helper or library cores you can execute Tcl procedures specific to those helper cores by using one of two procedures SYSLEVEL_GENERIC_PROC and SYSLEVEL_ARCHSUPPORT_PROC These tcl procedures must be specified in the data directory of the helper core and must follow the same naming conventions as the other PSF files For example a Tcl file for the proc_common_v1_00_a core must be named ina corresponding nomenclature proc_common_v2_1_0 tcl e The SYSLEVEL_GENERIC_PROC procedure is a generic procedure used to print any message e The SYSLEVEL_ARCHSUPPORT_PROC procedure is used to notify users of deprecated helper cores For example if the proc_common_v1_00_a core is deprecated the core developer can print a message in the tools every time this core is used within a non deprecated top level core by including this procedure in the tcl file of the helper core in the proc_common_v2_1_0 tc1 file of the proc_common_v1_00_a core as follows proc sysleve
309. roc myip_syslevel_update_proc ipinst_handle do something return 0 DRC Procedure for a Parameter After System Level Analysis Use the tag SYSLEVEL_DRC_PROC to specify Tcl procedure that performs DRC on the complete IP based on how the IP has been used in the system Input is a handle to the parameter object of a particular instance of that IP PARAMETER C_MYPARAM 5 SYSLEVEL_DRC_PROC sysdrc_myparam Embedded System Tools Reference Manual www xilinx com 251 UG111 July 06 2011 Appendix C EDK Tel Interface XILINX DRC Procedure for the IP After System Level Analysis Use the OPTION SYSLEVEL_DRC_PROC to specify the Tcl procedure that performs DRC after Platgen updates system level information The input handle is a handle to an instance of the IP For example if this particular IP has been instantiated the procedure can check to limit the number of instances of this IP check that this IP is always used in conjunction with another IP or check that this IP is never used along with another IP MPD Snippet OPTION SYSLEVEL_DRC_PROC syslevel_drce BUS_INTERFACE BUS SPLB BUS_STD PLB BUS_TYPE SLAVE PORT MYPORT DIR O Tcl snippet proc syslevel_dre ipinst_handle set myport_conn xget_hw_port_value Sipinst_handle MYPORT set mhs_handle xget_hw_parent_handle Sipinst_handle set sink_ports xget_hw_connected_ports_handle mhs_handle Sm
310. rol to the second stage _crtinit startup routine On returning from _crtinit it returns program control back to the XMDStub which signals to the debugger that the program has finished crt2 o This initialization file is used when the executable is loaded using a bootloader It populates all the vectors except the reset vector and transfers control to the second stage _crtinit startup routine On returning from _crtinit it ends the program by infinitely looping at the _exit label Because the reset vector is not populated on a processor reset control is transferred to the bootloader which can reload and restart the program crt3 o This initialization file is employed when the executable does not use any vectors and wishes to reduce code size It populates only the reset vector and transfers control to the second stage __crtinit startup routine On returning from __crtinit it ends the program by infinitely looping at the _exit label Because the other vectors are not populated the GNU linking mechanism does not pull in any of the interrupt and exception handling related routines thus saving code space Second Stage Initialization Files According to the C standard specification all global and static variables must be initialized to 0 This is a common functionality required by all the CRTs above Another routine _certinit is invoked The _crtinit routine initializes memory in the bss section of the program The _crtinit routine is also
311. rovides a separate installer for these called the Xilinx EDK BFM Package To use the Xilinx EDK BFM Package you must register and obtain a license to use the IBM CoreConnect Toolkit at http www xilinx com products ipcenter dr_pcentral_coreconnect htm After you register you receive instructions and a link to download the CoreConnect Toolkit files You can then install the files using the registration key provided After running the installer you can verify that the files were installed by typing the following command xilbfc check A Success message indicates you are ready to continue otherwise you will receive instructions on the error Using the Platform Studio BFM Package After successfully downloading and installing the Platform Studio BFM Package you can launch Platform Studio The following components are available e PLB v4 6 Master BFM plbv46_master_bfm The PLB v4 6 master model contains logic to initiate bus transactions on the PLB v4 6 bus automatically The model maintains an internal memory that can be initialized through the Bus Functional Language and may be dynamically checked during simulation or when all bus transactions have completed e PLB v4 6 Slave BFM plbv46_slave_bfm Embedded System Tools Reference Manual www xilinx com 55 UG111 July 6 2011 Chapter 6 Bus Functional Model Simulation XILINX The PLB v4 6 slave contains logic to respond to PLB v4 6 bus transactions based o
312. rpose Register Names Table 10 4 lists the special register names that are valid for PowerPC 440 processors Table 10 4 PowerPC 440 Processor Special Purpose REgister Names pe fpscr srr0 dear csrr1 dac2 dbdr iac4 decar ivor4 ivor10 inv0 itv2 dtv0 dcdbtrl mcsrr1 f5 f11 f17 23 29 msr pvr srr1 ivpr dbsr pir ccr0 dbcr2 uspre0 ivord ivor11 inv1 itv3 dtv1 dedbtrh f0 f6 f12 f18 f24 30 cr sprg0 tbl tsr dbcr0 rstcfg dbcr1 sprg4 ivor0 ivor6 ivor12 inv2 dnv0 dtv2 icdbtrl f1 f7 f13 f19 f25 f31 lr sprg1 tbu tcr iacl mmucr dvcl sprg5 ivorl ivor7 ivor13 inv3 dnv1 dtv3 icdbtrh f2 f8 f14 f20 f26 ctr sprg2 s icdbdr dec iac2 pid dvc2 sprg6 ivor2 ivor8 ivorl4 itv0 dnv2 dvlim mcsr f3 f9 f15 f21 27 xer prg3 esr csrr0 dacl ccr1 iac3 sprg7 ivor3 ivor9 ivor15 itv1 dnv3 ivlim mesrr0 f4 f10 f16 22 28 Note XMD always uses 64 bit notation to represent the Floating Point Registers f0 f31 In the case of a Single Precision floating point unit the 32 bit Single Precision value is extended to a 64 bit value For additional information about PowerPC 440 processor special register names refer to the Register Set Summary section of the PowerPC 440 Processor Block Reference Guide A link to the document is supplied in Appendix E Additional Resources XMD Reset Sequence When the rst command is issued XMD resets
313. s Slave FSL Ports Table 2 10 contains the required Slave FSL port naming conventions Table 2 10 Slave FSL Port Naming Conventions lt nFSL gt or A meaningful name or acronym for the slave I O The last five characters of lt nFSL_S gt lt nFSL_S gt must contain the string FSL_S upper lower or mixed case lt BI gt A bus identifier Optional for peripherals with a single slave FSL port and required for peripherals with multiple slave FSL ports lt BI gt must not contain the string FSL_S upper lower or mixed case For peripherals with multiple slave FSL ports the lt BI gt strings must be unique for each bus interface FSL Slave Outputs For interconnection to the FSL slaves must provide the following outputs lt BI gt lt nFSL_S gt _Data lt BI gt lt nFSL_S gt _Control lt BI gt lt nFSL_S gt _Exists Examples FSL_S_ Control Memcon_FSL_S_ Control out std_logic_vector 0 to C_ lt BI gt FSL_DWIDTH 1 out std_logic out std_logic out out Busl_timer_FSL_S Control out Bus1_timer_FSL_S_ Data Bus2_timer_FSL_S Control out Bus2_timer_FSL_S_ Data FSL Slave Inputs out out std_logic std_logic std_logic std_logic_vector 0 to C_ lt BI gt FSL_DWIDTH 1 std_logic std_logic_vector 0 to C_ lt BI gt FSL_DWIDTH 1 For interconnection to the FSL slaves must provide the following inputs lt BI gt lt nFSL gt _C1k lt BI gt lt nFSL gt _Rst lt BI gt
314. s API will also be a merged handle Arguments lt handle gt is one of the following PARAMETER the parent is the MPD IP instance or the merged IP instance object PORT the parent is the MPD IP instance the merged IP instance or the MHS object BUS_INTERFACE the parent is the MPD IP instance or the merged IP instance object IO_INTERFACE the parent is the MPD or the merged IP instance object e OPTION the parent is the MPD or the merged IP instance object IPINST the parent is the MHS or the merged MHS object e For MHS or MPD the parent is a NULL handle xget_hw_pcore dir from_mpd lt mpd_handle gt Description Returns the pcore directory path for the MPD Arguments lt mpd_hand1le gt is the handle to the MPD xget_hw_pcore dir lt ipinst_handle gt Description Returns the pcore directory for the given IP instance Arguments lt ipinst_hand1e gt is the handle to the IP instance xget_hw port connectors list lt ipinst_handle gt lt portName gt Description If the value connector of the port is within an amp separated list this API splits that list and returns a list of strings connector names Arguments lt ipinst_hand1le gt is the handle to the IP instance merged or original lt portName gt is the name of the port whose connectors are needed Embedded System Tools Reference Manual www xilinx com 237 UG111 July 06 2011 Appendix C EDK Tel Interface XILINX
315. s an example of how to handle timer counter interrupts but is application specific paramCallBackRef is a pointer to the callback function paramTmrCtrNumber is the number of the timer to which this handler is associated with returnNone noteNone RHEE KKRKEKR KEKE ERE REE RK KERR EERE REE EKER EEK EKER ER EK EKER KER ERE RE REE EREREKREEEE void TimerCounterHandler void CallBackRef u8 TmrCtrNumber XTmrCtr InstancePtr XTmrCtr CallBackRef Check if the timer counter has expired checking is not necessary since that s the reason this function is executed this just shows how the callback reference can be used as a pointer to the instance of the timer counter that expired increment a shared variable so the main thread of execution can see the timer expired ay if XTmrCtr_IsExpired InstancePtr TmrCtrNumber TimerExpired if TimerExpired 3 XTmrCtr_SetOptions InstancePtr TmrCtrNumber 0 Embedded System Tools Reference Manual www xilinx com 227 UG111 July 06 2011 Appendix B Interrupt Management XILINX 228 www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 XILINX Appendix C EDK Tcl Interface Introduction This appendix describes the various Tool Command Language Tcl Application Program Interfaces APIs available in EDK tools and methods for accessing information from EDK tools using Tcl APIs Each time EDK tools run they
316. s are the last sectors in the flash In a bottom boot flash device the smallest sectors are the first sectors in the flash layout After you determine the flash device type you must copy over the files to create a custom programming flow e If you have a bottom boot flash add the following line in your etc flash_params tcl file set FLASH_BOOT_CONFIG BOTTOM _BOOT_FLASH e Ifyou have a top boot flash add the following line in your etc flash_params tcl file set FLASH BOOT CONFIG TOP_BOOT FLASH Next run the flash programming from the command line with the following command xmd tcl flashwriter tcl Internally these variables cause the flash programmer to rearrange the sector map according to the boot topology 194 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Customizing Flash Programming Data Polling Algorithm for AMD Fujitsu Command Set The DQ7 data polling algorithm is used during erasure and programming operations on flash hardware that supports the AMD Fujitsu command set Certain flash devices are known to use a configuration register to control the behavior of the data polling DQ7 bit Some known flash devices that offer this configuration register feature are AT49BV322A T AT49BV162A T and AT49BV163A T It is required that DQ7 output 0 during an erase operation and 1 at the end of the operation Similarly DQ7 must output inverted data during programming and the actual
317. s gt block Continues from current PC or optionally specified lt Execute Start Address gt If block option is specified the command returns when the Processor stops on breakpoint or watchpoint The block option is useful in scripting xcycle step lt target id gt cycles Cycle steps through one clock cycle of PowerPC processor ISS If cycles is specified then step cycles number of clock cycles xlist lt target id gt Lists all of the breakpoint addresses xremove lt target id gt lt addr gt lt function name gt lt bp id gt all Removes one or more breakpoints or watchpoints xreset lt target id gt reset type Resets target Optionally provide target specific reset types such as the signals mentioned in Table 10 19 on page 167 xrun lt target id gt Runs program from the program start address xstate lt target id gt Returns the processor target state running or stopped xstep lt target id gt Single steps one MicroBlaze instruction If the PC is at an IMM instruction the next instruction also runs During a single step interrupts are disabled by keeping the BIP flag set Use xcont inue with breakpoints to enable interrupts while debugging xstop lt target id gt Stops the program execution xwatch lt target id gt r w lt address gt lt data value gt Sets read write watchpoints at a given lt address gt and optionally ch
318. s suite with which you can develop your embedded processor hardware e The Software Development Kit SDK based on the Eclipse open source framework which you can use to develop your embedded software application SDK is also available as a standalone program e Embedded processing Intellectual Property IP cores including processors and peripherals While the EDK environment supports creating and implementing designs the recommended flow is to begin with an ISE project then add an embedded processor source to the ISE project EDK depends on ISE components to synthesize the microprocessor hardware design to map that design to an FPGA target and to generate and download the bitstream For information about ISE refer to the ISE software documentation For links to ISE documentation and other useful information see Appendix E Additional Resources Embedded System Tools Reference Manual www xilinx com 7 UG111 July 6 2011 Chapter 1 Embedded System and Tools Architecture Overview XILINX Design Process Overview n lt HDL or Schematic Add Embedded Source The tools provided with EDK are designed to assist in all phases of the embedded design process as illustrated in Figure 1 1 SDK XPS Launches Automatically Design Entry 1 Create design in Base System Builder automatically launches the first time 2 Modify design in System Assembly View Other Sources
319. se files is the EDK installation directory When using the G compiler the Libsupc aand libstdc a files are also referenced These are the C language support and C platform libraries respectively Output Files The compiler generates the following files as output e AnELF file The default output file name is a exe on Windows e Assembly file if save temps or S option is used e Object file if save temps or c option is used e Preprocessor output i or ii file if save temps option is used File Types and Extensions The GNU compiler determines the type of your file from the file extension Table 9 1 lists the valid extensions and the corresponding file types The GCC wrapper calls the appropriate lower level tools by recognizing these file types Table 9 1 File Extensions Extension File type Dialect lt C file aC C file CXX C file Cpp C file C C file ce C file S Assembly file but might have preprocessor directives S Assembly file with no preprocessor directives 86 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Common Compiler Usage and Options Libraries Table 9 2 lists the libraries necessary for the powerpc_eabi_gcec and mb_gcc compilers Table 9 2 Libraries Used by the Compilers Library Particular libxil a Contain drivers software services such as XilMFS and initialization files develope
320. sections are mapped to memories in the system You do not need a linker script if you do not want to change the default contiguous assignment of program contents to memory There is a default linker script provided with the linker that places section contents contiguously You can selectively modify only the starting address of your program by defining the linker symbol _TEXT_START_ADDR on MicroBlaze processors or _START_ADDR on PowerPC processors as displayed in this example mb gcc lt input files and flags gt W1 defsym Wl TEXT START _ADDR 0x100 powerpc eabi gcc lt input files and flags gt W1 defsym Wl TEXT START ADDR 0x2000 mb 1ld lt o files gt defsym _TEXT START _ADDR 0x100 Embedded System Tools Reference Manual www xilinx com 97 UG111 July 6 2011 Chapter 9 GNU Compiler Tools XILINX The choices of the default script that will be used by the linker from the XILINX_EDK gnu lt procname gt lt platform gt lt processor_name gt 1lib ldscripts area are described as follows e e1f32 lt procname gt x is used by default when none of the following cases apply e e1f 32 lt procname gt xn is used when the linker is invoked with the n option e e1 32 lt procname gt xbn is used when the linker is invoked with the N option e e1f 32 lt procname gt xr is used when the linker is invoked with the r option e e1f 32 lt procname gt xu is used when the linker is invoked with the Ur option where lt procn
321. sh hardware e Flash hardware is assumed to be in a reset state when programming is attempted by the flash programming stub e Flash sectors are assumed to be in an unprotected state www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Flash Programmer Performance The flash programming stub does not attempt to unlock or initialize the flash and reports an error if the flash hardware is not in a ready and unlocked state Note The flash programmer does not currently support dual die flash devices which require every flash command to be offset with a Device Base Address DBA value Examples of such dual die devices are the 512 Mbit density devices in the Intel StrataFlash Embedded Memory P30 family of flash memory Flash Programmer Performance The following factors determine the speed at which an image can be programmed e The flash programmer communicates with the in system programming stub using JTAG Consequently the inherent bandwidth of the JTAG cable is in most cases the bottleneck in programming flash e When it is available on the system it is best to use external memory as scratch memory This will allow the debugger to download the flash image data without having to stream it in multiple iterations e Itis desirable to implement the fastest configuration possible when using the MicroBlaze soft processor You can improve programming speed by turning on features such as the barrel
322. sm When adding VHDL files those files are expected to be an instance specific customization and consequently are added to a logical library called lt instname gt _ lt wrapper gt _ lt hwver gt VHDL files must be generated in the lt projdir gt hdl elaborate lt instname gt _ lt wrapper gt _ lt hwver gt directory While Verilog does not use libraries the files must still be generated in the specified directory structure and location lt ipinst_handle gt is the handle of the IP instance lt fileuse gt is lib synlib simlib lt filename gt is the specified filename lt hd1lang gt is vhdl verilog xadd_hw_hdl_srcfile ipinst_handle lib xps_central_dma vhd vhdl xadd_hw_ipinst_busif lt ipinst_handle gt lt busif_name gt lt busif_value gt Description Arguments Example Creates and adds a bus interface specified by lt busif_name gt and lt busif_value gt to the IP instance specified by the lt ipinst_handle gt This API returns a handle to the newly created bus interface if successful and NULL otherwise lt ipinst_handle gt is the handle to the IP instance to which the bus interface has to be added lt busif_name gt is the name of the bus interface lt busif_value gt is the value of the bus interface Connect the ILMB bus interface from MicroBlaze to the ilmb_0 bus xadd_hw_ipinst_busif mb_handle ILMB ilmb_0 Embedded System Tools Reference Manual www xilinx com 243 UG111 July 06 2011
323. small un initialized data of a size less than 8 bytes You can change the size of the data going into this section with the G option This section has the w read write flag and must be mapped to RAM bss This section contains un initialized data This section has the w read write flag and must be mapped to RAM heap This section contains uninitialized data that is used as the global program heap Dynamic memory allocation routines allocate memory from this section This section must be mapped to RAM stack This section contains uninitialized data that is used as the program stack This section must be mapped to RAM This section is typically laid out right after the heap section In some versions of the linker the stack and heap sections might appear merged together into a section named bss_stack init This section contains language initialization code and has the same flags as text It must be mapped to initialized ROM fini This section contains language cleanup code and has the same flags as text It must be mapped to initialized ROM ctors This section contains a list of functions that must be invoked at program startup and the same flags as data and must be mapped to initialized RAM www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Common Compiler Usage and Options dtors This section contains a list of functions that must be invoked at program end the
324. ss Special PowerPC Features using XMD I Cache Data 0x70000000 0x70007fff T Cache TAG isses esc 0x70008000 0x7000ffff D Cache Data 0x78000000 0x78007fff D Cache TAG 0x78008000 0x7800ffff DCR escort orceca Sos Se sold s Byes 0x78020000 0x78020fff TEB es eaaa o E aN 0x70020000 0x70023fff Connected to ppc target id 0 Starting GDB server for ppc target id 0 at TCP port no 1234 XMD targets System 0 Hardware System on FPGA Device 5 Targets Target 0 PowerPC440 1 Hardware Debug Target XMD Example with a Program Running in ISOCM Memory and Accessing DCR Registers This example demonstrates a simple debug session with a program running on ISOCM memory of the PowerPC 405 processor target The ISOCM address parameters can be specified during the connect command If the XMP file is loaded XMD infers the ISOCM address parameters of the system from the MHS file Note In a Virtex 4 device ISOCM memory is readable This enables better debugging of a program running from ISOCM memory 146 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Connect Command Options XMD connect ppc hw debugdevice isocmstartadr OxFFFFE000 isocmsize 8192 isocmdcrstartadr 0x15 dcrstartadr 0xab000000 JTAG chain configuration Device ID Code IR Length Part Name 1 0a001093 8 System_ACE 2 5059093 16 XCF32P 3 01e58093 10 XC4VFX12 4 49608093
325. ssor Local Bus PLB or any other system level signals In addition you can configure the parameters of an existing ChipScope core for hardware debugging You can also provide JTAG based virtual input and output To configure the software for debugging you can set the processor debug parameters When co debugging is enabled for a ChipScope core you can set up mutual triggering between the software debugger and the hardware signals The JTAG interface can be configured to transport UART signals to the Xilinx Microprocessor Debugger XMD For detailed information on using the features provided in the Debug Configuration wizard see the Xilinx Platform Studio Help Simulation Model Generator Simgen The Simulation Platform Generation tool Simgen generates and configures various simulation models for the hardware To generate a behavioral model Simgen takes an MHS file as its primary design input For generating structural or timing models Simgen takes its primary design input from the post synthesis or post place and route design database respectively Simgen also reads the embedded application executable ELF file for each processor to initialize on chip memory thus allowing the modeled processor s to execute their software code during simulation Simgen also provides simulation models for external memory and has automated support to instantiate memory models in the simulation testbench and perform connection with the design under test
326. st processor peripherals have a single bus interface This is the simplest model for the PsfUtility For most such peripherals complete MPD specifications can be obtained without any additional attributes added to the source code Signal Naming Conventions The signal names must follow the conventions specified in Conventions for Defining HDL Peripherals on page 23 When there is only one bus interface no bus identifier need be specified for the bus signals Invoking the PsfUtility The command line for invoking PsfUtility is as follows psfutil hdl2mpd lt hdlfile gt lang vhdl ver top lt top_entity gt bus lt busstd gt lt bustype gt o lt mpdfile gt For example to create an MPD specification for an PLB slave peripheral such as UART the command is psfutil hdl2mpd uart vhd lang vhdl top uart bus plb s o uart mpd Alternatively you can use a prj file as input for invoking PsfUtility as follows psfutil hdl2mpd uart prj lang vhdl top uart bus plb s o uart mpd Embedded System Tools Reference Manual www xilinx com 21 UG111 July 6 2011 22 Chapter 2 Platform Specification Utility PsfUtility XILINX Peripherals with Multiple Bus Interfaces Some peripherals might have multiple associated bus interfaces These interfaces can be exclusive bus interfaces non exclusive bus interfaces or a combination of both All bus interfaces on the peripheral that can be connected to the peripheral simultaneously
327. st_port lt ipinst_handle gt lt port_name gt lt connector_name gt xadd_hw_ipinst lt mhs_handle gt lt inst_name gt lt ip_name gt lt hw_ver gt xadd_hw_ipinst_parameter lt ipinst_handle gt lt param_name gt lt param_value gt xadd_hw_subproperty lt prop_handle gt lt subprop_name gt lt subprop_value gt xadd_hw_toplevel_port lt mhs_handle gt lt port_name gt lt connector_name gt lt direction gt Delete Commands xdel_hw_ipinst lt mhs_handle gt lt inst_name gt xdel_hw_ipinst_busif lt ipinst_handle gt lt busif_name gt xdel_hw_ipinst_port lt ipinst_handle gt lt port_name gt xdel_hw_ipinst_parameter lt ipinst_handle gt lt param_name gt xdel_hw_subproperty lt prop_handle gt lt subprop_name gt xdel_hw_toplevel_port lt mhs_handle gt lt port_name gt Modify Commands xset_hw_parameter_value lt busif_handle gt lt busif_value gt xset_hw_port_value lt port_handle gt lt port_value gt xset_hw_busif_value lt busif_handle gt lt busif_value gt www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 g XILINX Tcl Example Procedures Advance Write Access Hardware API Descriptions Add Commands xadd_hw_hdl srcfile lt ipinst_handle gt lt fileuse gt lt filename gt lt hdllang gt Description Arguments Example Adds HDL files on the fly to the PAO This API should only be used in batch tools like platgen simgen and not in xps batch as a design entry mechani
328. stem design Figure B 5 shows a PowerPC processor interrupt flow without an interrupt controller User Program xvectors S section vectors Branch to vectoring code Branch to vectoring code INTR critical intr Interrupt Vectoring Code others p 9 user or peripheral interrupt handler function external intr Lookup the interrupt handler registered with the OS for the current interrupt type and jump to it others User or peripheral interrupt handlers registered directly with the OS layer XExc_VectorTable X11021 Figure B 5 PowerPC Processor Interrupt Flow without Interrupt Controller Figure B 6 shows a PowerPC processor interrupt flow with an interrupt controller User Program xvectors S section vectors Branch to critical intr vectoring code others Interrupt Vectoring Code Branch to __ xinte c external intr vectoring code XIntc_DevicelnterruptHandler Lookup the P interrupt handler user or peripheral others registered with interrupt handler function the OS for the current interrupt type and jump to it For each active interrupt call the registered interrupt handler XExc_VectorTable XIntc_DevicelnterruptHandler registered with the OS layer User or peripheral interrupt handlers registered with the interrupt controller driver HandlerTable X11022 Figure B 6 PowerPC Processor Interrupt Flow w
329. such as the interrupt signal AXI Master Clock and Reset M_AXI_ACLK M_AXI_ARESETN AXI Slave Clock and Reset S_AXI_ACLK S_AXI_ARESETN LMB Clock and Reset LMB_C1k LMB_Rst PLBV46 Master Clock and Reset MPLB_C1k MPLB_Rst PLBV46 Slave Clock and Reset SPLB_C1k SPLB_Rst 1 ACLK and or ARESETN can be bus interface specific or can be global across bus interfaces Global ports must be named ACLK and ARESETN Embedded System Tools Reference Manual www xilinx com 27 UG111 July 6 2011 Chapter 2 Platform Specification Utility PsfUtility XILINX Master AXI4 Ports Master AXI4 ports must use the naming conventions shown in Table 2 5 Table 2 5 Master AXI4 Port Naming Conventions lt BI gt A bus identifier For peripherals with multiple AXI4 ports the lt BI gt strings must be unique for each bus interface Trailing underline characters such as the lt BI gt string are ignored in AXI4 Master Outputs lt BI gt _awaddr lt BI gt _awlen lt BI gt _awsize lt BI gt _awburst lt BI gt _awprot lt BI gt _awcache lt BI gt _awvalid lt BI gt _wdata lt BI gt _wstrb 0 lt BI gt _wlast lt BI gt _wvalid lt BI gt _bready lt BI gt _araddr lt BI gt _arlen lt BI gt _arsize lt BI gt _arburst lt BI gt _arprot lt BI gt _arcache lt BI gt _arvalid lt BI gt _rready Examples m_axi_sg_awlen m_axi_sg_aws
330. supported only for Micron Memory Models used with XPS MIG 4 During simulation the following initialization errors can be observed in the simulator console but can be ignored for Behavioral simulation system_axi_tb inst_ddr_00 dqs_neg_timing_check at time 5485244 0 ps ERROR tDQSH violation on DQS bit 0 by 1039 0 ps system_axi_tb inst_ddr_03 cmd_task at time 3438850 0 ps ERROR Load Mode 0 Illegal value Reserved address bits must be programmed to zero Embedded System Tools Reference Manual www xilinx com 73 UG111 July 6 2011 Chapter 7 Simulation Model Generator Simgen XILINX 5 There is no support from Simgen to allow an application to load an ELF into external memory 6 Other non supported external memory models must be manually instantiated and connected in the simulation testbench and initialized according to the model specifications Simulating Your Design 74 When simulating your design there are some special considerations to keep in mind such as the global reset and tristate nets Xilinx ISE tools provide detailed information on how to simulate your VHDL or Verilog design Refer to the Simulating Your Design chapter in the ISE Synthesis and Simulation Design Guide for more information Appendix E Additional Resources contains a link to the document website Helper scripts generated at the test harness or testbench level are simulator setup scripts When run the setup script performs in
331. sym _TEXT_START_ADDR option If this is supplied to mb gcc compiler the text section of the output code starts from the given value You do not have to use defsym _TEXT_START_ADDR if you want to use the default start address set by the compiler This is a linker option and should be used when you invoke the linker separately If the linker is being invoked as a part of the mb gcc flow you must use the following option W1l defsym W1 TEXT START ADDR value relax This is a linker option that removes all unwanted imm instructions generated by the assembler The assembler generates an imm instruction for every instruction where the value of the immediate cannot be calculated during the assembler phase Most of these instructions do not need an imm instruction These are removed by the linker when the relax command line option is provided This option is required only when linker is invoked on its own When linker is invoked through the mb gcec compiler this option is automatically provided to the linker N This option sets the text and data section as readable and writable It also does not page align the data segment This option is required only for MicroBlaze programs The top level GCC compiler automatically includes this option while invoking the linker but if you intend to invoke the linker without using GCC use this option For more details on this option refer to the GNU manuals online A link to the manuals is prov
332. system Simulation Library Compiler Compxlib Compiles the EDK simulation libraries for the target simulator as required before starting behavioral simulation of the design Software Development Kit Software Development and Verification An integrated design environment the Software Development Kit SDK helps with the development of software application projects Library Generator Libgen Constructs a BSP comprising a customized collection of software libraries drivers and OS GNU Compiler Tools Builds a software application based on the platforms created by the Libgen www xilinx com 11 Chapter 1 Embedded System and Tools Architecture Overview 12 XILINX Table 1 1 EDK Tools and Utilities Cont d Xilinx Microprocessor Used for software download and debugging Also provides Debugger a channel through which the GNU debugger accesses the device GNU Debugger GUI for debugging software on either a simulation model or target device Bitstream Initializer Bitinit Updates an FPGA configuration bitstream to initialize the on chip instruction memory with the software executable Debug Configuration Wizard Automates hardware and software platform debug configuration tasks common to most designs System ACE File Generator GenACE Generates a Xilinx System ACE configuration file based on the FPGA configuration bitstream and software executable
333. t state system lt system_id gt state lt target_id gt state system lt system_id gt displays the current state of all targets When a lt target_id gt is specified state of that target is displayed When system lt system_id gt is specified the current state of all the targets in the system is displayed Embedded System Tools Reference Manual UG111 July 6 2011 www xilinx com 131 Chapter 10 Xilinx Microprocessor Debugger XMD XILINX Table 10 2 XMD User Commands Cont d command options stats Example Usage stats trace txt Description Displays execution statistics for the ISS target The lt filename gt is the trace output from trace collection targets system lt system_id gt targets system 1 stats lt filename gt stats stop stop Stops the target For MicroBlaze if the program is stalled at memory or FSL access it is stopped forcibly stp stp Steps through the specified number of instructions stp lt number of instructions gt stp 10 targets targets Lists information about all current targets or changes the current target targets lt target_id gt targets 0 terminal terminal jtag_uart_server lt port_number gt lt baudrate gt terminal terminal jtag_uart_server 4321 high JTAG based hyperterminal to communicate with mdm UART interface The UART interface should be enabled in the mdm If t
334. t lt option_name gt Description Returns the value of the option The value is specified in the MPD file and cannot be overwritten in MHS Arguments lt hand1le gt the handle to an MPD or a merged IP instance lt option_name gt is the name of the option whose value is required xget_hw parameter handle lt handle gt lt parameter_name gt Description Returns the handle to an associated parameter Arguments lt handle gt is the handle to the MPD original IP instance or merged IP instance lt parameter_name gt is the name of the associated parameter whose handle is required If lt parameter_name gt is specified as an asterisk a list of parameter handles is returned To access an individual parameter handle you can iterate over the list in Tcl xget_hw parameter _ value lt handle gt lt parameter_name gt Description Returns the value of the specified parameter Arguments lt handle gt is the handle to the MPD original IP instance or merged IP instance lt parameter_name gt is the name of the associated parameter whose value is required 236 www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 XILINX EDK Hardware Tcl Commands xget_hw_ parent_handle lt handle gt Description Returns the handle to the parent of the specified handle The type of parent handle is determined by the specified handle type If the specified handle is a merged handle the parent obtained through thi
335. t and required for peripherals with multiple slave DCR ports lt BI gt must not contain the string DCR upper lower or mixed case For peripherals with multiple slave DCR ports the lt BI gt strings must be unique for each bus interface DCR Slave Outputs For interconnection to the DCR all slaves must provide the following outputs lt BI gt lt Sl1n gt _dcrDBus out std_logic_vector 0 to C_ lt BI gt DCR_DWIDTH 1 lt BI gt lt S1n gt _dcrAck out std_logic Examples Uart_dcrAck out std_logic Intc_dcrAck out std_logic Memcon_dcrAck out std_logic Bus1_timer_dcrAck out std_logic Bus1_timer_dcrDBus out std_logic_vector 0 to C_ lt BI gt DCR_DWIDTH 1 Bus2_timer_dcrAck out std_logic Bus2_timer_dcrDBus out std_logic_vector 0 to C_ lt BI gt DCR_DWIDTH 1 DCR Slave Inputs For interconnection to the DCR all slaves must provide the following inputs lt BI gt lt nDCR gt _ABus in std_logic_vector 0 to C_ lt BI gt DCR_AWIDTH 1 lt BI gt lt nDCR gt _DBus in std_logic_vector 0 to C_ lt BI gt DCR_DWIDTH 1 lt BI gt lt nDCR gt _Read in std_logic lt BI gt lt nDCR gt _Write in std_logic Examples DCR_DBus in std_logic_vector 0 to C_ lt BI gt DCR_DWIDTH 1 Bus1_DCR_DBus in std_logic_vector 0 to C_ lt BI gt DCR_DWIDTH 1 32 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Conventions for Defining HDL Peripheral
336. t lt nFSL_M gt _Clk in std_logic lt BI gt lt nFSL_M gt _Data in std_logic_vector 0 to C_ lt BI gt FSL_DWIDTH 1 lt BI gt lt nFSL_M gt _Control in std_logic lt BI gt lt nFSL_M gt _Write in std_logic Examples FSL_M Write in std_logic Bus1_FSL_M Write in std_logic Busl_timer_FSL_M Control out std_logic Busl_timer_FSL_M Data out std_logic_vector 0 to C_ lt BI gt FSL_DWIDTH 1 Bus2_timer_FSL_M Control out std_logic Bus2_timer_FSL_M Data out std_logic_vector 0 to C_ lt BI gt FSL_DWIDTH 1 34 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Conventions for Defining HDL Peripherals Slave LMB Ports Slave LMB ports must follow the naming conventions shown in Table 2 12 Table 2 12 Slave LMB Port Naming Conventions lt Si1n gt A meaningful name or acronym for the slave output lt S1n gt must not contain the string LMB upper lower or mixed case so that slave outputs will not be confused with bus outputs lt nLMB gt A meaningful name or acronym for the slave input The last three characters of lt nLMB gt must contain the string LMB upper lower or mixed case lt BI gt Optional for peripherals with a single slave LMB port and required for peripherals with multiple slave LMB ports lt BI gt must not contain the string LMB upper lower or mixed case For peripherals with multiple slave LMB ports the lt BI gt strings must be unique
337. t _ prefix where lt BusIf gt is the actual name of the bus interface such as M_AXI_DP in MicroBlaze Allowed Parameters in Master and Slave Interfaces The following parameters are allowed in Master and Slave interfaces These are described in more detail in the MPD chapter of the Platform Specification Format Reference Manual For Master Interfaces the allowed parameters are e C_INTERCONNECT_ lt e nN CO AOAO OMA 2 0 2 A A Arvo On 1 VE A INTERCONNECT_ lt INTERCONNECT_ lt NTERCONNECT_ lt INTERCONNECT_ lt INTERCONNECT_ lt INTERCONNECT_ lt INTERCONNECT_ lt INTERCONNECT_ lt INTERCONNECT_ lt INTERCONNECT_ lt INTERCONNECT_ lt INTERCONNECT_ lt _ INTERCONNECT _ lt INTERCONNECT_ lt INTERCONNECT_ lt INTERCONNECT_ lt INTERCONNECT_ lt _ INTERCONNECT _ lt Buslf gt _BASE_ ID Buslf gt _IS_ACLK ASYNC Buslf gt _ACLK RATIO Buslf gt _ARB_ PRIORITY Buslf gt _AW_REGISTER Buslf gt _AR_ REGISTER Buslf gt _W_REGISTER Buslf gt _R_REGISTER Buslf gt _B_ REGISTER Buslf gt _WRITE_FIFO_DEPTH Buslf gt _READ FIFO_DEPTH Buslf gt _WRITE_ISSUING Buslf gt _READ ISSUING lave Interfaces the allowed parameters are
338. t param_value gt Description Creates and adds a parameter specified by lt param_name gt and lt param_value gt to the IP instance specified by the lt ipinst_handle gt This API returns a handle to the newly created parameter if successful and NULL otherwise Arguments lt ipinst_hand1e gt is the handle to the IP instance to which the parameter is to be added lt param_name gt is the name of the parameter lt param_value gt is the parameter value Example Add the C_DEBUG_ENABLED parameter to a MicroBlaze instance and set its value to 1 xadd_hw_ipinst_parameter mb_ handle C_DEBUG_ ENABLED 1 244 www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 XILINX Tcl Example Procedures xadd_hw_subproperty lt prop_handle gt lt subprop_name gt lt subprop_value gt Description Arguments Example Adds a subproperty to a property parameter port or bus interface lt prop_handle gt is a handle to the parameter port or bus interface lt subprop_name gt is the name of the sub property lt subprop_value gt is the value of the sub property For a list of sub properties refer to Microprocessor Peripheral Definition MPD in the Platform Specification Format Reference Manual and Additional Keywords in the Merged Hardware Datastructure on page 253 Add DIR to a port xadd_hw_subproperty port_handle DIR I xadd_hw_toplevel_port lt mhs_handle gt lt port_name gt
339. t use the naming conventions shown in Table 2 7 Table 2 7 Master AXI4LITE Port Naming Conventions lt BI gt A bus identifier For peripherals with multiple AXI4 ports the lt BI gt strings must be unique for each bus interface Trailing underline characters such as _ in the lt BI gt string are ignored AXI4LITE Master Outputs lt BI gt _arvalid lt BI gt _araddr lt BI gt _arprot lt BI gt _rready lt BI gt _awvalid lt BI gt _awaddr lt BI gt _awprot lt BI gt _wvalid lt BI gt _wdata lt BI gt _wstrb 0 lt BI gt _bready Examples m_axi_lite_wdata downto 0 m_axi_lite_wstrb downto 0 m_axi_lite_bready AXI4LITE Master Inputs lt BI gt _arready lt BI gt _rvalid lt BI gt _rdata lt BI gt _rresp lt BI gt _awready lt BI gt _wready lt BI gt _bvalid lt BI gt _bresp Examples m_axi_lite_rdata downto 0 m_axi_lite_rresp m_axi_lite_awready ou ou ou ou ou ou ou ou ou ou ou ou ou ou in in in in in in in in t std_logic t std_logic_vector C_ lt BI gt _ADDR_WIDTH 1 downto 0 t std_logic_vector 2 downto 0 t std_logic t std_logic t std_logic_vector C_ lt BI gt _ADDR_WIDTH 1 downto 0 t std_logic_vector 2 downto 0 t std_logic t std_logic_vector C_ lt BI gt _DATA_WIDTH 1 downto 0 t std_logic_vector C_ lt BI gt _DATA_WIDTH 8 1 downto t std_logic t std_logic_vector C_M_AXI_ LITE DATA WIDTH 1
340. tem ACE files is BIT to SVF ELF to SVF binary data to SVF SVF to ACE file The following section describes the options available in the genace tcl script www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX The Genace tcl Script The Genace tcl Script The genace tcl script uses Xilinx Microprocessor Debug XMD commands to generate ACE files This script is located in the XILINX_EDK data xmd directory Some non supported boards might require some customization such as changing the delay of programming after FPGA configuration or modifying the processor reset sequence For these boards copy the script to the local directory make the required changes and then use it to generate the ACE file Table 13 1 list the genace tcl script command options Syntax xmd tcl genace tcl ace lt ACE_file gt board lt board_type gt data lt data_files gt lt load_address gt elf lt elf_files gt hw lt bitstream_file gt jprog true false opt lt genace_options_file gt target lt target_type gt ppc_hw mdm Table 13 1 genace tcl Script Command Options Options Default Description ace lt ACE_file gt none The output ACE file The file prefix should not match any of input files bitstream elf data files prefix board lt board_type gt none This identifies the JTAG chain on the board Devices IR supported_board_list length Debug device and so
341. terface port 6470 protocol tcp XMD Connected to PowerPC Sim Controlling interface connected Connected to PowerPC target id 0 Starting GDB server for target id 0 at TCP port no 1234 XMD dow dhry2 elf XMD bps O0xffff09d0 XMD con Processor started Type stop to stop processor RUNNING gt DCR TLB and Cache Address Space and Access The XMD sets up address space for you to access TLB entries and Cache entries These address spaces can be specified with tlbstartadr icachestartadr and dcachestartadr as options to the connection command If the TLB and Cache address space is not specified XMD uses a default unused address space for this purpose When connected these address spaces are displayed in the XMD console For example I Cache Data 0x70000000 Ox70007 E I Cache TAG 0x70008000 0x7000ffff D Cache Data 0x78000000 Ox78007 E D Cache TAG 0x78008000 0x7800ffff DCR Scie ae eee 0x78020000 0x78020fff mE EEPE TEE 0x70020000 0x70023fff TLB Access Each TLB entry is represented by a 4 word entry Table 10 12 shows the 4 word entries available for PPC405 and PPC440 Table 10 12 PPC405 and PPC440 TLB Entries Word PPC405 PPC440 1 PID PID 2 TLBHI TLB Word0 excluding PID 3 TLBLO TLB Word1 4 Padded with 0 s TLB Word2 The total 64 TLB entries can be read from or written to the 256 words starting from the TLB st
342. the processor or system to bring them back to known states Following are the sequences of operation that rst does for each type of processors Embedded System Tools Reference Manual UG111 July 6 2011 www xilinx com 135 136 Chapter 10 Xilinx Microprocessor Debugger XMD XILINX PowerPC 405 Processors Disable virtual addressing If reset address 0xFFFFFFFC is writable and not on OCM write a branch to self instruction at the reset location If the reset address is not writable XMD cannot put the processor into a known state Set DBCRO to 0x81000000 Issue reset signal either system reset or processor reset through JTAG Debug Control Register DCR The processor starts running Stop the processor Restore the original instruction at reset address PowerPC 440 Processors 1 Set DBCRO to 0x81000000 2 Set register MMUCR to 0 3 Set DBCR1 and DBCR2 to 0 4 Set up TLB so that virtual addresses are the same as real addresses 5 Synchronize with the shadow TLB 6 If reset address 0xFFFFFFFC is writable write a branch to self instruction at the reset location If the reset address is not writable XMD cannot put the processor into a known state 7 Issue reset signal either system reset or processor reset through JTAG DCR The processor starts running 8 Stop the processor 9 Restore the original instruction at reset address MicroBlaze 1 Set a hardware breakpoint at reset location 0x0
343. ther tools that create the hardware platform work with the MHS design file and the IP data files MPD Internally the tools create the system view based on these files Each of the IP in the design has an MPD associated with it Optionally it can have an associated Tcl file Tcl files can contain DRC procedures procedures to automate calculation of parameters or they can perform other tasks The Tcl files that are used during the hardware platform generation are present in the individual cores directory along with the MPD files For Xilinx supplied cores the Tcl files are in the lt EDK install area gt hw XilinxProcessorIPLib pcores lt corename gt data directory Tcl Procedures Called During Hardware Platform Generation Platgen and many EDK batch tools such as Libgen Simgen and Bitinit run a few predefined Tcl procedures related to each IP to perform DRCs and to compute values of certain parameters on the IP For information on the Tcl file for a given IP see the Platform Format Specification Reference Manual A link to the document is supplied in Appendix E Additional Resources This section lists the Tcl procedures and describes how they can be called for user IP Tcl procedures can be classified based on e The action performed in that Tcl procedure e DRC These procedures perform DRCs on the system but do not modify the state of the system itself The return code provided by these procedures is captured by Platgen Hence if
344. tify the lowest clock frequency of all the masters and slaves connected to that interconnect That lowest frequency is then considered as base 1 All the ratios are then computed with respect to that frequency For example consider an AXI Interconnect axi_0 with the following e Three masters M1 M2 and M3 with frequencies of 200 MHz 100 MHz and 100 MHz respectively on their M_AXI interfaces e Twoslaves S1 and S2 with frequencies of 100 MHz and 50 MHz respectively on their S_AXI interfaces e A clock frequency of 100 MHz on the AXI Interconnect In this case the tools compute the ratios to be e Lowest clock frequency is on 2 gt ratio 1 e Ratio of M1 with respect to 2 200 50 gt 4 e Ratio of axi_0 with respect to S2 100 50 gt 2 and so on The C_INTERCONNECT_ lt BusIf gt _ACLK_RATIO parameters in the above example have the values as shown below e For M1 Master parameter C_INTERCONNECT_M_AXI_ACLK_RATIO 4 e For M2 Master parameter C_INTERCONNECT_M_AXI_ACLK_RATI Il N e For M3 Master parameter C_INTERCONNECT_M_AXI_ACLK_RATIO 2 e For axi_0 parameter C_INTERCONNECT_ACLK_RATIO 2 e For S1 Slave parameter C_INTERCONNECT_S_AXI_ACLK_RATIO 2 e For S2 Slave parameter C_INTERCONNECT_S_AXI_ACLK_RATIO 1 These values are automatically updated by the tools and you cannot override them www xili
345. tions for AXI Designs Allowed Parameters in Master and Slave Interfaces 00005 255 BUN VectofsS ecceri enepskorn deka ea diwidnne hone Keene te Kniss 257 Parameter Automations 0 0 0 00 000 c ccc aerer erreneren 257 Appendix E Additional Resources Xilinx Resources nunnana aaea ce cece cee e eee e eben ee bneeneeneens 261 ISE Documentation 0 0 00 ccc eee eee eens ene nes 261 EDK Documentation 0 0000 e eee eb ene ne ene 261 EDK Additional Resources 0 ccc cee cece cece een een eens 262 Embedded System Tools Reference Manual www xilinx com 6 UG111 EDK v 13 2 July 6 2011 XILINX Chapter 1 Embedded System and Tools Architecture Overview Scope About EDK This chapter describes the architecture of the embedded system tools and flows provided in the Xilinx Embedded Development Kit EDK for developing systems based on the MicroBlaze embedded processors and the PowerPC 405 and 440 processors The Xilinx Embedded Development Kit EDK system tools enable you to design a complete embedded processor system for implementation in a Xilinx FPGA device EDK is a component of the Integrated Software Environment ISE Design Suite Embedded and System Editions ISE is a Xilinx development system product that is required to implement designs into Xilinx programmable logic devices EDK includes e The Xilinx Platform Studio XPS system tool
346. ue Reed ted Ree weber E E E 43 Synthesis Netlist Cache ic 05 ices cca vlieas eee ie eet betes Leaeeceuren 44 Chapter 5 Command Line Mode Invoking XPS Command Line Mode 00 000 e cece eee 45 Creating a New Empty PRojeet 02 00042 0i4nteennin tans phndecnceeeegerndeah es 45 Creating a New Project With an Existing MHS 00008 46 Opening an Existing Project s 0 ci20sceviorgscstde ce enas cage eregasegealeeees 46 Saving Your Project Files eo 25 oxen ye vio kae kine eh earn EE dane es 46 Setting Project Options 25 0 5 cies cecedacieveies vedi secivdeceteseeee ees 46 Executing Flow Commands 20 06 40cceis cet ee ed ob env ev ee oie Viet vas 48 Reloading an MH S File L a uuan anner hy Iawdseenheue ewe ed eeuten 48 Adding or Updating an ELF File unnan unnan earann ranar r eee 49 Embedded System Tools Reference Manual www xilinx com UG111 EDK v 13 2 July 6 2011 XILINX Deleting an ELF Fle 5 oc sx axcre2eeiedecnues seyret eaeeenae nebacsg dae enaerhhs 49 Archiving Your Project PileS 657 x0 ndh en atk nes pebso ees ceva hacnidsauenesanes 49 Restrictions reinir erie een teehee ee yee ee ee eee 49 Chapter 6 Bus Functional Model Simulation Introduction necete a e dcr dead Sch Naat EE N 51 Bus Functional Simulation Basics 000000 c ccc cette ees 51 Bus Functional Model Use Cases 0c c cece eens 52 Bus Functional Simulation Methods 0 00
347. ugging programs and is typically used to verify that the correct utilities and data are in the correct memory location 210 www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 g XILINX Other Programs and Files mb ranlib This program creates an index for an archive file and adds this index to the archive file itself This allows the linker to speed up the process of linking to the library represented by the archive mb readelf This program displays information about an Executable Linked Format ELF file mb size This program lists the size of each section in the object file This is useful to determine the static memory requirements for utilities and data mb strings This is a useful program for determining the contents of binary files It lists the strings of printable characters in an object file mb strip This program removes all symbols from object files It can be used to reduce the size of the file and to prevent others from viewing the symbolic information in the file Other Programs and Files The following Tcl and Tk shells are invoked by various front end programs e cygitclsh30 e cygitkwish30 e ocygtclsh8s0 e cygwish80 e t1ix4180 Embedded System Tools Reference Manual www xilinx com 211 UG111 July 06 2011 Appendix A GNU Utilities XILINX 212 www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 XILINX Appendix B Interrupt Manageme
348. uired naming conventions for Bus Clock Reset and Interrupt signals These naming conventions are described in detail in Conventions for Defining HDL Peripherals on page 23 Note Following these naming conventions enables the PsfUtility to create a correct and complete MPD file 2 Create an XST Xilinx Synthesis Technology project file or a PAO file that lists the HDL sources required to implement the IP 3 Invoke the PsfUtility by providing the XST project file or the PAO file with additional options For more information on invoking the PsfUtility with different options see the following section Use Models for Automatic MPD Creation page 21 20 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 XILINX Use Models for Automatic MPD Creation Use Models for Automatic MPD Creation You can run the PsfUtility in a variety of ways depending on the bus standard and bus interface types used with the peripheral and the number of bus interfaces a peripheral contains Bus standards and types can be one of the following e AXI4 MASTER e AXI4 SLAVE e AXI4LITE MASTER e AXI4LITE SLAVE e AXISTREAMING same as POINT TO POINT e DCR design control register SLAVE e FSL fast simplex link SLAVE e FSL MASTER e LMB local memory bus SLAVE e PLBV46 processor local bus version 4 6 SLAVE e PLBV46 MASTER e POINT TO POINT BUS special case Peripherals with a Single Bus Interface Mo
349. unicating over XMD sockets interface The session ID is first assigned and subsequent calls return the session ID xtargets listSysID xtargets system lt system_ID gt print listTgtID xtargets target lt target_ID gt print prop Provides system and target information in the current XMD session listSysID returns a list of existing systems system lt system_ID gt provides information on the specified system print prints the different targets in the system listTgtID returns a list of existing targets in the system target lt target_ID gt provides information on the specified target The options print prints the target information prop returns the target properties Register Memory Options Table 10 17 Register Memory Options Option xdata_verify lt target id gt lt Binary filename gt lt load address gt Description Verifies if the lt Binary filename gt was downloaded correctly at lt load address gt memory xdisassemble lt inst gt Disassembles and displays one 32 bit instruction xelf verify lt target id gt lt filename gt elf Verifies if the lt filename gt elf is downloaded correctly to memory If lt filename gt elf is not specified verifies the last downloaded ELF file to target xrmem lt target id gt lt address gt lt number of bytes half word gt b h w xrmem lt target id gt var lt Global Variable Name gt Reads
350. us Functional Model BFM simulation within Xilinx Platform Studio Note BFM simulation can be run with ModelSim QuestaSim and ISim Introduction Bus Functional Simulation provides the ability to generate bus stimulus and thereby simplifies the verification of hardware components that attach to a bus Bus Functional Simulation circumvents the drawbacks to the two typical validation methods which are e Creating a test bench This is time consuming because it involves describing the connections and test vectors for all combinations of bus transactions e Creating a larger system with other known good components that create or respond to bus transactions This is time consuming because it requires that you describe the established connections to the device under test program the added components to generate the bus transactions to which the device will respond and potentially respond to bus transactions that the device is generating Such a system usually involves creating and compiling code storing that code in memory for the components to read and generating the correct bus transactions Bus Functional Simulation Basics Bus Functional Simulation usually involves the following components e A Bus Functional Model e A Bus Functional Language e A Bus Functional Compiler Bus Functional Models BFMs BFMs are hardware components that include and model a bus interface There are different BFMs for different buses For example PL
351. usif mb_handle ILMB xdel_hw_ipinst_port lt ipinst_handle gt lt port_name gt Description Deletes a specified port on an IP instance handle Arguments lt ipinst_handle gt is the handle of the IP instance lt port_name gt is the name of the port to be deleted Example Delete a C1k port on a given MicroBlaze instance xdel_hw_ipinst_port mb_handle Clk xdel hw _ipinst parameter lt ipinst_handle gt lt param_name gt Description Deletes a specified parameter on an IP instance handle Arguments lt ipinst_handle gt is a handle to the IP instance lt param_name gt is the name of the parameter to be deleted Example Delete the C_DEBUG_ENABLED parameter from a MicroBlaze instance xdel_hw_ipinst_parameter mb_ handle C_DEBUG_ ENABLED xdel_ hw _subproperty lt prop _handle gt lt subprop_name gt Description Deletes a specified subproperty from a property handle Arguments lt prop_handle gt is a handle to a parameter port or bus interface lt subprop_name gt is the name of the subproperty Example Delete SIGIS subproperty from a given port xdel_hw_subproperty port_handle SIGIS 246 www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 g XILINX Tcl Example Procedures xdel_ hw _toplevel_port lt mhs_handle gt lt port_name gt Description Deletes a top level port with the specified name Arguments lt mhs_handJ1e gt is the handle to the original MHS lt port_name gt
352. ut in secs gt XMDStub for XMD commands Note Ifthe program has any I O functions such as print or putnum that write output onto the UART or MDM UART it is printed on the console or terminal in which XMD was started Refer to Chapter 8 Library Generator Libgen for more information about libraries and I O functions Figure 10 4 page 158 illustrates a MicroBlaze sub target with an MDM Uart and a UARTlite Embedded System Tools Reference Manual www xilinx com 157 UG111 July 6 2011 Chapter 10 Xilinx Microprocessor Debugger XMD XILINX RS 232 Serial Cable Uartlite OPB PLBv46 Bus Local Memory MDM l Sat OPB PLBv46 Bus Local Memory X10844 MicroBlaze Figure 10 4 MicroBlaze Stub Target with MDM UART and UARTIite 158 www xilinx com Embedded System Tools Reference Manual UG111 July 6 2011 g XILINX Connect Command Options Stub Target Requirements To debug programs on the hardware board using XMD the following requirements must be met XMD uses a JTAG or serial connection to communicate with xMDStub on the board Therefore an mdm or a UART designated as XMDSTUB_PERIPHERAL in the MSS file is necessary on the target MicroBlaze system Platform Generator can create a system that includes a mdm or a UART if specified in its MHS file The JTAG cables supported with the xmpstub mode are e Xilinx parallel cable e Platform USB cable XMDStub o
353. vironment can reserve other memories Refer to the manual of the particular software platform that you are using to find out if any memory locations are deemed reserved Table 9 5 Hardware Reserved Memory Locations Default Text Pr r Famil R rved Memori R rved Pur ocessor Family eserved Memories eserved Purpose Start Address MicroBlaze 0x0 Ox4F Reset Interrupt Excep 0x50 tion and other reserved vector locations PowerPC OxFFFFFFFC Reset vector location OxFFFFO000 OxFFFFFFFF Embedded System Tools Reference Manual www xilinx com 93 UG111 July 6 2011 Chapter 9 GNU Compiler Tools XILINX I O Memory I O memory refers to addresses used by your program to communicate with memory mapped peripherals on the processor buses These addresses are defined as a part of your hardware platform specification User and Program Memory User and Program memory refers to all the memory that is required for your compiled executable to run By convention this includes memories for storing instructions read only data read write data program stack and program heap These sections can be stored in any addressable memory in your system By default the compiler generates code and data starting from the address listed in Table 9 5 and occupying contiguous memory locations This is the most common memory layout for programs You can modify the starting location of your program by defining in the linker the symbol
354. www xilinx com 171 UG111 July 6 2011 Chapter 11 GNU Debugger PowerPC 440 Targets XILINX Debugging for the PowerPC 440 processor is supported by powerpc eabi gdb and XMD through the GDB Remote TCP protocol XMD supports two remote targets Instruction Set Simulator ISS PowerPC 440 Hardware and Cycle Accurate PowerPC To connect to a PowerPC 440 target 1 Start XMD and connect to the board using the connect ppc command as described in Chapter 10 Xilinx Microprocessor Debugger XMD From GDB select Run gt Connect to target In the GDB target selection dialog box specify the following Target Remote TCP Hostname localhost Port 1234 Click OK The debugger powerpc eabi gdb attempts to make a connection to XMD adn if successful prints a message to the shell window where XMD was invoked Select View gt Console to open the console window On the console type set arch powerpc 440 to set the architecture to a PowerPC 440 processor At this point the debugger is connected to XMD in PowerPC 440 mode and controls the debugging The user interface can be used to debug the program and read and write memory and registers Console Mode To start powerpc eabi gdb in the console mode type the following xilinx gt powerpc eabi gdb nw executable elf In the console mode type the following two commands to connect to the board through XMD gdb target remote localhost 1234 gdb load
355. x EDK software platform For example file I O is supported in only a few well defined STDIN STDOUT streams Similarly locale functions thread safety and other such features may not be supported Note The C standard library is not built for a multi threaded environment Common C features such as new and delete are not thread safe Please use caution when using the C standard library in an operating system environment For more information on the GNU C standard library refer to the documentation available on the GNU website A link to the documentation is provided in Additional Resources page 261 Embedded System Tools Reference Manual www xilinx com 121 UG111 July 6 2011 Chapter 9 GNU Compiler Tools XILINX Position Independent Code Relocatable Code The MicroBlaze and PowerPC processor compilers support the fPIC switch to generate position independent code The PowerPC compiler supports the mrelocatable switches to generate a slightly different form of relocatable code While both these features are supported in the Xilinx compiler they are not supported by the rest of the libraries and tools because EDK only provides a standalone platform No loader or debugger can interpret relocatable code and perform the correct relocations at runtime These independent code features are not supported by the Xilinx libraries startup files or other tools Third party OS vendors could use these features as a standard
356. x000_00 18 interrupt handler interrupt handler g registered with For each active function 0x000_00 20 1n ES ll interrupt call the registered interrupt handler MB_InterruptVector Table XIntc_DevicelnterruptHandler registered with the B OS Layer User or peripheral interrupt handlers ja registered with the interrupt controller driver HandlerTable X11020 Figure B 4 MicroBlaze Interrupt Flow with Interrupt Controller 216 www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 XILINX Software Setup and Interrupt Flow Interrupt Flow for PowerPC Systems Interrupts on the PowerPC processors go through the following flow 1 Interrupts must be enabled on the PowerPC processor by setting appropriate bits in the Machine Status Registers MSR Depending on whether critical or non critical or both interrupts are being used appropriate bits must be set Upon the external interrupt signal being raised the processor first disables further interrupts The processor then calculates an address for the interrupt type and jumps to that address The calculation varies between the PowerPC 405 processor and the PowerPC 440 processor e The PowerPC 405 processor consults the software set value of the Exception Vector Prefix Register EVPR and adds a constant offset to this value depending on the interrupt type to determine the final physical address where the vect
357. ximum value of the channel width for the R and B channels between all the slaves and set those values on the AXI Interconnect Embedded System Tools Reference Manual www xilinx com 259 UG111 July 06 2011 Appendix D Interconnect Settings and Parameter Automations for AXI Designs XILINX 260 www xilinx com Embedded System Tools Reference Manual UG111 July 06 2011 XILINX Appendix E Additional Resources Xilinx Resources e ISE Design Suite Installation and Licensing Guide UG798 http www xilinx com support documentation sw_manuals xilinx13_2 iil pdf e ISE Design Suite 13 Release Notes Guide UG631 http www xilinx com support documentation sw_manuals xilinx13_2 im pdf e Xilinx Documentation http www xilinx com support documentation e Xilinx Glossary http www xilinx com support documentation sw_manuals glossary pdf e Xilinx Support http www xilinx com support htm ISE Documentation e Command Line Tools User Guide UG628 http www xilinx com support documentation sw_manuals xilinx13_2 devref pdf e Xilinx Synthesis and Simulation Design Guide UG626 http www xilinx com support documentation sw_manuals xilinx13_2 sim pdf EDK Documentation The following documents are available in your EDK install directory in install_directory doc usenglish You can also access the entire documentation set online at http www xilinx com ise embedded edk_docs htm Individu
358. xmdstub mno xl barrel shift xl mode bootstrap mxl pattern compare xl mode novectors mno xl pattern compare MicroBlaze Linker Options mhard float defsym _TEXT_START_ADDR value msoft float relax mxl float convert N mx float sqrt Processor Feature Selection Options mcpu vxk YY Z This option directs the compiler to generate code suited to MicroBlaze hardware version v X YY Z To get the most optimized and correct code for a given processor use this switch with the hardware version of the processor The mcpu switch behaves differently for different versions as described below e Pr v3 00 a Uses 3 stage processor pipeline mode Does not inhibit exception causing instructions being moved into delay slots e v3 00 a and v4 00 a Uses 3 stage processor pipeline model Inhibits exception causing instructions from being moved into delay slots e v5 00 aand later Uses 5 stage processor pipeline model Does not inhibit exception causing instructions from being moved into delay slots mlittle endian mbig endian Use these options to select the endianness of the target machine for which code is being compiled The endianness of the binary object file produced is also set appropriately based on this switch The GCC driver passes switches to the sub tools as cc1 cclplus ld to set the corresponding endianness in the sub tool The default is mbig endian Note You cannot link together object files of mixed endianness
359. you can take the files from the source area and include them as a part of your application sources Alternatively you can assemble the files into o files and place them in a common area To refer to the newly created object files instead of the standard files use the B directory name command line option while invoking mb gcc To prevent the default startup files from being used use the nostartfiles on the final compile line Note The miscellaneous compiler standard CRT files such as crti o and crtbegin o are not provided with source code They are available in the installation to be used as is You might need to bring them in on your final link command Reducing the Startup Code Size for C Programs If your application has stringent requirements on code size for C programs you might want to eliminate all sources of overhead This section describes how to reduce the overhead of invoking the C constructor or destructor code in a C program that does not require that code You might be able to save approximately 220 bytes of code space by making the following modifications 1 Follow the instructions for creating a custom copy of the startup files from the installation area as described in the preceding sections Specifically copy over the particular versions of crtn s and xcrtinit s that suit your application For example if your application is being bootstrapped and profiled copy crt2 s and pg crtinit s from the installation area
360. yport_conn SINK if llength S sink_ports gt 5 error MYPORT should not drive more than 5 signals return 1 else return 0 Platgen specific Call The OPTION PLATGEN_SYSLEVEL_UPDATE_PROC is called after all the common Tel procedures have been invoked If you want certain actions to occur only when Platgen runs and not when other tools run this procedure can be used MPD Snippet OPTION PLATGEN_SYSLEVEL_UPDATE_PROC platgen_syslevel_update Simgen specific Call The OPTION SIMGEN_SYSLEVEL_UPDATE_PROC is called after all the common Tcl procedures have been invoked If you want certain actions to occur when Simgen runs and not when other tools run this procedure can be used MPD Snippet OPTION SIMGEN_SYSLEVEL_UPDATE_PROC simgen_syslevel_update FORMAT PROC The FORMAT_PROC keyword defines the Tcl entry point that allows you to provide a specialized formatting procedure to format the value of the parameter The EDK tools deliver output files of two HDL types Verilog and VHDL Each format semantic requires that the parameter values be normalized to adhere to a stylized representation suitable for processing For example Verilog is case sensitive and does not have string manipulation functions When developing an IP you can use this Tcl entry point to specify procedures to format string values based on the HDL requirements Refer to the Platfo
361. ystem Builder Allows you to quickly create a working embedded design Wizard using any features of a supported development board or using basic functionality common to most embedded systems For initial project creation it is recommended to use the BSB wizard The Create and Import Peripheral Wizard Coprocessor Wizard Platform Generator Platgen XPS Command Line or No Window Mode Bus Functional Model Assists you in adding your own custom peripheral s to a design The CIP creates associated directories and data files required by XPS the Platform Specification Utility PsfUtility tool enables automatic generation of Microprocessor Peripheral Definition MPD files which are required to create IP peripherals that are compliant with the Embedded Development Kit EDK The CIP wizard in XPS supports features provided by the PsfUtility for MPD file creation recommended Helps you add a coprocessor to a CPU This applies to MicroBlaze based designs only Constructs the programmable system on a chip in the form of HDL and synthesized netlist files Allows you to run embedded design flows or change tool options from a command line Helps simplify the verification of custom peripherals by creating a model of the bus environment to use in place of the actual embedded system Simulation Model Generator Simgen Generates the hardware simulation model and the compilation script files for simulating the complete

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