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Themis PPC64 / TPPC64 Manual

1. 79 TTA D SE gt 959 82 4 93 Cs on Ce C337 E OU 3 o B com ao B 22 g Ho 5 g 5 5 SF n 9 aH uu g lt 913 B E E E E B 5 d B E 0n H g 3 e o WS lt u ps E lt 3 5 14 lt d p e sas g 2 MES zi bd t g 5 g 10 e 81 Cki 9 m 8 8 Eres DE SB Pin 1 978979 n 10685 1 ell OPE 1 g 80 00 m Ls Gua DI 18 SE B Toat ei EET D ego OO go Pee O goer 920 0 0 8 C ulta l oo g E BS a 38885585 0 E SS 22 seda n g 55 Qggnaos 5 sae CHa t cast 59 12 NOE Ne ii 2 88 cesT Fpa imei mi Ol SE o5 88 9 Rao4e i Ae 1 g R4045GG 8 a 5404155 Jol
2. U25 Bm aus ama Serial Ports TUAM 8 E amp F zg E J GC1 re JTAG m bcd MM 6 5V PMC Audio Codec Module Lock AD1881A out Key PCI Express SP Switch EH PLX Technology PMC XMC Module Unt Sume o pt PEX8516AA 25BI VME P2 foo 9 Ano 58 3 3V PMC 28 gt s Module Lock o mo out Key Pme 80000000 0 annnnnnn undi D 4 czs C24 C23 C22 D Top Side P BB1 connects to the Baseboard J GC1 PMC XMC Module Outline connects to a Graphics card Figure D 3 2P2 PMC XMC Carrier Board Component Connector Diagram Themis Computer D Board Diagrams 2P2 PMC XMC amp 2P3 PMC Carrier Boards 3 3V key 5V key P2601 00000000 Ed S000000 PMC Module 00000000 1 1 VME P1 1 PMC Carrier Board Riser Connectors und
3. 5 J1002 J1003 J1004 64 1 63 Figure A 17 PMC Card Slot Connector Pinout PMC Card slot connector signals are described in the following sections Slot Connector J1002 3 3V 32 bit The PMC slot signals 32 bit for connector J1002 are described in Table A 17 on page A 23 Slot Connector J1003 3 3V 32 bit The PMC slot signals 32 bit for connector J1003 are described in Table A 18 on page A 24 Slot Connector J1004 3 3V 64 bit The PMC slot signals 64 bit for connector J1004 are described in Table A 19 on page A 25 Themis Computer A Connector Pinouts and LED Indicators Table A 17 PMC Slot Connector J1002 Signals 32 bit CPU 1 Baseboard Pin Signal Pin Signal 1 No Connection 12V 3 Ground INTBZ 5 INTC INTD 7 BUSMODE1 5V 9 INTA 10 PCI RSVD 11 Ground 12 PCI RSVD 13 CLK 14 Ground 15 Ground 16 GNT 17 REQ 18 5V 19 V I O 20 AD 31 21 AD 28 22 AD 27 23 AD 25 24 Ground 25 Ground 26 3 27 AD 22 28 AD 21 29 AD 19 30 5V 31 V I O 32 AD 17 33 FRAME 34 Ground 35 Ground 36 IRDY 37 DEVSEL 38 5V 39 Ground 40 LOCK 41 SDONE 42 SBO 43 PAR 44 Ground 45 V I 0 46 AD 15 47 AD 12 48 AD 11 49 AD 09 50 5V 51 Ground 52 53 AD 06 54 AD 05 55 A
4. Figure A 16 CPU 1 P1 P2 VME Connector Pinouts VME64 P1 Connector e Connector Type 3 row x 32 pin 96 pin male VME64 e Manufacturer Part Harting 09031966921 The pinout and connector pin signals of the VME64 P1 connector for the CPU 1 Baseboard are shown in Table A 15 on page A 20 VME64 P2 Connector e Connector Type 3 row x 32 pin 96 pin male VME64 e Manufacturer Part Harting 09031966921 The pinout and connector pin signals of the VME64 P2 connector for the CPU 1 Baseboard are shown in Table A 16 on page A 21 Themis Computer TPPC64 Hardware Manual Table A 15 CPU 1 VME64 P1 Connector Pin Signals Pin Row A Signal Row B Signal Row C Signal 1 NC NC NC 2 NC NC NC 3 NC NC NC 4 NC VME_BGIN_L lt 0 gt NC 5 NC VME_BGOUT_L lt 0 gt NC 6 NC VME_BGIN_L lt 1 gt NC 7 NC VME BGOUT L 1 NC 8 NC VME BGIN 1 lt 2 gt NC 9 GND VME BGOUT L 2 GND 10 NC VME BGIN L 3 NC 11 GND VME BGOUT L 3 NC 12 NC NC NC 13 NC NC NC 14 NC NC NC 15 GND NC NC 16 NC NC NC 17 GND NC NC 18 NC NC NC 19 GND NC NC 20 NC GND NC 21 IACKIN L NC NC 22 VME IACKOUT L NC NC 23 NC GND NC 24 NC NC NC 25 NC NC NC 26 NC NC NC 27 NC NC NC 28 NC NC NC 29 NC NC NC 30 NC NC NC 31 12V NC 12V 32 VCC VCC VCC a
5. Bits Name Description Bese State cess 31 12 BS Base Address 0 R W Power up R 00 SPACE PCI Bus Address Space 0 Memory 1 Options a All other bits are Read 0 Table 4 4 Configuration Base Address 1 Register PCI BS1 Bits Name Description DU Ae State cess 31 12 BS Base Address 0 R W Power up R 00 SPACE PCI Bus Address Space 0 Memory 1 I O Options other bits are Read 0 4 8 Themis Computer 4 Universe Description Slave Image Programming 4 3 4 3 1 4 3 1 1 Slave Image Programming The Universe II recognizes two types of accesses on its bus interfaces accesses des tined for the other bus and accesses decoded for its own register space VME Slave Images A VMEbus slave image is used to access the resources of the PCI bus when the Uni verse II is not the VMEbus master The user may control the type of accesses by pro gramming specific attributes of the VMEbus slave image The Universe II will only accept accesses to the VMEbus from within the programmed limits of the VMEbus slave image Note The Bus Master Enable BM bit of the PCI CS register must be set in or der for the image to accept posted writes from an external VMEbus master If this bit is cleared while there is data in the VMEbus Slave Posted Write FIFO the data will be written to the PCI bus No further data is accepted into this FIFO unti
6. Ti Module 1 mE M 9 L E 2 Uc E L Module 0 2212 124 100 5 TPPC64 CPU 1 CPU 0 2P2 PMC XMC Carrier Board Figure C 7 CPU 0 CPU 1 Baseboards and 2P2 PMC XMC Carrier Board C 8 Themis Computer C Front Panel Connections and LEDs TPPC64 Front Panels C 2 6 TPPC64 2P3 2 CPU 0 CPU 1 amp 3 PMC Carrier Board ME PMC Module 3 USER ENBL SH DN PWR SYS STATUS ozv Z STATUS RST SLAN sys 9 oo OVER TEMP OVER TEMP CPU1 NT eS PMC Module 2 PWR OK uc n ORESET O See Figure C 1 for description of CPU 0 Front Panel e VLA Module 1 B f L A c 2 T A 1 100 1000 200 My CPU 1 CPU 0 2P3 Carrier Board Figure C 8 CPU 0 CPU 1 Baseboards and 3 PMC Carrier Board C 9 Themis Computer TPPC64 Hardware Manual C 3 LEDs Callouts describing TPPC64 front panel LEDs are shown in Figure C 9 below description and interpretation of front panel LEDs is given Table C 1 on page C 11 OVER TEMP OVER TEMP O 1 PWR OK RESET O O ST Lil lt SYS STATUS A lal A B C D 2 left to right 9 I yu TE SYS me t MSTR DIL OVER TEMP
7. 2 7 2 8 Estimated Power 2 8 Table 4 1 Universe II Miscellaneous Control Register MISC CTL 4 5 Table 4 2 Universe II Power Up Options eet tetto 4 7 Table 4 3 PCI Configuration Base Address 0 Register PCI 50 4 8 Table 4 4 PCI Configuration Base Address 1 Register PCI 51 4 8 Table 4 5 VMEbus Fields for VMEbus Slave Image eere 4 0 Table 4 6 PCI Bus Fields for VMEbus Slave Image eee 4 10 Table 4 7 Control Fields for VMEbus Slave 2 4 1 Table 4 8 PCI Bus Fields for PCI Bus Target 4 12 Table 4 9 PCI Bus Fields for PCI Bus Target Image eene 4 13 Table 4 10 Control Fields for PCI Bus Target 4 14 Table 4 11 Bus Fields for Special PCI Bus Target 4 14 Table 4 12 Control Fields for Special PCI Bus Target Image eese 4 15 Table 4 13 Special PCI Target Image Register Offset 188 2 2 2 2 4 15 Table A 1 Serial Ports and Connector Pin Signals eese A 2 Table A 2 USB Ports A and B Connector Pin Signals eese A 3 Table A 3 Gigabit Ethernet Connector Pin Signals and LED Inter
8. USER ENBL SH SYS STATUS ozv por STATUS Te Svs 9 s YY OVER TEMP 2 PMC Module 2 p RESET TI See Figure C 1 for description of Front Panel ozv Module 1 M lt Lern 5 5 8 8 el 110211111 2 3 Carrier Board Figure C 5 TPPC64 CPU 0 and 2 Carrier Board C 6 Themis Computer C Front Panel I O Connections and LEDs TPPC64 Front Panels C 2 4 TPPC64 1 2 CPU 0 amp CPU 1 Baseboards VME STATUS RST SLAVE sys 9 1 OVER TEMP OVER TEMP CPU1 M al See Figure C 1 for description of CPU 0 Front Panel C SERENA O gt Y n m do azr xzr ozv O O 5 e 5 8 8 a SO NA TPPC64 TPPC64 CPU O 1 Figure C 6 TPPC64 CPU 0 and CPU 1 Over temperature warning LED Power OK LED PMC Module 0 Themis Computer TPPC64 Hardware Manual 2 2 5 TPPC64 2P2 2 CPU 0 CPU 1 amp 2 PMC Carrier Board m PMC Module 2 lUSER ENBL SH 9 96 SYS STATUS ozv per ME STATUS Tg sys 97 MSTR OVER TEMP OVER TEMP CPU1 PWR OK RESET See Figure C 1 for description of CPU 0 Front Panel
9. eee eene 3 3 Figure 3 3 Custom Memory Module Topology Side View sese 3 7 Figure 4 1 Universe II Architectural Diagram esee 4 4 Figure 4 2 Address Translation for VMEbus to PCI Bus Transfers 4 11 Figure 4 3 Address Translation for PCI Bus to VMEbus Transfers 4 13 Figure 4 4 Memory Mapping in the Special PCI Target 2 1 4 16 Figure A 1 Dual Serial Ports A and B Connector 4 A 2 Figure A 2 Dual USB Ports A and B Connector 4 40 A 3 Figure 5 Ethernet Connector 4 Figure A 4 SCSI Connector PIBOUL A 5 Figure 5 CPU 0 Baseboard VME64 Connector Pinout 7 Figure 6 CPU 0 Baseboard VME64 P2 Connector Pinout 4 A 9 Figure 7 TPPC64 CPU 0 P2 Paddle Board I O Connections Top Side View A 12 Figure A 8 12V Power Connector Pinout ecu eee est qute Eo A 12 Figure A 9 Paddle Board Ultra320 SCSI Port B Connector Pinout 13 Figure 10 GPIO Connector Pinout A 13 Themis Computer xi TPPC64 Hardware Manual Figure A 11 12 Connector Pinout ey voe OTS A 15 Figure A 12 Dual Stereo Audio Connector esee A 15 Figure A 13 Ethernet 10 100Base T Connec
10. Stereo Audio In Stereo Audio Out 4 gt LJ thes see TTA 10 100Base T Ethernet RJ45 t 3311111 TIT M USBF USB5 USB E USB4 Copyright C 2095 INI I COMPUTER Grounding Block e 3 row VME only L USB D USB3 USB C USB2 THEMIS Ultra320 SCSI B A Front View Connector e 5 row LVD z e 3 row SE only Serial A A B Serial B GPIO Connector Front View Figure A 7 TPPC64 CPU 0 P2 Paddle Board Connections Top Side View 1 6 lt j F2 Connector 0000005 12V Power Connector Figure 8 12V Power Connector Pinout 12 Themis Computer A Connector Pinouts and LED Indicators CPU 0 Baseboard Table 8 12V Power Connector Pin Signals Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 12V 12V 12V Ground Ground Ground A 1 5 1 SCSI Symbol lt 1 5 2 Ultra320 SCSI Port B Connector e Connector Type High density 68 Pin Female Shielded Subminiature D e Manufacturer Part AMP 749069 7 The 68 pin female Ultra320 SCSI Port B is single ended SE for 3 row P2 con nectors and low voltage differential LVD for 5 row P2 connectors Figure A 9 shows the connector pinout Table A 10 page A 14 describes connector pin signals 34 1 2 5 Paddle Board Component Side 68 35 Figure A 9 Paddle Board
11. Themis Computer A Connector Pinouts and LED Indicators CPU 0 Baseboard A 1 2 CPU 0 VME Backplane Connectors The CPU 0 Baseboard is connected to the J1 J2 VMEO4 bus backplane through 3 row 5 row P2 VMEO4 connectors These are described in the following sec tions A 1 2 1 VME64 P1 Connector e Connector 3 row x 32 pin 96 pin male VME64 e Manufacturer Part Harting 09031966921 A pinout of the VME64 connector is shown in Figure 5 connector pin signals are described in Table A 5 on page A 8 Bottom Edge of Board Row C B EA 32 P1 1 P1701 Figure A 5 CPU 0 Baseboard VME64 P1 Connector Pinout Note In Table A 5 NC means No Connection e LL indicates an active Low A 7 Themis Computer TPPC64 Hardware Manual A 8 Table A 5 CPU 0 Baseboard VME64 P1 Connector Pin Signals Pin Row A Signal Row B Signal Row C Signal 1 VME D00 VME BBSY L VME D08 2 VME_ lt D01 gt VME_BCLR_L VME lt 09 gt 3 VME_ lt D02 gt VME_ACFAIL_L VME_ lt D10 gt 4 VME D03 BGIN 1 lt 0 gt VME_ lt D11 gt
12. VMEbus Ed posted writes with FIFO 4 r 4 ave coupled read logic q Interrupt Channel PoI Interrupt Handler Interrupts 4 gt gt Interrupts 4 M Bi Directional FIFO Figure 4 1 Universe Architectural Diagram The Universe 5 VMEbus Master Interface supports all of the addressing and data transfer modes as specified by the VMEO4 specification The Universe II does not support the A64 mode and modes intended to augment the 3U applications i e A40 and MD32 The Universe II is compatible with all the VMEbus modules that con form to pre VMEO64 specification The Universe II as the VMEbus Master supports RMW and ADOH The Universe II accepts BERR active low and DTACK as cycle terminations from the VMEbus The Universe II does not accept the RETRY as a termination from VMEbus Slave DTACK indicates the successful comple tion of a transaction The Universe II utilizes the ADOH cycle to implement the VMEbus Lock command allowing a PCI bus master to lock the VMEbus resources Themis Computer 4 Universe Description VMEbus Interface 4 2 4 VMEbus First Slot Detector As defined by the VME64 specification the Universe II samples the BG3IN right after the reset to determine if the TPPC64 resides in slot 1 If the BG3IN is sampled low right after the reset the TPPC64 becomes the SYSCON Otherwi
13. 1 2 2 VME64 P2 Connector e Connector 5 row x 32 pin 160 pin male VME64 e Manufacturer Part Harting 02 01 160 2101 A pinout of the VME64 P2 connector is shown in Figure A 6 connector pin signals are described in Table A 6 on page A 10 Bottom Edge of Board Row 2 Figure A 6 CPU 0 Baseboard VME64 P2 Connector Pinout Note In Table A 6 NC means No Connection e L indicates an active Low and indicate one member of a signal pair A thick border is used to group signals that are associated Themis Computer TPPC64 Hardware Manual Table A 6 CPU 0 Baseboard VME64 P2 Connector Pin Signals e GND 95 5 P F Row 2 Signal Row A Signal Row B Signal Row C Signal Row D Signal 1 TP1 RXD P 12V AUX 5 5V 2 VME DATA 2 GND GND GND 2 VME INT L 2 VME CLK 3 TP1 RXD N 12V AUX NC SCSI B TERMPWR SCSI B DIFFSENS 4 GND GND VME A 24 SCSI B ATN SCSI B ATN 5 1 TXD P 12V AUX VME A 25 SCSI B BSY S
14. 2 1 CPU 0 and CPU 1 Baseboards The TPPC64 0 and 1 Baseboards were designed to provide IBM 970FX PowerPC platform in an industry standard GRU VME64 bus form factor Both CPU 0 and CPU 1 are available at processor speeds up to 1 8 GHz 512 KB L2 cache see Figure 2 1 page 2 2 The Memory subsystem utilizes a custom high capacity Themis Memory Module that supports several memory configurations up to 4 GigaBytes see Table 2 1 Table 2 1 Memory Configurations SERLO Capacity Supported 1GB YES 2GB YES 4GB YES Special Order Themis Computer 2 1 TPPC64 Hardware Manual CPU 1 Baseboard 1 IBM 970FX PowerPC IC Bus A Elastic I F 450 MHz 36 bit c Bus C PCI X Bridge PCI Extension Legend e Front Panel Connector VME P2 Paddle Board 2 2 Elastic 450 MHz 36 bit CPU 0 IBM 970FX PowerPC System 209400 Bridge 3 2 GB sec EE 2 2 C Bus B HyperTransport 400 MHz 16 bit CPU 0 Baseboard C Bus A 2 Micro Controller Memory Module 1 GB 2 GB or 4 GB C Bus A Dual 66 133 MHz 64 bit o 1 I PCI X Bus A HyperTransport PCI X Bus B 10 100 1000 Gigabit Tunne
15. B 1 B22 CPU 1 Baseboard Juniper Pls sedo at t ae B 4 2 3 PMC XMC Carrier Board Jumper Pins eene B 5 B 3 Factory Configurable Solder Beads soot e miei eie hte dad B 7 B 3 1 CPU 0 Baseboard Solder Beads hc trat aod B 7 5 2 CPU 1 Baseboard Solder Beads eniti cat eiae ado efe B 10 3 3 PMC XMC Carrier Board Solder Beads 2 0 B 10 Appendix C Front Panel I O Connections and LEDS C 1 Introdueti tk 1 CL T Front Panel Dimensions wos oce rei pe io tore dnd C 1 Injector Ejector Handles C 1 1 211 VMBOZ4 type Handles C 2 CAD TriplesE type Handles a C 2 C2 Front C 3 2 1 TPPC64 1 1 CPU 0 Baseboard Only eere C 4 2 2 TPPC64 2P2 1 CPU 0 amp 2 PMC Carrier Board C 5 C 2 3 TPPC64 2P3 1 CPU 0 amp 3 PMC Carrier Board C 6 2 4 TPPC64 1 2 CPU 0 amp CPU 1 Baseboards C 7 2 5 64 2 2 2 0 1 amp 2 PMC Carrier Board C 8 C 2 6 TPPC64 2P3 2 CPU 0 1 amp 3 PMC Carrier Board C 9
16. 8 Bee g INR 28 87 Be S009 38 88 e o B eo g S o n np gre 00010601 g aoeceoeg D o o N gt 3 252 o sud JL o B 80 0 39s he 2992 3 81093 020225 B cumin um 4557028 555 555 392005908 39 2 8 Bron 2 9 hor ho 9 2 5 une iu A suo MPSA FOS OOLICE wg Ele Sg 8 yy amp i Be mm Zo v ELoSSLICISCILIS 5 1 5 UN MUN 1 2 RE nn ge m Be id ors uu B cub lt OD 2 E 5 25 ARD or SYN 5 gt 533 UE y 9 9799 55 555 12 8 S L engl S esse D e 252892 88 2 m 152500 SUIT 3333 TRE 98851059 222520265 WES Bottom Side Figure B 3 TPPC64 0 Baseboard Solder Bead Locations Bottom Side B 9 Themis Computer TPPC64 Hardware Manual B 3 2 CPU 1 Baseboard Solder Beads The solder beads on the TPPC64 CPU 1 Baseboard are located on both sides of the PCB six on the top and two on the bottom and are used for manufacturing purposes only Solder bead default settings are given in Table B 7 Table B 7 CPU 1 Baseboard Solder Bead Settings Top and Bottom Sides Setting Description Short 5 06 S
17. Themis Computer Index I2C Connector Pinout A 5 I2C Connector Pin Signals A 5 I2C Header Connector A 5 installation 1 3 SCSI Port B Connector Pinouts A 4 Serial Connector Pinout A 7 Serial A B Connector Pin Signals A 7 Serial Ports Connectors 17 Stereo Audio In Out Connectors A 5 USB Port Dual A 6 USB Ports C D E F A 18 USB Ports C D E F Connector Pinouts A 6 USB Ports C D E F Signals A 6 PC 133 timing 3 7 PCI Bus Fields Special PCI Bus Target Image 4 4 PCI Bus Fields for PCI Bus Target Image 4 3 PCI Bus Target Channel 4 3 PCI Bus Target Images 4 12 Control Fields 4 13 PCI Bus Fields 4 2 Special PCI Target Image 4 4 VMEbus Fields 4 12 PCI Configuration Base Address 0 Register PCI BSO 4 6 PCI Configuration Base Address 1 Register PCI BS1 4 8 PIBS 1 13 Placement of Mating Pins VME64 type Handles 3 PMC Card Slot Connectors CPU 1 A 22 PMC Carrier Board 2 4 D 1 PMC Carrier Board Solder Beads 10 PMC Module slot 1 A 27 PMC Module slot 2 A 27 PMC Module slot 3 A 27 PMC Slot Connector J1002 3 3V 32 bit A 22 PMC Slot Connector J1002 Signals 32 bit A 23 PMC Slot Connector J1003 3 3V 32 bit A 22 PMC Slot Connector J1003 Signals 32 bit A 24 PMC Slot Connector J1004 3 3V 64 bit A 22 PMC Slot Connector J1004 Signals 64 bit A 25 PMC XMC Carrier Board A 27 PMC XMC Carrier Board Manual Themis P N 112826 020 2 4 PMC XMC Module slot 1 A 27 PM
18. V Vdd core 8 VME Backplane Connectors CPU 0 A 7 1 19 VME Pin Signals System board 8 VME Pinout System board A 7 VME J2 P2 Pin Signals System board 0 VME J2 P2 Pinout System board A 9 VME Slave Images 4 9 Control Fields 4 11 PCI Bus Fields 4 0 VMEbus Fields 4 9 VME Status LEDs 11 VME system controller See SYSCON VME64 P1 Connector A 7 A 19 P2 Connector A 9 19 VME64 specification 4 6 VMEbus 32 bit 3 4 64 bit 3 4 Address Translation 4 11 Configuration 4 2 Fields for VMEbus Slave Image 4 9 First Slot Detector 4 5 Interface 4 2 interface configuration 3 Slave 4 2 Slave Image PCI Bus Fields 4 10 System Controller 3 4 VMEbus arbitrator 4 6 VMEbus Master 4 9 Warranty xxi Themis Computer Index 5 TPPC64 Hardware Manual Index 6 Themis Computer Place Stamp Here Themis Computer 47200 Bayside Parkway Fremont CA 94538 Attn Publications Department Fold here tape at top to seal d SIW3HL Reader Comment Card We welcome your comments and suggestions to help improve the 64 User Manual Please take time to let us know what you think about this manual Information provided in the manual was complete Agree 7 Disagree Not Applicable Information was well documented and easy to follow Agree Disagree Not Applicable Information was easily accessible Agree 2 Disagree Not Applicable 7 The manu
19. 1 4 Install the TPPC64 CPU 1 Power Board eese 1 6 1 5 v Terminate SC 5 DEVICES uae oe babet d eet Ca Ma En a a 1 7 16 Attach Peripheral Cables 1 9 1 6 1 Serial Port A and Port B and 1 10 1 6 1 1 Front Panel Connection 1 10 COBBSCUOD 1 10 1 6 2 Ethernet o Seed etian do 1 10 1 6 2 1 10 100 1000Base T Gigabit 1 10 1 6 2 2 JO TIOOBASO T s 1 11 1 6 3 UTtza320 SCSI Port A and Port 1 11 1 6 4 76 O0 and D 1 11 1 6 5 USB C 2 USB D 3 USB E 4 and USB F 5 1 11 1 6 6 Stereo Audio In Out eid 1 11 1 6 7 GPIO Header Connector 1 12 1 6 8 C Header Connectot ino aoe esse teet eue 1 12 1 6 9 12 volt Auxiliary Power Connector eene 1 12 ET VME Interface ioo ce e eae ea ees 1 13 1 8 TOD NVRAM Battery Replacement 1 14 2 System Overview and Specifications 2 1 2 1 CPU 0 CPU T BaseDOBEdS 2 2L PW PU Duality 2 3 2 2 PMCIXMC Garter Boards Side e NEM s 2 4 2 5 Graphics Board
20. no m Top Side Figure B 2 TPPC64 CPU 1 Baseboard Jumper Pin Locations Top Side B 6 Themis Computer B Jumper Pin and Solder Bead Configurations B 3 B 3 1 Factory Configurable Solder Beads Factory Configurable Solder Beads CPU 0 Baseboard Solder Beads Solder beads are found only on the bottom side solder side of the TPPC64 CPU 0 Baseboard and are described in Table B 6 In Table B 6 if no pad number is given only 2 solder pads exist If there are 3 solder pads the two pads listed are shorted together Short means a solder bead is installed creating an electrical path between two contacts Open means no solder bead is installed hence the path between the contacts is open Figure B 1 on page B 3 provides the location of the CPU 0 Baseboard solder beads Remember that pad 1 is indicated on the board by a thick bar line Caution When dealing with 3 pad solder bead switch a solder bead will short only one set of pads either 1 2 or 2 3 If a solder bead shorts more than 2 pads call Themis Customer Support Table B 6 CPU 0 Baseboard Solder Bead Settings Bottom Side Setting Description Short 1 2 The AMD8111 RTC Vdd is connected to the onboard battery n Short 2 3 The AMD8111 RTC Vdd is connected to 3 3 volt power
21. 2 4 Themis Computer TPPC64 Hardware Manual vi 24 Paddle and Power Phe bleed 2 4 2 5 Backplane Jumper Settings De aae ks 2 4 2 07 oodd ctc 2 5 2 6 1 Processor amp Memory Subsystems oda IP per tee 2 5 20 2 Auxiliary PRDetOls qute t osa Ue ua vh 2 6 2 7 Environmental Specification i eU 2 7 2 8 Estimated Power Requirements Miss a Pe UAE 2 8 Hardware OYerview ooi tet nce Pe a Nd de epu MR DUI UE 3 1 oh CPU and CPU T Baseboatels Lene ASA OUI TRAGE 3 1 3 1 1 IBM 970FX Processor and Cache 3 1 3 1 2 System I O Bridge and Memory Controller 3 2 3 1 3 HyperTransport Technology 3 2 3 1 3 1 AMD 8131 HyperTransport PCI X Tunnel 3 2 3 1 3 2 AMD 8111 HyperTransport I O Hub eese 3 3 3 1 4 Universe II PCI to VME Bridge 3 4 3 1 5 Dual Ultra320 SCSI Controller rte reist nt ena 3 5 31 6 CPC Super TO Controllet totos e d ese 3 6 3 1 7 Dual Gigabit Ethernet Controller 3 6 3 Memory Subsystem eiie db Goi ee M E 3 7 Universe I Description o L on PK RO 4 1 dT nBesatutes oo eat dn EE MM 4 1
22. 4 2 MMB DUS terface e ado eT eS RUP Urt dati nd 4 2 Z2 01 NNIBbUS CODI PUPA ss rois elses aon 4 2 42 2 Universe II as VMEbus Slave 4 2 4 2 3 Universe II as the VMEbus Master 2 4 44 2 01402 1 0 0 1 4 4044 0 410 4 3 424 VMEbus First Slot Detector 4 5 4 2 4 1 Automatic Slot Identification eene 4 6 4 2 4 2 Register Access at Power Up 4 6 4 2 5 Universe Il s Hardware Power Up Options seen 4 7 2 57 Slave Image Programinio dio ee eiue 4 9 4 3 D VME Slave ei E 4 9 43 14 VMEBb s Fields uiti tto 4 0 23 155 POIL Bus Fields MR n tede 4 10 Themis Computer Table of Contents Control Fields diete itid evi eine 4 11 432 PCL Bus Target Images e evel eer t E nhu Dai ide sci eiut d eia 4 12 PCI Bus e tt 4 12 4520 V MBbB s Fields eere 4 12 32 9 Control Fieldsi 5 tudo 4 13 4 3 2 4 4 14 4 4 Universe II s Interrupt and Interrupt Handler 2 4 17 4 4 1 VME and PCI Interr pters soe e RR Een pr UD ER etat 4 17 4 4 2 VMEbus Interrupt Handling eene 4 17 4 4 3 Universe I
23. Actual location 27 8 E of solder beads 5 33 Bueno SB9 mA 8888 i sb Description E Hn 355 jum g a3 gt of solder beads p ren HBBBBER D o May be set open DS B 1 Birao or short as per 50 m 0222 g g 8 egi SB2 amp m 99 B E manufacturing VME P1 00 is Computer 2005 PPC64 CPUO board rev A mmm E Bg um 28 Z9 e018 tela B 55 B8 s ES o8 8 8 OH 9919 cog B E sg ee D usu oSls Tee h QU ORE
24. BE 8 18313 mE xm 53 88 20 7 0 OO n gi 1218089190 amp Ets 25 325006 62225 5 9719382183 abu 222225598 B EI ag gog 5 16 ENS B B E325 Sp 2 e pup i 22 zt 9 9552 oes 2 588 09 8 B vod s 9192 41552096 Bs deo 4m g 256022 mi E n 2521553 O eso a dnun ud A ineo 40 E En SB11 fe SIRO eH sl m n ag 33 559552 D of ot 50 wo BA E 55 532533 O FAS eS cot LT CBE Sud 2 Bur 8 Oo 8 JEDE C pA oz 3 menn is s lt SB6 o m N 2 a ue 2B vm coon 2 22 lt o 0 9 2892 213258295 oA 34 99 Il E o B S 5 gp 2022 B Zgos gs0 222 progo il o 8 25 2 2050 TON gt jm 00000 200 ss a o 4 Goll ES Edd VOS 5 ae gt 8 o ree ot SP Sin 1 55 S 8655 gne 61 8 5 HER Di BS WET 1 8 5 25 5 ot Soa 8 899 gun 29185 2 8 8 2 42 2 20 ee semi 2 Bim amp 5 B 8 Be ot 7 S H 16952155 6192 19 100 as Do 2 e Th S Ell Y E s o SA pue 2 sn 5 6100 n 2 ARSE gi wea 2605 Bret C VME P2 9 0 BOAR BES ee E god stad 82935 0090008 Hn n Bi REEERE 17 98 amp 38 E 58 825 83
25. Front Panel Dimensions C G Gigabit Ethernet Ports 1 2 4 Gigabit Ethernet Connector Pin Signals and LEDs A 4 Gigabit Ethernet Port B A 27 Glossary 1 GPIO Connector Pinout A 3 GPIO Connector Pin Signals A 3 GPIO header 1 12 GPIO Header Connector A 3 H Harting 02 01 160 2101 A 9 Harting 09031966921 7 A 19 Headphones out AC97 format A 27 Honda HDRA E68LFDT SLA A 5 HyperTransport technology 3 2 I I2C Connector Pinout A 5 I2C Connector Pin Signals A 5 I2C header 1 12 I2C Header Connector A 5 I2C signals A 27 IACK Daisy Chain Driver DCD 4 6 IACKIN 2 4 IACKOUT 2 4 970FX Processor 3 1 In Case Of Difficulties xxi Index 2 Injection Ejector Handles C Intel FW82546 Ethernet controller 3 6 Intended Audience xvii ITT Cannon MDSM 18PE Z10 A 17 J Jumper pins B L LED Interpretation 11 LED status indicators A LEDs C 0 LEDs Front Panel interpretation 1 lithium battery 1 14 local 32 bit PCI bus 3 4 LPC Super I O Controller 3 6 M Mating Pins C 3 Memory Mapping Special PCI Target Image 4 16 Memory Module 2 Memory Module Connector A 29 Memory Subsystem 3 7 MISC_CTL register 4 5 N Non Volatile RAM 1 14 7 14 O OUT 2 4 P Paddle Board 2 4 10 100Base T Connector Pinout A 6 10 100Base T Connector Pin Signals 16 Connectors A 2 Ethernet 10 100Base T Connector A 6 GPIO Header Connector A 3
26. Memory Specifications Feature Function Specifications Custom Memory Modules for 1 GB gigabyte Main Memory 2 GB and 4 GB Memory Bus Interface 128 bit Data Path from CPU 3 2 GB sec 2 Channel ECC Custom Memory Module only Memory Modules see Table 2 1 page 2 1 Total Memory Configurations 1 GB 2 GB and 4 GB 2 5 Themis Computer TPPC64 Hardware Manual 2 6 2 Auxiliary Functions Table 2 4 summarizes the functional specifications of the auxiliary functions These specifications apply to all product configurations Table 2 4 Auxiliary Functions Specifications Feature Function Specifications Flash Memory 8 MB boot flash NVRAM TOD 8 KB battery backed UPI Static RAM plus timekeeper System Status LEDs Four LEDs located on Front Panel of the CPU 0 Baseboard See Appendix C Front Panel I O Connections and LEDs VME Status LEDs Four LEDs located on Front Panel of the CPU 0 Baseboard See Appendix C Front Panel I O Connections and LEDs Reset Switch Momentary Push button Generates POR Located on Front Panel Watchdog Timers 2 Level Watchdog Level One Interrupt Level Two XIR Voltage Sensors Monitors 12V 5V 3 3V 1 8V 1 5V 1 2V 1 15V CPU Core POR reset signal is generated when voltage drops below a specified threshold POR voltage Monitors whether the CPU temperature stays within a spec ified range Range can be changed by softw
27. Note The 2P2 PMC XMC Carrier Board has been designed to support a variety of CPU baseboards offered by Themis Computer Some of these baseboards have PCI Express ports that support the XMC capability of the 2P2 PMC XMC Carrier Board The TPPC64 however does not have PCI Express When mated with a TPPC64 the 2P2 PMC XMC Carrier Board will function as a PMC only carrier since the XMC capability is not supported Note that Figure A 20 page A 28 shows both PMC and XMC Module connectors 2P3 PMC Carrier Board I O components on the TPPC64 2P3 PMC Carrier Board include PMC Module slot 1 slot 2 and slot 3 There are no I O connectors installed directly on the front panel of the 2P3 PMC Carrier Board Any of the three PMC Modules installed into slots 1 2 or 3 may con tain I O connectors however Themis Computer TPPC64 Hardware Manual Note Consult the manual shipped with each PMC XMC Module installed on the Carrier Board for a description of I O functionality and connectivity 2P2 PMC XMC Carrier Board To XMC Module XMC Connector J15 e PCI Express x4 XMC Connector J16 PMC XMC Module Slot 2 e User I O To PMC Module Jn1 Connector J11 32 bit pins Jn2 Connector J12 32 bit pins Jn3 Connector J13 64 bit pins Jn4 Connector J14 e User I O PMC XMC Module Slot 1 Top View 3 3 volt Key 5 volt Key To Baseboard TPPC64 114 pin Plug Connector Mictor e PCI Not installed for T
28. Short Serial Ports A and B are connected to the Front Panel not connected to VME P2 Serial Ports and B are connected to P2 connected the Front Panel Short The system clock is 112 34 MHz SB03 Open The system clock is 224 68 MHz Short 1 2 Audio Codec 97 AC97 signals are connected to the PCI extension connector did Short 2 3 Audio Codec 97 AC97 signals are connected to the VME P2 connector Note Footnotes are described at the end of Table B 6 on page B 8 Themis Computer TPPC64 Hardware Manual Table B 6 CPU 0 Baseboard Solder Bead Settings Bottom Side Continued aati Setting Description Short The SCSI termination devices mounted on the TPPC64 CPU 0 Baseboard are from Unitrode 5805 Open The SCSI termination devices installed on the TPPC64 CPU 0 Baseboard are from Dallas Short Manufacturing use only 5 06 Normal operation The RESET pad of the PPC970FX CPU is set for pull up Short Internal clock termination of the PPC970FX CPU is enabled TUE Open Internal clock termination of the PPC970FX CPU is disabled external termination Short Serial Port B is connected to the LPC I O chip Open Serial Port B is connected to the Service Processor s serial port Short The JTAG scan test of the system is not performed i Open Perform the JTAG scan test of the system Short Enable the elasti
29. Table A 2 USB Ports A and B Connector Pin Signals Pin USB Signal Description A1 USBO PWR Port A Power A2 USBO D N Port A Data Negative A3 USBO D P Port A Data Positive A4 USBO GND Port A Ground B1 USB1 PWR Port B Power B2 USB1 D N Port B Data Negative B3 USB1 D P Port B Data Positive B4 USB1 GND Port B Ground A 3 Themis Computer TPPC64 Hardware Manual A 1 1 3 Gigabit Ethernet TPE Port A1 and Port A2 e Connector Dual RJA5 Connector 8 Pin per RJ45 16 pin total e Manufacturer Part Transpower Tyco 1610005 4 Ethernet TPE Port A1 and Port A2 on the front faceplate are each supported by an RJ45 connector with two embedded LEDs see Figure A 3 that supports 10 100 1000Base T transmission rates and is installed directly on the CPU 0 Baseboard Connector pin signals as well as LED interpretation are described in Table A 3 Symbol TP e CPU 0 Board Speed LED Gigabit Ethernet Ports A1 A2 Activity LED Figure A 3 Ethernet Connector Pinout Table A 3 Gigabit Ethernet Connector Pin Signals and LED Interpretation Pin Signal Description LED LED On Off State Interpretation 1 TRDO Transmit Receive 00 Yellow ON Steady 10 Mb s 2 TRDO Transmit Receive DO 090 OFF 100 Mb s 3 TRD1 Transmit Receive D1 Speed OFF 1000 Mb s 4 TRD2 Transmit Receive D2 Gr
30. 5 5 Ethernet 10 100Base T Connector 5 row P2 only A 16 1 5 6 Serial Port A RS232 and Port B RS232 A 17 A3 USB Porte C D and defe hes A 18 AO CPU 1 Baseboard CREE NH Pa tuse ene YS e ERE CH RENE AS d A 19 A 2 1 1 Front Panel Connectors 35 s A 19 A 2 2 1 Backplane Connectors 19 vii Themis Computer TPPC64 Hardware Manual AZ 2 1 PI Conector 19 A2 22 19 A 2 3 CPU 1 PMC Card Slot Connectors acide arant bn oed ena in dd A 22 A24 CPU LP2 Bowet Board 26 PMCIXMC Carrier Boards Ee rd 27 AG 2P2PMC XMC Cartier BOabd 27 AS JP3PMC Camer Board 27 Ad Memory Module 29 Appendix B Jumper Pin and Solder Bead Configurations B 1 BL B 1 B 2 Field Configurable Jumper Pins B 1 B 2 1 CPU 0 Baseboard Jumper euet eae
31. Flashing rateis 800 ms foreach transmis Sion or receive activity Ethernet N 100 Mbps 1000 Mbps Green e Ethernet A1 connection speed EE 100 1000 Speed Green e Ethernet A2 connection speed a ON or OFF means the LED is ON or OFF for 300 ms b CPU 0 and CPU 1 board temperatures including junction temperatures are polled every 15 seconds There is a counter that is incremented whenever the CPU 0 or CPU 1 junction temperature exceeds the preset OVER TEMP threshold If the 0 or CPU 1 junction temperature exceeds the preset threshold three consecutive polling times then the red OVER TEMP LED is turned on indicating the OVER TEMP status C 11 Themis Computer TPPC64 Hardware Manual C 12 Themis Computer D 1 D 2 Appendix Board Diagrams The following sections of this appendix contain diagrams of the various boards of the TPPC64 It is intended as a quick reference to component and connector identifi cation TPPC64 boards included are CPU 0 and CPU 1 Baseboards 2 2 PMC XMC Carrier Board 2P3 PMC Carrier Board See Appendix B Jumper Pin and Solder Bead Configurations for a description of jumper pin and solder bead configurations CPU 0 and CPU 1 Baseboards Figure D 1 page D 2 and Figure D 2 page D 3 identify major board components and connectors as seen from the component side of the CPU 0 and CPU 1 Baseboards respectively 2P2 PMC XMC amp
32. HyperTransport PCI X Tunnel Themis Computer 3 Hardware Overview 0 and CPU 1 Baseboards Major features of the AMD 8131 include the following 16 bit HyperTransport interface Side A 8 bit HyperTransport interface Side B Two PCI X bridges Bridge A Bridge B that support the following features PCI X modes and legacy PCI revision 2 2 modes 133 MHz 100 MHz 66 MHz and 33 MHz transfer rates in PCI X mode 66 MHz and 33 MHz PCI 2 2 modes Independent transfer rates and operational modes for each bridge Support for up to five PCI masters on each bridge IOAPIC APIC with four redirection registers for each bridge including a legacy interrupt controller and IOAPIC mode support SHPC compliant controller and support 829 OBGA package 3 1 3 2 AMD 8111 HyperTransport I O Hub The AMD 8111 HyperTransport Hub is a direct replacement for the traditional Southbridge chip integrating the functions of storage connectivity audio I O expansion security and system management into a single device see Figure 3 2 USB Z AMD 8111 HyperTransport Toward Host lt HyperTransport Link VO Hub IDE Unused 3 0 C 10 100 Ethernet SM Bus 0 GPIO 32 pins L 9 SM Bus 1 33 MHz 32 Bit 0 8 PCIBusC Y lt LPCBus N Figure 3 2 AMD 8111 HyperTransport Hub 3 3
33. L 27 SEL H 61 SEL L 28 CD H 62 CD L 29 REQ H 63 REQ_L 30 64 lO L 31 DAT H8 65 DAT L8 32 DAT H9 66 DAT L9 33 DAT 10 67 DAT L10 34 DAT H11 68 DAT L11 indicates an active high signal and L indicates an active low signal A 14 Themis Computer A Connector Pinouts and LED Indicators CPU 0 Baseboard 1 5 3 Header Connector 5 row P2 only e Connector Type In line 6 pin Header Male e Manufacturer Part Number Molex 22 11 2062 A pinout of the male 1x6 header connector is shown in F igure with con nector pin signals described in Table A 11 J10 VME P2 Connector Paddle Board Component Side Figure 2 Connector Pinout Table A 11 12 Connector Pin Signals Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Ground VME DATA Ground VME CLK Ground VME INT L A 1 5 4 Stereo Audio In Out Connectors 5 row P2 only e Connector Type Dual Stereo mini Jack 3 5 mm e Manufacturer Part Connect Tech CTP 354W S1 The dual stereo L R audio connectors on the front edge of the P2 Paddle Board are shown in Figure A 12 Stereo Stereo n Jack Out Jack Front View Paddle Board Edge Figure A 12 Dual Stereo Audio Connector A 15 Themis Computer TPPC64 Hardware Manual A 1 5 5 Ethernet 10 100Base T Connector 5 row P2 only e Connector Type RJ45 e Manufacturer Part Pulse JO011DO1B The TPPC64 P2 Paddle
34. Panel I O Connections and LEDs Pin signal descriptions are in Table A 2 on page 3 Appendix A USB C 2 USB D 3 USB E 4 and USB F 5 Signals version 1 1 for USB Ports C USB2 D USB3 E USB4 and USB5 are accessible only through the P2 connector of the TPPC64 VME backplane see Table A 6 page A 10 in Appendix A Connector Pinouts and LED Indicators As indicated in Table 1 2 page 1 9 although USB Ports C D E and F are all acces sible through a 5 row CPU 0 Paddle Board since the signals for USB Port F reside within row Z only USB Ports C D and E can be accessed through a 3 row CPU 0 Paddle Board Stereo Audio In Out Jacks Stereo Audio In and Out are accessed separately through standard mini plugs attached to each of the stereo 3 5 mm mini jacks on the CPU 0 Paddle Board Themis Computer TPPC64 Hardware Manual GPIO Header Connector The 6 pin GPIO general purpose input output header used for test purposes is on the top of the CPU 0 Paddle Board PCB and provides four GPIO signal pins an alarm pin and a ground pin see Table A 9 page A 13 Only two GPIO signals are accessible through a 3 row CPU 0 Paddle Board two more are accessible through a 5 row CPU 0 Paddle Board for a total of four 2 Header Connector The 6 pin I2C header used for test purposes is on the top of the CPU 0 Paddle Board PCB and provides separate data clock and interrupt pins along with three sepa
35. Speed JP7 JP8 PCI Clock Speed OFF OFF 33 MHz ON OFF 66 MHz OFF ON 100 MHz ON ON 133 MHz 2 3 PMC XMC Carrier Board Jumper Pins There are no jumper pins on either the 2P2 PMC XMC Carrier Board or the 2P3 PMC Carrier Board Instead the 2P2 PMC XMC Carrier Board has jumper pads that are either unshorted open or shorted by a resistor soldered directly to the pads see the PMC XMC Carrier Board Manual P N 112826 020 for details B 5 Themis Computer TPPC64 Hardware Manual sored seoru 4 527 j 908119 VME P1 O000000000000000000 E 09 gt Hi 5 o 2 8 BD T 8 z B m 9294318 4316 1 gt gt lt aw zoo an zr cca o Sc s VME P2 22992 S o a
36. TPPC64 Hardware Manual 1 If you are installing a SCSI device on SCSI A or SCSI B you must install a terminator on the last device in the SCSI bus chain If you do not terminate the last device on the SCSI bus SCSI devices attached to that bus may not operate properly see following Caution vices to operate correctly Only the last device including the SCSI Controller at each end of a SCSI bus chain should be terminated Since both SCSI A and SCSI B buses end at the TPPC64 SCSI controller see Figure 1 6 page 1 7 an on board terminator is automatically enabled turned On for each bus This means that the user may install up to 15 SCSI devices on either bus A or B install a terminator on the end of the SCSI bus and be assured that both ends of the SCSI bus are properly terminated Caution SCSI busses must be properly terminated in order for attached SCSI de Note Address all questions concerning available Paddle Boards for the TPPC64 to Themis Computer Customer Service 1 8 Themis Computer 1 Installation and Operation Attach Peripheral Cables 1 6 Attach Peripheral Cables 1 Attach peripheral cables to Front Panel and VME P2 Paddle Power Board connectors as needed A list of peripheral devices and voltage sources that can be connected to a TPPC64 system CPU 0 Paddle Board and Power Board 1 has no Front Panel connectors appears in Table 1 2 The fol lowing sections provide in
37. Ultra320 SCSI Port B Connector Pinout GPIO Header Connector e Connector Type In line 6 pin Header Male e Manufacturer Part Number Molex 22 11 2062 The GPIO header is a straight 1x6 male connector with the pinout shown in Figure A 10 and the connector pin signals described in Table A 9 J11 VME P2 Connector P Paddle Board Component Side Figure A 10 GPIO Connector Pinout Table A 9 GPIO Connector Pin Signals Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Ground GPIOO GPIO1 GPIO22 GPIO3 WD ALARM L a Signal is accessible through a 5 row P2 connector only A 13 Themis Computer TPPC64 Hardware Manual Table A 10 Paddle Board Ultra320 SCSI Port B Connector Pin Signals Pin Signal Name Pin Signal Name 1 DAT H12 High 35 DAT L12 L Low 2 DAT H13 36 DAT L13 3 DAT H14 37 DAT L14 4 DAT H15 38 DAT L15 5 PAR H1 39 PAR L1 6 DAT 40 DAT LO 7 DAT H1 41 DAT L1 8 DAT H2 42 DAT L2 9 DAT H3 43 DAT L3 10 DAT H4 44 DAT L4 11 DAT H5 45 DAT L5 12 DAT H6 46 DAT L6 13 DAT H7 47 DAT L7 14 PAR HO 48 PAR LO 15 GND 49 GND 16 DIFFSENSE 50 No Connection 17 TERMPWR 51 TERMPWR 18 TERMPWR 52 TERMPWR 19 No Connection 53 No Connection 20 SENSE P2 L 54 GND 21 ATN H 55 ATN L 22 GND 56 GND 23 BUSY H 57 BUSY L 24 ACK H 58 ACK L 25 RST H 59 L 26 MSG H 60 MSG
38. Universe Il s Interrupt and Interrupt Handler 4 4 4 4 1 4 4 2 4 4 3 4 4 4 Universe Il s Interrupt and Interrupt Handler VME and PCI Interrupters For the VMEbus the interrupt source can be mapped to any of the VMEbus interrupt output pins such as VIRQ 7 0 If a hardware and software source are assigned to the same VMEbus VIRQ n pin the software source always has higher priority Interrupt sources mapped to the PCI bus interrupts are generated via the PCI Inter rupt pin INT 0 For the VMEbus interrupt outputs the Universe II interrupter provides an 8 bit STATUS ID to a VMEbus interrupt handler Optionally the Universe II generates an internal interrupt to signal that the interrupt vector has been provided Interrupts mapped to the PCI bus interrupt output pin INT 0 are serviced by the PCI Interrupt Controller The IBM PPC970FX determines which interrupt sources are active by reading the interrupt status register in the Universe II The interrupt is negated after being serviced by the IBM PPC970FX VMEbus Interrupt Handling A VMEbus interrupt causes the Universe II to issue a normal VMEbus IACK cycle and to generate the specified interrupt output When the IACK cycle is completed the Universe II relinquishes the VMEbus The interrupt vector is read by the PCI resource servicing the interrupt output Hardware and internal interrupts are RORA Software interrupts are ROAK Universe Il s Mailbox Registers Un
39. en gt BE SB17 OR 008 05 ker UX Boso o mm o sez 39 Boses EE BE 888 HE Oooo To magu amp c m 855151503207 9 ores x 5803 toorn tyle S DD 1612778 PNS w 9 99 46 9 ng 08 POR 38g cou A es o 2 org 818888 9 ae ED 92 da aga 2888 5812 Eo Gg 2 PI ERE E E 3 C28 o Mio 45 ee Go 8528893 BER immu 5 2 2 85959 50 amy ieget SEs aso LIEN DB E gt PORIS 885 905 85 a BR 27099 Allg 2 HI asso nresescp 3928 8429558 Bee anng o O x 201 abl a8 EOD 8 E 224555 5 2 455 Tas Mom 2 4 gt gt 5816 S 3562 wwe 826952010 gen 9 SLO 2 lt lt 9920 22454 5 vu etin o mu mun d AEE e EE WU 928 gm 5652 5695 52685204046 N 4529 2 12261 82 552 BB 66565 Sag 0160 81958 ach 19 gt Ees CER ox 8 810014 ER 225 7 ALT CM si 7235 6949 220 60 s Dm 1192 8867 o 51026 a 81548 au 125 SB Saeco ee Nese M E 5852 1595 o 0290 P S n 80575 86 2 B58B8uBB
40. is the software code first invoked by a computer when powered on It enables the computer to boot by running other programs to assume control of the com puter Boot The process of initializing the hardware to execute and run an Operating Sys tem such as Solaris Linux or Windows cPCI Compact PCI An adaptation of the PCI Specification for industrial and or embedded applications requiring a more robust mechanical form factor than desktop PCI applications CPI Cycles per Instruction The number of clock cycles required to execute one instruction CTS Clear to send DCE to DTE DCD or CD Data carrier detected tone from a modem DCE to DTE DCE Data circuit terminating communications equipment a modem for exam E 1 Themis Computer TPPC64 Hardware Manual E 2 ple DDR SDRAM Double Data Rate Synchronous Dynamic Random Access Mem ory obtains greater bandwidth than regular SDRAM by transferring data on both the rising and falling edges of the clock signal called double pumped As a result the transfer rate nearly doubles without an increase in the frontside bus frequency DMA Direct Memory Access A facility of some architectures that allows a periph eral to read and write memory without intervention by the CPU DMA is a lim ited form or bus mastering DSR Data set ready DCE to DTE DTE Data terminal equipment a computer terminal or printer for example DTR Data terminal ready DTE
41. is marked B1 B5 B6 B9 Symbol CPU 0 Board Serial Ports e e Figure A 1 Dual Serial Ports A and B Connector Pinout Table A 1 Serial Ports A and B Connector Pin Signals Signal Name Port A Port B Pin ana Description Sio s Pin 1 DCD Carrier Detect DCD 1 2 RXD Receive Data RXD 2 3 TXD Transmit Data TXD 3 4 DTR Data Terminal Ready DTR 4 5 GND Signal Ground GND 5 6 DSR Data Set Ready DSR 6 7 RTS Request to send RTS 7 8 CTS Clear to send CTS 8 9 RI Ring indicator RI 9 PC board is marked A1 A5 A6 A9 a Important The and B associated with Serial Port connector pins on PC boards are interpreted as follows Port A pins are marked with a B Port B pins are marked with an A A 2 Themis Computer A Connector Pinouts and LED Indicators CPU 0 Baseboard A 1 1 2 USB Port A and Port B e Connector Type Type A Dual Stacked USB 1 1 standard e Manufacturer Part AMP 787617 4 Dual USB Ports USBO and B USB1 are installed on the front faceplate of the CPU 0 Baseboard see Appendix C Front Panel I O Connections and LEDs connector pinout for this stacked connector is given in Figure A 2 connector pin signals are described in Table A 2 USB Ports A and B support the USB 1 1 stan dard Symbol USB Ports A B CPU 0 Board J6 Figure A 2 Dual USB Ports A and B Connector Pinout
42. memory A command packet may be linked to another command packet so that when the DMA has finished the operations described by one command packet the DMA controller can automatically move on to the next command packet in the linked list of command packets refer to Controller on page 2 77 of the Universe II User s Manual Themis Computer Appendix Connector Pinouts and LED Indicators This appendix describes connector pinouts and their signals as well as LED status indicators for the TPPC64 and its associated boards The TPPC64 front panel con nectors and LEDs PMC XMC Carrier Boards 2P2 and 2P3 Paddle Board and Memory Module are each presented as individual sections A 1 A 1 1 A 1 1 1 CPU 0 Baseboard 0 Front Panel Connectors Serial Port A RS232 and Port B RS232 e Connector 2 stacked D Subminiature Micro D DB9 plug e Manufacturer Part ITT Cannon MDSM 18PE Z10 e Themis Cable P N 106878 Serial Port A TTYA and Port B TTYB are installed on the front faceplate of the CPU 0 Baseboard see Appendix C Front Panel I O Connections and LEDs connector pinout for both Serial Port A and Port B is given in Figure A 1 on page A 2 and connector pin signals are described in Table A 1 page A 2 As can be seen from Table A 1 both Port A and Port B follow RS232 protocol and provide full modem support A 1 Themis Computer TPPC64 Hardware Manual PC board
43. mode c The Universe ll operating mode VME system controller vs non VME system controller is determined by autosensing VME bus grant 3 during power up Table B 2 SCSI B Access Through VME P2 Connector CPU 0 Baseboard SCSI B Port Access Mode Auto Sensed VME P2 Connector 3 row VME backplane SE only NO YES 5 row VME backplane LVD or SE YES NO a 5 row access requires custom Paddle Board B 2 Themis Computer B Jumper Pin and Solder Bead Configurations Field Configurable Jumper Pins 11 191 ozon 8 4191 4120 E 7 059 c G G VME P1 594 O Le 4143 C4142 LA so patet reri I RII Spo NUTS TE 0000000 0000000 4 4 z 0000000 0000000 1000000090000 0000000009050 0000000 nnn 191 91
44. pet spei pron i diei sepu Ent teta tefie Rota C 10 viii Themis Computer Table of Contents Appendix D Board Diagrams D 1 D 1 0 and CPU 1 Baseboards uii dus Debt C02 deat pee ebd D 1 D 2 2P2 PMC XMC amp 2P3 PMC Carrier Boards D 1 Appendix E Glossary ote dte ten Re E 1 Appendix Slot Configurations sse F 1 Wr Index 1 Reader Comment Card ix Themis Computer TPPC64 Hardware Manual Themis Computer Table of Contents List of Figures Figure 1 1 TPPC64 0 Paddle 1 3 Figure 1 2 TPPC64 Paddle Board Connectors sese 1 4 Figure 1 3 TPPC64 0 Carrier Board and Paddle Board Installed 1 5 Figure 1 4 TPPC64 0 CPU 1 Carrier Board and Paddle Power Boards 1 5 Figure 1 5 TPPC64 CPU 1 Power Board essen enne enne 1 6 Figure 1 6 SCSI Termination Configurations esee nennen 1 7 Figure 1 7 Location of the TOD NVRAM Battery esee ene 1 14 Figure 1 8 TOD NVRAM Battery 1 15 Figure 21 TPPC64 CPU 0 CPU 1 Baseboard Block Diagram 2 2 Figure 3 1 8131 HyperTransport PCI X Tunnel 3 2 Figure 3 2 AMD 8111 HyperTransport Hub
45. signalling Tx Rx and GND from the Paddle Board Symbol Serial Ports i J6 5 2 3 6 Important Note 1 B B 5 02 must be configured before serial Ports A and B can be accessed from the P2 Paddle Board Paddle Board Edge Front View Figure A 14 Paddle Board Serial A and B Connector Pinouts Table A 13 Paddle Board Serial A and B Connector Pin Signals Serial Port A and Port B Pin Signal Name Pin Signal Name 1 NC 6 NC 2 RXD 7 NC 3 TXD 8 NC 4 NC 9 NC 5 GND Note No Connect Themis Computer A 17 TPPC64 Hardware Manual A 1 5 7 USB Ports C D and E F e Connector Type Type A Dual Stacked USB 1 1 standard two required e Manufacturer Part AMP 787617 4 USB Ports C USB2 D USB3 E USB4 and USBS are installed on the front edge of the TPPC64 Paddle Board with dual stacked Ports C and D below dual stacked Ports E and F see Figure A 7 on page A 12 A pinout for these stacked connectors is given in Figure 15 and connector pin signals are described in Table A 14 All USB Ports support the USB 1 1 standard Note that USB Port F USB5 is accessible only through a 5 row VME P2 connector Symbol lt gt Front View USB Port F is accessible only through a 5 row VME P2 Connector USB Ports 42 43 D F C E Paddle Board Edge Figure A 15 USB Ports C D E and F Connector Pinouts Tab
46. to DCE DUART Dual Universal Asynchronous Receiver Transmitter See UART Firmware This is software that stays with the hardware usually in a PROM or similar device FPGA Field Programmable Gate Array A gate array where the logic network can be programmed into the device after its manufacture An FPGA consists of an array of logic elements either gates or lookup table RAMs flip flops and programmable interconnect wiring GBIC GigaBit Interface Converter A hardware module used to attach network devices to fiber based transmission systems such as Fibre Channel and Gigabit Ethernet The GBIC converts serial electrical signals to serial optical signals and vice versa GHz Gigahertz billions of cycles per second 10 cps unit of frequency GUI The use of pictures rather than words to represent both the input and the out put of a program A program with a GUI runs under some windowing system HVD High Voltage Differential usually shortened to Differential see LVD Hardware In a system the CPU module cables and peripheral devices are typical examples of hardware PC Inter Integrated Circuit IOM I O Module Themis Computer E ISR In Service Reprogramming also Interrupt Service Routine JTAG Joint Test Action Group IEEE Standard 1149 1 for standard test access port protocol and boundary scan architecture LED Light Emitting Diode LVD Low Voltage Differential Device may A keyword ind
47. with any other VMEbus slave image 4 3 1 2 PCI Bus Fields The PCI bus fields specifies the mapping of a VMEbus transaction to the appropriate PCI bus transaction and allows users to translate a VMEbus address to a different address on the PCI bus The translation of VMEbus transactions beyond 4 GB results in a wrap around to the low portion of the address range Table 4 6 PCI Bus Fields for VMEbus Slave Image Field Register Bits Description Offsets VMEbus slave ad dress to a selected PCI ad Translation Offset VSIx TO dress Address space LAS in VSIx CTL Memory I O Configuration RMW LLRMW in VSIx_CTL RMW enable bit 4 10 Themis Computer 4 Universe Description A32 Image Offset 31 12 VME 31 12 o PCI 31 12 Slave Image Programming VMB 11 0 Y PCI 11 0 Figure 4 2 Address Translation for VMEbus to PCI Bus Transfers 4 3 1 3 Control Fields A VMEbus slave image is enabled using the EN bit of the control field The control field also specifies how reads and writes are processed either as a coupled transfer or a posted write At power up all images are disabled and configured for coupled reads and writes Table 4 7 Control Fields for VMEbus Slave Image Field Register Bits Description image enable EN in VSIx_CTL enable bit posted write PWEN in VSIx posted write enable bit prefetch
48. 0 PMC Cards 2 Cards 3 0 Graphics 0 Graphics 0 0 Audio 1 Audio VO 0 9 9 2 d 1 Figure F 1 TPPC64 VME Slot Configurations D Model TPP 54 1 2 1 1 PMC Card CPU 0 E Model TPPC64 2P2 2 P2B F 2 PMC Cards CPU 1 1 PMC Card CPU 0 F Model TPPC64 2P3 2 P3B 3 PMC Cards CPU 1 1 PMC Card CPU 0 VME Slots 3 VME Slots 2 VME Slots 3 PMC Cards 1 PMC Cards 3 PMC Cards 4 Graphics 0 Graphics 0 Graphics I O 0 Audio I O 0 Audio O 1 Audio O 0 S WA S AN X X S A amp amp 2 COC oC zs 3 Themis Computer TPPC64 Hardware Manual 4 Themis Computer Index Symbols 12V power connector 1 12 Numerics bus grants BG 2 4 IN to BG 2 4 10 100 1000Base T A 4 10 100 1000Base T Ethernet 1 10 10 100Base T Connector Pinout 16 10 100Base T Connector Pin Signals 16 10 100Base T Ethernet 1 11 2P2 PMC XMC Carrier Board 2 4 A 27 A 28 2P3 PMC Carrier Board 2 4 A 27 64 bit 133 Mhz PCI X bus 3 6 A Address Translation PCI Bus to VMEbus Transfers 4 5 AMD 8000 HyperTransport Technology 3 2 AMD 8111 HyperTransport I O Hub 3 3 AMD 8131 HyperTransport PCI X T
49. 2 EE choo cm S uec ent 953 8823 af reed IF St NE 8082 1042 20 o us 2 2 ultvu SB10 sees ere BS 12228 2 ozous m 8 25 54496 c eft 80905 Se S rso sue T mow 0 JM PED 8 Fc Es SB3 BESTE P Eee ans Page 901902 e BHO S 3 26099 0 EE S Jeu On et S 9 980999 BE soscu ol 85 2 800928 o 92 BOOP YL PP 19800 S zs Sg aeoo FSE 520 Wn Su easels Eg Elo 205 O O EE CB 3 E 128 o Sum 3 o Oe aay ty ad 5525 Og MIS 6 1269 T E 2 oS O 9300 Ge IEEE dos 05 6155253 TAAN E P 8 Hre HIE 7 dE PM Nu c MEC HT E 01659269 98 Ses a gno 77092068 81832283100 3 151662222 6 5565650 d 252 a ui 002252 0 d 598 288288 89025525 38 8 pyg tote S ER 28 4 Hed KE SEU Ee s ri SB4 38 BS Baa 4 621 6 ec OE SB8 Ooo D QM 5 E 3S2838ERHBB2B y D qa 52 Bee ED m US 3 AA An n istssr 00009 t S 4529 2 z5en a 9000 OF WeU
50. 2P3 PMC Carrier Boards Figure D 3 page D 4 and Figure D 4 page D 5 identify major components and connectors of the 2P2 PMC XMC and 2P3 PMC Carrier Boards respectively Note Refer to the PM C XMC Carrier Board Manual P N 112826 020 for in formation on the 2P2 PMC XMC and 2P3 PMC Carrier Boards D 1 Themis Computer TPPC64 Hardware Manual CPU 1 Riser Connector USB Port A Universe ll B Port B PCI to VME VME Status d Bridge LEDs 4 4 HyperT
51. 3 contains information on Service Processor and PIBS commands as well as a description of the Themis Computer VME software package for Yellow Dog Linux 4 0 Chapter Overview The chapters and appendices of this manual are briefly outlined as follows Chapter 1 Installation and Operation gives instructions on the installation and configuration of the TPPC64 for your particular environment and applica tion The information contained in this chapter is mandatory for the correct operation of the TPPC64 This chapter should be read in its entirety Chapter 2 System Overview and Specifications provides a brief overview of the TPPC64 along with its System Environmental and Power specifica tions Chapter 3 Hardware Overview describes the major IC chip components on the TPPC64 Chapter 4 Universe II Description provides detailed information concerning the PCI to VMEbus interface for the TPPC64 the Tundra Universe II For a more detailed description of the Universe II refer to the Universe II User s Manual available on the Tundra website at http www tundra com Appendix A Connector Pinouts and LED Indicators gives connector part numbers and pinouts for all user I O on the TPPC64 Themis Computer How to Use This Manual Appendix B Jumper Pin and Solder Bead Configurations provides a detailed description of each of the jumper pins and solder beads on the TPPC64 as well as diagrams illustrating t
52. 4 640 r gt a Hi ju 3 585 Figure 18 TPPC64 CPU 1 Power Board 1 6 lt i P2 Connector 000000 12V Power Connector Figure A 19 12V Power Connector Pinout Table A 20 12V Power Connector Pin Signals Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 12V 12V 12V Ground Ground Ground Themis Computer A Connector Pinouts and LED Indicators PMC XMC Carrier Boards A 3 1 PMC XMC Carrier Boards There are two types of Carrier Boards that will operate with the TPPC64 the 2P2 PMC XMC Carrier Board and the 2P3 PMC Carrier Board Note For more detailed information on Themis PMC XMC Carrier Boards refer to the PM C XMC Carrier Board Manual Themis P N 112826 020 2P2 PMC XMC Carrier Board A Caution A new 2P2 PMC XMC Carrier Board P N 112794 002 is designed to operate with the TPPC64 the original 2P2 PMC Carrier Board is not supported DO NOT ATTEMPT to operate the TPPC64 with the original 2P2 PMC Carrier Board A 3 2 components on the TPPC64 2P2 PMC XMC Carrier Board include Gigabit Ethernet Port B with embedded transformer dual LEDs RJ45 Stereo Audio Line in Mic in and Line out or Headphones out User defined 16 position rotary switch Serial TTY Port A and Port B System Serial Port E and Port F RS232 PMC XMC Module slot 1 and slot 2 see following Note signals available as P2 option
53. 411401 Mounted Baseboard Top side 4 240 2 Figure A 21 Memory Module Baseboard Connectors Socket Receptacle amp Plug A 29 Themis Computer TPPC64 Hardware Manual A 30 Themis Computer Appendix Jumper Pin and Solder Bead Configurations 1 Overview This appendix provides a summary of jumper pin and solder bead configurations for all boards on TPPC64 Jumper pins are considered field configurable and may be altered by a user on site Solder beads are considered factory configurable and must not be altered by the user If a solder bead requires reconfiguration contact Themis Customer Service the TPPC64 Warning Attempting to alter solder bead configuration could seriously damage DO NOT ATTEMPT TO ALTER SOLDER BEAD CONFIGURATIONS B 2 Field Configurable Jumper Pins B 2 1 CPU 0 Baseboard Jumper Pins Jumper pins are found only on the top side component side of the TPPC64 0 Baseboard and are described in Table 1 on page B 2 pins can be virtually changed by a command through the Service Processor see Caution a jumper has NOT been installed the setting of Table 1 jumper chapter on Service Processor Commands in the TPPC64 Software Manual B 1 Themis Computer TPPC64 Hardware Manual In Table B 1 an ON jumper pos
54. 5 VME_ lt D04 gt VME_BGOUT_L lt 0 gt VME_ lt D12 gt 6 VME_ lt D05 gt VME_BGIN_L lt 1 gt VME_ lt D13 gt 7 VME D06 VME BGOUT L 1 VME_ lt D14 gt 8 VME_ lt D07 gt VME_BGIN_L lt 2 gt VME_ lt D15 gt 9 GND VME_BGOUT_L lt 2 gt GND 10 VME_SYSCLK VME_BGIN_L lt 3 gt VME_SYSFAIL_L 11 GND VME_BGOUT_L lt 3 gt VME_BERR_L 12 VME DS 1 lt 1 gt VME BR 1 lt 0 gt VME SYSRESET L 13 VME DS 1 lt 0 gt VME BR 1 lt 1 gt VME WORD L 14 VME WRITE L VME BR L 2 VME lt 5 gt 15 GND VME BR 1 lt 3 gt VME lt 23 gt 16 VME DTACK L VME lt 0 gt VME lt 22 gt 17 GND VME lt 1 gt VME lt 21 gt 18 VME AS L VME lt 2 gt VME lt 20 gt 19 GND VME lt 3 gt VME lt 19 gt 20 VME IACK L GND VME lt 18 gt 21 VME IACKIN L NC VME lt 17 gt 22 VME IACKOUT L NC VME lt 16 gt 23 VME lt 04 GND VME lt 15 gt 24 VME lt 07 gt IRQ 1 lt 7 gt lt 14 gt 25 VME lt 06 gt VME IRQ 1 lt 6 gt VME lt 13 gt 26 VME lt 05 gt VME IRQ 1 lt 5 gt VME lt 12 gt 27 VME lt 04 gt IRQ 1 lt 4 gt VME lt 11 gt 28 VME lt 03 gt 1 lt 3 gt VME lt 10 gt 29 VME lt 02 gt IRQ 1 lt 2 gt VME lt 09 gt 30 VME lt 01 gt VME IRQ 1 lt 1 gt VME lt 08 gt 31 12V Not Used NC 12V 32 VCC VCC Themis Computer A Connector Pinouts and LED Indicators CPU 0 Baseboard
55. 8 Estimated Power Requirements Table 2 8 Estimated Power Requirements Watts Dissipation typical Single processor Watts Dissipation typical Dual processors 95 Watts 110 Watts max 138 Watts 160 Watts max Themis Computer Overview Section Chapter Hardware Overview The following sections provide a description of the major IC chip components of the TPPC64 3 1 3 1 1 CPU 0 and CPU 1 Baseboards A block diagram of the major CPU 0 and CPU 1 IC components is provided in Fig ure 2 1 on page 2 2 of Chapter 2 System Overview and Specifications IBM 970FX Processor and Cache PowerPC 970 processor a superscalar design with multiple pipe lined execution units is used on both TPPC64 Baseboards CPU 0 and CPU 1 Each CPU can be configured through the Service Processor to speeds up to 1 8 GHz For details on the 970FX Service Processor refer to the Themis TPPC64 Soft ware Manual P N 112106 023 With a design that optimizes high performance as well as a scalable instruction set architecture the IBM 970FX is ideal for a wide range of applications The 970FX is capable of executing in a 32 bit mixed 32 bit and 64 bit or 64 bit only environ ment At the present the TPPC64 is implemented under Linux Yellow Dog and operates with a software interface for the VME64bus and other on board peripheral devices again refer to the Themis TPPC64 Sof
56. A64 PCI Express 3 3 volt Key Note Refer to the checkbox note in 5 volt Key Section A 3 1 for important information on XMC connections Bottom View Figure A 20 The 2P2 PMC XMC Carrier Board Top and Bottom Views A 28 Themis Computer A Connector Pinouts and LED Indicators Memory Module Connector A 4 Memory Module Connector Connector 2 Part Socket Plug 2 row 240 pin Board to Board Socket is mounted on Baseboard Manufacturer Part Samtec QSH 120 01 L D A Hi Speed Socket A single custom Memory Module is installed onto the TPPC64 CPU 0 Baseboard with a 2 row 240 pin plug that connects to a socket directly mounted onto the top surface of the CPU 0 PCB see Figure A 21 ration see Figure 1 3 on page 1 5 between VME slots only one Memory Module Caution Because of the VME Specification requiring a 0 8 inch interboard sepa can be installed onto a TPPC64 Baseboard stacking not supported y P11401 Plug Side View Memory Module Mounted on Bottom side of Memory Module 4 1 Wiz 239 F 311401 239 1 Baseboard J11401 Socket Receptacle 4
57. Board contains a single Ethernet 10 100Base T integrated magnetics port RJ45 on its front edge see Figure A 13 for a connector pinout and Table A 13 for pin signals The RJ45 connector housing also contains two embed ded LEDs one yellow to indicate the ethernet link speed the second green to dis play network activity see Figure A 13 10 100Base T Symbol Ethernet TP e Speed e 100 Mbit sec e Off 10 Mbit sec Link LED Yellow 1 Network Activity LED Green Paddle Board Edge Front View Figure A 13 Ethernet 10 100Base T Connector Pinout Table A 12 Ethernet 10 100Base T Connector Pin Signals Pin Signal Name Description 1 TXD Transmit data positive 2 TXD Transmit data negative 3 RXD Receive data positive 4 5 6 RXD Receive data negative 7 NC No connection 8 GND Chassis ground A 16 Themis Computer A Connector Pinouts and LED Indicators CPU 0 Baseboard A 1 5 6 Serial Port A RS232 and Port B RS232 e Connector Type 2 stacked D Subminiature Micro D DB9 plug e Manufacturer Part ITT Cannon MDSM 18PE Z10 e Themis Cable P N 106878 The TPPC64 P2 Paddle Board contains two RS232 serial ports A and B on its front edge see Figure A 14 for a connector pinout and Table A 13 for pin signals Note that serial ports A and B have full modem support when accessed from the front panel but only minimal
58. C XMC Module slot 2 A 27 Power Board installation 1 6 Power Board CPU 1 A 26 Power Requirements 2 8 Processor amp Memory Subsystems 2 5 Programmable Slave Images VMEbus and PCI bus 4 18 Pulse JOO11D01B A 6 push button RESET switch A 7 R Registering the TPPC64 xxi RJ45 1 10 rotary switch A 27 Round Robin arbitration 4 6 S Samtec QSH 120 01 L D A A 29 SCSI controller 7 termination 7 1 6 SCSI A Access Definition B 2 5 SCSI A Connector Pinout 5 SCSI Controller 3 5 SCSI Port A Connector Pin Signals A 6 SCSI Port B Connector Paddle Board 13 SCSI Port B Connector Pinouts Paddle Board A 4 Serial TTY Ports E and F A 27 Serial Connector Pinout A 7 Serial A B Connector Pin Signals A 7 Index 3 Themis Computer TPPC64 Hardware Manual Serial Port A RS232 1 Serial Port B RS232 1 Serial Ports A B Connector Pinouts A 2 Serial Ports A B Connector Pin Signals A 2 Serial Ports A B Connectors A 7 Service Processor 3 Special PCI Target Image Register Offset 188 4 15 SPU CPU Duality 2 3 Status LEDs System 11 11 Stereo Audio 1 11 Stereo Audio In Out Connectors A 5 Stereo Audio Line in Mic in and Line out A 27 SYSCON B 2 SYSCON Module 4 5 System Board J1 P1 connector pin signals A 20 System Board VME J1 P1 Pin Signals 8 System Board VME J1 P1 Pinout 7 System Board VME J2 P2 Pin Signals A 0 System Board VME J2 P2 Pinout 9 System Specificatio
59. CSI B BSY 6 GND GND VME A 26 SCSI B ACK SCSI B ACK 7 TP1 TXD N 12V AUX VME A 27 SCSI B RST SCSI B RST 8 GND GND VME A 28 SCSI MSG SCSI B MSG 9 TP1 REF GPIOO VME A 29 SCSI B SEL SCSI B SEL VME A 30 SCSI CD SCSI B CD A 31 SCSI B REQC SCSI G ND USB2 P ND D 42 GND GND SCSI B IO SCSI B 10 USB5 N F 45V SCSI B DAT O SCSI B DAT O GND USB3 P D VME D 16 SCSI B DAT 1 C SCSI DAT 1 LED1 USB3 N D VME_D 17 SCSI B DAT 2JC SCSI_B_DAT 2 GND GND DI 18 SCSI B DAT 3 C SCSI B DAT 3 LED2 WD ALARM VME D 19 SCSI B DAT 4 C SCSI_B_DAT 4 GND TTYA TXD VME_D 20 SCSI_B_DAT 5 SCSI_B_DAT 5 GPIO2 TTYA RXD VME DI21 SCSI B DAT 6 C SCSI 6 NES GND TTYB TXD VME D 22 SCSI B DAT 7 C SCSI RXD VME_D 23 SCSI_B_PAR O SCSI B PAR OJ USBA P E GND SCSI B DAT B JC SCSI B DAT 8 23 AC97 BCLK 05 4 N E VME_D 24 SCSI B 9 SCSI DATI 9 24 GND GPIO1 VME D 25 SCSI B DAT 10 SCSI 10 25 AC97 DOUT 12 AUX VME D 26 SCSI B DAT 11
60. D 04 56 Ground 57 V I O 58 AD 03 59 AD 02 60 AD 01 61 AD 0 62 5V 63 Ground 64 REQ64 Themis Computer A 23 TPPC64 Hardware Manual 24 Table 18 Slot Connector J1003 Signals 32 bit Pin Signal Pin Signal 1 12V 2 TRST 3 TMS 4 TDO 5 TDI 6 Ground 7 Ground 8 PCI RSVD 9 PCI RSVD 10 PCI RSVD 11 BUSMODE2 12 3 3V 13 RST 14 BUSMODE3 15 3 3V 16 BUSMODE4 17 PCI RSVD 18 Ground 19 AD 30 20 AD 29 21 Ground 22 AD 26 23 AD 24 24 3 3V 25 IDSEL 26 AD 23 27 3 3V 28 AD 20 29 AD 18 30 Ground 31 AD 16 32 C BE 2 33 Ground 34 PCI RSVD 35 TRDY 36 3 3V 37 Ground 38 STOP 39 PERR 40 Ground 41 3 3V 42 SERR 43 C BE 1 44 Ground 45 AD 14 46 AD 13 47 Ground 48 AD 10 49 AD 08 50 3 3V 51 AD 07 52 PCI RSVD 53 3 3V 54 PCI RSVD 55 PMC RSVD 56 Ground 57 PMC RSVD 58 PCI RSVD 59 Ground 60 PCI RSVD 61 ACK64 62 3 3V 63 Ground 64 PCI RSVD Themis Computer A Connector Pinouts and LED Indicators CPU 1 Baseboard Table A 19 PMC Slot Connector J1004 Signals 64 bit Pin Signal Pin Signal 1 PCI RSVD Ground 3 Ground C BE 7 5 C BE 6 C BE 5 7 C BE 4 Ground 9 V I O 10 PAR64 11 AD 63 12 AD 62 13 AD 61 14 Ground 15 Gr
61. E Status LEDs SHUT DOWN POWER OK Serial Port TTY B VME STATUS o MASTER SYSTEM FAIL id lt Ultra320 SCSI Port A Note Port B is routed through the rear VME64 P2 connector LNK Link speed Yellow ON 10 Mbit sec OFF see dual LEDs below ACT Activity Green ON Signal detected Umm Link speed is 100 Mbit sec or 1000 Mbit sec when turned ON Figure C 3 TPPC64 CPU 0 Baseboard C 4 Themis Computer C Front Panel I O Connections and LEDs TPPC64 Front Panels 2 2 64 2 2 1 0 amp 2 PMC Carrier Board SSS A H USER ENBL SH 90 99 SYS STATUS gt STATUS SLAVE AST 6 sys bag 14 4 PMC Module 2 P M NND Ethernet B OVER TEMP O A b NN 1 Line In Mic In See Figure C 1 for description P RESET of Front Panel N Line Out Headphones Out D Q User defined Rotary Switch 9 gt Module 1 Line In Out Mic Headphones are switchable through on board solder beads See Table B 9 page B 13 TPPC64 CPU 0 2P2 PMC XMC Carrier Board Figure C 4 TPPC64 CPU 0 and 2P2 PMC XMC Carrier Board C 5 Themis Computer TPPC64 Hardware Manual C 2 3 TPPC64 2P3 1 CPU 0 amp 3 PMC Carrier Board PMC Module 3
62. F TE Stacked USB LVD 5 row or o ed Single Ended 3 row Ultra320 SCSI Port B gt vu m uw USB Ports E lt 5 Stacked USB GPIO Test Connector a gt a ve E Serial Ports A B Dual DB9 Top Side Figure 1 2 TPPC64 Paddle Board Connectors A Warning Do not install the CPU 0 Paddle Board behind the P1 connector of the VME64 backplane To do so may result in damage to both the Paddle Board and the CPU 0 Baseboard Install only behind the P2 connector 1 4 1 After unpacking the Paddle Board attach it directly behind the CPU 0 P2 connector of the VME64 backplane Attach the 6 pin male Molex connector end of the 12 volt auxiliary power cable P N 111230 001 to the J9 connector of the Paddle Board see Figure 1 2 and the two 6 spade lugs as follows also see CPU 0 P2 Paddle Board on page 12 Appendix A Connector Pinouts and LED Indicators Lug from pins 1 2 3 to a 12 volt source on the VME chassis power supply Lug from pins 4 5 6 to a ground source on the VME chassis power supply 3 Connect desired I O cables to the Paddle Board Themis Computer 1 Installation and Operation Install the TPPC64 CPU 0 Paddle Board VME64 Backplane VME J2 Connector Memory Board Top View TPPC64 CPU 0 Paddle Board 12V 2P2 PMC XMC Car
63. Figure C 6 64 CPU Q CPU T C 7 Figure 7 CPU 0 CPU 1 Baseboards and 2P2 PMC XMC Carrier Board C 8 Figure C 8 CPU 0 CPU 1 Baseboards and 3 PMC Carrier C 9 Figure C 9 TPPC64 Front Panel LEDS eese enne C 10 Figure D 1 0 Baseboard Front Panel Component and Connector Diagram D 2 Figure D 2 CPU 1 Baseboard Front Panel Component and Connector Diagram D 3 Figure D 3 2P2 PMC XMC Carrier Board Component Connector Diagram D 4 Figure D 4 2P3 PMC Carrier Board Component Connector Diagram D 5 Figure F 1 64 VME Slot 5 0 0000 0 3 xii Themis Computer Table of Contents List of Tables Table 1 1 TPPCO4 Model Configurations 1 1 Table 1 2 TPPCO4 Peripheral 1 9 Table 2 1 Memory 2 1 Table 2 2 Processor Specifications s sese eL ERR SA EXE UNA 2 5 Table 2 3 Memory SpecifiCattOns ae 2 5 Table 2 4 Auxiliary Functions Specifications eese eese eene 2 6 Table 2 5 TPPC64 Operating Environmental Specifications 2 7 Table 2 6 TPPCO64 Airflow Requirements 2 7 Table 2 7 TPPC64 Non operating Environmental Specifications
64. I Description and the Tundra Uni verse II User Manual Tundra 8091142 MD300 01 Themis Computer 3 Hardware Overview CPU 0 and CPU 1 Baseboards 3 1 5 Dual Ultra320 SCSI Controller The LSI Logic 53C1030 dual Ultra320 SCSI controller is an extremely high perfor mance and intelligent PCI X to dual channel Ultra320 SCSI controller with a Fusion MPT Message Passing Technology based architecture that provides the highest performance and unparalleled flexibility reliability and binary software compatibility LSI53C1030 is pin compatible with the LCI53C1010R Ultral60 SCSI control ler and has a 133 MHz 64 bit PCI X interface PCI X Bus B that is compliant with PCI 2 2 and PCI X Addendum Rev 1 0 and PCI Power Management Interface Other features include Double transition clocking for 320 MB s throughput on each channel Packetized protocol Quick Arbitrate and Select QAS e Skew compensation InterSymbol Interference ISI compensation Domain validation including margining Performance optimized architecture SCSI Interrupt Steering Logic SISL to provide alternate interrupt routing for RAID applications EEE 1149 1 JTAG boundary scan e Proven integrated LVDlink transceivers for direct attach to either low voltage differential or SE single ended SCSI buses with precision controlled slew rates Comprehensive SureLINK domain validation Flash and local memory interface Integrated
65. ISC Continued Bits Name Description Access State VME64 Auto ID R W 16 V64AUTO Write 0 no effect 1 Initiate sequence Power up This bit initiates the Universe II VME64 Auto ID Slave Option participation unspecified bits in this table are RESERVED for the Universe Reading the bits results an undefined state writing to these bits should be 0 4 2 4 1 4 2 4 2 4 6 When the Universe II is configured as the System Controller it provides the follow ing functions on the VMEbus A 16MHz Clock Driver Arbitration Module A bus timer An IACK Daisy Chain Driver DCD The TPPC64 supports Round Robin arbitration The VMEbus arbitrator time out is also controlled by the MISC register described above The timer may be set to either 16 Us 256 us or disabled The default setting is 16 Us The arbitration timer has a granularity of 8 us setting the timer to 16 Us means the timer may expire in as little as 8 Us or as much as 24 us It should also be noted that disabling the arbitration timer implies that the Universe II will not recover from an access error Disabling the arbitration timer is not recommended Automatic Slot Identification The Universe II supports two types of Auto ID functionality e Auto Slot ID as described by the VME64 specification Proprietary Method which is developed by Tundra Refer to Auto Slot ID VME64 Spec
66. Mirroring support Fusion MPT architecture with drivers supporting Windows NT 2000 Linux Solaris UnixWare and Novell netware operating systems 456 pin EPBGA package 3 5 Themis Computer TPPC64 Hardware Manual 3 1 6 LPC Super I O Controller The National Semiconductor PC87417 LPC Low Pin Count Super I O Controller is connected to the Southbridge HyperTransport I O bridge over the LPC bus It con trols the 8 MB boot flash as well as both TTYA and TTYB serial ports 3 1 7 Dual Gigabit Ethernet Controller The dual gigabit Gbit Ethernet interface uses one Intel FW82546 controller device to control both RJ45 Ethernet ports A1 and A2 and will auto sense the port speed to be either 10 100 Mbit sec or 1 Gbit sec rates The Ethernet controller is connected to the 133 Mhz 64 bit PCI X Bus B Each Ethernet connector contains two LEDs imbedded in the connector shell one for link speed yellow and the other for link activity green See Section A 1 1 3 Gigabit Ethernet TPE Port A1 and Port A2 on page A 4 for more details 3 6 Themis Computer 3 Hardware Overview Memory Subsystem 3 2 Memory Subsystem The TPPC64 supports a single custom Themis SDRAM Memory Module plugged directly into the Baseboard through a 2 row 240 pin connector see Figure 3 3 and secured to the PCB by five screws The memory data path is 72 bits with 8 bits assigned to ECC Memory complies to PC 133 timing Custom Me
67. NC No Connection Themis Computer A Connector Pinouts and LED Indicators CPU 1 Baseboard Table A 16 CPU 1 VME64 P2 Connector Pin Signals Pin Row A Signal Row B Signal Row C Signal 1 12V 5 2 GND GND NC 3 12V NC NC 4 GND NC NC 5 12V NC NC 6 GND NC NC 7 12V NC NC 8 GND NC NC 9 NC NC NC 10 GND NC NC 11 NC NC NC 12 GND GND NC 13 NC 5 14 GND NC NC 15 NC NC NC 16 GND NC NC 17 NC NC NC 18 GND NC NC 19 NC NC NC 20 GND NC NC 21 NC NC NC 22 GND GND NC 23 NC NC NC 24 GND NC NC 25 12V NC NC 26 GND NC NC 27 12V NC NC 28 GND NC NC 29 12V NC NC 30 GND NC NC 31 12V GND NC 32 GND 5V NC a NC No Connection Themis Computer A 21 TPPC64 Hardware Manual A 2 3 CPU 1 PMC Card Slot Connectors An optional PMC card can be connected to the CPU 1 Baseboard through three 3 64 pin slot connectors J1002 J1003 and J1004 This interface supports 3 3V 32 or 64 bits at 33 MHz or 66 MHz If an external PMC Carrier Board is not attached to CPU 1 the installed optional PMC card can operate through the PCI X Bus A at up to 133 MHz 64 bits e Connector 2 row x 32 64 pin 1 mm pin 3 required e Manufacturer Part 120521 1
68. OVER TEMP G NON PWR OK E F G H left to right J al ell Top Half Bottom Half Figure C 9 TPPC64 Front Panel LEDs Themis Computer C Front Panel Connections and LEDs LEDs Table C 1 TPPC64 Front Panel LED Interpretation Item Callout Function Color Frequency and or Interpretation A User USER Red e Defined by the user B Shutdown SH DN Orange e TPPC64 system is shutting down System Status Yellow on TPPC64 is operational POWER Off Power on TPPC64 board is not operational D Enable ENBL Green e TPPC64 system is up E System Reset RST Red e VME sysreset status VME F System SYS FAIL Orange e VME sysfail status Status G Master MSTR Yellow e TPPC64 is the VME master H Slave SLAVE Green e TPPC64 is the VME slave Green e CPU 0 temperature is OK Orange e CPU 0 exceeds warning threshold iid Over Temperature Red e CPU 0 exceeds overtemp threshold Status OVER TEMP Green e CPU 1 temperature is J Orange e CPU 1 exceeds warning threshold Red e CPU 1 exceeds overtemp threshold POWER K Poweris OK PWR OK Green eCPU 1 power is OK Status TE An Ethernet link has been established Gigabit L Link Connection LNK Yellow 9 Ethernet Link is 10 Mbps if N and O are off see below Ports AtandA2 Network Acht Green
69. SCSI B DAT 11 26 GND GND VME_D 27 SCSI B DAT 12 SCSI DAT 12 27 AC97 DIN 12 AUX VME_D 28 SCSI B DAT 13 SCSI B DAT 13 28 GND GND VME_D 29 SCSI_B_DAT 14 SCSI_B_DAT 14 29 AC97 SYNC 12 AUX VME D 30 SCSI B DAT 15 SCSI B 15 30 GND GND VME D 31 SCSI B PAR 1 SCSI B PAR 1 AC97 RST 12V AUX GND 5V 5V 5V A 10 Themis Computer A Connector Pinouts and LED Indicators A 1 3 A 1 4 CPU 0 Baseboard Push Button RESET A push button RESET switch is located on the Front Panel of the CPU 0 Baseboard and is accessible by inserting an object the size of a wooden toothpick or similar non conducting pointed object The RESET switch will initiate a POR Reset to the PPC970FX which is propagated throughout the TPPC64 Status LEDs The following LEDs are located on the Front Panel of the CPU 0 Baseboard see Appendix C Front Panel I O Connections and LEDs System Status LEDs User Shutdown Power OK and Enable VME Status LEDs Reset System Fail VME Master and VME Slave Table A 7 Color Interpretation of Front Panel LEDs Type LED Color Type Interpretation System Status User Red Static e Defined by user Shutdown Orange Static e TPPC64 system is shutting down Power OK Yellow Static e System power is operational Enable Green Static e System is up VME Status Reset Red Static VME system reset System Fail Orang
70. TPPC64 Hardware Manual THEMIS Themis Computer Americas and Pacific Rim 47200 Bayside Parkway Fremont CA 94538 Phone 510 252 0870 Fax 510 490 5529 World Wide Web http www themis com Version 1 1 January 2007 Themis Computer Rest of World 5 Rue Irene Joliot Curie 38320 Eybens France Phone 433 476 14 77 80 Fax 433 476 14 77 89 Copyright 2007 Themis Computer Inc ALL RIGHTS RESERVED No part of this publication may be reproduced in any form by photocopy microfilm retrieval system or by any other means now known or hereafter invented without the prior written permission of Themis Computer The information in this publication has been carefully checked and is believed to be accurate However Themis Computer assumes no responsibility for inaccuracies Themis Computer retains the right to make changes to this publication at any time without prior notice Themis Computer does not assume any liability arising from the application or use of this publication or the product s described herein RESTRICTED RIGHTS LEGEND Use duplication or disclosure by the United States Government is subject to the restrictions set forth in DFARS 252 227 7013 1 1 and FAR 52 227 19 TRADEMARKS Themis9 is a registered trademark of Themis Computer Inc PPC64 and PowerPC are registered trademarks of IBM Corporation Yellow Dog Linux is a trademark of Terra Soft Solutions LSI Logic is a registered trademark o
71. Themis Computer TPPC64 Hardware Manual 3 4 3 1 4 Major features of the AMD 8111 include the following An 8 bit HyperTransport interface 33 MHz 32 bit PCI 2 2 compliant PCI bus with support for up to eight PCI devices An 97 interface supporting soft modem and six channel soft audio An integrated 10 100 Ethernet MAC with MII interface not used Two USB ORCI controllers and one USB EHCI controller supporting six ports USB version 1 1 An LPC bus A high precision event timer A serial IRQ interface An IOAPIC controller A real time clock RTC ACPI compliant power management logic 32 GPIO pins multiplexed with other functions Privacy security logic 492 PBGA package Universe PCI to VME Bridge The Tundra CA91C142 Universe II controller ASIC interfaces the local 32 bit PCI bus to the 64 bit VMEbus The Universe II includes a 33 MHz 32 bit PCI bus inter face a fully compliant high performance 64 bit VMEbus interface as well as broad range of VMEbus address and data transfer modes of A32 A24 A16 master and slave transfer except for A64 and A40 D64 D32 D16 master and slave transfer except for MD32 MBLT BLT ADOH RMW LOCK and location monitors The Universe II also includes support for full VMEbus System Controller eight user programmable slave images and seven interrupt lines For more information on the Universe II refer to Chapter 4 Universe I
72. Themis Computer TPPC64 Hardware Manual xvi Themis Computer values its customer comments and opinions therefore a Reader Comment Card is located at the end of this manual for your use Please take the time to fill out this card with any comments concerning Themis products and ser vices and return it to Themis Computer Your comments may also be forwarded to Themis by sending email to docfeedback themis com TPPC64 Models The TPPC64 has a total of six 6 models presently available see Table mod els are based on a combination of the CPU 0 Baseboard the CPU 1 Baseboard and two types of Carrier Boards one with two PMC XMC module slots see following Caution and one with three PMC module slots TGA3D 3D Graphics Boards not supported by the TPPC64 at this time Caution A new 2P2 PMC XMC Carrier Board P N 112794 002 has been de signed to operate with the TPPC64 system replacing the original 2P2 PMC Carrier Board DO NOT ATTEMPT to operate the older 2P2 PMC Carrier Board with the TPPC64 Table 1 TPPC64 Model Configurations Baseboard 2P2 PMC XMC 2P3 PMC Carrier Board Carrier Board Model vee 51012 0 3 VMESIot20r3 TPPC64 1 1 TPPC64 2P2 1 Yes Slot 2 64 2P3 1 Yes Slot 2 TPPC64 1 2 Yes Yes TPPC64 2 2 2 Yes Yes Slot 3 64 2P3 2 Yes Yes Slot 3 a The 64 does not support PCI Express hen
73. U 1 ON Enable CPU 1 halt when CPC925 CHKSTOP is asserted JP5 OFF Disable CPU 1 halt when CPC925 CHKSTOP is asserted ON Disable the POR debug mode of the IBM PPC970FX CPU 1 JP6 OFF Enable the POR debug mode of the IBM PPC970FX CPU 1 JP7 PCI Mode only JP7 and JP8 are set together see Table B 5 on page B 5 to regulate the JP8 PCI speed of the PMC Module installed in CPU 1 and an attached PMC Carrier Board Short 1 2 CPU 1 JTAG scan data input is from the 0 board JP9 CPU 1 JTAG scan data input is from the RISCwatch connector on the Short 2 3 CPU 1 board ON Driver impedance of the CPU 1 PCI bridge for the secondary PCI bus PMC Module slot and PMC Carrier Board is 20 ohms JP10 OFF Driver impedance of the CPU 1 PCI bridge for the secondary PCI bus PMC Module slot and PMC Carrier Board is 40 ohms ON Driver impedance of the CPU 1 PCI bridge for the primary PCI bus 0 board interface is 20 ohms JP11 OFF Driver impedance of the CPU 1 PCI bridge for the primary PCI bus 0 board interface is 40 ohms a Boldface the default jumper position B 4 Themis Computer B Jumper Pin and Solder Bead Configurations Field Configurable Jumper Pins Table B 4 Setting CPU 1 PMC Module PCI X Mode Clock Speed JP2 JP3 PCI X Clock Speed ON ON 66 MHz OFF OFF 100 MHz OFF ON 133 MHz ON OFF Not Defined Table B 5 Setting CPU 1 PMC Module PCI Mode Clock
74. VINT MAP1 SW INT 000 BI Mod MISC CTL BI Disabled VD 28 AUTO_SYSCON Detect MISC_CTL SYSCON Enabled VBG3IN VCSR_SET SYSFAIL Asserted VD 27 SYSFAIL Assertion VCSR_CLR SYSFAIL EN Disabled VA 13 LSIO CTL LAS 0 Memory VA 12 PCI Target IMAGE VAS A16 VA 11 10 LSIO BS BS 0x0 VA 9 6 LSIO BD BD 0x0 VA 5 2 Themis Computer 4 7 TPPC64 Hardware Manual Table 4 2 Universe Power Up Options Continued Option Register Field Default Pins PCI Bus Size MISC STAT LCLSIZE 32 bit REQ64 PCI CSR Image Space PCI CSR BM Disabled VA 14 Refer to PCI Register Access SPACE are 2 VA 1 i PCI BS1 Table 4 4 PCI Bus Size MISC STAT LCLSIZE 32 bit REQ64 PCI CSR Image Size PCI CSR BM disabled VA 14 a The LAS field will enable the PCI CSR registers IOS or MS field if the EN FIELD of the LSIO register is set b As per PCI 2 1 Specification the PCI Bus Size is loaded on any RST event c Following the PCI 2 1 Specification the PCI Bus Size is loaded on any RST event The PCI Configuration Base Address 0 and Base Address 1 Registers offsets are 0x010 and 0x014 respectively The registers specify the 4KB aligned base address of the 4 KB Universe II register space on PCI The power up options determine if the registers are mapped into Memory or I O space Table 4 3 Configuration Base Address 0 Register PCI BSO
75. al Description Pin Signal Description 1 DB 12 Data 12 35 DB 12 Data 12 2 DB 13 Data 13 36 DB 13 Data 13 3 DB 14 Data 14 37 DB 14 Data 14 4 DB 15 Data 15 38 DB 15 Data 15 5 DB P1 Parity 1 39 DB P1 Parity 1 6 DB 0 Data 0 40 DB 0 Data 0 7 DB 1 Data 1 41 DB 1 Data 1 8 DB 2 Data 2 42 DB 2 Data 2 9 DB 3 Data 3 43 DB 3 Data 3 10 DB 4 Data 4 44 DB 4 Data 4 11 DB 5 Data 5 45 DB 5 Data 5 12 DB 6 Data 6 46 DB 6 Data 6 13 DB 7 Data 7 47 DB 7 Data 7 14 DB PO Parity 0 48 DB PO Parity 0 15 GND Ground 49 GND Ground 16 DiffSens Sense Differential 50 GND Ground 17 TermPwr Termination Power 51 TermPwr Termination Power 18 TermPwr Termination Power 52 TermPwr Termination Power 19 Open Not Connected 53 Open Not Connected 20 SCSI Sense Sense Cable 54 GND Ground 21 ATN Attention 55 ATN Attention 22 GND Ground 56 GND Ground 23 BSY Busy 57 BSY Busy 24 ACK Acknowledge 58 Acknowledge 25 RST Reset 59 RST Reset 26 MSG Message 60 MSG Message 27 SEL Select 61 SEL Select 28 CD Command 62 CD Command 29 REQ Request 63 REQ Request 30 Input Output 64 Input Output 31 DB 8 Data 8 65 DB 8 Data 8 32 DB 9 Data 9 66 DB 9 Data 9 33 DB 10 Data 10 67 DB 10 Data 10 34 DB 11 Data 11 68 DB 11 Data 11
76. al was useful Agree Disagree Not Applicable Please write down any comments you may have about this manual including how it can be improved Name Title Company Address
77. and TTYB Depending on the setting of CPU 0 solder bead 5 02 see Appendix B Jumper Pin and Solder Bead Configurations TTYA RS232 and TTYB RS232 are avail able from the Front Panel or from the Baseboard VME P2 connector and are sup ported by the serial controller Note Depending on the setting of solder bead 5 02 TTYA and TTYB are en abled for access from the Front Panel or from the VME P2 backplane When one access is enabled the alternate access is disabled Front Panel Connection When enabled through solder bead 5 02 shorted and TTYB are available through the Front Panel Use cable P N 108113 of the integration kit 9 pin male Micro DB9 to 25 pin male 506025 to access these ports from the Front Panel Two software control mechanisms are used to operate the TPPC64 system PIBS PowerPC Initialization and Boot Software commands and SPU Service Processor Unit commands When connecting a console to the system it is important to remember that TTYA must be used to access PIBS followed by the OS Operating System Linux for example and TTYB must be used to access the SPU see the TPPC64 Software Manual P N 112106 023 for more detail VME P2 Connection When enabled through solder bead SBO2 open and TTYB are available only through a paddle board connected to the VME P2 bus Ethernet Networks 10 100 1000Base T Gigabit The TPPC64 features dual RJ45 connectors on the Front Panel Ether
78. and a VMEbus master requests for a block read trans action BLT or MBLT When the Universe II receives a request for the block transfer it begins to fill its Read Data FIFO RDFIFO using burst transactions from the PCI bus resource The initiating VMEbus master then obtains its block read data from the RDFIFO of the Universe II rather than the PCI resources directly A RMW cycle allows a VMEbus master to read from a VMEbus slave and then write to the same resource without releasing the bus between the two operations Each one of the Universe II slave images can be programmed to map RMW cycles to the PCI Locked cycles RWM cycles are not supported with the unaligned or D24 Cycles In order to support the VMEbus broadcast capability Universe II has four Location Monitors The location monitor s image consist of a 4Kbyte image in A32 A24 or A16 space on the VMEbus If the Location Monitor is enabled an access to a Loca tion Monitor would cause the PCI Master Interface to issue an interrupt The Universe II supports the VMEbus lock commands as they are described in the VMEO4 Specification The ADOH cycles are used to execute the lock command with a special AM code A locked resource can not be accessed by any other resource as long as the VMEbus master has the bus ownership If Target Abort or Master Abort occurs during a locked transaction on the PCI bus the Universe II will relinquish its lock on the bus in accordance with the PCI Specificati
79. are Temperature Sensor 2 6 Themis Computer 2 System Overview and Specifications Environmental Specification 2 7 Environmental Specification Table 2 5 TPPC64 Operating Environmental Specifications Description Minimum Value Maximum Value Temperature Range 5 C 50 C Humidity Range 0 0 relative non condensing at 104 40 075 99 Altitude Range 0 feet Sea Level 10 000 feet 3 048 meters non condensing environment must be maintained at all times Themis recommends that the board be tional powered on and temperature stabilized before and during humidity testing Table 2 6 64 Airflow Requirements Airflow Required slot Maximum Inlet Temperature Altitude 15 93 CFM 50 Sea Level 23 13 CFM 50 10 000 feet 11 14 CFM 40 Sea Level 16 18 CFM 40 10 000 feet Table 2 7 64 Non operating Environmental Specifications Description Minimum Value Maximum Value Temperature Range 40 85 Humidity Range E relative non condensing at 104 F 40 C ee noue Altitude Range 0 feet 0 meters 38 370 feet 12 000 meters a Board must be non operational until such time as the environment can be assured to be non condensing and any or all condensation has been evaporated 2 7 Themis Computer TPPC64 Hardware Manual 2 8 2
80. attery pins are free of the battery socket see B in Figure 1 8 Discard the old battery in a suitable manner Themis Computer 1 Installation and Operation TOD NVRAM Battery Replacement Caution When prying the lithium battery from its socket be careful not to score or break traces on the PCB surface Battery holder screw Pin 1 indicator square pad pin socket Remove phillips head screw securing the battery holder Carefully pry battery long sides upward with special lift tool or long nose pliers exposing the 4 pin battery socket Figure 1 8 TOD NVRAM Battery Replacement 4 Position the new replacement battery over the empty socket so that the 1 indicator key on the battery is aligned with the pin 1 indicator on the PCB see C in Figure 1 8 Carefully push the battery into the socket when the four bat tery pins have engaged the socket holes until the battery is fully seated 5 Replace the battery holder and the phillips head screw previously removed and secure it to the TPPC64 CPU 0 Baseboard 1 15 Themis Computer TPPC64 Hardware Manual 1 16 Themis Computer General Section Chapter System Overview and Specifications This chapter gives an overview of the major board components of the TPPC64 along with a block diagram of the system Also included are system and environ mental specifications as well as estimated power requirements
81. both directions Programmable DMA controller with linked list support A broad range of VMEbus address and data transfer modes A32 A24 A16 master and slave transfer except for A64 and A40 D64 D32 D16 master and slave transfer except for MD32 MBLT BLT ADOH RMW LOCK and location monitors Support for full VMEbus System Controller Nine user programmable slave images on the VMEbus and the PCI bus ports Seven interrupt lines Auto initialization for the slave only applications Programmable registers from both the VMEbus and the PCI bus 4 1 Themis Computer TPPC64 Hardware Manual e Support for four mailbox registers Support for four location monitors e Support for eight semaphores Support for RMW Read Modify Write cycles and lock cycles This chapter is intended to outline the VMEbus to PCI Bus interface on the TPPC64 If more detailed information is need please refer to the Tundra Universe II User 5 Manual Spring 1998 Note Allregisters on the Universe II are little endian 4 2 4 2 4 2 1 4 2 2 VMEbus Interface VMEbus Configuration The following lists the initial configuration of the VMEbus system VMEbus First Slot Detector Two methods of Auto Slot ID Register Access at the power up Universe ll as the VMEbus Slave The Universe VMEbus Slave Channel supports all of the addressing and data transfer modes which are documented in the VME64 specificatio
82. c bus interface of the PPC970FX 0 PE Open Disable the elastic bus interface of the PPC970FX 0 Short 1 2 The reset button Front Panel is connected as the system reset Short 2 3 The reset button Front Panel is connected as the Service Processor reset only Short CPU 1 board is connected to the JTAG scan test of the system ui Open CPU 1 board is disconnected from the JTAG scan test of the system Short 1 2 CPU 0 JTAG scan data input is from the Northbridge CPC925 JTAG data output ics Short 2 3 CPU 0 JTAG scan data input is from the RISCwatch connector Short Enable 0 halt when Northbridge CPC925 CHKSTOP is asserted dt Open Disable 0 halt when Northbridge CPC925 CHKSTOP is asserted Short Disable the POR debug mode of the TPPC64 PPC970FX 0 Enable the POR debug mode of the 64 PPC970FX 0 a Boldface the default solder bead position b Note that serial ports A and B have full modem support when accessed from the front panel but only minimal signalling Tx Rx and GND from the P2 Paddle Board default setting B 8 Themis Computer B Jumper Pin and Solder Bead Configurations Factory Configurable Solder Beads Legend Thick bar Pad 1 z Solder short O pads2 amp 3 P 2 Irt i ag a
83. ce XMC Modules not supported b New 2P2 PMC XMC Carrier Board P N 112794 002 only the standard version 2P2 PMC Carrier Board is not compatible c The standard version 2P3 PMC Carrier Board is supported Themis Computer How to Use This Manual Intended Audience This manual is written for system integrators and programmers It contains all neces sary information for installation and configuration of the TPPC64 and assumes the Service Processor and PIBS program code 15 installed in the system Flash memory If you intend to operate the TPPC64 with an operating system other than Yellow Dog Linux 4 0 such as VxWorks or some other real time kernel please consult the appropriate documentation supplements accompanying your OS or kernel software Although all specific hardware and software features are described in the Hardware and Software manuals programmers wishing to write code for the TPPC64 without the benefit of an operating system or real time kernel will require additional data sheets Please refer to the section Related References on page xix for information concerning this documentation The reader should have a working knowledge of VME64 bus and PCI local bus specifications 64 bit processor architecture and gigabit Ethernet and Ultra320 SCSI specifications Unpacking Caution The TPPC64 contains statically sensitive components Industry standard antistatic measures must be observe
84. d a receiver serial to parallel converter each clocked separately Virtual Address An address produced by a processor that maps all system wide program visible memory Virtual addresses usually are translated by a combi nation of hardware and software to physical addresses which can be used to access physical memory Versa Module Europe is a standard for chassis rack based industrial computer systems based on 32 or 64 bit system architectures Write Cycle A VMEbus cycle used to transfer 1 2 3 4 or 8 bytes from a Master to a Slave XMC Switched Mezzanine Card E 5 Themis Computer TPPC64 Hardware Manual E 6 Themis Computer Appendix VME Slot Configurations The following foldout see Figure F 1 on page F 3 illustrates the slot configurations of all available models of the 64 see Table F 1 including the 2 2 PMC XMC Carrier Board and the 2P3 PMC Carrier Board Table F 1 TPPC64 Model Configurations BASSE 6 PMC XMC 2P3 PMC arrier Board Carrier Board bmw 12 2 VME Slot2or3 64 1 1 Yes TPPC64 2P2 1 Yes Slot 2 64 2P3 1 Yes Slot 2 64 1 2 Yes Yes TPPC64 2P2 2 Yes Yes Slot 3 64 2P3 2 Yes Yes Slot 3 1 The 64 does not support PCI Express hence XMC Modules are not supported 2 New 2P2 PMC XMC Carrier Board P N 112794 002 only the standa
85. d when removing the TPPC64 from its shipping container and during any subsequent handling A wrist strap provides grounding for static electricity between your body and the chassis of the system unit Remove the TPPC64 and accessories from the shipping container and check the con tents against the packing list Be certain to observe industry standard ESD protection procedures when handling static sensitive components The package should include all elements of your order Remove all TPPC64 boards from their antistatic wrapping and verify the ordered configuration Please report any shipping discrepancies to the Themis Computer Customer Support group immediately support themis com or 1 510 252 0870 Themis Computer TPPC64 Hardware Manual xviii How to Start Quickly To start making the TPPC64 operational quickly Themis Computer recommends that you read the following sections Chapter 1 Installation and Operation This chapter contains vital information on configuring the TPPC64 and the design and setup of VMEbus based sys tems Appendix B Jumper Pin and Solder Bead Configurations This appendix contains a complete listing of all jumper pins and solder beads along with all default settings Verify that the jumpers and beads on your system are set to meet your application requirements In addition to information contained in this TPPC64 Hardware Manual P N 112106 022 the TPPC64 Software Manual P N 112106 02
86. ds and two types of PMC Carrier Boards one with two PMC module slots 2P2 and one with three PMC module slots 2P3 Table 1 1 TPPC64 Model Configurations Baseboard 2P2 PMC XMC 2P3 PMC Carrier Board Carrier Board ved CPU 0 CPU 1 Slot 1 Slot 2 VME Slot 2 or 3 VME Slot 2 or 3 64 1 1 Yes 64 2P2 1 Yes Slot 2 64 2P3 1 Yes Slot 2 64 1 2 Yes Yes 64 2P2 2 Yes Yes Slot 3 64 2P3 2 Yes Yes Slot 3 a The 64 does not support PCI Express hence XMC Modules not supported b New 2P2 PMC XMC Carrier Board P N 112794 002 only the standard version 2P2 PMC Carrier Board is not compatible c The standard version 2P3 PMC Carrier Board is supported 1 1 Themis Computer TPPC64 Hardware Manual Caution new 2P2 PMC XMC Carrier Board P N 112794 002 has been de signed to operate with the TPPC64 which does not support the original 2P2 PMC Carrier Board DO NOT ATTEMPT to operate the original 2P2 PMC Carrier Board with the TPPC64 To determine your board type check the white sticker located near your Baseboard s VME P2 connector It contains such vital information as board type and revision serial number CPU frequency memory size and L2 cache size To install the TPPC64 a standard P1 P2 J1 J2 VME64 bus backplane 3 row or 5 row connectors is required If the TPPC64 is to be used in a work
87. e Static e VME system failure Master Yellow Static e Master VME access Slave Green Static e Slave VME access the VME Master LED is ON the TPPC64 currently owns the VME bus This does not mean that the TPPC64 is accessing the VME bus however If the TPPC64 is set to VME RwD Release When Done mode it releases VME ownership after each VME cycle This is accomplished by de asserting the signal If the LED is ON setting the TPPC64 to VME Release On Request mode can also mean that the TPPC64 owns the VME bus but is not accessing it Setting the TPPC64 in VME RWD mode increases VME performance since an arbitration phase is not needed for each VME cycle But it can also have a deep impact on others boards in the VME chassis Setting the system to ROR or RWD mode is done through an environment variable A 11 Themis Computer TPPC64 Hardware Manual A 1 5 CPU 0 P2 Paddle Board Figure 7 shows the I O connectors described in the following sections that are mounted on the TPPC64 CPU 0 P2 Paddle Board P N 112115 001 for 5 row 005 3 row The pinout for the 12 volt auxiliary power connector is shown in Figure A 6 connector pin signals are described in Table A 8 page A 13 Power cable P N 111230 001 is used to connect to a 12 volt power source on the VME rack 12V Auxiliary VME 3 Row P2 Connector Connector Power Connector a 5 Row Paddle Board is also available
88. ec tion until the system is totally removed from the rack Caution Removal of the EMI shield and insertion of a spine between mating front panels is a factory procedure and not recommended in the field VME64 Injector Ejector Handle B Triple E Ejector Handle Figure C 1 64 VME64 A and Triple E B Handles Themis Computer C Front Panel I O Connections and LEDs TPPC64 Front Panels vii M Mating Pin cdi installed Figure 2 Placement of Mating Pins on VME64 type Handles 5 2 TPPC64 Front Panels This section contains descriptive graphics of the front panels for each TPPC64 model configuration listed in Table 1 1 page 1 1 in Chapter 1 see Figure C 3 page C 4 through Figure 8 page 9 Note The front panels described on the following pages of this appendix are all shown with VME64 type handles C 3 Themis Computer TPPC64 Hardware Manual C 2 1 Serial Port TTY A Over temperature warning LED Reset Switch Gigabit Ethernet Port c Gigabit Ethernet Port A2 584 SH DI oul On vs STATUS VME STATUS T L OREST azr xz 100 100 1000 System a Lie VME Status LEDs OVER TEMP 64 TPPC64 1 1 CPU 0 Baseboard Only Dual USB Ports A and B version 1 1 SYSTEM STATUS USERA ENABL
89. ed PMC XMC Car rier Board For more information on the TGA 7000 which is a BIOS driven version of the The mis TGA 100 PMC Graphics Card consult the TGA 7000 PMC Graphics Card Installation Guide Themis P N 112874 021 2 4 Paddle and Power Boards Themis Computer provides a Paddle Board P N 112115 001 5 row 00523 row for TPPC64 0 and a Power Board P N 112876 001 5 005 3 row for CPU 1 both boards attach to the rear of the slot occupied by CPU 0 and CPU 1 respectively A description of all I O connectors and their signals for both the Paddle and Power Board is given in Appendix A Connector Pinouts and LED Indicators 2 5 2 4 Backplane Jumper Settings In compliance with the VME Specification the PMC Carrier Board assures the con tinuity between bus grants BG 0 3 IN to BG 0 3 OUT and the interrupt acknowl edge daisy chain IACKIN to IACKOUT Themis Computer 2 System Overview and Specifications System Specification 2 6 System Specification 2 6 1 Processor amp Memory Subsystems Table 2 2 and Table 2 3 contain processor and memory specifications Table 2 2 Processor Specifications Feature Function Specifications Processor IBM 970FX Processor Speed 1 8 GHz Performance 937 SPECint2000 1 8 GHz estimate 1051 SPECfp2000 1 8 GHz estimate Internal L2 Cache 512 KB CPU Bus Interface Elastic 450 MHz 36 bit Table 2 3
90. ed read PREN in VSIx CTL prefetched read enable bit enable PCI64 LD64EN in VSIx CTL enables 64 bit PIC bus trans actions Note For a VMEbus slave image to respond to an incoming cycle the PCI Mas ter Interface must be enabled bit BM in the PCI CSR register Themis Computer 4 11 TPPC64 Hardware Manual 4 12 4 3 2 4 3 2 1 PCI Bus Target Images The Universe II accepts accesses from the PCI bus with specific programmed PCI target images that open windows to the VMEbus and control to the type of access to the VMEbus There are eight 0 7 standard PCI target images and one special PCI target image The special PCI target image may be used for A16 and A24 transac tion freeing the other 8 images for standard A32 transactions PCI Bus Fields Decoding for VMEbus accesses is based on the address and command information produced by a PCI bus master The PCI Target Interface claims a cycle if there is an address match and if the command matches certain criteria The PCI target images are A32 capable only For accesses other than A32 the Spe cial PCI Target Image may be used refer to Section 4 3 2 4 Special PCI Target Image on page 4 14 Of the eight standard PCI target images the first and fifth PCI target images 0 and 4 have a 4 KB resolution PCI target images 1 to 3 and 5 to 7 have a 64 KB resolution Table 4 8 PCI Bus Fields for PCI Bus Target Image Field Register Bit
91. een 25 Table A 20 12V Power Connector Pin 1 A 26 Table B 1 CPU 0 Baseboard Jumper Pin Settings Top 1 B 2 Table B 2 SCSI B Access Through VME P2 Connector eese B 2 Table B 3 CPU 1 Baseboard Jumper Pin Settings Top 1 B 4 Table B 4 Setting CPU 1 PMC Module PCI X Mode Clock Speed B 5 Table B 5 Setting CPU 1 PMC Module PCI Mode Clock Speed B 5 Table B 6 CPU 0 Baseboard Solder Bead Settings Bottom Side B 7 Table B 7 CPU 1 Baseboard Solder Bead Settings Top and Bottom Sides B 10 Table C 1 TPPC64 Front Panel LED Interpretation eee C 11 Table F 1 TPPC64 Model Configurations 1 xiv Themis Computer How to Use This Manual This TPPC64 Hardware Manual describes all of the models see Table 1 page xvi of the Themis TPPC64 board level computer see following photo a high perfor mance system with a VME64bus backplane interface and up to two 970FX PowerPC PPC64 processors operating at 1 8 GHz manual and the associated Software Manual Serious damage can be caused by im Caution Before you begin installation carefully read each of the procedures in this proper handling of this product
92. een Bottom Flashing rate is 30 ms for 5 TRD2 Transmit Receive D2 Link each transmission receive T activity 6 TRD1i Transmit Receive D1 Activity 7 TRD3 Transmit Receive D3 a Both 100 Mb s and 1000 Mb s transmission rates are deter mined by LEDs placed below the dual Gigabit Ethernet RJ45 8 TRD3 Transmit Receive D3 connectors at the bottom of the TPPC64 faceplate Each Ethernet port A1 and A2 is assigned a 100 Mb s LED and a 1000 Mb s LED which turn ON to indicate the speed of the port A 4 Themis Computer A Connector Pinouts and LED Indicators CPU 0 Baseboard A 1 1 4 Ultra320 SCSI Port A e Connector Type Single SCSI Connector 68 Pin 0 8mm pitch e Manufacturer Part Honda Tsushin HDRA E68LFDT SLA e Themis Cable P N 108712 SCSI A is an Ultra320 protocol 320 MB sec port that is mounted directly to the faceplate of the CPU 0 Baseboard Figure A 4 shows the pinout of this connector with connector pin signals described in Table A 4 on page A 6 Note SCSI Port B signals are accessed through the VME P2 backplane connec tor see Figure A 17 page A 22 Symbol SCSI Port A lt 68 le 34 35 E 7 J4 CPU 0 Board Figure A 4 SCSI A Connector Pinout A 5 Themis Computer TPPC64 Hardware Manual A 6 Table A 4 SCSI Port A Connector Pin Signals Pin Sign
93. er to control the type of access to the PCI resources The VMEbus slave images are divided into VMEbus PCI bus and Con trol fields refer to Section 4 3 Slave Image Programming on page 4 9 For the PCI Slave Images the Universe II accepts accesses from the PCI bus with the specific programmed PCI target images Each one of the PCI bus slave images opens a window to the resources on the VMEbus and it allows the user to control the type of access to the VMEbus resources The PCI bus slave images are divided into VMEbus PCI bus and control fields There is one special PCI target image which is separate from the VMEbus PCI bus and the control fields refer to Section 4 3 Slave Image Programming on page 4 9 DMA Controller The Universe II utilizes an internal DMA controller for high performance data trans fer between the VMEbus and the PCI bus Universe parameters for the DMA transfer are software configurable DMA operations between the source and destina tion bus are decoupled via the use of a single bidirectional FIFO DMAFIFO There are two modes of operation for the DMA Linked List Mode and Direct Mode In Linked List Mode the Universe II loads the DMA registers from PCI memory and executes the transfers described by these registers In the direct mode the PCI master directly programs the DMA registers The DMA controller also utilizes the command packet A command packet is a block of DMA registers stored in PCI
94. erneath on bottom side PMC Module N 501000007 1802 5V key only 79 o gj 00000000060000 0000000000 10000000 2702 Secondary PCI to PCI Bridge Intel 2 1154 ADR JL Y 1 220 000000000000000000000 PMC Module N VME P2 O000000000 TE voor 82 11 DUUM 3 3V key 5V key Component Side PMC Module Voltage Key PMC Module Outline Figure D 4 2P3 PMC Carrier Board Component Connector Diagram Themis Computer TPPC64 Hardware Manual D 6 Themis Computer Appendix Glossary The terminology used in this manual generally follows industry conventions The following list defines the specific meanings of words and terms that may be used in this manual APB Advanced PCI Bridge Arbitration The process of assigning a resource to one of several requestors ASI An acronym for Address Space Identifier BIOS Basic Input Output System or Basic Integrated Operating System BIOS
95. ext are included in this document for the reasons described Note A note provides additional information concerning the procedure or action being described that may be helpful in carrying out the procedure or action operator or equipment damage This may involve but is not restricted to heavy equipment or sharp objects To reduce the risk follow the instructions accompany ing this symbol Caution A caution describes a procedure or action that may result in injury to the Warning A warning describes a procedure or action that may cause injury to the operator or equipment as a result of hazardous voltages To reduce the risk of elec trical shock and danger follow the instructions accompanying this symbol Sidebar sidebar adds detail to the section within which it is placed but is not absolutely vital to the description or procedure of the section Website Information Themis Computer corporate and product information may be accessed on the World Wide Web by browsing the website http www themis com The Sales amp Marketing Department may be reached at info themis com Themis Computer How to Use This Manual Product Warranty and Registration Please review the Themis Computer warranty and complete the product registration card delivered with your TPPC64 board s Return of the registration card is not required to activate your product warranty but by registering your TPPC64 Themis Co
96. f LSI Logic Corporation other trademarks or registered trademarks used in this publication are the property of their respective owners Themis Customer Support North America South America and Pacific Rim Telephone 510 252 0870 Fax 510 490 5529 E mail support themis com Web Site http www themis com 64 Hardware Manual Version 1 1 January 2007 Part Number 112106 022 TPPC64 Hardware Manual Version Revision History Version T 15 caecis a eR cba ua January 2007 Revised Figure 7 page 1 Appendix A to clarify relative positioning of USB ports D E and F on the CPU 0 P2 Paddle Board Ports C D are below ports E F port C is to the right of port D port E is to the right of port F Corrected Section A 1 5 7 USB Ports C D and E F Appendix A including Figure 15 to indicate that USB ports C D are below ports E F on the CPU 0 P2 Paddle Board and that port C is to the right of port D and port E is to the right of port F Version December 2006 iii Themis Computer TPPC64 Hardware Manual iv Themis Computer Table of Contents How to Use This Manual ete Pe rea terrae eh Ue ads AERE 1 Installation and Operation ad Ee Doi Oe ab dept 1 1 Li Determine Board Type 1 1 12 Check 1 2 1 3 Install the TPPC64 0 Paddle Board sese 1 3
97. f the four bits specifies a data width for the corresponding 16 MB regions The lower or 23 20 der bits correspond to the lower order address regions 0 16 bit 1 32 bit 19 16 Reserved PGM 3 0 R W 0 Program Data AM Code Each of the four bits specifies Program Data AM code for the 15 12 corresponding 16 mB region The lower order bits correspond to the lower order address regions 0 Data 1 Program SUPER R W 0 Supervisor User AM Code 5 0 Each of the four bits specifies Supervisor User AM code for the 11 8 corresponding 16 MB region Lower order bits correspond to the lower address regions 0 Non Privileged 1 Supervisor 07 02 BS 5 0 R W 0 Base Address Specifies a 64 MB aligned base address for this 64 MB image 01 Reserved 4 15 Themis Computer TPPC64 Hardware Manual Table 4 13 Special PCI Target Image Register Offset 188 Continued Bits Name Type t Description ae LAS R W 0 PCI Bus Address Space 0 PCI Bus Memory Space 1 PCI Bus Space 0 400 0000 64 16 BASE O0x3FF 0000 1 16 MB 3 24 BASE 0x300 0000 A16 BASE 0x2FF 0000 2 24 0 200 0000 64 MB A16 BASE 0x1FF 0000 1 A24 BASE 0x100 0000 Al6 BASE 0x0FF 0000 0 A24 BASE 0x000 0000 4 16 Figure 4 4 Memory Mapping in the Special PCI Target Image Themis Computer 4 Universe Description
98. formation on specific I O devices Also refer to Ap pendix A Connector Pinouts and LED Indicators and Appendix C Front Panel I O Connections and LEDs Table 1 2 64 Peripheral Devices CPU 0 Peripheral Access E Rp VME P2 Paddle Board 5 Row 3 Row USB A USB B USBO USB1 Yes No USB C USB D USBE E es USB2 USB3 USB4 USB F USB5 No Yes No Serial Port RS232 Serial Port B RS232 Yes 5 02 shorted e If no VME P2 connection Yes 5 02 open f no Front Panel connection Yes SCSI Port A Ultra320 68 pin e LVD No SCSI Port B Ultra320 68 pins Sub D No ies Tos LVD or SE SE only Gigabit Ethernet Port A1 and Port A2 Yes No dual RJ45 Ethernet 10 100Base T RJ45 Yes Yes No Stereo Audio In Stereo Audio Out No Mos No e AC97 GPIO Header 6 pins in line N Yes Yes Total of four I O signals GPIOO 1 2 3 GPIOO amp 1 only Header 6 pins in line No Yes No 12 volt Auxiliary Connector 6 pins Yes Installed on both CPU 0 Paddle No Required for CPU 0 operation Board and CPU 1 Power Board For CPU 1 use Power Board instead a Serial Port A is used for the PIBS Linux console and serial Port B for the SPU Service Processor Unit console 1 9 Themis Computer TPPC64 Hardware Manual 1 10 1 6 1 1 6 1 1 1 6 1 2 1 6 2 1 6 2 1 Serial Port A and Port B TTYA
99. gram Themis Computer D Board Diagrams LEDs OVER TEMP POWER OK PMC Module o amp o o o G v o ze 20 8 o o 5 9 e R RES 222 9 HE 5 oo s 825 gos imm gE o 8 R4888 o7 BB s 858 oo LE S 5 Fg E He TR AS BERERE r REESS 7 757 NI 30VN pJpog Ifd2 v92dd 00 01211 ASSY 9002 5 1HOINUAdOO e EN YaLNdWOd SIN3HL Top Side CPU Debugger RISCwatch Connector IBM 970FX PowerPC CPU 1 Bridge Pericom PI7C21P100NH 2P2 2P3 PMC Carrier Boards C11905 CPU Heat Sink 3 3V key PMC Module Voltage Key e 92012 B VME P1 PMC Carrier Board Riser Connector CPU Heat Sink Mounting Hole 1 of 6 PMC Module Mounting Hole 1 of 4 VME P2 PCB to Module Co
100. heir location Appendix C Front Panel Connections and LEDs illustrates front panels for all configurations of the TPPC64 Appendix D Board Diagrams provides board diagrams of the TPPC64 Appendix E Glossary lists the general definition of terms and abbreviations used in this manual Appendix F VME Slot Configurations illustrates the slot configurations of all models of the TPPC64 Related References The following is a list of related references TPPC64 Software Manual P N 112106 023 PMC XMC Carrier Board Manual P N 112826 020 PCI Local Bus Specification Revision 3 0 PCI Special Interest Group Port land American National Standard for VME64 ANSI VITA 1 1994 also 4 ANSI VITA 1 1 1997 PCI System Architecture by Shanley and Anderson MindShare Press Integrated Circuit Specifications IBM PowerPC 970FX RISC Microprocessor User s Manual Version 1 6 December 19 2005 PowerPC 970FX RISC Microprocessor Data Sheet Preliminary Electri cal Information SA14 2760 07 Version 2 3 June 4 2006 Preliminary e Universe II User VME to PCI Bus Bridge User Manual Tundra November 2002 Part No 8043010 001 03 Other documents regarding specific products are available from their respective ven dors xix Themis Computer TPPC64 Hardware Manual XX Notes Cautions Warnings and Sidebars The following icons and formatted t
101. hort 808 Open Short SB10 Open Short SB11 Open Manufacturing use only Short SB12 Open Short SB13 Open Short SB14 Open Short SB15 Open a Shaded listings indicate that the solder bead set is located on the bottom side of the b Boldface the default solder bead position B 3 3 PMC XMC Carrier Board Solder Beads For more detailed information on Themis PMC XMC Carrier Boards including sol der beads refer to the PMC XMC Carrier Board Manual Themis P N 112826 020 B 10 Themis Computer Appendix Front Panel I O Connections and LEDs C 1 Introduction This appendix contains diagrams of all front panels faceplates for each possible model configuration of the TPPC64 It is intended as a reference to the I O and mon itoring functions of the model being described See Table 1 1 page 1 1 in Chapter 1 Installation and Operation for a list of TPPC64 models PMC Module slot number To avoid confusion each front panel illustration in Ap Caution The PCI address of a PMC Module is not necessarily the same as the pendix C has a table correlating PCI address with PMC Module slot C 1 1 Front Panel Dimensions single slot front panels measure 264 mm 10 4 high by 20 32 mm 0 8 wide Double slot front panels are 264 mm 10 4 high by 40 64 mm 1 6 wide C 1 2 Injector Ejector Handles Two types of injector ejector handles can be ordered see Fig
102. icating flexibility of choice with no implied preference MHz Megahertz millions of cycles per second 106 cps unit of frequency Media Independent Interface or N A Not Applicable NC or N C No Connection PCB Printed Circuit Board PCI Peripheral Component Interconnect bus A 32 or 64 bit bus with multi plexed address and data lines as specified in the PCI Local Bus Specification Revision 2 1 June 1 1995 PHY Physical transceiver or sublayer Physical Address An address that maps to real physical memory or I O device space PIBS PowerPC Initialization and Boot Software PIBS similar to BIOS initializes the TPPC64 system and provides the functions to manage it PLD Programmable Logic Device PLL Phase Locked Loop A feedback control system that automatically adjusts the phase of a locally generated signal to match the phase of an input signal PMC PCI Mezzanine Card POR Power On Reset Probing A process implemented in the firmware and software to identify onboard hardware devices and add on cards on the PCI bus The probing process cre ates the device tree RO An abbreviation used to indicate Read Zero When software attempts to read an RO area zero will be returned Writes to RO are not permitted E 3 Themis Computer TPPC64 Hardware Manual E 4 RC RCK Receiver clock input external Read Cycle A VMEbus cycle used to transfer 1 2 3 4 or 8 bytes from a S
103. ich also contains details on custom software the Service Processor and PIBS for example that enable software programmers to effectively use the powerful features of the VMEbus 64 bit interface Service Processor commands are necessary to initialize configure and control the TPPC64 system PIBS PowerPC Initialization and Boot Software initializes the processor memory subsystem and other components found on the board and is responsible for loading the primary operating system Themis Computer TPPC64 Hardware Manual 1 8 TOD NVRAM Battery Replacement The Time of Day TOD clock and Non Volatile RAM are supplied by a lithium battery to operate the TOD clock and maintain the contents of the NVRAM during a power shutdown Located directly on the top side of the PCB and accessi ble through a hole in the heat sink see Figure 1 7 the battery provides power backup for up to 10 years In the event the battery must be replaced follow these steps 1 Locate the lithium battery on the top side of the TPPC64 CPU 0 Baseboard see Figure 1 7 Battery holder Pin 1 indicator key dot 4 pin keyed TOD NVRAM Lithium Battery Figure 1 7 Location of the TOD NVRAM Battery 2 Remove the phillips head screw securing the battery holder to the board see A in Figure 1 8 on page 1 15 3 With a special lift tool or long nose pliers carefully pry the long sides of the battery back and forth and upward until the four b
104. ified page 2 24 and Auto ID A Proprietary Tundra Method on page 2 25 of the Universe II Manual for more information Register Access at Power Up Register access at power up is used in a system where either the Universe II is inde pendent of the local CPU or a CPU is not present Since the Universe II and the IBM PPC970FX are present on the TPPC64 register access at power up is not supported Themis Computer 4 Universe Description VMEbus Interface 4 2 5 Universe Il s Hardware Power Up Options The Universe II power up options are determined right after the PWRRST based the level of VMEbus Address VA 31 1 and VMEbus Data VD 31 27 See Table 4 2 for the Universe power up options on the TPPC64 The Universe II is automatically configured at power up to operate in the default configuration listed in Table 4 2 It should be noted that all power up options are latched only at the positive edge of PWRRST they are loaded when SYSRST PWRRST and RST are negated Table 4 2 Universe 11 Power Up Options Option Register Field Default Pins EN Disabled VA 31 VRAI CTL VMEbus Register Access VAS M6 VA 30 29 Slave Image VRAI BS BS 0x00 VA 28 21 VMEbus CRICSR Slave VCSR LAS O Memory VA 20 Image VCSR TO TO 0x00 VA 19 15 MISC STAT DY4AUTO Disabled VD 30 MISC_CTL V64AUTO Disabled Auto ID VINT EN SW INT 0 VD 29 VINT STAT SW INT 0
105. ition means the jumper is installed shorting the pins and completing the circuit OFF means there is no jumper installed hence the path between the pins is open breaking the circuit Figure 1 on page B 3 provides the location of the various jumpers on the TPPC64 0 Baseboard In Figure B 1 jumper pin 1 is identified with a square and a triangle Table B 1 CPU 0 Baseboard Jumper Pin Settings Top Side Jumper Jumper Pins Position Description Force SCSI B into single ended SE mode when a 3 row VME backplane is JP2 used and connect SCSI B to VME P2 see Table B 2 OFF Allow autosense mode to determine if SCSI B bus is SE or LVD mode The TPPC64 0 board be affected by a reset SYSRST on the ON VMEbus JP3 The TPPC64 0 board cannot be affected by a reset SYSRST on the OFF VMEbus ON The TPPC64 CPU 0 board cannot assert a reset SYSRST on the VMEbus JP4 OFF The TPPC64 0 board may assert a reset SYSRST on the VMEbus The 64 board is forced to be the system controller SYSCON on the ON JP5 VMEbus OFF Autosensing is enabled to determine the VMEbus system controller a Boldface the default jumper position b When the TPPC64 is accessed through a 3 row VME backplane only SE mode is supported and a jumper must be installed on JP2 If there are one or more SE mode SCSI devices present on the SCSI bus the entire bus will run in SE
106. iverse II contains four 32 bit mailbox registers that provide an additional commu nication path between the PCI bus and the VMEbus The mailboxes support read and write accesses from either bus The mailboxes may be enabled to generate interrupts on either bus whenever written to The mailboxes are accessed from the same address spaces and in the same method as other Universe II registers Universe Il s Semaphores The Universe II contains two general purpose semaphore registers such as SEMAO each register contains four semaphores To obtain the ownership of a 4 17 Themis Computer TPPC64 Hardware Manual 4 18 4 4 5 4 4 6 semaphore a processor writes a logic one to the semaphore bit and an unique pattern to the associated tag field if a subsequent read of the tag field returns the same pat tern then the processor has gained the ownership of the semaphore In order to release the semaphore the processor writes a value of 0 to it Programmable Slave Images on the VME amp PCI bus There are two types of accesses that the Universe II recognizes on its bus interfaces accesses for its own register space and accesses destined elsewhere For the VME Slave Images the Universe II accepts accesses from the VMEbus within specific programmed slave images Each one of the VMEbus slave images opens a window to the resources on the PCI bus and through the specific attributes the VMEbus slave images allow the us
107. l Base T Ethernet AMD 8131 133 MHz 64 bit Ethernet A2 66 MHz 64 bit Intel 82546 HyperTransport Uitras20 Ultra320 SCSI PCI Extension 200 MHz 8 bit co LSI Logic Ultrax20 9091 1 53C1030 B B USBO usB1 B PCI Bridge USB C D E F USB2 3 A 5 Geom Universe Southbridge PCI VME 33 MHz 32 bit AMD 8111 Bridge MII 10 100 Ethernet B AC97 Audio In Out VME64 Bus Backplane Mictor Connector LPC Bus PCI Extension To 2P2 PMC XMC Carrier Board LPC n J Boot Flash y o 8 MBytes PC87417 Solder bead switched between VME P2 and PCI extension Solder bead switched between Front Panel and VME P2 Paddle Board DC to DC Converters MII Media Independent Interface TTY A and B are switched simultaneously Figure 2 1 TPPC64 CPU 0 CPU 1 Baseboard Block Diagram Themis Computer 2 System Overview and Specifications 2 1 1 CPU 0 and CPU 1 Baseboards The local I O subsystem is based on PCI and PCI X busses with separate channels provided for functions and external VME64bus P2 backplane access A list of peripheral devices and voltage sources that are supported by the TPPC64 system is given in Table 1 2 page 1 9 Chapter 1 Installation and Operation SPU CPU Duality A remarkable feature of the TPPC64 is the duality that exists between the SPU Ser
108. l the bit is set VMEbus Fields Before the Universe II responds to a VMEbus Master other than itself the address must lie between the base and bound addresses Also the address modified must match modifier specified by the address space access mode and type fields A description of the VMEbus fields for VMEbus Slave Images in presented in Table 4 5 page 4 9 The Universe II s eight VMEbus slave images 0 7 are bounded by A32 space Slave images 0 and 4 have 4 KB resolution Typically these images would be used as an A16 image since they provided the finest granularity Slave images 1 to 3 and 5 to 7 have a 64 KB resolution The maximum image size is 4 GB Table 4 5 VMEbus Fields for VMEbus Slave Image Field Register Bits Description base BS 31 12 or BS 31 16 in BS Multiples of 4 or 64 KBytes bound base to bound maximum of 4 BD 31 12 or BD 31 16 in 5 BD GB 4 9 Themis Computer TPPC64 Hardware Manual Table 4 5 VMEbus Fields for VMEbus Slave Image Continued Field Register Bits Description address space VAS in VSIx CTL A16 A24 A32 User 1 User 2 mode SUPER in VSlx Supervisor and or non privi leged type PGm in VSIx CTL Program and or data address space for the Universe II s control and status registers and must not overlap Warning The address space of a VMEbus slave image must not overlap with the
109. lave to a master Read Modify Write Cycle A VMEbus cycle used to read from and then write to a Slave location without permitting any other Master to access that location during that cycle RI Ring indicator ring tone detected DCE to DTE RIC Reset Interrupt Clock RMW Read Modify Write RTS Ready request to send DTE to DCE RXD or RD Receive data DCE to DTE SCSI Small Computer System Interface SCTS Secondary clear to send DCE to DTE SDCD Secondary data carrier detected tone from a modem DCE to DTE SDRAM Synchronous Dynamic Random Access Memory SE Single Ended as in Single Ended Differential SCSI SG Signal ground SO DIMM Small Outline Dual Inline Memory Module Software A collection of machine readable information instructions data and procedures that enable the computer to perform specific functions Typically stored on electronic media SRTS Secondary ready to send DTE to DCE SRXD Secondary receive data DCE to DTE STXD Secondary transmit data DTE to DCE TSOP Thin Small Outline Package very thin surface mount chip package with gull wing pins on the short sides TSOPs are approximately a third of the thick ness of SOJ chips TXD or TD Transmit data DTE to DCE UART Universal Asynchronous Receiver Transmitter An integrated circuit used Themis Computer E for serial communications that contains a transmitter parallel to serial con verter an
110. le A 14 USB Ports C D E and F Connector Pin Signals Pin USB Signal Description Pin USB Signal Description C1 USB2_PWR Port C Power E1 USB4_PWR Port E Power C2 USB2_D_N Port C Data Negative E2 USB4 D N Port E Data Negative USB2 D P Port C Data Positive USB4 D P Port E Data Positive C4 USB2 GND Port C Ground E4 USB4 GND Port E Ground D1 USB3 Port D Power F1 USB5_PWR Port F Power D2 USB3 D N Port D Data Negative F2 USB5 D N Port F Data Negative D3 USB3 D P Port D Data Positive F3 USB5 D P Port F Data Positive 04 USB3 Port D Ground F4 USB5 GND Port F Ground A 18 Themis Computer A Connector Pinouts and LED Indicators CPU 1 Baseboard A 2 A 2 1 A 2 2 Row C B Bottom Edge of Board We 2 2 1 2 2 2 CPU 1 Baseboard CPU 1 Front Panel Connectors front panel connectors for the TPPC64 are installed on the CPU 0 Baseboard CPU 1 cannot be used by itself if used a CPU 1 Baseboard must always be attached to a CPU 0 Baseboard CPU 1 VME Backplane Connectors The CPU 1 Baseboard is connected to J1 and J2 VME64 bus backplane through 3 row and 3 row P2 VMEO4 connectors These are described in Figure 16 and the following two sections 32 P1 P2 1
111. lower priority than any other PCI target image The 64 MB space is divided into four 4 16 MB spaces that are selected using AD 25 16 For each region the upper 64 KB map to VMEbus 16 space while the remaining portion map to VMEbus A24 space The addressing of this slave image is depicted in Figure 4 2 on page 4 11 Table 4 11 PCI Bus Fields for Special PCI Bus Target Image Field Register Bits Description 64 MB aligned base address pase 85103 for the image address space LAS Places Image in Memory or I O maximum datawidth VDW separately set each region for 16 or 32 bits mode SUPER separately set each region for supervisor or non privileged type PGM Program or data cycle VCT Separately sets each region as program or data Themis Computer 4 Universe Description Slave Image Programming Table 4 12 Control Fields for Special PCI Bus Target Image Field Register Bits Description image enable EN enable bit posted write PWEN posted write enable bit The special PCI target image register is described Table 4 13 Table 4 13 Special PCI Target Image Register Offset 188 2 Reset Bits Name Type State Description 0 EN R W 0 Image Enable 0 Disable 1 Enable 56 PWEN R W 0 Posted Write Enable 0 Disable 1 Enable 29 24 Reserved VDW 3 0 R W 0 VMEbus Maximum Datawidth Each o
112. mory Module Baseboard N m Figure 3 3 Custom Memory Module Topology Side View Memory capacities are offered in 1 GB 2 GB and 4 GB capacities see Table 2 1 page 2 1 TPPC64 memory design includes Error Correction Code ECC A single bit error in a 64 bit word is corrected without loss of a cycle In designing the memory subsystem considerable attention was paid to minimizing overall power consumption The typical active power consumption of a TPPC64 with 2 GB memory module is 95 watts CPU 0 only at 1 8 GHz running Linux and 137 watts both CPU 0 and CPU 1 at 1 8 GHz running Linux A Caution Because of the VME Specification requiring a 0 8 inch interboard sepa ration see Figure 1 3 on page 1 5 between VME slots only one Memory Module can be installed onto a TPPC64 Baseboard stacking is not supported Themis Computer TPPC64 Hardware Manual 3 8 Themis Computer Operation Section Chapter Universe Description 4 1 Features Tundra s Universe II CA91C142 interfaces the local 32 bit PCI bus to the VME bus The following lists some of the Universe features on the TPPC64 33 MHz 32 bit PCI bus interface Fully compliant high performance 64 bit VMEbus interface ntegral FIFOs buffer with multiple transactions from the PCI bus to the VME bus and from the VMEbus to the PCI
113. mportant that the TPPC64 Paddle Board be installed onto the VME64 backplane directly behind the P2 connector of the CPU 0 Baseboard to provide necessary voltage to CPU 0 circuitry Important If aTPPC64 Paddle Board properly connected to a 12 volt auxiliary power source is not attached to the CPU 0 P2 connector of the VME64 backplane the CPU 0 will not receive adequate current for proper operation The TPPC64 Paddle Board see Figure 1 1 is attached to the CPU 0 Baseboard through the VME P2 backplane see Figure 1 2 page 1 4 and Figure 1 3 on page 1 5 allowing access to essential backplane voltage sources as well as signals see Table A 6 page A 10 in Appendix A Connector Pinouts and LED Indica tors that may not be available through the front panel of the Baseboard Board a design can be built to suit your needs Address all questions concerning Note If you need to access VME P2 signals differently from the CPU 0 Paddle Paddle Boards for the TPPC64 to Themis Computer Customer Service Figure 1 1 TPPC64 CPU 0 Paddle Board 1 3 Themis Computer TPPC64 Hardware Manual 4 8 60 12 Test Connector 12 Power Connector Stereo Audio To VME64 In Jack Backplane Stereo Audio lt Out Jack P2 Connector Grounding 10 100 Connector Block Ethernet 2x28 gt E RJ45 e 3 row VME only 3 Hash E 2 um USB Ports E
114. mputer will be better able to provide you with timely information updates and product enhancement notifications Our Customer Support department is committed to providing the best product sup port in the computer industry Customer support is available 8am Spm PST Monday through Friday via telephone fax e mail and our website Themis Customer Support Telephone 1 510 252 0870 Fax 1 510 490 5529 E mail support themis com Website http www themis com In Case Of Difficulties If the TPPC64 does not behave as described or if you encounter difficulties installing or configuring the board please call Themis Computer technical support at 1 510 252 0870 fax your questions to 1 510 490 5529 or e mail to support the mis com You can also contact us via our web site http www themis com Your Comments are Welcome We are interested in improving our documentation and welcome your comments and suggestions You can email your comments to us at docfeedback themis com Please include the document part number 112106 022 in the subject line of your email xxi Themis Computer TPPC64 Hardware Manual xxii Themis Computer Installation Section ee Installation and Operation 1 1 Determine Board Type The Themis TPPC64 computer is available in six 6 models as defined in Table 1 1 All models are based on a combination of four different VME boards the TPPC64 CPU 0 and CPU 1 Baseboar
115. n The Universe II does not support the A64 mode and the modes intended to augment the 3U applica tions i e A40 and MD32 The Universe II becomes a slave when one of its eight programmed slave images or register images are accessed by a VMEbus master It is not implied that the Universe II cannot reflect a cycle on the VMEbus and access itself as it is capable of doing so Depending on the programmed values of the VMEbus slave images the incoming write transaction from the VMEbus may be treated as either posted or coupled refer to Section 4 3 Slave Image Program ming on page 4 9 If the post write operation is selected the data is written to a Posted Write Receive FIFO RXFIFO and the VMEbus master receives the data acknowledgment from the Universe II The Universe II transfers the write data from Themis Computer 4 Universe Description 4 2 3 VMEbus Interface the RXFIFO without the involvement of the initiating VMEbus master refer to Posted Writes on page 2 15 of the Universe II manual for a complete explanation of this operation If the coupled cycle operation is selected the transaction is com pleted on the PCI bus first and the data acknowledgment is sent to the VMEbus master With the coupled cycle the VMEbus is not available to other masters while the PCI bus is executing the transaction Read transactions may either be pre fetched or coupled A pre fetched read is initi ated when enabled by the user
116. n 2 5 System Status LEDs A 7 T TGA 100 PMC Graphics Card 2 4 TGA3D model configurations F TGA 7000 PMC Graphics Card 2 4 Time of Day TOD clock 1 14 TOD 1 14 TOD NVRAM battery 4 TPPC64 configurations 2 Memory Controller 3 2 model configurations xvi 1 1 System I O Bridge 3 2 System Specification 2 5 64 Baseboard Block Diagram 2 2 TPPC64 Front Panels C 3 Index 4 Transpower Tyco 1610005 4 A 4 Tundra Universe II 3 4 4 TXFIFO 4 4 U Ultra320 SCSI A and 1 11 Ultra320 SCSI A port A 5 Ultra320 SCSI Controller 3 5 Ultra320 SCSI Port B A 3 Universe 4 Architectural Diagram 4 4 Automatic Slot Identification 4 6 Hardware Power Up Options 4 7 Interrupt and Interrupt Handler 4 7 Mailbox Registers 4 17 Miscellaneous Control Register 4 5 Power Up Options 4 7 Register Access at Power Up 4 6 Semaphores 4 17 Slave Image Programming 4 9 SYSCON Module 4 5 System Controller 4 6 VME and PCI Interrupters 4 17 VMEbus Interrupt Handling 4 17 VMEbus Master 4 3 Universe II PCI to VME Bridge 3 4 Unpacking the TPPC64 xvii USB Port A 1 11 USB Port B 1 11 USB Port C 1 11 USB Port 1 11 USB Port E 1 11 USB Port 1 11 USB Port Dual A 3 18 USB Ports Connector Pinouts 3 USB Ports Connector Pin Signals 3 USB Ports C D E F 18 USB Ports C D E F Connector Pinouts A 8 USB Ports C D E F Connector Pin Signals A 6 User defined 16 position rotary switch A 27 Themis Computer Index
117. net Al and A2 for 10 100 1000Base T Ethernet interface connections Attach the TPPC64 to a net work through one of these Ethernet ports and verify that there is a proper physical connection If a 2P2 PMC XMC Carrier Board is added to the system a 10 100 1000Base T net work Ethernet B is available through the Front Panel of the 2P2 PMC XMC Car rier Board Ethernet A1 A2 and B may be active simultaneously Themis Computer 1 Installation and Operation Attach Peripheral Cables 1 6 2 2 10 100Base T 1 6 3 1 6 4 1 6 5 1 6 6 A 10 100Base T Ethernet interface is also available through row Z of the VME P2 backplane by using the RJ45 connector of a TPPC64 5 row CPU 0 Paddle Board see Install the TPPC64 CPU 0 Paddle Board on page 1 3 Ultra320 SCSI Port A and Port B The TPPC64 0 supports two Ultra320 SCSI ports SCSI Port LVD is accessed from the CPU 0 Front Panel through a 68 pin connector Attach SCSI cable P N 108712 to SCSI A SCSI Port B is accessed through a CPU 0 Paddle Board attached to the VME P2 connector LVD if using a 5 row Paddle Board SE if using a 3 row Paddle Board Attach SCSI cable P N 108432 to SCSI B It is possible to use both SCSI A and SCSI B connections simultaneously see Fig ure 1 6 on page 1 7 USB A 0 and USB B 1 USB Ports A USBO and USB1 both of which are version 1 1 are located on the Front Panel of TPPC64 CPU 0 see Appendix C Front
118. nnector 1 of 3 Figure D 2 CPU 1 Baseboard Front Panel Component and Connector Diagram D 3 Themis Computer TPPC64 Hardware Manual Note Refer to the checkbox note in Section A 3 1 for important information on XMC connections Flash Memory PMC XMC Module N Ethernet B Audio Out Audio In Rotary Switch Intel JS28F640J3D75 3311902 SIW3HI 928211 ASSY YSN NI 3QVN 2 9002 PCI to Local Bus Bridge 1 Xilinx VME P1 d 25 1 PLX Technology PCI9656 AN33 RN3I RN3O 8932 RN23 8826 ANAT Ter 10 100 1000 Ethernet ares sees Broadcom BCM5703CKHB U38 PCI to PCI Bridge Intel FW21154BE Baseboard amp Graphics Card Mictor Connectors underneath ps etas on bottom side Dual UART Controller EXAR XR16L25511M
119. of the Power Board and the lug ends according to Step 2 page 1 4 To VME64 12 V Power Connector P1 09000 1 4 175 om te al is Top Side 2 2 8 4 640 N z gt 3 585 Figure 1 5 TPPC64 CPU 1 Power Board 1 6 Themis Computer 1 Installation and Operation Terminate SCSI Devices 1 5 Front Panel Terminator Last SCSIA Device Terminate SCSI Devices All SCSI buses must be properly terminated The TPPC64 contains two SCSI buses SCSI Port A on the Front Panel of the Baseboard see Figure 1 6 and Appendix C Front Panel I O Connections and LEDs and SCSI bus B which is accessed through the VME P2 connector from an available connection such as the Multiple Paddle Board see Figure 1 1 on page 1 3 that is attached behind the VME64 backplane see Figure 1 3 on page 1 5 Since both the SCSI A bus and the SCSI B bus end at the TPPC64 the SCSI Controller is always at one end of the bus hence the on board terminator is always enabled P1 Connector SCSI Controller State On State On Terminator Terminator Terminator P2 Connector SCSI A Bus SCSI B Bus Figure 1 6 SCSI Termination Configurations 1 7 Themis Computer
120. on Universe as the VMEbus Master The Universe II becomes the VMEbus master when the VMEbus Master Interface is internally requested by the Interrupt Channel the PCI Bus Target Channel or the DMA channels The Interrupt Channel always has the highest priority over the other two channels and will request the VMEbus Master Interface when it receives an enabled VMEbus interrupt request The PCI Bus Target Channel and the DMA Channel compete for the VMEbus Mas ter Interface and are awarded it in a fair manner There are several methods available for user to configure the relative priority that the DMA channel and the PCI Bus Tar get Channel have over the VMEbus Master Interface The PCI Target Channel requests the VMEbus Master Interface when 4 3 Themis Computer TPPC64 Hardware Manual 4 4 the TXFIFO contains a completed transaction if there is a coupled cycle request The DMA Channel requests the VMEbus Master Interface when the DMAFIFO has 64 bytes available when reading from the VMEbus the DMAFIFO has 64 bytes in its FIFO when writing to the VMEbus the DMA block is complete gt Bi Directional DMA FIFO posted writes p VME Master pre fetch reads Slave coupled read PCI Bus Slave Channel PCI Bus
121. ound 16 AD 60 17 AD 59 18 AD 58 19 AD 57 20 Ground 21 V I O 22 AD 56 23 AD 55 24 AD 54 25 AD 53 26 Ground 27 Ground 28 AD 52 29 AD 51 30 AD 50 31 AD 49 32 Ground 33 Ground 34 AD 48 35 AD 47 36 AD 46 37 AD 45 38 Ground 39 V I O 40 AD 44 41 AD 43 42 AD 42 43 AD 41 44 Ground 45 Ground 46 AD 40 47 AD 39 48 AD 38 49 AD 37 50 Ground 51 Ground 52 AD 36 53 AD 35 54 AD 34 55 AD 33 56 Ground 57 V I O 58 AD 32 59 PCI RSVD 60 PCI RSVD 61 PCI RSVD 62 Ground 63 Ground 64 PCI RSVD Themis Computer A 25 TPPC64 Hardware Manual A 2 4 CPU 1 P2 Power Board The TPPC64 CPU 1 P2 Power Board P N 112876 001 5 row 005 3 row shown in Figure 18 is used only to provide 12 volts through a multi wire cable con nected to 12 volt auxiliary power source on the VME chassis power supply Spe cifically attach the 6 pin male Molex connector end of a 12 volt power cable P N 111230 001 to the P1 connector of the Power Board the two 6 spade lugs at the other end of the cable are then connected as follows Secure the lug from pins 1 2 3 to a 12 volt auxiliary source on the VME chas sis power supply Secure the lug from pins 4 5 6 to a ground source on the VME chassis power supply lt 12 V Power Connector P1 1 aren eee Al 4 175 al Vi2Pl a LEXXI a Top Side g in i 5 a
122. pretation 4 xiii Themis Computer TPPC64 Hardware Manual Table A 4 SCSI Port A Connector Pin Signals oso dbi orte respi A 6 Table A 5 CPU 0 Baseboard VME64 P1 Connector Pin Signals A 8 Table A 6 CPU 0 Baseboard VME64 P2 Connector Pin Signals A 10 Table A 7 Color Interpretation of Front Panel LEDS eee 11 Table 8 12V Power Connector Pin Signals eese A 13 Table A 9 GPIO Connector Pin Signals estie niente ea enne eR se nante ee A 13 Table A 10 Paddle Board Ultra320 SCSI Port B Connector Pin Signals 14 Table A I1 I2C Connector Pin Signals nte rtt cotidie tres iti daret A 15 Table A 12 Ethernet 10 100Base T Connector Pin Signals eese A 16 Table A 13 Paddle Board Serial A and B Connector Pin Signals A 17 Table 14 USB Ports C D E and Connector Pin Signals sss A 18 Table 15 CPU 1 VME64 P1 Connector Pin Signals eere A 20 Table A 16 VME64 P2 Connector Pin Signals 21 Table 17 Slot Connector 11002 Signals 32 bit see A 23 Table A 18 Slot Connector J1003 Signals 32 bit seen 24 Table 19 Slot Connector 11004 Signals 64 bit s
123. ransport Tundra CA91C142 ij 1 0 Bridge VME P1 TTY Port Southbridge TTY Port B _ AMD 8111 3 Service iid ae UMP em Processor Ta and PLD 55 Over Temp LED E 58 Ud ge Es TS ar poo er PMC Carri ie ec 84 E 3hd 7 a arrier sgle I O Bridge LL B Board Reset Button Northbridge HyperTransport amp TGA3D 3D E 8 Tunnel H DoM Riser i k B Jc s Connector CPC925 ERE 8 sites 8 AMD 8131 B d CPU Heat Sink 22 c Raed a 2 Mounting Hole ET mimis amp TE 1 of 10 Ultra320 uds 5 CHE E ci SCSI Port A SDRAM Memory AME H BRE Module Outline B Ethernet 10 100 E Controller Gigabit k Ethernet 1 i s IBM 970FX Mounting Hole 1 Gigabit Dual Ultra160 cr 1 of 5 Gigabit ne Ethernet SCSI Controller Ethernet 2 p Rm controller 4 LSI Logic VME P2 A1 Status To SYM53C1030 LEDs 2 B 1 s ot E d C A2 Status or LEDs 2 E EE E T cage Tazo ign 000 e E ere cuss CI Tete OE Intel 82546GB SCSI Port B is accessed through the VME P2 backplane connector The Memory Module mounts directly onto the CPU heat sink Top Side Ethernet 10 100 is accessed through the VME P2 backplane connector D 2 Figure D 1 CPU 0 Baseboard Front Panel Component and Connector Dia
124. rate ground pins see Table A 11 page A 15 12 volt Auxiliary Power Connector The 6 pin Molex auxiliary power connector located on the top of both the CPU 0 Paddle Board PCB and the CPU 1 Power Board PCB provides 12 volts directly from the VME chassis power supply CPU 0 details have already been given in Step 2 of the section Install the TPPC64 CPU 0 Paddle Board page 1 3 CPU 1 details have already been given in Step 1 of the section Install the TPPC64 CPU 1 Power Board page 1 6 A Caution The CPU 0 Paddle Board must be used to provide 12 volts to CPU 0 for adequate power If CPU 1 is installed the CPU 1 Power Board must be used to pro vide 12 volts to CPU 1 for adequate power DO NOT ATTEMPT to operate either 0 or CPU 1 without providing an adequate 12 volt auxiliary supply Themis Computer 1 Installation and Operation Configure the VME Interface 1 7 Configure the VME Interface Themis has implemented a variable and flexible VMEbus interface using onboard jumper pins and solder beads The TPPC64 is typically re configured when VMEbus boards are added removed or changed in the chassis Board configuration normally involves allocation of the VMEbus master access address interrupts and slave base addresses Consult Appendix B Jumper Pin and Solder Bead Configurations Details on configuring the VME interface are described in the TPPC64 Software Manual Themis P N 112106 023 wh
125. rd version 2P2 PMC Carrier Board is not compatible 3 The standard version 2P3 PMC Carrier Board is supported Themis Computer TPPC64 Hardware Manual J Note All models include the TPPC64 CPU 0 Baseboard signed to operate with the TPPC64 system which does not support the original 2P2 PMC Carrier Board DO NOT ATTEMPT to operate the original version of the 2P2 Carrier Board with the TPPC64 Caution A new 2 2 PMC XMC Carrier Board P N 112794 002 has been de F 2 Themis Computer F VME Slot Configurations 5 2006 U A Model TI TPPC64 2P3 PMC Carrier Board Front Panel P3B 3 PMC slots Slot 3 Type B Model TP P3A 3 PMC slots Slot 2 Type Top View VME Slot 2 or 3 P C Model TP 2P2 PMC XMC Carrier Board Front Panel P2B Audio 2 slots Slot 3 Type P2A Audio 2 slots Slot 2 Type VME Slot 2 or 3 Top View VME Slots PMC Cards Baseboard Front Panel Graphics VO Audio 1 0 m CPU 1 SS CPU 0 VME Slot 1 and 2 Top View Approved PMC Cards supported The TPPC64 does not support PCI Express therefore an XMC Module should not be installed in the 2P2 PMC XMC Carrier Board VME Slot CPU 0 No PMC Card PC64 2P2 1 P2A 2 PMC Cards CPU 0 PC64 2P3 1 P3A 3 PMC Cards CPU 0 1 VMESlots 2 VMESlots 2
126. rier Board PMC Module Interboard Separation Line Figure 1 3 TPPC64 0 Carrier Board and Paddle Board Installed VME64 Backplane VME J2 Connector Memory Board Top View TPPC64 CPU 0 Paddle Board LJ To 12V TPPC64 CPU 1 PMC Module Power Board Auxiliary 2 Power 12V Cable 2P2 PMC XMC Carrier Board de PMC Module Interboard Separation Line Figure 1 4 TPPC64 CPU 0 CPU 1 Carrier Board and Paddle Power Boards 1 5 Themis Computer TPPC64 Hardware Manual 1 4 Install the TPPC64 CPU 1 Power Board Note It is important that the TPPC64 Power Board be installed onto the VME64 backplane directly behind the P2 connector of the CPU 1 Baseboard to provide necessary voltage to CPU 1 circuitry If a Power Board properly connected to a 12 volt auxiliary source is not attached to the CPU 1 P2 connector of the back plane the CPU 1 will not receive adequate power for successful operation VMEO4 backplane To do so may result in damage to both the Power Board and the Warning Do not install the CPU 1 Power Board behind connector of the CPU 1 Baseboard Install only behind the P2 connector 1 As shown in Figure 1 4 on page 1 5 attach the TPPC64 Power Board to the VME P2 backplane connector behind the TPPC64 CPU 1 Baseboard 2 Attach the 6 pin Molex connector of a 12 volt power cable to the connec tor
127. s Description base BS 31 12 or BS 31 16 in LSIx BS Multiples of 4 or 64 KBytes bound base to bound maximum of 4 BD 31 12 or BD 31 16 in LSIx BD GB address space LAS in LSIx CTL Memory or I O A Warning The address space of a PCI bus slave image must not overlap with the address space for the Universe II s control and status registers and must not overlap with any other PCI bus slave image 4 3 2 2 VMEbus Fields The VMEbus fields cause the Universe II to generate the appropriate VMEbus address AM code and cycle type allowing PCI transactions to be mapped to a VMEbus transaction It is possible to use invalid combinations such as block trans fers in A16 space This may cause illegal transactions on the VMEbus accesses beyond the 4 GB limit will wrap around to the low address range Themis Computer 4 Universe Description Slave Image Programming A32 Image Offset 31 12 PCI 31 12 PCI 11 0 Y VME 31 12 VME 11 0 Figure 4 3 Address Translation for PCI Bus to VMEbus Transfers Table 4 9 PCI Bus Fields for PCI Bus Target Image Field Register Bits Description base BS 31 12 or BS 31 16 in LSIx BS MIEL bound BD 31 12 or BD 31 16 in LSIx BD 8 16 32 or 64 bits address space LAS in LSIx CTL A16 A24 A32 User 1 User 2 mode SUPER in LSIx CTL Supervisor or non privileged type PGM in LSI
128. s ES c puc goag r3 e cat cq Bs la g 0 R 628 E m BEES eo n gi VME P2 Fuse 6198 cn n BB i i R235 OO R Go s E To L eni U607 101 40605 31254026 e 0 cao 1 0 non og gt n nge i bod c bor suse mm Ep non angu 0001 E o S 197 237 ceos7cis1 ceosecios T 16199 a2 m Jt Q 4056 4054 4035 Top Side Figure B 1 TPPC64 CPU 0 Baseboard Jumper Pin Locations Top Side Themis Computer TPPC64 Hardware Manual 2 2 CPU 1 Baseboard Jumper Pins The jumper pins on the TPPC64 1 Baseboard are all the top side compo nent side of the PCB Jumper pin default settings are given in Table B 3 with their locations shown in Figure B 2 on page B 6 Table B 3 CPU 1 Baseboard Jumper Pin Settings Top Side Jumper Pins Jumper Position Description Short 1 2 VIO of CPU 1 PMC Module and attached PMC Carrier Board is 3 3V JP1 Short 2 3 VIO of CPU 1 PMC Module and attached PMC Carrier Board is 5V JP2 Mode only JP2 and JP3 are set together see Table 4 page B 5 to define the JP3 PCI X speed of the PMC Module installed in CPU 1 and an attached PMC Carrier Board ON Enable the elastic bus interface of the PPC970FX CPU 1 JP4 OFF Disable the elastic bus interface of the PPC970FX CP
129. s Mailbox d 4 17 444 Universe Ils Semaphores 4 17 4 4 5 Programmable Slave Images on the amp PCI bus 4 18 74 6 DMA Controller past ee ese tn 4 18 Appendix A Connector Pinouts and LED Indicators 1 AT CPU 5 1 1 1 CPU 0 Front Panel Connectors 2 2 1 A 1 1 1 Serial Port 232 and Port 232 1 12 USB Port A and Port A 3 A 1 1 3 Gigabit Ethernet TPE Port Al and Port 2 4 A 1 1 4 Ultra320 SCSI Port 5 A 1 2 0 VME Backplane Connectors esc io ee eee rara Gees ceived 7 A 1 2 1 VME 64 P1 Connector isis en to Inn enenatis 7 A 1 2 2 VME 64 P2 Connector 02 442 4 24525524 enne etant innse 9 31 3 RES 11 Stat s LEDS 11 Alas OPO RP add le aetatum ds A 12 A 1 5 1 Ultra320 SCSI Port B Connector eene A 13 A 1 5 2 GPIO Header Connector eod inr e D Ve pU E PH ORE A 13 1 5 3 I2C Header Connector 5 row P2 only A 15 A 1 5 4 Stereo Audio In Out Connectors 5 row P2 only A 15 A 1
130. se the SYSCON Module of the Universe II is disabled The software can set or clear the SYSCON bit the MISC register of the Universe The definition of the MISC register is provided in Table 4 1 offset of this register is 0x404 Table 4 1 Universe Miscellaneous Control Register MISC Bits Name Description Reser Access State VMEbus Time out R W 0000 Disable 0001 16 us 0010 32 us 0011 31 28 VBTO 64 us 0011 0100 128 us 0101 256 us 0110 512 us 0111 1024 us Others RESERVED 26 VARB VMEbus Arbitration Mode 0 Round Robin 1 Pri 0 R W ority VMEbus Arbitration Time out R W 00 Disable Timer 01 16 us minimum value of 8 25 24 VARRT us due to the 8 us clock granularity 10 256 us 9 others RESERVED 23 SW LST PCI Reset 0 no effect 1 initiate PCI bus LRST 0 W Software VMEbus SYSRESET W 2 0 no effect 1 Initiate VMEbus SYSRST 9 20 BI BI Mode 0 Universe II is Bl mode Power up R W 1 Universe II is not in mode Option Enable Global Bl mode Initiator R W 19 ENGBI 0 Assertion of VIRQ1 ignored 1 Assertion of 0 VIRQ1 puts the Universe Il in Bl mode 18 RESCIND Unused on the Universe II 1 R W SYSCON R W 17 SYSCON 0 Universe ll is not a VMEbus System Controller n 1 Universe is a VMEbus System Contoller Themis Computer TPPC64 Hardware Manual Table 4 1 Universe Miscellaneous Control Register M
131. station configura tion instead of an embedded controller a hard disk and graphics frame buffer or serial terminal will also be required Caution Not all VME64 chassis racks provide a 12 volt power supply that is suf ficient to power the dual board TPPC64 system Before installing the TPPC64 into VME64 backplane make sure that the power supply on your VME rack can pro vide sufficient power output to support your maximum board configuration layout for all voltages Check Configurations When you first receive your TPPC64 confirm that the jumper pin and solder bead configurations are appropriate for your application Appendix B Jumper Pin and Solder Bead Configurations gives a complete listing of jumper pin and solder bead definitions including default settings Solder bead settings are set by Themis at the factory before shipment and should be changed by Themis at the factory only Therefore it is recommended that you advise your Themis sales representative of your application needs at the time of purchase so the proper solder bead settings can be configured Warning Attempting to alter a solder bead configuration could seriously damage the TPPC64 system DO NOT ATTEMPT TO ALTER SOLDER BEAD CONFIG URATIONS Instead contact Themis to change any settings Themis Computer 1 Installation and Operation Install the TPPC64 CPU 0 Paddle Board 1 3 Install the TPPC64 0 Paddle Board Note Itis i
132. tor Pinout eene A 16 Figure 14 Paddle Board Serial A and B Connector Pinouts esses A 17 Figure A 15 USB Ports D E and Connector A 18 Figure A 16 CPU 1 P1 P2 VME Connector Pinouts essere 19 Figure A 17 PMC Card Slot Connector Pinout sese A 22 Figure A 18 TPPC64 CPU 1 Power Board eese nennen enne A 26 Figure A 19 12 Power Connector ene enne nennen ens A 26 Figure A 20 The 2 2 PMC XMC Carrier Board Top and Bottom Views 28 Figure A 21 Memory Module Baseboard Connectors Socket Receptacle amp Plug 29 Figure B 1 64 CPU 0 Baseboard Jumper Pin Locations Top Side B 3 Figure B 2 64 CPU 1 Baseboard Jumper Pin Locations Top Side B 6 Figure 3 TPPC64 0 Baseboard Solder Bead Locations Bottom Side B 9 Figure C 1 TPPC64 VME64 A and Triple E B C 2 Figure C 2 Placement of Mating Pins on VME64 type C 3 Figure C 3 TPPC64 CPU 0 Baseboard C 4 Figure 4 TPPC64 CPU 0 and 2P2 PMC XMC Carrier C 5 Figure C 5 TPPC64 CPU 0 2P3 PMC Carrier Board ssssssssssses C 6
133. tware Manual 3 1 Themis Computer TPPC64 Hardware Manual A 25 3 2 System Bridge and Memory Controller The TPPC64 connects both CPU 0 and CPU 1 processors through CPC925 System I O Bridge Northbridge which also controls access to the on board TPPC64 Memory Module as well as system I O access through the AMD 8131 HyperTransport Tunnel HyperTransport Technology The AMD 8000 HyperTransport core logic chipset series was designed to enhance high speed processors such as IBM 970FX and includes the AMD 8131 HyperTransport PCI X Tunnel and the AMD 8111 HyperTransport I O Hub AMD 8131 HyperTransport PCI X Tunnel The AMD 8131 HyperTransport PCI X Tunnel is a high speed device that provides two independent high performance PCI X bus bridges that are integrated with a high speed HyperTransport technology tunnel Tunnelling provides the capability to connect with other HyperTransport technology devices that are downstream see Figure 3 1 namely the AMD 8111 see next section in the TPPC64 8131 HyperTransport PCI X Tunnel AMD 8111 400MHz Side A Side B 200 MHz HyperTransport Link 4 HyperTransport Link Downstream 16 bits Upstream 4 16 bits Downstream 8 bits Upstream Device PCI X PCI X Bridge A ridge B 8 bits Downstream N IN 5 PCI XBusB Figure 3 1 AMD 8131
134. unnel 3 2 Amp 120521 1 A 22 AMP 787617 4 A 3 A 18 audio 1 11 Auxiliary Functions 2 6 B Backplane Jumper Settings 2 4 Baseboard D Baseboard Front Panel Component and Con nector Diagram D 2 D 3 Baseboard Jumper Locations 3 6 9 Baseboard Jumper Pin Settings B 2 B 4 Baseboard Solder Beads B 7 Baseboard Solder Bead Settings B 7 B 10 Baseboards CPU 0 and CPU 1 3 battery replacement 1 14 Board Diagrams D cables attaching 9 cache 3 Comments are Welcome xxi Configurations 2 connector pinouts connector signals A Console Port TTYA amp TTYB 1 10 Control Fields PCI Bus Target Image 4 4 Special PCI Bus Target Image 4 5 CPU 0 P2 Paddle Board 12 CPU 1 PI P2 VME Connector Pinouts A 9 CPU 1 P2 Power Board A 26 CPU 1 VME64 Connector Pin Signals A 20 CPU 1 VME64 P2 Connector Pin Signals A 27 D Daisy Chain Driver DCD 4 6 DMA Channel 4 3 DMA Controller 4 8 DMAFIFO 4 4 Dual Gigabit Ethernet Controller 3 6 Dual Ultra320 SCSI Controller 3 5 E ECC See Error Correction Code Environmental Specification 2 7 Error Correction Code ECC 3 7 Ethernet 10 100Base T 1 10 Gigabit 1 10 link activity green 3 6 Index 1 Themis Computer TPPC64 Hardware Manual link speed yellow 3 6 Ethernet 10 100Base T Connector A 6 ethernet gigabit 5 6 F Front Panel LED Interpretation 11 LEDs 10 Front Panel Diagrams C Front Panel Connectors CPU 0 A
135. ure C 1 page C 2 e VME64 type handles Elma for example which aid in both the insertion and the extraction of the PC board into and out of the VME backplane connectors Triple E type handles which aid only in the extraction of the PC board from the VME backplane connectors C 1 Themis Computer TPPC64 Hardware Manual C 2 C 1 2 1 C 1 2 2 When a board product such as the TPPC64 is shipped from Themis VME64 type handles will be installed unless the customer specifies a different handle such as the Triple E VME64 type Handles When ordered all Themis board products are shipped with VME64 type handles unless otherwise specified A multiple slot system will be shipped with all handles secured together by a mating pin inserted through two adjacent handles see Figure C 2 on page C 3 This assures that all boards will lock onto and release from the VME rack frame at the same time On those occasions when the customer is upgrading and must add or replace a board in the system it is important to make sure that a mating pin is used to secure two adjacent handles Triple E type Handles When extracting a multiple board system from the VME rack frame it is important to remember that since there is no mating pin to hold handles together each han dle works independently from all other handles hence the operator must extract the system from the rack frame by carefully manipulating each handle in the same dir
136. vice Processor Unit and the CPU Central Processor Unit The SPU is an 8 bit microcontroller that runs its own code with shell commands that access low level hardware on the TPPC64 unavailable by any other means The SPU console is attached to TTYB on the front panel the CPU through PIBS con sole is attached to TTYA on the front panel The SPU is responsible for initializing the TPPC64 chipset then passing con trol over to the CPU The SPU performs environmental monitoring of sensors and passes the information to the CPU over the AMD8111 HyperTransport I O Bridge shared NVRAM which is accessed by both the SPU and CPU In this way the SPU can shut down the CPU if it detects excessively high temperatures If the CPU crashes the SPU can serve as a debug tool to diagnose the system which must still be turned on even though it is essentially dead Consult the TPPC64 Software Manual P N 112106 023 for more detail on SPU and PIBS commands 2 3 Themis Computer TPPC64 Hardware Manual 2 2 PMC XMC Carrier Boards There are two types of Carrier Boards that will operate with the TPPC64 the 2P2 PMC XMC Carrer Board and the 2P3 PMC Carrier Board For detailed informa tion refer to the PM C XMC Carrier Board Manual Themis P N 112826 020 2 3 Graphics Board For graphics support Themis recommends the TGA 7000 PMC Graphics Card which can be installed in a vacant PMC Module slot of an install
137. x CTL Program or data cycle VCT in LSIx Single or Block 4 3 2 3 Control Fields Through the control fields the user specifies how writes are processed and enables a PCI target image The PCI target image is enabled by setting the EN bit Posted writes are performed when the PWEN bit is set and the particular PCI target image is accessed Posted writes are only decoded within PCI Memory space Access from other memory spaces are performed with coupled cycles regardless of the setting of the PWEN bit 4 13 Themis Computer TPPC64 Hardware Manual 4 14 Table 4 10 Control Fields for PCI Bus Target Image Field Register Bits Description image enable EN in LSIx CTL enable bit posted write PWEN in LSIx CTL posted write enable bit Note For a VMEbus slave image to respond to an incoming cycle the PCI Mas ter Interface must be enabled bit BM in the PCI register 4 3 2 4 Special PCI Target Image A special PCI target image is provided to expedite A16 and A24 transactions The other eight standard PCI target images are typically programmed to access A32 space The special PCI target image is a 64 MB space located either within memory or I O space that is decoded using PCI address lines 31 26 Its base address is aligned on 64 MB boundaries and no offsets are provided Therefore PCI address information is mapped directly to the VMEbus The special PCI target image has a

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