Home

(Programmer) AN - Renesas Electronics

1. VDD 5 0V glasses bn 22222422228 74HCT573A cs i z 20 VDD OE voD e m M u ROT ADO a aes PRI A0 wt 4 UI_RXD AD7 ADI 3o co E AL Ha AD6 AD2 EH bata o2 EZ A2 G ADS ADS 5 55 s IS A3 ADS 7 Dt Q4 E TC4050 150 o abs VDD AD6 855 95 3s A6 FP VDD N10 eS D6 06 A733 el 4 x al a s SINTESIS RO AD7 9 12 AT l g 9 sl al al s al EEPEREIESS222225308838333 mab va a 8525 2 e 5 TARSAR jao eH 5 6838588 apa H a E a aps 74 AD3 us Apo 23 AD2 72 ADI ADL ADO K ADO Target I F 5 BVDD az GND 1 2 AS lt 8 8 E En 7415139 iue Ho off x Of 0008 s R82 ASIB O0 B 67 RD S ile 16 s o Ole TASA AAA u one 66 E Nee FP TXD X3 29 8X FPRD MAX232CPE wel es X WR A19 2 Lis FP FLMDO S o Oho lu lu WRO Ada Eb gt o OFS 64 A20 3 11 o O iz ts 70F3313Y CM3 63 25 AA 14 X33 ona Pome HEX a ao 5 1 2316 of 4X C6 a PCMI es Q0a Alb ae xn Pao EX SE 5 Ola CN2 A u a xS xr2 cor 60 XL 02a Gob 2x 17 59 712 LM i Poz co jS X X 03a O1 HX lt 5 P03 P915
2. STX LEN Data 02H 1BH VEN MET MSC DEC1 DEC2 DEC3 UAE 3 DEV 10 Data continued SUM ETK SCF BOT RES 6 Checksum 03H Remarks 1 LEN Data length VEN Vendor code NEC 10H MET Macro extension code MSC Macro function code DEC1 Device extension code 1 DEC2 Device extension code 2 DEC3 Device extension code 3 UAE User flash ROM last address 3 bytes DEV Device name 10 bytes SCF Security flag information BOT Boot block number RES Reserved 6 bytes 2 For the vendor code VEN extension code MET function code MSC device extension code 1 DEC1 device extension code 2 DEC2 and device extension code 3 DEC3 the lower 7 bits are used as data entity and the highest bit is used as an odd parity The following shows an example 40 Application Note U19735EJ1VOAN CHAPTER 3 DESCRIPTION OF COMMAND PROCESSING Table 3 2 Example of Silicon Signature Data uPD78F0588 78K0 KC2 L Field Name Description Example of Silicon Signature Data Actual Value Vendor code NEC 10H 00010000B 10H Added 11011111B DFH Added 01000000B 04H Added 11111110B FEH Added 01111111B 7FH Added Macro extension code DFH Macro function code 04H Device extension code 1 FEH Device extension code 2 7FH Device extension code 3 7FH 01111111B 7FH Added User flash ROM last address FFH 11111111B 007FFFH Not added 01111111B 00000000B 7FH 00H 37H 38H 46H 30H 35H 38H 38H 20
3. 5 Atime out check is performed until data frame version data reception If a time out occurs a time out error C is returned time out time trn1 6 The received data frame version data is checked If data frame is normal Normal completion A If data frame is abnormal Data frame error D 4 12 3 Status at processing completion Status at Processing Completion Status Code Description Normal Normal acknowledgment The command was executed normally and version data was completion A ACK acquired normally Abnormal Checksum error The checksum of the transmitted command frame does not termination B match Negative acknowledgment Command frame data is abnormal such as invalid data length NACK LEN or no ETX Time out error C The status frame or data frame was not received within the specified time Data frame error D The checksum of the data frame received as version data does not match 92 Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE 4 12 4 Flowchart Abnormal termination B Data frame error D i J a Version Get D command processing v Wait from previous frame reception until next command transmission tcom v Command frame transmission processing Version Get Status frame No received No twr12 Time out error C No Data frame version d
4. Boot block number The last block number of the boot cluster that is currently selected 03 Reserved Reserved FFFFFFFFFFFF Note 1 The list of internal flash ROM last addresses is as follows Internal flash ROM 4 KB OFFFH FF1 a FEFO last address 8 KB 1FFFH 16 KB 3FFFH 32 KB 7FFFH Note 2 is on the next page 42 Application Note U19735EJ1VOAN CHAPTER 3 DESCRIPTION OF COMMAND PROCESSING Note 2 The device names are listed below Device name list Generic Name Part Number Actual Value Upper Row Signature Data Lower Row Character Code BNN A NA BEA A E BA PE KEN Pn N o o o o o lslelols s l l ES RE HEC RR EC eo pa PPT oneris a or p poe os p r o 2 a en epos pe ce TE paa pee EC E E prep EO O OS ae E l ESO AE ECCE ROK EO EO EIE KA O O pls ese ees EA EC sq epe Pee A rae EE E epale ole aj TEE Ria C O EZ p e o CIO CO A e E Application Note U19735EJ1VOAN 43 1 2 44 Generic Name 78K0 KC2 L CHAPTER 3 DESCRIPTION OF COMMAND PROCESSING Part Number D78F0581 D78F0582 D78F0583 D78F0586 D78F0587 D78F0588 2 2 Actual Value Upper Row Signature Data Lower Row Character Esc EBENA KEE ENEC EEG CREE EE ES REI ENEXEGENESESESESES AEZ Se Gs PAE a EN freee E Te te AE ENE ES EC MERA Application Note U19735EJ1VOAN CHAPTER 3 DESCRIPTION OF COMMAND PROCESSING 2 78KO Ix
5. anan asanaanenan aana cnn nnnr o rr ran REPRE KK KKK 88 4 11 3 Status at processing completion nennen eno eee anne enana nan 88 4 14 4 Flowchalts sis ian iii rd 89 AAAS Sample progra M torno Ee Dm UB UN PIE 90 4 12 Version Get Command 5 eaaa ana nawa aaa aaa eaaa nada nawa a en aab aa edere e aea Ba ren eaaa 91 A210 Processing sequence ch art uiia cree akak AG eto pros ertt daa ote cet de ee 91 4 12 2 Description of processing sequence ssssssseeeeeneeee menn 92 4 12 3 Status at processing completion sssssssesseeeeeenneenneeen nennen nennen nnne 92 AVIA Flowchart nee een E o aaa 93 4 42 5 Sample program ie a an ag ee he da 94 4 13 CHECKSUM Command 5 555545895 saanane naga naladu ana nepak Decio sone san da enun NG ganas a E gagan aaa aana segane naba 95 4 13 1 Processing sequence chart o arasan aranan a akan Na NG GE dap a aa dh ag gan an apa na a aan ik e NE aga NANG 95 4 13 2 Description of processing seguence sasa esasa anan aa anana cnn nnnr o rr rn rr nera KKK anana KKK KK 96 4 18 3 Status at processing completion ooooinnccincninnocnnccnnccnconnconnncnnnn conan nan cc ran cnn nennen nennen nnne nnns 96 4 13 47 FlOWClIaTL ir dde iet tao RGM a teo dd 97 443 5 Sample program nennen HU ER Re ede e DE e pte edes EET De ce Ie De de P ee de Ue es 98 4 14 Security Set Command aana ena eaaa ea nana nn nana na nana rc 99 4 14 1 Proce
6. HPD78F0741 78F0743 78F0745 78F0751 8 KB 78F0753 78F0755 HPD78F0742 78F0744 78F0746 78F0752 16 KB 78F0754 78F0756 Remark Products under development are included in the above tables Application Note U19735EJ1VOAN 13 CHAPTER 1 FLASH MEMORY PROGRAMMING Figure 1 3 Flash Memory Configuration lt Block number gt lt Address gt lt Flash memory size gt 1 KB i Block 1FH OAEFRH 1KB Block 10H 04000H NENNEN Ts 1KB Block OFH O3FFFH 1 KB Block 08H 02000H 1 KB Block 07H ras 1 KB Block 04H 01000H OOFFFH 1 KB Block 03H 1KB i Block 00H 00000H Remark Each block consists of 1 KB this figure only illustrates some blocks in the flash memory 14 Application Note U19735EJ1VOAN CHAPTER 1 FLASH MEMORY PROGRAMMING 1 4 Command List and Status List The flash memory incorporated in the 78K0 Kx2 L can be rewritten by using the commands listed in Table 1 2 The programmer transmits commands to control these functions to the 78K0 Kx2 L and checks the response status sent from the 78K0 Kx2 L to manipulate the flash memory 1 4 1 Command list The commands used by the programmer and their functions are listed below Command Number Table 1 2 List of Commands Transmitted from Programmer to 78K0 Kx2 L Command Name Chip Erase Block Erase Function Name Function Erases the entire flash memory area Erases a specified area in the flash memory Programming Wri
7. No Status frame received No twr11 Abnormal termination B Data frame silicon signature received No Timed out Normal data frame Data frame error D j Normal completion A fe TTA Application Note U19735EJ1VOAN 89 CHAPTER 4 UART COMMUNICATION MODE 4 11 5 Sample program The following shows a sample program for Silicon Signature command processing JAKA KAKAK KA KAKAK KK KK KK KERR RK ERE EKER ER RR RAR RE KER ERE KAKA KAKAK RARA ko kk RY Get silicon signature command el 755 a AAK KAKAK KA KAKAK KAKAK KA KAKAK KAKAK KAKA KAKA KK KK KA KAKAK RAR ER RAR RR kc kc ko kk J i u8 sig pointer to signature save area Aj r ul6 error code E A AN J ul6 fl ua getsig u8 sig ul6 rc fl wait tCOM wait before sending command put cmd ua FL COM GET SIGNATURE 1 fl cmd prm send GET SIGNATURE command rc get sfrm ua fl ua sfrm tWT11 MAX get status frame switch rc case FLC NO ERR break continue Z case FLC DFTO ERR return rc break case C default return rc break case B j rc get dfrm ua fl rxdata frm tFD2 MAX get status frame if rc if error return rc case D j memcpy sig fl rxdata frm OFS STA PLD fl rxdata frm OFS LEN copy Signature data return rc case A 90 Application Note U19735EJ1VOAN CHAPTER 4 UAR
8. case A case FLC_DFTO_ERR return rc break case C default return rc break case B return rc j Application Note U19735EJ1VOAN 59 CHAPTER 4 UART COMMUNICATION MODE 4 5 Baud Rate Set Command 4 5 1 Processing sequence chart Baud Rate Set command processing sequence Programmer lt 1 gt Wait from previous frame reception tco until next command transmission 78K0 Kx2 L Wait from command frame lt 3 gt transmission until Reset twT10 command transmission The baud rate of UART is switched lt 4 gt to the value set by the Baud Rate Set command lt 5 gt Reset command frame transmission lt 2 gt Baud Rate Set command frame transmission Time out check for status lt 6 gt 5 frame reception Time out occurs Status frame received within specified time oan out C M gulo a lt 7 gt Status frame reception nA Reception status ia N p ACK m PS Other than ACK pam count over N EE Yes No ACK Pe E di Go to lt gt y E e Mo qe ibt opem LP Note Do not exceed the retry count for the reset command transmission up to 16 times 60 Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE 4 5 2 Description of processing sequence lt 1 gt Waits from the previous frame reception until the next command transmission wait time tcom lt 2 gt The Baud Rate
9. low high u16 fl_con_dev void extern void init_fl_uart void extern void init_fl_csi void extern void stop_UARTO void ul6 rc NO_ERROR u8 cnt1 cnt2 SRMKO true disable UART Rx INT UARTEO false disable UART H W stop UARTO TxD RxD Hi Z OE ENABLE TxD output pFL RES low RESET low pmFL FLMDO PM OUT FLMDO Low output pFL FLMDO low pmFL TxD PM OUT TxD Low output pFL TxD low NDD low high FL VDD HI NDD high fl wait t1 wait TOOLC FLMDO TOOLD low gt high pFL_FLMDO hi FLMDO high pFL_TXD hi TOOLD high start_flto t12 start t12 wait timer fl wait t3 wait cnt1 3 while cnt1 cnt1 TOOLC FLMDO output pulse 2 times cnt2 2 while cnt2 cnt2 pFL FLMDO low FLMDO fl wait t4 wait pFL FLMDO hi FLMDO if cnt2 fl wait t5 wait else fl_wait t6 wait j 22 Application Note U19735EJ1VOAN CHAPTER 1 FLASH MEMORY PROGRAMMING TOOLD output pulse 7 times cnt2 7 while cnt2 cnt2 pFL TxD low TOOLD low fl wait t7 walt pFL_TxD hi TOOLD high if cnt2 fl wait t8 wait if cnt1 fl wait t9 wait elsel fl wait t10 wait j if check flto timeout t12 return FLC COM ERR yes j elsel stop fl timer no j RESET low high pFL RES hi RESET high OE DI
10. lt tpr tros tcov The 78K0 Kx2 L can execute the next communication after the MIN time has elapsed after completion of the current communication The programmer needs to transmit the following data within the period from the MIN time to the MAX time after completion of the current communication The MAX time is not specified but use approximately 3 seconds tpr tFD1 1FD2 gt The 78K0 Kx2 L can execute the next communication after the MIN time has elapsed after completion of the current communication The programmer needs to be ready for reception of the following data within the MIN time after completion of the current communication The MAX time is not specified but set the timeout to approximately 3 seconds Application Note U19735EJ1VOAN 105 CHAPTER 5 FLASH MEMORY PROGRAMMING PARAMETER CHARACTERISTICS 5 1 3 Command characteristics Command Condition Reset Note 1 Chip Erase 54 4 6 2 x total number of 883 6 136 1 x total number of blocks ms blocks ms Block Erase 15 2 ms 0 3 190 3 x execution count of simultaneous selection and erasure 139 9 x number of blocks to be erased ms Programming 132 9 ms 723 6 ms Verify Block Blank Check Baud Rate Set Silicon Signature Version Get Security Set 351 3 ms 352 5 ms Checksum Notes 1 Reception must be enabled for the programmer before command frame transmission 2 See 5
11. 28 Application Note U19735EJ1VOAN CHAPTER 2 COMMAND DATA FRAME FORMAT 2 1 Command Frame Transmission Processing For details of the flowchart of processing to transmit command frames read 4 1 Command Frame Transmission Processing Flowchart 2 2 Data Frame Transmission Processing The write data frame user program verify data frame user program and security data frame security flag are transmitted as a data frame For details of the flowchart of processing to transmit data frames read 4 2 Data Frame Transmission Processing Flowchart 2 3 Data Frame Reception Processing The status frame silicon signature data frame version data frame and checksum data frame are received as a data frame For details of the flowchart of processing to receive data frames read 4 3 Data Frame Reception Processing Flowchart Application Note U19735EJ1VOAN 29 CHAPTER 3 DESCRIPTION OF COMMAND PROCESSING 3 1 Reset Command 3 1 1 Description This command is used to check the establishment of communication between the programmer and the 78K0 Kx2 L after the communication mode is set The baud rate must be the same for the programmer and 78K0 Kx2 L Therefore synchronization is checked by executing the Reset command immediately after the serial programming mode transitions to the operating mode The default baud rate for the 78K0 Kx2 L is 125 000 bps 3 1 2 Command frame and status frame Figure 3 1 shows the format of a command frame for
12. aesaaesanewan nesune wane wane ena en anana n ena KARA anana re 13 1 4 Command List and Status List aaeeewnanenenan anana nann nn nan arena 15 1 43 Command list aas beet eit a 15 1 4 2 Status list iic ene eei tinm eee Rte nh 16 1 5 Power Application and Setting Flash Memory Programming Mode 17 1 5 14 UART communication mode 5 aa e a ap d aa a a a ag ak a E Ag a Ga a a senis tnnt enses 18 1 5 2 Mode setting flowchart iocis aa A an ee ed Us BE aaa A ees 19 15 3 Sample program dasah sag a a eaaa aaa ae nge a a E pik an ENT BAE Pit na De E eh En LAE e yan na ede ak 22 1 6 Shutting Down Target Power Supply asaanean nawa nawa nean anan anan anana anana anna en nnn AKASA KAS SEKERA nn 24 1 7 Command Execution Flow at Flash Memory Rewriting eese 24 CHAPTER 2 COMMAND DATA FRAME FORMAT seeeeee eee ee cnn snas nsn manas asa snas een aa 27 2 1 Command Frame Transmission Processing eee eese seen en nennen nnn 29 2 2 Data Frame Transmission Processing eeclesie nana anan anan nennen aaa Sana nnna 29 2 3 Data Frame Reception Processing cecceeeeeseeeeeeeeeeeeeenseneeeeeeeseeeeaseneaneeeeseeeseneneeneeeeeees 29 CHAPTER 3 DESCRIPTION OF COMMAND PROCESSING eese eseeenen nennen 30 3 1 Reset COMMANG aci A dd A Kaa nK RKO
13. 1 R i M 1 1 1 1 1 1 1 1 i Target 1 F i TG GND 16 62 TG VDD i TG RESET Sox 1 Ho ES TG RO 718 olf TG TxD H TG FLMDO 9 10 i mio O i Kasi ena 1 x o O x 1 1 CN2 B 1 1 1 1 1 1 Remark For details about connecting unused pins shown in this circuit diagram see the user s manual of each product 122 Application Note U19735EJ1VOAN APPENDIK A CIRCUIT DIAGRAMS REFERENCE Figure A 2 Reference Circuit Diagram of Programmer and 78K0 Kx2 L Main Board When Using 3 3 V Interactive Level Shifter 78K0 Kx2 L Flash Programmer Sample Application Main Board for Monowire UART I F VDD 5 0V SN74LVC2T45 U203 sess S vob lt lt 228 74HCT573A VDD TA48033 vDD I 0E won 2 2 uo lu u 20007 ADO 2 19 AO ULRO AD7 ADI 3 95 Q0 18 AL H A ca ADS AD2 es SEL A2 us dem c ADS AG 5 pi Q3 HS 3 3V 2 0V SW ADA 6 pa oa 35 Aa i 1 VDD ADS T bs os 34 A5 6 VDD AD6 8 13 AG z
14. C is returned time out time twr13 lt 4 gt The status code is checked When ST1 ACK Proceeds to lt 5 gt When ST1 z ACK Abnormal termination B 5 Waits from the previous frame reception until the next data frame transmission wait time tro 6 The data frame security setting data is transmitted by data frame transmission processing 7 Atime out check is performed until status frame reception If a time out occurs a time out error C is returned time out time twr14 8 The status code is checked When ST1 ACK Proceeds to 9 When ST1 z ACK Abnormal termination D 9 Atime out check is performed until status frame reception If a time out occurs a time out error C is returned time out time turis 10 The status code is checked When ST1 ACK Normal completion A When ST1 z ACK Abnormal termination E 4 14 3 Status at processing completion Status at Processing Completion Status Code Normal completion A Normal acknowledgment ACK Description The command was executed normally and security setting data was set normally Abnormal Parameter error termination B The command information parameter is not OOH or the parameter BOT is not 03H Checksum error The checksum of the transmitted command frame or data frame does not match Protect error An already prohibited flag is to be enabled Negative acknowledgment NACK Comma
15. Figure 3 25 shows the data frame of version data Figure 3 25 Version Data Frame from 78K0 Kx2 L to Programmer STX LEN Data SUM ETX 02H 06H DV1 DV2 DV3 FV1 FV2 FV3 Checksum 03H Remark DV1 Integer of device version fixed to OOH See 4 12 Version Get Command for details about the flowchart of the processing sequence between the DV2 First decimal place of device version fixed to OOH DV3 Second decimal place of device version fixed to 00H FV1 Integer of firmware version FV2 First decimal place of firmware version FV3 Second decimal place of firmware version programmer and the 78K0 Kx2 L the flowchart of command processing and the sample program 48 Application Note U19735EJ1VOAN CHAPTER 3 DESCRIPTION OF COMMAND PROCESSING 3 10 Checksum Command 3 10 1 Description This command is used to acquire the checksum data in the specified area For the checksum calculation start end address specify a fixed address in block units 2 KB starting from the top of the flash memory Checksum data is obtained by sequentially subtracting data in the specified address range from the initial value 0000H in 1 byte units 3 10 2 Command frame and status frame Figure 3 26 shows the format of a command frame for the Checksum command and Figure 3 27 shows the status frame for the command Figure 3 26 Checksum Command Frame from Programmer to 78K0 Kx2 L SOH LEN COM Comm
16. JAKA KAKA KAKAK RARA RARA RR RR ko kckckckckckckck ck ckockckck kk ko kk J pod send command amp check status Kof JAKA KA KK A KAKAK KAKAK KA KK RARA RARE KAKAK KAKA RR RARAS fl wait tCOM wait before sending command put cmd ua FL COM VERIFY 7 fl cmd prm send VERIFY command rc get sfrm ua fl ua sfrm tWT6 MAX get status frame switch rc case FLC_NO_ERR break continue case FLC_DFTO_ERR return rc break case C default return rc break case B AKK KA KK AKK KAKAK KAKAK KK KAKAK KA KAKAK KA KAKAK ko ko ko kk J send user data x RRR RRRR RR KAKAK KA RARA RRA AKK KAKA KAKAK RRA RAR k ko kk EE J send head top while 1 make send data frame if bottom send head gt 256 vest size gt 256 is_end false yes not is_end frame send_size 256 transmit size 256 byte else is_end true send_size bottom send_head 1 transmit size send_head 1 byte Application Note U19735EJ1VOAN bottom 81 CHAPTER 4 UART COMMUNICATION MODE 82 memcpy fl txdata frm buf send head send size set data frame payload send_head send_size fl wait tFD3 put dfrm ua send size fl txdata frm is end rc get sfrm ua fl ua sfrm tWT7 MAX switch rc case FLC NO ERR def case FLC_DFTO_ERR return rc default return rc j if fl st2 ua FLST ACK rc decode status fl st2 ua return rc j
17. Status ACK NG Normal completion A Application Note U19735EJ1VOAN 85 CHAPTER 4 UART COMMUNICATION MODE 4 10 5 Sample program The following shows a sample program for Block Blank Check command processing JAKA KAKAK KA KAKAK KK KK AKA KAKAK KAKAK KAKA KAKAK AKK KA KAKAK REA RAR RR ck ko RARAS Block blank check command A x AKK KAKAK kk KAKAK KAKAK KA kk ko heck kc kk KAKA KAKAK KAKA KAKAK KAKA RRA RARA RR RARAS i u32 top i u32 bottom i u8 whole r u16 top address of blank check bottom address of blank check lt 1l gt check w NON user flash lt 0 gt chek only user flash error code Re Aj v A AKA KA KNA KAKAK KAKAK KAKAK AKK KK KAKA KAKAK KK KK A KAKAK KAKA RR RRA RR ko ko kk ok J ul6 fl ua blk blank chk u32 top u32 bottom rc set range prm fl cmd prm block num top bottom block num get block num top fl cmd prm 6 fl wait tCOM bottom u8 whole set SAH SAM SAL get block num EAH EAM I EAL whole check only user area or not wait before sending command put cmd ua FL COM BLOCK BLANK CHK 7 1 fl_cmd_prm rc get sfrm ua fl ua sfrm tWT8 MAX block num get status frame 1 switch rc case FLC_NO_ERR return rc break case A case FLC_DFTO_ERR return rc break case C default return
18. Status frame received Yes lt Timed out twr Yes Time out error C di Wi 7 Yes Abnormal termination B N p A y Wait from previous frame reception until next data frame transmission 9 v Data frame transmission processing User program h Status frame DM No lt received Yes di Timed out MN a A w Yes Time out error C 2 Abnormal termination B Yes AN Abnormal termination D N P No I data frames transmitted Yes ie A Normal completion A NG A Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE 4 9 5 Sample program The following shows a sample program for Verify command processing EEE AS px x Verify command ES RARE RRA KAKAK KAKAK KK KAKAK KR KR RK KKK A K KK RK KKK KK RR KKK KKK KK kck ckckck ck KKK KK Z 1 u32 top Start address sk i u32 bottom end address X r u16 error code KKK KKK KK K KK K K K AK K K A K AK KKK KR K AS u16 fl ua verify u32 top u32 bottom u8 buf ul6 fc u32 send head send size bool is end AKK KK A KAKAK KER ER ERE KAKA KAKAK RARE RAR RR kk ko kk J ie set params JAKA KAKA KAKAK KK KK AKA RARE KEE AK ko kckckckckckckck KAKAK kk ko kk J set_range_prm fl_cmd_prm top bottom set SAH SAM SAL EAH EAM EAL
19. if is end break continue j return FLC NO ERR ST2 No case D send user data get status frame break continue break case C break case B ACK send all user data yes case A Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE 4 10 Block Blank Check Command 4 10 1 Processing seguence chart Block Blank Check command processing seguence Programmer 78K0 Kx2 L Wait from previous frame reception lt 1 gt until next command transmission tcom Block Blank Check command frame transmission lt 2 gt 7 twrs i ee Time out check for x number of Time out FSA status frame reception occurs blocks Status frame received within specified time lt 4 gt Status frame reception Time out error C Reception status ACK other than ACK Other than ACK ACK Abnormal termination B Normal completion A Application Note U19735EJIVOAN 83 CHAPTER 4 UART COMMUNICATION MODE 4 10 2 Description of processing sequence lt 1 gt Waits from the previous frame reception until the next command transmission wait time tcom lt 2 gt The Block Blank Check command is transmitted by command frame transmission processing lt 3 gt A time out check is performed from command transmission until status frame reception If a time out occurs a time out error C is returned
20. is end break j KAKAK KAKAK AKK AK KAKA KAKAK RR KAKAK AKK kc kc ko ke ke he kk kk RARAS Check internally verify KAKAK KAKAK AKK AK RARE KAKAK AKK KAKAK AKK RE RR ke ke RR REA ARS get status frame again rc get sfrm ua fl ua sfrm tWT5_MAX block_num switch rc case FLC NO ERR return rc break case A case FLC DFTO ERR return rc break case C default return rc break case E H return rc Application Note U19735EJ1VOAN 77 CHAPTER 4 UART COMMUNICATION MODE 4 9 Verify Command 4 9 1 Processing sequence chart Verify command processing sequence status frame reception Te Programmer 78K0 Kx2 L Wait from previous frame reception xU until next command transmission tcom lt 2 gt Verify command frame transmission Time out Time out check for A occurs lt 3 gt ANS Status frame received within specified time lt gt Status frame reception 4 Reception status ACK other than ACK Other than ACK A ACK c aes SA Wait from previous frame reception a until next data frame transmission tros lt 6 gt Data frame user data for verify transmission Time out occurs E Time out check for SES status frame reception ius Status frame received within specified time Time out error C wa M lt 8 gt Status frame reception ST1 ST2 p Receptio
21. twri6 tro1 Application Note U19735EJ1VOAN 119 CHAPTER 5 FLASH MEMORY PROGRAMMING PARAMETER CHARACTERISTICS 8 Programming command Command frame Status frame Data frame 1 Status frame 1 TOOLD output I TOOLD input twr3 tFD2 twra Data frame n Status frame n Status frame TOOLD output TOOLD input twr4 twrs 9 Verify command Command frame Status frame Data frame Status frame 1 TOOLD output E TOOLD input Tide TS twr7 Data frame n 1 Status frame n Data frame n Status frame n TOOLD output jai TOOLD input F Mr 10 Security Set command Command frame Status frame Data frame Status frame Status frame TOOLD output TOOLD input twr13 tros twr14 twris 11 Wait before command frame transmission Status frame Command frame TOOLD output TOOLD input tcom 120 Application Note U19735EJ1VOAN APPENDIK A CIRCUIT DIAGRAMS REFERENCE Figures A 1 and A 2 show circuit diagrams of the programmer and the 78K0 Kx2 L for reference Application Note U19735EJ1VOAN 121 APPENDIK A CIRCUIT DIAGRAMS REFERENCE Figure A 1 Reference Circuit Diagram of Programmer and 78K0 Kx2 L Main Board 78K0 Kx2 L Flash Programmer Sample Application Main Board for Monowire UART I F
22. 1 to 127 so M 7 is obtained Application Note U19735EJ1VOAN CHAPTER 5 FLASH MEMORY PROGRAMMING PARAMETER CHARACTERISTICS Block configuration when executing simultaneous selection and erasure when erasing blocks 1 to 127 lt Block number gt User area e A z v A AAA 22 22 u X 2 1 d E W 22 2 a NU gt v te a V m i 2 O sc US lt lt lt lt lt Range of blocks that can be selected and erased simultaneously gt Application Note U19735EJ1VOAN te de d te ee 113 CHAPTER 5 FLASH MEMORY PROGRAMMING PARAMETER CHARACTERISTICS Example 2 114 Erasing blocks 5 to 10 N number of blocks to be erased 6 lt 1 gt lt 2 gt lt 3 gt lt 4 gt The first start block number is 5 and the number of blocks to be erased is 6 the values that satisfy Condition 1 are therefore 1 2 and 4 Moreover the value that satisfies Condition 2 is 1 and the value that satisfies Condition 3 is 1 so the number of blocks to be selected and erased simultaneously is 1 only block 5 is the erased After block 5 is erased the next start block number is 6 and the number of blocks to be erased is 5 the values that satisfy Condition 1 are therefore 1 2 and 4 Moreover the values that satisfy Condition 2 are 1 and 2 the value that satisfies Condition 3 is 2 so the number of blocks to be selected and erased simu
23. 3 Simultaneous Selection and Erasure Performed by Block Erase Command for the calculation method of the execution count of simultaneous selection and erasure 3 Time for 256 byte data transmission 4 Time for one block transmission Remark The waits are defined as follows twro to twT16 gt The 78K0 Kx2 L completes command processing between the MIN and MAX times The programmer must check the status of the start bit of the reception frame until the MAX time has elapsed For commands without a specified MAX time set the time to approximately 3 seconds 106 Application Note U19735EJ1VOAN CHAPTER 5 FLASH MEMORY PROGRAMMING PARAMETER CHARACTERISTICS 5 2 Flash Memory Parameter Characteristics of 78K0 Ix2 5 2 1 Flash memory programming mode setting time Ready start time from RESETT Wait for Reset command Note See the table below The values in the table are reference values The values depend on the used oscillator and might therefore exceed the maximum value or fall below the minimum value 1 Detailed mode specification time Release of POC to TOOLCT 1 0 us TOOLDT to TOOLC pulse start 110 0 us Minimum Low width of TOOLC 110 0 us Minimum High width of TOOLC 110 0 us Setup time of TOOLC to TOOLD for Mode Setting 55 0 us Minimum Low width of TOOLD 110 0 us Minimum High width of TOOLD 110 0 us Setup time of TOOLD to TOOLC for Mode Setting 55 0 us Setup time of TOOLD to RESET fo
24. 5 4 UART Communication Mode In the figure below TOOLD is illustrated as two separate lines for the sake of description but it is actually a single line 1 Data frame TOOLD output TOOLD input tor tor 2 Programming mode setting Reset command Vo 7 RESET input Command frame Mp z kbps Reset command Status frame TOOLD output TOOLD input a Details of programming mode setting Vo Voo RAPE POC release OV RESET T1 4 T5 TOOLC TOOLD READY response T6 T7 T9 00 125 kbps T12 118 Application Note U19735EJ1VOAN CHAPTER 5 FLASH MEMORY PROGRAMMING PARAMETER CHARACTERISTICS 3 Transition from programming mode to normal operating mode RESET Don t care TOOLC TOOLD Don care 4 Chip Erase command Block Erase command Block Blank Check command Oscillating Frequency Set command Command frame Status frame TOOLD output TOOLD input twr1 twr2 twra twro 5 Baud Rate Set command Command frame Command frame Reset command Status frame TOOLD output TOOLD input twr10 twro 6 Silicon Signature command Version Get command Command frame Status frame Data frame TOOLD output V TOOLD input twr11 twri2 tro1 7 Checksum command Command frame Status frame Data frame TOOLD output TOOLD input
25. Frame from Programmer to 78K0 Kx2 L STX LEN Data SUM ETX 02H 08H FLG BOT FFH FFH FFH FFH FFH FFH Checksum 03H fixed fixed fixed fixed fixed fixed Remark FLG Security flag BOT Boot block cluster last block number fixed to 03H Figure 3 32 Status Frame for Security Data Writing from 78K0 Kx2 L to Programmer STX LEN Data SUM ETX 02H 01H ST1 b Checksum 03H Remark ST1 b Security data write result 3 11 4 Internal verify check and status frame Figure 3 33 shows the status frame for internal verify check Figure 3 33 Status Frame for Internal Verify Check from 78K0 Kx2 L to Programmer STX LEN Data SUM ETX 02H 01H ST1 c Checksum 03H Remark ST1 c Internal verify result The following table shows the contents in the security flag field Table 3 5 Contents of Security Flag Field Item Contents Fixed to 1 Boot block cluster rewrite disable flag 1 Enable 0 Disable Fixed to 1 Programming disable flag 1 Enable programming 0 Disable programming Block erase disable flag 1 Enable block erase 0 Disable block erase Chip erase disable flag 1 Enable chip erase 0 Disable chip erase Application Note U19735EJ1VOAN 51 CHAPTER 3 DESCRIPTION OF COMMAND PROCESSING each operation The following table shows the relationship between the
26. SUM ETX 02H 01H ST1 Checksum 03H Remark ST1 Block blank check result See 4 10 Block Blank Check Command for details about the flowchart of the processing sequence between the programmer and the 78K0 Kx2 L the flowchart of command processing and the sample program 38 Application Note U19735EJ1VOAN CHAPTER 3 DESCRIPTION OF COMMAND PROCESSING 3 8 Silicon Signature Command 3 8 1 Description This command is used to read information such as the write protocol information silicon signature of the device and security flag information 3 8 2 Command frame and status frame Figure 3 20 shows the format of a command frame for the Silicon Signature command and Figure 3 21 shows the status frame for the command Figure 3 20 Silicon Signature Command Frame from Programmer to 78K0 Kx2 L SOH LEN COM SUM ETX H 01H 01H NY En Checksum 03H Silicon Signature Figure 3 21 Status Frame for Silicon Signature Command from 78K0 Kx2 L to Programmer STX LEN Data SUM ETX 02H 01H ST1 Checksum 03H Remark ST1 Command reception result Application Note U19735EJ1VOAN 39 CHAPTER 3 DESCRIPTION OF COMMAND PROCESSING 3 8 3 Silicon signature data frame Figure 3 22 shows the format of a frame that includes silicon signature data Figure 3 22 Silicon Signature Data Frame from 78K0 Kx2 L to Programmer
27. V Radoo KR doo 30 SA Description ie snes O ee eee 30 3 1 2 Command frame and status frame ccccceeescceeeeeeeesseeeeeeaeeeeccaeeescaeeesecaeeseceeeeeescaeeesssneeeeseaeess 30 3 2 Baud Rate Set Command iii a rau dao 31 3 2 1 Description uite pd 31 3 2 2 Command frame and status frame sse eene enne nnne nnne 31 3 3 Chip Erase COMMON ii adu rele ferc cat ee mi aae d aaa cu ene ag E gae aana danganan nov 32 EON MEN egi eO 32 3 3 2 Command frame and status frame cccccceesceeeeeeeeeesceeeeseneeeccsueesecaeeesecaeecesceeeessceeesesneesessaeess 32 3 4 Block Erase Comtmand eno nade na ii ii di 33 3 41 Desctiption o nei EL io pa HE e coe due certe ee 33 3 4 Command frame and status frame ccccccceececeeeeeeeeeeceeeeeeeeeceueeescaeeesecaeecesseeeesssaeeeesseeesseaeess 33 3 5 Programming Command conoci 34 3 5 17 Description a lite 34 3 5 2 Command frame and status frame sse eene nnne rines 34 3 5 8 Data frame and status rame 5 ues aga e ah a TG Ia NENEK AN EEN AN ENEG aei a Ga a a a e aas 34 3 5 4 Completion of transferring all data and status frame 0esseessesenen ee aee nenen e nane ene a nane cnn 35 3 60 AR asas gana akan aaa DER 36 9 64 iDesctiptiOna s pen aaa it ad daa aa an dee a es nd aaa ave a t 36 3 6 2 Command frame and status frame c cccceeccceeeeeeeeeeeeeeeeceneeesenneeesceaeeesecaeecesseeeesseaeee
28. b gt lt 6 gt The first start block number is 25 and the number of blocks to be erased is 49 the values that satisfy Condition 1 are therefore 1 2 4 8 16 and 32 Moreover the value that satisfies Condition 2 is 1 and the value that satisfies Condition 3 is 1 so the number of blocks to be selected and erased simultaneously is 1 only block 25 is then erased After block 25 is erased the next start block number is 26 and the number of blocks to be erased is 48 the values that satisfy Condition 1 are therefore 1 2 4 8 16 and 32 Moreover the values that satisfy Condition 2 are 1 and 2 the value that satisfies Condition 3 is 2 so the number of blocks to be selected and erased simultaneously is 2 blocks 26 and 27 are then erased After blocks 26 and 27 are erased the next start block number is 28 and the number of blocks to be erased is 46 the values that satisfy Condition 1 are therefore 1 2 4 8 16 and 32 Moreover the values that satisfy Condition 2 are 1 2 and 4 the value that satisfies Condition 3 is 4 so the number of blocks to be selected and erased simultaneously is 4 blocks 28 to 31 are then erased After blocks 28 to 31 are erased the next start block number is 32 and the number of blocks to be erased is 42 the values that satisfy Condition 1 are therefore 1 2 4 8 16 and 32 Moreover the values that satisfy Condition 2 are 1 2 4 8 and 32 the value that satisfies Condition 3 is 32 so the numbe
29. functions Read this manual in the order of the CONTENTS e Tolearn more about hardware functions of the 78K0 Kx2 L and 78K0 Ix2 gt See the user s manual of the 78K0 Kx2 L and 78K0 x2 Data significance Higher digits on the left and lower digits on the right Active low representation XXX overscore over pin or signal name Note Footnote for item marked with Note in the text Caution Information requiring particular attention Remark Supplementary information Numeral representation Binary xxxx or xxxxB Decimal Hexadecimal XXXXH Application Note U19735EJ1VOAN 5 Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such Documents related to devices Document Name Document No 78K0 Kx2 L User s Manual U19111E 78K0 lx2 User s Manual U19353E 78KO Microcontrollers Instructions User s Manual U12326E Caution The related documents listed above are subject to change without notice Be sure to use the latest version of each document for designing 6 Application Note U19735EJ1VOAN CONTENTS CHAPTER 1 FLASH MEMORY PROGRAMMING 2 eeeeee enne nnn ne nene nana ana sa sa snas ann SKK 11 1 1 gt OVOEVIBW AA O 11 12 System CorifiguratiOh aaa anga settee duce ce aaa aaa eerie aaa delet aaa dana kaga aan 12 1 3 Flash Memory Configuration
30. i ea ALE aaa awe daa gk ue 50 3 11 2 Command frame and status frame s0essenenen anna anae nana Ae rana 50 3 11 3 Data frame and status ame niniin pnr niini i E g aeaiee eas 51 3 11 4 Internal verify check and status frame asseonesenerenan eee eee eee eee eee RKK 51 CHAPTER 4 UART COMMUNICATION MODE cssccaeennnanennnnn nana anana nn eee een anana nennen nns n nnns 53 4 1 Command Frame Transmission Processing Flowchart eene 53 4 2 Data Frame Transmission Processing Flowchart eere 54 4 3 Data Frame Reception Processing Flowchart eere 55 AS cuts egheuedeancdevser aeerenucdeteawedsccesenedetecseds 56 4 4 1 Processing Sequence chartis irine naran e e aa aaa apa nnne nnn tnn tnnt nter nnne enne rennen 56 4 4 2 Description of processing sequence cccoooccccnnonnccnnoncnnnnnnnnonnnnn cnn ttnt nn nan enne RKK nnne 57 4 4 3 Status at processing completion sssesssessseeeeeeeenneen nennen nnne nnne nennen nennen 57 444 FIOWCNEM ON 58 4 445 Sample program cia A A deeds dees 59 4 5 Baud Rate Set Command asana ewan nan awanan nean ne nane nenene rr 60 4 51 Processing sequence chart ict acest titan diac gan tede elu vu ua dejo 60 4 5 2 Description of processing sequence eeessssssieeeeeeeeeee eene nennen entrent nnne nnne nennen 61 4 5 8 Status at processing completi
31. low level and then the TOOLD and TOOLC pins are set to high level while keeping the RESET pin at low level Next the reset is ended by alternately inputting two pulses and seven pulses three times from the TOOLC and TOOLD pins respectively enabling the system to enter the flash memory programming mode The following figure illustrates a timing chart for setting the flash memory programming mode and selecting the communication mode Figure 1 4 Setting Flash Memory Programming Mode and Selecting Communication Mode Voo POC release A o o vppeee h 1 1 i ov i D 1 g Oey tence a ixi E g aR PR RTS SS kaa Po SS Se SS mom RESET i EE 1 1 Jj 1 1 1 1 1 D TOOLC i i h i h h READY response i i i i i i i O0 125000 bps 1 J i i i i i i 1 1 1 1 TOOLD i i 1 1 D E E E ES MEE 1 2 3 4 lt b gt 6 7 8 9 lt 10 gt 1 Power application Von 2 TOOLC TOOLD Low level output gt High level output lt 3 gt TOOILC pulse output 2 pulses 4 TOOLD pulse output 7 pulses lt b gt TOOILC pulse output 2 pulses 6 TOOLD pulse output 7 TOOI
32. manufactured by or for NEC Electronics as defined above M8E0904E Application Note U19735EJ1VOAN Caution Target Readers Purpose Organization How to Read This Manual Conventions INTRODUCTION Explanations in this application note assume use of the 78K0 Kx2 L as the representative microcontroller Users of a product other than the 78K0 Kx2 L should read 78K0 Kx2 L as referring to that product This application note is intended for users who understand the functions of the 78K0 Kx2 L and 78K0 Ix2 and who will use these products to design application systems The purpose of this application note is to help users understand how to develop dedicated flash memory programmers for rewriting the internal flash memory of the 78K0 Kx2 L and 78KO0 Ix2 The sample programs and circuit diagrams shown in this document are for reference only and are not intended for use in actual design ins Therefore these sample programs must be used at the user s own risk Correct operation is not guaranteed if these sample programs are used This manual consists of the following main sections Flash memory programming Command data frame format Description of command processing UART communication mode Flash memory programming parameter characteristics It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering logic circuits and microcontrollers e To gain a general understanding of
33. rc break case B j TpeLurn cc 86 Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE 4 11 Silicon Signature Command 4 11 1 Processing seguence chart Silicon Signature command processing seguence Programmer Time ot ra Wait from previous frame reception 1 A UE until next command transmission tcom 78K0 Kx2 L lt 2 gt Silicon Signature command frame transmission Time out check for lt 3 gt E status frame reception twr11 Status frame received within specified time out s Status frame reception Reception status ACK other than ACK p than ACK ae LA Time out check for t lt setane data frame reception FD1 Time out Data frame received occurs within specified time lt 6 gt Data frame silicon signature reception ue NC Nace po x pane data frame Co frame z ech Application Note U19735EJ1VOAN 87 CHAPTER 4 UART COMMUNICATION MODE 4 11 2 Description of processing sequence lt 1 gt Waits from the previous frame reception until the next command transmission wait time tcom lt 2 gt The Silicon Signature command is transmitted by command frame transmission processing lt 3 gt A time out check is performed from command transmission until status frame reception If a time out occurs a time out error C is returned time out time twr11 lt 4 gt The status code is checked
34. reception t until next command transmission COM lt 2 gt Block Erase command frame transmission Time out ea Time out check for jus occurs status frame reception 2 Status frame received within specified time Cmm error C Status frame reception Reception status ms ACK other than BERT nl s Other than ACK n ACK sm m Normal ad Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE 4 7 2 Description of processing sequence lt 1 gt Waits from the previous frame reception until the next command transmission wait time tcom lt 2 gt The Block Erase command is transmitted by command frame transmission processing lt 3 gt A time out check is performed from command transmission until status frame reception If a time out occurs a time out error C is returned time out time twrz lt 4 gt The status code is checked When ST1 ACK Normal completion A When ST1 ACK Abnormal termination B 4 7 3 Status at processing completion Status at Processing Completion Status Code Normal completion A Normal acknowledgment ACK Description The command was executed normally and block erase was performed normally Abnormal Parameter error termination B The specified end address is out of the flash memory range or the specified start end address is not the first end address of the block Checksum error The chec
35. security flag field settings and the enable disable status of Table 3 6 Security Flag Field and Enable Disable Status of Each Operation Operating Mode Command Flash Memory Programming Mode Command operation after security setting v Execution possible x Execution impossible Security A Writing and block erase in boot block cluster area are impossible Setting Item Programming Chip Erase Block Erase Disable programming x y x Disable chip erase y x Disable block erase y y x Boot block cluster A x A rewrite disable flag Remark For the enable disable status of each command in the self programming mode see the user s manual of each device See 4 14 Security Set Command for details about the flowchart of the processing sequence between the programmer and the 78K0 Kx2 L the flowchart of command processing and the sample program 52 Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE 4 1 Command Frame Transmission Processing Flowchart y Command frame transmission processing SS y Pa Command frame header SOH 01H transmission y Wait between data transmissions tor v Data length LEN transmission Wait between data transmissions tor v Command number COM transmission Y LEN 1 bytes transmitted No Wait between data transmissions
36. the Reset command and Figure 3 2 shows the status frame for the command Figure 3 1 Reset Command Frame from Programmer to 78K0 Kx2 L SOH LEN COM SUM ETK 01H 01H 00H Reset Checksum 03H Figure 3 2 Status Frame for Reset Command from 78K0 Kx2 L to Programmer STX LEN Data SUM ETX 02H 1 ST1 Checksum 03H Remark ST1 Synchronization detection result See 4 4 Reset Command for details about the flowchart of the processing sequence between the programmer and the 78K0 Kx2 L the flowchart of command processing and the sample program 30 Application Note U19735EJ1VOAN CHAPTER 3 DESCRIPTION OF COMMAND PROCESSING 3 2 Baud Rate Set Command 3 2 1 Description This command is used to change the baud rate for UART communication 125 000 bps by default Even if not changing the baud rate be sure to execute this command after synchronization processing If the command is not executed subsequent commands cannot be normally executed After the Baud Rate Set command has been executed the Reset command must be executed to check synchronization at the changed baud rate 3 2 2 Command frame and status frame Figure 3 8 shows the format of a command frame for the Baud Rate Set command and Figure 3 4 shows the status frame for the command Figure 3 3 Baud Rate Set Command Frame from Programmer to 78K0 Kx2 L SOH LEN COM Command Information SUM ETX 01H 06H 9AH D0
37. time out time twrs x number of blocks lt 4 gt The status code is checked When ST1 ACK Normal completion A When ST1 z ACK Abnormal termination B 4 10 3 Status at processing completion Status at Processing Completion Status Code Normal completion A Normal acknowledgment ACK Description The command was executed normally and block blank check was executed normally Abnormal termination B Parameter error The end address is out of the flash memory range the start end address is not the first end address of the block or the value of parameter D01 is other than 00H or 01H Checksum error The checksum of the transmitted command frame does not match Negative acknowledgment NACK Command frame data is abnormal such as invalid data length LEN or no ETX MRG11 error The flash memory of the specified block is not blank Time out error C The status frame was not received within the specified time 84 Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE 4 10 4 Flowchart Block Blank Check command processing v Wait from previous frame reception until next command transmission tcom v Command frame transmission processing Block Blank Check Status frame No received twrs x number of blocks Yes Time out error C Abnormal termination B i
38. 01H 07H SAHSAMSALEAHEAMEAL Checksum 03H Block Erase Remark SAH SAM SAL Block erase start address start address of any block SAH Start address high bits 23 to 16 SAM Start address middle bits 15 to 8 SAL Start address low bits 7 to 0 EAH EAM EAL Block erase end address last address of any block EAH End address high bits 23 to 16 EAM End address middle bits 15 to 8 EAL End address low bits 7 to 0 Figure 3 8 Status Frame for Block Erase Command from 78K0 Kx2 L to Programmer STX LEN Data SUM ETX 02H 01H ST1 Checksum 03H Remark ST1 Block erase result See 4 7 Block Erase Command for details about the flowchart of the processing sequence between the programmer and the 78K0 Kx2 L the flowchart of command processing and the sample program Application Note U19735EJ1VOAN 33 CHAPTER 3 DESCRIPTION OF COMMAND PROCESSING 3 5 Programming Command 3 5 1 Description This command is used to write the user program to the flash memory by transmitting write data after having transmitted the write start address and the write end address Internal verification is then executed after the last data has been transmitted and writing has been completed The write start end address can be set only in the block start end address units If both of the status frames ST1 and ST2 after the last data transmission indicate ACK the 78K0 Kx2 L firmware automatically execute
39. 1 D02H D02L D03 D04 Checksum 03H Note For details of the command information setting refer to Table 3 1 If data other than in Table 3 1 is set a time out error will occur If a time out error has occurred execute a hardware reset and re set the flash memory programming mode Remark D01 Invalid data DO2H DO2L Baud rate setting D03 Invalid data D04 Invalid data Table 3 1 Command Information Setting Baud Rate D04 125 000 bps Fixed to FFH Fixed to FFH Fixed to FFH 250 000 bps 500 000 bps Figure 3 4 Status Frame for Baud Rate Set Command from 78K0 Kx2 L to Programmer STX LEN Data SUM ETX 02H 01H ST1 Checksum 03H Remark ST1 Synchronization detection result See 4 5 Baud Rate Set Command for details about the flowchart of the processing sequence between the programmer and the 78K0 Kx2 L the flowchart of command processing and the sample program Application Note U19735EJ1VOAN 31 CHAPTER 3 DESCRIPTION OF COMMAND PROCESSING 3 3 Chip Erase Command 3 3 1 Description This command is used to erase the entire contents of the flash memory In addition all of the information that is set by security setting processing can be initialized by chip erase processing as long as erasure is not prohibited by the security setting see 3 11 Security Set Command 3 3 2 Command frame and status frame Figure 3 5 shows the format of a comma
40. 2 silicon signature data list Table 3 4 78KO Ix2 Silicon Signature Data List Description Data Hex Vendor code NEC Extension code Extension code Function code Function information Device information Device information Internal flash ROM Transmitted from lower bytes of address last address Device name uPD 78F0740 78F0741 78F0742 78F0750 78F0751 78F0752 78F0743 78F0744 78F0753 78F0754 78F0745 78F0746 78F0755 78F0756 Security information Security information Any Boot block number The last block number of the boot cluster that is currently selected 03 Reserved Reserved FFFFFFFFFFFF Note 1 The list of internal flash ROM last addresses is as follows Internal flash ROM 4KB 0FFFH lastagdress 8 KB 1FFFH FF1 16 KB 3FFFH FeRO Note 2 is on the next page Application Note U19735EJ1VOAN 45 46 CHAPTER 3 DESCRIPTION OF COMMAND PROCESSING Note 2 The device names are listed below Device name list Generic Name 78K0 1Y2 78K0 1A2 78K0 1B2 Part Number D78F0740 D78F0741 D78F0742 D78F0750 D78F0751 D78F0752 D78F0743 D78F0744 D78F0753 D78F0754 D78F0745 D78F0746 D78F0755 D78F0756 Actual Value Upper Row Signature Data Lower Row Character Code F 7 4 F 7 5 4 ERERENERESERNEN AI a En E EJ re Application Note U19735EJ1VOAN CHAPTER 3 DESCRIPTION OF COMMAND PROCESSI
41. 4 Milano Italy Tel 02 667541 Branch The Netherlands Steijgerweg 6 5616 HS Eindhoven The Netherlands Tel 040 265 40 10 Asia amp Oceania NEC Electronics China Co Ltd 7th Floor Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100083 P R China Tel 010 8235 1155 http www cn necel com Shanghai Branch Room 2509 2510 Bank of China Tower 200 Yincheng Road Central Pudong New Area Shanghai P R China P C 200120 Tel 021 5888 5400 http www cn necel com Shenzhen Branch Unit 01 39 F Excellence Times Square Building No 4068 Yi Tian Road Futian District Shenzhen P R China P C 518048 Tel 0755 8282 9800 http www cn necel com NEC Electronics Hong Kong Ltd Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 2886 9318 http www hk necel com NEC Electronics Taiwan Ltd 7F No 363 Fu Shing North Road Taipei Taiwan R O C Tel 02 8175 9600 http www tw necel com NEC Electronics Singapore Pte Ltd 238A Thomson Road 12 08 Novena Square Singapore 307684 Tel 6253 8311 http www sg necel com NEC Electronics Korea Ltd 11F Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 02 558 3737 http www kr necel com G0706
42. AK KAKA KAKAK AKK kokckckckckckckckckckckck kock ck REREREE Set security flag command JS f ORCkckck kk KA KAKAK RR REE KAKA KAKAK KAKA KAKAK RRA KA KER EEK KAKAK RAR RR ko ko RARAS 1 u8 sc Security flag data xr ul6 error code RRR RRR RRR RARA ERE REE KEE REE KE KERR KEE REE ERE RRR RR KAKAK KAKA RA AR ck ko k ko kc RARAS ul6 fl ua setscf u8 scf u8 bot ul6 rc KAKA KAKAK AKK KK RARE RE RRA RARA RR RRA RA AER RAR ko kc k kc ko EE feit set params KAKAK kk RARE EERE RR RARE RARA kckckokckckckckckckck ck ck ck kc k kk k kk J fl cmd prm 0 0x00 BLK must be 0x00 fl cmd prm 1 0x00 PAG must be 0x00 fl txdata frm 0 scf 0511101000 FLG bit 7 6 5 3 must be fl txdata frm 1 bot BOT fl txdata frm 2 Oxff must be Oxff fl txdata frm 3 Oxff must be Oxff fl txdata frm 4 Oxff must be Oxff fl txdata frm 5 Oxff must be Oxff fl txdata frm 6 Oxff must be Oxff fl txdata frm 7 Oxff must be Oxff KAKAK KAKAK ke kk KK KK KAKA ke ke e kk ke kc kc RRA RRA RR RAR RRA ko ko kk LK send command f KAKAK KAKAK AKK KK KAKA KAKAK ke ke ke kc kc KAKAK AKK RR RRA EERE fl wait tCOM wait before sending command put cmd ua FL COM SET SECURITY 3 fl cmd prm rc get sfrm ua fl ua sfrm tWT13 TO get status frame switch rc case FLC NO ERR break continu
43. CK Abnormal termination B When ST1 ACK The following processing is performed according to the ST2 value e When ST2 ACK If transmission of all data frames is completed the processing ends normally A If there still remain data frames to be transmitted the processing re executes the sequence from 5 e When ST2 z ACK Abnormal termination D 4 9 3 Status at processing completion Status at Processing Completion Status Code Description Normal Normal acknowledgment The command was executed normally and the verify was completion A ACK completed normally Abnormal Parameter error The start end address is out of the flash memory range or the termination B start end address is not the start end address of the block Checksum error The checksum of the transmitted command frame or data frame does not match Negative acknowledgment Command frame data is abnormal such as invalid data length NACK LEN or no ETX Time out error C The status frame was not received within the specified time Abnormal Verify error OFH ST2 A verify error has occurred termination D Application Note U19735EJ1VOAN 79 CHAPTER 4 UART COMMUNICATION MODE 4 9 4 Flowchart 80 Verify command processing v Wait from previous frame reception until next command transmission tcom v Command frame transmission processing Verify Y
44. DESCRIPTION OF COMMAND PROCESSING 3 7 Block Blank Check Command 3 7 1 Description This command is used to check if a block in the flash memory with a specified block number is blank erased state A block can be specified with the start address of the blank check start block and the last address of the blank check end block Successive multiple blocks can be specified 3 7 2 Command frame and status frame Figure 3 18 shows the format of a command frame for the Block Blank Check command and Figure 3 19 shows the status frame for the command Figure 3 18 Block Blank Check Command Frame from Programmer to 78K0 Kx2 L SOH LEN COM Command Information SUM ETK 01H 08H Seh SAH SAM SAL EAH EAM EAL D01 Checksum 03H u Block Blank Check Remark SAH SAM SAL Block blank check start address start address of any block SAH Start address high bits 23 to 16 SAM Start address middle bits 15 to 8 SAL Start address low bits 7 to 0 EAH EAM EAL Block blank check end address last address of any block EAH End address high bits 23 to 16 EAM End address middle bits 15 to 8 EAL End address low bits 7 to 0 D01 00H When performing a block blank check for a single block 01H When performing a blank check for the complete area before erasing the chip Figure 3 19 Status Frame for Block Blank Check Command from 78K0 Kx2 L to Programmer STX LEN Data
45. FX 8 Q2b 3X x m p P04 P914 SEX GND 030 X 0 pos P913 BE exeol ehe m es 233 Poe P912 BTX UG 2653 S100 P911 SX RS 5000 P910 SX i reno As Beal boa ADO o no 120 DSUB 9Pin i ADL 14 502 xL CA o AD2 15 10 AZ Bamsner bOro ramo no ADS 171 D03 a2 To Host PC ZARARRELSRARAARARLLARSHSS ZSZSSISoo22QPPPPP OZSEERER zB 2 D04 st SEISISIEFSFISERSSESESISEISEISEIS u ADS 19182 as LS AD6 20 507 e LS 6 AD7 21 a L3 AT Dee 27 AB 22 26 zl s s Ao RE IN jm A10 po N a 4 8 ala WR 29 u am 25 AN E al S e alla ZEN el s amp alo 55 RD 24 oe a3 28 a y 3 A14 ETA wo 31 A5 N DO AAE TEIN 32 vec m7 38 AN i s 45 N GND d M5M5408BFP 70H ua 22 GND ADO 13 12 A0 ADI 14 001 A Tar A DQ2 AL AD2 15 pas p AD3 17 AS LS 48 ADA 16 004 8 M DO5 A4 ADS 19 006 pend A5 AD6 20 6 D07 A6 AD7 21 STS AZ poe pea meu AB 22 lt 26 A9 s A9 A10 2 AIO WR 29 25 ALL vob M ad E A12 RD 24 o 28 A13 OE A3 LS m 33K Ms 3L EH x T 32 ais 1 55 A Rl po XA wee RAE ALS 16 enD Nan a aga aia A Gaga ANGE ang a a ana aa ape aaa RESET 1 d MSMSAOBBFP 70H US 1 a sw o GND i 78K0 Kx2 L Target Board for Monowire UART I F RESETKEY i 10u 1 1 1 i TG VDD s ED 1 L ner 1 GND R101 GND 1 vss i TG GND 10k WS 1 1 TG RESET l RESET 1 r 1 16 60 ro 190100 1 TG TxD 1 i 1 1 oat 1 1 0 47u 1 1 TOOLCO REGC i TG FLMDO Lo d 1 i TOOLCL a 1 i R102 u101 i 78KO Kx2 L 1 3 a i 3
46. G RxD x 719 ofe X TG TxD 1 TG FLMDO 9 10 i uj enm A2 B2 i X ORS t lo o4 e i GND DIR 1 i CN2 B i 1 1 1 1 i i 1 1 1 Remark For details about connecting unused pins shown in this circuit diagram see the user s manual of each product 124 Application Note U19735EJ1VOAN For further information please contact NEC Electronics Corporation 1753 Shimonumabe Nakahara ku Kawasaki Kanagawa 211 8668 Japan Tel 044 435 5111 http www necel com America NEC Electronics America Inc 2880 Scott Blvd Santa Clara CA 95050 2554 U S A Tel 408 588 6000 800 366 9782 http www am necel com Europe NEC Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 0211 65030 http www eu necel com Hanover Office Podbielskistrasse 166 B 30177 Hannover Tel 0 511 33 40 2 0 Munich Office Werner Eckert Strasse 9 81829 M nchen Tel 0 89 92 10 03 0 Stuttgart Office Industriestrasse 3 70565 Stuttgart Tel 0 711 99 01 0 0 United Kingdom Branch Cygnus House Sunrise Parkway Linford Wood Milton Keynes MK14 6NP U K Tel 01908 691 133 Succursale Francaise 9 rue Paul Dautier B P 52 78142 Velizy Villacoublay C dex France Tel 01 3067 5800 Sucursal en Espa a Juan Esplandiu 15 28007 Madrid Spain Tel 091 504 2787 Tyskland Filial T by Centrum Entrance S 7th floor 18322 T by Sweden Tel 08 638 72 00 Filiale Italiana Via Fabio Filzi 25 A 2012
47. H 20H 00110111B 7 00111000B 8 01000110B F 00110001B 00110000B 00111000B 00111000B 00100000B 00100000B Q 0 5 8 8 Q Device name 44H 01000100B D Not added Same as left Security flag information Any Not added column Boot block number fixed 03H 00000011B 03H Not added Reserved FFFFFFFFFFFFH FFFFFFFFFFFFH Not added See 4 11 Silicon Signature Command for details about the flowchart of the processing seguence between the programmer and the 78K0 Kx2 L the flowchart of command processing and the sample program Application Note U19735EJ1VOAN 41 3 8 4 CHAPTER 3 DESCRIPTION OF COMMAND PROCESSING Silicon signature list 1 78K0 Kx2 L silicon signature data list Vendor code Table 3 3 78K0 Kx2 L Silicon Signature Data List NEC Description Data Hex Extension code Extension code Function code Function information Device information Device information Internal flash ROM last address Transmitted from lower bytes of address Device name uPD 78F0550 78F0551 78F0552 78F0555 78F0556 78F0557 78F0560 78F0561 78F0562 78F0565 78F0566 78F0567 78F0571 78F0572 78F0573 78F0576 78F0577 78F0578 78F0581 78F0582 78F0583 78F0586 78F0587 78F0588 Security information Security information Any
48. ION OF COMMAND PROCESSING 3 5 4 Completion of transferring all data and status frame Figure 3 13 shows the status frame after transfer of all data is completed Figure 3 13 Status Frame After Completion of Transferring All Data from 78K0 Kx2 L to Programmer STX LEN Data SUM ETK 02H 01H ST1 c Checksum 03H Remark ST1 c Internal verify result See 4 8 Programming Command for details about the flowchart of the processing sequence between the programmer and the 78K0 Kx2 L the flowchart of command processing and the sample program Application Note U19735EJ1VOAN 35 CHAPTER 3 DESCRIPTION OF COMMAND PROCESSING 3 6 Verify Command 3 6 4 Description This command is used to compare the data transmitted from the programmer with the data read from the 78K0 Kx2 L read level in the specified address range and check whether they match The verify start end address can be set only in the block start end address units 3 6 2 Command frame and status frame Figure 3 14 shows the format of a command frame for the Verify command and Figure 3 15 shows the status frame for the command Figure 3 14 Verify Command Frame from Programmer to 78K0 Kx2 L SOH LEN COM Command Information SUM ETK 13H 01H 07H d SAH SAM SAL EAH EAM EAL Checksum 03H Verify Remark SAH SAM SAL Verify start addresses EAH EAM EAL Verify end addresses Figure 3 15 Status Frame for V
49. KAK AKK KAKA KAKAK KK A ck ck ko kc kc ko kc kk ok fl wait tCOM wait before sending command put cmd ua FL COM WRITE 7 fl cmd prm send Programming command rc get sfrm ua fl ua sfrm tWT3 TO get status frame switch rc case FLC NO ERR break continue case FLC DFTO ERR return rc break case C default return rc break case B KAKA KAKA KAKAK EER ER ERE RRR EKER ERE EERE KK KAKA ck kk ko kk send user data el FERRERA RR RRE RARE KAKAK AKA KAKAK AKK KK RARA ck kck RRA send_head top while 1 make send data frame if bottom send head gt 256 rest size gt 256 is_end false yes not is_end frame 76 Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE send_size 256 transmit size 256 byte else is_end true send_size bottom send_head 1 transmit size bottom send_head 1 byte memcpy f1 txdata frm rom_buf send_head send size set data frame payload send head send size fl wait tFD2 wait before sending data frame put dfrm ua send size fl txdata frm is end send user data rc get sfrm ua fl ua sfrm tWT4 MAX get status frame switch rc case FLC NO ERR break continue case FLC DFTO ERR return rc break case C default return rc break case B if fl st2 ua FLST_ACK ST2 ACK re decode_status fl_st2_ua No return rc case D if
50. LC pulse output 2 pulses 7 pulses 8 TOOLD pulse output 7 pulses 9 Resetrelease serial programming mode setting 10 READY pulse 00 125000 bps input start microcontroller gt programmer Application Note U19735EJ1VOAN 17 CHAPTER 1 FLASH MEMORY PROGRAMMING The following table shows the communication mode that can be selected with the 78K0 Kx2 L and the port to be used Table 1 4 78K0 Kx2 L Communication Mode and Used Port Communication Mode Port Used for Communication Single wire UART TOOLDO TOOLD1 1 5 1 UART communication mode The TOOLD pin is used for UART communication The communication conditions are as shown below Table 1 6 UART Communication Conditions Item Description Baud rate Communication is performed at 125 000 bps until the Baud Rate Set command for baud rate setting command processing is transmitted The transmission rate is changed to the baud rate set by the Baud Rate Set command from the transmission of the Reset command for baud rate command processing For details of the settable baud rate refer to 3 2 Baud Rate Set Command Parity bit None Data length 8 bits LSB first Stop bit 2 bits programmer gt 78K0 Kx2 L 1 bit 78K0 Kx2 L gt programmer The role of the master and slave is occasionally exchanged during UART communication so communication at the optimum timing is possible Caution Set the same baud rate to the master and
51. NG 3 9 Version Get Command 3 9 1 Description This command is used to acquire information on the 78K0 Kx2 L device version and firmware version The device version value is fixed to OOH Use this command when the programming parameters must be changed in accordance with the 78K0 Kx2 L firmware version Caution The firmware version may be updated during firmware update that does not affect the change of flash programming parameters at this time update of the firmware version is not reported Example Firmware version and programming parameters Programming Firmware version parameters Upgrade that requires changing of flash Parameter A programming parameters V2 00 Upgrade of items that does not affect the E Parameter B change of flash programming parameters V3 00 3 9 2 Command frame and status frame Figure 3 23 shows the format of a command frame for the Version Get command and Figure 3 24 shows the status frame for the command Figure 3 23 Version Get Command Frame from Programmer to 78K0 Kx2 L SOH LEN COM SUM ETK C5H 01H 01H Checksum 03H Version Get Figure 3 24 Status Frame for Version Get Command from 78K0 Kx2 L to Programmer STX LEN Data SUM ETX 02H 01H ST1 Checksum 03H Remark ST1 Command reception result Application Note U19735EJ1VOAN 47 CHAPTER 3 DESCRIPTION OF COMMAND PROCESSING 3 9 3 Version data frame
52. PTER 4 UART COMMUNICATION MODE 4 6 2 Description of processing sequence lt 1 gt Waits from the previous frame reception until the next command transmission wait time tcom lt 2 gt The Chip Erase command is transmitted by command frame transmission processing lt 3 gt A time out check is performed from command transmission until status frame reception If a time out occurs a time out error C is returned time out time twr lt 4 gt The status code is checked When ST1 ACK Normal completion A When ST1 ACK Abnormal termination B 4 6 3 Status at processing completion Status at Processing Completion Status Code Description Normal Normal acknowledgment The command was executed normally and chip erase was completion A ACK performed normally Abnormal Checksum error The checksum of the transmitted command frame does not termination B match Protect error Chip erase or boot block rewrite is prohibited in the security setting Negative acknowledgment Command frame data is abnormal such as invalid data length NACK LEN or no ETX MRG10 error An erase error has occurred MRG11 error Write error Time out error C The status frame was not received within the specified time Application Note U19735EJ1VOAN 65 CHAPTER 4 UART COMMUNICATION MODE 4 6 4 Flowchart 66 E Erase commana processing v Waits from previous frame reception until next co
53. SABLE TxD Hi Z pmFL TxD PM IN TxD Hi Z fl wait t11 MIN wait rc check ready pulse check READY PULSE from target device if roc return rc pulse width timing error j init fl uart Initialize UART h w for Flash device control UARTEO true enable UART h w SRIFO false clear UART Rx IRQ flag SRMKO false enable UART Rx INT return rc start RESET command proc Application Note U19735EJ1VOAN CHAPTER 1 FLASH MEMORY PROGRAMMING 1 6 Shutting Down Target Power Supply After each command execution is completed shut down the power supply to the target after setting the RESET pin to low level as shown below Set other pins to Hi Z when shutting down the power supply to the target Caution Shutting down the power supply and inputting a reset during command processing are prohibited Figure 1 5 Timing for Terminating Flash Memory Programming Mode 1 Voo i H A i i i RESET i x 1 i 1 Reset input Power shutdown 1 7 Command Execution Flow at Flash Memory Rewriting Figure 1 6 illustrates the basic flowchart when flash memory rewriting is performed with the programmer Other than commands shown in Figure 1 6 the Verify command and Checksum command are also supported 24 Application Note U19735EJ1VOAN CHAPTER 1 FLASH MEMORY PROGRAMMING Figure 1 6 Basic Flowchart for Flash Memory Rewrite Processing Basic flow Power appl
54. Set command is transmitted by command frame transmission processing lt 3 gt Waits from command transmission until Reset command transmission wait time twr10 lt 4 gt The baud rate of UART communication is switched to the value set by the Baud Rate Set command lt 5 gt The Reset command is transmitted by command frame transmission processing lt 6 gt A time out check is performed from command transmission until status frame reception If a time out occurs a time out error C is returned time out time twro lt 7 gt Since the status code should be ACK the processing ends normally A 4 5 3 Status at processing completion Status at Processing Completion Status Code Description Normal Normal acknowledgment The command was executed normally and the synchronization completion A ACK of the UART communication speed has been established between the programmer and the 78K0 Kx2 L Abnormal Checksum error The checksum of the transmitted command frame does not termination B match Negative acknowledgment Command frame data is abnormal such as invalid data length NACK LEN or no ETX Note Time out error C Data frame reception was timed out With the 78K0 Kx2 L this command also results in errors in the following cases e Command information D01 DO2H DO2L D03 D04 is invalid e The Reset command was not detected after setting the baud rate and receiving command frame data for 16 times Not
55. T COMMUNICATION MODE 4 12 Version Get Command 4 12 1 Processing seguence chart Version Get command processing seguence Programmer 78K0 Kx2 L Wait from previous frame reception lt 1 gt j RET 1 until next command transmission tcom lt 2 gt Version Get command frame transmission Time out check for lt 3 gt E twr 9 status frame reception da Time out occurs Status frame received within specified time Status frame reception m out error C Reception status ES ACK other than pd z than ACK Abnormal termination ie ds Time out check for trot data frame reception Time out Data frame received occurs within specified time lt 6 gt Data frame version data reception rom error C Normal po Yes No Nom i E Z Yes K Y Normal BAN Application Note U19735EJ1VOAN 91 CHAPTER 4 UART COMMUNICATION MODE 4 12 2 Description of processing seguence lt 1 gt Waits from the previous frame reception until the next command transmission wait time tcom lt 2 gt The Version Get command is transmitted by command frame transmission processing lt 3 gt A time out check is performed from command transmission until status frame reception If a time out occurs a time out error C is returned time out time twr12 lt 4 gt The status code is checked When ST1 ACK Proceeds to lt 5 gt When ST1 z ACK Abnormal termination B
56. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry ENESAS 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted
57. When ST1 ACK Proceeds to lt 5 gt When ST1 ACK Abnormal termination B lt 5 gt A time out check is performed until data frame silicon signature data reception If a time out occurs a time out error C is returned time out time trn1 lt 6 gt The received data frame silicon signature data is checked If data frame is normal Normal completion A If data frame is abnormal Data frame error D 4 11 3 Status at processing completion Status at Processing Completion Status Code Description Normal Normal acknowledgment The command was executed normally and silicon signature data completion A ACK was acquired normally Abnormal Checksum error The checksum of the transmitted command frame does not termination B match Negative acknowledgment Command frame data is abnormal such as invalid data length NACK LEN or no ETX Read error Reading security information failed Time out error C The status frame or data frame was not received within the specified time Data frame error D The checksum of the data frame received as silicon signature data does not match 88 Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE 4 11 4 Flowchart C Silicon Signature D C command processing v Wait from previous frame reception until next command transmission tcoM v Command frame transmission processing Silicon Signature
58. ame so LEN and COM are targets of checksum calculation SOH LEN COM SUM ETK 01H 01H 20H Checksum 03H Checksum calculation targets For this command frame checksum data is obtained as follows OOH initial value 01H LEN 20H COM DFH Borrow ignored Lower 8 bits only The command frame finally transmitted is as follows SOH LEN COM SUM ETX 01H 01H 20H DFH 03H Data frame To transmit a data frame as shown below LEN and D1 to D4 are targets of checksum calculation STX LEN D1 D2 D3 D4 SUM ETX 02H 04H FFH 80H 40H 22H Checksum 03H Checksum calculation targets For this data frame checksum data is obtained as follows 00H initial value 04H LEN FFH D1 80H D2 40H D3 22H D4 1BH Borrow ignored Lower 8 bits only The data frame finally transmitted is as follows STX LEN D1 D2 D3 D4 SUM ETX 02H 04H FFH 80H 40H 22H 1BH 03H When a data frame is received the checksum data is calculated in the same manner and the obtained value is used to detect a checksum error by judging whether the value is the same as that stored in the SUM field of the receive data When a data frame as shown below is received for example a checksum error is detected STX LEN D1 D2 D3 D4 SUM ETX 02H 04H FFH 80H 40H 22H 1AH 03H T Normally 1BH
59. anaaa aana eaa naa rr nan ananeng anana eng rene nr 73 4 8 3 Status at processing completion aessaaaae aan aana anae aaa A cnn cnn arrancan 74 ot ME do od Eo SE O gada ga en E a A 75 485 Sample Prodi niti ta NAN EA E esheets dees nul aims 76 4 9 Verify Comma M 78 4 9 1 Processing sequence chart oeae aa aea aa weke ena eee E aeea ANG AKE an aaa naa kaa eraasi nanak 78 4 9 2 Description of processing seguence asaaaaanaa anana aane a anana ran eene enne KK 79 4 9 3 Status at processing completion sssesae aana anna n eaaa aaa cnn carac rra rra rra 79 4 94 Flowclhiartz ioter ee eS A ea ee vo re ee 80 4 9 5 Sample program sess 15s coder Basa sa an tl hee t pa te a Eu 81 4 10 Block Blank Check Command saaesa esa eenan anana naen anana rr 83 4 10 1 Processing sequence Ghart sesadean anan aaa Kaanan gaen da E E dan a Gen dh NE a agen a E NGE anaa entere 83 4 10 2 Description of processing seguence anan asasaaeeaaa aana aana nean anana enne nnne 84 4 10 3 Status at processing completion ooocnnccinncninnocnnccnoncncnncnconnncnnnn conc cnn carac rra nr 84 4 10 4 do o E a 85 4 10 5 Sample prograrn oiii nce ir cie vein e cete iot draku b hu ee E a ce Pu evel 86 4 11 Silicon Signature Command asana ena en anna nan cr 87 4 11 1 Processing sequence chart aiia DN AGE EEN ENE di 87 4 11 2 Description of processing seguence
60. and Information SUM ETK BOH 01H 07H SAH SAM SAL EAH EAM EAL Checksum 03H Checksum Remark SAH SAM SAL Checksum calculation start addresses EAH EAM EAL Checksum calculation end addresses Figure 3 27 Status Frame for Checksum Command from 78K0 Kx2 L to Programmer STX LEN Data SUM ETX 02H 01H ST1 Checksum 03H Remark ST1 Command reception result 3 10 3 Checksum data frame Figure 3 28 shows the format of a frame that includes checksum data Figure 3 28 Checksum Data Frame from 78K0 Kx2 L to Programmer STX LEN Data SUM ETX 02H 02H CK1 CK2 Checksum 03H Remark CK1 Higher 8 bits of checksum data CK2 Lower 8 bits of checksum data See 4 13 Checksum Command for details about the flowchart of the processing sequence between the programmer and the 78K0 Kx2 L the flowchart of command processing and the sample program Application Note U19735EJ1VOAN 49 CHAPTER 3 DESCRIPTION OF COMMAND PROCESSING 3 11 Security Set Command 3 11 1 Description This command is used to perform security settings enabling disabling of write block erase chip erase and boot block cluster rewriting By performing these settings with this command rewriting of the flash memory by an unauthorized party can be restricted Caution Even after the security setting additional setting of changing from enable to disable can be performed however chang
61. arams A KAKA KAKAK AKK KK RARE RE RRE RARA RRA RRA ERA RR kc k ko RARAS set params set_range_prm fl_cmd_prm top bottom set SAH SAM SAL EAH EAM EAL AAN J L send command EAN fl wait tCOM wait before sending command put cmd ua FL COM GET CHECK SUM 7 fl cmd prm send GET VERSION command rc get sfrm ua fl ua sfrm tWT16 MAX get status frame switch rc case FLC NO ERR break continue case FLC_DFTO_ERR return rc break case C default return rc break case B j KAKAK KAKA KAKAK KK AKA KAKAK kc kc kc kc RR RRA RAR ER k ck ck kc kc k ko ko ko kk A get data frame Checksum data Es KAKA KAKAK RARE RARA RARE AKK KAKA KAKAK RR RAR kc kc k ko ko ko kk J rc get_dfrm_ua fl_rxdata_frm tFD1_MAX get status frame if rc if no error return rc case D sum fl rxdata frm OFS STA PLD lt lt 8 fl rxdata frm OFS STA PLD 1 SUM data return rc case A Application Note U19735EJ1VOAN set CHAPTER 4 UART COMMUNICATION MODE 4 14 Security Set Command 4 14 1 Processing seguence chart Security Set command processing sequence Programmer 78K0 Kx2 L Wait from previous frame reception sE until next command transmission tcom lt 2 gt Security Set command frame transmission B Time out__ E OS as Time out check for twr13 xt status frame reception ai Dus Status frame
62. as not received within the specified time Data frame error D The checksum of the data frame received as checksum data does not match 96 Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE 4 13 4 Flowchart checksum B processing d v Wait from previous frame reception until next command transmission tcom v Command frame transmission processing Checksum No Status frame received Time out error C Abnormal termination m C Data frame checksum data received No tFD1 Normal data frame 4 Time out error C zt Data frame error D Normal completion A Application Note U19735EJ1VOAN 97 CHAPTER 4 UART COMMUNICATION MODE 4 13 5 Sample program 98 The following shows a sample program for Checksum command processing AKK KA K KA KAKAK KK KK AKA KAKAK KAKAK KAKA KAKAK AKK KA KAKAK RARA RRA ck kc ARRAY Je Get checksum command A AAN i u16 sum pointer to checksum save area i i u32 top start address pe i u32 bottom end address r u16 error code RRR RRRR REE ER ERE REE KAKAK KAKAK RR RARE RARA RE RR RR RRE REE RA ckck ck ko k RR ko kk J ul6 fl ua getsum u16 sum u32 top u32 bottom ul6 rc FERRERA RR REA ERE REE RRA RARA RR RR RRE AER RAR RRA RARAS pst set p
63. ata received Normal data frame Normal completion A X Timed out Application Note U19735EJ1VOAN 93 CHAPTER 4 UART COMMUNICATION MODE 4 12 5 Sample program The following shows a sample program for Version Get command processing JAKA KAKAK KA KAKAK RR RRE KAKAK KAKAK KAKA KAKAK AKK KA KAKAK REE RAR RR kc kc kokok J FE Sl JA Get device firmware version command LE El JAKA KAKAK KAKAK AKK KAKA KAKAK AKK RR KA KAKAK KK KK AKA RR RRE RARE RRA RARA k ko ko kk J JE i u8 buf pointer to version date save area r ul6 error code x ERROR KAKAK KK KK KAKA kk kk kkk kkk kk kk kk kk kk kkk kk ul6 fl_ua_getver u8 buf RRERERERKARE RARAS ul6 rc fl wait tCOM wait before sending command put cmd ua FL COM GET VERSION 1 fl cmd prm send GET VERSION command rc get sfrm ua fl ua sfrm tWT12 TO get status frame switch rc case FLC NO ERR break continue case FLC_ DFTO ERR return rc break case C default return rc break case B H rc get dfrm ua fl rxdata frm tFD1 TO get data frame if rc return rc case D memcpy buf fl rxdata frm OFS STA PLD DFV LEN copy version data return rc case A ul6 fl_ua_getver u8 buf ul6 rc fl wait tCOM wait before sending command put cmd ua FL COM GET VERSION 1 fl cmd prm send GET VERSION command rc get sfrm ua fl
64. ation The programmer needs to be ready for reception of the following data within the MIN time after completion of the current communication The MAX time is not specified but set the timeout to approximately 3 seconds 108 Application Note U19735EJ1VOAN CHAPTER 5 FLASH MEMORY PROGRAMMING PARAMETER CHARACTERISTICS 5 2 3 Command characteristics Command Condition Reset twro Note 1 Chip Erase lwri 54 4 6 2 x total number of 883 6 136 1 x total number of blocks ms blocks ms Block Erase twr 15 2 ms 0 3 190 3 x execution count of simultaneous selection and erasure 139 9 x number of blocks to be erased ms Programming twra twraNotes 132 9 ms twrs 723 6 ms Verify twre Note 3 twr7 Block Blank Check twre Baud Rate Set twr10 Silicon Signature twrn1 Version Get twr12 Security Set twr13 twr14 351 3 ms twri5 352 5 ms Checksum twr16 Notes 1 Reception must be enabled for the programmer before command frame transmission 2 See 5 3 Simultaneous Selection and Erasure Performed by Block Erase Command for the calculation method of the execution count of simultaneous selection and erasure 3 Time for 256 byte data transmission 4 Time for one block transmission Remark The waits are defined as follows twro to twr16 gt The 78K0 lx2 completes command processing between the MIN and MAX times The programmer must check the sta
65. ation Note U19735EJ1VOAN 57 CHAPTER 4 UART COMMUNICATION MODE 4 4 4 Flowchart 58 Reset command processing Wait toc Command frame transmission processing Reset Status frame No received Yes Yes twro NG Retry count over Normal completion A m termination B Mc PES MENGE Application Note U19735EJ1VOAN Time out error C No No CHAPTER 4 UART COMMUNICATION MODE 4 4 5 Sample program The following shows a sample program for Reset command processing KAKAK KAKAK AK KAKAK RE e he ke hehe RR RR RRE RE RARE RAR KK KAKAK KA KAKAK RRA RR ko kc ko kk ko kk J X R Reset command x ES AN r ul6 error code x f kk ke ke kk kk ck ke KAKAK RARE RRA RR RR RRE EE RARE RAR RAR RR AREA RR RR ARA RR ko kc RE RARAS ul6 fl ua reset void 1 ul6 LE u32 retry set uart0 br BR 125000 change to 125000bps fl wait tCOM wait set ua dir rx Change Mono wire UART receive mode for retry 0 retry lt tRS retry fl wait t0C MIN wait put cmd ua FL COM RESET 1 fl cmd prm send RESET command rc get sfrm ua fl ua sfrm tWTO TO if rc FLC DFTO ERR ZP E o 2 break yes case C if rc FLC ACK ACK break yes case A else NOP continue case B if exit from loop switch rc iu case FLC_NO_ERR return rc break
66. atus frame reception twra Status frame received within specified time EM Time out error C y LE Z lt 8 gt Status frame reception e A Y i 1 Reception status ST1 Other than ACK ACK other than ACK 7 z CN JL X Abnormal termination B ACK Lr p S Ee a Reception status ST2 A ACK other than ACK J d ES ACK Abnormal termination D X A es 4 No Go to 5 Yes Time out A z eg t ber of occurs status frame reception X number o D d blocks Status frame received within specified time Y EN Eg Timeout error C d ES i Status frame reception E Reception status y ACK other than ACK Wi Other than ACK E Va VAS X Abnormal termination E NE 72 Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE 4 8 2 Description of processing sequence lt 1 gt Waits from the previous frame reception until the next command transmission wait time tcom lt 2 gt The Programming command is transmitted by command frame transmission processing lt 3 gt A time out check is performed from command transmission until status frame reception If a time out occurs a time out error C is returned time out time twrs lt 4 gt The status code is checked When ST1 ACK Proceeds to lt 5 gt When ST1 z ACK Abnormal termination B 5 Waits from the previous frame reception until the next data frame transmission wait time tr 6 User data is transmitte
67. chine if a user program has been downloaded to the programmer in advance For example NEC Electronics flash memory programmer PG FP5 can execute programming either by using the GUI software with a host machine connected or by itself standalone Figure 1 2 System Configuration Example Single wire UART communication mode LSB first transfer Host machine Programmer 78K0 Kx2 L Firmware RS 232C USB Remarks 1 The 78K0 Kx2 L can only communicate via the single wire UART communication mode 2 For the pins used by flash memory programming and the recommended connections of unused pins see the user s manual of each product 12 Application Note U19735EJ1VOAN CHAPTER 1 FLASH MEMORY PROGRAMMING 1 3 Flash Memory Configuration The 78K0 Kx2 L and 78K0 Ix2 must manage product specific information such as device name and memory information via the programmer Table 1 1 shows the flash memory size of the 78K0 Kx2 L and 78K0 Ix2 and Figure 1 3 shows the configuration of the flash memory Table 1 1 Size of Flash Memory for Each Product a Size of flash memory for 78K0 Kx2 L LPD78F0550 78F0555 78F0560 78F0565 HPD78F0551 78F0556 78F0561 78F0566 8 KB 78F0571 78F0576 78F0581 78F0586 HPD78F0552 78F0557 78F0562 78F0567 16 KB 78F0572 78F0577 78F0582 78F0587 HPD78F0573 78F0578 78F0583 78F0588 32 KB b Size of flash memory for 78K0 lx2
68. criptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of a customer s equipment shall be done under the full responsibility of the customer NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC Electronics endeavors to enhance the quality and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely In addition NEC Electronics products are not taken measures to prevent radioactive rays in the product design When customers use NEC Electronics products with their products customers shall on their own responsibility incorporate sufficient safety measures such as redundancy fire containment and anti failure features to their products in order to avoid risks of the damages to property including public or social property or injury including death to persons as the result of defects of NEC Electronics products NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC Electronics products developed based on a customer designated quality assura
69. d by data frame transmission processing 7 Atime out check is performed from user data transmission until data frame reception If a time out occurs a time out error C is returned time out time twr 8 The status code ST1 ST2 is checked also refer to the processing sequence chart and flowchart When ST1 z ACK Abnormal termination B When ST1 ACK The following processing is performed according to the ST2 value e When ST2 ACK Proceeds to 9 when transmission of all data frames is completed If there still remain data frames to be transmitted the processing re executes the sequence from 5 e When ST2 z ACK Abnormal termination D 9 Atime out check is performed until status frame reception If a time out occurs a time out error C is returned time out time twrs x number of blocks 10 The status code is checked When ST1 ACK Normal completion A When ST1 ACK Abnormal termination E Application Note U19735EJ1VOAN 73 CHAPTER 4 UART COMMUNICATION MODE 4 8 3 Status at processing completion Status at Processing Completion Normal completion A Normal acknowledgment ACK Status Code Description The command was executed normally and the user data was written normally Abnormal termination B Parameter error The start end address is out of the flash memory range or the specified start end address is not the first end address of the block Checksum error Th
70. designing a programmer 5 1 Flash Memory Parameter Characteristics of 78K0 Kx2 L 5 1 1 Flash memory programming mode setting time Ready start time from RESET tro 1 5 ms 3s Wait for Reset command toc 14 0 us 3s 1 Detailed mode specification time Release of POC to TOOLCT TOOLD to TOOLC pulse start T3 Minimum Low width of TOOLC T4 Minimum High width of TOOLC T5 Setup time of TOOLC to TOOLD for Mode Setting T6 Minimum Low width of TOOLD T7 Minimum High width of TOOLD T8 Setup time of TOOLD to TOOLC for Mode Setting T9 Setup time of TOOLD to RESET for Mode Setting T10 Ready start time from RESET T11 tno Maximum Setup time T12 RESET to TOOLC TOOLDI Minimum Low width TOOLC and TOOLD Minimum High width TOOLC and TOOLD 104 Application Note U19735EJ1VOAN CHAPTER 5 FLASH MEMORY PROGRAMMING PARAMETER CHARACTERISTICS 5 1 2 Programming characteristics Condition Between data frame transmissions Data frame T Data frame transmission frame transmission RE From status ine transmission until data frame troi transmission From status frame transmission until data frame troe transmission 2 From status frame transmission until data frame reception 3 From status frame transmission until command frame reception Notes 1 Enable successive reception for the programmer 2 Time for one block transmission Remark The waits are defined as follows
71. e case FLC_DFTO_ERR return rc break case C default return rc break case B KAKAK KA KAKAK AKK KAKA KAKAK RARA RR RARA RR RRA AKA kc koko ko kk send data frame security setting data KAKA KAKAK RARE RARA KAKAK KK KAKA KAKAK ck ckck ckck ko kc k ko ko ko ER J fl wait tFD3 put dfrm ua 6 fl txdata frm true send securithi setting data rc get sfrm ua fl ua sfrm tWT14 MAX get status frame switch rc case FLC NO ERR break continue case FLC DFTO ERR return rc break case C 102 Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE default return rc break case B AKK KAKAK KAKAK AKK KK KAKAK KK KK KAKA ERR ERE KAKA KAKAK ko kk J JE Check internally verify A RRR RRERRRRKKE EKER ER ER RRA RARA RRE RRA RR RAR RA ko ko ko kk rc get_sfrm_ua fl_ua_sfrm tWT15_MAX get status frame switch rc case FLC_NO_ERR return rc break case A case FLC_DFTO_ERR return rc break case C default return rc break case B j return rc Application Note U19735EJ1VOAN 103 CHAPTER 5 FLASH MEMORY PROGRAMMING PARAMETER CHARACTERISTICS This chapter describes the characteristics of parameter transmitted between the programmer and the devices 78K0 Kx2 L and 78K0 Ix2 in the flash memory programming mode Refer to the user s manual of the 78K0 Kx2 L or 78K0 1x2 for electrical specifications when
72. e f a time out error has occurred execute a hardware reset and re set to the flash memory programming mode Application Note U19735EJ1VOAN 61 CHAPTER 4 UART COMMUNICATION MODE 4 5 4 Flowchart 62 Baud Rate Set command processing v Wait from previous frame reception until next command transmission tcom v Command frame transmission processing Baud Rate Set v Wait from command frame transmission until Reset command transmission twr10 v Command frame transmission processing Reset Status frame No received Yes twro Yes Normal completion A Time out error C Application Note U19735EJ1VOAN No CHAPTER 4 UART COMMUNICATION MODE 4 5 5 Sample program The following shows a sample program for Baud Rate Set command processing EEE AS px EJ Set baudrate command A A KKK KKK KK K KAKAK KAKAK KERR KR KK KR RK KKK KR RK RK KKK KR KR RK KKK KR KK KKK KR ck ck ck ck kk 1 us brid baudrate ID r ul6 error code A AA Jj u16 fl ua setbaud u8 brid 1 ul6 RE u8 br u32 retry fl cmd prm 0 Oxff D01 invalid data fl cmd prm 1 0x00 DO2H adjust by target device fl cmd prm 2 brid DO2L fixed value fl cmd prm 3 Oxff D03 invalid data fl cmd prm 4 Oxff D04 invalid data switch brid de
73. e checksum of the transmitted command frame or data frame does not match Protect error Write is prohibited in the security setting A boot block is included in the specified range and boot block rewrite is prohibited Negative acknowledgment NACK Command frame data or data frame data is abnormal such as invalid data length LEN or no ETX Time out error C The status frame was not received within the specified time Abnormal termination D E 74 MRG10 error MRG11 error Write error A write error has occurred Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE 4 8 4 Flowchart JS I AN Programming command processing v Wait from previous frame reception until next command transmission tcom Y Command frame transmission processing Programming e Status frame received Yes Status ACK _ Yes M Abnormal termination B m Y fait from previous frame reception tFD2 until next data transmission v Data frame transmission processing User program Y tatus frame received Yes Yes E Y 2 f SN Time out error C No J P4 a Yes Abnormal termination B t lt Yes A Abnormal termination o Se v All data frames transmitt
74. ed _ Yes Status frame received Yes Timed out wrs Yes x number of v blocks gt X Yes Time out error C Y Nt J x KC A Abnormal termination E Normal completion A P M Application Note U19735EJ1VOAN 75 CHAPTER 4 UART COMMUNICATION MODE 4 8 5 Sample program The following shows a sample program for Programming command processing KAKAK KAKAK RARA RARE RRA RARA RR RRA ARRE RE RRA RARA RR RRA RARE ckck ck ck ckckck ck ko kockok J R Write command p KAKA KAKAK AKK RARA RK EKER RR RRA RRA RRE RE RRA RARA RR RRA RAR ERA ARA RA ck kc ko kk J PRAT 132 Op start address i u32 bottom end address r u16 error code KAKAK KAKAK RARA RRE RARA RR RR RRA ARRE RE RRA RARA RR kckckckckckckockck AR RA ko kc RARAS define fl_st2_ua l ua sfrm OFS STA PLD 1 ul6 fl ua write u32 top u32 bottom ul6 rc u32 send_head send_size bool is_end ul6 block_num block_num get_block_num top bottom get block num KAKA KAKAK AKK AK KAKAK RE RARE RAR RARE RE RR AR RA RRA Je set params v KAKA KAKAK AKK AK KAKAK AKK e RARA RR RARE AK RR ck ck RA kc ko ko ko kJ set range prm fl cmd prm top bottom set SAH SAM SAL EAH EAM EAL f ECkCkckckckokckckckckckokokokoko kc she ke ke e RARA RRA RARE RE RAR RA ko kc ko kk x send command amp check status x KAKA KAKAK AKK AK KAKA KA
75. ence lt 1 gt Waits from the previous frame reception until the next command transmission wait time tcom lt 2 gt The Checksum command is transmitted by command frame transmission processing lt 3 gt A time out check is performed from command transmission until status frame reception If a time out occurs a time out error C is returned time out time twr16 lt 4 gt The status code is checked When ST1 ACK Proceeds to lt 5 gt When ST1 s ACK Abnormal termination B lt 5 gt A time out check is performed until data frame checksum data reception If a time out occurs a time out error C is returned time out time trn1 lt 6 gt The received data frame checksum data is checked If data frame is normal Normal completion A If data frame is abnormal Data frame error D 4 13 3 Status at processing completion Status at Processing Completion Status Code Description Normal Normal acknowledgment The command was executed normally and checksum data was completion A ACK acquired normally Abnormal Parameter error The specified start end address is out of the flash memory termination B range or the start end address is not the start end address of the block Checksum error The checksum of the transmitted command frame does not match Negative acknowledgment Command frame data is abnormal such as invalid data length NACK LEN or no ETX Time out error C The status frame or data frame w
76. er ete ACK Se Yes No No Ya K Yes Goto lt 2 gt E matura Normal oo B Du CE MM Note Do not exceed the retry count for the reset command transmission up to 16 times 56 Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE 4 4 2 Description of processing seguence lt 1 gt Wait state wait time toc lt 2 gt The Reset command is transmitted by command frame transmission processing lt 3 gt A time out check is performed from command transmission until status frame reception If a time out occurs a time out error C is returned time out time tiro lt 4 gt The status code is checked When ST1 ACK Normal completion A When ST1 z ACK The retry count trs is checked The sequence is re executed from lt 2 gt if the retry count is not over If the retry count is over the processing ends abnormally B 4 4 3 Status at processing completion Status at Processing Completion Status Code Description Normal Normal acknowledgment The command was executed normally and synchronization completion A ACK between the programmer and the 78K0 Kx2 L has been established Abnormal Checksum error The checksum of the transmitted command frame does not termination B match Negative acknowledgment Command frame data is abnormal such as invalid data length NACK LEN or no ETX Time out error C The status frame was not received within the specified time Applic
77. erify Command from 78K0 Kx2 L to Programmer STX LEN Data SUM ETK 02H 01H ST1 a Checksum 03H Remark ST1 a Command reception result 3 6 3 Data frame and status frame Figure 3 16 shows the format of a frame that includes data to be verified and Figure 3 17 shows the status frame for the data Figure 3 16 Data Frame of Data to Be Verified from Programmer to 78K0 Kx2 L STX LEN Data SUM ETK ETB 00H to FFH 02H Verify Data Checksum 03H 17H 00H 256 Remark Verify Data User program to be verified 36 Application Note U19735EJ1VOAN CHAPTER 3 DESCRIPTION OF COMMAND PROCESSING Figure 3 17 Status Frame for Data Frame from 78K0 Kx2 L to Programmer STX LEN Data SUM ETX 02H 02H ST1 b ST2 b Checksum 03H Remark ST1 b Data reception check result ST2 b Verify result Note Even if a verify error occurs in the specified address range ACK is always returned as the verify result The status of all verify errors are reflected in the verify result for the last data Therefore the occurrence of verify errors can be checked only when all the verify processing for the specified address range is completed See 4 9 Verify Command for details about the flowchart of the processing sequence between the programmer and the 78K0 Kx2 L the flowchart of command processing and the sample program Application Note U19735EJ1VOAN 37 CHAPTER 3
78. es must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels I O settings or contents of registers A device is not initialized until the reset signal is received A reset operation must be executed immediately after power on for devices with reset functions POWER ON OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface as a rule switch on the external power supply after switching on the internal power supply When switching the power supply off as a rule switch off the external power supply and then the internal power supply Use of the reverse power on off sequences may result in the application of an overvoltage to the internal elements of the device causing malfunction and degradation of internal elements due to the passage of an abnormal current The correct power on off sequence must be judged separately for each device and according to related specifications governing the device INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I O pull up power supply while the device is not powered The current injection that results from in
79. esas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equ
80. fault case 0x00 br BR 125000 break case 0x01 br BR 250000 break case 0x02 br BR 500000 break fl wait tCOM wait before sending command put cmd ua FL COM SET BAUDRATE 1 5 fl cmd prm send Baudrate Set command set flbaud br change baud rate set uart0 br br change baud rate h w retry tRS while 1 fl wait tWT10 put cmd ua FL COM RESET 1 fl cmd prm send RESET command rc get sfrm ua fl ua sfrm tWTO TO get status frame if rc if retry continue else return rc break got ACK switch rc case FLC_NO_ERR return rc break case A case FLC_DFTO_ERR return rc break case C Lf default return rc break case B return rc j Application Note U19735EJ1VOAN 63 64 CHAPTER 4 UART COMMUNICATION MODE 4 6 Chip Erase Command 4 6 1 Processing sequence chart Chip Erase command processing sequence Programmer lt 1 gt Wait from previous frame reception until next command transmission tcom lt 2 gt 78K0 Kx2 L Chip Erase command frame transmission Time out lt 3 gt Time out check for i occurs status frame reception WTI Status frame m within specified time 3 Ne S 3 9 m C gt f lt 4 gt Status frame reception Reception status ACK other than ACK Other than ACK PE E Normal wee Application Note U19735EJ1VOAN CHA
81. hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document but Ren
82. ication to target See Figure 1 4 Mode setting reset release See 1 5 Selection of communication mode pulse input See 1 5 Y Synchronization processing Reset command See 3 1 Baud rate setting see 3 2 Silicon signature acquisition Silicon Signature command See 3 8 jani v Command execution T Processing No completed lt ves Target power shutdown Reset input and power shutdown during rewriting is processing prohibited because security information may be lost See 1 6 i S End Remark The example of each command execution is shown in Figure 1 7 Application Note U19735EJ1VOAN CHAPTER 1 FLASH MEMORY PROGRAMMING 26 Figure 1 7 General Command Execution Flow at Flash Memory Rewriting General command flow Block Blank Check command See 3 7 p Block Erase command execution See 3 4 Programming command execution See 3 5 Verify command execution See 3 6 Security Set command execution See 3 11 This command is used to check whether data communication between programmer and target device was normally completed Application Note U19735EJ1VOAN CHAPTER 2 COMMAND DATA FRAME FORMAT The programmer uses the command frame to transmit commands to the 78K0 Kx2 L The 78K0 Kx2 L uses the data frame
83. ing from disable to enable is not possible If an attempt is made to perform such a setting a protect error 10H will occur If such setting is required all of the security flags must first be initialized by executing the Chip Erase command the Block Erase command cannot be used to initialize the security flags If chip erase or boot block rewrite has been disabled however chip erase itself will be impossible so the settings cannot be erased from the programmer Re confirmation of security setting execution is therefore recommended before disabling chip erase due to this programmer specification 3 11 2 Command frame and status frame Figure 3 29 shows the format of a command frame for the Security Set command and Figure 3 30 shows the status frame for the command Figure 3 29 Security Set Command Frame from Programmer to 78K0 Kx2 L SOH LEN COM command SUM ETX Information 00H 00H 01H 03H AOH Security Set Checksum 03H y Set xed fixed Figure 3 30 Status Frame for Security Set Command from 78K0 Kx2 L to Programmer STX LEN Data SUM ETX 02H 01H ST1 a Checksum 03H Remark ST1 a Command reception result 50 Application Note U19735EJ1VOAN CHAPTER 3 DESCRIPTION OF COMMAND PROCESSING 3 11 3 Data frame and status frame Figure 3 31 shows the format ofa security data frame and Figure 3 32 shows the status frame for the data Figure 3 31 Security Data
84. ing j N m Timed out tro i trb2 Yes ANS ors A Reception time out error M P DA Yes Data length LEN received a xS Reception time out error gt NS 4 4 A received Timed out Yes Y NG J No TEN bytes Yes e gt Yes Checksum data _ SUM received _ No MX Timed out Mo toT Yes Y Reception time out error Wa eh p Yes gt Data frame ote Last data frame footer ETX 03H e received a or footer other than those of last data PERS Pa frame ETB 17H No Y e Timed out tor Yes v g 4 N Reception time out error e x i T Checksum error 7 95 No q y E Endofdataframe cu ecksum error reception M i Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE 4 4 Reset Command 4 4 1 Processing sequence chart Reset command processing sequence Programmer 78K0 Kx2 L lt 1 gt Wait toc lt 2 gt Reset command frame transmission Time ot Time out check for EIU 3 x occurs 8 status frame reception twro s frame received within specified time H C B ime out error C Wa lt 4 gt Status frame reception Reception MT ACK other than ACK Other than ACK Y hey count ov
85. ipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certai
86. k get start address of start block bottom get bottom addr eblk get end address of end block set range prm fl cmd prm top bottom set SAH SAM SAL EAH EAM EAL wt2 max make wt2 max sblk eblk fl wait tCOM wait before sending command put cmd ua FL COM ERASE BLOCK 1 6 fl cmd prm send ERASE CHIP command rc get sfrm ua fl ua sfrm wt2 max get status frame switch rc case FLC NO ERR return rc break case A case FLC DFTO ERR return rc break case C default return rc break case B return rc Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE 4 8 Programming Command 4 8 1 Processing sequence chart Programming command processing sequence Programmer 78K0 Kx2 L Wait from previous frame reception until next command transmission teom lt 2 gt Programming command frame transmission SS Time out uM Time out check for _ occurs lt 3 gt 5 status frame reception Time out error C gt Status frame received within specified time Status frame reception Reception status y ACK other than ACK A Al Wait from previous frame reception s until next data frame transmission troz Ex N N lt 6 gt Data frame user data transmission Time out reos Time out check for a WANG st
87. ksum of the transmitted command frame does not match Protect error Write block erase or chip erase is prohibited in the security setting A boot block is included in the specified range and boot block rewrite is prohibited Negative acknowledgment NACK Command frame data is abnormal such as invalid data length LEN or no ETX MRG10 error An erase error has occurred Time out error C The status frame was not received within the specified time Application Note U19735EJ1VOAN 69 CHAPTER 4 UART COMMUNICATION MODE 4 7 4 Flowchart 2m Erase command i processing v Wait from previous frame reception until next command transmission tcom v Command frame transmission processing Block Erase Status frame No received No twr2 Time out error C Normal completion A 70 Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE 4 7 5 Sample program The following shows a sample program for Block Erase command processing EE AS px EJ Erase block command f VA KKK KKK KK K KK K K K K K K A K AK K A KKK AS i u8 block block number PES r ul6 error code y f kk ke kk kk kk kc ec sk he ke he e RAR KAKAK AKK AK RRA RRA RA ERE RARE RAR RR RR RARA ARAS ul6 fl_ua_erase_blk ul6 sblk ul6 eblk ul6 c u32 wt2 max u32 top bottom top get top addr sbl
88. lt 7 gt The first start block number is 1 and the number of blocks to be erased is 127 the values that satisfy Condition 1 are therefore 1 2 4 8 16 32 and 64 Moreover the value that satisfies Condition 2 is 1 and the value that satisfies Condition 3 is 1 so the number of blocks to be selected and erased simultaneously is 1 only block 1 is then erased After block 1 is erased the next start block number is 2 and the number of blocks to be erased is 126 the values that satisfy Condition 1 are therefore 1 2 4 8 16 32 and 64 Moreover the values that satisfy Condition 2 are 1 and 2 the value that satisfies Condition 3 is 2 so the number of blocks to be selected and erased simultaneously is 2 blocks 2 and 3 are then erased After blocks 2 and 3 are erased the next start block number is 4 and the number of blocks to be erased is 124 the values that satisfy Condition 1 are therefore 1 2 4 8 16 32 and 64 Moreover the values that satisfy Condition 2 are 1 2 and 4 the value that satisfies Condition 3 is 4 so the number of blocks to be selected and erased simultaneously is 4 blocks 4 to 7 are then erased After blocks 4 to 7 are erased the next start block number is 8 and the number of blocks to be erased is 120 the values that satisfy Condition 1 are therefore 1 2 4 8 16 32 and 64 Moreover the values that satisfy Condition 2 are 1 2 4 and 8 the value that satisfies Condition 3 is 8 so the number of block
89. ltaneously is 2 blocks 6 and 7 are then erased After blocks 6 and 7 are erased the next start block number is 8 and the number of blocks to be erased is 3 the values that satisfy Condition 1 are therefore 1 and 2 Moreover the values that satisfy Condition 2 are 1 and 2 the value that satisfies Condition 3 is 2 so the number of blocks to be selected and erased simultaneously is 2 blocks 8 and 9 are then erased After blocks 8 and 9 are erased the next start block number is 10 and the number of blocks to be erased is 1 the value that satisfies Condition 1 is therefore 1 This also satisfies Conditions 2 and 3 so the number of blocks to be selected and erased simultaneously is 1 block 10 is then erased Therefore simultaneous selection and erasure is executed four times 5 6 and 7 8 and 9 and 10 to erase blocks 5 to 10 so M 4 is obtained Application Note U19735EJ1VOAN CHAPTER 5 FLASH MEMORY PROGRAMMING PARAMETER CHARACTERISTICS Block configuration when executing simultaneous selection and erasure when erasing blocks 5 to 10 lt Block number gt User area On a E T E T Th o A lt Range of blocks that can be selected and erased simultaneously gt Application Note U19735EJ1VOAN 115 CHAPTER 5 FLASH MEMORY PROGRAMMING PARAMETER CHARACTERISTICS Example 3 116 Erasing blocks 25 to 73 N number of blocks to be erased 49 lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt
90. mmand transmission tcom v Command frame transmission processing Chip Erase No Status frame received Yes twr1 Va Time out error C Status ACK NO Normal completion A Abnormal termination B Application Note U19735EJ1VOAN No CHAPTER 4 UART COMMUNICATION MODE 4 6 5 Sample program The following shows a sample program for Chip Erase command processing FAR RE KAKAK RR K K K AK K K K K K K K RR ck ckckckckckckckckchckckck ck kckckckckckckckckchckckckckckck ckckck ck KKK fi x Erase all chip command T EJ EE AS r u16 error code E FAR KKK KK K RRA RE KR KER KEK KK ckckckckckckckckchckckck KKK KK RR KKK KKK KK KKK KERR KKK KK ul6 fl ua erase all void ul6 c fl wait tCOM wait before sending command put cmd ua FL COM ERASE CHIP 1 fl cmd prm send ERASE CHIP command rc get sfrm ua fl ua sfrm tWT1 MAX get status frame Jed switch rc case FLC NO ERR return rc break case A case FLC DFTO ERR return rc break case C default return rc break case B Jj return rc Application Note U19735EJ1VOAN 68 CHAPTER 4 UART COMMUNICATION MODE 4 7 Block Erase Command 4 7 1 Processing sequence chart Block Erase command processing sequence Programmer 78K0 Kx2 L lt 1 gt Wait from previous frame
91. n of execution count M of simultaneous selection and 6raSure 111 5 4 UART Communication Mode oooccccconnniccconnnnccccnnnnnccccnnn cercana nene errar 118 APPENDIX A CIRCUIT DIAGRAMS REFERENCE 0oooccccoccoonnccccnnnnnnncnnnnnnnnnnnnnnnrnnnnnnrrnnnnnrrrnnnnanennnnas 121 10 Application Note U19735EJ1VOAN CHAPTER 1 FLASH MEMORY PROGRAMMING To rewrite the contents of the internal flash memory of the 78K0 Kx2 L a dedicated flash memory programmer hereafter referred to as the programmer is usually used This Application Note explains how to develop a dedicated programmer 1 1 Overview The 78K0 Kx2 L incorporates firmware that controls flash memory programming The programming to the internal flash memory is performed by transmitting receiving commands between the programmer and the 78K0 Kx2 L via serial communication Figure 1 1 System Outline of Flash Memory Programming in 78K0 Kx2 L 78K0 Kx2 L Firmware Serial communication Programmer Flash memory Application Note U19735EJ1VOAN 11 CHAPTER 1 FLASH MEMORY PROGRAMMING 1 2 System Configuration Examples of the system configuration for programming the flash memory are illustrated in Figure 1 2 Figure 1 2 illustrates how to program the flash memory with the programmer under control of a host machine Depending on how the programmer is connected the programmer can be used in a standalone mode without using the host ma
92. n period when the input level passes through the area between Vit MAX and Vin MIN HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down circuitry Each unused pin should be connected to Voo or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device PRECAUTION AGAINST ESD A strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequate When it is dry a humidifier should be used It is recommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devic
93. n status ST1 Es Other than ACK A ACK other than ACK Cosma termination iB Tm p M 57 a Reception status ST2 N St ACK other than ACK WA Other than ACK ACK Abnormal termination a LA n V h All data traines transmitted No x er _ Yes No Go to lt 5 gt Yes y ona completion IN NT Ly Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE 4 9 2 Description of processing sequence lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt b gt lt 6 gt lt 7 gt lt 8 gt Waits from the previous frame reception until the next command transmission wait time tcom The Verify command is transmitted by command frame transmission processing A time out check is performed from command transmission until status frame reception If a time out occurs a time out error C is returned time out time turc The status code is checked When ST1 ACK Proceeds to lt 5 gt When ST1 z ACK Abnormal termination B Waits from the previous frame reception until the next data frame transmission wait time trs User data for verifying is transmitted by data frame transmission processing A time out check is performed from user data transmission until status frame reception If a time out occurs a time out error C is returned time out time twr The status code ST1 ST2 is checked also refer to the processing sequence chart and flowchart When ST1 A
94. n use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics
95. nce program for a specific application The recommended applications of an NEC Electronics product depend on its quality grade as indicated below Customers must check the quality grade of each NEC Electronics product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC Electronics products is Standard unless otherwise expressly specified in NEC Electronics data sheets or data books etc If customers wish to use NEC Electronics products in applications not intended by NEC Electronics they must contact an NEC Electronics sales representative in advance to determine NEC Electronics willingness to support a given application Note 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries 2 NEC Electronics products means any product developed or
96. nd frame data is abnormal such as invalid data length LEN or no ETX Time out error C The status frame or data frame was not received within the specified time Abnormal MRG10 error termination MRG11 error D E Write error Writing security data has failed 100 Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE 4 14 4 Flowchart N Security Set command processing until next command transmission com Command frame transmission processing Security Set M y X lt Status Ack NO EN e Yes y Abnormal termination B M J v Vat from previous frame reception until next data frarretrenerission WP Data frame transmission processing Security data EE Status frame Tm received Yes lt E C Timed out xs Now ria Yes Time out error C O IM V y N lt Status ACK P No Yes Fd TN Abnormal termination D A J Status frame No received Yes No lt e Time out error C C Fy C SN Abnormal termination E Normal completion A a MEL NS Application Note U19735EJ1VOAN 101 CHAPTER 4 UART COMMUNICATION MODE 4 14 5 Sample program The following shows a sample program for Security Set command processing AKK KAKAK KA KAKAK KK KK AKA KAKAK KAK
97. nd frame for the Chip Erase command and Figure 3 6 shows the status frame for the command Figure 3 5 Chip Erase Command Frame from Programmer to 78K0 Kx2 L SOH LEN COM SUM ETK 01H 01H Sn Checksum 03H u Chip Erase Figure 3 6 Status Frame for Chip Erase Command from 78K0 Kx2 L to Programmer STX LEN Data SUM ETX 02H 01H ST1 Checksum 03H Remark ST1 Chip erase result See 4 6 Chip Erase Command for details about the flowchart of the processing sequence between the programmer and the 78K0 Kx2 L the flowchart of command processing and the sample program 32 Application Note U19735EJ1VOAN CHAPTER 3 DESCRIPTION OF COMMAND PROCESSING 3 4 Block Erase Command 3 4 1 Description This command is used to erase the content of flash memory of the block with the specified number A block can be specified with the first address of the block where erasing starts and the last address where erasing ends Successive multiple blocks can be specified Erasing cannot be performed however if erasing is prohibited due to the security setting see 3 11 Security Set Command 3 4 2 Command frame and status frame Figure 3 7 shows the format of a command frame for the Block Erase command and Figure 3 8 shows the status frame for the command Figure 3 7 Block Erase Command Frame from Programmer to 78K0 Kx2 L SOH LEN COM Command Information SUM ETK 22H
98. om the programmer Protect error Error returned if an attempt is made to execute processing that is prohibited by the Security Set command Negative acknowledgment NACK Negative acknowledgment MRG10 error Erase verify error MRG11 error Internal verify error or blank check error during data write Read error Error returned if reading security information fails Write error Write error When a dedicated programmer is developed however the processing may be retried without problem from the wait Reception of a checksum error or NACK is treated as an immediate abnormal end in this manual immediately before transmission of the command that results a checksum error or NACK In this event limiting the retry count is recommended for preventing infinite repetition of the retry operation Although not listed in the above table if a time out error BUSY time out or time out in data frame reception during UART communication occurs it is recommended to shutdown the power supply to the 78K0 Kx2 L refer to 1 6 Shutting Down Target Power Supply and then connect the power supply again 16 Application Note U19735EJ1VOAN CHAPTER 1 FLASH MEMORY PROGRAMMING 1 5 Power Application and Setting Flash Memory Programming Mode To rewrite the contents of the flash memory with the programmer the 78K0 Kx2 L must first be set to the flash memory programming mode The RESET TOOLD and TOOLC pins are set to
99. on sessesssesesseeeeeeneeeeeeneeenneennnenneen nennen nennen enne 61 45 4 tElIOWChalt deter eee get in b ee ap 62 4 5 5 Samiple programs eeu ec UEBER BEER ROM BD 63 4 6 Chip Erase Command er encia 64 46 1 Processing sequernce chart t ERG EE hg i a NG gga Waa lo ete ee a in 64 4 6 2 Description of processing sequence cccooncccnnoocccononnncnnnnnnonnnnn cnn nano eene eene nnne nnne nennen 65 4 6 3 Status at processing completion sessssssessseeeeeeeenneen nennen nennen nennen enne ns 65 46 4 A eed eae hie deett e vesti a Ue b ecc e A ERI 66 4 6 5 Sampleprogralmisz iue e Pest ete esee ti 67 4 7 Block Erase Command 2 ii nn re aa aaa a nga bawane daka nganaake abasa wajan 68 4 7 1 Processing Seduence chari saanane anana a Dan E ED r Uga ENG a GU Ga ae a nga EN ag AE E ngah nah kaa 68 4 7 2 Description of processing sequence sasana eaaa aana anna anaa rn nr rr ERP KKK 69 4 7 3 Status at processing completion ooonccnnnccninncnncccnoncnnncncnonnnnnnnn non ncono crac ran rra rca nc 69 2 7 4 Flowchart tena ea a a pn nga ng eaaa aa adas Kapa na tai rs 70 4 7 5 Sample progra Mrina EA EE ne GN ov vide NT ake 71 Application Note U19735EJ1VOAN 4 8 Programming Command cocine 72 4 8 1 Processing sequence chart sorses a naa aa E a wa a aaa aaa a ga a ad an a Na aas aa sada 72 4 8 2 Description of processing seguence asarana a
100. products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics ENESAS Application Note 78K0 Kx2 L 78KO Ix2 8 bit Single Chip Microcontrollers Flash Memory Programming Programmer 78K0 KY2 L uPD78F0550 78F0551 78F0552 78F0555 78F0556 78F0557 78K0 KA2 L 4PD78F0560 78F0561 78F0562 78F0565 78F0566 78F0567 78K0 KB2 L 4PD78F0571 78F0572 78F0573 78F0576 78F0577 78F0578 78K0 KC2 L uPD78F0581 78F0582 78F0583 78F0586 78F0587 78F0588 78K0 1Y2 HPD78F0740 78F0741 78F0742 78F0750 78F0751 78F0752 78K0 1A2 1PD78F0743 78F0744 78F0753 78F0754 78KO IB2 HPD78F0745 78F0746 78F0755 78F0756 Document No U19735EJ1VOANDO 1st edition Date Published August 2009 N O NEC Electronics Corporation 2009 Printed in Japan MEMO 2 Application Note U19735EJIVOAN NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between Vi MAX and Vin MIN due to noise etc the device may malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transitio
101. put of such a signal or I O pull up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device Application Note U19735EJ1VOAN The information in this document is current as of May 2009 The information is subject to change without notice For actual design in refer to the latest publications of NEC Electronics data sheets etc for the most up to date specifications of NEC Electronics products Not all products and or types are available in every country Please check with an NEC Electronics sales representative for availability and additional information e No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others Des
102. r e 6 6 GND AD7 21 5 AT DO8 A7 ng 27 AB 2215 ao 26 ETA 9 a S e ale aio 23 EIA 4 8 38 8 i now Ai 2 Eu a a al al BS A12 N a 2 al e 35 RD 24 oc A3 28 Aa L3 FEN vo 31 yoo iue 52 pais y lt 2 vec Ay 39 EVEN 36 Ais EN GND MS5M5408BFP 70H U4 gt GND GND ADO 13 12 A0 ADI mun Aon AL AD2 15 003 A 10 AZ AD3 17 oj 1 ADA 18 rad MB M ADS 19 006 As AS ADE 20 507 e S 6 AD7 21 5 AT Dos AI P 22 jara A9 mo 23 ALO WR 29 1 25 ALI VDD de MITA A12 12 RD 24 A13 8 A13 mas Ala 33K ais PL m voo me 2 A16 x 32 30 A17 RL X hizo Ar Als de A18 GND a RESET J EA me MSMS408BFP 70H US i Bises s x an y 78K0 Kx2 L Target Board for Monowire UART I F RESETKEY 10 E 10u c c 1 10p 10p 1 1 LL TG VDD VDO ee ee lt lt lt 4 TC ner 1 GND GND 1 1 n i ie BV 3 3V Interactive Level Shifter i ab ia Ls 1 1 AVSS i 1 1 TG RESET H 1 RESET 1 1 1 1 1 yet TOOLDO 1 5V 3 3V Level Shifter Target I F IG xD TOOLD1 f 1 TG TxD 1 1 1 2 woo 2 1 i o El s zi i i i TOOLCO REGC o 1 i 4 i a m Be S mermo 97 I TOOLCL i 8 8 1 1 ot c101 ag GND DIR im f E 12 12 D R102 TOOLO 1 Sw101 U101 1 14 SN74LVC2T45 14 1 T8KO Kx2 L 1 1 10k f CN3 A i a 2 1 s t o S i i xi el i AL Bl 1 E 1 1 1 A2 B2 1 1 1 1 t GND DR 1 i 1 1 SN74LVC2T45 1 H Target I F 1 TG GND Mo ol2 TG_VDD 1 i TG RESET 3o oli 1 1 i ui 1 I
103. r Mode Setting 55 0 us Ready start time from RESET 1 5 ms Maximum Setup time 13 bit counter Note 30 kHz 50 2 Detailed mode transition time transition from the programming mode to normal mode RESET to TOOLC TOOLDJ 500 0 us Minimum Low width TOOLC and TOOLD 110 0 us Minimum High width TOOLC and TOOLD Application Note U19735EJ1VOAN 107 CHAPTER 5 FLASH MEMORY PROGRAMMING PARAMETER CHARACTERISTICS 5 2 2 Programming characteristics Data Data frame transmission transmission EEC From status is transmission until data frame tro transmission From status frame transmission until data frame iro transmission 2 From status frame transmission until data frame tros reception 3 From status frame transmission until command frame tcom reception Notes 1 Enable successive reception for the programmer 2 Time for one block transmission Remark The waits are defined as follows lt DR tro3 tcov The 78K0 Ix2 can execute the next communication after the MIN time has elapsed after completion of the current communication The programmer needs to transmit the following data within the period from the MIN time to the MAX time after completion of the current communication The MAX time is not specified but use approximately 3 seconds tpr trp1 1FD2 gt The 78K0 Ix2 can execute the next communication after the MIN time has elapsed after completion of the current communic
104. r of blocks to be selected and erased simultaneously is 32 blocks 32 to 63 are then erased After blocks 32 to 63 are erased the next start block number is 64 and the number of blocks to be erased is 10 the values that satisfy Condition 1 are therefore 1 2 4 and 8 Moreover the values that satisfy Condition 2 are 1 2 4 and 8 the value that satisfies Condition 3 is 8 so the number of blocks to be selected and erased simultaneously is 8 blocks 64 to 71 are then erased After blocks 64 to 71 are erased the next start block number is 72 and the number of blocks to be erased is 2 the values that satisfy Condition 1 are therefore 1 and 2 Moreover the values that satisfy Condition 2 are 1 and 2 the value that satisfies Condition 3 is 2 so the number of blocks to be selected and erased simultaneously is 2 blocks 72 and 73 are then erased Therefore simultaneous selection and erasure is executed six times 25 26 and 27 28 to 31 32 to 63 64 to 71 and 72 and 73 to erase blocks 25 to 73 so M 6 is obtained Application Note U19735EJ1VOAN CHAPTER 5 FLASH MEMORY PROGRAMMING PARAMETER CHARACTERISTICS Block configuration when executing simultaneous selection and erasure when erasing blocks 25 to 73 lt Block number gt lt Range of blocks that can be selected and erased simultaneously gt Application Note U19735EJ1VOAN 117 CHAPTER 5 FLASH MEMORY PROGRAMMING PARAMETER CHARACTERISTICS
105. received C Time out error C within specified time 4 Status frame reception B N eo Reception status A ACK other than ACK Be Other than ACK A a En P ACK Ca i IN W Kanang termination B lt 5 gt KA r trD2 lt 6 gt Data frame security data transmission Time out___ ___ Time out check for occurs S gt ion WT14 lt status frame reception Status frame received within specified time lt 8 gt Status frame reception ie Reception status N NG ACK other than ACK WA Other than ACK aas quem termination iB ACK Time out 3 ime 9 Time out check for twris occurs status frame reception Status frame received within specified time p 10 Status frame reception Time out error C p 2 Reception status N 4 d ACK other than ACK E Other than ACK s m3 ACK 22d on oS sc be Ab ination E f ke normal termination E KOR completion A Sa _ us a Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE 4 14 2 Description of processing sequence lt 1 gt Waits from the previous frame reception until the next command transmission wait time tcom lt 2 gt The Security Set command is transmitted by command frame transmission processing lt 3 gt A time out check is performed from command transmission until status frame reception If a time out occurs a time out error
106. s internal verify Therefore the Status command for this internal verify must be transmitted 3 5 2 Command frame and status frame Figure 3 9 shows the format of a command frame for the Programming command and Figure 3 10 shows the status frame for the command Figure 3 9 Programming Command Frame from Programmer to 78K0 Kx2 L SOH LEN COM Command Information SUM ETK 40H 01H 07H 9 SAH SAM SAL EAH EAM EAL Checksum 03H Programming Remark SAH SAM SAL Write start addresses EAH EAM EAL Write end addresses Figure 3 10 Status Frame for Programming Command from 78K0 Kx2 L to Programmer STX LEN Data SUM ETK 02H 01H ST1 a Checksum 03H Remark ST1 a Command reception result 3 5 3 Data frame and status frame Figure 3 11 shows the format of a frame that includes data to be written and Figure 3 12 shows the status frame for the data Figure 3 11 Data Frame to Be Written from Programmer to 78K0 Kx2 L STX LEN Data SUM ETX ETB H to FFH oap Write Data Checksum 03H 17H 00H 256 Remark Write Data User program to be written Figure 3 12 Status Frame for Data Frame from 78K0 Kx2 L to Programmer STX LEN Data SUM ETX 02H 02H ST1 b ST2 b Checksum 03H Remark ST1 b Data reception check result ST2 b Write result 34 Application Note U19735EJ1VOAN CHAPTER 3 DESCRIPT
107. s to be selected and erased simultaneously is 8 blocks 8 to 15 are then erased After blocks 8 to 15 are erased the next start block number is 16 and the number of blocks to be erased is 112 the values that satisfy Condition 1 are therefore 1 2 4 8 16 32 and 64 Moreover the values that satisfy Condition 2 are 1 2 4 8 and 16 the value that satisfies Condition 3 is 16 so the number of blocks to be selected and erased simultaneously is 16 blocks 16 to 31 are then erased After blocks 16 to 31 are erased the next start block number is 32 and the number of blocks to be erased is 96 the values that satisfy Condition 1 are therefore 1 2 4 8 16 32 and 64 Moreover the values that satisfy Condition 2 are 1 2 4 8 16 and 32 the value that satisfies Condition 3 is 32 so the number of blocks to be selected and erased simultaneously is 32 blocks 32 to 63 are then erased After blocks 32 to 63 are erased the next start block number is 64 and the number of blocks to be erased is 64 the values that satisfy Condition 1 are therefore 1 2 4 8 16 32 and 64 Moreover the values that satisfy Condition 2 are 1 2 4 8 16 32 and 64 the value that satisfies Condition 3 is 64 so the number of blocks to be selected and erased simultaneously is 64 blocks 64 to 127 are then erased Therefore simultaneous selection and erasure is executed seven times 1 2 and 3 4 to 7 8 to 15 16 to 31 32 to 63 and 64 to 127 to erase blocks
108. slave devices when performing UART communication 18 Application Note U19735EJ1VOAN CHAPTER 1 FLASH MEMORY PROGRAMMING 1 5 2 Mode setting flowchart Transition processing to programming mode RESET pin low output TOOLC TOOLD pin low output Voo pin high output Target power supply on Wait T1 TOOLC pin high output TOOLD pin high output Start of time measurement until start of RESET pin high output Wait T3 o TOOLC pin low output T12 Wait T4 TOOLC pin high output Yes Have pulses been output from TOOLC twice Application Note U19735EJ1VOAN T6 19 CHAPTER 1 FLASH MEMORY PROGRAMMING TOOLD pin low output T7 TOOLD pin high output Have pulses been output from TOOLD 7 times Yes No Have pulses been output from TOOLC or TOOLD 3 times Yes No Has T12 elapsed Yes No 20 Application Note U19735EJ1VOAN CHAPTER 1 FLASH MEMORY PROGRAMMING Ready pulse check Initialization of UART hardware Normal termination Abnormal termination Application Note U19735EJ1VOAN 21 CHAPTER 1 FLASH MEMORY PROGRAMMING 1 5 3 Sample program The following shows a sample program for mode setting processing SAS J connect to Flash device KAKA KAKAK AKK KK KAKA KAKAK KAKAK AKA KAKA KAKA RA RR REE KAKA RA RR ck ck k ck k ko kk J
109. ssing sequence chart i o irisi aaa A a na Bak a a an Apa na anaa aaa naa asa 99 4 14 2 Description of processing seguence asana aanaa anane anana anaa nr near rre enn mener nnne 100 4 14 3 Status at processing completion saessa eaaa eaaa a anana n eee eee eee eee cnn anana Naane anana nnne nnne 100 414 4 o eai saa ds 101 4145 Sample program uci teo dene ai ana Sa ge iom rhe e EE ride nrc e ag gagang a Dana Ba 102 CHAPTER 5 FLASH MEMORY PROGRAMMING PARAMETER CHARACTERISTICS 104 5 1 Flash Memory Parameter Characteristics of 78K0 Kx2 L eren 104 5 1 1 Flash memory programming mode setting time 104 5 1 2 Programmirig characteristiCs sa bana toot rni tte dete co fne tdt e a gale s 105 51 3 Command characteristics 2 5 tein cec iue ee cree dee NGA E i E e c e ea Ede 106 Application Note U19735EJ1VOAN 9 5 2 Flash Memory Parameter Characteristics of 78K0 lX2 seen 107 5 2 1 Flash memory programming mode setting time 107 5 2 2 Programming characteristics aa saang inaa aa a a ga gak e dan a paia SK KKK nnns aga ka aa a NGE 108 5 2 3 Command characteristics ccoo ia dad dai 109 5 3 Simultaneous Selection and Erasure Performed by Block Erase Comman 110 5 3 1 Calculation of number of blocks to be selected and erased simultaneously 110 5 3 2 Calculatio
110. sssneesessatess 36 3 6 3 Data frame and status trame 55 Ta a aa a ak ga a age E a a a aa aa a nnn aaa na nnn nnn nnne 36 3 7 Block Blank Check Command eee eee eee eee anana anana nnne KRAS SK KEKS SAKRA nnn 38 37 Descriptiva cit ei 38 Application Note U19735EJ1VOAN 7 3 7 2 Command frame and status fraMe cccccccccccccccncnnnnnnnnnnnnnonononononononononnnnnnnonononnnnnnnnononononenenenenanenes 38 3 8 Silicon Signature Command aana esanewan wan awan anan aw wane wanan anae wnne wanara nawa nawa SA KEE nuin ananas nasa nananana 39 3 8 11 DeScrptiON sasana gan a An a A is 39 3 8 2 Command frame and status frame s0esseenen ene n een aan AKAN AAN ARAN Naane naen aane nana 39 3 8 3 Silicon signature data frame sa a gan ag dc dales a dee ak TS 40 3 8 4 SINGONsIYGh arsana aga coa 42 3 9 Version Get Command saa aaa ae aaa eese Na a KA a a a a aa aa a kaga a a a daa aa nawa na aaa 47 E PIE eliT AT 47 3 9 2 Command frame and status frame asasaran ene eaaa anaa nan nnnn rra 47 3 9 3 Version data frame i c pan ajan td 48 3 10 Checksum COMMA d ito 49 31051 D S NDUON tenes side AA aa dea ye cya de aie i ae ee ab ct eo 49 3 10 2 Command frame and status frame naen anae RENANE RAN anan KRK een eee 49 3 10 3 Checksum data ames as tet ak dea A NG eae ea 49 3 11 Security Set Command eiii cc 50 311 1 Description as hl ak aa aaa ee A
111. te Writes data to a specified area in the flash memory Verify Verify Compares the contents in a specified area in the flash memory with the data transmitted from the programmer Block Blank Check Blank check Checks the erase status of a specified block in the flash memory Silicon Signature Version Get Checksum Information acquisition Acquires 78K0 Kx2 L information product name flash memory configuration etc Acquires version of the 78K0 Kx2 L and firmware Acquires checksum data of a specified area Security Set Security Sets security information Reset Baud Rate Set Others Detects synchronization in communication Application Note U19735EJ1VOAN Sets the baud rate when UART communication mode is selected 15 CHAPTER 1 FLASH MEMORY PROGRAMMING 1 4 2 Status list The following table lists the status codes the programmer receives from the 78K0 Kx2 L Status Code Table 1 3 Status Code List Status Command number error Description Error returned if a command not supported is received Parameter error Error returned if command information parameter is invalid Normal acknowledgment ACK Normal acknowledgment Checksum error Error returned if data in a frame transmitted from the programmer is abnormal Verify error Error returned if a verify error has occurred upon verifying data transmitted fr
112. to transmit write data or verify data to the programmer A header footer data length information and checksum are appended to each frame to enhance the reliability of the transferred data The following shows the format of a command frame and data frame Figure 2 1 Command Frame Format SOH LEN COM Command information variable length SUM ETX 1 byte 1 byte 1 byte Max 255 bytes 1 byte 1 byte Figure 2 2 Data Frame Format STX LEN Data variable length SUM ETX or ETB 1 byte 1 byte Max 256 bytes 1 byte 1 byte Table 2 1 Description of Symbols in Each Frame Description Command frame header Data frame header Data length information 00H indicates 256 Command frame COM command information length Data frame Data field length Command number Checksum data for a frame Obtained by sequentially subtracting all of calculation target data from the initial value 00H in 1 byte units borrow is ignored The calculation targets are as follows Command frame LEN COM all of command information Data frame LEN all of data Footer of data frame other than the last frame Command frame footer or footer of last data frame The following shows examples of calculating the checksum SUM for a frame Application Note U19735EJ1VOAN 27 CHAPTER 2 COMMAND DATA FRAME FORMAT Command frame No command information is included in the following example of a Chip Erase command fr
113. tor v Transmits 1 byte command information Y Wait between data tor transmissions T v Checksum data SUM transmission y Wait between data transmissions tor v Command frame footer ETX 03H transmission YS End of command frame transmission eS Application Note U19735EJ1VOAN 53 CHAPTER 4 UART COMMUNICATION MODE 4 2 Data Frame Transmission Processing Flowchart 54 Data frame transmission processing Data frame header STX 02H transmission v Wait between data transmissions tor Y Data length LEN transmission lt m bytes lt _ transmitted pro Yes Wait between data transmissions tor Transmits 1 byte data v Wait between data transmissions v Checksum data SUM transmission v Wait between data transmissions Last data frame Yes tor tor No Transmission of last data frame footer ETX 03H Transmission of footer other than those of last data frame ETB 17H 7 N End of data frame transmission M y Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE 4 3 Data Frame Reception Processing Flowchart Data frame reception process
114. tus of the start bit of the reception frame until the MAX time has elapsed For commands without a specified MAX time set the time to approximately 3 seconds Application Note U19735EJ1VOAN 109 CHAPTER 5 FLASH MEMORY PROGRAMMING PARAMETER CHARACTERISTICS 5 3 Simultaneous Selection and Erasure Performed by Block Erase Command The Block Erase command of the 78K0 Kx2 L and 78KO Ix2 is executed by repeating simultaneous selection and erasure which erases multiple blocks simultaneously The wait time inserted during Block Erase command execution is therefore equal to the total execution time of simultaneous selection and erasure To calculate the total execution time of simultaneous selection and erasure the execution count M of the simultaneous selection and erasure must first be calculated M is calculated by obtaining the number of blocks to be erased simultaneously number of blocks to be selected and erased simultaneously The following describes the method for calculating the number of blocks to be selected and erased simultaneously and the execution count M 5 3 1 Calculation of number of blocks to be selected and erased simultaneously The number of blocks to be selected and erased simultaneously should be 1 2 4 8 16 32 64 or 128 depending on which satisfies all of the following conditions Condition 1 Number of blocks to be erased gt Number of blocks to be selected and erased sim
115. ua sfrm tWT12 MAX get status frame switch rc case FLC NO ERR break continue case FLC DFTO ERR return rc break case C default return rc break case B H rc get dfrm ua fl rxdata frm tFD2 MAX get data frame if rc return rc case D H memcpy buf fl rxdata frm OFS STA PLD DFV LEN copy version data return rc case A 94 Application Note U19735EJ1VOAN CHAPTER 4 UART COMMUNICATION MODE 4 13 Checksum Command 4 13 1 Processing seguence chart Checksum command processing seguence 78K0 Kx2 L Programmer Wait from previous frame reception Sl until next command transmission tcom lt 2 gt Checksum command frame transmission Wg Time out check for c 3 x Time out 9 status frame reception turis occurs 7 Status frame received within specified time lt 4 gt Status frame reception Time out error C Reception status ACK other than ACK Other than ACK ae s ACK 2 AME termination B Time out check for Mas o data frame reception trot Time out occurs Data frame received y within specified time AAA lt 6 gt Data frame checksum data reception 4 ime out error a 2 Noma data ae NG Yes No Yes _ E ad Kas frame gt fone completi i pletion A x l LA E Application Note U19735EJ1VOAN 95 CHAPTER 4 UART COMMUNICATION MODE 4 13 2 Description of processing segu
116. ultaneously Condition 2 Start block number Number of blocks to be selected and erased simultaneously Remainder is 0 Condition 3 The maximum value among the values that satisfy both Conditions 1 and 2 110 Application Note U19735EJ1VOAN CHAPTER 5 FLASH MEMORY PROGRAMMING PARAMETER CHARACTERISTICS 5 3 2 Calculation of execution count M of simultaneous selection and erasure Calculation of the execution count M is illustrated in the following flowchart ER BKNUM lt END BKNO ST BKNO 1 ST BKNO Start block number Meco END_BKNO End block number ER_BKNUM Number of blocks to be erased SSER_BKNUM Number of blocks to be selected and erased simultaneously SSER_BKNUM 128 M Execution count of simultaneous selection and erasure SSER_BKNUM SSER_BKNUM 2 Condition 1 ER BKNUM gt SSER BKNUM Condition 2 ST BKNO SSER BKNUM Remainder is 0 Yes ER BKNUM ER BKNUM SSER BKNUM Yes ER BKNUM 0 No End ST BKNO ST BKNO SSER BKNUM Note Based on the maximum value of SSER BKNUM 128 obtain the value that satisfies Conditions 1 and 2 by executing SSER BKNUM 2 Condition 3 is then satisfied Application Note U19735EJ1VOAN 111 CHAPTER 5 FLASH MEMORY PROGRAMMING PARAMETER CHARACTERISTICS Example 1 112 Erasing blocks 1 to 127 N number of blocks to be erased 127 lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt b gt lt 6 gt
117. z zz D6 6 of w x al af a s p s RERPERPBESSSSOSSISIZJS38555 207 sjo 2 AT de ES rca ined a i Saa ca 22442222222 33u u swa O ab Z ZZ E GND lt lt lt lt lt lt 10 11 DE E 3 2 S a 3 GND E gt 5832835883 5 AVREFO ADA E75 at us F E 5 AVSS AD3 73 EC I P10 AD2 4 72 ADI n ADI 5 71 ADO GND AVREFL ADO 5 B lt 4 Poo BVDD 4 oz x POL BVSS ND 2415139 OZ 3808 s 8 amp 9 FLMDO ASIB 67 RD S ilz 16 TEANSO D1 150 o TATA A ATA u 10 VOD RD 66 Fa M Fe voo 910 MAX232CPE o RESC we EX A A tas 4 WA A733 GND lu lu vss WRO Ada Eb x X 12 64 A20 3 u7 y ux x PCM3 E5 X Ala R2 x2 ij 70F3313Y pama E Ab L C6 cz RESET 14 62 4 3 13 ze RESET PCM1 2X Doa Alb VDD 15 61 GND 5 u cs is XT2 PCMO feo lt cs Ola a us 2x XT2 C51 zo KT 02a 00b Hi P02 cso Osa O1 18 58 10 9 Pos pois SEX 3 O2b X 5V 3 3V Level Shifter x GND lt a P94 P914 eK GND 039 X 1 2 2201 pos p913 POS ul o o evel keho eO es FP OE 21 55 FP_RESET 3 5 ol4 55 P06 P912 jaz X GND u6 So A3 S100 P911 55 X FP T x o O x xD 718 ols FP RxD X sooo P910 EX o O4 AE p99 52 FP FLMDO So ol10 c cu remo s 51 ADO 13 12 Ao FP OE i15 922 DSUB 9Pin TxDO P98 PX DO1 AO o O X ADI 14 002 AL A Blo or 2 ao AD2 15 10 A2 BamznenVOpaoganznalansesn AD 171 pes ape To Host PC ZAB3383S5833082882R3983883 DO4 A3 CNZ A KETENG EKA ADA 18 8 Aa PANEN E EP STIS Pa lan naaa ul ADS ig 005 A T A IRSE RR RS RISE RIS RII ees ee n DQ6 AS AD6 20 Do

(Programmer) AN - Renesas Electronics

Contents

Download Pdf Manuals

Related Search

Related Contents