PISA PIII TwisterT HW Doku V03
Contents
1. VIA VT82C686B Southbridge Rs232 JP11 emImeo JP12 2 1 CPU The PISA PIII TwisterT supports Socket 370 Intel Pentium IIl and Celeron both Tualatin Cores only as well as VIA C3 CPUs It is based on the VIA ProSavage PN133T chipset VT8606 TwisterT northbridge and VT82686B southbridge operating at 100 MHz or 133 MHz front side bus The system performance depends on the CPU you choose The following table shows the supported CPU types and their recommended jumper settings CPU internal frequency L2 cache core voltage JP1 JP2 JP3 JP4 INTEL Celeron 1000 256 100 1 5 2 3 closed 2 3 1 2 INTEL Celeron 1100 256 100 1 5 2 3 closed 2 3 1 2 INTEL Celeron 1200 256 100 1 5 2 3 closed 2 3 1 2 INTEL Celeron 1400 256 100 1 5 2 3 closed 2 3 1 2 INTEL Pentium III 1133 512 133 1 45 2 3 closed 2 3 2 3 INTEL Pentium III 1200 512 133 1 45 2 3 closed 2 3 2 3 INTEL Pentium Ill 1266 512 133 1 45 2 3 closed 2 3 2 3 VIA Ezra 800 64 133 1 35 1 2 open 1 2 2 3 VIA Ezra 1000 64 133 1 35 1 2 open 1 2 2 3 VIA Ezra T 1000 64 100 1 45 2 3 closed 2 3 1 2 VIA Nehemiah 1000 64 133 1 40 2 3 closed 2 3 2 3 VIA Nehemiah 1000 64 133 1 45 2 3 closed 2 3 2 3 Note Intel CPUs have 32 Kby2. Backlight Power header 6 pins 2 54 mm 12V 5V GND GND 5V 12V 19 PISA PIII TwisterT User s Manual Installation 2 7 1 LCD Connectors Digital IDC header 50 pins 2 0 mm LVDS FCC connector 40 pins 0 5 mm 12V 12V 1 GND GND CH1_RED 2 5V 5V 3 CH1 RED 3 ENVEE GND ENVEE 4 PO P1 CH GRN 5 P2 P3 GRN 6 P4 5 NC 1 P6 7 CH1_BLUE 8 P8 P9 CH BLUE 9 P10 ee P11 GND 10 P12 eo P13 CLK 11 P14 P15 CH1 CLK 12 P16 17 GND 13 P18 ee P19 NC 14 P20 21 NC 15 P22 23 PDC DATA 16 P24 25 CH2 RED 17 SHFTCLK FLM VSYNC CH2 RED 18 M DE HSYNC PDC CLK 19 GND ee ENBLIGHT CH2 GRN 20 P26 27 CH2 21 P28 29 DETECT 22 P30 P31 CH2_BLUE 23 P32 P33 CH2 BLUE 24 P34 P35 GND 25 CH2 CLK 26 CH2_CLK 27 GND 28 N C 29 N C 30 5V 3 31 5 3 32 5 3 33 5 3 34 ENBLIGHT 35 GND 36 GND 37 12V 38 12V 39 12V 40 Note The FCC connector for LVDS uses bottom contacts Turn flat foil cable contact side top down for insertion 20 PISA PIII TwisterT User s Manual Installation 2 7 2 Digital Display Data Mapping Signal Pin DSTN16 DSTN24 TFT18 TFT24 TFT2x18 P0 9 LB3 B0 R00 P1 10 LB2 B1 R10
3. 24 2 14 nasse eere 25 2 14 1 Primary eem 25 2 14 2 Secondary Channel optionally CompactFlash 26 2 15 Floppy DISK goes tiesto dare elei este 2 16 Parallel Port 2 17 Internal USB seen eee e ees 2 18 External USB cene dee rere 2 19 RJA5 Ethernet 2OD TRIS Lone secco HUE M to eto LA Moa 2 21 Keyboard Mouse Mini DIN 29 2 22 PISA Edge Connector 30 2 23 104 31 2 24 ome teer 32 2 25 PCI Interrupt Routing sseee e 32 2 26 Interrupts DMA channels Upper 33 Trademarks PISA is a registered trademark of JUMPtec Industrielle Computertechnik AG JUMPtec is the registered trademark of JUMPtec Industrielle Computertechnik AG PISA PIII TwisterT User s Manual Installation 1 General Information 1 1 Introduction The PISA PIII TwisterT is an all in one single board computer card for the PISA bus PISA PCI ISA designed for Intel s new generation Pentium IIl and Celeron Tualatin CPUs as well as VIA s C3 CPUs in Socket370 package The board uses the VIA ProSavage PN133T chipset VT8696 TwisterT Northbridge and VT86286B Southbridge ru
4. 0 opo 0 gp ek 30 PISA PIII TwisterT User s Manual Installation 2 23 PC 104 Conncetor Pn A 0 pr 09 A93 0 6 38 86 2 0 H 65 0 RO9 A JROM 5 pD4 20 JROI2 6 8 2 Alo 82 04 500 HRDY ORCH 5011 DACK7 DACK3 SD12 DRO DRQ3 Q z xxm Cc1 Oo 1 oo co gt 2 E 11 5 Ni Co co gt 4 109 8 9 0 6 8 0 80 e 2 31 PISA PIII TwisterT User s Manual Installation 2 24 Watchdog The watchdog can be enabled via SETUP and the user can define if the counter should start during system boot or later by an application software It has a programmable delay timer which expires once before the watchdog timer begins counting After the programmable timeout counter has expired a system reset will be generated If enabled in SETUP application software can access the watchdog register via the I O address defined in SETUP using IN and OUT instructions ISA Bus Name Description Bit 0 RUN 1 timeout counter is running Read Write Setting this bit resets TIMEOUT bit2 and initializes all counters Bit 1 TRIGGER must be toggled within the specified time interval to reload the Read Write timeout counter Bit 2 TIMEOUT 0 no timeout occurred Default after power up or after bitO is set Read only
5. 2625 0952291 avn SOIg usei4 AS vOL Od Acl PISA jeuueu SAAT jeuueu SCAT 161a Hage 1 Qc az 90981 VIA AS QNO 189 vod 23 016 3920 2 6 ININIG SIN 2 9 ININIG ur ao 3no eur uj eur1 1 PISA PIII TwisterT User s Manual Installation 1 3 Specifications Core CPU Socket 370 Intel Pentium III with 512KB L2 Cache up to 1 26 GHz 133MHz FSB Socket 370 Intel Celeron with 256 L2 Cache up to 1 4 GHz 100MHz FSB VIA C3 Ezra up to 933 MHz 100 133 MHz FSB VIA C3 Ezra T to 1 GHz 133 MHz FSB VIA Nehemiah to 1 2 GHz 133 MHz FSB ChipSet VIA ProSavage PN133T VT8696 TwisterT North Bridge VT82686B South Bridge On chip Caches Intel Celeron 32 L1 cache 256KB L2 cache Intel Pentium 32 KB L1 cache 512KB L2 cache VIA C3 CPUs 128 L1 cache 64 KB L2 victim cache Memory e 2 Standard 168 Pin DIMM sockets e 1GByte PC100 or PC133 independent of FSB speed ISA Bus Interface e 7862868 South Bridge e Standard PISA connector e Standard PC 104 connector PCI Bus Interface e VT8696 TwisterT North Bridge e Standard PISA connector Video e S3ProSavage4 AGP4x SXVGA Controller i
6. AGTL termination resistors enable disable JP3 3 Processor pin X4 functionality JP4 3 Processor FSB frequency selection JP5 2 Onboard buzzer enable disable JP6 3 LCD power supply level JP7 3 LCD power mode JP8 3 Clear CMOS JP9 2 BIOS crises recovery JP10 3 5485 receive transmit control JP11 2 5422 5485 line termination enable disable JP12 3 PCII O voltage level LJP1 3 voltage level solder jumper LJP2 3 1 voltage level solder jumper LJP 3 4 3 For internal use must be always open 11 PISA PIII TwisterT User s Manual Installation 1 4 Board Layout 1 4 1 Top Side CRT Monitor ise COM2 RS232 422 482 IrDA 12 JP11 Ethernet1 RJ45 Ethernet2 Primary IDE Northbridge with integrated x 6 m 40 eo oo 3 2 58 5 oo Sa SE 5 50 EO a gt 0 c digital LCD Aux Power Fan1 Fan2 12 Installation PISA PIII TwisterT User s Manual Bottom Side 1 4 2 J0329uuo2 jexyoos 5 4 32eduio3 mmm mmm dr sa 385 CES 13 PISA PIII TwisterT User s Manual Installation 2 Installation cm 9 Primary IDE il le Floppy sg 1m ESs LPT VIA VT8606 us ie Northbridge B kn with integrated RM PROSavage4 AGP 4x Graphics Buzzer
7. Connector LJP2 LJP1 LJP3 Lipa CO minm Compact Flash Socket 2 14 2 Secondary Channel optionally CompactFlash Pin Name Name Pin Name Name gt o oo 1 o Optionally a CompactFlash socket be mounted onto the solder side of the PISA PIII TwisterT board Note CompactFlash cards are IDE compatible and therefore no special Flash driver or a Flash file system is needed Capacities for CompactFlash range from 8 Mbyte to 2 Gbyte The CompactFlash socket is routed to the IDE secondary channel 26 PISA PIII TwisterT User s Manual Installation PROSavage4 AGP 4x Graphics VT82C686B Southbridge GND 2 DENSEL STB me 2 GND ee 4 n c 00 ee 1 GND ee 6 n c D1 6 GND ee 3 INDEX D2 ee SLIN GND ee 10 MTRO 03 ee 10 GND GND ee 12 DRVSEL1 D4 12 GND GND ee 11 DRVSELO D5 ee 14 GND GND ee 16 06 ee 16 GND GND ee 15 D7 ee 18 GND GND ee 20 STEP ACK 20 GND GND ee 22 WDATA BUSY ee 22 GND GND ee 24 WGATE PE 24 GND GND ee 26 SLCT 26 GND GND ee 28 WPROT GND ee 30 RDATA GND ee 32 HEADSEL GND ee 34 DSKCHG 2 17 Internal USB 5V 1 5V DATA2 3 DATAS DATA2 5 DATA3 GND 7 GND SHIELD 9 SHIELD 27 PISA PIII TwisterT User s Manual Installat
8. P2 11 LB1 LB1 BO B2 R01 P3 12 LBO LBO B1 B3 R11 P4 13 UB3 B2 B4 R02 P5 14 UB2 B3 B5 R12 P6 15 UB1 UB1 B4 B6 R03 P7 16 UBO UBO B5 B7 R13 P8 17 LG3 G0 R14 P9 18 LG2 LG2 61 R14 P10 19 161 161 G0 G2 R05 P11 20 LGO LGO G1 G3 R15 P12 21 063 62 64 G00 P13 22 UG2 UG2 G3 G5 G10 P14 23 UG1 UG1 G4 G6 G01 P15 24 UGO UGO G5 G7 G11 P16 25 LR3 RO G02 P17 26 LR2 LR2 R1 612 P18 27 LR1 LR1 RO R2 G03 P19 28 LRO LRO R1 R3 613 P20 29 UR3 R2 R4 G04 P21 30 UR2 UR2 R3 R5 G14 P22 31 UR1 UR1 R4 R6 G05 P23 32 URO URO R5 R7 G15 P24 33 B00 P25 34 B10 P26 41 B01 P27 42 B11 P28 43 B02 P29 44 B12 P30 45 B03 P31 46 B13 P32 4T B04 P33 48 B14 P34 49 05 P35 50 B15 21 PISA PIII TwisterT User s Manual Installation 2 g 5 2 mel Floppy 17587 BL Primary IDE b 4 5 5 usB1 2 VIA LPT VTB606 2 mE Northbridge JP5 Ethernet with integrated RJ45 PROSavage4 AGP 4x 1 1 Graphics Buzzer Ethernet2 RJ45 VIA VT82C686B Southbridge amp f f f f D CRT Monitor Rs232 2 8 AUX Power Connector The PISA P
9. Sound Ethernet 1 chipset internal onboard devices INTD USB Ethernet 2 chipset internal optional onboard devices PCI Interrupts may be shared with other peripherals DMA Used for Available Comment 0 Yes 1 ECP if enabled No alternate available if disabled 2 Floppy Disk Controller No 3 ECP if enabled No default available if disabled 4 Cascade No 5 7 Yes Upper Memory Used for Available Comment C0000h CDFFFh VGA BIOS No 56 kByte VGA BIOS CE000h DBFFFh Yes ISA bus or shadow RAM DC000h DFFFFh USB legacy No ISA bus or shadow RAM if disabled E0000h FFFFFh System BIOS No exact start address is displayed on summary screen 33
10. with integrated PROSavaged AGP 4x Graphics VIA VT82C686B Southbridge 2 4 Clear CMOS Data and BIOS Flash Recovery Jumper JP8 Clear CMOS Data JP9 BIOS Flash Recovery 1 2 Normal operation open Normal operation 2 3 Clear CMOS data closed Flash programming open operation Note For BIOS flash recovery operation JP9 has to be closed before power up and the crises recovery disk has to be installed in floppy drive gt Toclear the contents of the CMOS setup configuration the following procedure has to be done 1 Switch off power 2 Install jumper at position 2 3 for a few seconds 3 Install jumper again at position 1 2 2 5 COM COM3 RS232 DCD DSR RXD RTS TXD CTS DTR Ri GND Not connected 17 PISA PIII TwisterT User s Manual Installation Primary IDE with integrate PROSavaged AGP 4 Graphics Floppy VIA VT82C686B Southbridge 523289 2 R PS 2 Koya Mouse 2 6 COM2 RS232 422 485 IrDA 2 can be used in RS232 RS422 or RS485 mode The basic configuration is done via SETUP If RS485 mode is selected the signal controls the transmitter the polarity is determined by JP10 In RS422 or RS485 mode a 1000 differential termination resistor may be enabled by JP1
11. 1 JP10 Function JP11 Function 1 2 DTR low transmit high receive open Termination resistor disabled 2 3 high transmit DTR low receive closed Termination resistor enabled open No function do not leave open Connector COM2 DCD RXD TXD DTR GND RS422 TXD RS485 Data RS422 RXD GND IrDA IRRX Not connected DSR RTS CTS Ri Not connected RS422 TXD 65485 Data RS422 RXD 5V IrDA IRTX Not connected PISA PIII TwisterT User s Manual Installation UI A LS Primary IDE Floppy USB1 2 Tse USB4 VT82C686B Southbridge 2 2 JP11 emImeo JP12 2 7 LCD Interfaces The LCD panel type technology resolution can be selected via SETUP JP6 selects the voltage level for panel power supply on both the 50 pin IDC header for digital flat panels and on the 40 pin FFC connector for LVDS panels You have to set this jumper according to the type of LCD panel you want to use JP7 selects if the display power on the connectors should be permanently on or switched on an off by the panel power sequencing signal ENVDD Jumpers JP6 LCD Power Level JP7 LCD Power Mode 1 2 3 3 Volt 1 2 always on 2 3 5 Volt 2 3 switched with ENVDD open Open circuit open No operation don t use
12. 1 timeout has occurred system was reset After a timeout the watchdog is stopped until bitO is set 2 25 PCI Interrupt Routing The PISA PIll TwisterT board was designed due to PISA specification Rev 1 7 released in 1997 by Jumptec Industrial Computer AG For propper BIOS support the following PCI interrupt routing on external backplanes is recommended This routing mechanism may different from backplanes that were designed in far eastern countries PCI PCI PCI PCI RISA Slot Slot2 Slot3 1014 Slot AD19 AD20 AD21 22 Backplane PISAINTA PISA INTB PISA INTC PISA INTD Slot 1 AD19 INTA INT B INTC INTD Slot 2 AD20 INTD INTA INT B INTC Slot 3 AD21 INT C INTD INTA INTB Slot 4 AD22 INT INTC INTD INTA 32 PISA PIII TwisterT User s Manual Installation 2 26 Interrupts DMA channels Upper memory IRQ Function Available Note 0 Timer 0 No 1 Keyboard No 2 Slave 8259 No 3 COM2 No 1 4 COM1 No 1 5 SoundBlaster Emulation No 1 6 Floppy Disk Controller No 1 7 LPT1 No 1 8 Real Time Clock No 9 Yes 10 COM3 No 1 11 4 No 1 12 PS 2 Mouse No 1 13 Floating Point Unit No 14 Primary IDE No 1 15 Secondary IDE No 1 1 If the device is disabled in SETUP the interrupt is available PCI Interrupt Function Comment INTA VGA chipset internal device INTB INTC
13. Ill TwisterT board has a 4 pin power connector like standard hard disks have This connector may be used to power the board if it is used as a stand alone system without additional ISA or PCl cards on a backplane 12V GND GND 5V 3 8 1 Note Square marked pin on solder side is pin 4 5V not pin 1 12V 2 9 Fan Connectors Two Fans may be connected to the board TACHO FAN Power GND Fan power can be selected by solder jumpers LJP1 and LJP2 on the solder side of the PISA PIII TwisterT board 12 V power Power select FAN1 factory default Power select FAN2 5 V FAN power 22 PISA PIII TwisterT User s Manual Installation Primary IDE with integrate PROSavaged AGP 4 Graphics ies Floppy USB1 2 0563 1584 ie VT82C686B Southbridge Rs232 CRT Monit JP11 emImeo JP12 2 10 Onboard Reset Switch The PISA PIII TwisterT board has an onboard switch to reset the system 2 11 System Header PWR LED PWR LED GND 5 CLK DAT GND HD LED HD LED EXT RESET EXT TEMPO 5V_SB ATX 0 GND Notes KEYB CLK DAT GND 5V MOUSE_CLK MOUSE_DAT 5V n c n c SPEAKER GND EXT_RESET GND EXT_TEMP PWRBTN ATX 0 PS ON ATX 2 1 For temperature sensing conne
14. M clock speed is independent of the selected speed of the CPUs front side bus If PC133 and PC100 memory modules are mixed on the board the timing parameters of the slower module will be installed PC66 memory modules are not supported 15 PISA PIII TwisterT User s Manual Installation Primary IDE 1 Floppy Northbridge with integrated PROSavaged AGP 4x Graphics VIA VT82C686B Southbridge 2 3 PCII O Voltage Jumper 12 selects the PCI I O voltage for the PISA board JP12 Function open Factory default setting The PISA board is installed in a backplane which connects the VCCIO pin of the PISA slot to the VCCIO pins of the PCI slots 1 2 The PISA board is installed in a backplane with 5V PCI slots and the VCCIO pin of the PISA slot is not connected to the VCCIO pin of any PCI slot 2 3 The PISA board is installed in a backplane with 3 3V PCI slots and the VCCIO pin of the PISA slot is not connected to the VCCIO pin of any PCI slot Or the PISA board is used without a backplane care about correct setting of jumper JP12 if the PISA PIII TwisterT board is installed in a backplane Wrong settings may damage the board and the backplane 16 PISA PIII TwisterT User s Manual Installation Primary IDE 1 Floppy Northbridge
15. PISA PIII TwisterT All In One Socket370 CPU Card User s Manual Version 0 3 10 06 2003 MSC Vertriebs GmbH Design Center Neufahrn Copyright Notice This document is copyrighted 2002 by MSC Vertriebs GmbH rights are reserved MSC Vertriebs GmbH reserves the right to make improvements to the products described in this manual at any time without notice No part of this manual may be reproduced copied translated or transmitted in any form or by any means without the prior written permission of MSC Vertriebs GmbH Information provided in this manual is intended to be accurate and reliable However MSC Vertriebs GmbH assumes no responsibility for its use nor for any infringements upon the rights of third parties which may result from its use Important Information This product is not an end user product It was developed and manufactured for further processing by trained personnel EMC Rules This unit has to be installed in a shielded housing If not installed in a properly shielded enclosure and used in accordance with the instruction manual this product may cause radio interference in which case the user may be required to take adequate measures at his or her own expense Care and handling precautions for Lithium batteries Do not short circuit Do not heat or incinerate Do not charge Do not deform or disassemble Do not apply solder directly Always observe proper polarities Caution Danger of explo
16. an be accessed by mounting a CompactFlash connector onto the solder side of the board Onboard features also include four high speed RS 232 serial ports one configurable as 5422 485 one IrDA one bi directional SPP EPP ECP parallel port one floppy drive controller and four USB 1 1 ports 128kbit sec stereo applications are supported by a SoundBlasterPro Direct Sound AC97 Digital Audio controller An onboard 5 25 power connector give the possibility to use the PISA PIII TwisterT as a standalone system without a backplane The implemented PC 104 interface allows you to install additional functions using standard PC 104 modules Please visit our web site http www msc de gt products gt downloads gt PISA where you can find drivers firmware updates and documentation Installation PISA PIII TwisterT User s Manual 1 2 Block Diagram Svr Svr sonoubew 4ejoguo2 4319528 4319528 60802109 PWR BTN amp Rp uolsua 3 XLV DOM Use ioeduio Is i olesn 2 n jeuondo untur asn 5 5 asn z olasn 141 P ZEZSH TETSU uoo 89892281 eBpuquinos VIA Suuoyuow Weysks 22 5 OON pjeogKoy 94009 em WOO vor 9875 enoo
17. ct a 10k NTC to EXT TEMP and GND EXT TEMP Reference SEMITEC JT Thermistor Type 103JT 025 3435 2 In order to use ATX extension of the PISA PIII TwisterT board connect the appropriate signals of an ATX power supply to these pins 23 PISA PIII TwisterT User s Manual Primary IDE Floppy 2 12 Onboard Buzzer The onboard buzzer can be enabled by jumper JP5 JP5 Buzzer closed enabled open dsiabled 2 13 Onboard Sound LINE IN LEFT AGND AGND LINE IN RIGHT MIC IN AGND MIC VCC SOUND LEFT and SOUND RIGHT have no additional amplifiers CD IN LEFT CD GND CD GND CD IN RIGHT SOUND LEFT AGND SOUND RIGHT Do only connect active speakers to these outputs Installation PISA PIII TwisterT User s Manual Installation 2 14 EIDE Primary IDE 1 Floppy 2 2 JP11 emImeo JP12 2 14 1 Primary Channel RESET DATA DATA6 DATAS DATA4 DATA3 DATA2 DATA1 DATAO GND DRQO lOW IOR IORDY DAKO IRQ14 ADR1 ADRO 50 ACTIV 25 GND DATA DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 KEY missing pin GND GND GND CSEL GND n c CBLID ADR2 51 GND PISA PIII TwisterT User s Manual Installation LVDS LCD
18. ion Primary IDE Floppy PROSavage4 AGP 4x Graphics VIA VT82C686B Southbridge 2 18 External USB 5V 0 DATAO GND 1 ra BES 5V 1 DATA1 GND 2 19 RJ45 Ethernet Link LED EMI Shield RX RX TX TX The second Ethernet controller is available as an option 28 PISA PIII TwisterT User s Manual Installation Primary IDE Floppy PROSavage4 AGP 4x Graphics VIA VT82C686B Southbridge 2 20 CRT RED 1 9 DDCVCC GREEN 2 10 GND SYNC BLUE 3 32 1 11 reserved reserved 4 60006 12 DDC SDA GND 5 10 90909 8 13 HSYNC GNDRED 6 14 VSYNC GNDGREEN 7 15 DDC CLK GNDBLUE 8 2 21 Keyboard Mouse Mini DIN Connector 6 5 KB 5V 4 3 GND MDATA 2521 KB Note standard PS 2 keybord may be connected directly In order to use a mouse or both keyboard and mouse an Y adapter is needed 29 PISA PIII TwisterT User s Manual Installation 2 22 PISA Edge Connector Pin ISA Bus Top Layer ISA Bus Bottom Layer PCI Bus Top Layer PCI Bus Bottom Layer IOCHCK amp RESETDRV 16 5 15 DROS 22 sag A A 5 sas ROS TEE SBHE 16 1 AD14 LA23 10 516 AD12 43 MEMWE DACKS xn VIO 014 MASTER SD15 eno 0
19. ital Audio Controller VT1612A AC 97 2 2 VSR Codec Line out Line in CD in MIC in PISA PIII TwisterT User s Manual Installation System Monitoring e 2fans CPU system e 3ltemperatures CPU board external 2 pin header e CPU core voltage 2 5V 3 3V 5V 12V Power Supply 5V 5 12V 5 required for additional PC 104 and fans 12V 5 only required for additional PC 104 cards Supply Current Windows 2000 CPUBURN EXE 5V 6 6A Intel Celeron 1 2 GHz 1 4 GHz 100 FBS 6 9A Intel Pentium 1 26 GHz 133 MHz FSB 5 0A VIA C3 EZRA 800 MHz 133 MHz FSB 5 2A VIA C3 EZRA T 1 0 GHz 133 MHz FSB 5 5 C3 NEHEMIAH 1 0 GHz 1 2 GHz 133 MHz FSB 12V depends on PC 104 card and or fans 12V depends on PC 104 card Environment Temperature operating 0 60 non operating 25 85 C Humidity rel operating 0 95 non operating 5 95 Dimensions 185 x 125 mm PISA PIII TwisterT User s Manual Connectors Overview Installation Interface Connector Type CPU staggered 370 pins ZIF socket PCI Bus PISA standard edge connector PC 104 ISA Bus Standard 64 40 pins connector female Memory 2 x DIMM socket 168 pins EIDE Primary IDC header 40 pins 2 rows 2 54mm Secondary CampactFlash socket 50 pins optional Floppy IDC header 34 pins 2 rows 2 54 mm Para
20. llel Port IDC header 26 pins 2 rows 2 54 mm 1 IDC header 10 pins 2 rows 2 54 mm COM2 IDC header 20 pins 2 rows 2 54 mm COM3 IDC header 10 pins 2 rows 2 54 mm COM4 IDC header 10 pins 2 rows 2 54 mm CRT Interface 15pol HDSUB HDSUB 15 pins LCD Panel digital IDC header 50 pins 2 rows 2mm LCD Panel LVDS FFC connector 40 pins 1 row bottom 0 5 mm Type HIROSE FH12S 40S 0 5SH LCD Inverter Power pin header 6 pins 1 row 2 54 mm LAN 1 2 RJ 45 CAT5 USB 1 2 Dual USB connector type A USB 3 4 2 x pin header 5 pins 1 row 2 54 mm Sound pin header 14 pins 2 rows 2 54 mm Fan 1 2 2x pin header 3 pins 1 row 2 54 mm AUX Power 54 power connector Keyboard Mouse external PS 2 6 pins System Connector pin header 30 pins 2 rows 2 54 mm Keyboard Mouse intern pin header 7 pins 1 row 2 54 mm Reset pin header 2 pins 1 row 2 54 mm Power LED pin header 5 pins 1 row 2 54 mm IDE LED pin header 2 pins 1 row 2 54 mm Speaker pin header 4 pins 1 row 2 54 mm SMBus pin header 4 pins 1 row 2 54 mm Temperature sensor pin header 2 pins 1 row 2 54 mm ATX extension pin header 4 pins 2 rows 2 54 mm 10 PISA PIII TwisterT User s Manual Installation Jumpers Name Pin Description JP1 3 Processor AGTL voltage level JP2 2 VT8606 internal
21. ning at 100 MHz or 133 MHz front side bus With an LCD CRT SXVGA controller up to two 100MBit Ethernet controllers an EIDE controller a floppy controller as well as sound LPT keyboard and mouse interfaces four serial communication ports and four USB ports the PISA PIII TwisterT packs all the functions of an industrial computer onto a single card This makes it an ideal solution for embedded applications Two 168 pin standard DIMM socket are giving you the flexibility to configure your system up to 1 GByte of 3 3V SDRAM PC100 and PC133 The integrated 3 ProSavage4 4x 2D 3D Video accelerator with 128 bit graphic engine uses 8 16 or 32 MByte of system memory The PISA PIII TwisterT board includes one 36 bit DSTN TFT flat panel and one 2 channel 110 MHz LVDS interface by actually supporting display types with resolutions up to 1400 x 1050 pixels Up to two Intel 82551ER PCI 10 100BaseTx Ethernet controllers can be equipped which give access to high speed networks through standard RJ45 connectors in the front panel of the board The PISA PIII TwisterT includes a high speed local bus EIDE controller This controller supports through ATA PIO mode3 mode4 and Ultra DMA 33 66 100 hard disks enabling data transfer rates up to 100 MByte sec Up to two devices including large hard disks CD ROM drives tape backup drives or other IDE devices may be connected to the 40pin 2 54mm primary IDE header Optionally the secondary EIDE port c
22. ntegrated into North Bridge e 8 16 32 MB fame buffer shared with system memory e CRT Interface 15 VGA connector integrated into front panel e X Flat Panel Interface 36 bit TTL and 2 channel 110 MHz LVDS e type selectable via BIOS setup e Connector for backlight inverter power supply Realtime Clock e VT82686B South Bridge PISA PIII TwisterT User s Manual Installation Ethernet Floppy Disk Serial Parallel USB Lithium battery Intel 82551ER Ethernet Controller 10 100 MBit Second Intel 82551ER Ethernet Controller 10 100 MBit optional RJ45 standard connectors integrated into front panel 2 drives supported AT PS2 compatible floppy disk interface 1 RS232 COMI 1 x RS232 RS422 RS485 IrDA configurable via BIOS setup 2x RS232 COM3 1x parallel Port PS 2 compatible ECP EPP configurable via BIOS setup 2x USB 1 1 integrated into front panel 2x USB 1 1 2x 5 pin header Keyboard Mouse BIOS Flashdisk Watchdog Sound MFII Keyboard Interface PS 2 Mouse Interface 512 KByte Flash ROM 29F004 TSOP32 with integrated 64KB boot block PhoenixBIOS 4 0 Release 6 1 optional CompactFlash connector on solder side PIC12C509 PIC Controller Programmable delay from 1 to 255 seconds or minutes Programmable timeout from 1 to 255 seconds or minutes action HW RESET Re triggerable via ISA l O port SoundBlasterPro Hardware and DirectSound Ready AC 97 Dig
23. sion if the battery is incorrectly replaced When battery replacement is necessary use only the exact same battery or a battery recommended by the manufacturer Pay attention to the local area regulations regarding the proper disposal of used batteries 1 General Information eeeseseseeeeesen ene enne nnne nnn nnn 5 1 4 Introductionis nee ERR 5 12 Block Diagram eerte ete ee 6 1 3 Specifications es e A at Eie ete E 7 1 4 Board Payouts segete e n a eee ed 12 TAA uiii ote ce 12 1 4 2 SIO e E A E E 13 Installation 14 x eoe 14 2 2 SDRAM e nO 15 2 3 Voltage ee oec tdeo 16 2 4 Clear CMOS Data and BIOS Flash Recovery 17 25 1 5232 17 2 6 RS232 422 485 18 237 ECD Interfaces eet HERR 19 2 7 1 LCD Connectors ener nnn nnns 20 2 7 2 Digital Display Data 21 28 AUX Power Connector 22 2 9 FAN Connectors ele e ete estere re RN eS 22 2 10 Onboard Reset 23 2441 System Header tr itr re Pre id pens 23 2 12 Onboard 22 24 2 13 Onboard
24. te L1 caches CPUs have 128 Kbyte L1 caches Do not run any CPU without an adequate fan and heatsink 14 PISA PIII TwisterT User s Manual Installation 2 2 SDRAM digital LCD ek Primary IDE ofa Sound BEI rimary 1 Bs VIA vios Northbridge with integrate PROSavage4 AGP 4x Graphics USB1 2 VIA VT82C686B Southbridge 232 CRT Monit JP11 JP12 The PISA PIII TwisterT board has two DIMM sockets for standard 3 3V SDRAM DIMM modules The advanced memory controller supports 256 Mbit DRAM technology thus supporting up to 512 Mbyte per bank or 1 Gbyte in one DIMM socket The following table shows the SDRAM organizations which are supported Organization Capacity Module max Capacity 2 DIMMs 4M x 64 32 MByte single or double sided 64 MByte 8M x 64 64 MByte single or double sided 128 MByte 16M x 64 128 MByte single or double sided 256 MByte 32M x 64 256 MByte single or double sided 512 MByte 64M x 64 512 MByte single or double sided 1 GByte 128M x 64 1 GByte double sided 2 GByte Notes DRAM controller supports PC133 PC100 memory modules The memory timing is installed automatically by the BIOS according to the SPD information read from the serial on the module SDRA
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