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Manual - Excalibur Systems, Inc.

1. Sync RT Address Reserved P Message Error Instrumentation Service Request Broadcast Command Received Busy Subsystem Flag Dynamic Bus Control Acceptance Terminal Flag Figure 9 1 MIL STD 1553B Word Formats NOTE T R Transmit Receive P Parity EXC 1553P104 MCH3 User s Manual page 9 1 Chapter 9 Appendices Appendix B MIL STD 1553B Message Formats BC to RT RT to BC RT to RT Mode w o Data Mode w Data Transmit Mode w Data Receive Broadcast BC to RTs Broadcast RT to RTs Broadcast Mode w o Data Broadcast Mode w Data Receive Command Transmit Command if Receive Command Mode Command Mode Command HIE Mode Command Receive Command Receive Command Mode Command Mode Command 4 Data Data Word Word Data i Status Next ee Word Word Command Status Data Data Data Next Word Word Word Word Command Transmit i Status Data Data Data A Status Next Command Word Word Word Word Word Command Status Word Next Command x Status Data Next Word Word Command Data 4 Status Next Word Word Command Data Data Word Word Transmit Command Next Command Data Next Data Next ee Word Command Status Data Data Data x Next Word Word Word Word Command Word Command Figure 9 2 MIL STD 1553B Message Formats NOTE Response t
2. ees ees ee ee Re Re ee ee ee Re ee ee 3 5 3 2 5 Pending Interrupt Register ese ee Re ee ee Re ee ee 3 6 3 2 6 Interrupt Log List Pointer Register ees se ee ee ee ee Re ee ee ee 3 7 3 2 7 BITMWordihediter ss ESE ol EE GE RE ER ES tears eS 3 7 3 2 8 Minor Frame Timer Register esse ee ees ee ee ee ee ee ee ee ee ee ee ee 3 8 3 2 9 Command Block Pointer Register esse ese ee ke ee ee ee 3 8 3 3 BO Architeelure is ee ee Ee ld ee Ee 3 9 3 3 1 Control Word ts events ann serene a deve det ren ties 3 10 J3 31 1 Opcode Definition tte EE REEKSE EE ENE Se EE ER EES be See Ee 3 11 3 3 1 2 BC Condition Codes ie ke AR RA Re Re 3 13 3 3 2 1553 Command Words ee ee Re RA ee RA ee Re ge 3 13 3 3 3 Data Pointer EE Es ice EL ER Ge GO GE DE Ee Ee De 3 14 3 3 4 1553 Status Words sis see EE DR Se EER De SE ee RE EE GR SR ER Dene ee ee ete 3 14 3 3 5 Branch tele SR ER DE EE AE es 3 14 3 3 6 MEE AR ER ke ie tenes ji ge Le OE AE ON 3 14 3 4 Command Block Chaining iii ee 3 15 3 5 Memory Architecture ie SE Gee Se Oe RR Be ee eke Ee Ee 3 16 3 6 MIL STD 1553A Operation BC Mode iese esse ese 3 17 EXC 1553P104 MCH3 User s Manual page i Contents 4 Remote Terminal Operation cccccccssseesseeeeeeeeeeeseeeeeeeees 4 1 4 1 Control Registers RT Mode ccecsecceeeeeeeeeeeeeeeeeeees 4 2 4 1 1 eende date SA EE EE OR EE RE EE eia 4 3 4 1 2 Operational Status Register ees ee Re ee Re ee
3. determines the channel s mode of operation MSEL1 MSELO Mode of Operation 0 0 BC 0 1 RT 1 0 BM 1 1 RT Concurrent BM Mode 07 A B_STD Military Standard 1553A or 1553B This bit determines whether the board will operate under MIL STD 1553A or 1553B protocol 1 Forces the board to look for all responses in 9usec or generate time out errors 0 Automatically allows the board to operate under the MIL STD 1553B protocol see MIL STD 1553A Operation BC Mode page 3 17 04 06 Reserved These read only bits are not applicable 03 EX Channel Executing This read only bit indicates whether the channel is presently executing or is idle 1 The channel is executing 0 The channel is idle 02 Reserved This read only bit is not applicable 01 Ready Channel Ready This read only bit is cleared on reset 1 The channel has completed initialization or BIT and regular operation may begin 00 TERACT Channel Terminal Active This read only bit is cleared on reset 1 The channel is presently processing a 1553 message Note When STEX transitions from 1 to 0 EX and TERACT stay active until command processing is complete Operational Status Register page 3 4 Excalibur Systems Chapter 3 Bus Controller Operation 3 2 3 Current Command Register Address 0004 H READ ONLY The Current Command register contains the last 1553 command that was transmitted by the board Upon the execution of each Command Block this regist
4. ol o ii N Q 8 JE je E Q 3 3 E 5 _ Q io l EE NE 3 iy 72 E AJP CHANNEL 0 CHANNEL 1 G 5 EER N O Nl la la A g a BE S o AJP1 rT rz IZ Fi x O P1 z B32 re A32 Co C19 Do os P2 90 17mm 3 55 Figure 7 1 EXC 1553P104 MCH3 Board Layout EXC 1553P104 MCH3 User s Manual page 7 1 Chapter 7 7 2 7 3 7 3 1 Mechanical and Electrical Specifications LED Indicators The EXC 1553P104 MCHB8 board contains three LEDs The LEDs indicate that a 1553 message is being processed by the corresponding channel TERACT bit set to 1 in Operational Status Register Operation of both channels is identical Each LED corresponds to a channel listed below LED Indication LD1 Channel 0 LD2 Channel 1 LD3 Channel 2 LED Indicators Jumpers Groups of Jumper Headers are provided on the board for various user selectable functions These headers are mounted with 2 mm shorting blocks according to the default board setup see Factory Default Jumper Settings page 7 4 In high vibration environments these jumpers can be soldered or Wire Wrapped The EXC 1553P104 MCH3 board contains sets of Jumper arrays that control the Logical Address Segment the base I O address and the interrupt line selected for the board There are also Jumpers for the 1553 interface Direct Transformer Coupled VO Address Decoding Jumpers JP12 JP19 The VO Address Decoding Jumpers select one of the board s four
5. Bit 10 of the Status Word 08 SRQ Service Request Bit This bit sets the Service Request bit of the MIL STD 1553B Status Word Bit 11 of the Status Word 04 07 Reserved Setto0 03 BUSY Busy Bit Assertion of this bit is reflected in the outgoing MIL STD 1553B Status Word 1 Prevents memory accesses Bit 16 of the Status Word 02 SSYSF Subsystem Flag Bit This bit sets the Subsystem Flag bit of the MIL STD 1553B Status word Bit 17 of the Status Word 01 Reserved Setto0 00 TF Terminal Flag Assertion of this bit is reflected in the outgoing MIL STD 1553B Status Word The board automatically sets this bit if a BIT failure occurs Inhibit Terminal Flag mode code prevents the assertion by the host Override Inhibit Terminal Flag Mode Code re establishes the Terminal Flag option Bit 19 of the Status Word 1553 Status Word Bits Register MIL STD 1553B EXC 1553P104 MCH3 User s Manual page 4 11 Chapter 4 Remote Terminal Operation For MIL STD 1553A applications the 1553 Status Word Bits register Bit Bit Name Description 15 IMCLR Immediate Clear Function 1 Enables the Immediate Clear Function IMF of the board Enabling the IMF results in the clearing of the bits 10 19 immediately after a Status Word is transmitted To enable this function set this bit when writing to bits 10 19 This bit should be used consistently since once set it will remain set and once cleared it will remain cleared 10 14 Reserved Se
6. Broadcast Data Pointer XXXX H Index equals three Index decrements to two Index equals two Index decrements to one Index equals one Index decrements to zero Data Pointer A updated to 010E H interrupt generated Excalibur Systems Chapter 4 Remote Terminal Operation CONTROL WORD DATA POINTERA DATA POINTER B Message Information BROADCAST Word DATA POINTER Time Tag DATA DATA N Data Words BUFFER BUFFER BROADCAST Message __ BUFFER Figure 4 4 EXC 1553P104 MCH3 Descriptor Block Receive CONTROL WORD DATA POINTERA DATA POINTER B Message Information Word XXXX hex Time Tag y DATA DATA N Data Words BUFFER BUFFER A B Message N Figure 4 5 EXC 1553P104 MCH3 Descriptor Block Transmit EXC 1553P104 MCH3 User s Manual page 4 23 Chapter 4 4 2 6 Remote Terminal Operation Ping Pong Handshake Mode 0 The EXC 1553P104 MCHS3 provides a software handshake that indicates the enable and disable of buffer ping pong operation During remote terminal operation the board asynchronous ping pongs between two subaddress or mode code data buffers To perform buffer service the application software must freeze the remote terminal s access to a single buffer The board s ping pong enable disable handshake allows the applicatio
7. consecutive I O addresses The Jumper setting are Jumpers Address Lines JP12 A2 JP13 A3 JP14 A4 JP15 A5 JP16 A6 JP17 A7 JP18 A8 JP19 A9 VO Address Decoding Jumpers JP12 JP19 A Jumper covered with a shorting block logic 0 at bit position An uncovered Jumper logic 1 at bit position Example To select I O Base Address 0280 H short with shorting blocks Jumpers JP18 and JP16 JP12 page 7 2 Excalibur Systems Chapter 7 7 3 2 7 3 3 Mechanical and Electrical Specifications Board Logical Address Jumpers JP20 JP24 The Addressing Decoding Jumpers are used to set the Base Address of the board within the PC s memory space The EXC 1553P104 MCH3 board occupies 32K one half segment of memory within the PC s lower one megabyte of memory address space Jumpers JP20 JP24 corresponding to address lines A15 A19 are used to select the Base Address of this half segment as shown below Jumpers Address Lines JP20 A15 JP21 A16 JP22 A17 JP23 A18 JP24 A19 Address Decoding Jumpers JP20 JP24 A Jumper covered with a shorting block logic 0 at bit position An uncovered Jumper logic 1 at bit position NOTE Do not use Address 0000 all shorted as this may cause the board not to function properly Example To set Channel 0 to Logical Address Segment D0000 H short with a shorting block Jumpers JP20 and JP22 Interrupt Select Jumpers JP1 JP11 The Interrupt Select Jumpers are used to select the d
8. only the first Command Word will be stored However in an RT to RT transfer the first command word is the Receive Command and the second Command Word is the Transmit Command Data Pointer The fourth location in the Monitor Block is the Data Pointer This pointer points to the first memory location to store the Data Words associated with the message for this block The data associated with each individual message will be stored contiguously This data structure allows the board to store the specified number of data words NOTE In an RT to RT transfer the BM uses the Data Pointer as the location in memory to store the transmitting data in the transfer Status Words The next two locations in the Monitor Block are for Status Words As the RT responds to the BC s command the corresponding Status Word will be stored in Status Word 1 However in an RT to RT transfer the first status word will be the status of the Transmitting RT while the second Status Word will be the status of the Receiving RT Time Tag The seventh location in the Monitor Block is the Time Tag associated with the message The Time Tag is stored into this location at the end of message processing i e captured after the command is validated Reserved The last location in the Monitor Block is reserved page 5 12 Excalibur Systems Chapter 5 Bus Monitor Operation 5 4 Bus Monitor Block Chaining The host determines the first Monitor Block by setting the st
9. use the same encoding scheme as receive subaddress illegalization Register 0030 H through 003E H controls the illegalization of mode codes Register 0030 H governs the illegalization of receive mode codes T R bit 0 00000 through 01111 and register 0032 H mode codes 10000 through 11111 Register blocks Transmit Mode Code T R bit 1 Broadcast Receive Mode Codes and Broadcast Transmit Mode Codes use the same decode scheme as receive mode codes Table 4 2 shows the illegalization register map For Receive Transmit Broadcast Receive and Broadcast Transmit blocks the numbers shown in the column under each bit number identify the specific subaddress or mode code in hex that the register bit illegalizes Logical 0 legal Logical 1 illegal Name Register Address H Bit Number 15 14 13 12 11 10 O98 08 07 06 O05 04 03 02 O01 00 0020 OF OE OD oC OB OA 09 08 07 06 05 04 03 02 00 Receive 0022 iF 1E 1D 1C 1B 1A 19 18 17 16 15 14 18 12 11 10 0024 OF OE OD oC OB OA 09 08 07 06 05 04 03 02 O1 00 Transmit 0026 iF 1E 1D 1C 1B 1A 19 18 17 16 15 14 18 12 11 10 Broadcast 0028 OF OE OD 0C OB OA 09 08 07 06 05 04 03 02 Of 00 Receive 002A iF 1E 1D iC 1B 1A 19 18 17 16 15 14 13 12 11 10 Broadcast 002C XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX Transmit 002E XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX Mode Code 0030 OF OE OD 0C OB OA 09 08 07 06 05 04 03 02 01 00 Receive 0032 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 18 1
10. 1 SUBADDRESS 30 SUBADDRESS 31 MODE CODE 0 MODE CODE 1 MODE CODE 30 MODE CODE 31 MODE CODE 0 MODE CODE 1 MODE CODE 30 MODE CODE 31 Excalibur Systems Chapter 4 Remote Terminal Operation 4 2 1 Receive Control Word Information contained in the Receive Control Word assists the board in message processing The following bits describe the receive subaddress descriptor Control Word The descriptor Control Word is initialized by the host and updated by the board during Command post processing Bit 08 15 07 06 05 04 03 02 01 00 Receive Control Word Bit Name INDX INTX IWA IBRD BAC Reserved A B BRD Nil Description Index Field These bits define multiple message buffer length The host uses this field to instruct the board to buffer N messages N can range from 0 00 H to 256 FF H If buffer ping ponging is enabled the INDX field is don t care i e does not contain applicable information During ping pong mode operation you should initialize the index field to 00 H The RT does not perform multiple message buffering in the ping pong mode of operation The index decrements each time a complete message is transacted no message errors The index does not decrement if the subaddress is illegalized The board can generate an interrupt when the index field transitions from one to zero see bit 07 Interrupt Index Equals Zero 1 Enables the generation of
11. 1 5 General Memory Map page 1 9 Overview The EXC 1553P104 MCHB3 is an intelligent three channel MIL STD 1553 interface board for PC 104 systems The EXC 1553P104 MCH3 provides a complete solution for developing and testing 1553 interfaces and performing system simulation of the MIL STD 1553 bus The board handles all standard variations of the MIL STD 1558 protocol Each channel of the EXC 1553P104 MCHB8 contains 64Kbytes of dual port RAM for data blocks control registers and Look up tables All data blocks and control registers are memory mapped and may be accessed in real time Each of the independent dual redundant 1553 channels may be programmed to operate in one of four modes of operation Bus Controller Remote Terminal Bus Monitor and RT Concurrent Bus Monitor The EXC 1553P104 MCH38 comes complete with menu driven software a C driver software library including source code and mating connector for each channel The EXC 1553P104 MCH3 E option is an extended temperature 40 to 85 C ruggedized version of the board for industrial or harsh environment applications For each channel of the EXC 1553P104 MCH3 E all components are soldered on to the printed circuit board sockets are not used enabling use in high vibration environments EXC 1553P104 MCH3 User s Manual page 1 1 Chapter 1 Introduction Fig
12. Bus B 09 MSBF Memory Test Fail Most significant memory byte failure 08 LSBF Memory Test Fail Least significant memory byte failure 00 07 UDB 7 0 User Defined Bits BIT Word Register EXC 1553P104 MCH3 User s Manual page 5 7 Chapter 5 5 2 8 5 2 9 5 2 10 Bus Monitor Operation Time Tag Register Address 000E H READ ONLY The Time Tag register reflects the state of a 16 bit free running ring counter in the RT and Bus Monitor modes This counter will remain a free running counter as long as the channel is not in a reset mode The resolution of this counter is 64usec bit The Time Tag counter begins operation on the falling final edge of the reset pulse Bit Bit Name Description 00 15 TT 15 0 Time Tag Counter Bits These bits indicate the state of the 16 bit internal counter Time Tag Register Initial Monitor Block Pointer Register Address 0016 H READ WRITE The Initial Monitor Block Pointer register contains the starting location of the Monitor Blocks NOTE Do not change this register while BM mode is active i e Operational Status Register bit 03 1 Bit Bit Name Description 00 15 MBA 15 0 Initial Monitor Block Address These bits indicate the starting location of the Monitor Block Initial Monitor Block Pointer Register Initial Monitor Data Pointer Register Address 0018 H READ WRITE The Initial Monitor Data Pointer register contains the starting location of the Monitor Data NOT
13. Conirol Register Remote Terminal Operation Address 0000 H READ WRITE Use the Control register to configure the board for RT operation To make changes to the RT mode and this register the STEX bit Bit 15 must be logic 0 Bit 15 14 13 12 11 10 09 07 08 Bit Name STEX SBIT Reserved BUAEN BUBEN Reserved PPACK RTM 1 0 Description Start Channel Execution 1 Initiates board channel operation 0 Inhibits board channel operation A remote terminal address parity error prevents RT Mode operation regardless of the logical state of this bit If an RT address parity error exists bit 03 of the Operational Status Register will be set low and bit 02 of the Operational Status Register will be set high Start Channel BIT 1 Places the channel into the Built In Test routine The BIT routine takes 1msec to execute and has a fault coverage of 93 4 If the channel has been started the host must halt the channel in order to place the channel into the Built In Test mode STEX 0 Note If Start BIT SBIT and Start Execution STEX are both set on one register write SBIT has priority Set to 0 Bus A Enable 1 Enables Bus A operation 0 The board does not recognize Commands received over Bus A Bus B Enable 1 Enables Bus B operation 0 The board does not recognize Commands received over Bus B Set to 0 Ping Pong Acknowledge This read only bit acknowledges the Ping Pong
14. Current Address Field 01 1 15 Bit Base Address 1 Bit Current Address Field Table 4 3 RT Mode 2 Control Word and MIB Pointer Structure page 4 36 Excalibur Systems Chapter 4 Remote Terminal Operation Figure 4 7 describes the relationship between TA CA and MIB Time Tag Message Info Word Time Tag Message Info Word Data Circular Buffer Message Information Circular Buffer MIB Length 15 8 7 0 Descriptor Block Figure 4 7 RT Mode 2 Descriptor Block and Circular Buffers Control Word EXC 1553P104 MCH3 User s Manual page 4 37 Chapter 4 4 5 Mode Code and Subaddress The EXC 1553P104 MCH3 provides subaddress and mode code decoding that meets MIL STD 553B requirements In addition the board has automatic internal illegal Command decoding for reserved MIL STD 1553B mode codes Table 4 4 shows the board s response to all possible mode code combinations T R Mode Code Function 0 00000 01111 Undefined w o data 0 10000 Undefined with data 0 10001 Synchronize with data 0 10010 Undefined 0 10011 Undefined 0 10100 Selected Transmitter Shutdown 0 10101 Override Selected Transmitted Shutdown 0 10110 11111 Reserved 1 00000 Dynamic Bus Control 1 00001 Synchronize Table 4 4 page 4 38 Remote Terminal Operation Operation a WN N WP A On Command Word stored Status Word transmitted Command Word stored Data Word stored Status Word tra
15. Last Command mode code if illegalized and updates Status Word 10011 Transmit BIT Word 1 2 3 4 10100 10101 Undefined with data Command Word stored Status Word transmitted BIT Word transmitted from BIT Word Register Data Word stored Transmit BIT Word Command Word stored Status Word transmitted Data Word transmitted 1 2 3 10110 11111 Reserved 1 2 3 Command Word stored Status Word transmitted Data Word transmitted Mode Code Description continued from previous page Excalibur Systems Chapter 4 4 6 4 7 Remote Terminal Operation Encoder and Decoder The EXC 1553P104 MCH3 receives the Command Word from the MIL STD 1553 bus and processes it either by the primary or secondary decoder Each decoder checks for the proper sync pulse and Manchester waveform edge skew correct number of bits and parity If the Command is a receive Command the board processes each incoming Data Word for correct format Word count and contiguous data If a message error is detected the board stops processing the remainder if any of the message suppresses Status Word transmission and asserts bit 09 ME bit of the Status Word The board automatically compares the transmitted Word encoder Word with the reflected decoder Word by way of the continuous loop back feature If the encoder Word and reflected Word do not match the WRAPF bit is asserted in the BIT Word Register and an interrupt will be gen
16. Pin Assignments page 7 5 Chapter 7 page 7 6 Signal BUSAHI 0 BUSALO 0 BUSBHI 0 BUSBLO 0 BUSAHI 1 BUSALO 1 BUSBHI 1 BUSBLO 1 BUSAHI 2 BUSALO 2 BUSBHI 2 BUSBLO 2 SHIELD case Mechanical and Electrical Specifications Description Channel 0 Bus A connection Channel 0 Bus B connection Channel 1 Bus A connection Channel 1 Bus B connection Channel 2 Bus A connection Channel 2 Bus B connection Provided for 1553 cables shield connection This signal is connected to the case of the computer Connectors J1 J2 and J3 Signals Description Excalibur Systems Chapter 7 7 4 2 EXC 1553P104 MCH3 User s Manual VOCHRDY AEN A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 AO Table 7 1 Table 7 2 Mechanical and Electrical Specifications PC 104 Bus Connectors Pinout Connectors P1 and P2 RESETDRV 5V IRQ2 9 12V 12V KEY SMEMW SMEMR loWn IORn IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 ALE 5V GND GND XT AT Connector P1 IRQ10 IRO11 IRQ12 IRQ15 IRQ14 5V GND GND AT Bus Extension P2 page 7 7 Chapter 7 7 5 Mechanical and Electrical Specifications Power Reduirements The EXC 1553P104 MCH3 power requirements are listed in the following table EXC 1553P104 MCH3 with no channels installed 5V 200 mA Each installed channel requires 5V 55mA 0 duty cycle non tra
17. RT instruction condition codes and the block access message error The control word is defined below 15 12 11 1 e 09 08 07 01 00 0 Retry BUSA B RT RT Conditions Codes Block Access ME Figure 3 3 Control Word Definition Bit Bit Name 12 15 Opcode 10 11 Retry Number 09 Bus A B 08 RT RT Transfer 01 07 Condition Codes 00 Block Access Message Error Control Word Description page 3 10 Description These bits define the opcode to be used by the board for that particular Command Block If the opcode does not perform any 1553 function all other bits are ignored Each of the available opcodes is defined in Opcode Definition page 3 11 These bits define the number of retries for each individual Command Block and if retry opcode is used If the Ping Pong Enable Bit bit 02 of the Control Register is not enabled all retries will occur on the programmed bus However if bit 02 is enabled the first retry will always occur on the alternate bus the second retry will occur on the primary bus the third retry will occur on the alternate bus and the fourth retry will occur on the primary bus BIT 11 BIT10 No of Retries 0 1 1 1 0 2 1 1 3 0 0 4 This bit defines on which of the two buses the command will be transmitted i e primary bus Logic 1 Bus A Logic 0 Bus B This bit defines whether or not the present Command Block is an RT to RT transfer and if the board should transmit
18. RT transfer and conditions associated with the message The board also stores each Command Word associated with the message in the appropriate location For normal 1553 commands only the first Command Word location will contain data For RT to RT commands the second Command Word location will contain data and bit 08 in the Message Information Word will be set For each command the Data Pointer is read to determine where to store data words The board stores data sequentially from the top memory location The board also stores each status word associated with the message in the appropriate location For normal 1553 commands only the first status word location will contain data For RT to RT commands the second status word location will contain data EXC 1553P104 MCH3 User s Manual page 5 1 Chapter 5 Bus Monitor Operation The board begins monitoring after Control Register bit 15 1 L e assertion of TERACT and STEX bits After reception the board begins post processing Command post processing involves storing data to memory An optional interrupt log entry is performed after a monitor is entered Monitor Time Out e MIL STD 1553A 9usec e MIL STD 1553B 15usec Error Condition Message Processing When the monitor detects an error condition in either the Command Word Data Words or the RT s status the monitor block will not store the data The monitor block counter increments The initial message Data Pointer rema
19. The most significant 11 bits determine the base address of the buffer The board increments the ring buffer pointer on the occurrence of the first interrupt storing the ITW and IAW at buffer locations 00 H and 02 H respectively The board logs ensuing interrupts sequentially into the ring buffer until interrupt number 16 occurs The board enters interrupt 16 s ITW in buffer location 3C H and the IAW at location 3E H The board increments the ring buffer pointer as interrupts occur The least significant five bits of the Interrupt Log List Pointer register reflect the ring buffer pointer value Table 6 1 shows the ring buffer architecture The user reads the ring buffer pointer value to determine the number of interrupts that have occurred By extracting the least significant five bits from the Interrupt Log List Register and logical shifting the data once to the right the host determines the number of interrupt events gt Ring Buffer Pointer _ Base Address 00 H IW 1 Base Address 20 H IW 9 Base Address 02 H IAW 1 Base Address 22 H IAW 9 Base Address 04 H IW 2 Base Address 24 H IIW 10 Base Address 06 H IAW 2 Base Address 26 H IAW 10 Base Address 08 H IIW 3 Base Address 28 H IW 11 Base Address 0A H IAW 3 Base Address 2A H IAW 11 Base Address 0C H IIW 4 Base Address 2C H IW 12 Base Address OE H IAW 4 Base Address 2E H IAW 12 B
20. an interrupt when the index field transitions from one to zero The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing Interrupt When Accessed 1 Enables the generation of an interrupt when the subaddress receives a valid Command The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing Interrupt Broadcast Received 1 Enables the generation of an interrupt when the subaddress receives a valid broadcast Command The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing Block Accessed The host initializes this bit to zero the board overwrites the zero with a logic one upon completion of message processing Upon reading a one the host resets this bit to zero in preparation for the next message Set to 0 Buffer A B Indicates the last buffer accessed when buffer ping pong is enabled During initialization the host designates the first buffer used by setting this bit 1 Buffer A 0 Buffer B This bit is a don t care if buffer ping ponging is not enabled Broadcast Received 1 Reception of a valid broadcast Command Notice Il 1 Enables the use of the Broadcast Data Pointer as a buffer for Broadcast Command information 0 Broadcast inf
21. complete message processed the EXC 1553P104 MCH8 generates a Message Information Word and Time Tag Word These Words aid the host in further message processing The Message Information Word contains Word count message type and message error information The Time Tag Word is a 16 bit Word containing the Command validity time The Time Tag Word data comes from the board s internal Time Tag counter Subaddress Receive Data For receive Commands the board stores Data Words plus two additional Words The board adds a Receive Information Word and Time Tag Word to each receive Command data packet The board places the Receive Information Word and Time Tag Word ahead of the Data Words associated with a receive Command see Figures4 3 4 4 and4 5 above When message errors occur the board stores the Receive Information Word and Time Tag Word Once a message error condition is observed all Data Words are considered invalid Data storage occurs at the memory location pointed to by the Data pointer plus two 16 bit locations page 4 26 Excalibur Systems Chapter 4 Remote Terminal Operation RECEIVE INFORMATION WORD The following bits describe the Receive Information Word contents Bit 11 15 10 09 08 07 05 06 04 03 02 01 00 Bit Name WC 4 0 Reserved BUA B RTRT ME Reserved ILL TO OVR PRTY MAN Description Word Count Bits These five bits contain Word count information extracted f
22. condition is met if the board detects that the RT s Status Word has the Message Error bit set 05 Status Word Response with the Busy bit set Bit time 16 in 1553A mode This condition is met if the board detects that the RT s Status Word has the Busy bit set 04 Status Word Response with the Terminal Flag bit set Bit time 19 in 1553A mode This condition is met if the board detects that the RT s Status Word has the Terminal Flag bit set 03 Status Word Response with the Subsystem Fail bit set Bit time 17 in 1553A mode This condition is met if the board detects that the RT s Status Word has the Subsystem Fail bit set 02 Status Word Response with the Instrumentation bit set Bit time 10 in 1553A mode This condition is met if the board detects that the RT s Status Word has the Instrumentation bit set 01 Status Word Response with the Service Request bit set Bit time 11 in 1553A mode This condition is met if the board detects that the RT s Status Word has the Service Request bit set Condition Codes 1553 Command Words The next two locations of the BC Mode Command Block are for 1553 Command Words In most 1553 messages only the first Command Word needs to be initialized However in an RT to RT transfer the first Command Word is the Receive Command and the second Command Word is the Transmit Command EXC 1553P104 MCH3 User s Manual page 3 13 Chapter 3 3 3 3 3 3 4 3 3 5 3 3 6 Bus Controller Oper
23. into the Interrupt Log List if the Interrupt Log List is enabled The interrupt architecture allows for the entry of 16 interrupts into a 32 word ring buffer The EXC 1553P104 MCH3 channel automatically handles the interrupt logging overhead Each interrupt generates two words of information to assist the host in performing interrupt processing The Interrupt Identification Word IIW identifies the type s of interrupt that occurred The Interrupt Address Word IAW identifies the interrupt source e g subaddress or command block via a 16 bit address EXC 1553P104 MCH3 User s Manual page 6 1 Chapter 6 6 1 1 6 1 2 Channel Interrupt Architecture Interrupt Identification Word IIW The Interrupt Identification Word is a 16 bit word identifying the interrupt type The format is similar to the Pending Interrupt Register The host reads the ITW to determine which interrupt event occurred The bit description for the IIW is provided below Bit Bit Name Description 12 15 Reserved Setto0 11 MERR Message Error Interrupt All modes 10 SUBAD Subaddress Accessed Interrupt RT Mode 09 BDRCV Broadcast Command Received Interrupt RT Mode 08 IXEQO Index Equal Zero Interrupt RT Mode 07 ILCMD Illegal Command Interrupt RT Mode 06 Reserved Setto0 05 EOL End Of List BC Mode 04 ILLCMD Illogical Command BC Mode 03 ILLOP Illogical Opcode BC Mode 02 RTF Retry Fail BC Mode 01 CBA Command Block Accessed BC Mode 00 MB
24. is reset to zero If CAF is less than the specified MIB length CA and MIB CAF point to the next available memory location in each buffer Control Word bits 15 to 08 specify the MIB length For transmit Commands the board begins transmission of data from memory location CA After message processing completes the board enters the message information Word and time tag Word into the MIB At the end of message processing the board updates CA and the MIB CAF If CAF equals the specified MIB length CA is updated to TA and the MIB CAF is reset to zero If CAF is less than the specified MIB length CA and MIB CAF point to the next available memory location in each buffer NOTE In this mode the BRD bit is added to the Message Information Word bit 05 The board generates a circular buffer empty full interrupt when the MIB reaches the end and begins a new message at the top of the buffer Bit 08 of the Mask Register and bit 07 of the Descriptor Control Word mask enable the generation of the Full Empty interrupt Control Word Length of MIB MIB Pointer Structure Bits 8 15 messages Base and CAF FF 128 8 Bit Base Address 8 Bit Current Address Field 7F 64 9 Bit Base Address 7 Bit Current Address Field 3F 32 10 Bit Base Address 6 Bit Current Address Field 1F 16 11 Bit Base Address 5 Bit Current Address Field OF 8 12 Bit Base Address 4 Bit Current Address Field 07 4 13 Bit Base Address 3 Bit Current Address Field 03 2 14 Bit Base Address 2 Bit
25. not been completed within 7usec Wrap Fail The board automatically compares the transmitted Word encoder word to the reflected decoder word by way of the continuous loop back feature If the encoder word and reflected Word do not match the WRAPF bit is set The loop back path is via the MIL STD 1553 bus transceiver Terminal Address Parity Fail This bit reflects the outcome of the remote terminal address parity check 1 A parity failure When a parity error occurs the board does not begin operation STEX bit forced to a logic 0 and bus A and B do not enable BIT Fail 1 A BIT failure Interrogate bits 11 through 08 to determine the specific bus that failed 1553 Status Word bit time 19 Terminal Flag is automatically set to a logic one when a BIT failure occurs Bus A Fail 1 A BIT test failure in Bus A Bus B Fail 1 A BIT test failure in Bus B Memory Test Fail Most significant memory byte failure Memory Test Fail Least significant memory byte failure User Defined Bits page 4 9 Chapter 4 Remote Terminal Operation Time Tag Register Address 000E H READ ONLY The Time Tag register reflects the state of a 16 bit free running counter The resolution of this counter is 64usec bit The Time Tag counter is automatically reset when the board receives a valid synchronize without Data mode code The board automatically loads the Time Tag counter with the data associated with reception of a valid synchroniz
26. operation The Ping Pong Enable is acknowledged by transitioning from a logical zero to a logical one while the Ping Pong Disable is acknowledged by transitioning from a logical one to a logical zero Remote Terminal Mode bits These two bits determine the RT mode of operation RTM 1 0 RT Mode 0 0 Mode 0 Index or Ping Pong Operation O 1 X Reserved 1 0 Mode 1 Circular Buffer 1 Operation 1 1 Mode 2 Circular Buffer 2 Operation Control Register continues on next page EXC 1553P104 MCH3 User s Manual page 4 3 Chapter 4 Bit 05 06 04 03 02 01 00 Bit Name Reserved BCEN DYNBC PPEN INTEN XMTSW Remote Terminal Operation Description Set to 0 Broadcast Enable 1 Enables the broadcast option for RT Mode 0 Enables remote terminal address 31 as a unique remote terminal address Dynamic Bus Control Acceptance This bit controls the board s ability to accept the dynamic bus Control mode code 1 Allows the board to respond to a dynamic bus Control mode code with status Word bit 18 set to a logic one 0 Prevents the assertion of status Word bit 18 upon reception of the dynamic mode code Ping Pong Enable 1 Enables the ping pong buffer feature of the board and disables the message indexing feature 0 Disables the ping pong feature and enables the message indexing feature Interrupt Log Enable 1 Enables the interrupt logging feature 0 Prevents the logging of interrup
27. protocol 1 Enables the XMTSW bit Bit 00 of the Control Register 1553A 0 Automatically allows the board to operate under the MIL STD 1553B protocol These read only bits are not applicable Channel Executing This read only bit indicates whether the board is presently executing or is idle 1 The channel is executing 0 The channel is idle Terminal Address Parity Fail Read only This bit indicates the observance of a terminal address parity error The board checks for odd parity This bit reflects the parity of Operational Status Register bits 10 15 Channel Ready This read only bit is cleared on reset 1 The channel has completed initialization or BIT and regular operation may begin Channel Terminal Active This read only bit is cleared on reset 1 The channel is presently processing a 1553 message Operational Status Register NOTE 1 Remote Terminal Address and Parity are checked on start of execution 2 To make changes to the RT Mode and this register the STEX bit Bit 15 in the Control Register must be logic 0 EXC 1553P104 MCH3 User s Manual page 4 5 Chapter 4 Remote Terminal Operation Address 0004 H READ ONLY Current Command Block Register This 16 bit register contains the last valid 1553 Command processed by the board Bit Bit Name Description 00 15 CC 15 0 Current Command These bits contain the latest valid 1553 Command that was received by the board This regis
28. ring buffer that contains information pertinent to the service of interrupts The EXC 1553P104 MCHB8 architecture requires the location of the Interrupt Log List on a 32 word boundary The most significant 11 bits of this register designate the location of the Interrupt Log List within a 64K memory space The lower 5 bits of this register should be initialized to a logic 0 The board controls the lower 5 bits to implement the ring buffer architecture Read this register to determine the location and number of interrupts within the Interrupt Log List least significant 5 bits Bit Bit Name Description 00 15 ILLP 15 0 Interrupt Log List Pointer Bits Note Bits 15 05 indicate the starting Base address while bits 04 00 indicate the ring location of the Interrupt Log List Interrupt Log List Pointer Register page 4 8 Excalibur Systems Chapter 4 4 1 7 BIT Word Register Remote Terminal Operation Address 000C H READ WRITE The BIT Word register contains information on the current status of the channel s hardware The RT transmits the contents of this register upon reception of a Transmit BIT Word Mode Code The user defines the lower 8 bits of this register Bit 15 14 13 12 11 10 09 08 Bit Name DMAF WRAPF TAPF BITF BUAF BUBF MSBF LSBF 00 07 UDB 7 0 BIT Word Register EXC 1553P104 MCH3 User s Manual Description DMA Fail 1 All the channel s internal DMA activity had
29. 0000 H Figure 3 1 Control Registers Map BC Mode NOTE The information in this section describes the operation of a single channel of the EXC 1553P104 MCH3 in BC mode Operating and addressing the second and third channels is identical to that of the first channel with the appropriate base address page 3 2 Excalibur Systems Chapter 3 3 2 1 Control Register Bus Controller Operation Address 0000 H READ WRITE Use the Control register to configure the board for BC mode operation To make changes to the BC and this register the STEX bit Bit 15 must be logic 0 Bit 15 14 10 13 09 05 08 04 03 02 01 00 Bit Name STEX SBIT Reserved ERTO Reserved BCEN Reserved PPEN INTEN Reserved Control Register EXC 1553P104 MCH3 User s Manual Description Start Execution 1 Initiates board channel operation 0 Inhibits board channel operation After execution begins writing a logic 0 will halt the board channel after completing the current 1553 message Start BIT 1 Places the channel into the Built In Test routine The BIT test takes 1msec to execute and has a fault coverage of 93 4 Once the channel has been started the host must halt the channel in order to place it into the Built In Test mode STEX 0 Note If Start BIT SBIT and Start Execution STEX are both set on one register write BIT has priority Set to 0 Extended Response Time Out 1 Enables the e
30. 04 H 00100 RTPTY 0 H 0 Sum of 1s 1 odd Operational Status Register Bit 02 0 RTA 4 0 04 H 00100 RTPTY 1 H 0 Sum of 1s 2 even Operational Status Register Bit 02 0 NOTE The board checks the Terminal Address and parity after RT mode operation has been started With Broadcast disabled RTA 4 0 11111 operates as a normal RT address The BIT Word Register parity fail bit is valid after RT mode has been started The Terminal Address is also programmed via a write to the Operational Status Register The board loads the Terminal Address upon completion of the Control Register write which activates RT mode Reset The software reset see Software Reset Register page 1 6 is also equivalent to a hardware power on reset and takes 5usec to complete Assertion of reset results in the immediate reset of the channel and termination of Command processing The user is responsible for the re initialization of the RT Mode for operation A Reset Remote Terminal mode code Mode Code 01000 T R 1 clears the encoder decoders resets the time tag enables the busses to the programmed host state and re enables the Terminal Flag for assertion This reset is performed after the transmission of the 1553 Status Word page 4 42 Excalibur Systems Chapter 4 Remote Terminal Operation 4 10 MIL STD 1553A Operation RT Mode To maximize flexibility the EXC 1553P104 MCHB can operate in many different systems that use va
31. 04 MCH3 User s Manual page 5 3 Chapter 5 5 2 1 Control Register Bus Monitor Operation Address 0000 H READ WRITE Use the Control register to configure the board for Bus Monitor operation To make changes to the Bus Monitor and to this register the STEX bit Bit 15 must be logic 0 NOTE The user has 5usec after TERACT Operational Status Register bit 00 is active to stop operation Bit Bit Name 15 STEX 14 SBIT 10 13 Reserved 09 ERTO 06 08 Reserved 05 BMTC 04 BCEN 02 03 Reserved 01 INTEN 00 Reserved Control Register page 5 4 Description Start Execution 1 Initiates board operation 0 Inhibits board operation After execution has begun writing a logic 0 will halt the board after completing the current 1553 message Start BIT Built In Test routine 1 Places the board into the Built In Test routine The BIT test takes 1msec to execute and has a fault coverage of 93 4 If the channel has been started the host must halt the board in order to place it into the Built In Test mode STEX 0 Note If Start BIT SBIT and Start Execution STEX are both set on one register write BIT has priority Set to 0 Extended Response Time Out 1 Enables the extended response time out option and forces the BM mode to look for an RT s response time in 30usec or generate time out errors 0 Enables for the standard time out in 14usec Set to 0 Bus Monitor Control This bit det
32. 1 6 1 1 Interrupt Identification Word W ees ee ee ee ee Re ee ee 6 2 6 1 2 Interrupt Address Word IAW e ees ee ee ee ee ee Re ee ee 6 2 6 1 3 Interrupt Log List Address ee Re Re Re ee Re ee ee ee 6 3 7 Mechanical and Electrical SpecificationS sesse ese 7 1 el Board Laat siet ER ER DE GE DE DE SO 7 1 T2 LED ie se EE OE cero cee 7 2 7 8 SUMIPO S EE EER BEE ES EE GE EE EE ay 7 2 7 3 1 VO Address Decoding JumperS iese se ee ee ee RR ee ee 7 2 7 3 2 Board Logical Address JumperS see ee ee ee ee ee ee ee 7 3 7 3 3 Interrupt Select Jumpers iese ke ee ee ee AR ee ee ee ke 7 3 7 3 4 Channel 0 Channel 1 and Channel 2 ee ee ee ee ee ee ee EE EER EE EE EE EE 7 4 7 3 5 Factory Default Jumper Settings iese ese ke ee Re ee ke ee ee 7 4 7 4 Connectors ARE erate AE RE N AN 7 5 7 4 1 Connectors J1 J2and J8 Ee EE EE Ee Ge SERS ee eka ee EE Ne EE 7 5 7 4 2 PC 104 Bus Connectors Pinout Connectors P1 and P2 nasses 7 7 7 5 Power Requirement iss esse Re ee 7 8 8 Ordering Information ee RR RE RR EE EER nnmnnn 8 1 Appendi S sa ei Se KEN ed N eg EE We ee ENS WERE 9 1 Appendix A MIL STD 1553B Word Formats sesse sees 9 1 Appendix B MIL STD 1553B Message Formats iss ese 9 2 EXC 1553P104 MCH3 User s Manual page iii Contents Figures page iv Figure 1 1 Figure 1 2 Figure 1 3 Figure 1 4 Figure 1 5 Figure 2 1 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 F
33. 1553B response in 14usec 0 1 1553B standard extended response in 30usec 1 0 1553A standard 1553A response in 9usec 1 1 1553A standard extended response in 21sec Table 5 1 MIL STD 1553A B Operation BM Mode When configured as a MIL STD 1553A bus monitor the EXC 1553P104 MCHS will operate as follows e Looks for the RT response within 9usec Ignores the T R bit for all mode codes Defines all mode codes without data e Defines subaddress 00000 as a mode code page 5 16 Excalibur Systems Chapter 6 6 1 Channel Interrupt Architecture Channel Interrupt Architecture Chapter 6 describes the channel interrupt architecture The following topics are covered Overview page 6 1 Interrupt Identification Word page 6 2 Interrupt Address Word page 6 2 Interrupt Log List Address page 6 3 Overview The EXC 1553P104 MCH3 channel interrupt architecture involves three Control Registers an Interrupt Log List and the interrupt line The three Control Registers include a Pending Interrupt Register Interrupt Mask Register and Interrupt Log List Register The Pending Interrupt Register contains information that identifies the events generating the interrupts The Interrupt Mask Register allows the user to mask or disable the generation of interrupts The Interrupt Log List Register contains the base address of a 32 word interrupt ring buffer The lower twelve interrupt bits of the Pending Interrupt Register are entered
34. 2 11 10 Mode Code 0034 OF OE OD 0C OB OA 09 08 07 06 05 04 03 02 0 00 Transmit 0036 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 18 12 11 10 Mode 0038 OF OE OD oC OB OA 09 08 07 06 05 04 03 02 00 Broadcast Receive 003A iF 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10 Mode 003C OF OE OD oC OB OA 09 08 07 06 05 04 03 02 00 Broadcast Transmit 003E YY YY YY YY YY YY YY YY YY YY YY YY YY VY VY YY Table 4 2 Illegalization Register Map EXC 1553P104 MCH3 User s Manual page 4 13 Chapter 4 4 2 Remote Terminal Operation 1 XX Automatically illegalized by EXC 1553P104 MCH3 2 YY Automatically illegalized by EXC 1553P104 MCH3 in 1553B only 3 ZZ Automatically illegalized by EXC 1553P104 MCH3 in 1553B and 1553A if XMTSW is enabled 4 WW Automatically illegalized in 1553A 5 UU Automatically illegalized in 1553A if XMTSW enabled Descriptor Block To process messages the board uses data from the Control Registers with data stored in the RAM The board accesses a 4 word descriptor block stored in RAM The descriptor block is accessed at the beginning and end of Command processing Multiple descriptor blocks are sequentially entered into memory to form a descriptor table The following paragraphs discuss the descriptor block in detail The host controlling the board allocates 512 consecutive memory spaces for the subaddress and mode code descriptor table see Figure 4 2 page 4 16 The top of the descriptor table can reside
35. 3 07 Reserved set to 0 02 IS2 1 Channel 2 Interrupt Active 01 IS1 1 Channel 1 Interrupt Active 00 ISO 1 Channel 0 Interrupt Active Interrupt Status Reset Register Read Definition NOTE The board specific interrupt line IRQ2 IRQ3 etc JP1 JP11 is chosen through jumpers on the board The source of this interrupt comes from one of the channels Each channel has a Pending Interrupt register containing the cause of the last interrupt page 1 8 Excalibur Systems Chapter 1 Introduction 1 5 General Memory Map The EXC 1553P104 MCH3 has three channels installed on the board but it uses only 32K bytes of PC memory This is implemented via a bank 0 5 switching mechanism At any given time only 32K bytes of the board s memory are available Figure 1 5 illustrates the memory allocation of the EXC 1553P104 MCH3 board Channel 0 Channel 1 Channel 2 Memory Area Memory Area Memory Area BANK BANK BANK BANK BANK BANK 0 1 2 3 4 5 Figure 1 5 General Memory Map EXC 1553P104 MCH3 User s Manual page 1 9 Chapter 2 General Channel Operation General Channel Operation Chapter 2 describes the general channel operation of the EXC 1553P104 MCH8 which applies to each available 1553 channel on the board Each 1553 channel occupies a 32K word area of the board s Memory Address Space This area is shared between the Channel Memory Block used for data and message control and the Channel Register Block used for variou
36. 3A Operation BC Mode page 3 17 Bus Controller Message Processing To process messages the EXC 1553P104 MCH3 uses data supplied in the control registers along with data stored in RAM memory The board accesses eight words stored in RAM memory called a command block The command block is accessed at the beginning and end of command processing NOTE In BC mode the board does not need to re read the Command Block on a retry situation The user allocates memory spaces for the minor frame The top of the command blocks can reside at any address location Defined and entered into memory by the user the control registers are linked to the Command Block via the Command Block Pointer Register contents Each command block contains a Control Word Command Word1 Command Word2 Data Pointer Status Word 1 Status Word 2 Branch Address and Timer Value This chapter provides a complete description of each location Control Word information allows the board to control the commands transmitted over the 1553 bus The Control word allows the board to transmit commands on a specific bus perform retries initiate RT to RT transfers and interrupt on certain conditions The host defines each Command Word associated with each command block For normal 1553 commands only the first Command Word location will contain valid data For RT to RT commands as specified in the Control Word the host must define the first Command Word as a receive and the second Comm
37. 53A or 1553B Standard This bit determines whether the board will look for the RT s response in 9usec MIL STD 1553A or in 15usec MIL STD 1553B 1 Forces the board to declare a time out error condition if the RT has not responded in 9usec 0 Allows the board to declare a time out error condition if the RT has not responded in 15usec These read only bits should be ignored on read Set to 0 Channel Executing This read only bit indicates whether the channel is presently executing or whether it is idle 1 The channel is executing 0 The channel is idle Set to 0 Channel Ready This read only bit is cleared on reset 1 The channel has completed initialization or BIT and regular operation may begin Channel Terminal Active This read only bit is cleared on reset 1 The board is presently processing a message page 5 5 Chapter 5 5 2 3 5 2 4 5 2 5 Bus Monitor Operation Current Command Register Address 0004 H READ ONLY The Current Command Register contains the last valid command that was transmitted over the 1553 bus In an RT to RT transfer this register will update as each of the two commands are received by the Bus Monitor Bit Bit Name Description 00 15 CC 15 0 Current Command These bits contain the latest 1553 word that was received by the Bus Monitor Current Command Register Interrupt Mask Register Address 0006 H READ WRITE The EXC 1553P104 MCHS interrupt architecture all
38. C Monitor Block Count Equal Zero BM Mode Interrupt Identification Word IIW Interrupt Address Word IAW The Interrupt Address Word is a 16 bit word that identifies the interrupt source The IAW has different meanings in each mode of operation The IAW in e RT mode identifies the subaddress or mode code descriptor that generated the interrupt e BC mode points to the command block addressed when the interrupt occurred e BM mode marks the monitor counter count when the interrupt occurred Use the IAW with the Initial Monitor Command Block Pointer Register to determine the monitor command block that generates the interrupt When in RT Concurrent BM mode the user determines if the LAW contains information for the RT or the BM The determination is made by comparing the contents of the IAW base address with the descriptor base address Ifa match occurs then the IAW contains a subaddress or mode code identifier If no match occurs the IAW contains monitor counter information page 6 2 Excalibur Systems Chapter 6 6 1 3 Channel Interrupt Architecture Interrupt Log List Address The Interrupt Log List resides in a 32 word ring buffer The host defines the location buffer within the memory space via the Interrupt Log List Register Restrict the ring buffer address to a 32 word boundary During initialization write a value to the Interrupt Log List Pointer Register Initialize the least significant five bits to a logic 0
39. Chapter 4 4 2 4 Remote Terminal Operation Mode Code Transmit Control Word Information contained in the Mode Code Transmit Control Word assists the EXC 1553P104 MCH3 in message processing The following bits describe the transmit mode code descriptor Control Word The user initializes the descriptor Control Word and the board updates it during Command post processing NOTE Bit 07 15 06 05 04 03 02 01 00 In MIL STD 1553A all mode codes are without data and the T R bit is ignored Bit Name Reserved IWA IBRD BAC Reserved A B BRD Reserved Description Set to 0 Interrupt When Accessed 1 Enables the generation of an interrupt when mode code Command is received The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing Interrupt Broadcast Received 1 Enables the generation of an interrupt when a broadcast mode code is received The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing Block Accessed The host initializes this bit to 0 the board overwrites the 0 with a logic 1 upon completion of message processing Upon reading a 1 the host resets this bit to 0 in preparation for the next message Set to 0 Buffer A B This bit indicates the last buffer accessed when buffer ping pong is enabled Dur
40. Circular Buffer Modes is ee ee ee ee ee 4 32 4 4 1 Mode 1 Operation esse see ke ee RA Re Re a ee ge ee ee de 4 32 4 4 2 Mode 1 Descriptor Block sscceeeesseeeeeesneeeeeneeeeeenaeeeeeseeeeeenneeees 4 32 4 4 3 Mode 1 Circular Buffer ee ke Re Re Re ee Re ee Re 4 33 4 4 4 Mode 2 Operation ceccecesccesseeseneeeeeeeeeeeeeeseeeeaeeesaeeseaeeesaressaeeesaees 4 34 4 4 5 Mode 2 Descriptor Block sscceeeesseeeeeesneeeeeneeeeseneeeseeneeeesenaeeees 4 35 4 4 6 Mode 2 Circular Buffer ie ee ke Re Re Re ee Re ee Re 4 36 4 5 Mode Code and Subaddress cccccececceeeeeeeeeseeeeeees 4 38 46 Encoder and Decodel is sg oe ee Cae 4 41 4 7 RT to RT Transfer Compare ccceeeeeeeeeeeeeeeeeees 4 41 4 8 Terminal Address ie aiden heel ated oie iat 4 42 4 LESBIER DER DER ES EA EA DRS RE 4 42 4 10 MIL STD 1553A Operation RT Mode 0008 4 43 5 Bus Monitor Operation ivicciscccscccscteieiisiecsescleeatteceersenccccews 5 1 5 1 Bus Monitor Message Processing i iis ee ee ee ee 5 1 5 1 1 Error Condition Message Processing sisie ses ee ee ea ke ee ea ee 5 2 5 2 Control Registers BM Mode ee ee 5 3 5 2 1 Gontrol Redisters EERS EREGAS BERE EER Re ee Gee OS ESE De Ne eg ee 5 4 5 2 2 Operational Status Register ees ee ke ee Re Re RR ee bee 5 5 5 2 3 Current Command Register iese ee ee ke Re ee ge ee 5 6 5 2 4 Interrupt Mask Register esse ee ee Re ee Re Re e
41. E Do not change this register while BM mode is active i e Operational Status Register bit 03 1 Bit Bit Name Description 00 15 MBA 15 0 Initial Monitor Data Address These bits indicate the starting location of the Monitor Data Initial Monitor Data Pointer Register page 5 8 Excalibur Systems Chapter 5 5 2 11 5 2 12 5 2 13 Bus Monitor Operation Monitor Block Counter Register Address 001A H READ WRITE The Monitor Block Counter register contains the number of Monitor Blocks you want to log After execution begins the register automatically decrements as commands are logged When this register is decremented from 1 to 0 an interrupt will be generated if enabled The board will start over at the initial pointers as identified in the Initial Monitor Block Pointer Register and the Initial Monitor Data Pointer Register NOTE It is recommended that this register not be changed while the BM mode is active i e Operational Status Register bit 03 1 Bit Bit Name Description 00 15 MBC 15 0 Monitor Block Count These bits indicate the number of Monitor Blocks to log Monitor Block Counter Register Monitor Filter Hi Register Address 001C H READ WRITE The Monitor Filter Hi register determines which RTs RT 31 through RT 16 the board will monitor Bit Bit Name Description 00 15 MFH 31 16 Monitor Filter These bits determine which RT to monitor Monitor Filter Hi Register Monitor Filter Lo Re
42. EXC 1553P104 MCH3 MIL STD 1553 TEST AND SIMULATION BOARD FOR PC 104 COMPATIBLE COMPUTERS User s Manual NM XCA LIB EXCALIBUR SYSTEMS 311 Meacham Avenue Elmont N Y 11003 Tel 516 327 000 Fax 516 327 4645 e mail excalibur mil 1553 com website www mil 1553 com Contents 1 Contents IA TFOCUCHION ERG Ee ee ee al 1 1 Wed OVERVIEW ae thee EE ED Ee a 1 1 EXC 1553P104 MGH3 Board FeatureS esse sesse ee see ee ee ee ee 1 2 t2 ei EE EE EE EE a 1 3 1 2 1 Software Installation is EES ee sie ESEL SE Pe KOEK Gee Re Eg ENE GO Ee ee 1 3 1 2 2 Board SE Uie OR ER aeiaai inap eE pa iaka Rainiaea 1 3 1 3 1553 Bus Gonneeons Ee EE seg es ee ge ge See gees 1 5 1 4 General I O Map N ee ge ee Pe Se 1 6 1 4 3 Software Reset Register iese ee ee Re ee Re ke Re ee ge ee 1 6 1 4 4 Bank Select Register see ee Re ee Re ee RA ee ee ee ea 1 7 1 4 5 Interrupt Status Reset Register esse ee ee Re ee RR ee ee 1 8 1 5 General Memory Map ai n ee De eed 1 9 General Channel Operation ee eie EE EE EE 2 1 Bus Controller Operation ee EE EER EER EER EE EE 3 1 3 1 Bus Controller Message ProcessiNg iss ee ee ee 3 1 3 2 Control Registers BC Mode ees ee 3 2 3 2 1 Control Register EE EE iin A Gee Ee Es oe PER Es alee N EE ee 3 3 3 2 2 Operational Status Register ees ee Re ee Re ee Re ee ee 3 4 3 2 3 Current Command Register ee ee ee Re Re Re Re ge ee 3 5 3 2 4 Interrupt Mask Register
43. List Pointer register indicates the starting address of the Interrupt Log List See Interrupt Log List Address page 6 3 The Interrupt Log List is a 32 word ring buffer that contains information pertinent to the service of interrupts The board architecture requires the location of the Interrupt Log List on a 32 word boundary The most significant 11 bits of this register designate the location of the Interrupt Log List within a 64K word memory space Initialize the lower five bits of this register to a logic 0 The board controls the lower five bits to implement the ring buffer architecture This register is read to determine the location and number of interrupts within the Interrupt Log List least significant five bits Bit Bit Name Description 00 15 ILLP 15 0 Interrupt Log List Pointer Bits Bits 05 15 indicate the starting Base Address while Bits 00 04 indicate the ring location of the Interrupt Log List Interrupt Log List Pointer Register BIT Word Register Address 000C H READ WRITE The BIT Word register contains information on the current status of the board Bit Bit Name Description 15 DMAF DMA Fail 1 All the channels internal DMA activity has not been completed within 7usec 13 14 Reserved Setto0 12 BITF BIT Fail 1 A BIT failure Interrogate bits 11 and 10 to determine the specific bus that failed 11 BUAF Bus A Fail 1 A BIT test failure in Bus A 10 BUBF Bus B Fail 1 A BIT test failure in
44. P31 and JP32 Factory Default Jumper Settings The factory default settings are JP25 JP36 Pins 1 amp 2 Shorted Transformer Coupled mode for all channels JP12 JP16 JP18 Shorted VO Base Address 0280 H JP20 JP22 Shorted Logical Address Segment DOOOO H JP4 Shorted Interrupt selected to IRQ5 page 7 4 Excalibur Systems Chapter 7 7 4 7 4 1 EXC 1553P104 MCH3 User s Manual Mechanical and Electrical Specifications Connectors The EXC 1553P104 MCHS contains five Connectors e Three 5 pin Right angle Connectors 0 1 spacing J1 J2 amp J3 one per channel e One 64 pin Stackthrough Connector with key P1 e One 40 pin Stackthrough Connector with key P2 Connectors J1 J2 and J3 The three 5 pin Molex Right angle Connectors P N 90136 2105 contain all the relevant signals for a specific channel Mating Connectors P N 90156 0145 with crimp terminals P N 90119 2111 are included Each Connector is associated with a specific channel Channel 0 with Connector J1 Channel 1 with Connector J2 and Channel 2 with Connector J3 Figure 7 2 Connectors J1 and J2 Layout Front View Pin Connector J1 Pin Connector J2 Pin Connector J3 1 BUSAHI 0 1 BUSAHI 1 1 BUSAHI 2 2 BUSALO 0 2 BUSALO 1 2 BUSALO 2 3 SHIELD 3 SHIELD 3 SHIELD 4 BUSBLO 0 4 BUSBLO_1 4 BUSBLO_2 5 BUSBHIO 5 BUSBHI 1 5 BUSBHI 2 Connectors J1 J2 and J3
45. PF bit is set The loopback path is via the MIL STD 1553 bus transceiver 13 Reserved Ignore on read 12 BITF BIT Fail 1 A BIT failure Interrogate bits 11 through 08 to determine the specific failure 11 BUAF Bus A Fail 1 A BIT test failure in Bus A 10 BUBF Bus B Fail 1 A BIT test failure in Bus B 09 MSBF Memory Test Fail Most significant memory byte failure 08 LSBF Memory Test Fail Least significant memory byte failure 00 07 UDB 7 0 User Defined Bits BIT Word Register EXC 1553P104 MCH3 User s Manual page 3 7 Chapter 3 3 2 8 3 2 9 Bus Controller Operation Minor Frame Timer Register Address 000E H READ ONLY The Minor Frame Timer register MFT reflects the state of the 16 bit MFT counter This counter is loaded via the Load Minor Frame Timer opcode Opcode 1110 Bit Bit Name Description 00 15 MFT 15 0 Minor Frame Timer These bits indicate the value of the timer Minor Frame Timer Register Command Block Pointer Register Address 0010 H READ WRITE The Command Block Pointer register contains the location to start the Command Blocks After execution begins this register is automatically updated with the address of the next block Bit Bit Name Description 00 15 CBA 15 0 Command Block Address These bits indicate the starting location of the Command Block Command Block Pointer Register page 3 8 Excalibur Systems Chapter 3 3 3 Bus Controller Operation BC Architectu
46. Re ee bee 4 5 4 1 3 Current Command Block Register see ee ee Re Re Re ge ee 4 6 4 1 4 Interrupt Mask Register ees ee ee ee Re Re ee ee ee ee Re ee ee ee 4 6 4 1 5 Pending Interrupt Register ese ee Re ee ee ee Re ee ee 4 7 4 1 6 Interrupt Log List Pointer Register ees see ee ee ee ee ee Re ee ee ee 4 8 4 1 7 BIT Word Register tes EE este sti SS Wieder Gee ge EE BENE Es Des 4 9 4 1 8 Time Tag Register eraa EE EE EE OE RE N 4 10 4 1 9 RT Descriptor Pointer Register ese ese ee ee ee ee Re ee 4 10 4 1 10 1553 Status Word Bits Register iese ee ee ee RA ee ke ee 4 11 4 1 11 legalization Registers ees ee ee ee Re ee ee ee ee ee Re ee 4 12 4 2 Descriptor Block AE DR i AD 4 14 4 2 1 Receive Control Word ee ee ee Re Re ee Re ee Re ee Re ee 4 17 4 2 2 Transmit Control Word ee ek Re ee ke Re 4 18 4 2 3 Mode Code Receive Control Word ee ee Re ee Re 4 19 4 2 4 Mode Code Transmit Control Word ee Re Re 4 20 4 2 5 Data Pointer A and B Mode 0 ee ee Re ee ee Ee ee 4 21 4 2 6 Ping Pong Handshake Mode 0 ees ee ee Re ee ee ee ee ee 4 24 4 2 7 Broadcast Data Pointer Mode 0 0 es ceeeseeeeenseeeeeenereeesnneeeeteeeees 4 25 43 Data Structures Es Es ESE EE BE Eg ee GREG ge DE seed 4 26 4 3 1 Subaddress Receive Data sees ee Re ee Re ee Re ee ee 4 26 4 3 2 Subaddress Transmit Data sesse ese ee ke ee Re ee Re ee ee 4 28 4 3 3 Meel ee APE ERNA EA ne Mannie eet eee eed 4 29 4 4 RT
47. Register Words Time Tag Reserved Msg Info Wd CMD Words Data Ptr Sts Words Time Tag Reserved Msg Info Wd CMD Words Data Ptr Sts Words Time Tag Reserved Figure 5 5 Memory Architecture for Bus Monitor Mode page 5 14 Excalibur Systems Chapter 5 5 6 Bus Monitor Operation RT Concurrent Monitor Operation For applications that reguire simultaneous Remote Terminal and Bus Monitor operation the board should be configured as both a remote terminal and bus monitor This feature allows the RT to communicate on the bus for one specific address and to monitor the bus for other specific addresses Configuration as both Bus Monitor and RT precludes the board from monitoring its own remote terminal address When the board is configured as both RT and Bus Monitor the RT has priority over the Bus Monitor For example commands to the RT will always take priority over commands for the Bus Monitor The examples below describe what happens if the RT is defined for terminal address 1 and the Bus Monitor is to monitor terminal address 12 Example 1 Bus A CMD TA 12 Bus B CMD TA 1 In this example the Bus Monitor will decode the first command on bus A realize the message is for terminal address 12 and start monitoring the message However as soon as the board realizes the second command on bus B is to terminal address 1 the RT will take priority and begin RT message processing Example 2 Bus A CMD TA 1 B
48. TF bit set if BITF bit asserted Command Word stored Status Word transmitted Alternate bus disabled POND Command Word stored Status Word transmitted Alternate bus enabled Note Reception of the override transmitter shut down mode code does not enable a channel not previously enabled in the Control Register Reset remote terminal mode code clears the transmitter shut down function WE DR 1 Command Word stored 2 Terminal flag bit set to 0 and assertion disabled 3 Status Word transmitted Command Word stored Terminal flag bit enabled for assertion Status Word transmitted W oo Command Word stored Status Word transmitted Software reset AM Command Word stored Status Word transmitted ND Command Word stored Service reguest bit set to a logic zero in out going Status Status Word transmitted Data Word transmitted Clears the SRQ bit in the 1553 Status Word Bits Register ND ORO 1 Command Word stored 2 Status Word transmitted 3 Data Word stored Mode Code Description continues on next page page 4 39 Chapter 4 T R 1 1 1 1 Table 4 4 page 4 40 Remote Terminal Operation Mode Code Function Operation 10010 Transmit Last Command 5 1 Command Word stored 2 Last Status Word transmitted 3 4 Data Word stored Transmit Last Last Command Word transmitted Command Transmitted Data Word is all 0 after reset Note The board stores the Transmit
49. a Pointer A gt 0200 H XXXX Reserved for Transmit Info Word equals 0100 H 0202 H XXXX Reserved for Time Tag Word 0204 H FFFF Data Word 1 0206 H FFFF Data Word 2 0208 H FFFF Data Word 3 NOTE Data Pointer A points to the top of the Data structure not to the top of the Data Words TRANSMIT INFORMATION WORD The following bits describe the Transmit Information Word contents Bit Bit Name Description 11 15 WC 4 0 Word Count Bits These five bits contain Word count information extracted from the receive Command Word bits 15 to 19 10 Reserved Ignore on read 09 BUA B Bus A B 1 The message was received on Bus A 0 The message was received on Bus B 08 Reserved Ignore on read 07 ME Message Error 1 A message error condition was observed during processing See bits 00 to 04 for more detail 05 06 Reserved Ignore on read 04 ILL Illegal Command Received 1 The Command received was an illegal Command 03 Reserved Ignore on read 02 OVR Overrun Error 1 The board received a Data Word with a Transmit Command 00 01 Reserved Ignore on read Transmit Information Word page 4 28 Excalibur Systems Chapter 4 4 3 3 Remote Terminal Operation Mode Code Data The Transmit and Receive Data Structures for mode codes are similar to those for a subaddress The receive Data structure contains an Information Word Time Tag Word and message Data Word All receive mode codes with data have one
50. and Word as a transmit EXC 1553P104 MCH3 User s Manual page 3 1 Chapter 3 3 2 Bus Controller Operation For a receive command the Data Pointer is read to determine where Data Words are retrieved The board retrieves Data Words seguentially from the address specified by the Data Pointer Fora transmit command the Data Pointer is read to determine the top memory location The board stores Data Words seguentially from this top memory location The board reads the command block during minor frame processing The board then begins the acguisition of Data Words for either transmission or storage After transmission or reception the board begins post processing The command block is updated The board modifies the Control Word as reguired An optional interrupt log entry is performed after the command block update Control Registers BC Mode The control registers are read write unless otherwise stated All control registers must be accessed in word mode All control register bits are active high and are reset to 0 unless otherwise stated Figure 3 1 below illustrates the control registers for Bus Controller mode Reserved 0012 003E H Command Block Pointer Register 0010H Minor Frame Timer OOOE H BIT Word Register 000C H Interrupt Log List Pointer Register OOOA H Pending Interrupt Register 0008 H Interrupt Mask Register 0006 H Current Command Block Register 0004 H Operational Status Register 0002 H Control Register
51. are cleared on a host read Bit Bit Name 12 15 Reserved 11 MERR 06 10 Reserved 05 EOL 04 ILLCMD 03 ILLOP 02 RTF 01 CBA 00 Reserved Pending Interrupt Register page 3 6 Description Ignore on read Message Error Interrupt 1 A message error occurred The board can detect Manchester sync field word count 1553 word parity bit count and protocol errors This bit will be set and an interrupt generated if not masked after message processing is complete Ignore on read End Of List Interrupt 1 The board is at the end of the command block llogical Command Interrupt The board checks for RT to RT Terminal address field match RT to RT transmit receive bit mismatch and correct order and broadcast transmit commands If illogical commands occur the board will halt execution 1 An illogical command i e Transmit Broadcast or improperly formatted RT RT message has been written into the Command Block Illogical Opcode Interrupt 1 An illogical opcode i e any reserved opcode was used in the command block The board halts operation if this condition occurs Retry Fail Interrupt 1 All programmed retries failed Command Block Accessed Interrupt 1 A command block was accessed Opcode 1010 if enabled Ignore on read Excalibur Systems Chapter 3 3 2 6 3 2 7 Bus Controller Operation Interrupt Log List Pointer Register Address 000A H READ WRITE The Interrupt Log List Poin
52. art address in the Initial Monitor Block Pointer Register Figure 5 4 shows the Monitor Block as the blocks execute in a contiguous fashion Monitor Block 1 p Monitor Block 2 p Monitor Block 3 L Monitor Block 4 p Monitor Block 5 L p Monitor Block 6 Figure 5 4 Bus Monitor Block Structuring EXC 1553P104 MCH3 User s Manual page 5 13 Chapter 5 5 5 Bus Monitor Operation Memory Architecture The configuration shows the Monitor Blocks data locations and the Interrupt Log List as separate entities Figure 5 5 shows that the first block of memory is allocated for the Monitor Blocks Notice that the Initial Monitor Block Pointer Register points to the initial Monitor Block location the Initial Monitor Data Pointer Register points to the initial Data location Interrupt Log List Pointer Register points to the Interrupt Log and the Monitor Block Counter Register contains the Monitor Block count After execution begins the board will build command blocks and store Data Words until the count reaches 0 When the count reaches 0 the board will simply wrap back to the initial values and start again Register Monitor Register Data Register Interrupt Blocks Storage Log List Initial Msg Info Initial Memory Interrupt Int Info Monitor Wd CMD Monitor Log List Wd Block Words Data Pointer Monitor Pointer Data Ptr Pointer Register Block Register Sts
53. ase Address 10 H IIW 5 Base Address 30 H IW 13 Base Address 12 H IAW 5 Base Address 32 H IAW 13 Base Address 14 H IIW 6 Base Address 34 H IIW 14 Base Address 16 H IAW 6 Base Address 36 H IAW 14 Base Address 18 H IIW 7 Base Address 38 H IIW 15 Base Address 1A H IAW 7 Base Address 3A H IAW 15 Base Address 1C H IIW 8 Base Address 3C H IIW 16 Base Address 1E H IAW 8 Base Address 3E H IAW 16 oe E I EE DE Interrupt Log List Interrupt Log List Address Register Contents Address Register Contents Table 6 1 Interrupt Ring Buffer EXC 1553P104 MCH3 User s Manual page 6 3 Chapter 6 Channel Interrupt Architecture page 6 4 Excalibur Systems Chapter 7 Mechanical and Electrical Specifications 7 Mechanical and Electrical Specifications Chapter 7 describes the mechanical and electrical specifications of the EXC 1553P104 MCHS board The following topics are discussed Board Layout page 7 1 LED Indicators page 7 2 Jumpers page 7 2 Connectors page 7 5 Power Requirements page 7 8 7 1 Board Layout 1G 13 BU A BUS B al j E CHANNEL 2 Aa LIE T4 T3 N rm oz IZ Fi lo D x a Z MEM ADD lt T2 T1 qJP19 Q N BUSA BUSE 5
54. associated Data Word Data storage occurs at the memory location pointed to by the Data pointer plus two 16 bit locations Reception of the synchronize with Data mode code automatically loads the Time Tag counter and stores the Data Word at the address defined by the Data pointer plus two 16 bit locations The transmit mode code Data structure contains an Information Word Time Tag Word and associated Data Word The host is responsible for linking the board Data Pointer to the data e g Transmit Vector Word For mode codes with internally generated Data Words e g Transmit BIT Word Transmit Last Command the transmitted Data Word is added to the Data structure For MIL STD 1553A mode of operation all mode codes are defined without Data Words For mode codes without data the Data structure contains the Message Information Word and Time Tag Word only NOTE In MIL STD 1553A all mode codes are without data and the T R bit is ignored EXC 1553P104 MCH3 User s Manual page 4 29 Chapter 4 Remote Terminal Operation MODE CODE RECEIVE INFORMATION WORD The following bits describe the Mode Code Receive Information Word contents Bit Bit Name 11 15 MC 4 0 10 Reserved 09 BUA B 08 RTRT 07 ME 05 06 Reserved 04 ILL 03 TO 02 OVR 01 PRTY 00 MAN Description Mode Code These five bits contain the mode code information extracted from the receive Command Word bits 15 to 19 Ignore on read Bus A B 1 The message was re
55. at any address location The Control registers are linked to the descriptor table via the Descriptor Address Register contents Each descriptor block contains a Control Word Data Pointer A Data Pointer B and Broadcast Data Pointer Each subaddress and mode code is assigned a descriptor for receive and transmit Commands T R bit equals zero or one Control Word information allows the board to generate interrupts buffer messages and control message processing For a receive Command the Data List Pointer is read to determine the top of the data buffer The board stores data sequentially from the top of data buffer plus two locations e g 0100H 0102H 0104H 0106H etc When processing a transmit Command the Data List Pointer is read to determine where Data Words are retrieved The board retrieves Data Words sequentially from the address the Data List Pointer designates plus two 16 bit address locations The Broadcast Data Pointer allows for separate storage of non broadcast data from broadcast data per MIL STD 1553B Notice II The user enables or disables this feature via the Control Word s least significant bit When disabled the non broadcast and broadcast data is stored via Data List Pointer A or B For transmit Commands the Broadcast Data Pointer is not used The board does not transmit any information on the receipt of a broadcast transmit Command page 4 14 Excalibur Systems Chapter 4 Remote Terminal Operation The board r
56. ation Data Pointer The fourth location of the BC Mode Command Block is the data pointer that points to the first memory location to store or retrieve the Data Words associated with the message for that command block This data structure allows the board to store or retrieve the exact specified number of Data Words thus saving memory space and providing efficient space allocation NOTE In an RT to RT transfer the board uses the data pointer as the location in memory to store the transmitted data in the transfer One common application for the data pointer occurs when the board needs to send the same data words to several RTs Here each Command Block associated with those messages would contain the same data pointer value and therefore retrieve and transmit the same data Note that the Data Pointer is never updated i e the board reads and writes the pointer but never changes its value 1553 Status Words The next two locations in the BC Mode Command Block are for Status Words As the RT responds to the BC s command the corresponding Status Word will be stored in Status Word 1 In an RT RT transfer the first Status Word will be the status of the Transmitting RT while the second Status Word will be the status of the Receiving RT Branch Address The seventh location in the BC Mode Command Block contains the starting location of the branch This location simply allows the board to branch to another location in memory when cer
57. buffers wrap around page 4 34 Excalibur Systems Chapter 4 4 4 5 Remote Terminal Operation Mode 2 Descriptor Block Each subaddress and mode code both transmit and receive has a unique pair of circular buffers The board decodes the Command Word T R bit subaddress mode field and Word_count mode_code field to select a unique descriptor block which contains Control Word TA CA and MIB see Figure 4 7 page 4 37 To implement Circular Buffer 2 s architecture the descriptor block and Control Register are different than in Mode 0 Bits 15 through 08 of the Control Word specify the Message Information Buffer MIB length the maximum MIB size is 256 Table 4 3 shows how the Control Word s most significant bits select the depth of the MIB The Control Words eight most significant bits remain static during message processing The second Word of the description block defines the top address TA of the Data circular buffer The TA pointer remains static during message processing The third descriptor Word identifies the current address i e CA of the Data circular buffer The application software reads the dynamic CA pointer to determine the current address of the Data buffer The board increments the CA pointer at the end of message processing until the MIB buffer is full When the MIB wraps around the SUMMIT loads the CA pointer with the TA pointer The fourth Word in the descriptor block defines the top or base address o
58. ceived on Bus A 0 The message was received on Bus B Remote Terminal to Remote Terminal Transfer 1 The Command processed was an RT to RT transfer Message Error 1 A message error condition was observed during processing See bits 00 to 04 for details Ignore on read Illegal Command Received 1 The Command received was an illegal Command Time out Error 1 The board did not receive the proper number of Data Words i e the number of Data Words received was less than the Word count specified in the Command Word Overrun Error 1 The board received a Word when none was expected or the number of Data Words received was greater than expected Parity Error 1 The board observed a parity error in the incoming Data Words Manchester Error 1 The board observed a Manchester error in the incoming Data Words Mode Code Receive Information Word page 4 30 Excalibur Systems Chapter 4 Remote Terminal Operation MODE CODE TRANSMIT INFORMATION WORD The following bits describe the Mode Code Transmit Information Word contents Bit Bit Name 11 15 MC 4 0 10 Reserved 09 BUA B 08 Reserved 07 ME 05 06 Reserved 04 ILL 03 Reserved 02 OVR 00 01 Reserved Description Mode Code These five bits contain the mode code information extracted from the Command Word bits 15 to 19 Ignore on read Bus A B 1 The message was received on Bus A 0 The message was received on Bus B Ignore
59. d processing takes place i e no 1553 This opcode instructs the board to go to the command block as specified in the branch address location No command process takes place i e no 1553 This opcode instructs the channel to perform an internal built in test If the channel passes the built in test then processing of the next command block will continue However if the channel fails the built in test then processing stops No command processing takes place i e no 1553 This opcode instructs the board to execute the current command block and proceed to the next command block This opcode allows for continuous operations This opcode instructs the board to execute the current command block and unconditionally branch to the location as specified in the branch address location This opcode instructs the board to execute the current command block and branch only if the condition is met If no conditions are met the opcode appears as an execute and continue This opcode instructs the board to perform automatic retries as specified in the control word if particular conditions occur If no conditions are met the opcode appears as an execute and continue This opcode instructs the board to perform automatic retries as specified in the control word if particular conditions occur If the conditions are met the board retries Once all retries have executed the board branches to the location as specified in the branc
60. e ee ee ee ee 5 6 5 2 5 Pending Interrupt Register ese ee Re ee ee ee ee ee ee ee 5 6 5 2 6 Interrupt Log List Pointer Register ees sees ee ee ee ee Re ee ee ee 5 7 5 2 7 BIT Word Registers 00datie seen fe an Ge a 5 7 5 2 8 Time Tag Begistef Ese EERS cedaetesensuncenccctedee De Ee casks EER EE REF ee cvncees 5 8 page ii Excalibur Systems Contents 5 2 9 Initial Monitor Block Pointer Register iese see ee ee Re ee ee ee 5 8 5 2 10 Initial Monitor Data Pointer Register sesse ee ee Re ee ee ee 5 8 5 2 11 Monitor Block Counter Register iese see ee ee Re Re RA ee ee 5 9 5 2 12 Monitor Filter Hi Register sesse ees ese ee ee ee ee ee ee ee ee ee ee ee 5 9 5 2 13 Monitor Filter Lo Register ees ee ee ee ee ee ee ee ee ee ee ee ee 5 9 5 3 Bus Monitor Architecture iss ee ee ee ee 5 10 5 3 1 Message Information Word ees ee ee Re ee ee ee 5 10 5 3 2 Command WordS ss se ee Es deeded piece RD Ee Leiden ede Site 5 12 5 3 3 DEEA eli ER ER OR ER RE 5 12 5 3 4 Status WOrdS AR EA WEE OE EO N 5 12 5 3 5 BREER NE MEE aie EN 5 12 5 3 6 BR RE RE RE RE RR ER 5 12 5 4 Bus Monitor Block ChainiNg sesse ees ee ee ee 5 13 5 5 Memory Architecture i e ees see ee ee Ge ee 5 14 5 6 RT Concurrent Monitor OperatiON iese ee 5 15 5 7 MIL STD 1553A Operation BM Mode esse sees 5 16 6 Channel Interrupt Architecture sesse ese ee EER EER ERGE 6 1 6 1 SOVGIVIOW si EE DE EDE DR ED ED en nen 6
61. e with Data mode code The Time Tag counter begins operation in one of two cases e Either within 64usec of the rising final edge of a reset e Or the receipt of one of the following valid mode codes reset of the remote terminal syne with without data When the board is halted STEX bit 15 in the Control register 0 the Time Tag continues to run Bit Bit Name Description 00 15 TT 15 0 Time Tag Counter Bits Time Tag Register RT Descriptor Pointer Register Address 0010 H READ WRITE Each subaddress and mode code has a reserved block of memory containing information about how to process a valid Command to that subaddress or mode code Located contiguously in memory these reserved memory locations are called a descriptor space The RT Descriptor Pointer register contains an address that points to the top of this memory space The board uses the T R bit subaddress mode code field and mode code to select one block in the descriptor table for message processing The RT Descriptor Pointer register is static during message processing Bit Bit Name Description 00 15 RTDA 15 0 RT Descriptor Address Bits RT Descriptor Pointer Register page 4 10 Excalibur Systems Chapter 4 4 1 10 Remote Terminal Operation 1553 Status Word Bits Register Address 0012 H READ WRITE The 1553 Status Word Bits register controls the outgoing MIL STD 1553 Status Word The host controls the Instrumentation Busy Terminal Flag Se
62. eads the descriptor block during Command processing i e after assertion of TERACT The board reads the Control Word and three Data Pointers The board then begins the acguisition of Data Words for either transmission or storage After transmission or reception the board begins post processing The Descriptor Block is updated An optional interrupt log entry is performed after a descriptor update During the descriptor update the board modifies the Control Word index field and bits 4 2 and 1 if required The board updates Data Pointer A if no message errors occurred during the message transaction Reception of a broadcast Command with no message errors results in the update of the Broadcast Data Pointer Neither Data Pointer A or B is updated if the board has the ping pong mode of operation enabled EXC 1553P104 MCH3 User s Manual page 4 15 Chapter 4 Single Descriptor Block 6 Brdcast Data Pointer 4 Data Pointer B 2 Data Pointer A 0 Control Word RELATIVE ADDRESS 0000 E RECEIVE RELATIVE ADDRESS 0008 H RECEIVE RELATIVE ADDRESS 00F8 H RELATIVE ADDRESS 0100 H TRANSMIT RELATIVE ADDRESS 01F8 H TRANSMIT RELATIVE ADDRESS 0200 H RECEIVE RECEIVE RELATIVE ADDRESS 02F8 H RELATIVE ADDRESS 0300 H TRANSMIT RELATIVE ADDRESS 03F8 H TRANSMIT Figure 4 2 Descriptor Table page 4 16 Remote Terminal Operation SUBADDRESS 0 SUBADDRESS 1 SUBADDRESS 30 SUBADDRESS 31 SUBADDRESS 0 SUBADDRESS
63. egins at the address location pointed to by the TA pointer and CA is made to equal TA If CA is less than BA CA points to the next available memory location in the buffer i e CA 1 NOTE In this mode the Message Information Word bit 5 reflects the reception of broadcast message via the BRD bit The board generates a circular buffer empty full interrupt when the buffer reaches the end 1 e CA greater than BA and begins a new message at the top of the buffer Bit 08 of the Mask Register and bit 07 of the Descriptor Control Word mask enables the generation of the Full Empty interrupt EXC 1553P104 MCH3 User s Manual page 4 33 Chapter 4 Remote Terminal Operation Figure 4 6 describes the relationship between TA BA and CA e Data Words e e Time Tag Message Info Word CIRCULAR BUFFER Data Words e Time Tag Message Info Word CONTROL WORD Descriptor Block Figure 4 6 RT Mode 1 Descriptor Block and Circular Buffer 4 4 4 Mode 2 Operation In this mode the board separates message data and message information into unique circular buffers The separation of data from message information simplifies the software that loads and unloads data from the buffers The message information buffer contains Time Tag and Message Information Words for each message transacted on the bus while the data buffer contains the message Data Words After processing a pre determined number of messages both
64. er assignment The board decodes the Command Word T R bit subaddress mode code field and Word_count mode_code field to select a unique descriptor block that contains Control Word TA CA and BA see Figure 4 6 To implement Circular Buffer 1 s architecture the 4 word descriptor block and Control Register are different than in the Mode 0 Bits 15 through 08 of the Control Word are don t care The second Word of the descriptor block defines the buffer s starting or top address TA The TA pointer remains static during message processing The fourth entry into the descriptor block identifies the buffer s bottom address i e BA and also remains static during message processing The third descriptor block Words represent the current address i e CA in the buffer and is dynamic If the board observes no message error conditions the CA pointer updates at the end of message processing The application software reads the dynamic CA pointer to determine the current bottom of the buffer page 4 32 Excalibur Systems Chapter 4 4 4 3 Remote Terminal Operation The TA top of buffer and BA bottom of buffer pointers define the circular buffer s length The CA pointer identifies the current address i e last accessed address plus one The circular buffer wraps to the top address after completing a message that results in CA being greater than or equal to BA If CA increments past BA during intra message processing the board w
65. er will automatically be updated This register is updated when transmission of the Command Word begins In an RT to RT transfer the register will reflect the latest Command Word as it is transmitted Bit Bit Name Description 00 15 CC 15 0 Current Command These bits contain the latest 1553 command that was transmitted by the Bus Controller Current Command Register 3 2 4 Interrupt Mask Register Address 0006 H READ WRITE The BC Mode interrupt architecture allows the host to mask or temporarily disable the service of interrupts While masked interrupt activity does not occur The unmasking of an interrupt after the event occurs does not generate an interrupt for that event An interrupt is masked only if the corresponding bit of this register is set to a logic 0 Bit Bit Name Description 12 15 Reserved Set to 0 11 MERR Message Error Interrupt 06 10 Reserved Set to 0 05 EOL End Of List Interrupt 04 ILLCMD Illegal Command Interrupt 03 ILLOP Illogical Opcode Interrupt 02 RTF Retry Fail Interrupt 01 CBA Command Block Accessed Interrupt 00 Reserved Set to 0 Interrupt Mask Register EXC 1553P104 MCH3 User s Manual page 3 5 Chapter 3 3 2 5 Bus Controller Operation Pending Interrupt Register Address 0008 H READ ONLY The Pending Interrupt register is used to identify which of the interrupts occurred during operation The assertion of any bit in this register generates an interrupt NOTE All register bits
66. erated if enabled In addition to the loop back compare test a timer precludes a transmission greater than 800usec by the assertion of Fail Safe Timer This timer is reset upon receipt of another Command Remote Terminal Response Time MIL STD 1553A 7usec MIL STD 1553B 10usec Data Contiguity Time Out 1 0usec RT to RT Transfer Compare The RT to RT Terminal Address compare logic ensures that the incoming Status Word s Terminal Address matches the Terminal Address of the transmitting RT specified in the Command Word An incorrect match results in setting the message error bit and suppressing transmission of the Status Word RT to RT transfer time out 55 to 59usec The board does not check ME or SSYSF of the transmitting remote terminal when receiving EXC 1553P104 MCH3 User s Manual page 4 41 Chapter 4 4 8 4 9 Remote Terminal Operation Terminal Address The EXC 1553P104 MCH3 Terminal Address is programmed via the most significant six bits in the Operational Status Register RTA 4 0 and RTPTY The Terminal Address parity is odd RTPTY is set to a logic state to satisfy this requirement When the Operational Status Register bit 02 TAPE is set this indicates incorrect Terminal Address parity The Operational Status Register bit 02 is valid after the rising final edge of a reset For example RTA 4 0 05 H 00101 RTPTY 1 H 1 Sum of 1s 3 odd Operational Status Register Bit 02 0 RTA 4 0
67. eration MIL STD 1553A Operation BC Mode To maximize flexibility the EXC 1553P104 MCHB can operate in many different systems that use various protocols Specifically two of the protocols that the board may be used with are MIL STD 1553A and MIL STD 1553B To meet these protocols configure the board through the Control register ERTO Bit 09 and the Operational Status register A B_STD Bit 07 Table 3 1 defines the four ways to program the EXC 1553P104 MCH3 AIB STD ERTO RESULT 0 0 1553B standard 1553B response in 14 usec 0 1 1553B standard extended response in 30 usec 1 0 1553A standard 1553A response in 9 usec 1 1 1553A standard extended response in 21 usec Table 3 1 MIL STD 1553A B Operation BC Mode When configured as a MIL STD 1553A bus controller the board will operate as follows e Looks for the RT response within 9usec e Defines all mode codes without data e Defines subaddress 00000 as a mode code EXC 1553P104 MCH3 User s Manual page 3 17 Chapter 3 Bus Controller Operation page 3 18 Excalibur Systems Chapter 4 Remote Terminal Operation 4 Remote Terminal Operation Chapter 4 describes EXC 1553P104 MCH3 operation in Remote Terminal RT mode The following topics are covered Control Registers RT Mode page 4 2 Descriptor Block page 4 14 Data Structures page 4 26 RT Circular Buffer Modes page 4 32 Mode Code and Subaddress page 4 38 Encoder and Decoder page 4 41 RT to RT Transfer Compa
68. ermines whether the board will monitor all RTs or selected RTs 1 The board will monitor only the RTs as specified in the Monitor Filter Hi and Lo registers 0 The board will monitor all RTs Broadcast Enable 1 Enables the RT address 31 to be used as a message broadcast 0 Enables remote terminal address 31 as a normal address Set to 0 Interrupt Log Enable 1 Enables the interrupt logging feature 0 Prevents the logging of interrupts Set to 0 Excalibur Systems Chapter 5 5 2 2 Operational Status Register Bus Monitor Operation Address 0002 H READ WRITE The Operational Status register reflects pertinent status information for the board and is not reset to 0000 H on reset Instead the bit A B STD is set to 1 To make changes to the Monitor and to this register the STEX bit Control Register bit 15 must be logic 0 NOTE Bit 10 15 09 08 07 05 06 04 03 02 01 00 Operational Status Register EXC 1553P104 MCH3 User s Manual Bit Name Reserved MSEL1 MSELO A B_STD Reserved Reserved EX Reserved READY TERACT Description Set to 0 Mode Select 1 In conjunction with Mode Select 0 this bit determines the board mode of operation Mode Select 0 In conjunction with Mode Select 1 this bit determines the board mode of operation MSEL1 MSELO Mode of Operation 0 0 BC Mode 0 1 RT Mode 1 0 BM Mode 1 1 RT Concurrent BM Mode Military Standard 15
69. esired PC Interrupt line in cases when the interrupt mode is used Each jumper selects one interrupt line as shown below JP1 JP2 JP3 JP4 JP5 JP6 JP7 JP8 JP9 JP10 JP11 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRO10 IRQ11 IRO12 IRO14 IRQ15 NOTE 1 When using interrupt mode only one of the 11 jumpers JP1 JP11 should be shorted per your requirements 2 When not using interrupts all jumpers should be left open Example To select the IRQ5 PC Interrupt line short with shorting block JP4 EXC 1553P104 MCH3 User s Manual page 7 3 Chapter 7 7 3 4 7 3 5 Mechanical and Electrical Specifications Channel 0 Channel 1 and Channel 2 JP25 JP36 1553 Coupling Mode Select Jumpers The board can be either direct coupled or transformer coupled to the 1553 bus Groups of four Jumpers select the coupling mode for each channel The table below defines the jumper settings for all twelve Jumpers Coupling Mode Seiting Direct Coupled Short pins 2 and 3 of channel x jumper group Transformer Coupled Short pins 1 and 2 of channel x jumper group Jumper Settings Required to Select Coupling Mode The table below defines the jumper groups for each channel Channel Bus Jumper Group 0 A JP25 JP26 0 B JP27 JP28 1 A JP29 JP30 1 B JP31 JP32 2 A JP33 JP34 2 B JP35 JP36 Channel Jumper Groups Example To set Channel 1 to transformer coupled short with a shorting block pins 1 and 2 of JP29 JP30 J
70. f the Message Information Buffer i e MIB and the current MIB address 1 e offset from base address The SUMMIT enters the message information Word and Time Tag Word into the MIB for each message until the end of the MIB is reached When the MIB reaches the end the next message s message information Word and Time Tag Word is entered at the top of the MIB The MIB pointer is a semi static pointer The board updates the current address field at the end of message processing The Base Address field remains static NOTE In this mode of operation bits INDX NII and A B of the descriptor Control Word and the PPEN bit of the Control Register are don t care EXC 1553P104 MCH3 User s Manual page 4 35 Chapter 4 4 4 6 Remote Terminal Operation Mode 2 Circular Buffer RECEIVE MESSAGE PROCESSING The board begins all message processing by reading the descriptor block of the subaddress or mode code Command received i e Control Word TA CA and MIB The board begins storage of Data Word s starting at the location contained in the CA pointer The board automatically updates the CA pointer internally as message processing progresses The board stores the message information Word and Time Tag Word into the MIB after receiving the correct number of Data Words At the end of message processing the board updates CA and the MIB Current Address Field CAF If CAF equals the specified MIB length CA is updated to TA and the MIB CAF
71. g operation For index operation the board accesses only Data Pointer A The board updates Data pointer A after message processing is complete and the index field is not equal to zero and ping pong operation disabled Bit 15 is the most significant bit bit 00 is the least significant bit Data Pointer A and B For ping pong buffer operation the host uses either Data Pointer A or Data Pointer B The board determines which pointer to access via the state of Control Word bit 02 The board retrieves or stores Data Words from the address contained in the Data pointer automatically incrementing the Data Pointer as Data Words are received The Data pointer is never updated as part of Command post processing in the ping pong mode of operation See Figures 4 4 and 4 5 EXC 1553P104 MCH3 User s Manual page 4 21 Chapter 4 Receive Subaddress 1 Descriptor Block Command 1 Receive three Words Command 2 Receive two Words Command 3 Receive three Words Figure 4 3 RT Non Broadcast Receive Message Indexing Note X don t care page 4 22 CONTROL WORD DATA POINTER A DATA POINTER B BROADCAST DATA POINTER Message Info Word Time Tag Data Word 1 Data Word 2 Data Word 3 Message Info Word Time Tag Data Word 1 Data Word 2 Message Info Word Time Tag Data Word 1 Data Word 2 Data Word 3 Remote Terminal Operation Index field contents 03XX H Data Pointer A 0100 H Data Pointer B XXXX H
72. gister Introduction Address BASE 2 H WRITE The Bank Select register sets the desired bank number Writing a 0 to this address selects Bank 0 which contains the lower 32K of Channel 0 Writing a 1 to this address selects Bank 1 which contains the upper 32K of Channel 0 etc This register is set to 0 at power up Bit Value 03 07 X Don t care 00 02 OH 1H 2H 3H 4H 5H 6 7 H Bank Select Register EXC 1553P104 MCH3 User s Manual Description Bank 0 Channel 0 Lower 32K Bank 1 Channel 0 Upper 32K Bank 2 Channel 1 Lower 32K Bank 3 Channel 1 Upper 32K Bank 4 Channel 2 Lower 32K Bank 5 Channel 2 Upper 32K Reserved set to 0 page 1 7 Chapter 1 1 4 5 Introduction Interrupt Status Reset Register Address BASE 3 H READ WRITE The Interrupt Status Reset register is used to poll and reset the board interrupt request Writing a value of 1 to the appropriate bit will reset the corresponding channel interrupt request Writing a value of 0 has no effect Bit Bit Name Description 03 07 Reserved set to 0 02 IR2 1 Channel 2 Interrupt Reset 01 IR1 1 Channel 1 Interrupt Reset 00 IRO 1 Channel 0 Interrupt Reset Interrupt Status Reset Register Write Definition Reading this register indicates which channels are generating interrupts More than one bit at a time may be set generating interrupts from more than one channel at a time Bit Bit Name Description 0
73. gister Address 001E H READ WRITE The Monitor Filter Lo register determines which RTs RT 15 through RT 0 the board will monitor Bit Bit Name Description 00 15 MFL 15 0 Monitor Filter These bits determine which RT to monitor Monitor Filter Lo Register EXC 1553P104 MCH3 User s Manual page 5 9 Chapter 5 5 3 5 3 1 Bus Monitor Operation Bus Monitor Architecture To meet the MIL STD 1553 monitor requirements the board uses a Monitor Block architecture that takes advantage of both Control Registers and RAM The Monitor Block that is located in contiguous memory requires eight 16 bit locations for each message These eight locations include e A Message Information Word Two Command Word locations A Data Pointer e Two Status Word locations e A Time Tag location e A reserved location The user must initialize the starting locations of the Monitor Block the Data Pointer the Block Counter and the Interrupt Log Pointer From then on the board will build a Monitor Block for each message it receives over the 1553 bus Figure 5 2 shows a diagram of the Monitor Block followed by a description of each location associated with the Monitor Block Message Info Word Command Word 1 Command Word 2 Data Pointer Status Word 1 Status Word 2 Time Tag Reserved Figure 5 2 Bus Monitor Block Diagram Message Information Word The first memory location of each Monitor Block contains the message infor
74. h address location If no conditions are met the opcode appears as an execute and branch page 3 11 Chapter 3 Opcode 1001 1010 1011 1100 1101 1110 1111 Field Name Retry on Condition Branch if all Retries Fail Interrupt Continue Call Return to Call Reserved Load Minor Frame Timer Return to Branch Opcode Definition NOTE page 3 12 Bus Controller Operation Definition This opcode instructs the board to perform automatic retries as specified in the control word if particular conditions occur If the conditions are met and all the retries fail the board branches to the location as specified in the branch address location If no conditions are met the opcode appears as an execute and continue This opcode instructs the board to interrupt and continue processing on the next command block When using this opcode no 1553 processing occurs This opcode instructs the board to go to the command block as specified in the branch address location without processing this block The next command block address is saved in an internal register so that the board may remember one address and return to the next command block No command processing takes place i e no 1553 This opcode instructs the board to return to the command block address saved during the Call opcode No command processing takes place i e no 1553 The board will generate an illegal opcode interrupt if i
75. igure 3 6 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 7 1 Figure 7 2 Figure 9 1 Figure 9 2 EXC 1553P104 MCH3 Block Diagram esse esse ee esse ees ee ee ee 1 2 Direct Coupled Connection One Bus Shown 1 5 Transformer Coupled Connection One Bus Shown 1 5 General VO Map esse ee ee Re AR Re RA ek ee ee 1 6 General Memory Map sees ee Re AA Re ke ee ee 1 9 Channel Memory Map sesse ee ek AR ke ee ee ee ee 2 1 Control Registers Map BC Mode i eek se Re Re 3 2 BC Command Block Architecture iese ese eke ee Re RA 3 9 Control Word Definition seek ke Re RA Ak ee 3 10 Message Control Options ee ee RR Re RA ee 3 15 Minor Frame Seguencing iis ees see ee RA ke ee ee 3 15 Memory Architecture for BC Mode sesse ee ee ee ke 3 16 Control Registers Map RT Mode eek ee ee Re Re 4 2 Descriptor Tabie EE Ee a hla eins 4 16 RT Non Broadcast Receive Message Indexing eee 4 22 EXC 1553P104 MCHS Descriptor Block Receive 06 4 23 EXC 1553P104 MCHS3 Descriptor Block Transmit 4 23 RT Mode 1 Descriptor Block and Circular Buffer 4 34 RT Mode 2 Descriptor Block and Circular Buffers 4 37 Control Registers Map BM Mode iese ee ee Re ee 5 3 Bus Monitor Block Diagram iese Re Re Re 5 10 Message Informa
76. ill access memory read or write address locations past BA Delimit all circular buffer boundaries with at least 34 address locations NOTE In this mode of operation bits INDX NII and A B of the descriptor Control Word and the PPEN bit of the Control Register are don t care Mode 1 Circular Buffer RECEIVE MESSAGE PROCESSING The board begins all message processing by reading a unique descriptor block after reception and validation of a subaddress or mode code Command Word The board internally increments the CA pointer to store the receive Data Word s After message processing completes the board stores the Message Information Word and Time Tag Word into the circular buffer preceding the message data At the end of message processing the board updates CA Gif no errors detected For CA larger than BA storage of next message begins at the address location pointed to by the TA pointer and CA is made equal to TA If CA is less than BA CA points to the next available memory location in the buffer e CA 1 For transmit Commands the board begins transmission of data from memory location CA 2 Reserve the first two locations for the message information Word and Time Tag Word After message processing completes the board enters the message information Word and Time Tag Word into the circular buffer At the end of message processing the board updates CA if no errors detected For CA larger than BA storage of the next message b
77. ime Intermessage gap page 9 2 Excalibur Systems Chapter 9 Appendices EXC 1553P104 MCH3 User s Manual page 9 3 Chapter 9 Appendices The information contained in this document is believed to be accurate However no responsibility is assumed by Excalibur Systems Inc for its use and no license or rights are granted by implication or otherwise in connection therewith Specifications are subject to change without notice November 2001 Rev A 1 page 9 4 Excalibur Systems
78. ing initialization you designate the first buffer used by setting this bit 1 Buffer A 0 Buffer B This bit is a don t care if buffer ping ponging is not enabled Broadcast Received 1 Reception of a broadcast Command Set to 0 Mode Code Transmit Control Word page 4 20 Excalibur Systems Chapter 4 4 2 5 Remote Terminal Operation Data Pointer A and B Mode 0 Data List Pointer A and B contains address information for the retrieval and storage of message Data Words In the index mode of operation the board reads Data Pointer A to determine the location of data for retrieval or storage The board uses the Data Pointer to initialize an internal counter which increments after each Data Word For a receive Command the board stores the incoming Data Word sequentially into memory As part of Command post processing the board writes a new Data pointer into the descriptor block The board continues to update the Data pointer until the Control Word index field decrements to zero An example is shown in Figure 4 3 RT Non Broadcast Receive Message Indexing page 4 22 NOTE The index feature is not applicable for transmit Commands i e T R bit 1 Bit Bit Name Description 00 15 DP 15 0 Data Pointer Bits The second and third Words of the descriptor block contain the data buffer location The board accesses either Data Pointer A or Data Pointer B depending on the state of Control Word Bit 02 during ping pon
79. ins constant The monitor block pointer increments Message information bits of the monitor block are changed to reflect the error An interrupt is given indicating a message has occurred See Message Information Bits page 5 11 page 5 2 Excalibur Systems Chapter 5 5 2 Control Registers BM Mode Bus Monitor Operation The control registers are read write unless otherwise stated All control registers must be accessed in word mode All Control Register bits are active high and are reset to 0 unless otherwise stated Figure 5 1 below illustrates the control registers for Bus Monitor mode Reserved Monitor Filter Register Lo Monitor Filter Register Hi Monitor Block Counter Register Initial Monitor Data Pointer Register Initial Monitor Command Block Pointer Register Reserved Time Tag Register BIT Word Register Interrupt Log List Pointer Register Pending Interrupt Register Interrupt Mask Register Current Command Block Register Operational Status Register Control Register Figure 5 1 Control Registers Map BM Mode 0020 003E H 001E H 001C H 001A H 0018 H 0016 H 0010 0014 H 000E H 000C H 000A H 0008 H 0006 H 0004 H 0002 H 0000 H NOTE The information in this section describes the operation of a single channel of the EXC 1553P104 MCH3 in RT mode Operating and addressing the second and third channels is identical to that of the first channel with the appropriate Base Address EXC 1553P1
80. mation word Each information word contains the opcode retry number bus definition RT to RT messages and the message information 15 12 11 10 07 00 100 09 08 0100 00 BUSAB RT RT Message Information Figure 5 3 Message Information Word page 5 10 Excalibur Systems Chapter 5 Bit Number 12 15 10 11 09 08 00 07 Bus Monitor Operation Description Default With the Monitor Block architecture resembling the BC Command Block architecture these bits default to a 0100 state which is the Execute and Continue opcode in case the monitor must switch to the BC mode of operation Default With the Monitor Block architecture resembling the BC these bits default to a 00 state If the monitor must switch to the BC the retries will be set at four per message Bus A B This bit defines on which of the two buses the command was received Logic 1 Bus A Logic 0 Bus B RT to RT Transfer This bit defines whether or not the message associated with this Monitor Block was an RT to RT transfer and whether the board saved the second command word This bit will be set only if the board is instructed to monitor the Receive RT Message Information Bits These bits define the conditions of the message received by the board for that particular Monitor Block Each of the message information bits is defined in the following section Message Information Word MESSAGE INFORMATION BITS Message information bits are
81. n Figure 3 5 shows a configuration of four minor frames in which Message A is sent in every frame Message B is sent in every other frame and Message C is sent once Each minor frame goes out at 10msec 100Hz If each minor frame is 10msec long Message A is sent every 10msec Message B is sent every 20msec and Message C is sent every 40msec gt gt BE n MINOR MINOR MINOR MINOR FRAME FRAME FRAME FRAME 1 2 3 4 A A A A B B C 10 msec 10 msec 10 msec 10 msec _ lt lt lt lt Figure 3 5 Minor Frame Sequencing EXC 1553P104 MCH3 User s Manual page 3 15 Chapter 3 3 5 Bus Controller Operation Memory Architecture After reviewing the control registers it is advantageous to look at how to set up memory to configure the EXC 1553P104 MCH3 as a Bus Controller This section shows one method for defining the memory configuration The configuration shows the Command Blocks data locations and the Interrupt Log List as separate entities Figure 3 6 shows that the first block of memory is allocated for the Command Blocks Notice that the Command Block Pointer Register initially points to the control word of the first Command Block After completing execution of that first Command Block the Command Block Pointer Register will automatically be updated to show the address of the next Command Block Following the Command Block locations is the memory req
82. n software to asynchronously freeze i e disable ping pong operation the remote terminal to a single buffer The handshake mechanism functions as follows Prior to starting remote terminal operation enable the buffer ping pong feature by writing a logical 1 to bit 02 of the Control Register During ping pong operation the remote terminal ping pongs between the two data buffers for each subaddress or mode code on a message by message basis Each unique MIL STD 1553 subaddress and mode code is assigned two data buffer locations A and B The remote terminal retrieves data from a buffer or stores data into a buffer depending on the message type 1 e transmit or receive Command During ping pong operation the remote terminal determines the active subaddress or mode code buffer at the beginning of message processing the remote terminal complements bit 02 of the Descriptor Control Word to access the alternate buffer on the following message i e ping pong To off load or load the subaddress and mode code buffers without collisions e g remote terminal writing and application software reading the same buffer the application software must disable ping pong operation 1 e freeze the remote terminal access to a single buffer either A or B Disabling ping pong operation allows the application software to off load or load the alternate buffer while the remote terminal continues to use the active buffer To implement this architecture pi
83. ng pong operation must enable and disable asynchronously via software with feedback to indicate that buffer ping ponging is truly disabled Second unique subaddress and mode code flags indicate which buffer is active Each unique subaddress and mode code is assigned a flag that indicates the active buffer To begin the process of off loading or loading the remote terminal s subaddress and or mode code buffers when using the ping pong feature the application software performs the following sequences disables ping pong operation determines the active buffer service the alternate buffer enables ping pong operation page 4 24 Excalibur Systems Chapter 4 4 2 7 Remote Terminal Operation The application software disables ping pong operation by writing a logical 0 to Control Register bit 02 The disable of ping pong operation is acknowledged by bit 09 of the Control Register Bit 09 of the Control Register acknowledges the ping pong disable by transitioning from a logical 1 to a logical 0 The application software interrogates bit 02 of each Descriptor Control Word to determine the active buffer on a subaddress or mode code basis If bit 02 is a logical 0 the remote terminal uses Buffer A and the application software off loads or loads Buffer A The application software enables ping pong operation by writing a logical 1 to Control Register bit 02 The enable of ping pong operation is acknowledged by bit 09 of the Control Register Bi
84. nsmitted Command Word stored Data Word stored Time Tag counter loaded with Data Word value Status Word transmitted Command Word stored Data Word stored Status Word transmitted Command Word stored Data Word stored Status Word transmitted Command Word stored Data Word stored Status Word transmitted Command Word stored Data Word stored Status Word transmitted Command Word stored Data Word stored Status Word transmitted Command Word stored 2 Dynamic Bus Acceptance bit set in outgoing Status Word if enabled in the Control Register Status Word transmitted Command Word stored Time Tag counter reset to 0000 H Status Word transmitted Mode Code Description continues on next page Excalibur Systems Chapter 4 T R Mode Code 1 00010 1 00011 1 00100 1 00101 1 00110 1 001111 1 01000 1 01001 01111 1 10000 1 10001 Table 4 4 EXC 1553P104 MCH3 User s Manual Function Transmit Status Word Initiate Self Test Transmitter Shutdown Override Transmitter Shutdown Inhibit Terminal Flag Bit Override Inhibit Terminal Flag Reset Remote Terminal Reserved Transmit Vector Word Reserved Remote Terminal Operation Operation 1 Command Word stored 2 Last Status Word transmitted 3 Status Word cleared after reset Note The board updates Status Word if illegalized Command Word stored Status Word transmitted BIT initiated
85. nsmitting on 1553 bus 5V 250mA 25 duty cycle transmitting on 1553 bus 5V 410mA 50 duty cycle transmitting on 1553 bus 5V 650mA 87 5 duty cycle transmitting on 1553 bus Example The maximum power requirements for a 3 channel board 25 duty cycle per channel will be 5V 200mA 3 x 250mA 950mA page 7 8 Excalibur Systems Chapter 8 Ordering Information 8 Ordering Information Chapter 8 explains how to indicate the options you want when ordering an EXC 1553P104 MCH3 board Add E to the name of the board to indicate the extended temperature ruggedization option PART NUMBER DESCRIPTION EXC 1553P104 MCH3 Three Channel MIL STD 1553 interface board for PC 104 Systems Supports BC RT BM or RT Concurrent BM EXC 1553P104 MCH3 E As above with extended temperature operation and ruggedized 40 to 85 C EXC 1553P104 MCH3 User s Manual page 8 1 Chapter 8 Ordering Information page 8 2 Excalibur Systems Chapter 9 Appendices 9 Appendices Chapter 9 contains appendices describing the Military Standard 1553B word and message formats The following topics are included MIL STD 1553B Word Formats page 9 1 MIL STD 1553B Message Formats page 9 2 Appendix A MIL STD 1553B Word Formats Register Bits 1553 Bit Times Command Word 5 1 5 5 1 Sync RT Address TE SubAddress Mode Word Count Mode P Code Data Word 16 A Sync lt Data P Status Word 5
86. nterrupt enabled and automatically stop execution if a reserved opcode is used This opcode instructs the board to load the minor frame timer MFT with the value stored in the eighth location of the current command block The timer will be loaded after the previous MFT has decremented to zero After the MFT timer is loaded with the new value the board will proceed to the next command block No command processing takes place i e no 1553 This opcode instructs the board to return to the command block address saved during a Branch opcode No command processing takes place i e no 1553 For retries with interrupts enabled all interrupts are logged after message processing is complete Excalibur Systems Chapter 3 3 3 2 Bus Controller Operation 3 3 1 2 BC CONDITION CODES Condition codes have been provided as a means for the EXC 1553P104 MCHS to perform certain functions based on the RT s Status Word In an RT to RT transfer the conditions apply to both of the Status Words Each bit of the condition codes is defined below Bit Number Description 07 Message Error This condition will be met if the board detects an error in the RT s response or if it detects no response The board will wait 15usec in 1553B mode and 9usec in 1553A mode before declaring an RT no response see MIL STD 1553A Operation BC Mode page 3 17 06 Status Word Response with the Message Error bit set Bit time 09 in 1553A mode This
87. on read Message Error 1 A message error condition was observed during processing See bits 00 to 04 for details Ignore on read Illegal Command Received 1 The Command received was an illegal Command Ignore on read Overrun Error 1 The board received a Data Word with a Transmit Command Ignore on read Mode Code Transmit Information Word EXC 1553P104 MCH3 User s Manual page 4 31 Chapter 4 4 4 4 4 1 4 4 2 Remote Terminal Operation RT Circular Buffer Modes The RT circular buffer modes simplify the software service of remote terminals implementing bulk or periodic data transfers You can select the preferred mode at start up by writing to Control Register bits 07 and 08 see Control Register page 4 3 The two modes Mode 1 and Mode 2 are discussed in sections 4 4 1 and 4 4 2 Mode 1 Operation In this mode the board merges transmit or receive data into a circular buffer along with message information For each valid receive message the board enters a message information Word Time Tag Word and Data Word s into a unique receive circular buffer For each valid transmit message the board enters a message information Word and Time Tag Word into reserved memory locations within the transmit circular buffer The board automatically controls the wrap around of circular buffers Mode 1 Descriptor Block Each subaddress and mode code both transmit and receive has a unique circular buff
88. ontrol Word page 4 18 Excalibur Systems Chapter 4 Remote Terminal Operation 4 2 3 Mode Code Receive Control Word Information contained in the Mode Code Receive Control Word assists the EXC 1553P104 MCH3 in message processing The following bits describe the receive mode code descriptor Control Word The descriptor control Word is initialized by the host and updated by the board during Command post processing In MIL STD 1553A all mode codes are without data and the T R bit is ignored NOTE Bit 08 15 07 06 05 04 03 02 01 00 Bit Name INDX INTX IWA IBRD BAC Reserved A B BRD Nil Description Index Field These bits define multiple message buffer length The host uses this field to instruct the board to buffer N messages N can range from 0 00 H to 256 FF H If buffer ping ponging is enabled the INDX field is don t care i e does not contain applicable information The board does not perform message buffering in the ping pong mode of operation The index decrements each time a complete message is transacted no message errors The index does not decrement if the mode code is illegalized The board can generate an interrupt when the index field transitions from one to zero see bit 07 Interrupt Index Equals 0 1 Enables the generation of an interrupt when the index field transitions from 1 to 0 The interrupt is entered into the Pending Interrupt Register if no
89. ormation is stored in the same buffer as non broadcast information EXC 1553P104 MCH3 User s Manual page 4 17 Chapter 4 Remote Terminal Operation 4 2 2 Transmit Control Word Information contained in the Transmit Control Word assists the EXC 1553P104 MCHB8 in message processing The following bits describe the transmit subaddress descriptor Control Word The descriptor control Word is initialized by the host and updated by the board during Command post processing Bit Bit Name Description 07 15 Reserved Set to 0 06 IWA Interrupt When Accessed 1 Enables the generation of an interrupt when the subaddress receives a valid Command The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing 05 Reserved Set to 0 04 BAC Block Accessed The host initializes this bit to zero the board overwrites the zero with a logic one upon completion of message processing Upon reading a one the host resets this bit to zero in preparation for the next message 03 Reserved Set to 0 02 A B Buffer A B Indicates the Data pointer to access when buffer ping pong is enabled During initialization the host designates the first buffer used by setting this bit 1 Buffer A 0 Buffer B This bit is a don t care if buffer ping ponging is not enabled 01 BRD Broadcast Received 1 Reception of a Broadcast Command 00 Reserved Set to 0 Transmit C
90. ows the host to mask or temporarily disable the service of interrupts While masked interrupt activity does not occur The unmasking of an interrupt after the event occurs does not generate an interrupt for that event An interrupt is masked if the corresponding bit of this register is set to logic 0 Bit Bit Name Description 12 15 Reserved Setto0 11 MERR Message Error Interrupt 01 10 Reserved Setto0 00 MBC Monitor Block Counter Interrupt Interrupt Mask Register Pending Interrupt Register Address 0008 H READ ONLY The Pending Interrupt register is used to identify which of the interrupts occurred during operation All register bits are cleared on a host read Bit Bit Name Description 12 15 Reserved Ignore on read 11 MERR Message Error Interrupt 1 A message error occurred The Monitor can detect Manchester sync field word count 1553 word parity bit count and protocol errors This bit will be set and an interrupt generated after message processing is complete 01 10 Reserved Ignore on read 00 MBC Monitor Block Counter Interrupt This bit is set if the board s monitor block counter reaches zero transition from 1 to 0 Note The Monitor does not discriminate between error free messages and those messages with errors Pending Interrupt Register page 5 6 Excalibur Systems Chapter 5 5 2 6 5 2 7 Bus Monitor Operation Interrupt Log List Pointer Register Address 000A H READ WRITE The Interrupt Log
91. provided as a means to supply more data on the message In an RT to RT transfer the information applies to both of the status words Each message information bit is defined below Bit Number 07 06 05 04 03 02 01 00 Description Message Error This bit will be set if the monitor detects an error in either the Command Word Data Words or the RT s status Mode Code without Data This bit will be set if the monitor detects that the command being processed is a mode code without data words Broadcast This bit will be set if the monitor detects that the command being processed is a broadcast message Reserved Time Out Error This bit will be set if the RT did not receive the proper number of Data Words e g the number of Data Words received was less than the word count specified in the Command Word Overrun Error This bit will be set if the RT received a word when none were expected or the number of Data Words received was greater than expected Parity Error This bit will be set if a parity error has occurred on one of the message words Manchester Error This bit will be set if a Manchester error has occurred on one of the Data Words Message Information Bits EXC 1553P104 MCH3 User s Manual page 5 11 Chapter 5 5 3 2 5 3 3 5 3 4 5 3 5 5 3 6 Bus Monitor Operation Command Words The next two locations in the board Monitor Block are for Command Words In non RT to RT 1553 messages
92. re As defined in MIL STD 1553 the Bus Controller initiates all communications on the bus To comply with MIL STD 1553 bus controller requirements the EXC 1553P104 MCH3 uses a Command Block architecture that takes advantage of both control registers and RAM Each Command Word transmitted over the bus must be associated with a Command Block The Command Block requires eight contiguous 16 bit memory locations for each message These eight locations include a Control Word 1st location Command Word1 2nd location Command Word2 Data Pointer Status Word 1 Status Word 2 Branch Address Timer Value 8th location Figure 3 2 BC Command Block Architecture The host must initialize each of the locations associated with each Command Block The exception is for the two status locations that will be updated as Command Words are transmitted and corresponding Status Words are received Command Blocks may be linked together in such a manner as to allow the generation of Major and Minor message frames In addition the BC can detect the assertion of Status Word bits and generate interrupts or branch to a new message frame depending of course on the specific conditions that arise EXC 1553P104 MCH3 User s Manual page 3 9 Chapter 3 3 3 1 Control Word Bus Controller Operation The first memory location of each BC Mode Command Block contains the Control word Each control word contains the opcode retry number bus definition RT to
93. re page 4 41 Terminal Address page 4 42 Reset page 4 42 MIL STD 1553A Operation RT Mode page 4 43 NOTE The EXC 1553P104 MCHB can be configured as both a remote terminal and monitor For more information about this feature see RT Concurrent Monitor Operation page 5 15 EXC 1553P104 MCH3 User s Manual page 4 1 Chapter 4 4 1 Remote Terminal Operation Control Registers RT Mode The Control registers are read write unless otherwise stated All Control registers must be accessed in Word mode All Control register bits are active high and are reset to 0 unless otherwise stated Figure 4 1 below illustrates the Control registers for Remote Terminal mode Illegalization Registers 16 registers Reserved 1553 Status Word Bits Register RT Descriptor Pointer Register Time Tag Register BIT Word Register Interrupt Log List Pointer Register Pending Interrupt Register Interrupt Mask Register Current Command Block Register Operational Status Register Control Register 0020 003E H 0014 001E H 0012 H 0010 H OOOE H 000C H 000A H 0008 H 0006 H 0004 H 0002 H 0000 H Figure 4 1 Control Registers Map RT Mode NOTE The information in this section describes the operation of a single channel of the EXC 1553P104 MCH3 in RT mode Operating and addressing the second and third channels is identical to that of the first channel with the appropriate Base Address page 4 2 Excalibur Systems Chapter 4 4 1 1
94. rious protocols Specifically two of the protocols that the board may be used with are MIL STD 1553A and MIL STD 1553B To meet these protocols you can configure the board through the Control register XMTSW Bit 00 and the Operational Status register A B STD Bit 07 Table 4 5 defines the three ways to program the EXC 1553P104 MCHS A B STD XMTSW RESULT protocol selected 0 X 1553B response 1553B Standard 1 0 1553A response 1553A Standard 1 1 1553A response auto execute the TRANSMIT LAST STATUS WORD mode code Table 4 5 MIL STD 1553A B Operation RT Mode When configured as a remote terminal to meet MIL STD 1553A the EXC 1553P104 MCHS will operate as follows e Responds with a Status Word within 7usec Ignores the T R bit for all mode codes e All mode codes are defined without data e All mode codes use mode code transmit control and information Words e Mode code 00000 is defined as dynamic bus control DBC e Subaddress 00000 defines a mode code ME and TF bits are defined in the 1553 Status Word all other Status Word bits are programmable i e NO BUSY mode etc e Broadcast of all mode codes except Mode Code 00000 DBC and mode code 00010 transmit Status Word if enabled is allowed e To illegalize a Mode Code the user needs to illegalize both the receive and transmit versions e Illegalization of row 1F H is not automatic EXC 1553P104 MCH3 User s Manual page 4 43 Chapter 5 5 1 Bus Moni
95. rom the receive Command Word bits 15 to 19 Ignore on read Bus A B 1 The message was received on Bus A 0 The message was received on Bus B Remote Terminal to Remote Terminal Transfer The Command processed was an RT to RT transfer Message Error 1 A message error condition was observed during processing See bits 00 to 04 for details Ignore on read Illegal Command Received 1 The Command received was an illegal Command Time Out Error 1 The board did not receive the proper number of Data Words i e the number of Data Words received was less than the Word count specified in the Command Word Overrun Error 1 The board received a Word when none was expected or the number of Data Words received was greater then expected Parity Error 1 The board observed a parity error in the incoming Data Words Manchester Error 1 The board observed a Manchester error in the incoming Data Words Receive Information Word EXC 1553P104 MCH3 User s Manual page 4 27 Chapter 4 4 3 2 Remote Terminal Operation Subaddress Transmit Data The user is responsible for organizing the data packet i e N Data Words into memory and establishing the applicable Data Pointer The user can allocate two 16 bit memory locations at the top of the data packet for the storage of the Transmit Information Word and the Time Tag Word An example transmit Data structure for three Words is shown below Dat
96. rvice Request and Subsystem Flag by writing to bits 09 through 00 of this register The board s Status Word response reflects assertion of these bit s until negated by the host unless the Immediate Clear Function is enabled The Immediate Clear Function automatically clears these bits after being transmitted in a Status Word The Immediate Clear Function does not affect the operation of the Transmit Last Status Word and Transmit Last Command Word Mode Codes Transaction of a legal valid Command with the INS bit set toa logic one and the Immediate Clear Function enabled results in the transmission of a 1553 Status Word with bit 10 asserted If the ensuing Command is a Transmit Last Status Word or Last Command mode code bit 10 of the outgoing 1553 Status Word remains a logic 1 For MIL STD 1553B applications the 1553 Status Word Bits register is as follows Bit Bit Name Description 15 IMCLR Immediate Clear Function 1 Enables the Immediate Clear Function IMF of the board Enabling the IMF results in the clearing of the INS BUSY TF SRQ and or SUBF bit immediately after a message is completed To enable this function set this bit to 1 when setting bit s INS BUSY TF SRQ and or SSYSF to 1 This bit should be used consistently since once set it will remain set and once cleared it will remain cleared 10 14 Reserved Setto 0 09 INS Instrumentation Bit This bit sets the Instrumentation bit of the MIL STD 1553B Status Word
97. s page 1 2 Excalibur Systems Chapter 1 1 2 1 2 1 1 2 2 Introduction Installation To install the EXC 1553P104 MCH8 add the appropriate software for your operating system and then configure and install the hardware Software Installation The EXC 1553P104 MCH3 is delivered with software compatible with several operating systems For information about installing the accompanying software drivers see ReadMe txt on the Galahad Software Tools diskettes that came with your board Board Installation Before installing the board it 1s very important to e Select one of the board s four consecutive I O address e Determine which half segment of memory is available on your PC to set the Base Address of the board e Select the desired PC interrupt line For information and instructions about these setting see Chapter 7 Mechanical and Electrical Specifications Jumpers page 7 2 and the ReadMe txt on the Galahad Software Tools diskettes that came with your board WARNING You should wear a suitably grounded electrostatic discharge wrist strap whenever handling the Excalibur board To install the EXC 1553P104 MCH3 follow the instructions in the order given below 1 Set Jumpers JP12 JP19 according to the I O port selected see VO Address Decoding Jumpers page 7 2 2 Set Jumpers JP20 P24 according to the memory segment selected see Board Logical Address Jumpers page 7 3 3 Set Jumpers JP1 JP11 according
98. s control registers see Figure 2 1 A powerful RISC processing unit UTMC SUMMIT XT 1553 protocol controller provides automatic message handling message status general operational status and interrupt information The user has direct access to all control registers and data blocks in Real Time To control the board operation access the RAM and control registers The EXC 1553P104 MCH3 may be configured to support MIL STD 1553A as well as MIL STD 1558B protocol CHANNEL MEMORY BLOCK 0040 FFFE H 1553 Message Storage Control Data Storage CHANNEL REGISTERS BLOCK 0000 003E H 32 Control Registers Figure 2 1 Channel Memory Map Chapters 3 4 and 5 of the User s Manual explain the operation of a single channel of the EXC 1553P104 MCHB in each of the three modes Bus Controller Remote Terminal and Bus Monitor NOTE Operating and addressing the second and third channels are identical to that of the first channel with the appropriate Base Address EXC 1553P104 MCH3 User s Manual page 2 1 Chapter 2 General Channel Operation page 2 2 Excalibur Systems Chapter 3 3 1 Bus Controller Operation Bus Controller Operation Chapter 3 describes EXC 1553P104 MCH3 operation in Bus Controller BC mode The following topics are covered Bus Controller Message Processing page 3 1 Control Registers BC Mode page 3 2 BC Architecture page 3 9 Command Block Chaining page 3 15 Memory Architecture page 3 16 MIL STD 155
99. ssage Error Interrupt 1 A message error occurred The board can detect Manchester sync field Word count errors too many or too few MIL STD 1553 Word parity bit count errors too many or too few and protocol errors If not masked this bit is always set and an interrupt generated when the board asserts bit time 9 Message Error of the 1553 status Word e g illegal Commands invalid Data Word etc Subaddress Accessed Interrupt 1 A pre selected subaddress has transacted a message To determine the exact subaddress the host interrogates the interrupt log IAW Broadcast Command Received Interrupt 1 The board s receipt of a valid broadcast Command The board suppresses status Word transmission Index Equal Zero Interrupt The board sets this bit to 1 to indicate the completion of a pre defined number of Commands by the RT Upon assertion of this interrupt the host updates the subaddress descriptor to prevent the potential loss of data Illegal Command Interrupt 1 The board received an illegal Command Upon receipt of this Command the board responds with a status Word only Bit time 09 Message Error of the 1553 status Word is set to a logic 1 Ignore on read page 4 7 Chapter 4 Remote Terminal Operation Interrupt Log List Pointer Register Address 000A H READ WRITE The Interrupt Log List Pointer indicates the starting address of the Interrupt Log List The Interrupt Log List is a 32 word
100. t 09 of the Control Register acknowledges the ping pong enable by transitioning from a logical 0 to a logical 1 Broadcast Data Pointer Mode 0 The Broadcast Data Pointer contains the address for the Message Information Word Time Tag Word and Data Words associated with a broadcast Command The following bits describe the receive subaddress mode code descriptor Broadcast Data Pointer If ping pong operation is disabled the board automatically increments this Data Pointer during Command post processing Bit Bit Name Description 00 15 BP 15 0 Broadcast Data Pointer The fourth Word of the descriptor block contains the broadcast data buffer location This pointer can reside anywhere in memory space The board accesses this pointer when Control Word bit 00 is a logic 1 and broadcast is enabled Bit 15 is the most significant bit bit 00 is the least significant bit Notes 1 If ping pong is enabled this pointer does not update 2 When the broadcast Command is followed by a Transmit Last Command or Last Status Word mode code the board transmits a Status Word with bit 15 of the Status Word set to a logic 1 The broadcast bit is cleared when the next valid non Broadcast Command is received Broadcast Data Pointer EXC 1553P104 MCH3 User s Manual page 4 25 Chapter 4 4 3 4 3 1 Remote Terminal Operation Data Structures The following sections discuss the Data structures that result from Command processing For each
101. t Coupled Connection One Bus Shown If operating in the more standard Transformer coupling mode use stub coupler devices which are available from Excalibur Systems Inc Two terminators are required for each coupler which services a single bus e g Bus A See Figure 1 3 For more information about our couplers check our website www mil 1553 com To other 1553 device EXC 1553P104 MCH Transformer Coupled 1553 Device Transformer Coupled s A s B s C Terminator Terminator 78 Ohm Three Stub Coupler 78 Ohm Figure 1 3 Transformer Coupled Connection One Bus Shown EXC 1553P104 MCH3 User s Manual page 1 5 Chapter 1 1 4 1 4 3 Introduction General VO Map The board uses four I O addresses starting at the Base I O Address which is set with the appropriate Jumpers JP12 JP19 as follows BASE ADDRESS 3 H BASE ADDRESS 0 H Figure 1 4 General VO Map Software Reset Register Address BASE 0 H WRITE The Software Reset register resets the channel Writing a 1 to the appropriate bit will reset the corresponding channel Writing a value of 0 has no effect This register is set to 0 at power up Bit Description 03 07 Reserved set to 0 02 1 Channel 2 Software Reset 01 1 Channel 1 Software Reset 00 1 Channel 0 Software Reset Software Reset Register page 1 6 Excalibur Systems Chapter 1 1 4 4 Bank Select Re
102. t masked in the Mask Register An interrupt is generated after message processing Interrupt When Accessed 1 Enables the generation of an interrupt when mode code Command is received The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing Interrupt Broadcast Received 1 Enables the generation of an interrupt when a valid broadcast mode code Command is received The interrupt is entered into the Pending Interrupt Register if not masked in the Mask Register An interrupt is generated after message processing Block Accessed The host initializes this bit to zero the board overwrites the zero with a logic 1 upon completion of message processing Upon reading a one the host resets this bit to zero in preparation for the next message Set to 0 Buffer A B Indicates the last buffer accessed when buffer ping pong is enabled During initialization you designate the first buffer used by setting this bit 1 Buffer A 0 Buffer B This bit is a don t care if buffer ping ponging is not enabled Broadcast Received 1 Reception of a valid broadcast Command Notice Il 1 Enables the use of the Broadcast Data Pointer as a buffer for broadcast Command information 0 Broadcast information is stored in the same buffer as non broadcast information Mode Code Receive Control Word EXC 1553P104 MCH3 User s Manual page 4 19
103. tain opcodes are used Timer Value The last location in the BC Mode Command Block is the Timer Value This timer is used for one of two purposes e To set up minor frame schedules when using the Load Minor Frame Timer opcode 1110 The MFT counter is clocked by a 15 625 KHz 64usec internal clock The MFT counter runs continuously during message processing and must decrement to zero prior to loading the next Minor Frame time value e Asa message to message timer MMT when using the Skip opcode 0001 The MMT timer is clocked at the 24 MHz 41 666nsec rate and allows for scheduling of specific time between message execution page 3 14 Excalibur Systems Chapter 3 3 4 Bus Controller Operation Command Block Chaining To determine the first Command Block set the initial start address in the Command Block Pointer Register Address 0010 H The Command Blocks will execute in a contiguous fashion as long as no go to branch call or return opcodes are used With the use of these opcodes almost any memory configuration is possible Figures 3 4 and 3 5 show how several Command Blocks may be linked together to form a command frame and how branch opcodes may be used to link minor frames The minimum BC intermessage gap is 28 0usec FRAME N RETRIES CONDITIONAL FAIL BRANCH ERROR SERVICE FRAME FRAME RETURN RETURN Figure 3 4 Message Control Options The example i
104. ter indicates the starting address of the Interrupt Log List The Interrupt Log List is a 32 word ring buffer that contains information pertinent to the service of interrupts The EXC 1553P104 MCHB8 architecture requires the location of the Interrupt Log List on a 32 word boundary The most significant 11 bits of this register designate the location of the Interrupt Log List within a 64K word memory space Initialize the lower 5 bits of this register to a logic 0 by the host The board controls the lower 5 bits to implement the ring buffer architecture Read this register to determine the location and number of interrupts within the Interrupt Log List least significant 5 bits Bit Bit Name Description 00 15 ILLP 15 0 Interrupt Log List Pointer Bits Note Bits 5 15 indicate the starting Base address while bits 4 0 indicate the ring location of the Interrupt Log List Interrupt Log List Pointer Register BIT Word Register Address 000C H READ WRITE The BIT Word register contains information on the current status of the channel hardware The user defines the lower 8 bits of this register Bit Bit Name Description 15 DMAF DMA Fail 1 All the channel s internal DMA activity was not completed within 16usec 14 WRAPF Wrap Fail The board automatically compares the transmitted word encoder word to the reflected decoder word by way of the continuous loopback feature If the encoder word and reflected word do not match the WRA
105. ter is valid 13usec after the TERACT bit Bit 00 of the Operational Status Register is set to 0 Current Command Block Register Interrupt Mask Register Address 0006 H READ WRITE The EXC 1553P104 MCHB8 interrupt architecture allows for the masking of all interrupts An interrupt is masked if the corresponding bit of this register is set to logic 0 This feature allows the host to temporarily disable the service of interrupts While masked interrupt activity does not occur The unmasking of an interrupt after the event occurs does not generate an interrupt for that event Bit Bit Name Description 12 15 Reserved Set to 0 11 MERR Message Error Interrupt 10 SUBAD Subaddress Accessed Interrupt 09 BDRCV Broadcast Command Received Interrupt 08 IXEQO Index Equal Zero Interrupt 07 ILLCMD Illegal Command Interrupt 00 06 Reserved Set to 0 Interrupt Mask Register page 4 6 Excalibur Systems Chapter 4 4 1 5 Pending Interrupt Register Remote Terminal Operation Address 0008 H READ ONLY The Pending Interrupt Register is used to identify events that generate interrupts The assertion of any bit in this register generates an interrupt A register read of the Pending Interrupt Register will clear all bits Bit 12 15 Reserved 11 10 09 08 07 00 06 Reserved Pending Interrupt Register EXC 1553P104 MCH3 User s Manual Bit Name MERR SUBAD BDRCV IXEQO ILCMD Description Ignore on read Me
106. the second command word The board always stores data associated with an RT to RT These bits define the condition code the board uses for that particular Command Block Each of the available condition codes are defined in BC Condition Codes page 3 13 The board sets this bit to 1 indicating a protocol message error occurred in the RT s response For this occurrence the board will overwrite this bit prior to storing the Control Word into memory An example of this type of error would be noise on the 1553 bus Excalibur Systems Chapter 3 3 3 1 1 OPCODE DEFINITION Opcode 0000 0001 0010 0011 0100 0101 0110 0111 1000 Field Name End Of List Skip Go To Built in Test Execute Block Continue Execute Block Branch Execute Block Branch on Condition Retry on Condition Retry on Condition Branch EXC 1553P104 MCH3 User s Manual Bus Controller Operation Definition This opcode instructs the board that the end of the command block has been encountered Command processing stops and the interrupt is generated if the interrupt is enabled No command processing takes place i e no 1553 This opcode instructs the board to load the message to message timer with the value stored in timer value location The board will then wait the specific time before proceeding to the next command block This opcode allows for scheduling a specific time between message execution No comman
107. tion Word sees ee ee Re Re 5 10 Bus Monitor Block Structuring iss esse eke RA Re ee 5 13 Memory Architecture for Bus Monitor Mode sesse esse ees 5 14 EXC 1553P104 MCH3 Board Layout ccecsceeeeeeeeeteeeees 7 1 Connectors J1 and J2 Layout Front View s es 7 5 MIL STD 1553B Word FormatS esse esse esse ee Re ee 9 1 MIL STD 1553B Message Formats 9 2 Excalibur Systems Contents Tables Table 3 1 MIL STD 1553A B Operation BC Mode ee ee ee ee 3 17 Table 4 1 Illegalization Register Blocks i ee ee ee Re Re ee 4 12 Table 4 2 Illegalization Register Map esse ee Re ee ee Re ee eke 4 13 Table 4 3 RT Mode 2 Control Word and MIB Pointer Structure 4 36 Table 4 4 Mode Code Description ee AA Re RA Re Re 4 38 Table 4 5 MIL STD 1553A B Operation RT Mode ees ee Re 4 43 Table 5 1 MIL STD 1553A B Operation BM Mode ese ee ee ee 5 16 Table 6 1 Interrupt Ring Butter orerar iora ee ee Ee ee AA ee ee Ke ee Ke ee 6 3 Table 7 1 XT AT Connector P1 esse ee Re Re Re Re ek Re ee 7 7 Table 7 2 AT Bus Extension P2 sees a Re ee ee ee Tiin 7 7 EXC 1553P104 MCH3 User s Manual page v Chapter 1 1 1 Introduction Introduction Chapter 1 provides an overview of the EXC 1553P104 MCH3B avionics communication board The following topics are covered 1 1 Overview page 1 1 1 2 Installation page 1 3 1 3 1553 Bus Connections page 1 5 1 4 General I O Map page 1 6
108. to the interrupt lines selected see Interrupt Select Jumpers page 7 8 4 1553 devices may be connected to the 1553 bus either directly direct coupled or via a bus coupling stub transformer coupled Use Jumpers JP25 JP28 JP29 JP32 and JP33 JP36 to set the coupling mode to the 1553 bus es see 1553 Coupling Mode Select Jumpers page 7 4 EXC 1553P104 MCH3 User s Manual page 1 3 Chapter 1 Introduction 5 Make certain the computer power source is disconnected Insert the EXC 1553P104 MCHS board into any PC 104 slot If AT interrupts are to be used i e IRQ greater than 7 a 16 bit slot must be used If only XT interrupts are to be used no loss in speed or functionality will occur if an 8 bit slot is used Once the board is installed a mating I O connector wired with required cables should be attached to the board The cables may be connected to and disconnected from the board while power to the computer is turned on but not while the board is transmitting over the bus page 1 4 Excalibur Systems Chapter 1 1 3 Introduction 1553 Bus Connections For short distances direct coupling may be used to connect the EXC 1553P104 MCH3 directly to another 1553 device To ensure data integrity you must make certain that the cable connecting the two devices is properly terminated with 78 Ohm resistors see Figure 1 2 1553 Device Direct Coupled EXC 1553P104 MCH3 with Direct Coupled Cable Figure 1 2 Direc
109. tor Operation Bus Monitor Operation Chapter 5 describes EXC 1553P104 MCH3 operation in Bus Monitor BM mode The following topics are covered Bus Monitor Message Processing page 5 1 Control Registers BM Mode page 5 3 Bus Monitor Architecture page 5 10 Bus Monitor Block Chaining page 5 18 Memory Architecture page 5 14 RT Concurrent Monitor Operation page 5 15 MIL STD 1553A Operation BC Mode page 5 16 Bus Monitor Message Processing To process messages the EXC 1553P104 MCH3 uses data supplied in the Control Registers along with RAM memory There are eight 16 bit memory locations for each message called a monitor block seven are used and one is reserved The monitor block is updated at the end of command processing The following paragraphs discuss the command block in detail The user allocates memory spaces for each monitor block The top of the monitor blocks can reside at any address location The Control Registers are initialized by the host and linked to the Monitor Block via the Initial Monitor Block Pointer Register and the Monitor Block Counter Register contents Each monitor block contains a Message Information Word Command Word 1 Command Word 2 Data Pointer Status Word 1 Status Word 2 and Time Tag For a full description of each location see Bus Monitor Architecture page 5 10 The Message Information Word allows the board to inform the user on which bus the command was received whether the message was an RT to
110. ts Transmit Last Status Word 1 Allows the board to automatically execute the Transmit Status Word mode code when configured for MIL STD 1553A mode operation Control Register continued from previous page page 4 4 Excalibur Systems Chapter 4 4 1 2 Operational Status Register Remote Terminal Operation Address 0002 H READ WRITE The Operational Status register provides pertinent status information for RT Mode and is not reset to 0000 H on reset Instead the bits A B_STD and RTA 4 0 are set to 1 Bit 11 15 10 09 08 07 04 06 03 02 01 00 Bit Name RTA 4 0 RTAPTY MSEL1 MSELO A B_STD Reserved EX TAPF READY TERACT Description Remote Terminal Address Bits These five bits contain the remote terminal address The RTA4 bit is the MSB bit while the RTAO bit is the LSB bit Terminal Address Parity Bit This bit is appended to the remote terminal address bus RTA 4 0 to supply odd parity The board requires odd parity for proper operation Mode Select 1 In conjunction with Mode Select 0 this bit determines the channel s mode of operation Mode Select 0 In conjunction with Mode Select 1 this bit determines the channel s mode of operation MSEL1 MSELO Mode of Operation 0 0 BC Mode 0 1 RT Mode 1 0 BM Mode 1 1 RT Concurrent Monitor Mode Military Standard 1553A or 1553B This bit determines whether the board will operate under MIL STD 1553A or 1553B
111. tto0 09 SB10 Status bit time 10 08 SB11 Status bit time 11 07 SB12 Status bit time 12 06 SB13 Status bit time 13 05 SB14 Status bit time 14 04 SB15 Status bit time 15 03 SB16 Status bit time 16 02 SB17 Status bit time 17 01 SB18 Status bit time 18 00 SB19 Status bit time 19 1553 Status Word Bits Register MIL STD 1553A 4 1 11 lllegalization Registers Address 0020 003E H The 16 registers are divided into eight blocks two registers per block as shown in Table 4 1 below Block Name Address H Receive 0020 and 0022 Transmit 0024 and 0026 Broadcast Receive 0028 and 002A Broadcast Transmit Automatically Illegalized 002C and 002E Mode Code Receive 0030 and 0032 Mode Code Transmit 0034 and 0036 Broadcast Mode Code Receive 0038 and 003A Broadcast Mode Code Transmit 003C and 003E Table 4 1 Illegalization Register Blocks page 4 12 Excalibur Systems Chapter 4 Remote Terminal Operation The blocks correspond to the following types of Commands Register address 0020 H and 0022 H illegalize receive Commands to 32 subaddresses The most significant bit of register 0020 H controls the illegalization of subaddress 01111 The least significant bit controls subaddress 00000 Register 0022 H controls illegalization of subaddresses 10000 through 11111 The least significant bit relates to subaddress 10000 the most significant bit relates to subaddress 11111 Transmit Commands and Broadcast Commands both receive and transmit
112. uired for all the data words In BC applications the number of data words for each Command Block is known In Figure 3 6 for example the first Command Block has allocated several memory locations for expected data Conversely the second Command Block has only allocated a few memory locations Since the number of data words associated with each Command Block is known memory may be used efficiently Also shown as a separate memory area is the Interrupt Log List see Interrupt Log List Pointer Register page 3 7 Notice that the Interrupt Log List Pointer Register points to the top of the initial Log List After execution of that first BC Command Block the Interrupt Log List Pointer Register will automatically be updated if interrupt condition exists Register Command Data Register Interrupt Blocks Storage Log List Block CMD Words Command Control Word Memory Interrupt Int Info Word 4 Pointer Reg Data Pointer Log List CMD Block Pointer Reg Status Words Int Info Word Branch Add CMD Block Msg Timer Int Info Word Control Word CMD Words CMD Block Data Pointer Int Info Word Status Words CMD Block Branch Add Msg Timer Gegee ig l ords Data Pointer ie rd Status Words Branch Add died Msg Timer Figure 3 6 Memory Architecture for BC Mode page 3 16 Excalibur Systems Chapter 3 3 6 Bus Controller Op
113. ure 1 1 is a block diagram of the EXC 1553P104 MCH3 PC pues BUSALO gt q BUSAL 0 ADDF Channel 0 g ee BUSAH 0 DATA M BUFFER ASIC Module XFRMR 4 BUSBLO p1 i SuMMIT XT B BUSBH 0 I 1 1553 i ig sy BUSAL1 M CONNECTIONS i Channel 1 gy EE BUSAH 1 1 PC ASIC Module BUSBL1 J2 CNTRL _ INTERFACE SUMMIT XT S AMA RR i CONTROLLER e B EBUSBRI1 y I ad I BUSAL 2 lt _ gt XFRMR Aa a SUMMIT XT gt XFRMR e BUSBL 2 E l 24 MHz lt gt A BUSBH 2 1 OSC I I Figure 1 1 EXC 1553P104 MCH3 Block Diagram EXC 1553P104 MCH3 Board Features Three MIL STD 1553 independent dual redundant channels Single supply 5V operation Features Per Channel Operates as BC RT BM or RT Concurrent BM Multiple protocol capability MIL STD 1553A MIL STD 1553B Autonomous operation in all modes 64Kbytes word memory mapped RAM 32 control registers Polling or interrupt driven Real time operation Built In Test capability C software library included Ruggedized extended temperature range available BC Mode Major Minor frames Programmable intermessage gap Automatic retry RT Mode Single RT simulation Subaddress double buffering Circular buffer mode Message illegalization 16 bit time tag Programmable broadcast mode BM Mode 16 bit time tag Filtering per RT Interrupt history list Programmable monitor block count See Ordering Information page 8 1 for the exact part number
114. us B CMD TA 12 In Example 2 the RT will decode the first command on bus A realize the message is for terminal address 1 and start message processing As the message on bus Bis received the board will realize it is to terminal address 12 but since the RT has priority the Bus Monitor will not switch to the bus monitor mode EXC 1553P104 MCH3 User s Manual page 5 15 Chapter 5 5 7 Bus Monitor Operation The above examples also apply to an RT to RT message For example if the first command in an RT to RT transfer matches the terminal address of the RT the entire message will be stored Message 1 However if the first command in an RT to RT transfer matches the terminal address of the Bus Monitor and the second command matches the terminal address of the RT the RT will take priority and only the RT message is stored Message 2 Below is an RT to RT message example Message 1 CMD TA 1 CMD TA 12 Message 2 CMD TA 12 CMD TA 1 MIL STD 1553A Operation BM Mode To maximize flexibility the EXC 1553P104 MCH3 can operate in many different systems that use various protocols Specifically two of the protocols that the board may be used with are MIL STD 1553A and MIL STD 1553B To meet these protocols configure the board through the Control Register ERTO Bit 09 and the Operational Status Register A B_STD Bit 07 Table 5 1 defines the four ways to program the EXC 1553P104 MCHS AIB STD ERTO RESULT 0 0 1553B standard
115. xtended response time out option and forces the BC Mode to look for an RTs response time in 30usec or generate time out errors 0 Enables for the standard time out in 14usec Set to 0 Broadcast Enable 1 Enables the broadcast option for BC Mode 0 Enables Remote Terminal 31 as a unique remote terminal address When enabled the board does not expect a Status Word response from the Remote Terminal Set to 0 Ping Pong Enable This bit controls the method by which the board will retry messages 1 Allows the board to ping pong between buses during retries 0 All retries will be performed on the programmed bus as defined in the Retry Number field of the Command Block control word Interrupt Log List Enable 1 Enables the interrupt log list 0 Prevents the logging of interrupts as they occur Set to 0 page 3 3 Chapter 3 Bus Controller Operation 3 2 2 Operational Status Register Address 0002 H READ WRITE The Operational Status register provides pertinent status information for BC Mode and is not reset to OOOOH on reset Instead the bit A B_STD is set to 1 NOTE To make changes to the BC and this register the STEX bit Bit 15 in the Control Register must be logic 0 Bit Bit Name Description 10 15 Reserved Set to 0 09 MSEL1 Mode Select 1 In conjunction with Mode Select 0 this bit determines the channel s mode of operation 08 MSELO Mode Select 0 In conjunction with Mode Select 1 this bit

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