Application Note
Contents
1. Powers the device Decoupling Filtering capacitors must be added to improve startup stability and reduce source voltage drop Supply ripple must not exceed 20 mVrms VDDPLLA 0 9V to 1 1V Decoupling filtering RLC circuit Powers the PLLA cell The VDDPLLA power supply pin draws small current but it is noise sensitive Care must be taken in VDDPLLA power supply routing decoupling and also on bypass capacitors Supply ripple must not exceed 10 mVrms VDDPLLUTMI 0 9V to 1 1V Decoupling filtering RLC circuit Powers the PLLUTMI cell The VDDPLLUTMI power supply pin draws small current but it is noise sensitive Care must be taken in VDDPLLUTMI power supply routing decoupling and also on bypass capacitors Supply ripple must not exceed 10 mVrms VDDBU 1 8V to 3 6V Decoupling capacitor 100 nF Powers the Backup unit Slow Clock Oscillator On chip RC and a part of the System Controller Supply ripple must not exceed 30 mVrms VDDOSC 1 65V to 3 6V Decoupling Filtering RLC circuit Powers the main oscillator cells The VDDOSC power supply pin draws small current but it is noise sensitive Care must be taken in VDDOSC power supply routing decoupling and also on bypass capacitors Supply ripple must not exceed 30 mVrms VDDIOMO 1 65V to 1 95V Decoupling capacitor 100 nF If the DDRSDR Controller is not used VDDIOMO must be tied to GNDIOM Power the DDR2 L2. Internal architecture of processor ARM Thumb instruction sets Embedded in circuit emulator ARM9EJ S Technical Reference Manual ARM926EJ S Technical Reference Manual Evaluation Kit User Guide AT91SAM9G45 EKES User Guide Using SDRAM on AT91SAM9 Microcontrollers Using SDRAM on AT91SAM9 Microcontrollers Application Note NAND Flash Support in AT91SAM9 Microcontrollers NAND Flash Support in AT91SAM9 Microcontrollers Application Note Implementation of DDR2 on AT91SAM9G45 Devices Implementation of DDR2 on AT91SAM9G45 Devices Application Note 2 Application Note memm 6494D ATARM 09 Mar 10 es Application Note 3 Schematic Check List CAUTION The AT91SAM9 board design must comply with the power up and power down sequence guidelines provided in the datasheet to guarantee reliable operation of the device 1 0V 1 8V and 3 3V Power Supplies Schematic Example DG DC Converter VDDANA X 100nF GNDBU C VDDBU ro VDDIOPO 1 2 100nF J GNDIOP MIE VDDUTMII BT GNDUTMI DQ DC Converter _ T gt VDDIOMO 1 18V 100nF T GNDIOM DC DC Converter E VDDOORE 100nF I GNDOOFE Linear Regulator 1 These values are given only as a typical example 6494D ATARM 09 Mar 10 T Signal Name VDDCORE AMEL Recommended Pin Connection 0 9V to 1 1V Decoupling capacitor 100 nF Description
3. AT91SAM9G45 Microcontroller Schematic Check List 1 Introduction This application note is a schematic review check list for systems embedding the Atmel ARM Thumb based AT91SAM9G45 microcontroller It gives requirements concerning the different pin connections that must be consid ered before starting any new board design and describes the minimum hardware resources required to quickly develop an application with the AT91SAM9G45 It does not consider PCB layout constraints It also gives advice regarding low power design constraints to minimize power consumption This application note is not intended to be exhaustive Its objective is to cover as many configurations of use as possible The Check List table has a column reserved for reviewing designers to verify the line item has been checked AMEL T AT91 ARM Thumb based Microcontrollers Application Note 6494D ATARM 09 Mar 10 AMEL 2 Associated Documentation Before going further into this application note it is strongly recommended to check the latest documents for the AT91SAM9G45 Microcontroller on Atmel s Web site Table 2 1 gives the associated documentation needed to support full understanding of this appli cation note Table 2 1 Associated Documentation Information Document Title User Manual Electrical Mechanical Characteristics AT91 ARM Thumb based Microcontrollers AT91SAM9G45 Preliminary Ordering Information Datasheet Errata
4. D 3 D 39 5 0 15kQ 4 GND DHSDM DFSDM DHSDP Shell Shield 22k Q SAS DFSDP als Cre IHF to 104F 6K8 1 Q VBG 10 pF GND 12 Application Note muz 6494D ATARM 09 Mar 10 es Application Note 4 External Bus Interface EBI Hardware Interface These tables detail the connections to be applied between the EBI pins and the external devices for each Memory Controller Table 4 1 EBI Pins and External Static Devices Connections Pins of the Interfaced Device wie 8 bit Static 3 16 bit Static zma 82 bit Static EBL Device Devices Device Devices Devices Device Controller MC DO D7 DO D7 DO D7 DO D7 DO D7 DO D7 DO D7 D8 D15 D8 D15 D8 D15 D8 D15 D8 15 DB 15 D16 D23 D16 D23 D16 D23 D16 D23 D24 D31 D24 D31 D24 D31 D24 D31 A0 NBSO AO NLB NLB BEO A1 NWR2 NBS2 A1 AO AO WE NLB BE2 A2 A22 A 2 22 A 1 21 A 1 21 A 0 20 A 0 20 A 0 20 A23 A2505 A 23 25 A 22 24 A 22 24 A 21 23 A 21 23 A 21 23 NCSO CS CS CS CS CS CS NCS1 DDRSDCS CS CS CS CS CS CS NCS2 CS CS CS CS CS CS NCS3 NANDCS CS CS CS CS CS CS NCS4 CFCSO CS CS CS CS CS CS NCS5 CFCS1 CS CS CS CS CS CS NRD CFOE OE OE OE OE OE OE NWRO NWE WE WE WE WE WE WE NWR1 NBS1 WE NUB WE NUB BE1 NWR3 NBS3 WE NUB BE3 Notes 1 NWRO enables lower byte writes NWR1 e
5. OW IOW CFCE1 z CE1 cso CFCE2 CE2 CS1 SDCK CK CLK SDCK CK m SDCKE CKE CKE 5 RAS RAS RAS CAS CAS CAS z 14 Application Note memm 6494D ATARM 09 Mar 10 es Application Note Table 4 2 EBI Pins and External Device Connections Continued Pins of the Interfaced Device a DDR2 LPDDR SDRAM CompactFlash 5 ssa NAND Flash Controller DDRC SDRAMC SMC SDWE WE WE u NWAIT WAIT WAIT Pxx0 CD1 or CD2 CD1 or CD2 Pxx CE Pxx0 RDY Notes 1 Not directly connected to the CompactFlash slot Permits the control of the bidirectional buffer between the EBI data bus and the CompactFlash slot 2 Any PIO line 3 CE connection depends on the NAND Flash 6494D ATARM For standard NAND Flash devices it must be connected to any free PIO line For CE don t care NAND Flash devices it can be either connected to NCS3 NANDCS or to any free PIO line 1 08 1 015 pins used only for 16 bit NAND Flash device EBI_NWAIT signal is multiplexed with PC15 09 Mar 10 AMEL 15 AMEL 5 AT91SAM Boot Program Hardware Constraints See the AT91SAM Boot Program section of the AT91SAM9G45 Datasheet for more details on the boot program 5 1 AT91SAM Boot Program Supported Crystals MHz A 12 MHz Crystal or external clock in bypass mode is mandatory in order to generate USB and PLL clocks correctly for the followi
6. PDDR I O lines Decoupling Filtering capacitors must be added to improve startup stability and reduce source voltage drop VDDIOM1 1 65V to 1 95V or 3 0V to 3 6V Decoupling capacitor 100 nF Powers the External Bus Interface I O lines Dual voltage range supported The I O drives are selected by programming the EBI_DRIVE field in the CCFG_EBICSA register At power up the high drive mode for 3 3V memories is selected Decoupling Filtering capacitors must be added to improve startup stability and reduce source voltage drop Application Note memm 6494D ATARM 09 Mar 10 es Application Note Mw Signal Name Recommended Pin Connection Description Powers the USB device and host UTMI interface V to 3 6V VDDUTMII Alea gt 1 2 UE Decoupling capacitor 100 nF Decoupling Filtering capacitors must be added to improve startup stability and reduce source voltage drop 0 9V to 1 1V Powers the USB device and host UTMI core VDDUTMIC Decoupling Filtering capacitors ear f 100 nF and 2 2uF 2 Decoupling Filtering capacitors must be added to improve ep startup stability and reduce source voltage drop VDDIOPO 1 65V to 3 6V Powers the peripherals I O lines VDDIOP1 Decoupling Filtering capacitors e f VDDIOP2 100 nP O Decoupling Filtering capacitors must be added to improve startup stability and reduce source voltage drop anaes P the Analog to Di
7. PIO NPCSO PB3 5 5 TWI EEPROM Boot The TWI EEPROM Flash Boot program searches for a valid application in an EEPROM memory TWI EEPROM Boot supports all I2C compatible EEPROM memories using 7 bits device address 0x50 Table 5 4 Pins Driven during TWI EEPROM Boot Program Execution Peripheral Pin PIO Line TWIO TWDO PA20 TWIO TWCKO PA21 5 6 SAM BA Boot The SAM BA Boot Assistant supports serial communication via the DBGU or the USB Device Port Table 5 5 Pins Driven during SAM BA Boot Program Execution Peripheral Pin PIO Line DBGU DRXD PB12 DBGU DTXD PB13 AMEL 17 6494D ATARM 09 Mar 10 AMEL Revision History Change Request Doc Rev Comments Ref XIN XOUT 12MHz Main Oscillator in Normal Mode edited text removed and figure 7064 G G updated gt Row A15 edited in Table 4 2 EBI Pins and External Device Connections 7028 DDR_VREF contents edited 6982 A Supply ripple unit mV changed into mVrms 6831 6494 Only 1 capacitor value in front of VDDIOP in Section 3 Schematic Check List table 6868 A new reference at the bottom of Table 2 1 Associated Documentation 6775 Note added to VDDIOMO signal in table Note added to DDR_D0O DDR_D15 and DDR_A0O DDR_A13 signals in DDR 6736 Memory Interface DDR2 SDRAM LPDDR Controller table part DDR_VREF signal added to DDR Memo
8. are driven to 0 at reset If the DDR2 Controller is used with LPDDR or DDR2 memory DDR_VREF is connected to VDDIOMOZ i e 0 9V Reference voltage for DDR2 Controller DDR_VREF l If the DDR2 Controller is not used DDR_VREF is If the DDR2 Controller is used with an connected to GND SDRAM memory DDR_VREF is connected to GND or VDDIOMO 2 SMC SDRAM Controller CompactFlash Support NAND Flash Support See External Bus Interface EBI Hardware Interface on page 13 USB High Speed Host UHPHS HFSDPA HFSDPB Abplicationdebenden Integrated pull down resistor to prevent over consumption HHSDPA HHSDPB PE P when the host is disconnected HFSDMA HFSDMB Appiic tionidebendent Integrated pull down resistor to prevent over consumption HHSDMA HHSDMB EE p i when the host is disconnected 6494D ATARM 09 Mar 10 AMEL AMEL M Signal Name Recommended Pin Connection Description USB High Speed Device UDPHS Integrated programmable pull up resistor Integrated programmable pull down resistor to prevent SE over consumption when the host is disconnected DHSDM DFSDP Application dependent To reduce power consumpiion if USB Device is not used connect the embedded pull up Integrated programmable pull down resistor to prevent over consumption when the host is disconnected DHSDP DFSDM Application dependent To reduce power consumption if USB Device is not us
9. ed connect the embedded pull down 10 Application Note memm 6494D ATARM 09 Mar 10 Application Note Notes 1 These values are given only as a typical example 2 Decoupling capacitors must be connected as close as possible to the microcontroller and on each concerned pin 100nF Hi VDDCORE 100nF Hi VDDCORE 100nF l i VDDCORE GND 3 It is recommended to establish accessibility to a JTAG connector for debug in any case 4 Ina well shielded environment subject to low magnetic and electric field interference the pin may be left unconnected In noisy environments a connection to ground is recommended 5 Example of USB High Speed Host connection A termination 39 Ohm serial resistor must be connected to HFSDPx and HFSDMx More details are in the USB High Speed Host Port section of the AT91SAM9G45 Datasheet PIO VBUS DETECT A Receptacle 1 VBUS HHSDM 2 D 3 D 15kQ 4 GND HFsom AE Shield 1 HHSDP 22k Q CRPB E HFSDP 6K8 1 Q AMEL n 6494D ATARM 09 Mar 10 AMEL 6 Typical USB High Speed Device connection As there is an embedded pull up no external circuitry is necessary to enable and disable the 1 5 k Ohm pull up A termination 39 Ohm serial resistor must be connected to DFSDP and DFSDM More details are in the USB High Speed Device Port section of the AT91SAM9G45 Datasheet PIO VBUS DETECT B Receptacle 1 VBUS e 2
10. en low to provide a reset signal to the external components or asserted low externally to reset the Application dependent microcontroller NRST Can be connected to a push button for hardware reset By default the User Reset is enabled after a General Reset so that it is possible for a component to assert low and reset the microcontroller An internal pull up resistor to Vyppiopo 100 kOhm is available for User Reset and External Reset control In harsh environments It is strongly recommended to tie this This pin i hmitt tri i t TST pin to GNDBU if not used or to add h gt gt ASA kOh an external low value resistor such nterna pulzgown resistor to 15 m as 1 kOhm Must be tied to Vyppiopo to boot from Embedded ROM BM Applicati t gt pplibaiondependen Must be tied to GNDIOP to boot from external memory EBI Chip Select 0 Shutdown Wakeup Logic Application dependent A typical application connects the pin This pin is a push pull output SHDN SHDN to the shutdown input of the SHDN pin is driven low to GNDBU by the Shutdown DC DC Converter providing the main Controller SHDWO power supplies This pin is an input only WKUP behavior can be configured through the Shutdown Controller SHDWO WKUP W to Viana PIO All PIOs are pulled up inputs 100 kOhms at reset except those which are multiplexed with the Address Bus signals that require to be enabled a
11. gital C ter ADC and i OE er owers the Analog to Digital Converter and some VDDANA Decoupling Filtering RLC circuit PIOD 1 0 lines Application dependent GNDCORE pins are common to VDDCORE pins GNDCORE Core Chip Ground GNDCORE pins should be connected as shortly as possible to the system ground plane GNDBU pin is provided for VDDBU pins GNDBU Backup Ground GNDBU pin should be connected as shortly as possible to the system ground plane GNDIOM pins are common to VDDIOMO and VDDIOM1 3 pins DR2 EBI I O L PPR a and PALA GNDIOM pins should be connected as shortly as possible to the system ground plane GNDIOP pins are common to VDDIOPO VDDIOP1 and VDDIOP2 pins ipheral ISI I O li SHECE Peripherals and a GNDIOP pins should be connected as shortly as possible to the system ground plane GNDOSC pin is provided for VDDOSC VDDPLLA and GNDOSC PLLA PLLUTMI and Oscillator Ground OWAL n i r Gr a PAR GNDOSC pin should be connected as shortly as possible to the system ground plane GNDUTMI pins are common to VDDUTMII and UDPHS and UHPHS UTMI Core and VDDUTMIC pins GNDUTMI F interface Ground GNDUTMI pins should be connected as shortly as possible to the system ground plane GNDANA pins are common to VDDANA pins GNDANA Analog Ground GNDANA pins should be connected as shortly as possible to the system ground plane 6494D ATARM 09 Mar 10 AMEL Signal Name AMEL Recommended Pin Connection Description Clock Oscillat
12. nables upper byte writes 2 NWRx enables corresponding byte x writes x 0 1 2 or 3 3 NBSO and NBS1 enable respectively lower and upper bytes of the lower 16 bit word 4 NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16 bit word 13 6494D ATARM 09 Mar 10 AMEL AMEL Table 4 2 EBI Pins and External Device Connections Pins of the Interfaced Device sianels DDR2 LPDDR SDRAM compadeasy PER NAND Flash EBI_ True IDE Mode Controller DDRC SDRAMC SMC DO D7 DO D7 DO D7 DO D7 DO D7 00 1 07 D8 D15 D8 D15 D8 D15 D8 15 D8 15 I 08 1 015 D16 D31 D16 D31 gt AO NBSO z AO AO A1 NWR2 NBS2 A1 Al E DQM0 DQM3 DQMO DQM3 DQMO DQM3 n DQS0 DQM1 DQS0 DQS1 z A2 A10 A 0 8 A 0 8 A 2 10 A 2 10 A11 A9 A9 SDA10 A10 A12 A13 A14 A 11 12 A 11 12 z A15 A13 A13 A16 BAO BAO BAO A17 BA1 BA1 BA1 A18 A20 5 A21 NANDALE gt ALE A22 NANDCLE REG REG CLE A23 A24 A25 z CFRNW CFRNW NCS0 NCS1 DDRSDCS DDRCS SDCS NCS2 z NCS3 NANDCS CE NCS4 CFCSO CFCSO CFCSo NCS5 CFCS1 CFCs1 CFCs1 NANDOE z OE NANDWE m WE NRD CFOE OE NWRO NWE CFWE z WE WE NWR1 NBS1 CFIOR 2 IOR IOR NWR3 NBS3 CFIOW B I
13. ng boots 5 2 NAND Flash Boot The first block must be guaranteed by the manufacturer There is no ECC check The supported SLC small block NAND Flash devices are described in the Boot Strategies sec tion of the product datasheet The NAND Flash boot also supports all the SLC large block NAND Flash devices Table 5 1 Pins Driven during NAND Flash Boot Program Execution Peripheral Pin PIO Line EBI CS3 SMC NANDCS PC14 EBI CS3 SMC NAND ALE A21 EBI CS3 SMC NAND CLE A22 EBI CS3 SMC Cmd Addr Data D 16 0 5 3 SD Card Boot SD Card Boot supports all SD Card memories compliant with SD Memory Card Specification V2 0 This includes SDHC cards Table 5 2 Pins Driven during SD Card Boot Program Execution Peripheral Pin PIO Line MCIO MCIO_CK PAO MCIO MCIO_CD PA1 MCIO MCIO_DO PA2 MCIO MCIO_D1 PA3 MCIO MCIO_D2 PA4 MCIO MCIO_D3 PA5 16 Application Note memm 6494D ATARM 09 Mar 10 es Application Note 5 4 Serial and DataFlash Boot Two kinds of SPI Flash are supported SPI Serial Flash and SPI DataFlash The SPI Flash bootloader tries to boot on SPIO Chip Select O first looking for SPI Serial Flash and then for SPI DataFlash The SPI Flash Boot program supports all Serial Flash devices e all Atmel DataFlash devices Table 5 3 Pins Driven during Serial or DataFlash Boot Program Execution Peripheral Pin PIO Line SPIO MOSI PB1 SPIO MISO PBO SPIO SPCK PB2 S
14. or and PLL XIN XOUT 12MHz Main Oscillator in Normal Mode Crystals between 8 and 16 MHz USB High Speed not Full Speed Host and Device peripherals need a 12 Mhz clock Capacitors on XIN and XOUT crystal load capacitance dependent Crystal load capacitance to check Ccpysqa AT91SAM9G45 XOUT GNDOSC CCRYSTAL ee Crext _ Example for a 12 MHz crystal with a load capacitance of Corystat 15 pF external capacitors are required Crexr 22 pF Refer to the electrical specifications of the AT91SAM9G45 Datasheet XIN XOUT 12MHz Main Oscillator in Bypass Mode XIN external clock source XOUT can be left unconnected USB High speed not Full Speed Host and Device peripherals need a 12 Mhz clock VDDOSC square wave signal External clock source up to 50 MHz Duty Cycle 40 to 60 Refer to the electrical specifications of the AT91SAM9G45 Datasheet Application Note saa 6494D ATARM 09 Mar 10 es Application Note Signal Name Recommended Pin Connection Description Crystal load capacitance to check ConvsTaL32 AT91SAM9G45 XOUT32 XIN32 32 768 kHz Crystal XOUT32 Capacitors on XIN32 and XOUT32 crystal load capacitance dependent Slow Clock Oscillator ee Cexra2 T lL Crextsa Example for a 32 768 kHz crystal with a load capacitance of CcnvsTaL32 12 5 pF external capacitors are requi
15. ormation in this document is provided in connection with Atmel products No license express or implied by estoppel or otherwise to any intellectual property right is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH IN ATMELS TERMS AND CONDI TIONS OF SALE LOCATED ON ATMELS WEB SITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifica tions and product descriptions at any time without notice Atmel does not make any commitment to update the information contained herein Unless specifically pro vided otherwise Atmel products are not suitable for and shall not be used in automotive applications Atmel s products are not intended authorized or warranted for use as components in applications intended to supp
16. ort or sustain life OWERED ARMa 2010 Atmel Corporation All rights reserved Atmel Atmel logo and combinations thereof DataFlash SAM BA and others are registered trademarks and others are trademarks of Atmel Corporation or its subsidiaries ARM the ARM Powered logo Thumb and others are regis tered trademarks or trademarks of ARM Ltd Other terms and product names may be the trademarks of others 6494D ATARM 09 Mar 10
17. red Crexta2 19 pF Refer to the electrical specifications of the AT91SAM9G45 Datasheet XIN32 XOUT32 VDDBU square wave signal XIN32 external clock source External clock source up to 44 kHz Slow Clock Oscillator XOUT32 can be left unconnected Refer to the electrical specifications of the in AT91SAM9G45 Datasheet Bypass Mode ICE and JTAG TCK Pull up 100 kOhm This pin is a Schmitt trigger input No internal pull up resistor TMS Pull up 100 kOhm This pin is a Schmitt trigger input No internal pull up resistor This pin is a Schmitt trigger input TDI Pull up 100 kOhm BE No internal pull up resistor TDO Floating Output driven at up to Vyppiopo RTCK Floating Output driven at up to Vyppioop Please refer to the I O line NTRST considerations and the errata sections of the AT91SAM9G45 Datasheet In harsh environments It is strongly recommended to tie this Internal pull down resistor to GNDBU 15 kOhm JTAGSEL pin to GNDBU if not used or to add p an external low value resistor such Must be tied to VyppBu to enter JTAG Boundary Scan as 1 kOhm This pin is a Schmitt trigger input Internal pull up resistor to Vyppiopo 100 kOhm 6494D ATARM 09 Mar 10 T AMEL Signal Name Recommended Pin Connection Description Reset Test NRST is a bidirectional pin Schmitt trigger input It is handled by the on chip reset controller and can be driv
18. ry Interface DDR2 SDRAM LPDDR F 6734 Controller table part 6494B EBI CS0 changed into EBI CS3 in Table 5 1 TWI TWD TWCK changed into TWIO TWDO TWCKO in Table 5 4 In Section 5 1 AT91SAM Boot Program Supported Crystals MHz NAND Flash rfo memory changed into EEPROM memory and TWI EEPROM memories changed into EEPROM memories In Section 3 Schematic Check List Supply Voltage Ripple information added to 6691 VDDCORE VDDPLLA VDDPLLUTMI VDDBU and VDDOSC 6494A First issue 18 Application Note memm 6494D ATARM 09 Mar 10 AIMEL T Headquarters Atmel Corporation 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 487 2600 International Atmel Asia Unit 1 5 amp 16 19 F BEA Tower Millennium City 5 418 Kwun Tong Road Kwun Tong Kowloon Hong Kong Tel 852 2245 6100 Fax 852 2722 1369 Product Contact Web Site www atmel com www atmel com AT91SAM Atmel Europe Le Krebs 8 Rue Jean Pierre Timbaud BP 309 78054 Saint Quentin en Yvelines Cedex France Tel 33 1 30 60 70 00 Fax 33 1 30 60 71 11 Technical Support AT91SAM Support Atmel techincal support Atmel Japan 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Tel 81 3 3523 3551 Fax 81 3 3523 7581 Sales Contacts www atmel com contacts Literature Requests www atmel com literature Disclaimer The inf
19. s peripherals Refer to the column Reset State of the PIO Controller PAX multiplexing tables in the product datasheet PBx Application dependent PCx Schmitt Trigger on All Inputs To reduce power consumption if not used the concerned PIO can be configured as an output driven at 0 with internal pull up disabled ADC 2 4V to VDDANA ADVREF is a pure analog input TSADVREF Decoupling Filtering capacitors To reduce power consumption if ADC is not used Application dependent connect ADVREF to GNDANA Application Note m 6494D ATARM 09 Mar 10 es Application Note M Signal Name Recommended Pin Connection Description EBI DO D31 Application dependent Data Bus DO to D31 All data bus lines are pulled up inputs to Vyppiom at reset Note D16 to D31 are multiplexed with the PIOC controller A0 A25 Application dependent Address Bus A0 to A25 All address lines are driven to 0 at reset Note A19 to A25 are multiplexed with the PIOC controller DDR Memory Interface DDR2 SDR AM LPDDR Controller DDR_DO DDR_D15 Application dependent If the DDRSDR Controller is not used DDR_DO DDR_D15 pins can be left unconnected Data Bus Data bus lines are pulled up inputs to Vyppiomo at reset DDR_A0 DDR_A13 Application dependent If the DDRSDR Controller is not used DDR_A0 DDR_A13 pins can be left unconnected Address Bus All address lines
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