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i.MX6 Hardware Manual

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1. 9999000000b 099999999999 20 57 9 9 ous 2 88 0000000 E Som 204252 000000000 68 0000000 60 000 0000 Figure 2 phyFLEX i MX 6 Component Placement top view PHYTEC Messtechnik GmbH 2013 L 773e 2 5
2. CE JO00000000000000000 100 BH 5050 Uo ud go go go go 0000000 oD JTAG Interface at X4 top view Figure 9 PHYTEC Messtechnik GmbH 2013 L 773e 2 phyFLEX i MX 6 PFL A XL1 xxx 0 0 On DE oon do Of E GEO duo 00 Hun o do gogo DE om Db on CB ao 0 O O coon on g oD CEO on
3. Figure 10 JTAG Interface at X4 bottom view Pin 1 of the JTAG connector X4 is on the connector side of the module Pin 2 of the JTAG connector 15 on the controller side of the module Table 29 shows details on the JTAG signal pin assignment 60 PHYTEC Messtechnik GmbH 2013 L 773e 2 Debug Interfaces Note The JTAG connector X4 only populates phyFLEX i MX 6 modules with a specific order option We recommend integration of a standard 2 mm pitch pin header connector in the user target circuitry to allow easy program updates via the JTAG interface Signal Signal A B VSUPPLY 2 1 TREF VDD 3V3 LOGIC VDD 3V3 LOGIC via 0 Ohms GND 4 3 X JTAG TRSTB GND 5 X JTAG TDI GND 8 T X JTAG TMS GND 10 19 X JTAG TCK GND 12 11 X JTAG RTCK connected via 0 Ohms to X JTAG TCK GND 14 13 X JTAG TDO GND 16 15 X PM nRESET IN GND 18 17 not connected GND 20 119 not connected Table 29 JTAG Connector X4 Signal Assignment Note Row A is on the controller side of the module and
4. 6 PFL A XLI xxx WEO LEO ROO HEO N cro 040 dic CROCSSEOCRO QHHCEO ED COD 3001591 00 1080 50123250 TP2 DEC H GE Rao 08127 0 Rt4Guc 8 85 PESE UTE L 00000000 WA 00000000 A30 8 2 Figure 3 phyFLEX i MX 6 Component Placement bottom view 6 PHYTEC Messtechnik GmbH 2013 1 773 2 Introduction 1 3 Minimum Requirements to operate the phyFLEX i MX 6 Basic operation of the phyFLEX 1 MX 6 only requires supply of a 5 input voltage with 2A load and the corresponding GND connection These supply pins are located at the phyFLEX Connector X1 VDD 5V INR AI A2 B2 B3 Connect all 5 V VCC input pins to your power supply and at least the matching number of GND pins Corresponding GND 4 A10 A16 B4 B7 Please refer to section 2 for information on additional GND Pins located at the phyFLEX Connector X1 Caut
5. Figure 7 Jumper Locations bottom view PHYTEC Messtechnik GmbH 2013 L 773e 2 25 6 PFL A XLI xxx The jumpers J solder jumper have the following functions Jumper Description Type Chapter J3 J3 connects the write protect input of the on board EEPROM with GND If this jumper is not populated the EEPROM is write protected EEPROM is not write protected open EEPROM is write protected The protection can be changed by the EEPROM WP signal J5 J8 These jumpers are connected to the boot 10 21 configuration inputs of the 1 6 They can be J24 J28 used to change the boot settings according to the J30 i MX 6 datasheet Please refer to the i MX 6 data sheet for more detailed information J9 J9 selects rising or falling edge strobe for the LVDS Deserializer at U12 used for the camera connectivity of the phyFLEX 1 MX 6 CSII1 2 3 rising edge strobe used for LVDS camera signals 1 2 falling edge strobe used for the LVDS camera signals J31 J31 selects rising or falling edge strobe for the LVDS Deserializer at U27 used for the camera connectivity of
6. TT EE HE x 8 om zi WLANBluetooth 0000 e dm sd gale 05 d E pe L 000 mr ch n n n n Q no TH Parts Figure 13 phyFLEX Carrier Board Overview of Connectors LEDs and Buttons 78 PHYTEC Messtechnik GmbH 2013 L 773e 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board 18 2 1 Connectors and Pin Header Table lists all available connectors on the phyFLEX Carrier Board Figure 13 highlights the location of each connector for easy identification Reference See Designator Section phyFLEX fix connector for mounting the A phyFLEX 1 MX 6 PNE phyFLEX optional connector for mounting the phyFLEX 1 MX 6 2894 X4 JTAG pin header connector 2 X7 Speaker connector X8 Line out connector X9 Headset out connector 18 3 11 X10 Microphone in connector Line in connector Wall adapter input power jack to supply main board power 12 V max 5 INA X26 USB OTG connector 18 3 7 18 322 X28 Ethernet0 POE RJ 45 connector and 18 3 5 X30 SPII pin header connector 16 3 13 X40 DVI connector 18 3 9 X41 CPU fan connector 18 3 19 8 X45 USBDNO USBDNI amp 18 3 6 connector X50 Serial interface
7. a 5 B go Of do OE gogo un on 0 g M on onon Rocko on 0 m ng o 0 DE o gogo mmo doo go og go go gogo CEU go 000000000000000 0000000000 OO000000000000000000000000
8. Not connected Not connected Not connected Not connected Ground 0 V Not connected Not connected Not connected Not connected Not connected Ground 0 V Not connected Not connected reserved Not connected Not connected Ground 0 V Not connected Not connected reserved Not connected Not connected Ground 0 V Not connected Not connected reserved Not connected Not connected Ground 0 V Not connected Not connected Not connected Not connected Not connected phyFLEX i MX 6 PFL A XLI xxx Pinout of the phyFLEX optional Connector X2 Row B continued ZA zz Z 2121122 X2B17 X2B18 X2B19 X2B20 X2B21 X2B22 X2B23 X2B24 X2B25 X2B26 X2B27 X2B28 X2B29 X2B30 X2B31 X2B32 X2B33 X2B34 X2B35 X2B36 X2B37 X2B38 X2B39 X2B40 X2B41 X2B42 X2B43 X2B44 X2B45 X2B46 X2B47 X2B48 X2B49 X2B50 Table 6 Note Signals on the phyFLEX fix X1 and phyFLEX optional X2 connectors have fixed positions equal for all phyFLEX SOMs Furthermore all phyFLEX SOMs support all interfaces specified for the phyFLEX fix connector X1 As opposed to this the phyFLEX optional connector X2 has optional but defined interfaces at fixed L 773e 2 PHYTEC Messtechnik GmbH 2013 18 Pin Descrip
9. Table 13 PHYTEC Messtechnik GmbH 2013 6 PFL A XLI xxx 6 System Memory The phyFLEX 1 MX 6 provides three types of on board memory e 2 Banks DDR3 RAM 1 GB DDR3 SDRAM up to 4 GB NAND Flash VFBGA 1 GB up to 16 GB e PC EEPROM 4 kB e SPI Flash 16 MB The following sections of this chapter detail each memory type used on the phyFLEX 1 MX 6 6 1 DDR3 SDRAM U2 U9 The RAM memory of the phyFLEX i MX 6 is comprised of up to two 64 bit wide banks each of four 16 bit wide DDR3 SDRAM chips Bank 1 U2 U5 Bank 2 U6 U9 The chips are connected to the special DRR interface called Multi Mode DDR Controller MMDC of the 1 6 processor The DDR3 memory is accessed via the second AHB port starting at 0x1000 0000 Typically the DDR3 SDRAM initialization is performed by a boot loader or operating system following a power on reset and must not be changed at a later point by any application code When writing custom code independent of an operating system or boot loader SDRAM must be initialized by accessing the appropriate SDRAM configuration registers on the 1 MX 6 controller Refer to the i MX 6 Reference Manual for accessing and configuring these registers 1 Please contact PHYTEC for more information about additional module configurations 38 PHYTEC Messtechnik GmbH 2013 1 773 2 System Memory 6 2
10. 90 ADC AAs Power ntis 90 ARICA Power geteilt 91 Table 44 Power Management Connector 22 93 Table 45 USB Hub s Status LEDs D93 96 100 Table 46 USB V BUS indicator LEDS a eee nei hes 100 Table 47 Distribution of the USB Hub s U5 Ports 100 Table 48 Display Data Connector Signal Description 104 Table 49 Auxiliary Interfaces at PDI Data Connector X65 106 Table 50 PDI Power Connector X65 Signal Description 107 Table 51 HDMI DVI Connector X40 108 Table 52 PHYTEC Camera Connector X63 oett tuts 110 Table 53 PHYTEC Camera Connector 4 111 18616542 TE Connect ned 114 Table 55 Addresses in Use 2 114 Table 56 SPIO Connector Selection 115 Table 57 SPIO Pin Header X53 Pinout 0 115 Table 58 SPIL Pin Header X30 Pinout tee tienes 116 Table 59 GPIO Pin Header X54 ona eee 116 Table 60 GPIO Function Description 117 T able 6l PCle0 Connector OS UO te di ute 119 Table 62 SATA Data Connector 62 66 66 121 Table 63 Molex Disk Power Connector 1
11. 121 Table 64 CPU Fan Connector X41 122 Table 65 Wi Fi Bluetooth Connector X58 123 Table 66 phyFLEX Carrier Board DIP Switch S3 Descriptions 125 Table 67 JTAG Connector 66606660660066 127 Table 68 RTC Interrupt Configuration 129 vi PHYTEC Messtechnik GmbH 2013 L 773e 2 Conventions Abbreviations and Acronyms Conventions Abbreviations and Acronyms This hardware manual describes the PFL A XL1 System on Module in the following referred to as phyFLEX i MX 6 The manual specifies the phyFLEX i MX 6 s design and function Precise specifications for the Freescale Semiconductor 1 6 micro controllers can be found in the enclosed microcontroller Data Sheet User s Manual Note We refrain from providing detailed part specific information within this manual which can be subject to continuous changes due to part maintenance for our products Please read the paragraph Product Change Management and information in this manual on parts populated on the SOM within the Preface Note The BSP delivered with the phyFLEX i MX 6 usually includes drivers and or software for controlling all components such as interfaces memory etc Therefore programming close to hardware at register level is not necessary in most cases For this reason this manual contains no detailed descri
12. 7 R 96 115 232 1 44 ICD essere ati 128 S SATA 52 SD MMC Card Interfaces 41 Serial Interfaces 43 SMT Connector ood 8 SPEED EED 98 SPI PIAS i 38 40 SPI Interface 50 Storage Temperature 70 Supply Voltage 27 System Configuration 33 System 38 System 27 Technical 69 Touch Screen Connectivity 107 6 PFL A XLI xxx Camera Signals 26 67 M 49 MAC 49 NAND Flash 39 0 Operating Temperature 70 Operating Voltage 70 P tet 103 phyFLEX Carrier Board 1 79 eer 129 JTAG 127 T Pin 79 BUE Lect tenido n 128 126 TC 124 Switches e 81 Lo CERE EU 88 tabo 112 T 112 D E SLATE xs the 89 RD 0790 88 Po m 101 P UU
13. Pin Signal Name Description 1 GND Ground 2 12 V power supply 3 Tacho Fan Speed Signal 4 PWM Speed Control Signal Table 64 Fan Connector X41 18 3 20 Wi Fi Bluetooth Connector X58 A Wi Fi Bluetooth module such as the PHYTEC PCM 958 can connect to the carrier board s pin header at X58 Different interfaces connect to the Wi Fi Bluetooth module UARTI SPIO 500 To provide the TTL signals of UARTI at the Wi Fi Bluetooth connector X58 jumpers J27 J30 must be closed at 2 3 Use of 51010 for Wi Fi Bluetooth requires JP13 to be switched from position 1 2 to 2 3 LED D107 indicates that SDIO is available at connector X58 No special configuration is required to use SPIO CS3 for Wi Fi Bluetooth connectivity Table 65 shows the pinout of connector X58 122 PHYTEC Messtechnik GmbH 2013 1 773 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board 123 Pin ST SL Description 1 0 3 3 V SPIO CS3 2 Ground 3 O 3 3 V 5210 MOSI 4 1 8 V VCC1V8 5 O 3 3 V SPIO 6 1 8 V VCC1V8 7 Ground 8 Ground 9 O 3 3 V UARTI TXD WLAN TTL 10 3 3 V VREF 01 11 0 3 3 V UARTI RTS WLAN TTL 12 3 3 V VREF SDI 13 IO 3 3 V 5 0 D5 WLAN 14 3 3V VCC3V3 15 Ground 16 3 3V VCC3V3 17 3 3 V SD0 D4 WLAN 18 Ground 19 3 3 V 5 0 06 WLAN 20 3 3 V SPIO MISO 21 3 3V 5 0 D3 WLAN 22 I 3 3 V UARTI RXD WLAN TTL 23 Ground 24 1
14. phyFLEX i MX 6 Hardware Manual Document No L 773e 2 SOM Prod No PFL A XL1 xxx SOM PCB No 1362 1 CB Prod No 01 PCB No 1364 2 1364 3 Edition March 2013 A product of a PHYTEC Technology Holding company 6 PFL A XLI xxx Copyrighted products are not explicitly indicated in this manual The absence of the trademark or and copyright symbols does not imply that a product is not protected Additionally registered patents and trademarks are similarly not expressly indicated in this manual The information in this document has been carefully checked and is considered to be entirely reliable However PHYTEC Messtechnik GmbH assumes no responsibility for any inaccuracies PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product PHYTEC Messtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages that might result Additionally PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software PHYTEC Messtechnik GmbH further reserves the right to alter the layout and or design of the hardware without prior notification and accepts no liability for doing
15. 6 The PHY operates with a data transmission speed of 10 Mbit s 100 Mbit s or 1000 Mbit s 8 4 1 Ethernet PHY 011 With an Ethernet PHY mounted at U11 the phyFLEX i MX 6 has been designed for use in 10 100Base T and 1000Base T networks The 10 100 1000Base T interface with its LED signals extends to the phyFLEX fix Connector X1 Pin Signal ST Voltage Domain Description reference voltage for 10 100Mbit for X ETHO ANALOG hyFLEX 1 MX 6 this pin SIT VOLTAGE HDD S Ep is 1 connected to a 100 nF capacitor tied to ground X1B26 X A TX0 VDD 3V3 LOGIC data A transmit X1B27 A TX0 VDD 3V3 LOGIC data A transmit X1B28 LEDO OC VDD 3V3 LOGIC link LED output XIB29 X B RX0 ETH I VDD 3V3 LOGIC data B receivet XIB30 X I VDD 3V3 LOGIC data B receive X1B32 X C VDD 3V3 LOGIC data C only X1B33 X_ETHO C VDD 3V3 LOGIC data C only GbE X1B34 X LEDI OC VDD 3V3 LOGIC traffic LED output X1B35 D ETH VDD 3V3 LOGIC data D only GbE X1B36 ETHO D ETH VDD 3V3 LOGIC data D only GbE Table 19 Location of the Ethernet Signals The on board GbE PHY sup
16. 142 VCCS X Voltage is off 2 3 VCC5_X Voltage is on Table 43 Power Jumpers 18 3 2 1 Wall Adapter Input X12 Caution Do not use a laboratory adapter to supply power to the carrier board Power spikes during power on could destroy the phyFLEX module mounted on the carrier board Do not change modules or jumper settings while the carrier board is supplied with power Permissible input voltage at X12 12 V DC regulated The required current load capacity of the power supply depends on the specific configuration of the phyFLEX mounted on the carrier board as well as whether optional PCIe boards USB Devices or SATA drives are connected to the carrier board An adapter with a minimum supply of 2 0 A is recommended PHYTEC Messtechnik GmbH 2013 L 773e 2 9 6 PFL A XLI xxx Caution The power supply circuitry on the carrier board is not designed to support all connectable devices at the same time Polarity 412 VDC EL oen gt 2000 mA 5 0 mm 27 GND Figure 18 Power Connector corresponding to Wall Adapter Input X12 Note If many functions and peripherals of the phyCORE i MX 6 kit are used at the same time the power consumption might exceed 60 W 5 A Wall Adapter Input X12 is not capable to support this In this case connector X55 must be used This Connector supports a current of up to 16 18 3 2 2 Power over Ethernet Plus PoE The Po
17. 3v3 Logic serial TES transmit signal X1A19 reference voltage REF_O VDD 3V3 LOGIC 4 voltage X1A20 X UARTO RxD TTL I 3v3 Logic UARTA serial data bb duci receive signal Table 16 Location of the UART Signals The signals extend from UARTS respectively UART4 of the 1 6 directly to the phyFLEX Connector without conversion to RS 232 level External RS 232 transceivers must be attached by the user if RS 232 levels are required 44 PHYTEC Messtechnik GmbH 2013 1 773 2 Serial Interfaces 8 2 USB OTG Interface The phyFLEX i MX 6 provides a high speed USB OTG interface which uses the 1 MX 6 embedded HS USB OTG PHY An external USB Standard A for USB host USB Standard B for USB device or USB mini AB for USB OTG connector is all that is needed to interface the phyFLEX 1 MX 6 USB OTG functionality The applicable interface signals can be found on the phyFLEX fix Connector X1 as shown in Table 17 Pin Signal ST Voltage Domain Description USBO 5 51437 X USB0 nVBUSEN VDD 3V3 LOGIC enable active low X1A38 X USB0 VBUS 5 input 51439 X 08 0 IPU Logic USBO overcurrent pin 41 reference voltage REF O VDD 3V3 LOGIC Uo PO oltage XIA42 X USB0 CHGDET 0 VDD 3v3 Loic charger detection X1B38 X USBO D USB I O i MX 6 internal USBO da
18. phyFLEX i MX 6 PFL A XLI xxx Figure 16 phyFLEX i MX 6 SOM Connectivity to the Carrier Board 88 112111617 POwerlns SCHeING eosam oe e puo MER RE 89 Figure 18 Power Connector corresponding to Wall Adapter Input X12 92 Figure 19 RS 232 Interface Connectors X50 and 51 95 Figure 20 RS 232 Connector X50 Signal Mapping 96 Figure 21 RS 232 Connector X51 Signal Mapping UARTO 96 Figure 22 CAN Connector X52 Signal 97 Figure 23 Ethernet Interface at Connector X28 98 Figure 24 Components supporting the USB Host Interface 99 Figure 25 USB Interface at Connector 26 101 Figure 26 PHYTEC Display Interface PDI at Connector X65 103 Figure 27 Camera Interface at Connector X63 110 Figure 28 Audio Interface at Connectors X7 X8 X9 X10 X11 112 Figure 29 SD MM Card interfaces at connector X57 and X56 118 Figure 30 Boot Mode Selection DIP Switch 83 124 Figure 31 System Reset Button 126 Figure 32 RTC with Battery 128 List of Tables Table 1 Signal Types used in this ix Table 2 Abbreviations and Acronyms used in this Manual X Table3 Pinout of the phyFLEX fix Connector
19. F General Purpose I Os GND Connection H Humidity I PC EEPROM Interface Index 1 1000Base T 47 100Base T 47 101388621 aote tlc 47 9 9 67 A Audio Interface 5 B Block Diagram 4 Booting 33 Camera Interface 66 XN cct uiu th ds 52 97 61 11 32 Control Management IC 32 D i audiet tenis 30 cents 30 DDR3 VIT 30 DDR3 SDRAM 38 Debug 58 Dimensions 70 Display Interface oi 62 E EEPROM 38 39 EEPROM Write Protection 40 xlii EMIC Mu test 32 68 see etes 61 Environment Management IC 68 Ethernet 47 PHYTEC Messtechnik GmbH 2013 L 773e 2 por 110 KOA screen 110 asco n 99 103 PU Reena Neer nee eee EREMO EN 112 AN Bote ds 112 AU ee 78 112 phyFLEX Connector 8 10 Physical Dimensions 69 PHYTEC Display Interface 103 Pin Description 8 Pinout K PEE EN 11 12 13 14 15 P 16 17 18 uade 19 20 21 22 PMIC c eto ete toot 28 Power Consumption 70 Power Domains 29 Power Supply
20. General purpose input output 8 General purpose input output 9 General purpose input output 10 2 0 data 1200 clock Ground 0 V 1200 reference voltage Reset input Reset output Power management bus data EMIC Power management bus clock EMIC Ground 0 V Power on wakeup power off input Power good output Fan PWM output Fan tacho input Pinout of the phyFLEX fix Connector X1 Row A continued Description 5 V Primary Voltage Supply Input 5 V Primary Voltage Supply Input 5 V Primary Voltage Supply Input Ground 0 V JTAG reference voltage Reserved Ground 0 V Pinout of the phy FLEX fix Connector Row 13 VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD PM VDD 3V3 LOGIC VDD 3V3 LOGIC VDD PM Voltage Domain 5V 5V 5V VDD_3V3_LOGIC L 773e_2 1 0 1 0 REF OC OC BI OC BI IPU OC OC 5V PD X1A61 62 6 1 62 61 X1A63 X1A64 Rei X1A65 X1A66 PACIO X1A67 Belo 1 68 X1A69 X1A70 X1A71 X1A72 X1A73 X PM nRESET IN X PM nRESET OUT X1A74 X PM SDA X1A75 X SCL X1A76 X PM nON WAKEUP X1A77 IS X PM PWR GOOD X PM PWM X PM TACHO X1A78 X1A79 X1A80 Table 3 Pin Signal XIBI
21. VDD 3V3 LOGIC X2A49 X CLK O VDD 3V3 LOGIC Cameral refe rence voltage 2 50 reference voltage REF VDD 3V3 LOGIC Table 35 Camera Interface Signal Location at X2 To assists the implementation of a power management the Deserializer s REN inputs are connected to the CSIO DATA EN pad U27 respectively to the EIM DAIO pad U12 of the 1 6 Furthermore the nPWRDN signals of the Deserializers are connected to the ENET RX ER pad U27 respectively to the EIM EBO pad U12 of the 1 6 Thereby the LVDS Deserializer can be turned off by software 66 PHYTEC Messtechnik GmbH 2013 1 773 2 LVDS Camera Interface 14 1 Signal Configuration J9 and J31 selects rising or falling edge strobe for the LVDS Deserializer at 9 U12 used for the camera connectivity of the phyFLEX 1 MX 6 CSII port J31 selects rising or falling edge strobe for the LVDS Deserializer at U27 used for the camera connectivity of the phyFLEX 1 MX 6 CSIO port Position Description Type 243 rising edge strobe used for the LVDS camera OR signals 0402 1 2 falling edge strobe used for the LVDS camera signals Table 36 LVDS Signal Configuration J9 731 PHYTEC Messtechnik GmbH 2013 1 773 2 67 phyFLEX i MX 6 PFL A XLI xxx 15 Environment Management IC EMIC U19 The optional Environment Management IC EMIC
22. VDD 3V3 PMIC IO VDD SDO LDOs VDD 501 VDD MX6 HIGH Figure 8 Powering scheme of phyFLEX i MX 6 PHYTEC Messtechnik GmbH 2013 1 773 2 31 6 PFL A XLI xxx 4 3 Supply Voltage for external Logic The voltage level of the phyFLEX s logic circuitry is VDD 3V3 LOGIC 3 3 V which is generated on board In order to allow connecting external devices to the phyFLEX 1 MX 6 without the need of another voltage source in addition to the primary supply this voltage is brought out at the different reference voltage pins of the phyFLEX Connector Use of level shifters supplied with VDD 3V3 LOGIC allows converting the signals according to the needs on the custom target hardware Alternatively signals can be connected to an open drain circuitry with a pull up resistor attached to VDD 3V3 LOGIC Please use this voltage only as reference and not for supplying purpose 4 4 Control Management IC CMIC U17 The phyFLEX 1 MX 6 provides an on board Control Management IC CMIC at position U17 to control different phyFLEX specific functions such as power management reset or boot configuration Please refer to the phyFLEX specification for further information 32 PHYTEC Messtechnik GmbH 2013 1 773 2 System Configuration and Booting 5 System Configuration and Booting Although most features of the 1 6 microcontroller are configured and or programmed during the initialization routine othe
23. 0 to the desired output level A high level turns the LED on a low level turns it off PHYTEC Messtechnik GmbH 2013 L 773e 2 57 6 PFL A XLI xxx 11 Debug Interface X4 The phyFLEX i MX 6 is equipped with a JTAG interface for downloading program code into the external flash internal controller RAM or for debugging programs currently executing The JTAG interface extends to the phyFLEX fix connector and also to a 2 0 mm pitch pin header at X4 on the edge of the module PCB Table 28 shows the location of the JTAG pins on the phyFLEX fix connector X1 Pin Signal ST Voltage Domain Description X1A5 X nTRST 1 VDD 3V3 LOGIC Men nese X1A6 X JTAG TDI I VDD_3V3_ LOGIC JTAG TDI X1A7 X JTAG TMS VDD 3V3 LOGIC JTAG TMS 8 X 0 VDD 3V3 LOGIC JTAG TDO X1A9 X I VDD 3V3 LOGIC o X1A10 GND Ground 0 V XIAII X JTAG RTCLK O VDD 3V3 LOGIC I m 2 RTCLK JTAG 5 reference voltage REF VDD 3V3 LOGIC reference voltage Table 28 Debug Interface Signal Location at phyFLEX Connector Figure 9 and Figure 10 show the position of the debug interface JT AG connector X4 on the phyFLEX 1 MX 6 module 58 PHYTEC Messtechnik GmbH 2013 1 773 2 Debug Interfaces 59 um Up moon a
24. Touch Touch Touch Not connected Ground Light sensor analog input SL 3 3 7 3 3 7 3 3 7 3 3 7 3 3 7 3 3 7 3 3 7 3 3 7 3 3 7 3 3 7 3 3 7 3 3 7 3 3 7 3 3 7 3 3 7 3 3 7 3 3 7 3 3 7 3 3 7 ST O 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 Signal name DISP ENA PHYWIRE GND USB DP DN2 USB DM DN2 GND LVDS_LO LVDS 10 GND LVDS 14 LVDS 11 GND LVDS L2 LVDS L2 GND LVDS 13 LVDS L3 GND LVDS CLK LVDS_CLK GND TS X TS TS TS Y NC GND LS ANA Display Data Connector Signal Description continued 105 L 773e 2 Pin B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 Table 48 PHYTEC Messtechnik GmbH 2013 phyFLEX i MX 6 PFL A XLI xxx The table below shows the auxiliary interfaces at display data connector X65 Signal Description USBDN2 USB host interface derived form port 2 of the USB hub at U33 Suitable for optional features e g front USB 12 0 interface for optional EEPROM or other devices SPIO SPI interface to connect optional SPI slave 1 WIRE Hardware Introspection Interface For internal use only Power_ON Wake OFF Power on off signal to allow for an ON OFF switch on a front pa
25. 15 X1B16 X1B17 8 2 X_ETHO_ANALOG_ VOLTAGE GND X A TX0 X ETHO 0 X LEDO X B RX0 X GND X C X ETHO C X ETHO LEDI X ETHO D X ETHO D GND X_USB0_D X_USB0_D X_USB0_ID N C N C Pinout of the phyFLEX fix Connector X1 Row B continued L 773e 2 PHYTEC Messtechnik GmbH 2013 X1B19 X1B20 X1B21 X1B22 X1B23 X1B24 X1B25 X1B26 X1B27 X1B28 X1B29 X1B30 X1B31 X1B32 X1B33 X1B34 X1B35 X1B36 X1B37 X1B38 X1B39 X1B40 X1B41 X1B42 X1B43 X1B44 X1B45 Table 4 14 Pin Description reserved Not connected Not connected Ground 0 V LVDSO 0220 LVDSO data0 LVDSO display enable low active LVDSO datal LVDSO datal Ground 0 V LVDSO data2 LVDSO data2 LVDSO backlight PWM output LVDSO data3 LVDSO data3 Ground 0 V LVDSO0 clock LVDSO clock LVDSO reference voltage 20160 present signal low active PCIe0 reference voltage Ground 0 V 0 transmit lane PCIe0 transmit lane 20160 wake signal low active 20160 receive PCIe0 receive lane Ground 0 V PCIe0 clock PCIe0 clock lane Boot configuration 0 Boot configuration 1 Boot configuration 2 Ground 0 V reserved 1 MX 6 internal 1 MX 6 internal
26. L 773e 2 125 phyFLEX i MX 6 PFL A XLI xxx 18 3 22 System Reset Button S1 Figure 31 System Reset Button 51 The phyFLEX Carrier Board is equipped with a system reset button at Sl Pressing the button will reset the phyFLEX mounted on the phyFLEX Carrier Board In the sequel the phyFLEX module generates the signal nRESET OUT which resets the peripheral devices on the phyFLEX Carrier Board such as the USB Hub etc 126 PHYTEC Messtechnik GmbH 2013 1 773 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board 18 3 23 JTAG Interface X4 The JTAG interface of the phyFLEX 1 MX 6 is accessible at connector X4 on the carrier board This interface 1 compliant with JTAG specification IEEE 1149 1 or IEEE 1149 7 No jumper settings are necessary for using the JTAG port The following table describes the signal configuration at X4 When referencing contact numbers note that pin 1 located at the angled corner Pins towards the labeling ARM JTAG odd numbered Pin Signal Name ST SL Description 1 VREF JTAG O 33 JTAG reference voltage 2 VREF JTAG O 33 JTAG reference voltage 3 nJTAG TRST I 3 3V JTAG Test Reset 4 6 8 10 GND Ground 12 14 18 20 5 JTAG TDI I 3 317 JTAG Test Data Input 7 JTAG TMS 3 3V JTAG Test Mode Select Signal 9 JTAG TCK I 3 3V JTAG Test Clock Signal T JTAG RTCLK O 33 J TAG Return Test Clock Signal 13
27. PClex TX Ground PClex RX PClex PRSNT Ground Ground Signal Name GND3 REFCLK HSOP 0 GND8 HSON 0 HSLP 0 GND4 HSLN 0 PRSNT2 GND9 GND5 PCIe0 Connector X59 continued PHYTEC Messtechnik GmbH 2013 Pin B13 14 14 15 15 16 16 17 17 18 B18 Table 61 120 The phyFLEX i MX 6 on the phyFLEX Carrier Board 18 3 18 SATA X62 X61 The phyFLEX Carrier Board provides the possibility to directly connect an SATA hard disk drive There are two connectors provided The first connector X62 is a Foxconn LD1807F S51P and dedicated for Data Signals The Second Connector X61 is Molex Disk Drive Connector and dedicated for power supply of the hard disk drive Description Ground Ground Ground SATA TX SATA TX Ground SATA _ RX SATA RX Ground Signal Name Shield1 Shield2 GND TX RX GND SATA Data Connector X62 Description 12 V power supply Ground Ground 5 V power supply Signal Name VCC12 GND GND 5 Molex Disk Power Connector X61 L 773e 2 121 Pin SI Table 63 PHYTEC Messtechnik GmbH 2013 6 PFL A XLI xxx 18 3 19 CPU Fan Connector X41 If a CPU Fan 15 used the carrier board supports the direct connection of a standard CPU fan with speed control at X41
28. SPIO pin B2 SPIO MISO pin X65 SPIO MOSD pin SPIO_CS1 Wi Fi Bluetooth 5 SPIO pin 20 SPIO MISO pin 3 connector X58 5 0 51 pin 1 SPIO CS3 SPIO pin header see Table 7 connector X53 Table 56 SPIO Connector Selection Pin ST SL Description 1 NC Not Connected 2 NC Not Connected 3 NC Not Connected 4 0 3 3 V SPIO CS2 5 0 3 3 V SPIO CS3 6 I 3 3 V SPIO MISO 7 0 3 3 V 5210 MOSI 8 0 3 3 V SPIO CLK 9 GND Ground 10 O 3 3V VREF SPIO Table 57 SPIO Pin Header X53 Pinout The second 5211 interface is available with two chip selects at pin header connector X30 PHYTEC Messtechnik GmbH 2013 L 773e 2 115 phyFLEX i MX 6 PFL A XLI xxx Pin ST SL Description 1 NC Not Connected 2 NC Not Connected 3 NC Not Connected 4 0 33V SPII CSI 5 0 33V SPIO CSO 6 I 33V 5211_7150 7 0 33V 5211 MOSI 8 0 3 3 V CLK 9 GND Ground 10 0 33V VREF SPII Table 58 SPII Pin Header X30 Pinout 18 3 14 User programmable 5 Some GPIOs on phyFLEX Carrier Board are reserved for several functions All GPIOs are also mapped at GPIO Connector X54 See Table 60 which function each GPIO has Pin ST SL Description 1 3 3 V VREF GPIO 2 3 3 V GPIOO 3 LO 3 3 V GPIOI 4 LO 3 3V GPIO2 5 IO 3 3V GPIO3 6 LO 3 3V GPIO4 7 LO 3 3 V GPIO5 8 LO 3 3 V GPIO6 9 LO 3 3 V GP
29. VDD 3V3 LOGIC 1 MX 6 internal 1 MX 6 internal 1 MX 6 internal 1 MX 6 internal VDD 3V3 LOGIC 1 MX 6 internal 1 MX 6 internal 1 MX 6 internal 1 MX 6 internal VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC 1 MX 6 internal 1 MX 6 internal VDD 3V3 LOGIC 1 MX 6 internal 1 MX 6 internal 1 6 internal 1 6 internal VDD_PM VDD_PM VDD_PM LVDS_O LVDS_O 1 0 LVDS O LVDS O LVDS O LVDS O 1 0 LVDS O LVDS O LVDS O LVDS O REF O RSVD N C N C X BOOTO X BOOTI X BOOT2 Pinout of the phyFLEX fix Connector X1 Row B continued 15 L 773e 2 X1B46 X1B47 X1B48 X1B49 X1B50 1 51 X1B52 X1B53 X1B54 X1B55 X1B56 X1B57 X1B58 X1B59 X1B60 X1B61 X1B62 X1B63 X1B64 X1B65 X1B66 X1B67 X1B68 X1B69 X1B70 X1B71 X1B72 X1B73 X1B74 X1B75 X1B76 X1B77 X1B78 Table 4 PHYTEC Messtechnik GmbH 2013 Description I2C1 data 1201 clock I2C1 reference voltage CANO transmit CANO receive Ground 0 V CANO reference voltage HDMIO data HDMIO clock SATAO transmit lane SATAO transmit lane Ground 0 V SATAO receive SATAO receive lane SDI data 3 SD1 command SD1 clock Ground 0 17 5101 reference voltage SDI write protection active low 5101 card detection active low SD1 data 0 SD1 data 1 Ground
30. X HDMIO TMDS CLOCK TMDS 1 6 internal A X2B12 X HDMIO VO VDD 3V3 LOGIC X2B13 X HDMIO nHPD I VDD 3V3 LOGIC HEIDE x m d plug detect Table 34 HDMI Interface Signal Location at X2 PHYTEC Messtechnik GmbH 2013 1 773 2 65 6 PFL A XLI xxx 14 LVDS Camera Interface phyFLEX i MX 6 uses two l channel 10 Bit LVDS Random Lock Deserializer U12 and U27 to receive LVDS Signals from a LVDS Camera Interface The LVDS Deserializer converts the LVDS Signals to a 10 bit wide parallel data bus and separate clock which can be used as inputs for the 1 6 Camera Sensor Interfaces U12 15 connected to and U27 is connected to CSIO The 10 bit wide data bus consists of 8 color information bits and 2 sync bits HSYNC VSYNC The following table shows the location of the applicable interface signals CAMERAx X CAMERAx l X CAMERAx L on the phyFLEX Connector Pin Signal ST Voltage Domain Description X2A40 X CAMERAO 10 LVDS I VDD 3V3 LOGIC Camera0 028 X2A41 X CAMERAO L0 LVDS I VDD 3V3 LOGIC Camera0 data 0 X2A43 X CAMERAO CLK VDD 3V3 LOGIC 2 master clock Camera0 refe rence voltage X2A46 X 10 LVDS I VDD 3V3 LOGIC Cameral datat X2A47 X L0 LVDS I VDD 3V3 LOGIC data Cameral master clock X2A44 reference voltage REF
31. X1B2 X1B3 X1B4 X1B5 X1B6 X1B7 Table 4 PHYTEC Messtechnik GmbH 2013 5100 reference voltage SDO write protection active low SDO card detection active low SDO data 3 5100 command Ground 0 V 5100 clock SDO data 0 5100 data 1 SDO data 2 5100 data 4 Ground 0 V SDO data 5 SDO data 6 SDO data 7 reserved reference voltage for 10 100 Mbit Ground 0 V ETHO data A transmit ETHO data A transmit ETHO link LED output data B receive ETHO data B receive Ground 0 V ETHO data C only GbE ETHO data C only GbE ETHO traffic LED output ETHO data D only GbE data D only GbE Ground 0 V USBO data USBO datat USBO ID Pin Not connected Not connected Ground 0 V USBO data USBO datat phyFLEX i MX 6 PFL A XLI xxx VDD SD0 VDD SD0 VDD SD0 VDD SD0 VDD SD0 VDD SD0 VDD SD0 VDD SD0 VDD SD0 VDD SD0 VDD 00 VDD SD0 VDD SD0 VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC 1 MX 6 internal 1 MX 6 internal VDD 3V3 LOGIC 1 MX 6 internal 1 MX 6 internal REF O ETH O ETH O OC ETH I ETH I ETH ETH OC ETH ETH USB USB X1B8 X1B9 0 X1B12 X1B13 4 1
32. 00000 98 bo 127 DAO mp IR 108 XA ERE 122 PO 99 D S NOE ACER 95 AA Od stel ELA taba 97 b ist PERPE PE EE SPEM 122 XI RP 119 AOL ASI E 121 b OP MERE 121 134 PHYTEC Messtechnik GmbH 2013 L 773e 2 U USB 45 46 39 2 2 E TON ERN MP 47 BO JUN MERE 26 67 V pn VCC PM 30 19 eee 68 VDD 5V IN 29 5 eee eee ee eee eee eee ee eee eee ee eee 4 0 VD D_5 V INR 2 7 It t TAN POR eee 2 Pee ee 26 67 8 38 W eiie tt pne 44 ne 70 USB 45 X USB 2 0 ees 101 101 USB ou tiis otis 99 HEN 58 USB 45 PHYTEC Messtechnik GmbH 2013 1 773 2 135 phyFLEX i MX 6 PFL A XLI xxx 136 PHYTEC Messtechnik GmbH 2013 1 773 2 Suggestions for Improvement Document phyFLEX i MX 6 Document number L 773e 2 March 2013 How would you improve this manual Did you find any mistakes in this manual page Submitted by Customer number Name
33. 1 6 controller ar e shown in Table 11 PHYTEC Messtechnik GmbH 2013 L 773e 2 33 Bootsource NAND SSD eMMC SPIO alternative on board memory e g SSD eMMC 5100 external Serial UART or USB SATAO USBO specific e g PCIe Ethernet On board memory e g X BOOTO 1 0 o lr o phyFLEX i MX 6 PFL A XLI xxx 1 1 c X BOOTI X BOOT2 1 1 2 2 Boot Mode 0 1 optional 2 optional 3 optional 4 optional 5 optional 6 optional 7 optional Table 10 Standard phyFLEX Boot Options phyFLEX i MX 6 specific boot options are shown in the following table Boot Mode X BOOT2 X X BOOTO Bootsource 0 1 1 1 NAND 5213 CSO on board SPI 1 1 1 0 Flash if populated same as mode 2 5213 CSO on board SPI 2 1 0 1 Flash if populated same as mode 1 3 1 0 0 5100 external 4 0 1 1 Serial USB OTG USBO same as mode 6 5 0 1 0 SATA 6 0 0 1 Serial USB OTG USBO same as mode 4 7 0 0 0 Bootconfig from eFUSE Table 11 phyFLEX i MX 6 specific Boot Options 34 PHYTEC Messtechnik GmbH 2013 L 773e 2 System Configuration and Booting The BOOT 2 0 lines have 10 pull up resistors populated on the module Hence leaving the three pins unconnected sets the controller to boot mod
34. 1 2 GHz core clock frequency e Boot from different memory devices NAND Flash standard phyFLEX bus Commonly used interfaces such as Ethernet USB UART SPI audio PCIe SATA CAN display and camera connectivity both LVDS are available at up to three high density 0 5 mm samtec connector enabling the phyFLEX i MX 6 to be plugged like a big chip into target application e Single supply voltage of 5 V e All controller required supplies generated on board e Improved interference safety achieved through multi layer PCB technology and dedicated ground pins e up to DDR3 SDRAM e up to 16 GB on board NAND Flash 2 PHYTEC Messtechnik GmbH 2013 L 773e 2 Introduction Up to 16 MB on board serial Flash bootable Up to 4 kB EEPROM Serial interface with 4 lines TTL allowing simple hardware handshake High Speed USB OTG transceiver High Speed USB HOST transceiver 10 100 1000 Mbit Ethernet interface Two I C interfaces Two SPI interfaces PCIe Interface IS Interface CAN interface Media Local Bus MLB interface 4 Channel LVDS 24 Bit LCD Interface HDMI interface Two LVDS Camera Interface Two SD MMC card interfaces SATA interface Support of standard 20 pin debug interface through JTAG connector Eleven GPIO IRQ ports with phyFLEX flex connector even more Two user programmable LEDs Power Management IC PMIC Optional Environment Management IC EMIC to monitor v
35. 3 3 V UARTI CTS WLAN TTL 25 3 3 V SD0 D2 WLAN 26 Ground 27 IO 3 3 V SD0 DI WLAN 28 3 3 V SD0_D7 WLAN 29 3 3 V SD0_D0 WLAN 30 IO 3 3 V 500 CMD WLAN 31 Ground 32 0 3 3 V 5 0 CLK _ WLAN Table 65 Wi Fi Bluetooth Connector X58 L 773e 2 PHYTEC Messtechnik GmbH 2013 phyFLEX i MX 6 PFL A XLI xxx 18 3 21 Boot Mode Selection S3 Figure 30 Boot Mode Selection DIP Switch S3 The boot mode DIP Switch 53 is provided to configure the boot mode of the phyFLEX i MX 6 after reset This DIP Switch allows to choose different boot sources The following table gives an overview of the different boot Sources Note The following table describes only settings suitable for the phyFLEX i MX 6 Other settings must not be used with the phyFLEX 1 MX 6 124 PHYTEC Messtechnik GmbH 2013 1 773 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board Boot X BOOT2 BOOTI X BOOTO BOOT Source Mode 53 3 53 2 53 1 0 1 1 1 On board mass storage NAND SSD eMMC 1 1 1 0 SPIO 2 1 0 1 Alternative on board mass storage SSD eMMC 3 1 0 0 5100 external 4 0 1 1 Serial UARTO 5 0 1 0 SATAO 6 0 0 1 USBO Specific 0 0 PCIe Ec Ethernet Table 66 phyFLEX Carrier Board DIP Switch S3 Descriptions P Default settings are in bold blue text PHYTEC Messtechnik GmbH 2013
36. Company Address Return to PHYTEC Messtechnik GmbH Postfach 100403 D 55135 Mainz Germany Fax 49 6131 9221 33 PHYTEC MesstechnikGmbH 2013 L 773e 2 Published by mer MIEL PHYTEC Messtechnik GmbH 2013 Ordering No L 773e_2 Printed in Germany
37. DB 9F UARTI with 18 3 3 handshakes Table 37 phyFLEX Carrier Board Connectors and Pin Headers Ethernet is not supported by the phyFLEX i MX 6 PHYTEC Messtechnik GmbH 2013 1 773 2 79 phyFLEX i MX 6 PFL A XLI xxx Description pies Designator Section X51 Serial Interface DB 9F UARTO without 18 3 3 Handshakes X52 CAN interface DB 9M 18 3 4 X53 SPIO pin header connector 18 3 13 X54 GPIO pin header connector 16 3 14 X55 Alternative power connector 12 V gt 5 A 8 3 2 X56 Secure Digital MultiMedia Card 1011 18 3 16 X57 Secure Digital MultiMedia Card slot0 X58 Wi Fi Bluetooth connector 18 3 20 X59 PCIeO0 connector 18 3 17 X61 SATA power connector 18 3 18 X62 SATA data connector X63 Camera 0 phyCAM S Connector 18 3 10 X64 Camera 1 phyCAM S Connector 16 3 10 X65 PDI PHYTEC Display Interface 18 3 6 Table 37 phyFLEX Carrier Board Connectors and Pin Headers continued Note Ensure that all module connections are not to exceed their expressed maximum voltage or current Maximum signal input values are indicated in the corresponding controller User s Manual Data Sheets As damage from improper connections varies according to use and application it is the user s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals 80 PHYTEC Mes
38. Interface Signal Location at 12 1 LVDS Display Interface pixel mapping The phyFLEX specification defines the pixel mapping of the LVDS display interface The pixel mapping equates to the OpenLDI respectively Intel 24 0 or JEIDA standard Thus you can connect 18 bit as well as 24 bit LVDS displays to the phyFLEX Table 32 and Table 33 show the recommended pixel mapping of the LVDS display However since the 1 6 LDB Module supports also the SPWG pixel mapping this one can be used as well by setting the appropriated configuration bit PHYTEC Messtechnik GmbH 2013 1 773 2 63 phyFLEX i MX 6 PFL A XLI xxx Note To be fully compatible to the phyFLEX specification make sure that the LVDS display you want to use provides the same pin mapping as the phyFLEX JEIDA respectively OpenLDI Normally this is only important for 24 bit LVDS displays because due to the organization of the LVDS pixel mapping all common 18 bit LVDS displays should RO Gl B2 R2 G3 B4 RO L 773e 2 G2 B3 R3 G4 B5 RI 3 0 R2 G3 B4 0 4 0 R3 G4 B5 0 3 0 R4 G5 HSYNC 0 Work 18 bit LVDS Display 2 1 R5 BO VSYNC 0 1 1 00 Bl DE 0 Pixel Mapping of 18 bit LVDS Display Interface 3 0 R4 G5 B6 GO 4 0 R5 G6 B7 Gl 3 0 R6 G7 HSYNC BO CLK 1 2 Table 32 24 bit LVDS
39. PHYTEC Messtechnik GmbH 2013 L 773e 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board LED Color Description vee Section D96 green suspend status indicator LED for USB 18 3 6 hub s upstream port D106 red 5100 Card Connector X57 active 18 3 16 D107 red SDO Wi Fi Bluetooth Connector X58 active 18 3 20 D85 green Indicates presence of VBUS at the USB OTG 1837 interface D84 Indicates presence of VBUS at the USB Host interface USB1 USB hub s upstream D87 green VBUS indicator for USB Hub downstream port USB 18 3 6 DNO VBUS indicator for USB Hub downstream port USB D88 green DNI Table 39 phyFLEX Carrier Board LEDs Descriptions continued Note Detailed descriptions of the assembled connectors jumpers and switches can be found in the following chapters PHYTEC Messtechnik GmbH 2013 1 773 2 83 6 PFL A XLI xxx 18 2 4 Jumpers phyFLEX Carrier Board comes pre configured with removable jumpers JP and solder jumpers J The jumpers allow the user flexibility of configuring a limited number of features for development constraint purposes Table 40 below lists the jumpers their default positions and their functions in each position Figure 14 depicts the jumper pad numbering scheme for reference when altering jumper settings on the development board Figure 15
40. Row A 11 Table4 Pinout of the phyFLEX fix Connector Row B 13 Table 5 Pinout of the phyFLEX optional Connector X2 Row A 16 Table6 Pinout of the phyFLEX optional Connector X2 Row B 17 Table 7 Pinout of the phyFLEX flex Connector Row A 19 Table 8 Pinout of the phyFLEX flex Connector Row B 20 Table 9 Jumper 5161189 oes eeu te et tette 26 Table 10 Standard phyFLEX Boot 34 iv PHYTEC Messtechnik GmbH 2013 L 773e 2 Contents phyFLEX i MX 6 specific Boot Options Boot Configuration Pins at phyFLEX flex Connector X3 Boot Configuration Signals generated by the EEPROM write protection states via J3 Location of SD MMC Card Interface Signals Location of the UART 1 Location of the USB Signals Location of the USB Host Signals Location of the Ethernet 1 1 Interface Signal SPI Interface Signal Location IS Interface Signal CAN Interface Signal SATA Inter
41. SDO data 7 SD1 data 3 SD1 command SD1 clock SD1 reference voltage SD1 write protec tion active low SD1 card detection active low SD1 data 0 SD1 data 1 SD1 data 2 Voltage Domain VDD SDO VDD SDI VDD SDI VDD SDI VDD SDI VDD SDI VDD SDI VDD SDI VDD SDI VDD SDI phyFLEX i MX 6 PFL A XLI xxx ST 0 0 REF O I Signal X SD0 D7 X 01 X SDI CMD X SDI CLK reference voltage X 501 nWP X 501 nCD X SD1 X SDI DI X SDI D2 Location of SD MMC Card Interface Signals continued L 773e 2 PHYTEC Messtechnik GmbH 2013 Pin X1B22 2 15 2 16 X2A17 X2A19 X2A20 X2A21 X2A22 X2A23 X2A25 Table 15 42 Serial Interfaces Serial Interfaces 8 phyFLEX 1 MX 6 provides numerous serial interfaces some of which are equipped with a transceiver to allow direct connection to external devices Two High speed UARTs TTL derived from UART3 and UARTA of the 1 MX 6 with up to 4 MHz and one with hardware flow control RTS and CTS signals High speed USB OTG interface extended directly from the i MX 6 s USB HS OTG PHY USB PHY High speed USB HOST interface extended directly from the i MX 6 USB HOST PHY USB PHY Auto MDIX enabled 10 100 1000 Mbit Ethernet interface Two interface derived from port 2 and port 3 of the i MX 6 Two Serial Periphera
42. are located on the phyFLEX module Furthermore BCFG1 4 BCFG2 1 and BCFG4 2 have 10 on board configuration resistors too The specific boot configuration settings which are set by the on board configuration resistors can be changed by modifying the resistors on the module or by connecting a configuration resistor e g 1 kQ to the configuration signal Please consider that any change of the default BCFG configuration can also influence other boot modes which might result in faulty boot behavior For further information about the different boot modes and the influence of the BCFG pins please see i MX 6 Reference Manual Table 13 shows to which level the CMIC sets the different configuration signals for the boot modes Z means that the CMIC sets the signal to high impedance and thus the value of the configuration resistor is used 36 PHYTEC Messtechnik GmbH 2013 1 773 2 System Configuration and Booting BCFG4 2 062 064 064 057 064 064 064 064 37 BCFG2 1 depends on NAND size 057 057 057 057 057 057 057 BCFGI 7 4 0b1000 060011 060011 050107 057777 060010 ObZZZZ ObZZZZ BOOT MODE 1 0 0b10 0b10 0b10 0b10 0601 0510 0601 0500 Description NAND SPI SPI SDO USB OTG SATA USB OTG eFUSE Boot Configuration Signals generated by the CMIC L 773e 2 Boot mode
43. brought out on the connector have on board resistors which are laid out for a capacitive load of max 150 pF in fast mode The following table lists the port on the phyFLEX Connector Pin Signal ST Voltage Domain Description X1A68 X I2C0 SDA 1 0 VDD 3V3 LOGIC 1200 X1A69 X 2 0 SCL 1 0 VDD 3V3 LOGIC 2 0 clock XIA7I reference REF VDD 3V3 LOGIC 1200 reference voltage voltage 2 1 X SDA 1 0 VDD 3V3 LOGIC 1201 data X2A2 X SCL 1 0 VDD 3V3 LOGIC 1201 clock X2A3 reference REF O VDD 3V3 LOGIC 1201 reference voltage URS voltage Table 20 Interface Signal Location PHYTEC Messtechnik GmbH 2013 1 773 2 49 phyFLEX i MX 6 PFL A XLI xxx 8 6 SPI Interface The Serial Peripheral Interface SPI interface is a four wire bidirectional serial bus that provides a simple and efficient method for data exchange among devices The phyFLEX provides two SPI interfaced on the phyFLEX fix connector X1 The SPI interfaces provide three respectively two chip select signals The Enhanced Configurable SPI ECSPI of the 1 6 has five separate modules ECSPD ECSPI3 ECSPI4 and ECSPI5 which support data rates of up to 20 Mbit s The interface signals of the third and fifth module ECSPI3 ECSPI5 are made available on the phyFLEX Connector This module is master slave configurable The following Description SPIO master output slave inp
44. configurations which are not suitable for the phyFLEX i MX 6 are not described in the following chapters 18 2 Overview of the phyFLEX Carrier Board Peripherals The phyFLEX Carrier Board is depicted in Figure 13 It is equipped with the components and peripherals listed in Table Table 38 Table and Table For a more detailed description of each peripheral refer to the appropriate chapter listed in the applicable table Figure 3 highlights the location of each peripheral for easy identification PHYTEC Messtechnik GmbH 2013 L 773e 2 77 phyFLEX i MX 6 PFL A XL1 xxx LAN WLAN DIDieviiecet wwan Dominira wan TIDieniiecer wean JE on D m 8 L ag m 80 B o o 6 mini PCle1e 5 Y Pans 7 66 TEHHHTHHIHE 999 BB PO E Z nea 048 igo op od 8 loo 8 m 0 88 a 8 COM 48 13 8 IE m PE LE a m STM32 S OB on O M o o olz oo um o oo ooo ID as 8985 Ei 00 18 Qooo e A n oem pear Ba a Sols HBH 000 ga mud Be
45. so Copyright 2013 PHYTEC Messtechnik GmbH D 55129 Mainz Rights including those of translation reprint broadcast photomechanical or similar reproduction and storage or processing in computer systems in whole or in part are reserved No reproduction may occur without the express written consent from PHYTEC Messtechnik GmbH NORTH AMERICA PHYTEC America LLC 203 Parfitt Way SW Suite G100 Bainbridge Island WA 98110 USA 1 800 278 9913 sales phytec com 1 800 278 9913 support phytec com 1 206 780 9135 http www phytec com L 773e_2 EUROPE Address PHYTEC Messtechnik GmbH Robert Koch Str 39 D 55129 Mainz GERMANY Ordering 49 6131 9221 32 Information sales phytec de Technical 49 6131 9221 31 Support support phytec de Fax 49 6131 9221 33 oa http www phytec de http www phytec eu 2 Edition March 2013 PHYTEC Messtechnik GmbH 2013 Contents Conventions Abbreviations and Acronyms Preface Introductio ee n e 1 1 1 Block 1 on est e E te ets 1 2 phyFLEX i MX 6 Component Placement 1 3 Minimum Requirements to operate the phyFLEX 1 MX 6 Pin 1 0 0001000 4 1 Primary System Power VDD 5V IN 4 2 Power Management IC PMIC 014 42 1 Power Domains ertt Este 4 3 Supply Voltag
46. the phyFLEX 1 MX 6 CSIO 243 rising edge strobe used for the LVDS camera signals 1 2 falling edge strobe used for the LVDS camera signals Table 9 Jumper Settings 1 Default settings are in bold blue text 26 PHYTEC Messtechnik GmbH 2013 L 773e 2 Power 4 Power The phyFLEX i MX 6 operates off of a single power supply voltage The following sections of this chapter discuss the primary power pins on the phyFLEX Connector X1 in detail 4 1 Primary System Power VDD 5V IN R The phyFLEX 1 MX 6 operates off of a primary voltage supply with a nominal value of 5 V On board switching regulators generate the 3 3 V 2 5 V 1 375 V 1 5 V 0 75 V 1 2 V and 3 V voltage supplies required by the 1 6 MCU and on board components from the primary 5 V supplied to the SOM For proper operation the phyFLEX i MX 6 must be supplied with a voltage source of 5 V 5 with 2 A load at VCC pins on the phyFLEX Connector VDD 5V INR AI A2 BI B2 Connect all 5 V VCC input pins to your power supply and at least the matching number of GND pins Corresponding GND X1 4 A10 A16 B4 B7 B13 Please refer to section 2 for information on additional GND Pins located at the phyFLEX Connector Caution As a general design rule we recommend connecting all GND pins neighboring signals which are being used in the application circuitry For maximum EMI performance all GND pins should be c
47. wake signals are realized by GPIOs Table 25 shows the position of the PCIe signals on the phyFLEX fix connector Description 20160 present signal low active PCIe0 reference voltage PCIe0 transmit lane PCle0 transmit lane 0 wake signal low active PCIe0 receive lane PCIe0 receive lane PCIe0 clock PCIe0 clock lane 53 Voltage Domain VDD 3V3 LOGIC VDD 3V3 LOGIC i MX 6 internal i MX 6 internal VDD 3V3 LOGIC i MX 6 internal 1 MX 6 internal 1 MX 6 internal 1 MX 6 internal ST 1 0 REF O PCIe PCIe 1 0 PCIe I PCIe I PCIe_O PCIe_O Signal X 0 nPRSNT reference voltage X PCIe0 X 0 TX X PCIe0 nWAKE X PCIe0 RX X 0 RX X PCIe0 CLK X 0 CLK PCIe Interface Signal Location L 773e 2 Pin X1B65 X1B66 X1B68 X1B69 X1B70 X1B71 X1B72 X1B74 X1B75 Table 25 PHYTEC Messtechnik GmbH 2013 phyFLEX i MX 6 PFL A XLI xxx 8 11 Media Local Bus The Media Local Bus MLB interface provides a link to a MOST data network using the standardized Media Local Bus protocol up to 150 Mbit s for inter chip communication The Media Local Bus interface is implemented as MediaLB 6 pin interface differential The module is backward compatible to MLB 50 The MLB interface is only available on the not standardized phyFLEX flex connector X3 Th
48. 0 V SD1 data 2 Not connected Not connected Not connected Not connected Ground 0 V Not connected Not connected Not connected Not connected Not connected Ground 0 V Not connected Pinout of the phyFLEX optional Connector X2 Row A L 773e_2 phyFLEX i MX 6 PFL A XL1 xxx Voltage Domain VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC 1 6 internal 1 6 internal 1 6 internal 1 6 internal VDD SDI VDD SDI VDD SDI VDD SDI VDD SD1 VDD SD1 VDD SD1 VDD SD1 VDD SD1 PHYTEC Messtechnik GmbH 2013 Pin Signal 2 1 2 2 X2A3 X2A4 X CANO TXD X2A5 X CANO RXD 2 7 reference voltage X2A8 X2A9 2 10 2 11 X2A12 2 13 2 14 X2AI5 X2A16 X2A17 X2A18 GND X2A19 X2A20 X2A21 X2A22 X2A23 X2A24 KEND X2A25 X2A26 N C X2A27 N C X2A28 N C X2A29 N C X2A31 N C X2A32 N C X2A33 N C X2A34 N C X2A35 N C X2A37 N C Table 5 16 Pin Description X2A38 Not connected X2A39 Not connected X2A40 VDD 3V3 LOGIC Camera0 data 2 41 VDD 3V3 LOGIC Camera0 data X2A42 Ken Ground 0 V 2 43 ONO VDD 3V3 LOGIC Camera
49. 0 master clock 2 44 oles VDD 3V3 LOGIC Camera0 reference voltage X2A45 RSVD reserved X2A46 VDD 3V3 LOGIC data X2A47 VDD 3V3 LOGIC 1 data X2A48 Ground 0 V X2A49 VDD 3V3 LOGIC master clock X2A50 VDD 3V3 LOGIC Cameral reference voltage Table 5 Pinout of the phyFLEX optional Connector X2 Row A continued Pin Signal ST Voltage Domain Description 2 1 1 6 internal HDMIO data2 TMDS X2B2 VE 0 i MX 6 internal HDMIO data2 X2B3 Ground 0 V TMDS 5 2 4 0 i MX 6 internal HDMIO datal TMDS 2 5 0 1 6 internal HDMIO datal X2B6 REF Von ava Logie DM voltage TMDS_ X2B7 0 i MX 6 internal HDMIO data0 TMDS 2 8 VUE 0 i MX 6 internal HDMIO data0 X2B9 KEND Ground 0 V TMDS 2 10 201 0 1 6 internal HDMIO clock TMDS X2B11 0 1 6 internal HDMIO clock X2B12 VDD 3V3 LOGIC HDMIO CEC X2B13 1 VDD 3V3 LOGIC 2 14 Not connected 2 15 Ground 0 V X2B16 N C Not connected Table 6 Pinout of the phyFLEX optional Connector X2 Row B 17 L 773e 2 PHYTEC Messtechnik GmbH 2013
50. 0000000000 0000000000000000000000000 OO0O0O0O000000000000000000000 OO0O00000000000000000000000 O000000000000000000000000 O0000000000000000000000000 0000000000000000000000000 O0000000000000000000000000 OO0O00000000000000000000000 O000000000000000000000000 O000000000000000000000000 O000000000000000000000000 O000000000000000000000000 000 0 un un 500 0000000000 0000000000 0000000000 0000000000 0000000000 0000000000 9000000000 o B EJ 000000000000 BHjoooooooooo jloooooooooo as ELI Qo mua Lj oro ua 00000 000000000000 e ooo Hn 00 OD oro uu gu 000000000000000000000000 590000 uu 000 010 O000000000000000000000000 OO0O00000000000000000000000 O0000000000000000000000000 O000000000000000000000000 O0000000000000000000000000 OO00000000000000000000000 nooo uu LJ 00000000 N 00006000 000 o oo 000 oo n o B ond un 000000000000
51. 000000000000 00000000 00000000 D uuu 00 00000 0 0 00000 0000000 0000 0 00000 0000000 a 5 ge om an 00 Figure 6 Jumper Locations top view 24 PHYTEC Messtechnik GmbH 2013 L 773e 2 Jumpers phyFLEX flex 00 000 UD 00030 ao 05 0 002 0 cto 05 OOO oto 05080 go opao ongo ua 00 ua on un aa a B un Un Un 00 a 0000000 00 00 0 0600 00000 0 000000 0000000 0000000 0000100 a B un CLO o a im p n 0 0 nagar Tra nen ow oo 000 0 0 0 0 o
52. 1 L D A PHYTEC part number lead free 0 Please refer to the corresponding data sheets and mechanical specifications provided Samtec www samtec com PHYTEC Messtechnik GmbH 2013 1 773 2 71 phyFLEX i MX 6 PFL A XLI xxx 17 Hints for Integrating and Handling the phyFLEX i MX 6 17 1 Integrating the phyFLEX i MX 6 Besides this hardware manual much information is available to facilitate the integration of the phyFLEX 1 MX 6 into customer applications the design of the standard phyFLEX Carrier Board can be used as a reference for any customer application many answers to common questions can be found at http www phytec de de support faq faq phyFLEX i MX 6 html http www phytec eu europe support faq faq phyFLEX i MX 6 html the link Carrier Board within the category Dimensional Drawing leads to the layout data as shown in Figure 12 It is available in different file formats Use of this data allows to integrate the phyFLEX 1 MX 6 SOM as a single component into your design different support packages are available to support you in all stages of your embedded development Please visit http www phytec de de support support pakete html or http www phytec eu europe support support packages html or contact our sales team for more details PHYTEC Messtechnik GmbH 2013 L 773e 2 l PA 72 Hints for Integrating and Handling m arata Cic DE
53. 3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC 2V 5 3V L 773e 2 I LVDS O LVDS O MLB I O MLB I O I MLB I O MLB I O LVDS I 0 LVDS I 0 1 0 1 0 1 1 11 0 1 0 PWR I PWR I X EIM OE X EIM BCLK X DA13 X DA14 X 5 X_CLK2 P X 2 N X GPIO 16 X D22 D X KEY COLI X KEY ROWI PMIC VBBAT VDD MX6 SNVS X3B12 X3B13 X3B14 X3BI5 X3B16 X3B17 X3B18 X3B19 X3B20 X3B21 X3B22 X3B23 X3B24 X3B25 X3B26 X3B27 X3B28 X3B29 X3B30 X3B31 X3B32 X3B33 X3B34 X3B35 X3B36 X3B37 X3B38 X3B39 X3B40 X3B41 X3B42 X3B43 X3B44 X3B45 X3B46 Table 8 PHYTEC Messtechnik GmbH 2013 DIO display clock DIO pin4 DISPO data6 DISPO data7 Ground 0 V DISPO datal0 DISPO datal 1 DISPO data12 DISPO datal5 DISPO data20 Ground 0 V DISPO data21 DISPO data22 DISPO data23 phyFLEX i MX 6 PFL A XLI xxx VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC 0 0 0 X DIO DISP CLK X DIO 4 X DISPO DAT6 X DISPO DAT7 X DISPO DATIO X DISPO X DISPO DATI2 X 21520 5 X DISPO DAT20 X 21520 1 X DISPO DAT22 X D
54. 5 Caution Please see the datasheet of the Ethernet PHY when designing the Ethernet transformer circuitry 8 4 2 Software Reset of the Ethernet Controller The Ethernet PHY at U11 can be reset by software The reset input of the Ethernet PHY is permanently connected to Pad D23 GPIO3_ 23 of the 1 MX 6 48 PHYTEC Messtechnik GmbH 2013 L 773e 2 Serial Interfaces 8 4 3 Address In a computer network such as a local area network LAN the MAC Media Access Control address is a unique computer hardware number For a connection to the Internet a table is used to convert the assigned IP number to the hardware s MAC address In order to guarantee that the MAC address is unique all addresses are managed in a central location PHYTEC has acquired a pool of MAC addresses The MAC address of the phyFLEX 1 MX 6 is located on the bar code sticker attached to the module This number is a 12 digit HEX value 8 5 Interface The Inter Integrated Circuit interface is a two wire bidirectional serial bus that provides a simple and efficient method for data exchange among devices The i MX 6 contains three identical and independent multimaster fast mode modules The interface of the second and third module I2C2 and I2C3 are available on the phyFLEX Connectors The first module connects to the on board EEPROM refer to section 6 3 and to the EMIC at 1 19 see section 15 Both I2C interfaces which are
55. 73 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board 18 3 6 USB Host Connectivity X45 X65 X66 59 4 8 Figure 24 Components supporting the USB Host Interface The USB host interface of the phyFLEX is accessible via the USB hub controller U33 on the carrier board The controller supports control of input USB devices such as keyboard mouse or USB key The USB hub has 4 downstream facing ports Two ports extend to standard USB connectors at X45 dual USB A and Ethernet These interfaces are compliant with USB revision 3 0 The remaining ports are accessible at the display data connector X65 and the mini PCIe Connector X66 These two interfaces provide only the data lines D and D They do not feature a supply line Vbus Please note that the USB interfaces of the phyFLEX i MX 6 Module are only compliant to USB 2 0 Because of that USB 3 0 devices attached to X45 will not operate at their maximum transmission rate PHYTEC Messtechnik GmbH 2013 1 773 2 99 6 PFL A XLI xxx LEDs D93 to D96 signal the USB hub s upstream port status The following table shows the function of the LED Color Description D93 green High speed indicator LED for USB hub s upstream port connection speed D94 green Super speed indicator LED for USB hub s upstream port connection spe
56. Board Support Packages BSPs and Design Services for our hardware will further reduce your development time and risk and allow you to focus on your product expertise Take advantage of PHYTEC products to shorten time to market reduce development costs and avoid substantial design issues and risks With this new innovative full system solution you will be able to bring your new ideas to market in the most timely and cost efficient manner For more information go to http www phytec de de leistungen entwicklungsunterstuetzung html or www phytec eu europe oem integration evaluation start up html Ordering Information The part numbering of the phyFLEX has the following structure PFL A xx xxxxxx A2 Generation A First Generation B Second Generation Product number consecutive Assembly options depending on model Version number In order to receive product specific information on changes and updates in the best way also in the future we recommend to register at http www phytec de de support registrierung html or http www phytec eu europe support registration html xli PHYTEC Messtechnik GmbH 2013 1 773 2 Preface For technical support and additional information concerning your product please visit the support section of our web site which provides product specific information such 35 errata sheets application notes FAQs etc http www phytec de de support faq faq phy FLEX 1 MX6 html h
57. D 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC L 773e 2 Signal VDD 5V IN R VDD 5V IN R VDD 5V IN R GND GND X UARTI TxD TTL X UARTI RxD TTL X UART RTS TTL X UART CTS TTL GND reference voltage X SPIO MOSI X 8 0 MISO X SPIO CSBOOT X SPIO CSO X SPIO CSI reference voltage X SPIO CLK Pin 1 1 1 2 X1A3 4 X1A5 X1A6 X1A7 X1A8 X1A9 X1A10 X1A11 X1A12 X1A13 14 15 X1A16 17 X1A18 X1A19 X1A20 X1A21 X1A22 X1A23 X1A24 X1A25 X1A26 X1A27 X1A28 X1A29 Table 3 PHYTEC Messtechnik GmbH 2013 5211 chip select 0 5211 master output slave input 5211 master input slave output SPII reference voltage Ground 0 V SPII clock signal SPII chip select 1 11580 VBUS enable active low USBO VBUS input USBO overcurrent input Ground 0 V USBO reference voltage USBO charger detection 11581 VBUS enable active low USBI VBUS input USB1 overcurrent input Ground 0 V USB1 reference voltage 2 receive clock T S receive frame 125 receive data IS reference voltage Ground 0 V T S transmit data General purpose input output 0 General purpose input output 1 General purpose input output 2 GPIO reference voltage Groun
58. DD MX6 SOC i MX6SOC VDDSOC IN 1 375 V VDD MX6 HIGH 1 6 internal regulator 3 0 V VDDHIGH IN VDD MX6 SNVS iMX 6 backup supply VDD SNVS IN 3 0 V VDD ETH IO 1 6 supply 2 5 NVCC Ethernet PHY RGMII IO supply VDD ETH 1V2 Ethernet PHY core voltage 1 2 V derived from 5V_IN_R via current sense amplifier at U16 PHYTEC Messtechnik GmbH 2013 1 773 2 29 phyFLEX i MX 6 PFL A XLI xxx i MX6 03 supply SD3 i MX6 SD2 supply SD2 CMIC supply PMIC IO supply i MX 6 DDR NVCC DRAM RAM devices RAM devices termination voltage i MX 6 DDR3 reference voltage DRAM VREF RAM devices reference voltage 1 pad supply NVCC JTAG NVCC LCD NVCC CSI NVCC EIM NVCC GPIO I2C EEPROM SPI Flash NAND Flash Camera Deserializer Ethernet PHY EMIC PHYTEC Messtechnik GmbH 2013 L 773e 2 VDD SD0 3 3 V VDD SD1 3 3 V VDD PM 3 3 V VDD 3V3 PMIC IO 3 3 V VDD DDR3 1 5 1 5 V DDR3 VTT 0 75 V DDR3 VREF 0 75 V VDD 3V3 LOGIC 3 3 V Power VDD 5V IN R Current Sense IC VDD 5V IN 3 3V LDO VDD PM VDD MX6 ARM VDD MX6 SOC DDR3 VTT VDD DDR3 1V5 DDR3 LDO DDR3 VREF VDD_3V3 VDD_3V3_LOGIC SWITCH PERI SWG VDD ETH 1V2 o amp 2 o E o m z 0 DA9063 VDD ETH IO VDD MX6 SNVS
59. Display 2 1 R7 B2 VSYNC Bl 1 1 02 B3 DE 0 Pixel Mapping of 24 bit LVDS Display Interface PHYTEC Messtechnik GmbH 2013 CLK AO Al A2 A3 Table 33 64 LVDS Display Interface 13 High Definition Multimedia Interface HDMI The High Definition Multimedia Interface HDMI of the phyFLEX i MX 6 is compliant to HDMI 1 4 and DVI 1 0 It supports a maximum pixel clock of up to 340 MHz for up to 720p at 100 Hz and 7201 at 200 Hz or 1080 at 60 Hz and 10801 7201 at 120 Hz HDTV display resolutions and a graphic display resolution of up to 2048x1536 QXGA Please refer to the i MX Reference Manual for more information The following table shows the location of the HDMI signals on the phyFLEX optional connector X2 Pin Signal ST Voltage Domain Description X2A8 X HDMIO SDA VO VDD 3V3 LOGIC PA HC X2A9 X HDMIO SCL VO VDD 3V3 LOGIC TEA ES X2B1 X TMDS DATA2 TMDS i MX 6 internal Bid X2B2 X TMDS DATA2 TMDS i MX 6 internal Brod X2B4 X TMDS DATAI TMDS i MX 6 internal 0 X2B5 X TMDS DATAI TMDS 1 6 internal 2 HDMIO X2B6 reference voltage REF O VDD 3V3 LOGIC reference voltage X2B7 X TMDS DATAO TMDS i MX 6 internal 2 X2B8 X TMDS DATAO TMDS 1 6 internal X2B10 X TMDS CLOCK TMDS i MX 6 internal 22 X2B11
60. EC Messtechnik GmbH 2013 X3A36 KEND 3 60 Table 7 ST LVDS O LVDS O Pin Signal LVDS O LVDS O LVDS O LVDS O LVDS LVDS O Table 8 20 Pin Description CSIO data4 LVDSI clock LVDSI clock Ground 0 V Media local bus data line Media local bus data line CSIO data5 Media local bus signal line Media local bus signal line Ground 0 V Media local bus clock Media local bus clock CSIO data9 EIM load burst address EIM Read write Ground 0 V CSIO data8 EIM output enable EIM burst clock EIM address data13 EIM address data14 Ground 0 V EIM address data15 Differential clock2 Differential clock2 GPIO16 EIM data22 Ground 0 V 0510 7 0510 6 Keypad column1 Keypad rowl PMIC Backup power supply Ground 0 V 1 MX6 Backup power supply normally generated by PMIC Pinout of the phyFLEX flex Connector X3 Row B continued 21 VDD 3V3 LOGIC 1 6 internal 1 6 internal 1 MX 6 internal 1 MX 6 internal VDD 3V3 LOGIC 1 MX 6 internal 1 MX 6 internal 1 MX 6 internal 1 MX 6 internal VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC 1 MX 6 internal 1 MX 6 internal VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V
61. GIC X GPIOI 10 VDD 3V3 LOGIC X GPIO2 10 VDD 3V3 LOGIC reference vpp 3 3 LOGIC voltage 2 uiu X GPIO3 VDD 3V3 LOGIC X GPIO4 0 VDD 3V3 LOGIC X GPIOS 10 VDD 3V3 LOGIC X GPIO6 0 VDD 3V3 LOGIC Location of GPIO Pins L 773e 2 Pin 4 X1A54 X1A55 X1A56 X1A57 X1A59 X1A60 X1A61 X1A62 Table 27 PHYTEC Messtechnik GmbH 2013 phyFLEX i MX 6 PFL A XLI xxx Pin Signal ST Voltage Domain Description General purpose X1A63 X GPIO7 I O VDD 3V3 LOGIC input output 7 GPIO7 13 of i MX 6 General purpose X1A65 X 8 I O VDD 3V3 LOGIC input output 8 4 5 of i MX 6 General purpose X1A66 X 9 I O VDD 3V3 LOGIC input output 9 GPIO2 23 of i MX 6 General purpose X1A67 X GPIOIO I O VDD 3V3 LOGIC input output 10 GPIO2 24 of i MX 6 Table 27 Location of GPIO Pins continued Beside these 11 dedicated GPIOs most of the 1 6 signals which are connected directly to the module connector can be configured to act as GPIOs due to the multiplexing functionality of most controller pins 56 PHYTEC Messtechnik GmbH 2013 1 773 2 General Purpose I O 10 User LEDs The phyFLEX 1 MX 6 provides two user LEDs on board a red D2 and a green D1 D2 can be controlled by setting GPIO2 31 pad and can by controlled by setting 30 pad
62. I clock positive output Cl NC Not connected C2 NC Not connected C3 NC Not connected C4 NC Not connected C5 NC Not connected 51 Shield Shield 52 Shield Shield S3 NC Not connected 54 NC Not connected S5 Shield Shield Table 51 HDMI DVI Connector X40 Pinout continued PHYTEC Messtechnik GmbH 2013 1 773 2 109 phyFLEX i MX 6 PFL A XLI xxx 18 3 10 Camera Interface X63 X64 Figure 27 Camera Interface at Connector X63 The phyFLEX i MX 6 has two camera interfaces This interfaces extend from the phyFLEX Connector to the RJ45 sockets X63 and X64 on the carrier board The camera interfaces are compatible with the PHYTEC phyCAM S camera interface standard The table below shows the pinout of connector X63 Pinf Signal Name Description 1 0 10 LVDS Input 2 0 1 0 LVDS Input 3 Camera RXCLK LVDS Clock 4 SDA CAMERA Data 5 DC SCL CAMERA Clock 6 0 RXCLK LVDS Clock 7 VCC_CAMERAO Power supply camera 3 3 V 8 GND Ground Table 52 PHYTEC Camera Connector X63 110 PHYTEC Messtechnik GmbH 2013 L 773e 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board The following table shows the pinout of connector X64 Pin Signal N
63. I2C_SDA_ CAMERA pin 5 I2C SCL CAMERA derived from 12 1 Display data connector X65 pin B8 2 0 SDA pin B7 2 SCL Table 54 Connectivity To avoid any conflicts when connecting external 150 devices to the phyFLEX Carrier Board the addresses of the on board devices must be considered On the carrier board only 12 0 is used for the different devices is reserved for camera interfaces Some of the addresses can be configured by jumper Table 55 hsts the addresses already in use The table shows only the default address Please refer to section 18 2 4 for alternative address settings Device Address used 12 0 Jumper 7 MSB RTC U28 0x51 A D converter U7 0x64 Touch screen controller 06 0x41 Switchable to J12 0x44 Audio Controller U25 0x18 LED dimmer U52 0x62 Table 55 PCO Addresses in Use 114 PHYTEC Messtechnik GmbH 2013 1 773 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board 18 3 13 SPI Connectivity The carrier board supports connectivity to both SPI Interfaces of the phyFLEX Module The SPIO interface is available at the display data connector X65 Wi Fi Bluetooth connector X58 and the SPIO pin header connector X53 SPIO supports 3 slave select signals SPIO CSO is reserved to address the SPI Flash on the module and is not available on the carrier board Connector Location PDI data connector pin
64. IO7 10 IO 3 3 V GPIO8 11 LO 3 3 V GPIO9 12 LO 3 3V GPIO10 13 GND Ground 14 GND Ground Table 59 GPIO Pin Header X54 Pinout 116 PHYTEC Messtechnik GmbH 2013 1 773 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board GPIO Function GPIOO Interrupt Touch Controller at U6 GPIOS If JP1 is connected between pin 2 and 3 signal RTC INT is connected to GPIOS GPIO6 SPI IRQ at LCD Connector X65 pin B5 GPIOIO Connected to User LED D105 Table 60 GPIO Function Description 18 3 15 User programmable LEDs The phyFLEX Carrier Board provides 5 user programmable LEDs LED D105 is directly connected to GPIO10 of the phyFLEX 1 MX 6 X1A67 A logic 1 at GPIOIO turns the LED on The other user programmable LEDs D86 D97 D99 are controlled by a 4 bit LED dimmer at U52 which is connected to 1200 at adress 0x62 PHYTEC Messtechnik GmbH 2013 1 773 2 117 6 PFL A XLI xxx 18 3 16 Secure Digital Memory Card MultiMedia Card X57 X56 0 00000000 00000000 Figure 29 SD MM Card interfaces at connector X57 and X56 The phyFLEX Carrier Board provides two standard SDHC card slots at X57 and X56 for connection to SD MM cards It allows easy and convenient connection to peripheral devices like SD and MM cards Power to the SD interface is supp
65. ISPO DAT23 Pinout of the phyFLEX flex Connector X3 Row B continued X3B47 X3B48 X3B49 X3B50 X3B51 3 52 X3B53 X3B54 X3B55 X3B56 X3B57 X3B58 X3B59 X3B60 Table 8 Caution Signals on the phyFLEX optional connector X3 are module specific This connector has only fixed Ground signals All other signals of the phyFLEX flex connector depend on the features of the controller populating the SOM L 773e_2 PHYTEC Messtechnik GmbH 2013 22 Jumpers 3 Jumpers For configuration purposes the phyFLEX 1 MX 6 has several solder jumpers some of which have been installed prior to delivery Figure 5 illustrates the numbering of the solder jumper pads while Figure 6 and Figure 7 indicate the location of the solder jumpers on the board Table 9 below provides a functional summary of the solder jumpers which can be changed to adapt the phyFLEX 1 MX 6 to your needs It shows their default positions and possible alternative positions and functions A detailed description of each solder jumper can be found in the applicable chapter listed in the table Note Jumpers not listed should not be changed as they are installed with regard to the configuration of the phyFLEX i MX 6 closed 1 1 IE 1 E gm 2 2 5 e g 3 e g 3 e g 5 Figure 5 Typical Jumper Pad Numbering Scheme If manual jumper modification is required please ensure that the board as w
66. JTAG TDO 3 3V JTAG Test Data Output 15 nRESET_IN I 3 3V System Reset 17 n c 19 n c Table 67 JTAG Connector X4 PHYTEC Messtechnik GmbH 2013 1 773 2 127 phyFLEX i MX 6 PFL A XLI xxx 18 3 24 RTC at 028 Figure 32 RTC with Battery Buffer For real time or time driven applications the phyFLEX Carrier Board is equipped with an RTC 8564 Real Time Clock at U28 This RTC device provides the following features Serial input output bus I C address 0x51 7 MSB e Power consumption Bus active 400 kHz gt 1 mA Bus inactive CLKOUT inactive 275 nA e Clock function with four year calendar e Century bit for year 2000 compliance Universal timer with alarm and overflow indication e 24 hour format e Automatic word address incrementing e Programmable alarm timer and interrupt functions 128 PHYTEC Messtechnik GmbH 2013 1 773 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board The Real Time Clock is programmed via the bus address 0x51 Since the phyFLEX 1 MX 6 is equipped with an internal controller the protocol is processed very effectively without extensive processor action refer also to section 8 5 The Real Time Clock also provides an interrupt output that extends to jumper JP1 Jumper JP1 allows to connect the RTC interrupt to the Power ON Wake Off
67. LEX i MX 6 System on Module Types of Signals Different types of signals are brought out at the phyFLEX Connector The following table lists the abbreviations used to specify the type ofa signal Abbr PWR I REF O I 0 1 0 IPU OC BI OC 5V PD LVDS I LVDS O LVDS TMDS O USB I O 1227883 Description Supply voltage input Reference voltage output Digital input Digital output Bidirectional input output Digital input with pull up must only be connected to GND jumper or open collector output Open collector input output with pull up Open collector output without pull up requires an external pull up 5 V tolerant input with pull down Differential line pairs 100 Ohm LVDS level input Differential line pairs 100 Ohm LVDS level output Differential line pairs 100 Ohm LVDS level bidirectional input output Differential line pairs 100 Ohm TMDS level output Differential line pairs 90 Ohm USB level bidirectional input output PHYTEC Messtechnik GmbH 2013 Signal Type Power Ref Voltage Input Output IO IPU OC Bidir PU OC Output 5V Input PD LVDS Input LVDS Output LVDS IO TMDS Output USB IO viii Conventions Abbreviations and Acronyms ETHERNET Differential line pairs 100 Ohm ETH I Input Ethernet level input ETHERNET Differential line pairs 100 Ohm ETH Output Ethernet level onput ETHE
68. NAND Flash Memory U13 Use of Flash as non volatile memory on the phyFLEX i MX 6 provides an easily reprogrammable means of code storage The following Flash devices can be used on the phyFLEX 1 MX 6 The Flash devices are programmable with 3 3 V No dedicated programming voltage is required As of the printing of this manual these NAND Flash devices generally have a life expectancy of at least 100 000 erase program cycles and a data retention rate of 10 years The NAND Flash memories are connected to the External Interface Module EIM CS0 NANDF C50 of the EIM interface selects the NAND Flash at U13 6 3 PC EEPROM 010 The phyFLEX i MX 6 is populated with a non volatile 4 kB EEPROM with an PC interface at U10 This memory can be used to store configuration data or other general purpose data This device 5 accessed through port 1 the 1 6 The control registers for PC port 1 are mapped between addresses 0x021A 0000 and 0x021A 3FFF Please see the iMX6 Reference Manual for detailed information on the registers The three lower address bits are fixed to zero which means that the EEPROM can be accessed at address 0x50 Write protection to the device is accomplished via jumper J3 Refer to section 6 3 1 for further details See the manufacturer s data sheet for interfacing and operation PHYTEC Messtechnik GmbH 2013 1 773 2 39 phyFLEX i MX 6 PFL A XLI xxx 6 3 1 EEPROM Write Protecti
69. O 3 3 V EIM address data7 BCFGI 7 X3A53 X EIM 3 3 V EIM address data8 BCFG2 0 55 EIM DA9 3 3 V EIM address data9 BCFG2 1 X3A56 X EIM DAIO I O 3 3 V EIM address datalO BCFG2 2 Table 12 Boot Configuration Pins at phyFLEX flex Connector X3 35 L 773e 2 PHYTEC Messtechnik GmbH 2013 6 PFL A XLI xxx Pin Signal SL Description Configuration Pin X3A57 X_EIM 1 0 3 3 V EIM address datall BCFG2 3 X3A58 X EIM 12 1 3 3 V EIM address datal2 BCFG2 4 59 X A16 JO 33V EIM address16 BCFG3 0 X3B25 X EIM LBA JO 33V EIM load burst address BCFG4 2 X3B26 X RW 13 3 V EIM Read write BCFG4 5 X3B31 X DAI3 1 3 3 V EIM address datal3 BCFG2 5 X3B32 X DAI4 1 3 3 V EIM address datal4 BCFG2 6 X3B34 X DAI5 1 3 3 V EIM address datal5 BCFG2 7 Table 12 Boot Configuration Pins at phyFLEX flex Connector continued By setting the desired boot mode with the phyFLEX boot configuration pins BOOT 2 0 the CMIC which is populated on the module sets some of the appropriate BCFG pins and the BOOT MODE 1 0 pins of 1 6 controller Only BCFG1 7 4 BCFG2 1 BCFG4 2 and BOOT _MODE 1 0 can be set by the CMIC All other BCFG pins are set to a fixed value by 10 configuration resistors which
70. PFL A XLI xxx General Purpose UOS 0100100010 55 User LEDs 001 57 Debug Interface X1 1 000000101021 58 LVDS Display Interface 000101010101010 62 12 1 LVDS Display Interface pixel mapping 63 High Definition Multimedia Interface HDMIL 65 LVDS Camera Interface 0001010101010 66 14 1 Signal Configuration J9 and J31 67 Environment Management IC EMIC U19 68 Technical Specifications 5 2 1 1 1 1 1 1 1 1 1 1 eoo 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 2 2 2 69 Hints for Integrating and Handling the phyFLEX i MX 6 72 17 1 Integrating the phyFLEX 1 MX 72 17 2 Handling the 1 entm etie eee 74 phyFLEX i MX 6 on the phyFLEX Carrier Board 75 18 1 Concept of the phyFLEX Carrier 76 18 2 Overview of the phyFLEX Carrier Board Peripherals 77 18 2 1 Connectors and Pin 79 18 22 S WICE Ste 81 E E 82 8 24 1 1 1 1 1 1 1 1 1 1 0 1 000000000 84 18 3 Functional Components on the phyFLEX Carrier Board 88 18 3 1 phyFLEX i MX 6 SOM Connectivity X2 88 18 3 2 0 0 0000006 89 18 3 2 1 Wall Adapter Input 12 9 18 3 2 2 Power over Ethernet P
71. Power Management plug connector X22 To enter the different power states signal Power ON Wake OFF must be active low for different times as described in the text above 94 PHYTEC Messtechnik GmbH 2013 1 773 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board 18 3 3 RS 232 Connectivity X51 X50 _ Figure 19 RS 232 Interface Connectors X50 and X51 Connectors X50 and X51 are DB9 sub connectors and provide connection interfaces to UARTO X51 and UARTI X50 of the phyFLEX i MX 6 UART4 and UART3 of the 1 6 Two RS 232 transceivers U10 U11 on the carrier board convert the TTL level signals from the phyFLEX i MX 6 RS 232 level signals The serial interface UARTI allows for a 5 wire connection including the signals RTS and CTS for hardware flow control UARTO provides only signals TX and RX Figure 20 and Figure 21 below show the signal mapping of the RS 232 level signals at connectors X50 and X51 The RS 232 interface at connector X51 UARTO is hard wired and no jumpers must be configured for proper operation PHYTEC Messtechnik GmbH 2013 1 773 2 95 phyFLEX i MX 6 PFL A XLI xxx To use the RS 232 interface UARTI at X50 jumpers J27 to J30 on the backside of the carrier board must be set to 1 2 1 6 2 Pin 2 TxD RS232 3 Pin 7 RTS RS232 3 8 Pin 3 RxD RS232 4 Pin 8 CTS RS232 9 5 Pin 5 GND Figure 20 RS 232 Connector X50 Signal Mapping UARTI 1 6 2 Pin 2 T
72. RNET Differential line pairs 100 Ohm IO Ethernet level bidirectional input output PCIe Input Differential line pairs 100 Ohm PCIe PCIe I level input PCIe Output Differential line pairs 100 Ohm PCIe PCIe level output MLB Output Differential line pairs 100 Ohm Media MLB O local bus output MLB IO Differential line pairs 100 Ohm Media MLB I O local bus bidirectional input output 51 2 Differential line pairs 100 Ohm CSI 2 I Input CSI 2 level input Table 1 Signal Types used in this Manual Abbreviations and Acronyms Many acronyms and abbreviations are used throughout this manual Use the table below to navigate unfamiliar terms used in this document Abbreviation Definition BSP Board Support Package Software delivered with the Development Kit including an operating system Windows or Linux preinstalled on the module and Development Tools CB Carrier Board used in reference to the phyFLEX Development Kit Carrier Board DFF D flip flop EMB External memory bus EMI Electromagnetic Interference GPI General purpose input GPIO General purpose input and output GPO General purpose output PHYTEC Messtechnik GmbH 2013 L 773e 2 1X phyFLEX i MX 6 PFL A XLI xxx IRAM Internal RAM the internal static RAM on the Freescale Semiconductor i MX 6 microcontroller J Solder jumper these ty
73. Signal or to the GPIO5 of the phyFLEX i MX 6 An interrupt occurs in the event of a clock alarm timer alarm timer overflow and event counter alarm It has to be cleared software With the interrupt function the Real Time Clock can be utilized in various applications Position Description 1 2 RTC Interrupt connected to Power ON Wake Off 2 3 RTC Interrupt connected to 5 Table 68 Interrupt Configuration JP 1 After connection of the supply voltage the Real Time Clock generates no interrupt The RTC must be first initialized see RTC Data Sheet for more information Use of a coin cell at BAT1 allows to buffer the RTC 4 connected to GPIO 9 pin T2 of the i MX 6 on the phyFLEX i MX 6 PHYTEC Messtechnik GmbH 2013 1 773 2 129 phyFLEX i MX 6 PFL A XLI xxx 130 PHYTEC Messtechnik GmbH 2013 1 773 2 Revision History 19 Revision History o in this manual 25 09 2012 First draft Preliminary documentation L 773e 0 Describes the phyFLEX 1 MX 6 with phyFLEX Carrier Board 07 12 2012 Manual First Edition appropriate for the 2 L 773e 1 PCB of the carrier board 15 03 2013 Manual Second Edition information updated L 773e_2 for the 1 PCB of the phyFLEX i MX 6 and the 3 PCB of the carrier board PHYTEC Messtechnik GmbH 2013 1 773 2 131 phyFLEX i MX 6 PFL A XLI xxx 132 PHYTEC Messtechnik GmbH 2013 1 773 2 Index 133
74. VDD 3V3 LOGIC CANO receive CANO reference voltage X2A7 reference voltage REF VDD 3V3 LOGIC Table 23 CAN Interface Signal Location 8 9 SATA Interface The SATA II interface of the phyFLEX 1 MX 6 is a high speed serialized ATA data link interface compliant with SATA Revision 3 0 physical layer complies with SATA Revision 2 5 which supports data rates of up to 3 0 Gbit s The interface includes an internal DMA engine command layer transport layer link layer and the physical layer The interface itself supports only one SATA device The phyFLEX 1 MX 6 provides an SATA II Interface at the phyFLEX optional connector X2 at the following locations Pin Signal ST Voltage Domain Description 2 10 SATAO TX LVDS 1 6 internal SATAO transmit X2A11 X SATAO TX LVDS 1 6 SATAO transmit lane 2 13 SATAO RX LVDS I 1 6 internal SATAO receive lane X2A14 X SATAO RX LVDS 1 6 internal SATAO receive lane Table 24 SATA Interface Signal Location 52 PHYTEC Messtechnik GmbH 2013 1 773 2 Serial Interfaces 8 10 PCI Express Interface The 1 lane PCI Express interface of the phyFLEX 1 MX 6 provides PCle Gen 2 0 functionality which supports 5 Gbit s operation Furthermore the interface is fully backwards compatible to the 2 5 Gbit s Gen 1 1 specification The present and the
75. Xs e Switch to configure the boot order of the 1 6 e Full featured 4 line RS 232 transceiver supporting data rates of up to 1 Mbps hardware handshake and RS 232 connector Second 2 line RS 232 transceiver supporting data rates of up to 1 Mbps e High Integrated and isolated CAN interface e USB 3 0 Hub with 4 downstream ports available at different Connectors the 1 6 supports only USB 2 0 e USB OTG interface PHYTEC Messtechnik GmbH 2013 1 773 2 75 6 PFL A XLI xxx e 10 100 1000 Mbps Ethernet interfaces e Support of two buses from the SOM available at different connectors on the carrier board Connectivity to two SPI interfaces from the phyFLEX Module Complete audio interface available at four 3 5 mm audio jacks speaker connector e DVI interface e PHYTEC Display Interface PDI LVDS display with separate connectors for data lines and display backlight supply voltage e Circuitry to allow dimming of a backlight e Touchscreen interface for use of 4 wire resistive touch screens e Two LVDS camera interfaces compatible to PHYTEC phyCAM S camera standard with for camera control e Two Secure Digital Card Multi Media Card Interfaces e PHYTEC Wi Fi Bluetooth Connector DIP Switch to configure the boot options for the phyFLEX 1 MX 6 module mounted RTC with battery supply backup SATA Power and Data Connector PCIe Port Five user programmable LEDs Pin header c
76. al PHYTEC Messtechnik GmbH 2013 L 773e 2 70 Technical Specifications Connectors on the phyFLEX i MX 6 Manufacturer Samtec phyFLEX fix X1 Number of pins per contact rows 160 pins 2 rows of 80 pins each Samtec part number lead free BSH 080 01 L D A K TR phyFLEX optional X2 Number of pins per contact rows 100 pins 2 rows of 50 pins each Samtec part number lead free BSH 050 01 L D A K TR phyFLEX flex X3 Number of pins per contact rows 120 pins 2 rows of 60 pins each Samtec part number lead free BSH 060 01 L D A The following list shows the receptacle sockets that correspond to the connectors populating the underside of the phyFLEX 1 MX 6 The given connector height indicates the distance between the two connected PCBs when the module is mounted on the corresponding carrier board In order to get the exact spacing the maximum component height 3 mm on the bottom side of the phyFLEX must be subtracted Connector height 5 mm Manufacturer Samtec Number of pins per contact row 160 pins 2 rows of 80 pins each Samtec part number lead free ASP 167037 01 BTH 080 01 L D A K TR PHYTEC part number lead free VM245 Number of pins per contact row 100 pins 2 rows of 50 pins each Samtec part number lead free BTH 050 01 L D A K TR PHYTEC part number lead free 7 Number of pins per contact row 120 pins 2 rows of 60 pins each Samtec part number lead free BTH 060 0
77. ame Description 1 Cameral 10 LVDS Input 2 Cameral L0 LVDS Input 3 0 RXCLK LVDS Clock 4 SDA CAMERA Data 5 SCL CAMERA Clock 6 Cameral RXCLK LVDS Clock 7 VCC CAMERAI Power supply camera 3 3 V 8 GND Ground Table 53 PHYTEC Camera Connector X64 PHYTEC Messtechnik GmbH 2013 1 773 2 111 6 PFL A XLI xxx 18 3 11 Audio Interface X7 X8 X9 X10 X11 B 1 1 1 oxo i o a Li L1 T T fF 7 Figure 28 Audio Interface at Connectors X7 X6 X9 X10 X11 The audio interface provides a method of exploring the phyFLEX i MX 6 PS capabilities The phyFLEX Carrier Board is populated with a low power stereo audio codec with integrated mono class d amplifier at U25 It provides a High Performance Audio DAC and ADC with sample rates from 8 kHz to 96 kHz It supports a stereo line input stereo microphone input stereo line output stereo headphone output and direct speaker output The audio codec is interfaced to the phyFLEX 1 MX 6 via PS interface for audio data and the interface for codec configuration PC address 0x18 Audio devices can be connected to 3 5 mm audio jacks at X8 X9 X10 and X11 A detailed list of applicable connectors 112 PHYTEC Messtechnik GmbH 2013 1 773 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board is p
78. and Intel AC 97 standard The 1 MX 6 provides three instances of the SSI module On the phyFLEX i MX 6 5515 is brought out to the phyFLEX Connector With reference to the phyFLEX specification the main purpose of this interface is to connect to an external codec such as Four signals extend from the 1 6 SSI module to the phyFLEX Connector 1250 1250 I2S0_ADC 1250 DAC Signal ST Voltage Domain Description X1A48 X 1250 1 0 VDD 3V3 LOGIC 18 clock 1 49 X 1250 FRM 1 0 VDD 3V3 LOGIC 175 frame 1 50 X 1250 ADC I VDD 3V3 LOGIC I S receive data 1 51 reference voltage REF VDD 3V3 LOGIC I S reference voltage X1A53 X 1250 DAC 0 VDD 3V3 LOGIC I S transmit data Table 22 PS Interface Signal Location PHYTEC Messtechnik GmbH 2013 1 773 2 51 phyFLEX i MX 6 PFL A XLI xxx 8 8 CAN Interface The CAN interface of the phyFLEX 1i MX 6 is connected to the first FlexCAN module FlexCAN1 of the i MX 6 which is a full implementation of the CAN protocol specification Version 2 0B It supports standard and extended message frames and programmable bit rates of up to 1 Mb s The signals of the CAN interface are brought out on the phyFLEX optional connector X2 The following table shows the position of the signals Pin Signal ST Voltage Domain Description X2A4 X CANO TXD O VDD 3V3 LOGIC transmit X2A5 X CANO RXD I
79. at U19 gives the possibility to detect monitor and record particular physical parameter such as current consumption temperature und voltages Furthermore the Environment Management IC comes with a PWM output and a tacho input for fan controlling and an Management bus 68 PHYTEC Messtechnik GmbH 2013 1 773 2 Technical Specifications 16 Technical Specifications The physical dimensions of the phyFLEX i MX 6 are represented in Figure 11 The module s profile is max 10mm thick with a maximum component height of 3 0 mm on the bottom connector side of the PCB and approximately 5 0mm the top microcontroller side The board itself is approximately 1 4 mm thick 3mm 60mm 8mm 44mm phyFLEX i MX 6 70mm Figure 11 Physical Dimensions top view PHYTEC Messtechnik GmbH 2013 1 773 2 69 phyFLEX i MX 6 PFL A XLI xxx Note To facilitate the integration of the phyFLEX 1 MX 6 into your design the footprint of the phyFLEX i MX 6 is available for download see 60 mm x 70 mm TBD 40 C to 125 C 0 to 70 C commercial 40 C to 85 C industrial 95 r F not condensed 5 V 5 TBD section 17 1 Additional specifications Dimensions Weight Storage temperature Operating temperature Humidity Operating voltage Power consumption These specifications describe the standard configuration of the phyFLEX i MX 6 as of the printing of this manu
80. ccording to product forecasts e Offer long term frame contract to customers PHYTEC Messtechnik GmbH 2013 773 2 Preface Change management in case of functional changes e Avoid impacts on Product functionality by choosing equivalent replacement parts e Avoid impacts on Product functionality by compensating changes through HW redesign or backward compatible SW maintenance e Provide early change notifications concerning functional relevant changes of our Products Therefore we refrain from providing detailed part specific information within this manual which can be subject to continuous changes due to part maintenance for our products In order to receive reliable up to date and detailed information concerning parts used for our product please contact our support team for through the given contact information within this manual PHYTEC Messtechnik GmbH 2013 L 773e 2 XV phyFLEX i MX 6 PFL A XLI xxx 1 PHYTEC Messtechnik GmbH 2013 773 2 Introduction 1 Introduction The phyFLEX 1 MX 6 belongs to PHYTEC s phyFLEX System on Module family The phyFLEX SOMs represent the continuous development of PHYTEC System on Module technology Like its mini micro and nanoMODUL predecessors the phyFLEX boards integrate all core elements of a microcontroller system on a subminiature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware de
81. ch other This interface is compliant with USB revision 2 0 Jumper JP5 configures the OTG operating mode By default this jumper is open which leaves the USB OTG ID pin floating and thus configuring the OTG interface as slave Alternatively this jumper can be closed connecting USB OTG ID to GND and configuring the OTG interface as host Typically the configuration of a connecting device as host or slave is done automatically via a USB OTG cable PHYTEC Messtechnik GmbH 2013 1 773 2 101 6 PFL A XLI xxx However given the limited number of OTG enabled devices in the embedded market this jumper 1s provided to either simulate an OTG cable or force the OTG interface into host mode when OTG operation is not required LED 085 signals VBUS power output 102 PHYTEC Messtechnik GmbH 2013 1 773 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board 18 3 8 Display Touch Connectivity X65 H H P e 205 59 IT Figure 26 Display Interface PDI at Connector X65 The various performance classes of the phyFLEX family allow to attach a large number of different displays varying in resolution signal level type of the backlight pinout etc In order not to limit the range of displays connectable to the phyFLEX the phyFLEX carrier board has no special display connector suitable only for a small number of displays The new
82. concept intends the use of an adapter board e g PHYTEC s LCD display adapters LCD 014 LCD 017 and LCD 018 to attach a special display or display family to the phyFLEX A new PHYTEC Display Interface PDI was defined to connect the adapter board to the phyFLEX Carrier Board It consists of two universal connectors which provide the connectivity for the display adapter They allow easy adaption also to any customer display One connector 40 pin FCC connector 0 5 mm pitch at X65 PHYTEC Messtechnik GmbH 2013 L 773e 2 103 6 PFL A XLI xxx is intend for connecting all data signals to the display adapter It combines various interface signals like LVDS USB DC etc required to hook up a display The second connector of the PDI AMP microMatch 8 338069 2 at X65 provides all supply voltages needed to supply the display and a backlight and the brightness control The following sections contain specific information on each connector 18 3 8 1 Display Data Connector X65 PDI data connector X65 provides display data from the serial LVDS display interface of thephyFLEX 1 MX 6 see section 12 In addition other useful interfaces such as USB etc are available at PDI data connector X65 Table 49 hsts all miscellaneous signals and gives detailed explanations The following table shows the pin out of the PDI s display data connectors at X65 The display data connector at X65 is 40 pin FCC connec
83. d 0 V General purpose input output 3 General purpose input output 4 phyFLEX i MX 6 PFL A XL1 xxx VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC 5V VDD_3V3_LOGIC VDD_3V3_LOGIC VDD_3V3_LOGIC VDD_3V3_LOGIC 5V VDD_3V3_LOGIC VDD_3V3_LOGIC VDD_3V3_LOGIC VDD_3V3_LOGIC VDD_3V3_LOGIC VDD_3V3_LOGIC VDD_3V3_LOGIC VDD_3V3_LOGIC VDD_3V3_LOGIC VDD_3V3_LOGIC VDD_3V3_LOGIC VDD_3V3_LOGIC VDD_3V3_LOGIC 1 0 REF O 1 0 X USB0 nVBUSEN X USB0 VBUS X 08 0 nOC reference voltage X USBO CHGDET GND X 1250 CLK 250 FRM X 1250 ADC reference voltage X 1250 DAC X GPIOO X_GPIO1 X GPIO2 reference voltage X GPIO3 X GPIO4 Pinout of the phyFLEX fix Connector X1 Row A continued L 773e_2 X1A30 X1A31 X1A32 X1A33 X1A34 X1A35 X1A36 X1A37 X1A38 X1A39 X1A40 X1A41 X1A42 X1A43 X1A44 X1A45 X1A46 X1A47 X1A48 X1A49 X1A50 X1A51 X1A52 X1A53 X1A54 X1A55 X1A56 X1A57 X1A58 X1A59 X1A60 Table 3 1 5211 is not available for 1 6 Solo and 1 6 Dual Lite PHYTEC Messtechnik GmbH 2013 12 Pin Description General purpose input output 5 General purpose input output 6 General purpose input output 7 Ground 0 V
84. d plane But at least all GND pins neighboring signals which are being used in the application circuitry should be connected to GND 74 PHYTEC Messtechnik GmbH 2013 1 773 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board 18 The phyFLEX i MX 6 on the phyFLEX Carrier Board PHYTEC phyFLEX Carrier Boards are fully equipped with all mechanical and electrical components necessary for the speedy and secure start up and subsequent communication to and programming of applicable PHYTEC System on Module SOM modules phyFLEX Carrier Boards are designed for evaluation testing and prototyping of PHYTEC System on Module in laboratory environments prior to their use in customer designed applications The phyFLEX Carrier Board provides a flexible development platform enabling quick and easy start up and subsequent programming of the phyFLEX 1 MX 6 System on Module The carrier board design allows easy connection of additional extension boards featuring various functions that support fast and convenient prototyping and software evaluation The phyFLEX Carrier Board supports the following features for the phyFLEX i MX 6 modules e Power supply circuits to supply the phyFLEX 1 MX 6 and the peripheral devices of the carrier board e 12 V Power Supply e POE Power over Ethernet support 25 W e Support of all interfaces available at the phyFLEX fix and phyFLEX optional Connector e Support of different power modes of the appropriate phyFLE
85. e The primary input power of the phyFLEX 1 MX 6 Carrier Board comes from either the wall adapter jack X12 12 V or connector X55 input current gt 5 A or the Power over Ethernet circuit via Ethernet jack X28 Switching regulators on the carrier board generate six different voltages to supply the phyFLEX i MX 6 and the different components of the carrier board supported by the SOM The following table lists the five voltage domains and their main use PHYTEC Messtechnik GmbH 2013 1 773 2 89 phyFLEX i MX 6 PFL A XLI xxx Voltage domain Description supply voltage VCC5 X VCC5 VCC3V3 buck VCCI2 converter PDI interface PCle SATA CPU fan resulting from either VCC12 In or VCC POE supply voltage PDI interface SATA DVI CAN 5 USB VCC5 X Supply voltage phyFLEX SOM supply voltage PDI camera CPU fan power VCC3V3 management RTC Wi Fi Bluetooth SD MMC card interface UART interface PCIe 8 supply voltage Wi Fi Bluetooth VCCIVS8 Audio Supply voltage audio codec 5 Supply voltage mini 201617 connector X66 VCCIVI Supply core voltage USB Hub Table 41 Voltage Domains on the Carrier Board Five LEDs on the phyFLEX Carrier Board show the status of the different voltage domains The assignment of the LEDs to the voltage domains is shown in the following table LEDs Color Description 291 green VCCI2 12 V POE voltage attached to connecto
86. e 0 NAND boot Note As some of the signals which are brought out on the phyFLEX flex connector are used to configure the boot mode for specific boot options please make sure that these signals are not driven by any device on the baseboard during reset The signals which may affect the boot configuration are shown in Table Pin Signal SL Description Configuration Pin X3A31 X EIM WAIT 3 3 V EIM wait BCFG4 1 X3A32 X EIM A24 13 3 V address24 BCFG4 0 X3A33 23 33 address23 BCFG3 7 4 22 JO 33V EIM address22 BCFG3 6 X3A35 X 21 13 3 V EIM address21 BCFG3 5 7 20 JO 33V EIM address20 BCFG3 4 X3A38 X 19 JO 33V EIM address19 BCFG3 3 X3A39 A18 JO 13 3 V EIM address18 BCFG3 2 X3A40 X 17 JO 33V EIM address17 BCFG3 1 41 EBO JO 13 3 V EIM enable byteO BCFG4 3 43 3 3 V EIM enable bytel BCFG4 4 X3A44 X IVO 3 3 V EIM address data0 BCFGI 0 45 EIM 10 3 3 V EIM address datal BCFGI 1 X3A46 X EIM 2 3 3 V EIM address data2 1 2 X3A47 X EIM I O 3 3 EIM address data3 BCFGI 3 X3A49 X 4 IVO 3 3 EIM address data4 BCFGI 4 X3A50 X EIM 5 l O 3 3 EIM address data5 BCFGI 5 51 10 3 3 V EIM address data6 BCFGI 6 X3A52 X EIM DA7 IV
87. e PCB as viewed from above even if all connector contacts extend to the bottom of the module The numbering scheme is thus consistent for both the module s phyFLEX Connector as well as the mating connector on the phyFLEX Carrier Board or target hardware thereby considerably reducing the risk of pin identification errors The following figure illustrates the numbered matrix system It shows phyFLEX 1 MX 6 with all three SMT phyFLEX Connectors on its underside defined as dotted lines mounted on a carrier board In order to facilitate understanding of the pin assignment scheme the diagram presents a cross view of the phyFLEX 1 MX 6 module showing the phyFLEX Connector mounted on the underside of the module s PCB gt ra jc e T m Ja phyFLEX top view zl C S Figure 4 Pinout of the phyFLEX Connector top view PHYTEC Messtechnik GmbH 2013 L 773e 2 9 6 PFL A XLI xxx Table 3 to Table 8 provide an overview of the pinout of the different phyFLEX Connectors X2 and X3 with signal names and descriptions specific to the phyFLEX 1 MX 6 It also provides the appropriate voltage domain signal type ST and a functional grouping of the signals The signal type includes also information about the signal A description of the signal types can be found in Table 1 The Freescale Semiconductor 1 6 i
88. e following table shows the position of the signals on the connector Description Media local bus data line Media local bus data line Media local bus signal line Media local bus signal line Media local bus clock Media local bus clock PHYTEC Messtechnik GmbH 2013 1 773 2 Voltage Domain 1 MX 6 internal 1 MX 6 internal 1 MX 6 internal 1 MX 6 internal 1 MX 6 internal 1 MX 6 internal ST MLB I O MLB I O MLB I O MLB I O MLB O MLB O Signal X MLB DP X MLB DN X MLB SP X MLB SN X MLB CP X MLB CN Media Local Bus Interface Signal Location Pin X3B16 X3B17 X3B19 X3B20 X3B22 X3B23 Table 26 54 General Purpose I O 9 General Purpose I Os The phyFLEX bus provides 11 GPIO signals Table shows the location of the GPIO pins on the phyFLEX Connector as well as the corresponding ports of 1 6 General purpose input output 0 GPIOS_8 of i MX 6 General purpose input output 1 GPIOS_7 of i MX 6 General purpose input output 2 4 18 of i MX 6 GPIO reference voltage General purpose input output 3 GPIO4_19 of i MX 6 General purpose input output 4 GPIO1_6 of i MX 6 General purpose input output 5 GPIO1_9 of i MX 6 General purpose input output 6 GPIO7 12 of i MX 6 55 Description Signal IST Voltage Domain X GPIOO I O VDD 3V3 LO
89. e for external 4 4 Control Management IC CMIC 017 System Configuration and Booting 3 System 2 2 2 2 2 2 2 2 2 2 12 2 2 2 2 2 2 2 2 2 2 2 2 6 1 DDR3 SDRAM 02 09 6 2 NAND Flash Memory U13 5 3 po o 6 3 1 EEPROM Write Protection Control J3 6 4 SPI Flash Memory U25 s oeste Green iret SD Card Interfaces epo eon 2 2 2 2 2 1212 121 1 1 lever 21 1 1 1 8 1 Universal Asynchronous 8 2 oec 8 3 USB Host Intertate sso TREES 8 4 Ethernet Interface bua tue 8 44 1 Ethernet PHY 8 4 2 Software Reset of the Ethernet Controller 8 4 3 40016585 8 5 Interface ete 8 7 PS Audio Interface SSD ees SS 8 9 SATA Interface oa 8 10 PCI Express duin 8 11 Media Local Bus eere erre err rre nee List of Figures List of Tables 1 9 PHYTEC Messtechnik GmbH 2013 L 773e 2 phyFLEX i MX 6
90. ed D95 green High speed suspend status indicator LED for USB hub s upstream port D96 green Superspeed suspend status indicator LED for USB hub s upstream port Table 45 USB Hub s Status LEDs D93 D96 LEDs D84 1287 and D88 indicate the presence of the VBUS supply voltage LED Color Description D84 green VBUS indicator LED USB hub s upstream D87 green USB30 VBUS DNO indicator LED X45 D88 green USB30 VBUS DNI indicator LED X45 Table 46 USB VBUS indicator LEDs Table 47 shows the distribution of the four downstream facing ports to the different connectors USB hub port Connector Connector Type USB DNO X45 bottom USB A 3 0 USB DNI X45 top USB A 3 0 40 pin FCC pins B16 D and USB DN2 X65 B17 D USB DN3 X66 iE pins 36 D and D38 Table 47 Distribution of the USB Hub s U5 Ports 100 PHYTEC Messtechnik GmbH 2013 L 773e 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board 18 3 7 USB OTG Connectivity X26 iso HB UPS Figure 25 USB OTG Interface at Connector X26 The USB OTG interface of the phyFLEX 15 accessible at connector X26 USB micro AB on the carrier board The phyFLEX supports the On The Go feature The Universal Serial Bus On The Go is a device capable to initiate the session control the connection and exchange Host Peripheral roles between ea
91. ell as surrounding components and sockets remain undamaged while de soldering Overheating the board can cause the solder pads to loosen rendering the module inoperable Carefully heat neighboring connections in pairs After a few alternations components can be removed with the solder iron tip Alternatively a hot air gun can be used to heat and loosen the bonds PHYTEC Messtechnik GmbH 2013 L 773e 2 23 phyFLEX i MX 6 PFL A XLI xxx Please pay special attention to the column to ensure you are using the correct type of jumper 0 Ohms 10k Ohms etc The jumpers are either 0805 package or 0402 package with a 1 8 W or better power rating o E 0200 Gogo 0000 oro un unu 800 oo mnunump Hu B m D m B a 29999999 29990090909 0 gogoa 0000 0900 05 mo 00 00 05 o 0000 gogo 0 om 0002000 on ua ua O000000000000000000000000 O0000000000000000000000000 O000000000000000000000000 OO000000000000000000000000 OO000000000000000000000000 OO000000000000000000000000 O00000000000000
92. es one fixed and one optional SD MMC Card interface On the phyFLEX 1 MX 6 the interface signals extend from the controllers third and second Ultra Secured Digital uSDHC3 uSDHC2 Host Controller to the phyFLEX Connector Table shows the location of the different interface signals on the phyFLEX Connector The MMC SD SDIO Host Controller is fully compatible with the SD Memory Card Specification 3 0 and SD I O Specification Part El v1 10 SD MMC Card interface SDO uSDHC3 of the 1 6 supports 8 data channels and SD1 uSDHC2 of the i MX 6 4 data channels Both interfaces have a maximum data rate of up to i MX6 Reference Manual for more 104 MB s refer to the information Pin Signal ST Description 8 reference voltage REF VDD SDO 4 XIB9 X 800 nwP VDD_SD0 EE 2 10 X 00 nCD I VDD 5 ao XIBII X 5 UO VDD 00 SDO data 3 XIBI2 X SD0 CMD O VDD 8 0 SD0 command 721813 GND Ground 0 V 4 X CLK O VDD 500 SD0 clock XIBI5 X 5 UO VDD 00 SDO data 0 6 X 5 DI UO VDD 00 SDO data 1 XIBI7 X SD0 D2 IO VDD 00 520 2 XIBI8 X 520 UO VDD 00 SDO data 4 X1B20 5 5 IO VDD 00 SDO data 5 X1B21 X 5 VO VDD 00 SDO data 6 Table 15 Location of SD MMC Card Interface Signals 41 L 773e 2 PHYTEC Messtechnik GmbH 2013 Description
93. face Signal PCIe Interface Signal Media Local Bus Interface Signal Location Location of GPIO Pins een Debug Interface Signal Location at phyFLEX Connector X1 58 JTAG Connector X4 Signal Assignment Display Interface Signal Location Second Display Interface Signal Location at X3 Pixel Mapping of 18 bit LVDS Display Interface Pixel Mapping of 24 bit LVDS Display Interface HDMI Interface Signal Location at 2 Camera Interface Signal Location at 2 LVDS Signal Configuration 9 and J31 phyFLEX Carrier Board Connectors and Pin Headers phyFLEX Carrier Board Push Buttons Descriptions phyFLEX Carrier Board LEDs Descriptins Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 PHYTEC Messtechnik GmbH 2013 L 773e 2 phyFLEX i MX 6 PFL A XLI xxx Table 40 phyFLEX Carrier Board Jumper Descriptions 86 Table 41 Voltage Domains on the Carrier
94. g JP11 142 2 3 JP13 1 2 2 3 J9 1 2 2 3 J12 1 2 2 3 J27 J30 1 2 2 3 Table 40 PHYTEC Messtechnik GmbH 2013 phyFLEX i MX 6 PFL A XLI xxx 18 3 Functional Components on the phyFLEX Carrier Board This section describes the functional components of the phyFLEX Carrier Board supporting the phyFLEX 1 MX 6 Each subsection details a particular connector interface and associated jumpers for configuring that interface 18 3 1 phyFLEX i MX 6 SOM Connectivity X1 X2 Figure 16 phyFLEX i MX 6 SOM Connectivity to the Carrier Board Connectors X1 and X2 on the carrier board provide the phyFLEX System on Module connectivity The connector is keyed for proper insertion of the SOM Figure 16 above shows the location of connectors X1 and X2 along with the pin numbering scheme as described in section 2 88 PHYTEC Messtechnik GmbH 2013 1 773 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board Caution Samtec connectors guarantee optimal connection and proper insertion of the phyFLEX i MX 6 Please make sure that the phyFLEX i MX 6 is fully plugged into the matting connectors of the carrier board Otherwise individual signals may have a bad or no contact 18 3 2 Power occu JP11 Pur Management x22 05 0 X12 X55 Figure 17 Powering Schem
95. ion We recommend connecting all available 5 V input pins to the power supply system on a custom carrier board housing the phyFLEX i MX 6 and at least the matching number of GND pins neighboring the 5 V pins In addition proper implementation of the phyFLEX i MX 6 module into a target application also requires connecting all GND pins neighboring signals that are being used in the application circuitry Please refer to section 4 for more information PHYTEC Messtechnik GmbH 2013 L 773e 2 7 6 PFL A XLI xxx 2 PinDescription Please note that all module connections are not to exceed their expressed maximum voltage or current Maximum signal input values are indicated in the corresponding controller manuals data sheets As damage from improper connections varies according to use and application it is the user s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals As Figure 4 indicates all phyFLEX bus signals extend to up to three surface mount technology SMT connectors 0 5 mm referred to as phyFLEX Connector This allows the phyFLEX i MX 6 to be plugged into any target application like a big chip As well the location of the commonly used interfaces as the mechanical specifications of the connectors are clearly defined The first connector is called phyFLEX fix connector All phyFLEX SOMs supp
96. l Interface SPI interface extended from the third and fifth SPI module eCSPI3 and eCSPI5 of the i MX 6 1 5 audio interface originating from the fifth module of the 1 6 s Synchronous Serial Interface SSI5 CAN 2 0B interface extended directly from the 1 MX 6 FlexCANI module SATA II 3 0 Gbps extended directly from the 1 6 SATA PHY PCI Express Gen 2 0 extended directly from the 1 6 PCIe PHY Media Local Bus MLB interface connecting to the 1 6 s MediaLB 150 block l 10 11 The following sections of this chapter detail each of these serial interfaces and any applicable configuration jumpers PHYTEC Messtechnik GmbH 2013 1 773 2 43 phyFLEX i MX 6 PFL A XLI xxx 8 1 Universal Asynchronous Interface The jphyFLEX MX 6 provides two high speed universal asynchronous interfaces with up to 4 MHz and one with additional hardware flow control RTS and CTS signals The following table shows the location of the signals on the phyFLEX Connector Pin Signal ST Voltage Domain Description 12 X UARTI TxD TTL O 3v3 Logic UARTS serial 5 transmit signal 13 UARTI RxD TTL I VDD 5V3 0010 13 senal data oS receive signal XIAI4 X UARTI RTS TTL O VDD 3V3 LOGIC brun Tequest to XIAIS X UARTI CTS TTL I VDD 3V3 LOGIC EE clean fo 1 17 reference voltage REF VDD 3V3 LOGIC voltage XIA18 X UARTO TxD TTL O
97. ld ensure conformance following any modifications to the products as well as implementation of the products into target systems PHYTEC Messtechnik GmbH 2013 1 773 2 xiii phyFLEX i MX 6 PFL A XLI xxx Product Change Management and information in this manual on parts populated on the SOM When buying a PHYTEC SOM you will in addition to our HW and SW offerings receive a free obsolescence maintenance service for the HW we provide Our PCM Product Change Management Team of developers is continuously processing all incoming PCN s Product Change Notifications from vendors and distributors concerning parts which are being used in our products Possible impacts to the functionality of our products due to changes of functionality or obsolesce of a certain part are being evaluated in order to take the right masseurs in purchasing or within our HW SW design Our general philosophy here is We never discontinue a product as long as there is demand for it Therefore we have established a set of methods to fulfill our philosophy Avoiding strategies e Avoid changes by evaluating longlivety of parts during design in phase Ensure availability of equivalent second source parts e Stay in close contact with part vendors to be aware of roadmap strategies Change management in rare event of an obsolete and non replaceable part Ensure long term availability by stocking parts through last time buy management a
98. lied by inserting the appropriate card into the SD MMC slot 5100 at X57 shares the SDIO signals with the Wi Fi Bluetooth connector X58 To use the SDO card slot at X57 JP13 must be closed at 1 and 2 LED D106 shows that card slot SDO X57 is active 118 PHYTEC Messtechnik GmbH 2013 1 773 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board 18 3 17 PCIe Connectivity X59 The phyFLEX Carrier Board provides one PCIe x1 lane at X59 60 is available at this connector Pin Signal Name Description AI GND Ground Bl VCC12 12 V power supply A2 VCC12 12 V power supply B2 VCC12 12 V power supply A3 VCC12 12 V power supply B3 NC Not connected A4 GND Ground B4 GND Ground AS NC Not connected B5 NC Not connected A6 NC Not connected B6 NC Not connected AT NC Not connected B7 GND2 Ground 8 Not connected B8 3 3V1 3 3 V power supply VCC3V3 9 3 3 2 3 3 V power supply VCC3V3 B9 NC Not connected 10 3 3V3 3 3 V power supply VCC3V3 3 3VAUX 3 3 V power supply VCC3V3 11 PWRGD RESET OUT B11 WAKE PClex WAKE 12 GND7 Ground B12 NC Not connected A13 REFCLK CLK Table 61 PCIe0 Connector X59 PHYTEC Messtechnik GmbH 2013 1 773 2 119 L 773e 2 phyFLEX i MX 6 PFL A XLI xxx Description Ground PClex PClex TX Ground
99. lus PoE 92 18 3 2 3 Power Management Connector 22 93 18 3 3 RS 232 Connectivity X51 50 95 18 3 4 Connectivity X52 s epit e e teet 97 18 3 5 Ethernet Connectivity X28 sss 98 18 3 6 USB Host Connectivity X45 X65 66 99 18 3 7 USB Connectivity 26 101 18 3 8 Display Touch Connectivity 65 103 18 3 8 1 Display Data Connector 65 104 18 3 8 2 Display Power Connector X65 107 18 3 8 3 Touch Screen Connectivity 107 18 3 9 High Definition Multimedia Interface HDMI X40 108 18 3 10 Camera Interface X63 4 110 18 3 11 Audio Interface X7 X8 X9 X10 X11 112 18 3 12 TOC One Ct VARY dod ete e ecoute diets 114 L 773e 2 PHYTEC Messtechnik GmbH 2013 9 10 11 12 13 14 15 16 17 18 Contents iii 18 3 13 SPI Connectivity o lng eR NS 18 3 14 User programmable 18 3 15 User programmable 5 18 3 16 Secure Digital Memory Card MultiMedia Card XIT elm 18 3 17 PCIe ConnecHvily X99 uec tat fte be 83 48 SAT A CX02 eiae kon ed shed e 18 3 19 CPU Fan Connecto
100. mplementation of an OEM able SOM subassembly as the core of your embedded design allows you to focus on hardware peripherals and firmware without expending resources to re invent microcontroller circuitry Furthermore much of the value of the phyFLEX module lies in its layout and test PHYTEC s new phyFLEX product family consists of a series of extremely compact embedded control engines featuring various processing performance classes while using the newly developed phyFLEX embedded bus standard The standardized connector footprint and pin assignment of the phyFLEX bus makes this new SOM generation extremely scalable and flexible This also allows to use the same carrier board to create different applications depending on the required processing power With this new SOM concept it is possible to design entire embedded product families around vastly different processor performances while optimizing overall system cost In addition future advances in processor technology are already considered with this new embedded bus standard making product upgrades very easy Another major advantage is the forgone risk of potential system hardware redesign steps caused by processor or other critical component discontinuation Just use one of PHYTEC s other phyFLEX SOMs thereby ensuring an extended product life cycle of your embedded application PHYTEC Messtechnik GmbH 2013 L 773e 2 phyFLEX i MX 6 PFL A XLI xxx Production ready
101. nal EV data2 X1B57 X LVDSO 12 LVDS O 1 6 internal LVDSO data2 LVDSO MIB c coe VDD 3V3 LOGIC backlight PWM output 1 59 X_LVDS0_L3 LVDS i MX 6 internal L D50 2 E data3 X1B60 X LVDSO L3 LVDS O 1 6 internal LVDSO data3 XIB62 X LVDSO0 CLK LVDS i MX 6 interna 0 S 2 clock X1B63 X LVDSO CLK LVDS O i MX 6 internal LVDSO clock LVDSO X1B64 reference voltage REF VDD 3V3 LOGIC reference voltage Table 30 Display Interface Signal Location 62 PHYTEC Messtechnik GmbH 2013 L 773e 2 LVDS Display Interface Furthermore the phyFLEX 1 MX 6 supports a second LVDS Display at the non standardized phyFLEX flex connector X3 The table below shows the location of the signals Pin Signal ST Voltage Domain Description X3Bl X LVDS1 TX0 P LVDS O liMX6intemal LYPS data0 X3B2 X LVDSI TXON LVDS i MX 6 internal X3B4 X 177051 TXI P LVDS O liMX6intemal LYPS datal X3BS X LVDSI TXIN LVDS iMX 6 internal X3B7 X LVDS1 TX2P LVDS O liMX6intemal LYPS data2 X3B8 X LVDSI_TX2 N LVDS_O iMX 6 internal 2 X3B10 X LVDSI TX3 P LVDS O liMX6intenal data3 203811 X LVDSI_TX3 N LVDS 1 6 internal 2 X3B13 X LVDS1 LVDS O liMX6intemal clock X3Bl4 X LVDSI_CLK N LVDS_O i MX 6 internal Table 31 Second Display
102. nel It connects to the PWRON input of the on the phyFLEX 1 MX 6 and to the power management connector X22 LVDS DISP EN Can be used to enable or disable the display or to shutdown the backlight LVDS DISP BACKLIGHT PWM PWM output to control the brightness of display s backlight 0 dark 100 bright LS ANA Analog light sensor input The analog light sensor input at pin 40 extends to an 8 bit A D converter U7 which is connected to the I2CO Bus at address 0x64 get the maximum adjustment range the output voltage of an applicable light sensor should range from 0 V to VRef VCC3V3 Table 49 Auxiliary Interfaces at PDI Data Connector X65 106 PHYTEC Messtechnik GmbH 2013 1 773 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board 18 3 8 2 Display Power Connector X65 The display power connector X65 AMP microMatch 8 188275 2 provides all supply voltages needed to supply the display and a backlight Pin Signal name ST SL Description Al GND Ground A2 VCC3V3 O 3 37 3 3V power supply display A3 GND Ground 4 5 1 5 5V power supply display AS GND Ground A6 5 1 0 5V 5 V power supply display A7 GND Ground 8 5 1 0 5V 5 V power supply display A9 GND Ground A10 LVDS DISP BACK 3 3 V PWM brightness output LIGHT PWM VCC12 O 12 Backlight power supply 12 VCC12 O 12 Backlight power s
103. ollowing conventions were used in the Jumper column of the jumper table Table See Section 18 3 23 18 3 7 18 3 4 18 3 2 L 773e_2 e J solder jumper JP removable jumper Description Jumper connects the RTC Interrupt to the Power ON Wake Off Signal or to the 02105 Signal of the phyFLEX i MX 6 RTC Interrupt connect to Power ON Wake Off RTC Interrupt connect to 5 Jumper JP5 forces the USB OTG interface of the phyFLEX 1 MX 6 to function either as host master or device slave USBO0 ID floating phyFLEX i MX 6 in slave mode or according to the mode configured by software USBO ID connected to GND phyFLEX i MX 6 in host mode Jumper JP7 allows to connect an terminating resistor of 120 Ohm to the CAN interface Terminating resistor not connected Terminating resistor connected Jumper JP10 selects whether the voltage 5 and VCC3V3 are turned on and off by _ GOOD signal of the phyFLEX i MX 6 or are permanently switched on Power ON connected to high level VCC5 and VCC3V3 are permanently on Power ON connected to GOOD If PWR GOOD is low the voltages VCC5 and VCC3V3 are switched on phyFLEX Carrier Board Jumper Descriptions PHYTEC Messtechnik GmbH 2013 Jumper Setting 1 2 243 1 5 1 2 JP7 open 1 2 JP10 1 2 2 3 Table 40 86 The phyFLEX i MX 6 on the ph
104. oltage current and temperature and for fan control One Wake Up input Industrial temperature range 40 C to 85 C PHYTEC Messtechnik GmbH 2013 L 773e 2 3 phyFLEX i MX 6 PFL A XLI xxx 1 1 Block Diagram Control Signals Reset Wake up Bootpins Control Signals FAN control PM Bus E x USB USB both i MX6 internal PHY Display LVDSO 4 Lanes clock HDMI 1 output lanes 1 input lane 10 100 1000 MBit Ethernet 12C EEPROM DDRS 64Bit Bank1 Ethernet PHY DDRS 64Bit Bank2 phyFLEX fix X1 and phyFLEX optional X Connector NAND Flash SATA 2x UART SPI NOR Flash 2 x SD Interface 8 bit 4 bit 2 x SPI 1 with 4 CS 1 with 1 CS 2 12 9 GPIOs JTAG CSIO Camera parallel Camera0 LVDS LVDS Converter CSI1 phyFLEX flex X3 Connctor CSI 1 Parallel Camera GPIOs DISPO parallel Display Inteface and Address Databus multiplexed with other functions at connector X1 or X2 Figure 1 Block Diagram of the phyFLEX i MX 6 4 PHYTEC Messtechnik GmbH 2013 1 773 2 Introduction 1 22 phyFLEX i MX 6 Component Placement 8 vizo 886 Uu VUED CEO PORDCEOLREO 9GED SEED 98520 268230 0620 masy 520 GED SHED 21860 gor 42
105. on Control J3 Jumper J3 controls write access to the EEPROM 010 device Closing this jumper allows write access to the device while removing this jumper will cause the EEPROM to enter write protect mode thereby disabling write access to the device The following configurations are possible EEPROM Write Protection State J3 Write access allowed closed Write protected open Table 14 EEPROM write protection states via J3 Note If the jumper is not set the write protection signal can also be changed by GPIO3 19 of the 1 6 controller 6 4 SPI Flash Memory 025 The optional SPI Flash Memory of the phyFLEX i MX 6 at U25 can be used to store configuration data or any other general purpose data Beside this it can also be used as boot device The device is accessed through eCSPI3 050 on the i MX 6 The control registers for eCSPI3 are mapped between addresses 0x0201 0000 and 0x0201 3FFF Please see the i MX 6 Reference Manual for detailed information on the registers As of the printing of this manual these SPI Flash devices generally have a life expectancy of at least 100 000 erase program cycles and a data retention rate of 20 years This makes the SPI Flash a reliable and secure solution to store the first and second level bootloaders 1 Defaults are in bold blue text 40 PHYTEC Messtechnik GmbH 2013 L 773e 2 SD MMC Card Interfaces 7 SD MMC Card Interfaces The phyFLEX bus featur
106. onnected to a solid ground plane PHYTEC Messtechnik GmbH 2013 L 773e 2 27 phyFLEX i MX 6 PFL A XLI xxx 4 2 Power Management IC PMIC U14 The phyFLEX i MX 6 provides the on board Power Management IC DA9063 at position U14 to generate different voltages required by the processor and the on board components Figure 8 presents a graphical depiction of the powering scheme The DA9063 supports many functions like on chip RTC and different power management functionalities like dynamic voltage control different low power modes and regulator supervision It is connected to the i MX 6 via the on board bus The address of the DA9063 is 0x58 28 PHYTEC Messtechnik GmbH 2013 L 773e 2 Power 4 2 1 Power Domains External voltages e VDD 5V INR 5V main supply voltage e USB0 VBUS USBO Bus voltage must be supplied with 5 V 11 USBO is used e USBI VBUS USBI Bus voltage must be supplied with 5 V if USBI is used e PMIC VBBAT PMIC Backup supply Internal voltages VDD 5V IN only used to generate other voltages Internally generated voltages VDD MX6 ARM 1 375 V VDD MX6 SOC 1375V VDD 3V3 LOGIC 3 3 V VDD 3V3 IO 3 3V VDD 00 and VDD SD1 3 3V VDD ETH IO 2 5V VDD MX6 SNVS 3 0 V VDD MX6 HIGH 3 0V VDD PM 3 3 VDD ETH 1V2 1 2V VDD DDR3 1 5 15V DDR3 VIT 0 75 V DDR3 VREF 0 75 V VDD MX6 i MX6 VDDARM IN 1 375 V VDDARMO3 IN V
107. onnector to connect to 10 GPIOs of the phyFLEX Module Fan Connector e JTAG interface for programming and debugging 18 1 Concept of the phyFLEX Carrier Board The phyFLEX Carrier Board provides a flexible development platform enabling quick and easy start up and subsequent programming of the phyFLEX System on Module The carrier board design allows easy connection of additional extension boards featuring various functions that support fast and convenient prototyping and software evaluation The carrier board is compatible with all phyFLEX SOMs 76 PHYTEC Messtechnik GmbH 2013 1 773 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board This modular development platform concept includes the following components e the phyFLEX i MX 6 Module populated with the 1 MX 6 processor and all applicable SOM circuitry such as DDR SDRAM Flash PHYs and transceivers to name a few e the phyFLEX Carrier Board which offers all essential components and connectors for start up including a power socket which enables connection to an external power adapter interface connectors such as DB 9 USB and Ethernet allowing for use of the SOM s interfaces with standard cable The following sections contain specific information relevant to the operation of the phyFLEX 1 MX 6 mounted on the phyFLEX Carrier Board Note Only features of the phyFLEX Carrier Board which are supported by phyFLEX 1 MX 6 described Jumper settings
108. ort all interfaces specified for this connector at the same locations The second connector X2 called phyFLEX optional connector has optional but defined interfaces at fixed positions e g SATA CAN camera phyFLEX SOMs can but do not have to support the interfaces at the phyFLEX optional connector The third connector phyFLEX flex connector X3 has only fixed Ground signals All other signals of the phyFLEX flex connector are module specific and depend on the features of the controller populating the SOM The numbering scheme for the phyFLEX Connector is based on a two dimensional matrix in which column positions are identified by a letter and row position by a number with prefixed Connector Reference X1 phyFLEX fix X2 phyFLEX optional X3 phyFLEX flex Pin X1A1 for example is always located in the upper left hand corner of the matrix of connector Xl The pin numbering values increase moving down on the board Lettering of the pin connector rows progresses alphabetically from left to right refer to Figure 4 8 PHYTEC Messtechnik GmbH 2013 L 773e 2 Pin Description The numbered matrix can be aligned with the phyFLEX i MX 6 viewed from above phyFLEX Connector pointing down or with the socket of the corresponding phyFLEX Carrier Board user target circuitry The upper left hand corner of the numbered matrix pin X1A1 is thus covered with the corner of the phyFLEX 1 MX 6 The numbering scheme is always in relation to th
109. pes of jumpers require solder equipment to remove and place JP Solderless jumper these types of jumpers can be removed and placed by hand with no special tools PCB Printed circuit board PDI PHYTEC Display Interface defined to connect PHYTEC display adapter boards or custom adapters PEB PHYTEC Extension Board PMIC Power management IC PoE Power over Ethernet POR Power on reset RTC Real time clock SMT Surface mount technology SOM System on Module used in reference to the PFL A XL 1 phyFLEX i MX 6 module Sx User button Sx e g S1 S2 etc used in reference to the available user buttons or DIP Switches on the carrier board Sx y Switch y of DIP Switch Sx used in reference to the DIP Switch on the carrier board Table 2 Abbreviations and Acronyms used in this Manual X PHYTEC Messtechnik GmbH 2013 L 773e 2 Preface Preface As a member of PHYTEC s new phyFLEX product family the phyFLEX i MX 6 is of a series of PHYTEC System on Modules SOMs that can be populated with different controllers and hence offers various functions and configurations PHYTEC supports a variety of 8 16 and 32 bit controllers in two ways 1 as the basis for Rapid Development Kits which serve as a reference and evaluation platform 2 as insertready fully functional phyFLEX OEM modules which can be embedded directly into the user s peripheral hardware design I
110. ports HP Auto MDIX technology eliminating the need for the consideration of a direct connect LAN cable or a cross over patch cable It detects the TX and RX pins of the connected device and automatically configures the PHY TX and RX PHYTEC Messtechnik GmbH 2013 1 773 2 47 phyFLEX i MX 6 PFL A XLI xxx pins accordingly The Ethernet PHY also features an Auto negotiation to automatically determine the best speed and duplex mode The Ethernet controller is connected to the RGMII interface of the 1 6 Please refer to the iMX6 Reference Manual for more information about this interface In order to connect the module to an existing 10 100 1000Base T network some external circuitry is required The required termination resistors on the analog signals Az B C D are integrated in the chip so there is no need to connect external termination resistors to these signals Connection to an external Ethernet magnetics should be done using very short signal traces The A A B B C C and D D signals should be routed as 100 Ohm differential pairs The same applies for the signal lines after the transformer circuit The carrier board layout should avoid any other signal lines crossing the Ethernet signals If you are using the applicable carrier board for the phyFLEX 1 MX 6 part number PBA B 01 the external circuitry mentioned above is already integrated on the board refer to section 18 3
111. provides a detailed view of the phyFLEX Carrier Board jumpers and their default settings In these diagrams a beveled edge indicates the location of pin 1 Before making connections to peripheral connectors it is advisable to consult the applicable section in this manual for setting the associated jumpers removable jumper solder jumper 1 1 2 1 2 3 2 3 e g 1 e g 5 e g J9 Figure 14 Typical Jumper Numbering Scheme Table provides a comprehensive list of all carrier board jumpers The table only provides a concise summary of jumper descriptions For a detailed description of each jumper see the applicable chapter listing in the right hand column of the table If manual modification of the solder jumpers 15 required please ensure that the board as well as surrounding components and sockets remain undamaged while de soldering Overheating the board can cause the solder pads to loosen rendering the board inoperable Carefully heat neighboring connections in pairs After a few alternations components can be removed with the solder iron tip Alternatively a hot air gun can be used to heat and loosen the bonds 84 PHYTEC Messtechnik GmbH 2013 L 773e 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board JP5 JP11 1 JP13 JP10 Figure 15 phyFLEX Carrier Board Jumper Locations PHYTEC Messtechnik GmbH 2013 1 773 2 85 6 PFL A XLI xxx The f
112. ption of the controller s registers or information relevant for software development Please refer to the i MX 6 Reference Manual if such information is needed to connect customer designed applications Conventions The conventions used in this manual are as follows Signals that are preceded by an n or character e g nRD RD or ZRD or that have a dash on top of the signal name e g RD are designated as active low signals That is their active state is when they are driven low or are driving low A 0 indicates a logic zero or low level signal while a I represents a logic one or high level signal The hex numbers given for addresses of devices always represent the 7 MSB of the address byte The correct value of the LSB which depends on the desired command read 1 or write 0 must be added to get the complete address byte E g given address in this manual 0x41 gt complete address byte 0x83 to read from the device and 0x82 to write to the device PHYTEC Messtechnik GmbH 2013 L 773e 2 vil phyFLEX i MX 6 PFL A XLI xxx Tables which describe jumper settings show the default position in bold blue text Text in blue italic indicates a hyperlink within or external to the document Click these links to quickly jump to the applicable URL part chapter table or figure References made to the phyFLEX Connector always refer to the high density samtec connector on the undersides of the phyF
113. r 41 18 3 20 Wi Fi Bluetooth Connector X58 18 3 21 Boot Mode Selection 53 18 3 22 System Reset Button S1 iiec tinae 18 3 23 JTAG Interface dU tuse tica auti ts I9 Revision History cues peo e hie TNL qur List of Figures Figure 1 Block Diagram of the phyFLEX 1 MX 6 Figure2 phyFLEX i MX 6 Component Placement top view Figure3 phyFLEX i MX 6 Component Placement bottom view Figure 4 Pinout of the phyFLEX Connector top view Figure 5 Typical Jumper Pad Numbering Figure 6 Jumper Locations top view Figure 7 Jumper Locations bottom Figure 8 Powering scheme of phyFLEX 1 6 Figure 9 JTAG Interface at X4 top view iet hts Figure 10 JTAG Interface at bottom Figure 11 Physical Dimensions top view e Figure 12 Footprint of the phyFLEX 1 MX 6 Figure 13 phyFLEX Carrier Board Overview of Connectors LEDs and bec a pud Figure 14 Typical Jumper Numbering Scheme Figure 15 phyFLEX Carrier Board Jumper Locations PHYTEC Messtechnik GmbH 2013 L 773e 2
114. r X28 D100 green 2 IN 12 V supply voltage for the phyFLEX Carrier Board attached to connector X12 or X55 D102 green 12 12V supply voltage for DC to DC synchronous buck controller and peripherals on the phyFLEX Carrier Board resulting from either VCC12 IN or VCC12 POE D101 green VCC5 5 V supply voltage for the phyFLEX module D112 green VCC5 5 V supply voltage for various peripherals on the phyFLEX Carrier Board D111 green VCC 3V3 X 3 3 V supply voltage for peripherals on the phyFLEX Carrier Board Table 42 Power LEDs 9 PCIel is not supported by the phyFLEX i MX 6 90 PHYTEC Messtechnik GmbH 2013 1 773 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board Two jumpers on the phyFLEX 1 MX 6 Carrier Board allow to enable or disable single voltage domains The following table lists the jumpers and the associated voltage domain Voltage domain Jumper Description JP10 Jumper JP10 selects whether the voltages VCC5 and VCC3V3 are turned on and off by the PWR GOOD signal of the phyFLEX i MX 6 or VCCS are permanently switched on VC C3V3 1 2 Power ON connected to high level VCC5 and VCC3V3 are permanently on 2 3 Power ON connected to PWR GOOD If PWR GOOD is low the voltages VCC5 and VCC3V3 are switched on JP11 Jumper JP11 allows to control the supply voltage of VCC5 X ofthe phyFLEX 1i MX 6 module
115. r features which impact program execution must be configured prior to initialization via pin termination The system start up configuration includes e Boot device order configuration During the reset cycle the operational system boot mode of the 1 6 processor is determined by the configuration of two BOOTMODE pins BOOT 1 0 These pins select the boot type If the boot type is set to Internal boot BOOT MODE 1 0 10 BOOT CFGx 7 0 are used to configure further boot options You can find further information about these boot pins in the i MX 6 Reference Manual The internal ROM code is the first code executed during the initialization process of the 1 6 after POR The ROM code detects which boot devices the controller has to check by using the BOOT MODE 1 0 particular CFGxx 7 0 configuration For serial boot devices the ROM code polls the communication interface selected initiates the download of the code into the internal RAM and triggers its execution from there For memory booting the ROM code finds the bootstrap in permanent memories such as NAND Flash or SD Cards and executes it Please refer to the i MX 6 Reference Manual for more information The phyFLEX 1 MX 6 provides three boot configuration pins BOOT 2 0 The setting of these pins configures the boot device which is selected by the processor The standard phyFLEX boot options are shown in Table 10 Boot options specific for the
116. r jumper settings while the carrier board is supplied with power over the Ethernet 18 3 2 3 Power Management Connector X22 The pin header X22 provides the Power Management Signals Pin Signal Name Description 1 VCC3V3 3 3 V power supply 2 RESET OUT Reset Output 3 RESET IN Reset Input 4 Power ON Wake OFF Power ON Wake Off Signal 5 PM SDA Power Management PC SDA 7 6 PM SCL Power Management SCL Not connected 8 PWR_GOOD Power Good Signal 9 NC Not connected 10 GND Ground Table 44 Power Management Connector X22 10 function of this signal is not available yet PHYTEC Messtechnik GmbH 2013 1 773 2 93 phyFLEX i MX 6 PFL A XLI xxx 18 3 2 3 1 Power States e RUN can be entered by pressing using power button S2 less than 5 seconds Button 52 is connected to Power ON Wake OFF Signal e OFF can also be entered using power button S2 In this mode we have to make a distinction between two possible of OFF modes The first is when the system is shut down by software In this case the phyFLEX 1 MX 6 will stop the running processes and shutdown If button S2 is held for a time longer than 5 seconds OFF mode will be reached by turning off the phyFLEX 1 MX 6 internal voltages without stopping processes and shutdown It is also possible to control state modes from outside the carrier board with the help of the Power ON Wake OFF Signal accessible on the
117. resented below The pin header connector at X7 allows for direct connection of a Mono Class D 1W BTL 8 Ohm Speaker Audio Outputs X8 Line Output X9 Headset Output X7 Speaker Output Audio Inputs X10 Microphone In Line In Please refer to the audio codec s reference manual for additional information regarding the special interface specification The audio codec s master clock of 19 2 MHz will be generated at 1 on the carrier board The microphone input X10 and the headset output X9 allows jack detection The jack detection of the microphone input is hardwired while jack detection of the headset output can be disabled by jumper J9 In default position 2 3 jumper J9 connects the shield contact of audio jack X9 headset out to the HPCOM output driver of the stereo audio codec at U25 In this configuration jack detection is enabled Connecting the shield contact to GND 79 at 1 2 disables the jack detection function PHYTEC Messtechnik GmbH 2013 1 773 2 113 6 PFL A XLI xxx 18 3 12 Connectivity The carrier board provides two buses 2 0 and 2 These are available at different connectors on the phyFLEX Carrier Board The following table provides a list of the connectors and pins with connectivity Connector Location Camera interface X63 pin 4 12 SDA CAMERA pin 5 2 SCL CAMERA derived from 12 1 Camera interface X64 pin 4
118. row B is on the connector side of the module PHYTEC offers a JTAG Emulator adapter order code JA 002 for connecting the phyFLEX 1 MX 6 to a standard emulator The JTAG Emulator adapter extends the signals of the module s JTAG connector to a standard ARM connector with 2 mm pin pitch The JA 002 therefore functions as an adapter for connecting the module s non ARM compatible JTAG connector X4 to standard Emulator connectors PHYTEC Messtechnik GmbH 2013 L 773e 2 61 phyFLEX i MX 6 PFL A XLI xxx 12 LVDS Display Interface The LVDS Signals from the on chip LVDS Display Bridge LDB of the 1 6 are brought out at the phyFLEX fix connector Thus LVDS Display can connect directly to the phyFLEX 1 MX 6 The location of the applicable interface signals X LVDSO 10 3 X LVDSO L0 3 X LVDSO and X LVDSO CLK and of the two control signals display enable and backlight PWM nLVDSO DISP EN LVDSO DISP BL can be found in the table below Pin Signal ST Voltage Domain Description X1B50 1 0 10 LVDS i MX 6 internal 50 m E 0 1 51 LVDSO 10 LVDS 1 6 internal LVDSO data0 LVDSO X1B52 X LVDSO nDISP EN O VDD 3V3 LOGIC display enable low active X1B53 X LVDSO 11 LVDS O 1 6 internal Eye datal X1B54 X LVDSO 11 LVDS O 1 6 internal LVDS0 datal X1B56 X LVDSO0 12 LVDS O 1 6 inter
119. s a multi voltage operated microcontroller and as such special attention should be paid to the interface voltage levels to avoid unintentional damage to the microcontroller and other on board components Please refer to the Freescale Semiconductor i MX 6 Reference Manual for details on the functions and features of controller signals and port pins 1 The specified direction indicated refers to the standard phyFLEX use of the pin 10 PHYTEC Messtechnik GmbH 2013 L 773e 2 Pin Description Description 5 V Primary Voltage Supply Input 5 V Primary Voltage Supply Input 5 V Primary Voltage Supply Input Ground 0 V JTAG reset input low active JTAG TDI JTAG TMS JTAG TDO JTAG clock input Ground 0 V Not connected UARTI serial transmit signal UARTI serial data receive signal UARTI request to send UARTI clear to send Ground 0 V UARTI reference voltage UARTO serial transmit signal UARTO reference voltage UARTO serial data receive signal SPIO master output slave input Ground 0 V SPIO master input slave output SPIO Chip Select BOOT SPIO Chip Select 0 SPIO Chip Select 1 SPIO reference voltage Ground 0 V SPIO clock signal Pinout of the phy FLEX fix Connector Row 11 Voltage domain VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VD
120. s of the various USB Host interfaces as well as the different supply voltages Figure 13 shows the location of the LEDs Their function 15 listed in the table below LED Color Description 55 Section Indicates presence of 12 V input voltage VCCI2 POE X from Ethernet at connector X28 D100 green Indicates presence of 12 V input voltage VCC12 IN at power connector X12 or X55 12 V supply voltage VCC12 available at the DC to D102 green DC synchronous buck controller U58 derived from VCCI2 IN or VCCI2 POE 1952 5 V supply voltage 5 X for the DIUI SEI El MAK 6 5 V supply voltage 5 for various peripherals on the phyFLEX Carrier Board D111 green 3 3 V supply voltage VCC3V3 X for various peripherals on the phyFLEX Carrier Board available User LED connected to GPIO10 GPIO2 24 at D105 green a i MX 6 D97 red User LEDO conrolled by a 4 bit LED dimmer U52 D98 yellow User LEDI conrolled by a 4 bit LED dimmer U52 099 yellow User LED2 conrolled by a 4 bit LED dimmer U52 D86 green User LED3 conrolled by a 4 bit LED dimmer U52 High speed indicator LED for USB hub s upstream 18 3 15 neuen port connection speed D94 green Super speed indicator LED for USB hub s upstream 18 3 6 port connection speed D95 green High speed suspend status indicator LED for USB hub s upstream port Table 39 phyFLEX Carrier Board LEDs Descriptins 82
121. shift the PC interface signals and the hot plug detect signal from IO voltage VCC3V3 to 5 V while the data and clock signals extend directly form the phyFLEX Connector to the DVI receptacle Pin Signal name ST SL Description HDMI TMDS DATA2 O HDMI HDMI data channel 2 1 j negative output 2 HDMI TMDS DATA2 O HDMI HDMI data channel 2 positive output 3 GND Ground 4 NC Not connected 5 NC Not connected 6 X HDMI SCL 5 HDMI clock signal 7 X HDMI SDA 5V HDMI data signal 8 NC Not connected 9 HDMI TMDS DATAI O HDMI HDMI data channel 1 negative output 10 HDMI TMDS DATAI O HDMI HDMI data channel 1 positive output 11 GND Ground 12 NC Not connected 13 NC Not connected 14 V5 HDMI O 5V 5 V power supply 15 GND Ground Table 51 HDMI DVI Connector X40 Pinout 108 PHYTEC Messtechnik GmbH 2013 1 773 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board Pin Signal name ST SL Description 16 nX HDMI HPD I 5 HDMI hot plug detection HDMI TMDS DATAO O HDMI HDMI data channel 0 i negative output 18 HDMI TMDS DATAO O HDMI HDMI data channel 0 positive output 19 GND Ground 20 NC Not connected 21 NC Not connected 22 GND Ground 23 HDMI TMDS CLOCK O HDMI HDMI clock positive output 24 HDMI TMDS CLOCK O HDMI HDM
122. stechnik GmbH 2013 1 773 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board 18 2 2 Switches The phyFLEX Carrier Board is populated with some switches which are essential for the operation of the phyFLEX 1 MX 6 module on the carrier board Figure 13 shows the location of the switches and push buttons See Button Description Section 51 System Reset Button system reset signal 18322 generation S2 Power Button powering on and off main Not supply voltages of the carrier board implemented yet S3 DIP switch boot mode selection 18 3 21 Table 38 phyFLEX Carrier Board Push Buttons Descriptions 51 Issues a system reset signal Pressing this button will toggle the nRESET IN pin X1A72 of the phyFLEX microcontroller LOW causing the controller to reset S2 Issues a power on off wake event Pressing this button less than 5 seconds will wake up the phyFLEX 1 MX 6 module and the peripherals on the carrier board or will turn on the system if it 1 powered off Pressing this button more than 5 seconds will turn off the system without proper shut down of the operating system S3 This DIP switch allows to change the booting device order of the phyFLEX i MX 6 PHYTEC Messtechnik GmbH 2013 L 773e 2 81 6 PFL A XLI xxx 18 2 3 LEDs The phyFLEX Carrier Board is populated with numerous LEDs to indicate the statu
123. ta 9 X USB0 D USB I O i MX 6 internal USBO data XIB40 USBO ID I VDD 3V3 LOGIC USBO ID Pin Table 17 Location of the USB OTG Signals PHYTEC Messtechnik GmbH 2013 L 773e 2 45 phyFLEX i MX 6 PFL A XLI xxx 8 3 USB Host Interface The phyFLEX 1 MX 6 provides a high speed USB Host interface which uses the i MX 6 embedded HS USB Host PHY An external USB Standard A for USB host connector is all that is needed to interface the phyFLEX 1 MX 6 USB Host functionality The applicable interface signals D D PWR OC can be found on the Description USB1 VBUS enable active low USB1 VBUS input USBI overcurrent pin USBI reference oltage SBO data U USBO Voltage Domain VDD 3V3 LOGIC 5y VDD 3V3 LOGIC VDD 3V3 LOGIC 1 MX 6 internal 1 MX 6 internal ST O PWR I IPU REF O X1B44 X USBI D USB I O USB phyFLEX fix Connector X1 Pin Signal X1A43 X USBI nVBUSEN 1444 X USBI VBUS XIA45 X USBI nOC X1A47 reference voltage 1 45 X USBI Table 18 Location of the USB Host Signals PHYTEC Messtechnik GmbH 2013 L 773e 2 46 Serial Interfaces 8 4 Ethernet Interface Connection of the phyFLEX 1 MX 6 to the world wide web or a local area network LAN is possible using the on board GbE PHY at U11 It is connected to the interface of the 1
124. tion positions e g SATA CAN camera Other phyFLEX SOMs might have more or less interfaces 19 Pin Signal ST Voltage Domain Description X3AI CSI 2 i MX 6 internal CSI clock X3A2 CSI 2 1 6 internal CSI clock X3A3 I VDD 3V3 LOGIC 0510 0 X3A4 CSI 2 I i MX 6 internal CSI data0 X3A5 CSI 2 I i MX 6 internal CSI data0 X3A6 Ground 0 V X3A7 CSI 2 i MX 6 internal CSI datal X3A8 CSI 2 I i MX 6 internal CSI datal X3A9 I VDD 3V3 LOGIC 0510 1 X3A10 CSI 2 I i MX 6 internal CSI data2 CSI 2 I i MX 6 internal CSI data2 X3A12 Ground 0 V X3A13 CSI 2 I i MX 6 internal CSI data3 X3A14 CSI 2 I i MX 6 internal CSI data3 X3A15 I VDD 3V3 LOGIC 0510 2 X3A16 I VDD 3V3 LOGIC 0510 3 X3A17 I VDD_3V3_LOGIC 0510 4 X3A18 Ground 0 7 X3A19 I VDD 3V3 LOGIC 0510 5 X3A20 I VDD 3V3 LOGIC 0510 6 X3A21 I VDD 3V3 LOGIC 0510 7 X3A22 I VDD 3V3 LOGIC 0510 8 X3A23 I VDD 3V3 LOGIC 0510 9 X3A24 Ground 0 V X3A25 0 3V3 LOGIC 0510 master clock X3A26 0 VDD 3V3 LOGIC 0510 pixel clock X3A27 I 3V3 LOGIC 0510 vertical sync X3A28 0 VDD 3V3 LOGIC 0510 data enable X3A29 I VDD 3V3 LOGIC Tamper X3A30 Ground 0 V X3A31 X EIM WAIT I VDD 3V3 LOGIC EIM wait X3A32 X A24 0 VDD 3V3 LOGIC address24 X3A33 X EIM A23 VDD 3V3 LOGIC EIM address23 X3A34 X EIM A22 0 VDD 3V3 LOGIC EIM address22 X3A35 X EIM A21 VDD 3V3 LOGIC EIM address21 Table 7 Pino
125. tor with 0 5 mm pitch Pin Signal name ST SL Description Bl SPIO SCLK O 3 3 V SPI 0 clock B2 SPIO MISO 3 3 SPI 0 master data in slave data out B3 SPIO MOSI 3 3 V SPI 0 master data out slave data in B4 0 CSI O 3 3 V SPI 0 chip select display B5 GPIO6 1 3 3 V Display interrupt input B6 VCC3V3 O 3 3 V Power supply display B7 12 0 SCL VO 33 clock signal B8 2 0 SDA VO 3 3 data signal B9 GND Ground B10 LS BRIGHT O 3 3 V PWM brightness output B11 VCC3V3 O 3 3 V Logic supply voltage B12 PWR KEY I 3 3 V Power on off Button Table 48 Display Data Connector Signal Description 2 Provided to supply any logic on the display adapter Max draw 100 mA 104 PHYTEC Messtechnik GmbH 2013 1 773 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board Description Display enable signal Hardware Introspection Interface for internal use only Ground USB DN2 data USB DN data Ground LVDS data channel 0 negative output LVDS data channel 0 positive output Ground LVDS data channel 1 negative output LVDS data channel 1 positive output Ground LVDS data channel 2 negative output LVDS data channel 2 positive output Ground LVDS data channel 3 negative output LVDS data channel 3 positive output Ground LVDS clock channel negative output LVDS clock channel positive output Ground Touch
126. ttp www phytec eu europe support faq faq phyFLEX i MX6 html Declaration of Electro Magnetic Conformity of the phyFLEX i MX 6 PHYTEC System on Module henceforth products are designed for installation in electrical appliances or as dedicated Evaluation Boards 1 for use as a test and prototype platform for hardware software development in laboratory environments Caution PHYTEC products lacking protective enclosures are subject to damage by ESD and hence may only be unpacked handled or operated in environments in which sufficient precautionary measures have been taken in respect to ESD dangers It is also necessary that only appropriately trained personnel such as electricians technicians and engineers handle and or operate these products Moreover PHYTEC products should not be operated without protection circuitry if connections to the product s pin header rows are longer than 3 m PHYTEC products fulfill the norms of the European Union s Directive for Electro Magnetic Conformity only in accordance to the descriptions and rules of usage indicated in this hardware manual particularly in respect to the pin header row connectors power connector and serial interface to a host PC Implementation of PHYTEC products into target devices as well as user modifications and extensions of PHYTEC products is subject to renewed establishment of conformity to and certification of Electro Magnetic Directives Users shou
127. und This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyFLEX boards even in high noise environments PHYTEC Messtechnik GmbH 2013 L 773e 2 1 phyFLEX i MX 6 PFL A XLI xxx phyFLEX boards achieve their small size through modern SMD technology and multi layer design In accordance with the complexity of the module 0402 packaged SMD components and laser drilled microvias are used on the boards providing phyFLEX users with access to this cutting edge miniaturization technology for integration into their own design The phyFLEX i MX 6 is a subminiature 60 mm x 70 mm insert ready System on Module populated with the Freescale Semiconductor i MX 6 microcontroller Its universal design enables its insertion in a wide range of embedded applications Precise specifications for the controller populating the board can be found in the applicable controller reference manual or datasheet The descriptions in this manual are based on the Freescale Semiconductor i MX 6 No description of compatible microcontroller derivative functions 1s included as such functions are not relevant for the basic functioning of the phyFLEX 1 MX 6 The phyFLEX 1 MX 6 offers the following features Subminiature System on Module 60mm x 70 mm achieved through modern SMD technology e Populated with the Freescale Semiconductor 1 MX 6 microcontroller BGA624 packaging e Max
128. upply Table 50 PDI Power Connector X65 Signal Description 18 3 8 3 Touch Screen Connectivity As many smaller applications need a touch screen as user interface provisions are made to connect 4 wire resistive touch screens to the PDI data connector X65 pins B34 B37 refer to Table The signals from the touch screen panel are processed by a touch panel controller at U6 The touch panel controller is connected to bus 1200 at address 0x41 By changing jumper J12 the address can be set to 0x44 if needed refer to Table An additional interrupt output is connected to GPIOO X1A54 on the phyFLEX fix Connector of the phyFELX 1 MX 6 PHYTEC Messtechnik GmbH 2013 1 773 2 107 phyFLEX i MX 6 PFL A XLI xxx 18 3 9 High Definition Multimedia Interface HDMI X40 The High Definition Multimedia Interface HDMI of the phyFLEX 1 MX 6 Module is compliant to HDMI 1 4 HDCP 1 4 and DVI 1 0 It supports a maximum pixel clock of 340 Mhz at a resolution of up to 1080p 60 Mhz and 720 10801 120 Mhz Please refer to the 6 Reference Manual for more information The HDMI interface brought out at an DVI female connector X40 on phyFLEX Carrier Board comprises the following signal groups three pairs of data signals one pair of clock signals an PC bus which 15 exclusively for the HDMI interface and the hot plug detect HPD signal Level shifters
129. ut 5210 master input slave output SPIO chip select BOOT SPIO chip select 0 SPIO chip select 1 SPIO reference voltage SPIO clock signal 5211 chip select 0 SPI master output slave input SPI master input slave output 5211 reference voltage 5211 clock signal 5211 chip select 1 L 773e 2 Voltage Domain VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC ST O REF O O O Signal X SPIO MOSI X 210 MISO X 8 0 CSBOOT X SPIO CSO X SPIO CSI reference voltage X SPIO CLK X SPH CSO X SPI MOSI X 5 reference voltage X SPIL CLK X SPH CSI SPI Interface Signal Location PHYTEC Messtechnik GmbH 2013 table lists the SPI signals on the phyFLEX Connector Pin X1A21 X1A23 X1A24 X1A25 X1A26 X1A27 X1A29 X1A30 X1A31 X1A32 X1A33 X1A35 X1A36 Table 21 50 Serial Interfaces 8 7 T S Audio Interface SSD The Synchronous Serial Interface SSI of the phyFLEX 1 MX 6 is a full duplex serial interface that allows to communicate with a variety of serial devices such as standard codecs digital signal processors DSPs microprocessors peripherals and popular industry audio codecs that implement the inter IC sound bus standard 125
130. ut of the phyFLEX flex Connector X3 Row A L 773e 2 PHYTEC Messtechnik GmbH 2013 Ground 0 V EIM address20 EIM address19 EIM address18 EIM address17 EIM enable byteO Ground 0 V EIM enable bytel EIM address data0 EIM address datal EIM address data2 EIM address data3 Ground 0 V EIM address data4 EIM address data5 EIM address data6 EIM address data7 EIM address data8 Ground 0 V EIM address data9 EIM address data10 EIM address datall EIM address data12 EIM address16 Ground 0 V Description LVDSI data0 LVDSI data0 Ground 0 V LVDSI datal LVDSI datal DISPO data9 PWM2 output LVDSI data2 LVDSI data2 Ground 0 V LVDSI 0283 LVDSI data3 Pinout of the phyFLEX flex Connector X3 Row B L 773e 2 6 PFL A XLI xxx VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC VDD 3V3 LOGIC Pinout of the phyFLEX flex Connector X3 Row A continued Votlage domain 1 MX 6 internal 1 MX 6 internal 1 MX 6 internal 1 MX 6 internal VDD 3V3 LOGIC 1 MX 6 internal 1 MX 6 internal 1 MX 6 internal 1 MX 6 internal PHYT
131. velopments PHYTEC s phyFLEX family introduces the newly developed phyFLEX embedded bus standard Apart from processor performance a large number of embedded solutions require a corresponding number of standard interfaces Among these process interfaces are for example Ethernet USB UART SPI PCle audio and display connectivity The phyFLEX bus exactly meets this requirement with the phyFLEX fix connector As well the location of the commonly used interfaces as the mechanical specifications are clearly defined Beside this the phyFLEX concept also considers that different controllers have many different interfaces To take this into account the phyFLEX concept allows two more connectors the phyFLEX optional connector which has optional but defined interfaces at fixed positions e g SATA CAN camera and the phyFLEX flex connector which has only fixed Ground signals All other signals of the phyFLEX flex connector are module specific All interface signals of PHYTEC s new phyFLEX bus are available on up to three high density pitch 0 5 mm connectors allowing the phyFLEXs to be plugged like a big chip into a target application As independent research indicates that approximately 70 96 of all EMI Electro Magnetic Interference problems stem from insufficient supply voltage grounding of electronic components in high frequency environments approximately 20 of all pin header connectors on the phyFLEX bus are dedicated to Gro
132. wer over Ethernet Plus POE circuit provides a method of powering the board via the Ethernet interface In this configuration the carrier board acts as the Powered Device PD while the connecting Ethernet interface acts as the Power Source Equipment PSE For applications that require Ethernet connectivity this is an extremely convenient method to also simultaneously provide power To make use of the PoE circuit a PSE e g a PoE enabled router or switch is necessary LED D91 indicates the availability of the PoE supply voltage The PoE circuit generates a supply voltage of 12 V which is feed into the VCC12 branch through an ideal diode The IEEE PoE standard restricts the maximum amount of power a PSE must provide and therefore a PD can consume The carrier board PoE circuit was designed to provide up to 25 W of power to the board 92 PHYTEC Messtechnik GmbH 2013 L 773e 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board The carrier board Ethernet connector X28 supports both PSE sourcing methods of power over the data wires or power over the spare wires Caution The PoE circuit was designed to provide up to 25 W of power to the board This is less than the board can potentially consume Be aware that this limitation could cause board operation to fail if peak power is exceeded due to enabled peripherals Do not supply the system over Ethernet if the power consumption expected might exceed 25 W Do not change modules o
133. xD RS232 7 3 8 Pin 3 RxD RS232 4 9 5 Pin 5 GND Figure 21 5 232 Connector X51 Signal Mapping UARTO 96 PHYTEC Messtechnik GmbH 2013 1 773 2 The phyFLEX i MX 6 on the phyFLEX Carrier Board 18 3 4 CAN Connectivity X52 Connector X52 is a SUB D9M connector and provides connection interfaces to the CAN interface of 1 6 The TTL level signals from the phyFLEX 1 MX 6 are converted to differential CAN signals by the CAN transceiver at U24 This chip is completely integrated with DC DC Switching Regulator to generate an isolated 5 V voltage Jumper JP7 can be installed to add a 120 Ohm termination resistor across the CAN data lines if needed refer to Table 1 6 Pin 6 GND CAN ISO 2 Pin 2 CANL 3 7 Pin 7 CANH 8 Pin 3 GND CAN ISO 4 9 5 Figure 22 CAN Connector X52 Signal Mapping PHYTEC Messtechnik GmbH 2013 1 773 2 97 phyFLEX i MX 6 PFL A XLI xxx 18 3 5 Ethernet Connectivity X28 Figure 23 Ethernet Interface at Connector X28 The Ethernet interface of the phyFLEX is accessible at the RJ 45 connector X28 on the carrier board Due to its characteristics this interface is hard wired and can not be configured via jumpers The LEDs for LINK green and SPEED yellow indication are integrated in the connector The Ethernet interface also supports Power over Ethernet PoE Please refer to section 18 3 2 2 for more information 98 PHYTEC Messtechnik GmbH 2013 1 7
134. xe 49 3mm 64mm 70mm D1 im amet E UOI pa D2 2mm mounting hole 5 26mm 44mm 5 93mm 5 08mm 4 88mm Figure 12 Footprint of the phyFLEX i MX 6 PHYTEC Messtechnik GmbH 2013 L 773e 2 73 6 PFL A XLI xxx 17 2 Handling the phyFLEX i MX 6 e Modifications on the phyFLEX Module Removal of various components such as the microcontroller and the standard quartz is not advisable given the compact nature of the module Should this nonetheless be necessary please ensure that the board as well as surrounding components and sockets remain undamaged while de soldering Overheating the board can cause the solder pads to loosen rendering the module inoperable Carefully heat neighboring connections in pairs After a few alternations components can be removed with the solder iron tip Alternatively a hot air gun can be used to heat and loosen the bonds Caution If any modifications to the module are performed regardless of their nature the manufacturer guarantee is voided Integrating the phyFLEX into a Target Application Successful integration in user target circuitry greatly depends on the adherence to the layout design rules for the GND connections of the phyFLEX module For maximum EMI performance we recommend as a general design rule to connect all GND pins to a solid groun
135. yFLEX Carrier Board See Section 18 3 2 18 3 16 and 18 3 20 18 3 11 18 3 8 3 18 3 3 and 18 3 20 Description Jumper JP11 allows to control the supply voltage of 5_ ofthe phyFLEX i MX 6 module VCCS5 X Voltage is off 5 X Voltage is on Jumper JP13 allows to route the signals of SDIOO either to the SD card slot X57 or to the Wi Fi Bluetooth connector X58 00 routed to the SD card slot X57 SDO routed to the Wi Fi Bluetooth connector X58 Jumper J9 connects the shield contact of audio Jack X9 headphone out to either GND or the HPCOM output driver of the stereo audio codec at U25 Connecting the shield contact to HPCOM allows using the jack detection function of the stereo audio codec Shield contact connected to GND jack detection disabled Shield contact connected to the HPCOM output driver of the stereo audio codec jack detection enabled Jumper J12 configures the PC address of the touch screen controller at U6 Touch Controller U6 Address 0x41 Touch Controller U6 Address 0x44 Jumpers J27 J30 connect the TTL signals of UARTI either to the RS 232 transceiver at U11 thus making UARTI available at DB 9 connector X50 at RS 232 level or to the Wi Fi Bluetooth module connector X58 at TTL level UARTI connected to Transceiver U11 UARTI connected to wifi Bluetooth module connector X58 phyFLEX Carrier Board Jumper Descriptions continued 87 L 773e 2 Jumper Settin

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