SMT365e User Manual - Sundance Multiprocessor Technology Ltd.
Contents
1. VO connectorr FPGA PROG control Primary TIM connector CPLD JTAG A eve AAR e 9 9 9 9 9 ete of ty a ete Oe ee ee 9 ee E e tots vc es ee orotate ee eet etes ees zh 0000 se H vent Exar e oe 5 5 Dad connector o ee E e 0 000 i ee ed rd ins s n 9 i den e ai ata Mi he bid de sesse Lec e e000 HE t FS me 2 2 r FPGA LEDs e eoeeee FPGA JTAG DSP LEDS 7 drr COO E OO og em 3 T m o Technology Lid DOC 9 949 OCC OCC OE OC ee te ete e ee ee ee ee ee ee AG Done LED Global TIM connector mm SHEE F pa LU DU SMTZ3ESE VI RE msn ad o OC TEL E DIN ON Mi e e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 e m a o a o ete et ee te oo e Ie 35 PS e Secondary TIM connector Version 2 1 Serial Ports amp Other C60 VO The C60 contains various I O ports These signals are connected to a 0 1 pitch DIL pin header The pin out of this connector is shown here Page 20 of 26 SMT365e User Manual T DY Tr O TV Ad gt oO DRO FSRO DXO FSXO CLKRO CLKXO CLKSO CLKS1 CLKX1 CLKR1 URA1 URAO URA3 URA4 URA2 DR2 FSR2 DX2 FSX2 CLKR2 CLKX2 CLKS2 DX1 FSX1 FSR1 DR1 UXAO GPIO8 UXA4 UXA3 UXA2 UXA12. D D 6 SHB connectors for high speed data transfer Intended Audience There are two existing versions of the firmware for the SMT365e For each of the versions of the different firmware is loaded in the FPGA Firmware version 1 1 or Firmware version 1 2 This user manual covers the version 1 2 of the firmware for the SMT365e implemented with the model described in the SMT6500 help file Refer to section Firmware versions Version 2 1 Page 7 of 26 SMT365e User Manual Block Diagram The following drawing shows the block diagram of the SMT365e module The main components of the SMT365e are A Texas Instruments DSP One Xilinx FPGA Virtex ll device 256MB of SDRAM DC DC Converters for DSP J1 Top Primary TIM and FPGA cores Connector Comm Port 0 amp 3 26 VO pins Timer amp Control 15 VO pins McBSP Utopia 2x Comm Ports SDL GPIO 4 LEDs amp 4VOpins FPGA Controller Virtex ll FF1152 Sundance High speed Bus 824 VO pins Used 776 60 way Samtec x 6 DEE ra Global Bus 74 VO pins 52 VO pins 4x Comm Port SDL J2 Bottom Primary TIM Connector Comm Port 1 2 5 4 Version 2 1 Page 8 of 26 SMT365e User Manual Architecture Description DSP The Texas Instruments DSP can r
3. SMT365E User Manual Certificate Number FM 55022 User Manual QCF42 Version 3 0 5 2 01 Sundance Multiprocessor Technology Ltd 2001 SMT365e User Manual Version 2 1 Page 2 of 26 Revision History Date Comments Engineer Version 20 01 03 Added FPGA pin out GP 1 0 3 31 01 03 Changed CPLD hdr pin out GP 1 0 4 Set DSP clk 600 emif clk 100 17 03 03 Added location of SDBs on the board 1 0 6 NES 19 09 03 Updated Data Sheets Hyperlinks section 1 0 8 aa Updated Reprogramming chapter Update the user manual supports the new 2 0 firmware implementation V3 0 XC2V6000 and the firmware V1 0 XC2V8000 Update the user manual supports the new 2 2 firmware implementation for 2xSDBs 32bits V3 12 XC2V6000 Version 2 1 Page 3 of 26 SMT365e User Manual Table of Contents Revision PISTON aia a ce tac NN SR GV tasses 2 Contacting Sundane ide 4 Notational CONVentiONnS ss Nis Ve NAN ER Ge NN A NIE Re N RANG RR UE n ed dk Ke sd ed 5 POP NE a EE m 5 EER d ED EE EE EE MD PEE 5 a aa een AA 5 Register Descriptions n EE in Di ed one 5 Outline Description ns N n cel dine ee e seen se ans sun 6 imende d ADR isa 6 Block Diagram iss eek EEN EA NE KG N GE N N N AK we N N a RE Re ed we N AE NR die 7 Architecture Description 8 SP o 8 BOOM cS 8 ase ees EA N EE EE 9 SDRAM EE M 9 FLASH SE DOE De DE GE GE EO De Dt GE EG
4. URDO URD1 URD2 URD3 URD4 URD5 URD6 URD7 URCLK URENB URCLAV URSOC UXDO UXD1 UXD2 UXD3 UXD4 UXD5 UXD6 UXD7 UXCLK UXENB UXCLAV UXSOC NC GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 V33 V33 TTL2 TTL3 GPIOO GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GND GND TTLO TTL1 FPGA and CPLD JTAG The following shows the pin outs for JP2 CPLD and JP3 FPGA JTAG connectors Signal Pin Pin Signal V33 1 TMS TCK TDO GND TDI Version 2 1 Page 21 of 26 SMT365e User Manual Virtex Memory Map define SMT365eCP0 volatile unsigned int 0x90000000 define SMT365eCP1 volatile unsigned int 0x90008000 define SMT365eCP2 volatile unsigned int 0x90010000 define SMT365eCP3 volatile unsigned int 0x90018000 define SMT365eCP4 volatile unsigned int 0x90020000 define SMT365eCP5 volatile unsigned int 0x90028000 define SMT365eCP0 STA volatile unsigned int 0x90004000 define SMT365eCP1 STA volatile unsigned int 0x9000C
5. The module must be fixed to a TIM40 compliant carrier board The SMT365e TIM is in a range of modules that must be supplied with a 3 3V power source In addition to the 5V supply specified in the TIM specification these new generation modules require an additional 3 3V supply to be presented on the two diagonally opposite TIM mounting holes The lack of this 3 3V power supply should not damage the module although it will obviously be inoperable prolonged operation under these circumstances is not recommended The SMT365e is compatible with all Sundance TIM carrier boards It is a 5V tolerant module and as such it may be used in mixed systems with older TIM modules carrier boards and VO modules Use of the TIM on SMT327 cPCI motherboards may require a firmware upgrade If LED D6 on the SMT365e remains illuminated once the TIM is plugged in and powered up the SMT327 needs the upgrade The latest firmware is supplied with all new boards shipped Please contact Sundance directly if you have an older board and need the upgrade The external ambient temperature must remain between 0 C and 40 C and the relative humidity must not exceed 95 non condensing Power Consumption The power consumption of this TIM is dependent on the operating conditions in terms of core activity and I O activity The maximum power consumption is 10W Version 2 1 Page 19 of 26 SMT365e User Manual Connector Positions DSP Boot mode
6. Pin Control JP7 connector SMT365e User Manual Jumper Position Can also be controlled by the DSP 1 2 2 3 Out PROG asserted PROG asserted for the PROG under control of continuously duration of RESET DSP DSP Boot Mode Control JP6 connector DSP will boot from flash Out DSP will be set to boot from HPI Version 2 1 Page 25 of 26 SMT365e User Manual Bibliography 1 Sundance Help file 2 SMT6400 help file DSP support package and SMT6500 help file FPGA support package 3 TMS320C6000 Peripherals Reference Guide literature number SPRU190 It describes common peripherals available on the TMS320C6000 digital signal processors This book includes information on the internal data and program memories the external memory interface EMIF the host port multichannel buffered serial ports direct memory access DMA clocking and phase locked loop PLL and the power down modes 4 TIM 40 MODULE SPECIFICATION Including TMS320C44 Addendum 5 SDB Technical Specification 6 SHB Technical Specification 7 TMS320C4x User s Guide literature number SPRU063 It describes the C4x 32 bit fixed point processor developed for digital signal processing as well as parallel processing applications Covered are its architecture internal register structure instruction set pipeline specifications and operation of its six DMA channels and six communication ports Software and hardware appl
7. define GLOBAL BUS STAR volatile unsigned int 0x90088000 define GLOBAL BUS LENGTH volatile unsigned int 0x90090000 Version 2 1 Page 22 of 26 SMT365e User Manual define SMT365eTCLK volatile unsigned int 0x900C0000 define SMT365eTIMCONFIG volatile unsigned int 0x900C8000 define SMT365eLED volatile unsigned int 0x900D0000 define SMT365eINTCTRLA volatile unsigned int 0x900E0000 define SMT365eINTCTRL4 EX volatile unsigned int 0x900E4000 define SMT365eINTCTRLS volatile unsigned int 0x900E8000 define SMT365eINTCTRL5 EX volatile unsigned int 0x900EC000 define SMT365eINTCTRL6 volatile unsigned int 0x900F0000 define SMT365eINTCTRL6 EX volatile unsigned int 0x900F4000 define SMT365eINTCTRL7 volatile unsigned int 0x900F8000 define SMT365eINTCTRL7_EX volatile unsigned int 0x900FC000 Version 2 1 Page 23 of 26 SMT365e User Manual SHB pin out SHB generic pin out QSH Pin number QSH Pin number USERDEFO USERDEF2 USERDEF1 USERDEF3 Note Hw is a short for Half word i e 16 bit Word This standard is implemented using SAMTEC QSTRIP 0 50mm Hi speed connectors Version 2 1 Page 24 of 26 FPGA PROG
8. 0 It implements the following communication resources e Six Comport interfaces e Four 16 bit Sundance Digital Bus interfaces e One Global Bus interface Version control Revision numbers for both the boot code and FPGA firmware are stored in the Flash ROM during programming as zero terminated ASCII strings The SMT6001 utility can be used to display the version numbers of the bootloader and the FPGA data Firmware versions The SMT6001 utility includes the latest version of the bootloader and the latest version of the FPGA data that implements the FPGA architecture described in the SMT6500 help file Customers who wish to use the old firmware can obtain it from our support web forum Reprogramming the firmware and boot code The contents of the flash ROM are managed using the SMT6001 utility This includes the latest firmware and bootloader along with complete documentation on how to reprogram the ROM The utility assumes that you have Code Composer Studio installed and that it has been configured correctly for the installed TIMs The Sundance Wizard can help you with this To confirm that the ROM has been programmed correctly you should run the confidence test in the BoardInfo utility SMT6300 Version 2 1 Page 12 of 26 SMT365e User Manual Comports The DSP has six comports numbered 0 to 5 The addresses of the Comport registers are described in the SMT6400 help file SHB The SMT365e has six SHB connectors all of
9. 000 define SMT365eCP2 STA volatile unsigned int 0x90014000 define SMT365eCP3 STA volatile unsigned int 0x9001C000 define SMT365eCP4 STA volatile unsigned int 0x90024000 define SMT365eCP5 STA volatile unsigned int 0x9002C000 define SMT365eGB STAT volatile unsigned int 0x90034000 define SMT365eSDB STA volatile unsigned int 0x90038000 define SMT365eSTAT volatile unsigned int 0x9003C000 define SMT365eSDBA volatile unsigned int 0x90040000 define SMT365eSDBB volatile unsigned int 0x90050000 define SMT365eSDBC volatile unsigned int 0x90060000 define SMT365eSDBD volatile unsigned int 0x90070000 define SMT365eSDBA STA volatile unsigned int 0x90048000 define SMT365eSDBB STA volatile unsigned int 0x90058000 define SMT365eSDBC STA volatile unsigned int 0x90068000 define SMT365eSDBD STA volatile unsigned int 0x90078000 define SMT365eSDBA INPUTFLAG volatile unsigned int 0x90044000 define SMT365eSDBB INPUTFLAG volatile unsigned int 0x90054000 define SMT365eSDBC INPUTFLAG volatile unsigned int 0x90064000 define SMT365eSDBD INPUTFLAG volatile unsigned int 0x90074000 define SMT365eSDBA OUTPUTFLAG volatile unsigned int 0x9004C000 define SMT365eSDBB OUTPUTFLAG volatile unsigned int 0x9005C000 define SMT365eSDBC OUTPUTFLAG volatile unsigned int 0x9006C000 define SMT365eSDBD OUTPUTFLAG volatile unsigned int 0x9007C000 define GLOBAL BUS volatile unsigned int 0x900A0000 define GLOBAL BUS CTRL volatile unsigned int 0x90080000
10. 1 requires it a Troubleshooting Our Knowledge data base and FAQ sections may help you to resolve some known issues Application Development Depending on the complexity of your application you can develop code for SMT365 modules in several ways SMT6400 For simple applications the Sundance SMT6400 software support package project examples and its associated header files SmtTim h and ModSup h can suffice The SMT6400 product is installed by the Sundance Wizard and it is free of charge 3L Diamond This module is fully supported by 3L Diamond which Sundance recommends for all but the simplest of applications A SMT365e has to be declared as appropriate in configuration files as one processor of type e SMT365E SMT6500 This is the support package for the FPGA It may be used to develop your application in the FPGA of the module Version 2 1 Page 18 of 26 SMT365e User Manual Operating Conditions Safety The module presents no hazard to the user EMC The module is designed to operate within an enclosed host system that provides adequate EMC shielding Operation within the EU EMC guidelines is only guaranteed when the module is installed within an appropriate host system The module is protected from damage by fast voltage transients introduced along output cables from outside the host system Short circuiting any output to ground does not cause the host PC system to lock up or reboot General Requirements
11. D LED LED D11 D12 D13 D14 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 The four remaining LEDs D2 5 are connected to the C60 s GPIO pins 12 15 Version 2 1 Page 14 of 26 SMT365e User Manual CONFIG amp NMI The TIM specification describes the operation of an open collector type signal CONFIG that is driven low after reset This signal on a standard C4x based TIM is connected to the processor s IIOF3 pin On the SMT365 the CONFIG signal is asserted after power on and can be released by writing the value 1 lt lt 6 to the config register Conversely CONFIG may be re asserted by writing 0 to this bit It is not possible for software to read the state of the CONFIG signal The NMI signal from the TIM connector can be routed to the DSP NMI pin WARNING Several software components include code sequences that assume setting GIE 0 in the DSP CSR will inhibit all interrupts NMI violates that assumption If an NMI occurs during such code sequences it may not be safe to return from the interrupt This may be particularly significant if you are using the compiler s software pipelining facility Config Register 31 8 7 i i NMI CONFIG Field Description i NFIG I CONFIG 0 dive CONFIG low 1 tri state CONFIG NMI O Disconnect NMI from the DSP 1 Connect NMI from TIM to the DSP Config and NMI DSP lines are described in the SMT6400 help file Version 2 1 Page 15 of 26 SMT365e User Manual Timer The TIM TCLKO a
12. De N aan 10 Vitex FPGA erre 11 EES olie A 11 Firmware VEFSIONS cinc EEN NAN Ek RS Ge Ne ed N NE ie ee Ee Gee RA N de Ke Ge N ee 11 Reprogramming the firmware and boot code esse ER RR EE EER EE ERGE 11 Boys ele AE OE N OE OR OR N N i acl EN Ee 12 o ooo uo ne 12 Global US 12 LED SE N Hede ase ee ee N Ge GE GN NC e Ge eN ER RO ie 13 LED eis a EE EE e nnmnnn 13 CONFIG amp NMI sesse sesse ek GE N GE N ES dd KW N N NR KA N NAKA Ee N GE 14 Config sies RE AE a EE 14 TEE AGA Ee ea AG ea a dus 15 Ende nige bees AE UU kae tobias 15 le digi rin 16 Code COMPOSE sion 17 Version 2 1 Page 4 of 26 SMT365e User Manual Application Development nn 17 OU KO PR EE OE AAO GA 17 c MI tae 17 SIE bs 17 Operating CONGITIONS em M 18 EA 18 EME emmener S DR UU 18 General Requirements oaa epo epu EERSTE ERK ena saa een EER EER RGN ERR V oen S EDEN ROK EE Rd 18 Power ConsBUmplloliasuss soie ce DE EE bett tos iodo idos 18 Connector Positions Xa N EE In EE RAS KEN Eo IS Se GER Ed KAN EI IUE ER EN GR DEIN MEM UR URS ENE kk n n 19 Serial Ports amp Other C60 VO ii sans osse kk GR d p Medi AN KI MM N UP EPI Ki N N ae n 20 FPGA and CPLD J AG e ee ns DEN DNI DICEN E 20 Virtex Memory Mapua AAAH 21 O 23 SHB deneli PINK AN 23 FPGA PROG Pin Control JP 7 CONNECTION si corr rene sesse sees se oe ee Ee ee 24 DSP Boot Mode Control JPO CODPgCEor iss REK e b o e e Rui 24 Bibliograp
13. at 133MHz maximum It operates at one sixth of the core clock speed The EMIFA CEO memory space control register should be programmed with the value 0x000000D0 64 bits SDRAM Version 2 1 Page 10 of 26 SMT365e User Manual FLASH 4MB of Flash ROM is connected to the DSP in the EMIFB CE1 amp CE2 memory spaces The ROM holds boot code for the DSP configuration data for the FPGA and optional user defined code The EMIFB CE1 and CE2 space control registers should be programmed with the values 0x00000030 and OxFFFFFF23 respectively As the DSP only provides 20 address lines on its EMIFB both CE1 amp CE2 are used to access this device This in itself allows the direct access to 2MB A paging mechanism is used to select which half of the 4MB device is visible in this 2MB window As the EMIFB CE1 amp CE2 memory spaces alias throughout the available range the flash device can be accessed using the address range 0x67E00000 0x681FFFFF This gives a 2MB continuous memory space Selecting the visible flash memory page 2 pages of 2MB involves writing to the following addresses as shown the data written is irrelevant Address Flash page selected 0x60000000 Page 0 0x60000100 Page 1 The EMIFB CEO memory space control register should be programmed with the value OxFFFOCO03 Version 2 1 Page 11 of 26 SMT365e User Manual Virtex FPGA The FPGA Field Programmable Gate Array is a Xilinx Virtex ll device XC2V600
14. gure the FPGA following reset assuming a 600MHz clock The external devices implemented in the FPGA such as comports must not be used during this configuration It is safest to wait for the configuration to complete Note that comports will appear to be not ready until the FPGA has been configured The FPGA programming algorithm is not described here It can be found in the boot code Version 2 1 Page 9 of 26 SMT365e User Manual EMIF Control Registers The DSP has two external memory interfaces EMIF which are 64 bits wide and 16 bits wide The DSP contains several registers that control the external memory interface EMIF A full description of these registers can be found in the DSP C6000 Peripherals Reference Guide The standard bootstrap will initialise these registers to use the following resources Memory space Resource Address range EMIFA Internal program memory 0x00000000 OxOOOFFFFF 1MB CEO SDRAM 0x80000000 Ox8FFFFFFF CE1 Virtex 0x90000000 Ox9FFFFFFF Memory space Resource Address range EMIFB CEO Flash paging control 0x60000000 0x60000200 CE1 4MB Flash 1 half 0x64000000 0x640FFFFF CE2 4MB Flash 2 half 0x68000000 0x680FFFFF CES FPGA Configuration control 0x6C000000 0x6C000002 SDRAM Memory space CEO is used to access 256MB of SDRAM over EMIFA The speed of the SDRAM is dependent on the processor variant Using the C6416 the SDRAM will operate
15. hy aaa 25 le SE EN ER EE ta 26 Contacting Sundance You can contact Sundance for additional information by login onto the Sundance Support forum Version 2 1 Page 5 of 26 SMT365e User Manual Notational Conventions DSP The terms DSP C64xx and TMS320C64xx will be used interchangeably throughout this document SDB The term SDB will be used throughout this document to refer to the Sundance Digital Bus interface SHB The term SHB will be used throughout this document to refer to the Sundance High speed Bus interface Register Descriptions The format of registers is described using diagrams of the following form 31 24 23 16 15 8 7 0 OFLAGLEVEL R 00000000 RW 10000000 R 00000000 R 10000000 The digits at the top of the diagram indicate bit positions within the register and the central section names bits or bit fields The bottom row describes what may be done to the field and its value after reset Shaded fields are reserved and should only ever be written with zeroes R Readable by the CPU W Writeable by the CPU RW Readable and writeable by the CPU Binary digits indicate the value of the field after reset Version 2 1 Page 6 of 26 SMT365e User Manual Outline Description The SMT365 is a DSP module size 2 TIM offering the following features D TMS320C6416 processor running at 600MHz Six comports 256MB of SDRAM 100MHz 4MB of Flash ROM Global Bus connector D D DO
16. ications are included 8 Xilinx Virtex ll datasheet 9 TMSC6416 datasheet Version 2 1 INDEX A Application Development 17 Architecture Description 8 B Bibliography 25 Block Diagram 7 Boot Mode 8 C Code Composer 17 Comport 12 CONFIG amp NMI 14 E EMIF Control Registers 9 F Firmware Reprogramming 11 Firmware versions 11 Flash 10 I IIOF lines 16 L LEDs 13 Page 26 of 26 SMT365e User Manual LED register 13 N Notational Conventions 5 O Operating Conditions 18 P Power consumption 18 R Register Descriptions 5 S SDRAM 9 Serial Ports 20 SHB 12 SMT6400 17 SMT6500 17 T Timer 15 V Version Control 11 Virtex memory map 21
17. nd TCLK1 signals can be routed to the DSP s TOUT TINP pins The signal direction must be specified together with the routing information in the timer control register Timer Control Register 31 6 5 4 3 0 Reserved TCLK1 TCLKO Reserved Field Description TOLKO O TIM TCLKO is an input 1 Enable TIM TCLKO as an output IM TCLK1 i i TCLKi 0 T C is an input 1 Enable TIM TCLK1 as an output If the TIM TCLKx pin is selected as an output the DSP TOUTx signal will be used to drive it The TIM TCLKx pin will always drive the DSP TINPx input TCLKOEN The Timer control register is described in the SMT6400 help file Version 2 1 Page 16 of 26 SMT365e User Manual IIOF interrupt The firmware can generate pulses on the external interrupt lines of the TIM Only the interrupt line IIOF1 and IIOF2 are connected from to the DSP and the HOST e IOF1 is connected from the DSP side to the HOST side so the DSP interrupts the HOST e IOF2 is connected from the HOST side to the DSP side so the HOST interrupts the DSP The IIOF interrupt lines are described in the SMT6400 help file Version 2 1 Page 17 of 26 SMT365e User Manual Code Composer This module is fully compatible with the Code Composer Studio debug and development environment This extends to both the software and JTAG debugging hardware The driver to use is the tixds64xx 11 dvr CCS version 3 0 or later is required as the reprogramming utility SMT600
18. un at up to 600MHz The DSP is doted of 256MB of Synchronous DRAM SDRAM The DSP is a TMS320C6416 type This is a fixed point digital signal processor provided by Texas Instruments The processor will run with zero wait states from internal SRAM The internal memory is 1MB in size and can be partitioned between normal SRAM and L2 cache An on board crystal oscillator provides the clock used for the DSP which them multiplies this by twelve internally Boot Mode The DSP is connected to the on board flash ROM that contains the Sundance bootloader and the FPGA bitstream Following reset the DSP will automatically load the data from the flash ROM into its internal program memory at address O and then start executing from there All this code is the Sundance bootloader and it is made up of two parts FPGA configuration and processor configuration FPGA configuration uses data in the ROM to configure the FPGA A processor configuration sets the processor into a standard state by writing into the DSP internal registers of the EMIF Then it configures the FPGA from the data held in the flash ROM The bootloader is executed It will continually check the six comports until data appears on one of them This will next load a program in boot format from this comport Note that the bootloader will not read data arriving on other comports Finally the control is passed to the loaded DSP application The DSP will take approximately about 46s to confi
19. which are connected to the DSP to give 16 bit 32 bit SDB interfaces on two SHB connectors These interfaces operate with a fixed clock rate of 100MHz Note that the four other SHB connectors are not used The following figure shows their localisation on the board Global bus The SMT365e provides a single global bus interface This is only accessible from the DSP The addresses of the global bus registers are shown in the Virtex Memory Map and are described in the SMT6400 help file Version 2 1 Page 13 of 26 SMT365e User Manual LED Setting The SMT365e has 13 LEDs One shows the FPGA configuration status and the other 4 are under DSP control LED D6 always displays the state of the FPGA DONE pin This LED is off when the FPGA is configured DONE 1 and on when it is not configured DONE 0 This LED should go on when the board is first powered up and go off when the FPGA has been successfully programmed this is the standard operation of the boot code resident in the flash memory device If the LED does not light at power on check that you have the mounting pillars and screws fitted properly If it stays on the DSP is not booting correctly or is set to boot in a non standard way Four of the remaining LEDs can be controlled with the LED register D11 D12 D13 D14 Writing 1 will illuminate the LED writing 0 will turn it off Note that the LEDs D7 D10 are not used LED Register 0x900D0000 31 4 7 6 5 4 3 2 1 0 LED LE
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