73S8024C Demo Board User Manual
Contents
1. i SCLK P 1 1 SIO 5 2 XTALIN sca 3 SELECT 4 OFFB 5 XTAL GND b GND 5v agy JP 5 0V 5v a NS VPC 2 must be SELECT SSM 110 L SV set to 3 3V 3 3v 5V R1 Q Resistors not 2 populated SCLK R2 5 510 Cl C2 C8 C9 and 11 must be TPI Signal names 3 ES 5mm of the Ul pins 0 4 feter Es 4 INT and connected by thick track J 10uF PGND R3 2 7351121 5 wider than 0 5mm ai PIN18 12 000MHz Evaluation 6 GND C2 0 1uF board TP2 11 must rend 1mustbe QL1 8 5 0V aa placed clos o sv Es pin L ou TF O Ut TSM 110 01 1 SV E 5 1 28 CLKDIV1 AUX2UC pit 27 CLKDIV2 auxiuc 27 1 1OUC CLKDIVI 2 1 GND 4 XTALOUT e CLKDIV2 3 LIN XTALIN E 4 T 81 vec OFF 28 3 3w 5 N GND b 1 PWRDN 6 1 8 pwann 21 E2. Name Pin Description XTALIN 24 Crystal oscillator input can either be connected to crystal or driven as a source for the card clock XTALOUT 25 Crystal oscillator output connected to crystal Left open if XTALIN is being used as external clock input VDDF_ADJ 18 fault threshold adjustment input this pin can be used to adjust the values controls deactivation of the card Must be left open if unused NC 5 7 Non connected pin Table 6 7358024C Power and Ground Pins Name Pin Description VDD 21 System interface supply voltage and supply voltage for internal circuitry VPC 6 DC DC converter power supply source GND 4 DC DC converter ground GND 22 Digital ground LIN 5 External inductor Connect external inductor from pin 2 to VPC Keep the inductor close to pin 2 Table 7 72S8024C Microcontroller Interface Pins Name Pin Description CMDVCC 19 Command VCC negative assertion Logic low on this pin causes the LDO regulator to ramp the Vcc supply to the card and initiates a card activation sequence if a card is present 5V 3V 3 5 volt 3 volt card selection Logic one selects 5 volts for Vcc and card interface logic low selects 3 volt operation When the part is to be used with a single card voltage this pin should be tied to either GND or Vpp However it includes a high impedance pull up resistor to default this pin high
3. selection of 5V card when not connected PWRDN 8 Power Down control input Active high When the Power Down mode is set high all internal analog functions are disabled to place the 73S8024C in its lowest power consumption mode The Power Down mode is only allowed out of a card session i e when CMDVCC 1 CLKDIV1 1 Sets the divide ratio from the XTAL oscillator or external clock input to the CLKDIV2 2 card clock These pins include pull down resistors CLKDIV1 CLKDIV2 CLOCK RATE 0 0 XTALIN 8 0 1 XTALIN 4 1 1 XTALIN 2 1 0 XTALIN OFF 23 Interrupt signal to the processor Active low multi function indicating fault conditions and or card presence Open drain output configuration includes an internal 22 pull up to RSTIN 20 Reset Input This signal is the reset command to the card OUC 26 System controller data I O to from the card Includes a pull up resistor to AUX1UC 27 System controller auxiliary data I O to from the card Includes a pull up resistor to Vpp AUX2UC 28 System controller auxiliary data I O to from the card Includes a pull up resistor to Rev 1 3 UM_8024C_061 7358024C Demo Board User Manual 3 4 73S8024C Pinout CLKDIV1 1 AUX2UC CLKDIV2 2 AUX1UC 5V 3V OUC GND XTALOUT LIN XTALIN VPC OFF NC GND 73S8024C PWRDN VDD PRES RSTIN PRES CMDVCC yo VDDF ADJ AUX2 vec AUX1 RST GND CLK Figure 4 7358024C 5028 Pinout Top View Rev 1 3 11
4. ouc GND AUX1 UC o RSTIN AUX2UC CMDVCC OFF PWRDN 5V 3V GND CKDIV2 CKDIV1 Vpc Power Supply Configure JP2 7 to 3 3V Note CLKSTOP and CLKLEV can be left NC if unused 5V 3V too for 5V cards only Figure 2 7358024C Demo Board Basic Connections 6 Rev 1 3 UM_8024C_061 7358024 Demo Board User Manual 3 Hardware Description 3 1 Demo Board Connectors Jumpers and Test Points Table 1 describes the 73S8024C Demo Board connectors jumpers and test points The Item in Table 1 refers to Figure 3 Table 1 7358024C Demo Board Connector Jumper and Test Points Schematic p Silkscreen Name Function Reference Connectors 1 J2 5V Board Supply 7358024C auxiliary interface I OUC AUX1UC Auxiliary Interface AUX2UC external clock SCLK and interrupt OFF pins The external clock SCLK can be left open when JP1 is in position XTAL The 5V power supply is unused and must be left open and JP2 must be inserted in position 3 3V 9 J4 3 3V Board Power 3 3V board power supply and the 73S8024C host Digital Control control signals RSTIN CMDVCC 5V 3V PWRDWN Signals CLKDIV2 and CLKDIV1 16 J5 Smart Card Smart card connector Connector When inserting a card credit card size format contacts must face up 11 J6 Smart Card SIM SAM smart card format connector Connector J6 is wired in parallel to the smart card connector J5 underneath the PCB No SIM SAM
5. 7358024 Demo Board User Manual UM_8024C_061 4 Design Considerations 4 1 General Layout Rules e Route the auxiliary signals away from card interface signals e Keep the CLK signal as short as possible and with few bends in the trace Keep the route of the CLK trace to one layer avoid vias to other plane Keep the CLK trace away from other traces especially RST and VCC Filtering of the CLK trace is allowed for noise purpose Up to 30 pF to ground is allowed at the CLK pin of the smart card connector In addition the zero ohm series resistor R7 can be replaced for additional filtering no more than 100 e Keep the VCC trace as short as possible Make the trace a minimum of 0 5 mm thick In addition keep the VCC away from other traces especially RST and CLK e Keep the trace from L1 to pin 5 of the IC as short as possible e Keep the RST trace away from the VCC and CLK traces Up to 30 pF to ground is allowed for filtering e Keep the 0 1 uF capacitor close to the VDD pin of the device and directly take the other end to ground e Keep the 0 1 uF capacitor close to the VPC pin of the device and directly take the other end to ground e Keep the 3 3 uF 1 0 uF for NDS capacitor close to the VCC pin of the smart card connector and directly take other end to ground 4 2 Optimization for Compliance with EMV and NDS The default configuration of the demo board contains a 27 pF capacitor C12 from the CLK pin of the smart conne
6. RAN 2 VDD CMDVCCB 7 H Pres BSTN 20 8 V m 3 SELEC RSTIN 8 VDD 11 PRES CMDVCC Hg duE GND 9 gt T 27 vo VDDF ADJ Ty gt 5v 3 3V 10 AUX2 vec 13 16 JP3 must be SSM 110 L SV 14 A a E 15 set to 3 3V R7 J4 R5 R6 USRO Y eg 1 i USR1 0 47uF Signal names H USR2 P4 73580240 0 refer to i USAS i 1 5 USRS 7 ki R8 R9 Evaluation USR6 Ru Ru board 7 9587 HEADER LOCK 3NZ ES ci 8 GND 27pF 4 Resistors 3 3V not 10 J Gi l populated TSM 110 O1 L SV VTOUF SE R10 Gi Rit 12 0 tuF Rd Rd Connectors are positioned to allow a if vec multiple 8024C boards stacking to a TP4 7351121 evaluation board Also used for a 1 4 5 connecting external signals when used as a 1 0 e T 1 RST 1 stand alone board TPS 2 TP3 to TPB to be placed JP5 PRESB 1 4 very close to the pads 1 C8 2 4 4 1 of 25 gt 475 3 Z TP8 PRES 1 ls la e CARD DETECT lt gt POLARITY SELECT 1 1 JP6 ND c12 1 27pF 2 VDD 1 8 1 d VDD an inis Card detection ar qr switches are 05820520 ODAN normally open oo J5 J6 Smart Card Connector SIM SAM Connector Figure 5 7388024C Demo Board Electrical Schematic Rev 1 3 13 7358024 Demo Board User Manual UM_8024C_061 5 2 Bill of Materials Table 8 provides the bill of materials for the 7358024C Demo Board schematic provided in Figure 5 Table 8 73S8024C Demo Board Bill of M
7. should be inserted when using the credit card size connector J5 Jumpers 3 JP1 Clock Selection Jumper to select between a crystal or an external clock as the frequency reference to the device The default setting is for a crystal 17 JP2 VPC Select Jumper to select the value of the power supply for the smart card DC DC converter 73S8024C input VPC To support both card voltages JP2 must be set to position 3 3V The default setting is 3 3V 2 JP3 VDD Select Jumper to select the digital voltage which supplies the 7358024C Must be set for 3 3V 8 JP4 Not used 15 JP5 Card Polarity The setting of JP5 and JP6 depends on the type of 14 JP6 Detect Select smart card connector used nominally open or closed and which 73S8024C card presence switch input is used The switch is nominally open for the 73S8024C Demo Board The jumpers can be set to 1 Use of PRES default JP5 set to PRES JP6 set to VDD 2 Use of PRES JP5 set to PREB JP6 set to GND Rev 1 3 7358024 Demo Board User Manual UM_8024C_061 Schematic pu Silkscreen Name Function Reference Test Points 10 TP1 Pin 17 VDDF ADJ VDD voltage fault adjustment The pin to the left is connected to the VDDF ADJ pin of the 73S8024C and the pin to the right is GND When either a resistor R3 or a resistor network R1 and is populated on the board it adjusts the VDD fault level that internally triggers a card deactivation se
8. 24 Demo Board User Manual Revision History Revision Date Description 1 0 6 8 2004 First publication 1 1 8 2 2004 Minor corrections 1 2 8 23 2005 Added new logo 1 3 11 11 2009 Added Section 1 1 Package Contents Added Section 1 2 Safety and ESD Notes Added Section 6 Ordering Information Added Section 7 Related Documentation Added Section 8 Contact Information Miscellaneous editorial changes Rev 1 3 19
9. 288024C Microcontroller Interface Pins 10 Table 8 7358024C Demo Board Bill of 14 Table 9 Order Numbers and Packaging 18 Rev 1 3 UM_8024C_061 7358024C Demo Board User Manual 1 Introduction The 73S8024C Demo Board is a platform for evaluating the Teridian 7358024C Smart Card Interface device The board incorporates the 73S8024C integrated circuit and has been designed to operate either as a standalone platform to be used in conjunction with an external microcontroller or as a daughter card to be used in conjunction with the 7351121F evaluation platform The board has been designed to comply with the EMV 2000 Specification Version 4 0 7358024C Demo Boards can easily be modified to comply with NDS specifications by replacing a few external components that are highlighted in this document TERIDIAN T Y mo R13 Figure 1 7358024 Demo Board 1 1 Package Contents The 7388024C Demo Board Kit includes e 7388024C Demo Board e The following documents on CD e 7358024C Data Sheet e 7358024 Demo Board User Manual this document e Application Note 1 2 Safety and ESD Notes Extreme caution should be taken when handling the 73S8024C Demo Board after connection to live voltages lt The 73S8024C Demo Board is ESD sensitive ESD precautions should be tak
10. 5 1 10 Package Contents d uelitietetels 5 172 Safety ESD NOES orrein ce 5 Basic Connection E E dada dd dd a dd aux 6 Hardware 7 3 1 Demo Board Connectors Jumpers and Test Points 7 3 2 Recommended Operating Conditions and Absolute Maximum 5 9 73580246 Pin DescriptlOn tee rt t br Ho Eat re 9 3 4 739580240 PinOUt ete ett rtr rrr rre e redire reat Aaa aa e Mang 11 Design Considerations U Uu uu u u J J 12 4 1 General Layout Rules ie ae 12 4 2 Optimization for Compliance with EMV and NDS a 12 73S8024C Demo Board Schematics PCB Layouts and Bill of Materials 13 Belt S CH EM aIO t nan m Ble Su E EEE 13 5 2 Billo VS Ora S u uu eel ll randa 14 5 3 PGB EayOUts u o nt nas eee Plaid ae da dada Q k kau k debt dota 15 Ordering Information 18 Related Documentation J J J J 18 Contacto a 18 0 niit iaa 19 Rev 1 3 3 7358024 Demo Board User Manu
11. al UM_8024C_061 Figures Figure 1 7388024 C Demo Board iiit Ion 5 Figure 2 7358024 Demo Board Basic Connections 6 Figure 3 7358024 Demo Board Connectors Jumpers and Test 8 Figure 4 7358024 5028 Pinout Top View a 11 Figure 5 7388024C Demo Board Electrical 13 Figure 6 7358024C Demo Board View a 15 Figure 7 73S8024C Demo Board Bottom View nennen 15 Figure 8 73S8024C Demo Board Top Signal Layer 16 Figure 9 73S8024C Demo Board Middle Layer 1 Ground Plane nono 16 Figure 10 7358024 Middle Layer 2 Supply Plane 17 Figure 11 7358024C Demo Board Bottom Signal 17 Tables Table 1 7358024C Demo Board Connector Jumper and Test 7 Table 2 Recommended Operating Conditions 9 Table 3 Absolute Maximum 5 9 Table 4 7358024C Card Interface 5 9 Table 5 7358024C Miscellaneous PINS isi rsrsrsr enerne erene aaee Eanan aaa aeii 10 Table 6 7358024C Power and Ground Pins a 10 Table 7 7
12. aterials Digikey Part Item Quantity Reference Part PCB Footprint Number Part Number Manufacturer 1 3 C1 C3 C10 10 uF 805 PCC2225CT ND ECJ 2FB0J106M Panasonic 2 2 C2 C8 0 1 uF 603 PCC1762CT ND ECJ 1VB1C104K Panasonic 3 2 C4 C5 22 pF 603 PCC220ACVCT ND ECJ 1VC1H220J Panasonic 4 1 C11 3 3 HF 805 PCC1925CT ND ECJ 2YB0J335K Panasonic 5 2 C12 C13 27 pF 402 PCC270CQCT ND 0 1 270 6 1 L1 10 uH X SLF6025 TDK 7 5 JP1 JP2 JP3 JP5 HEADER 3 3pins 2 54 mm S1011 36 ND PZC36SAAN Sullins JP6 pitch 8 1 JP4 Header Lock 3 3pins 2 54 mm WM2701 ND 22 11 2032 Molex pitch 9 2 91 93 SSM 110 L SV SSM 110 L SV X SSM 110 L SV Samtec 10 2 J2 J4 TSM 110 01 SV TSM 110 01 SVX TSM 110 01 L S Samtec V 11 1 J5 Smart Card CCMO2 2504 ccm02 2504 ND ccm02 2504 ITTCannon Connector 12 1 J6 SIM SAM Connector ITT CCMO03 3754 CCMO3 3754CT ND CCM03 3754 ITTCannon 13 3 R2 R4 R7 0 603 PO 0GCT ND ERJ 3GEYOROOV Panasonic 14 2 R5 R6 X 603 X X 15 4 R1 R8 R9 R10 Ru 603 X X 16 4 R3 R11 R12 R13 Rd 603 X X 17 8 TP1 TP2 TP3 TP4 2 2X1_Header 1011 36 ND PZC36SAAN Sullins TP5 TP6 TP7 TP8 18 1 U1 7358024 28SOP X 7358024 Teridian Semiconductor 19 1 Y1 12 000 MHz HC 49US X190 ND ECS 120 20 4DN ECS 20 2 C4 C5 22 pF 603 PCC220ACVCT ND ECJ 1VC1H220J Panasonic Ru and Rd are not populated on the board They can be implemented to adju
13. ayn ER DIAN Simplifying System Integration 7358024C Demo Board User Manual November 11 2009 Rev 1 3 UM_8024C_061 7358024 Demo Board User Manual UM_8024C_061 2009 Teridian Semiconductor Corporation All rights reserved Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation Simplifying System Integration is a trademark of Teridian Semiconductor Corporation All other trademarks are the property of their respective owners Teridian Semiconductor Corporation makes no warranty for the use of its products other than expressly contained in the Company s warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions The company assumes no responsibility for any errors which may appear in this document reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein Accordingly the reader is cautioned to verify that this document is current by comparing it to the latest version on http www teridian com or by checking with your sales representative Teridian Semiconductor Corp 6440 Oak Canyon Suite 100 Irvine CA 92618 TEL 714 508 8800 FAX 714 508 8877 http www teridian com 2 Rev 1 3 UM_8024C_061 7358024C Demo Board User Manual DONO Table of Contents I irad cll dad
14. ctor to ground and a 27 pF capacitor C13 from the RST pin of the smart connector to ground These capacitors serve as filters for the CLK and RST signals in the case of long traces or test equipment perturbations The capacitor on CLK reduces ringing on the trace reduces coupling to other traces and slows down the edge of the CLK signal The capacitor on RST helps the perturbation specification in a noisy environment The filter capacitors can be useful in the EMV test environment and have no effect on NDS testing C12 and C13 are represented on both the schematic and the BOM These capacitors are optional filter capacitors on the smart card lines CLK and RST respectively for each card interface These capacitors may be adjusted value not to exceed 30 pF or removed to optimize performance in each specific application PCB card clock frequency compliance with applicable standards etc The default VCC capacitor of 3 3 uF is required to meet the dynamic VCC smart card supply transient current requirement as specified in the EMV2000 version 4 0 specification For compliance with NDS a smaller capacitor of 1 uF is required to meet the activation discharge time specification 12 Rev 1 3 UM 8024C 061 7358024 Demo Board User Manual 5 7358024 Demo Board Schematics PCB Layouts and Bill of Materials 5 1 Schematic
15. en when handling this board Rev 1 3 7358024 Demo Board User Manual UM_8024C_061 2 Basic Connections The basic connections to the demo board are described below and shown in Figure 2 1 Connect power supply Apply 3 3 V to pin 10 of J4 2 Control signals to the device can be connected through J2 and J4 see Figure 2 and the Electrical Schematic Figure 5 3 To set the clock frequency with an external clock source e Set to the SCLK setting e Apply clock source to pin 1 of J2 e Apply 3 3 1 or GND 0 to CLKDIV1 and CLKDIV2 pins to set the desired clock rate as follows gt CLKDIV1 CLKDIV2 0 clock frequency SCLK 8 gt CLKDIV1 0 CLKDIV2 1 clock frequency SCLK 4 gt CLKDIV1 1 CLKDIV2 0 clock frequency SCLK gt CLKDIV1 CLKDIV2 1 clock frequency SCLK 2 4 To set the clock frequency using crystal Y1 e The crystal included on the demo board is 12 MHz e Set to XTAL position e Apply 3 3V 1 or GND 0 to CLKDIV1 and CLKDIV2 pins to set the desired clock rate as follows gt CLKDIV1 CLKDIV2 0 clock frequency 1 5 MHz gt CLKDIV1 0 CLKDIV2 1 clock frequency MHz gt CLKDIV1 1 CLKDIV2 0 clock frequency 12 MHz gt CLKDIV1 CLKDIV2 1 clock frequency 6 MHz External clock source JP1 must be in position SCLK when using an external clock Otherwise pin SCLK can be left open 1 Vpp Power Supply 2 7V to 3 6V 3 3V 50mA SCLK dt VDD
16. ge 0 3 to VDD 0 5 VDC Pin Current 100 mA ESD Tolerance Card interface pins 6 kV ESD Tolerance Other pins 2 kV ESD testing on Card pins is HBM condition 3 pulses each polarity referenced to ground 3 3 73S8024C Pin Description Table 4 73S8024C Card Interface Pins Name Pin Description 1 0 11 Card I O Data signal to from card Includes a pull up resistor to Vcc AUX1 13 AUX1 Auxiliary data signal to from card Includes a pull up resistor to Voc AUX2 12 AUX2 Auxiliary data signal to from card Includes a pull up resistor to Voc RST 14 Card reset provides reset RST signal to card CLK 15 Card clock provides clock signal CLK to card The rate of this clock is determined by crystal oscillator frequency or external clock input and CLKDIV selections PRES 10 Card Presence switch active high indicates card is present Should be tied to GND when not used but it includes a high impedance pull down resistor PRES 9 Card Presence switch active low indicates card is present Should be tied to Vpp when not used but it includes a high impedance pull up resistor VCC 17 Card power supply logically controlled by sequencer output of LDO GND 14 Card ground Rev 1 3 regulator Requires an external filter capacitor to the card GND 7358024 Demo Board User Manual UM_8024C_061 Table 5 73S8024C Miscellaneous Pins
17. quence By default the resistors R1 and R3 are not connected This provides a VDD fault level of 2 3V typical internally set to the 73S8024C Refer to the 73S8024C Data Sheet for further information about VDD fault level and determination of the resistor values 20 TP2 Factory Test Factory test pin Do not connect 7 TP3 VCC 2 pin test points for each respective smart card signal 12 TP4 1 0 The pin label name is the respective signal i e VCC 6 TP5 RST CLK and the 2nd pin is GND 13 TP6 C8 5 TP7 CLK 4 TP8 C4 Se Po 5 8 Figure 3 7358024C Demo Board Connectors Jumpers and Test Points Rev 1 3 UM_8024C_061 7358024 Demo Board User Manual 3 2 Recommended Operating Conditions and Absolute Maximum Ratings Table 2 lists the recommended operating conditions and Table 3 lists the absolute maximum ratings Operation outside these rating limits may cause permanent damage to the device Table 2 Recommended Operating Conditions Parameter Rating Supply Voltage Vpp 2 7 to 3 6 VDC Supply Voltage Vpc 2 7 to 3 6 VDC Ambient Operating Temperature 40 C to 85 Input Voltage for Digital Inputs 0 V to 0 3 V Table 3 Absolute Maximum Ratings Parameter Rating Supply Voltage Voo 0 5 to 4 0 VDC Supply Voltage Vpc 0 5 to 4 0 VDC Input Voltage for Digital Inputs 0 3 to VDD 0 5 VDC Storage Temperature 60 C to 150 Pin Volta
18. st the features of the smart card reader 14 Rev 1 3 UM 8024C 061 7388024C Demo Board User Manual 5 3 PCB Layouts Figure 7 73S8024C Demo Board Bottom View Rev 1 3 7358024 Demo Board User Manual UM_8024C_061 e 2308 ly e e e e e Figure 9 73S8024C Demo Board Middle Layer 1 Ground Plane Rev 1 3 UM_8024C_061 7358024C Demo Board User Manual Ld Li Ld Ld e e e e Figure 11 73S8024C Demo Board Bottom Signal Layer Rev 1 3 17 7358024 Demo Board User Manual UM_8024C_061 6 Ordering Information Table 9 lists the order number used to identify the 7358024C Demo Board Table 9 Order Numbers and Packaging Marks Part Description Order Number 7358024 28 Pin SO Demo Board 7388024C DB 7 Related Documentation The following 7358024 documents are available from Teridian Semiconductor Corporation 7358024C Data Sheet 7358024 Demo Board User Manual this document Teridian 73S8024C versus Philips TDA8024T Application Note 8 Contact Information For more information about Teridian Semiconductor products or to check the availability of the 7358024 contact us at 6440 Oak Canyon Road Suite 100 Irvine CA 92618 5201 Telephone 714 508 8800 FAX 714 508 8878 Email scr support teridian com For a complete list of worldwide sales offices go to http www teridian com 18 Rev 1 3 UM_8024C_061 73580
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