freedm-32p672 development kit board user manual
Contents
1. 13 2 11 JUMPER SETTINGS FOR ENABLING OF RCLK 31 16 15 2 12 JUMPER SETTINGS FOR ENABLING OF TCLK 15 0 17 2 13 JUMPER SETTINGS FOR ENABLING OF TCLKQ 31 16 18 2 14 JUMPER SETTINGS FOR DATA LOOPBACK ON LINKS 2 ouest ta 20 2 15 JUMPER SETTINGS FOR DATA LOOPBACK CROSS CONNECT ON LINKS 0 AND 1 nitet onceberi 21 2 16 JUMPER SETTINGS FOR BERT EMULATION 22 2 47 PLACEMENT OF OSCILLATORS IN THE SOCKETS 23 PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE i PVC RELEASED k PMC Sierra Inc 2352 FREEDM 32P672 DEVELOPMENT KIT BOARD USER ya ts aioe qut MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL 3 CONFIGURATIONS FOR THE TEST CASES 25 3 1 CONFIGURATION FOR PCI INTERFACE TEST 25 3 2 CONFIGURATION FOR UNCHANNELIZED T1 LOOPBACK MODE u aaa dx Rd es 26 3 3 CONFIGURATION FOR UNCHANNELIZED E1 LOOPBACK MODE aet aene 28 34 CONFIGURATION FOR 16 1 16 E1 UNCHANNELIZED LOOPBACK MODE a E AER 31 35 CONFIGURATION FOR UNCHANNELIZED 52 MBIT S 33 3 6 CONFIGURATION FOR UNCHANNELIZED MIXED DS3 T1 E1 DATATOGOPBAUN ddp teer ode 35 3 7 CONFIGURATION FOR UNCHANNELIZ2. PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 29 RELEASED PM2352 FREEDM 32P672 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 DEVELOPMENT KIT BOARD USER MANUAL B15 respectivel es ere P11 RCLK 31 16 Pins A16 through A31 shorted to pins B16 through B31 respectivel P13 TCLK 15 0 Pins AO through A15 shorted to pins BO through B15 respectivel P14 TCLK 31 16 Pins A16 through A31 shorted to pins B16 through B31 respectivel 2 048 MHz provision to RCLK 31 16 inputs of FREEDM 32P672 2 048 MHz provision to TCLK 15 0 inputs of FREEDM 32P672 2 048 MHz provision to TCLK 31 16 inputs of FREEDM 32P672 2 048 MHz selection for RCLK 2 0 7 RCL52 2 0 Pins B RO 1 and B R2 shorted to pins C RO C R1 and C R2 respectively Columns 0 1 and 2 048 MHz selection for TCLK 2 0 P7 TCL52 2 0 Pins B TO B T1 and B T2 shorted to pins C TO C T1 and C T2 respectively Columns 0 1 and P15 TD RD 15 2 Pins A2 through A15 shorted to pins B2 through B15 respectively P10 TD Pins A16 through Loopback on links 16 through RD 31 16 A31 shorted to 31 pins B16 through B31 respectivel Loopback on links 2 through 15 P2 TD RD 1 0 TDO shorted to Loopback on links 0 and 1 RDO TD1 shorted to RD1 Note 2 048 MHz oscillators should be placed in sockets OSC 1 and OSC 4 If loopback is not to be performed on each of the 32 links jumper setting
3. Pins AO A1 A2 and TFPB 3 0 grounded A3 shorted to pins BO B1 B2 and B3 respectivel Pins in column A shorted to pins in column B respectivel Pins Ay shorted to pins By respectively where y link to be operated at DS3 T1 or E1 The pins Bz shorted to pins Cz where z link to be disabled Pins Ay shorted to pins By respectively where y link to be operated at T1 or E1 The pins Bz shorted to pins Cz where z link to be disabled Pins Ay shorted to pins By respectively where y link to be operated at DS3 T1 or E1 The pins Bz shorted to pins Cz where z link to be disabled Pins Ay shorted to pins By respectively where y link to be operated at T1 or E1 The pins Bz RFP8B and TFP8B grounded DS3 provision to RCLK 2 0 inputs of FREEDM 32P672 T1 E1 clocks connected to selective links for Mixed DS3 T1 E1 operation Selected Links enabled for T1 E1 operation Mixed mode DS3 provision to TCLK 2 0 inputs of FREEDM 32P672 T1 E1 clocks connected to selective links for Mixed DS3 T1 E1 operation Selected Links enabled for T1 E1 operation Mixed mode PROPRIETARY AND CONFIDENTIAL PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 36 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 pp aayqa DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL mes to pins Cz z link to be disabled 0 Pins
4. other where 2 x n lt 15 where 2 lt n lt 15 Note Loopback can be performed on any link independent of the other links Pins on headers P10 and P15 corresponding to link n where 2 lt n lt 31 need not be shorted if loopback is not to be performed on link n PROPRIETARY AND CONFIDENTIAL PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 20 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 y nu lt smTqc sn DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL P10 P15 s _ i Loopback on links 16 to 31 Loopback on links 2 to 15 Figure 16 Jumper settings for data loopback on links 2 to 31 2 15 Jumper settings for Data loopback cross connect on links 0 and 1 Placement of shorting jumpers over header P2 result in configuration of either loopback or cross connect of data on links 0 and 1 This is shown in Figure 17 The jumper settings are also listed in Table 14 PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 21 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 k a ssOrrr r DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL RD1 TDO RD1 one Simultaneous Cross Connect Simultaneous Loopback Figure 17 Jumper settings for loopback cross connect on links 0 and 1 P2 Table
5. settings for enabling of RCLK 31 16 JUMPER SETTING CONFIGURATION HEADER A n shorted to pin B n RCLK n connected to FREEDM 16 lt n lt 31 32P672 16 lt n lt 31 Pin C n shorted to pin B n RCLK n grounded 16 lt n lt 31 16 lt lt 31 For channelized non H MVIP mode externally gapped RCLK 31 16 should be provided by means of a wire to board connector plugged into pins of rows B and C on header P11 The ground plugs on the wire to board connector should mate with the ground pins row C on header P11 PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 15 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 y SMW mc _ 5 DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL A B A B RCLK 31 16 lt T1 E1 RCLK 31 16 grounded Non H MVIP Mode H MVIP Mode Note Each of the RCLK inputs to FREEDM 32P672 chip can be independently enabled Figure 13 Jumper settings for enabling of RCLK 31 16 P11 PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 16 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 y s f lt DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL 2 12 Jumper settings for enabling of TCLK 15 0 TCLK 15 0 should
6. 1 PMC Sierra Inc PM2352 FREEDM 32P672 pu apup aaa qq H __ DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL respectivel P msi eee P7 RCL52 2 0 Pins B RO B R1 1 544 MHz selection for and B R2 shorted RCLK 2 0 to pins C RO C R1 and C R2 respectively Columns 0 1 and P7 TCL52 2 0 Pins B TO B T1 1 544 MHz selection for and B T2 shorted TCLK 2 0 to pins C TO C T1 and C T2 respectively Columns 0 1 and P15 TD RD 15 2 Pins A2 through Loopback on links 2 through A15 shorted to pins 15 B2 through B15 respectivel P10 TD Pins A16 through Loopback on links 16 through RD 31 16 A31 shorted to pins 31 B16 through B31 respectivel P2 TD RD 1 0 TDO shorted to Loopback on links 0 and 1 to RD1 Note 1 544 MHz oscillators should be placed in sockets OSC 1 and OSC 4 If loopback is not to be performed on each of the 32 links jumper settings will be similar to those shown in Table 18 except for the unused RCLK TCLK RD and TD Unused RCLK and TCLK should be grounded by placing jumpers over pins of columns B and C of the unused links Unused RD and TD need not be shorted 3 Configuration for unchannelized E1 loopback mode Each of the 32 transmit receive links can be configured independently to transmit receive unchannelized E1 data This is done by the software Loopback can be performed on any of these 32
7. 3 7 Configuration for unchannelized 2 048 Mbit s H MVIP data loopback One or more link groups can be configured to receive transmit unchannelized 2 048 Mbit s H MVIP data The jumper settings for performing loopback of 2 048 Mbit s H MVIP data on all the 32 links is shown in Table 22 Table 22 Configuration for unchannelized 2 048 Mbit s H MVIP data loopback LENE Dm SETTINGS WE ual Jumper over pins B SYSCLK 1 to liit 0 Pins BO B1 B2 4 096 MHz provision to and B3 shorted to RMVCK pins AO A1 A2 and inputs of FREEDM 32P672 A3 respectively TMVCK 3 0 Pins BO B1 B2 4 096 MHz provision to and shorted to TMVCK inputs of FREEDM pins AO A1 A2 and 32P672 A3 respectively P4 RMV8DC amp Pins in row C RMV8DC amp TMV8DC TMV8DC shorted to pins in grounded row D respectively P4 RMV8FPC amp Pins in row A RMV8FPC amp TMV8FPC TMV8FPC shorted to pins in grounded row B respectively RFPB 3 0 Pins CO C1 C2 RFPB 3 0 pulled high and C3 shorted to pins BO B1 B2 and B3 respectively P1 3 0 Pins CO C1 C2 3 0 pulled high and C3 shorted to pins BO B1 B2 and B3 respectively RFP8B amp Pins in column RFP8B and TFP8B grounded TFP8B shorted to pins in column B respectively RCLK 15 0 Pins CO through RCLK 15 0 grounded PROPRIETARY AND CONFIDENTIAL PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 38 RELEASED 2 1 PMC Sierra Inc PM2352
8. e 16 T1 links and 16 links e 3 DS 3 unchannelized 52 Mbit s links e Mixed mode 1 DS 3 link and T1 E1 links With external gapped clock frame pulse signals channelized non H MVIP as well as H MVIP mode can be supported This includes channelized 8 Mbit s H MVIP mode for which an external frame pulse as well as frame pulse clocks are required Note that the supplied software does not include support for includes channelized 8 Mbit s H MVIP mode This section gives a detailed description of the jumper settings on the various headers Figure 1 represents the block diagram for the FREEDM 32P672 development kit board PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 2 RELEASED 2 k PMC Sierra Inc PM2352 FREEDM 32P672 a n RU sur DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL Figure 1 FREEDM 32P672 Development Kit Board Diagram PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 3 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 k m O S mVVr r _ 5 DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL 2 1 Voltage Selection The FREEDM 32P672 requires 3 3 V source The user has the option of using either the 3 3 V provided by the PCI connector or a board regulated 3 3 V source The jumper setting
9. Shorting jumper over pins A and SYSCLK from oscillator Shorting jumper over pins B and SYSCLK from PCICLKO Note Pins B and C should only be shorted when the card is installed in a system with a 33 MHz PCI bus 2 3 Jumper setting for RMVCK 3 0 provision Each of the four RMVCK inputs to the FREEDM 32P672 chip can be configured independently Each RMVCK input to the FREEDM 32P672 chip can either be grounded or provided with a 4 096 MHz clock from an oscillator The jumper settings on header P5 to achieve these configurations are as shown in Figure 5 The jumper settings are also listed in Table 2 In non H MVIP or 8 192 Mbit s H MVIP mode RMVCK 3 0 should be grounded To ground RMVCK n 0 lt n lt 3 pin B n should be shorted to pin C n on header P5 4 096 MHz clock from an oscillator can be provided to RMVCK n by shorting pins B n and A n The jumper settings in Figure 5 a correspond to 4 096 MHz on RMVCK 3 0 whereas the jumper settings in Figure 5 b correspond to grounded RMVCK 3 0 PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 5 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 k SM R nm 6 DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL 3 2 1 0 3 2 1 0 A OPO OA B B RMVCK 3 0 4 096 MHz RMVCK 3 0
10. are shown in Figure 6 The jumper settings are also listed in Table 3 In non H MVIP or 8 192 Mbit s H MVIP mode TMVCK 3 0 should be grounded To ground TMVCK n 0 x n lt 3 pin B n should be shorted to pin C n on header P6 The 4 096 MHz clock from an oscillator can be provided to TMVCK n by shorting pins B n and A n The jumper settings in Figure 6 a correspond to 4 096 MHz TMVCK 3 0 whereas the jumper settings in Figure 6 b correspond to grounded TMVCK 3 0 1 2 0 1 2 3 A UC B O 0 5 Oils TMVCK 3 0 4 096 MHz TMVCK 3 0 lt GND Note Numbers written above the header represent the link groups Figure 6 Jumper setting for TMVCK 3 0 P6 Table 3 Jumper setting for TMVCK 3 0 JUMPER SETTINGS CONFIGURATION Shorting jumper over pins A n 4 096 MHz input TMVCK n B n 0 lt n lt 3 0 lt lt 3 Unchannelized 2 048 Mbit s MVIP mode Shorting jumper over pins TMVCK n grounded and B n 0 lt lt 3 0 lt lt 3 Non 2 048 Mbit s H MVIP mode PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 7 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 y sn 5 DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL Note Each of the TMVCK inputs can be configured independent of the other TMVCK inputs For channelized 2 048 Mbit s H MVIP mode external TMVC
11. 14 Jumper settings for loopback cross connect on links 0 and 1 HEADER JUMPER SETTING CONFIGURATION P2 TDO shorted to RD1 Cross connect on links 0 and 1 TD1 shorted to RDO P2 TDO shorted to RDO Loopback on links 0 and 1 TD1 shorted to RD1 2 16 Jumper settings for BERT Emulation Link 2 is used to emulate the BERT interface To emulate BERT interface link 2 should act as the source of TBD data and at the same time receive data on RBD output of FREEDM 32P672 chip RBCLK and TBCLK are respectively shorted to RCLK 2 and TCLK 2 The jumper settings on headers P15 and P7 for BERT Emulation are listed in Table 15 and are also shown in Figure 18 and Figure 19 GND D GND TBD RBD TD2 RD2 D O iat O O oai Figure 18 Jumper settings for BERT data emulation P15 PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 22 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 k wr tts r DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL RCL52 0 2 TCL52 0 2 eu er Ox Ka X OEC Oc CF Oe OS RBCLK TBCLK Figure 19 Jumper settings for BERT Clock Emulation P7 Table 15 Jumper settings for BERT Clock Emulation E c RD2 und to D 2 to shorted to 2 17 Placement of oscillators in the sockets Table 16 lists the oscillators to be placed in the sockets prior t
12. A Ry shorted 053 selection for RCLK 2 0 to pins B Ry One of the links 0 1 or 2 is respectively where operated at DS3 rate y 0 1 or 2 is the link to be operated at DS3 Pins B Rz shorted to C Rz where z links not used for DS3 TCL52 2 0 Pins A Ty shorted DS3 selection for TCLK 2 0 to pins B Ty One of the links 0 1 or 2 is respectively where operated at DS3 rate y 0 1 or 2 is the link to be operated at DS3 Pins B Tz shorted to C Tz where z links not used for DS3 TD RD 15 2 Pins Ay shorted to Loopback on selected links pins By respectively where y link to be operated at DSS T1 E1 Pins Ay shorted to Loopback on selected links on 16 pins By respectively where y link to be operated at T1 E1 TD RD 1 0 TDy shorted to RDy Loopback on selected links respectively where y link to be operated at DS3 T1 E1 Note 1 All unused RCLK and TCLK should be grounded by placing shorting jumpers over pins of columns B and C of the unused links Shorting jumpers need not be placed over unused receive transmit links PROPRIETARY AND CONFIDENTIAL PMC SIERRA AND FOR ITS CUSTOMERS INTERNAL USE 37 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 y wn 0 s 5 DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL Note 2 The aggregate instantaneous clock rate over all 32 possible links is limited to 64 MHz
13. BO B1 B2 RMVCK S3 0 grounded and B3 shorted to pins CO C1 C2 and C3 respectively TMVCK 3 0 Pins BO B1 B2 TMVCK 3 0 grounded and B3 shorted to pins CO C1 C2 and C3 respectively P4 RMV8DC amp Pins in row C RMV8DC amp TMV8DC TMV8DC shorted to pins in grounded row D respectively RMV8FPC amp Pins in row A RMV8FPC amp TMV8FPC shorted to pins in grounded row B respectively Ll 0 Pins AO A1 A2 and RFPB 3 0 grounded A3 shorted to pins BO B1 B2 and B3 respectively TFPB 3 0 Pins AO A1 A2 and TFPB 3 0 grounded A3 shorted to pins BO B1 B2 and B3 respectively amp Pins in row RFP8B and TFP8B grounded shorted to pins in LM B respectively 5 0 Pins A0 through 1 544 MHz provision to A15 shorted to pins RCLK 15 0 inputs of BO through B15 FREEDM 32P672 respectively RCLK 31 16 Pins A16 through 1 544 MHz provision to PROPRIETARY AND CONFIDENTIAL PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 25 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 puypi aaa yw y iC DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL A31 shorted to pins RCLK 31 16 inputs of B16 through B31 FREEDM 32P672 respectivel TCLK 15 0 Pins AO through 1 544 MHz provision to A15 shorted to pins TCLK 15 0 inputs of BO through B15 FREEDM 32P672 respectivel TCLK 31 16 Pins A16 through 1 544 MHz provision to A31
14. MHz 32 bit Peripheral Component Interconnect PCI 2 1 compliant bus for configuration monitoring and transfer of packet data e The Development Kit supports both unchannelized H MVIP as well as non H MVIP traffic Channelized T1 E1 traffic on the 32 links is not directly supported since there is no provision for gapping of the link clocks Channelized H MVIP mode is not directly supported since the frame pulses are not generated on the Development Kit card Channelized T1 E1 operation can be supported only with an external gapped clock i e gapped clock from an external source Channelized H MVIP mode can be supported with external frame pulses and frame pulse clocks PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 1 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 pHuE EPI SM n DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL 2 HARDWARE CONFIGURATION Jumper settings are used to configure the Development Kit board for various modes of operation The supported modes include e Unchannelized T1 mode Unchannelized E1 mode e Unchannelized 52 MHz mode e Unchannelized 2 048 Mbit s H MVIP mode e Mixed mode For non H MVIP modes only the following configurations can be achieved using jumper settings e 32 T1 links e 32 E1 links
15. Pins BO B1 B2 TMVCK 3 0 grounded and B3 shorted to pins CO C1 C2 and C3 respectively RMV8DC amp Pins in row C RMV8DC amp TMV8DC pr fepe shorted to pins in grounded row D respectively ub amp Pins in row RMV8FPC amp TMV8FPC shorted to pins in grounded row B respectively 0 Pins AO A1 A2 and RFPB 3 0 grounded A3 shorted to pins BO B1 B2 and B3 respectively TFPB 3 0 Pins AO A1 A2 and TFPB 3 0 grounded A3 shorted to pins BO B1 B2 and B3 respectively RFP8B 8 Pins in column A RFP8B and TFP8B grounded TFP8B shorted to pins in column B respectively RCLK 15 0 Pins Ay shorted to 52 MHz provision to RCLK 2 0 pins By inputs of FREEDM 32P672 PROPRIETARY AND CONFIDENTIAL PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 33 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 apup aasawa sawa DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL RCLK 31 16 Pins C16 through RCLK 31 16 grounded C31 shorted to pins B16 through B31 respectivel P13 TCLK 15 0 Pins Ay shorted to 52 MHz provision to TCLK 2 0 pins By inputs of FREEDM 32P672 respectively where select 2 links to provision and y link to be disable the third operated at 52Mhz The pins Bz shorted to pins Cz where z link to be disabled P14 TCLK 31 16 Pins C16 through TCLK 31 16 grounded C31 shorted to pins B16 through B31 resp
16. T2 shorted TCLK 2 0 to pins C TO C T1 and C T2 respectively Columns 0 1 and P15 TD RD 15 2 Pins A2 through Loopback on links 2 through A15 shorted to pins 15 B2 through B15 respectively P10 TD Pins A16 through Loopback on links 16 through RD 31 16 A31 shorted to pins 31 B16 through B31 respectively P2 TD RD 1 0 TDO shorted to Loopback on links 0 and 1 RDO TD1 shorted to RD1 Note If links O through 15 are to be configured for unchannelized E1 data and links 16 through 31 are to be configured for T1 data 2 048 MHz oscillator should PROPRIETARY AND CONFIDENTIAL PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 32 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 sarqrrssTssqA K7Haau __ DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL be placed in socket OSC 1 whereas 1 544 MHz oscillator should be placed in OSC 4 3 5 Configuration for unchannelized 52 Mbit s Links 0 through 2 can be configured for supporting 52 Mbit s data The jumper settings for simultaneous loopback of 52 Mbit s on links 0 through 2 is shown in Table 20 Table 20 Simultaneous loopback of unchannelized 52 Mbit s data on links 0 through 2 SIGNAL JUMPER CONFIGURATION ACHIEVED SETTINGS EAE LL Jumper over pins B SYSCLK set to 40 MHz 0 Pins BO B1 B2 RMVCK S3 0 grounded and B3 shorted to pins CO C1 C2 and C3 respectively TMVCK 3 0
17. achieve this configuration are shown in Figure 8 They are also listed in Table 5 TFP8B O O RFP8B O O A B C A B C RFP8B lt GND RFP8B 3 3V TFP8B GND TFP8B lt 3 3V Non 8 192 Mbit s H MVIP Mode Unchannelized 8 192 Mbit s H MVIP Mode Figure 8 Jumper settings for RFP8B and TFP8B P9 Table 5 Jumper settings for RFP8B and TFP8B HEADER JUMPER SETTING CONFIGURATION P9 Pinsin column C shorted to TFP8B and RFP8B pulled high PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 9 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 DEEP qa rrsr rFF ara DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL lle corresponding pins column B 3 3 Pins in column A shorted to TFP8B and RFP8B grounded corresponding pins in column B Non 8 192 Mbit s H MVIP mode For 8 192 Mbit s H MVIP mode external TFP8B and RFP8B have to be provided by means of a wire to board connector plugged into pins of columns A and B on header P9 The ground plugs on the wire to board connector should mate with the ground pins column A on header P9 2 7 Jumper settings for RFPB 3 0 RFPB 3 0 should be pulled down to ground when unchannelized 2 048 Mbit s H MVIP mode is not used If the links in one or more link groups are used for unchannelized 2 048 Mbit s H MVIP mode RFPB inputs for these link groups should be pulled high R
18. be grounded when unchannelized H MVIP mode is used on links 0 through 15 If one or more links from 0 through 15 is used for transmitting non H MVIP traffic the corresponding transmit link clocks i e TCLK n where 0 lt n lt 15 should be enabled The jumper settings on header P13 for enabling TCLK 15 0 are listed in Table 11 Figure 14 shows the jumper settings for enabling all 16 transmit link clocks from TCLK 15 through TCLK O O Oloj ol ool o D O O o ojoj o OJO o oo o o sy o o o CEA B oJ A A B C TCLK 2 0 T1 E1 DS 3 52 MHz TCLK 15 0 lt GND TCLK 15 3 lt T1 E1 TCLK 15 0 enabled TCLK 15 0 grounded Non H MVIP Mode H MVIP Mode N N E 0 E 2 E A E 4 E 3 E 5 Note The pins for links O through 15 are not in sequential order Each of the TCLK inputs to FREEDM 32P672 chip can be independently enabled Figure 14 Jumper settings for enabling of TCLK 15 0 P13 PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 17 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 y a _ DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE
19. down to ground when unchannelized 2 048 Mbit s H MVIP mode is not used If the links in one or more link groups are used for unchannelized 2 048 Mbit s H MVIP mode the TFPB inputs for these link groups should be pulled high TFPB for each link group can be configured independently The jumper settings on header P1 to achieve these configurations are listed in Figure 10 They are also listed in Table 7 0 1 2 3 0 1 2 3 A OOOO B B GO 0 Ole TFPB 3 0 lt GND TFPB 3 0 lt 3 3V Note TFPB for each link group can be independently configured with a single shorting jumper Figure 10 Jumper settings for TFPB 3 0 P1 Table 7 Jumper settings for TFPB 3 0 HEADER JUMPER SETTINGS CONFIGURATION P1 Pin A n shorted to pin TFPB n grounded B n 0 lt lt 3 0 lt lt 3 2 048 Mbit s H MVIP mode Pin C n shorted to TFPB n pulled high 3 3 V PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 11 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 pa apu A IO DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL HEADER JUMPER SETTINGS CONFIGURATION pin B n 0 lt n lt 3 0xnx3 2 2 048 Mbit s H MVIP mode on link group n For channelized 2 048 Mbit s H MVIP mode external TFPB 3 0 has to be provided by means of a wire t
20. iwl Jumper over pins EIL Sc to udi 0 Pins BO B1 B2 RMVCK S3 0 grounded and B3 shorted to pins CO C1 C2 and C3 respectively TMVCK 3 0 Pins BO B1 B2 TMVCK 3 0 grounded and B3 shorted to pins CO C1 C2 and C3 respectively P4 RMV8DC amp Pins row C RMV8DC amp TMV8DC TMV8DC shorted to pins in grounded row D respectively P4 RMV8FPC amp Pins in row A RMV8FPC amp TMV8FPC TMV8FPC shorted to pins in grounded row B respectively RFPB 3 0 Pins A2 and RFPB 3 0 grounded A3 shorted to pins BO B1 B2 and B3 respectively TFPB 3 0 Pins AO A1 A2 and TFPB 3 0 grounded A3 shorted to pins BO B1 B2 and B3 respectively RFP8B amp Pins in row A RFP8B and TFP8B grounded shorted to pins in row B respectively 5 0 Pins AO through 1 544 MHz provision to A15 shorted to pins RCLK 15 0 inputs of BO through B15 FREEDM 32P672 respectively P11 RCLK 31 16 Pins A16 through 1 544 MHz provision to A31 shorted to pins RCLK 31 16 inputs of B16 through B31 FREEDM 32P672 respectively P13 TCLK 15 0 Pins AO through 1 544 MHz provision to A15 shorted to pins TCLK 15 0 inputs of BO through B15 FREEDM 32P672 respectively P14 TCLK 31 16 Pins A16 through 1 544 MHz provision to A31 shorted to pins TCLK 31 16 inputs of B16 through B31 FREEDM 32P672 PROPRIETARY AND CONFIDENTIAL PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 27 RELEASED 2
21. 1 DEVELOPMENT KIT BOARD USER MANUAL Table 11 Jumper settings for TCLK 15 0 HEADER JUMPER SETTING CONFIGURATION P13 Pin A n shorted to pin TCLK n connected to FREEDM 0 x n lt 15 32P672 0 lt lt 15 P13 Pin C n shorted to pin B n TCLK n grounded 0 lt lt 15 0 lt lt 15 For channelized non H MVIP mode externally gapped TCLK 15 0 should be provided by means of a wire to board connector plugged into pins of rows B and C on header P13 The ground plugs on the wire to board connector should mate with the ground pins row C on header P13 2 13 Jumper settings for enabling of TCLK 31 16 TCLK 31 16 should be grounded when unchannelized H MVIP mode is used on links 16 through 31 If one or more links from 16 through 31 are used for transmitting non H MVIP traffic the corresponding transmit link clocks i e TCLK n where 16 lt n lt 31 should be enabled The jumper settings on header P14 for enabling TCLK 31 16 are listed in Table 12 Figure 15 shows the jumper settings for enabling all 16 transmit link clocks from TCLK 31 through TCLK 16 For channelized non H MVIP mode externally gapped TCLK 31 16 should be provided by means of a wire to board connector plugged into pins of rows B and C on header P14 The ground plugs on the wire to board connector should mate with the ground pins row C on header P14 Table 12 SEIS at settings for enabling TCLK 31 16 JUMPER SETTING CONFIGURATION HEA
22. 3 respectively TMVCK 3 0 Pins BO B1 B2 TMVCK 3 0 grounded and B3 shorted to pins CO C1 C2 and C3 respectively RMV8DC amp Pins in row C RMV8DC amp TMV8DC pr we shorted to pins in grounded row D respectively a amp Pins in rowA RMV8FPC amp TMV8FPC shorted to pins in grounded sm B respectively 0 Pins AO A1 A2 and RFPB 3 0 grounded A3 shorted to pins BO B1 B2 and B3 respectively 3 0 Pins AO A1 A2 TFPB 3 0 grounded A3 shorted to pins BO B1 B2 and B3 respectively HFP8B amp Pins in column A RFP8B and TFP8B grounded TFP8B shorted to pins in column B respectively P12 RCLK 15 0 Pins AO and 2 1 544 MHz provision to shorted to pins RCLK 0 and RCLK 2 inputs and B2 of FREEDM 32P672 PROPRIETARY AND CONFIDENTIAL PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 42 RELEASED PM2352 FREEDM 32P672 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 DEVELOPMENT KIT BOARD USER MANUAL respectively Bx shorted to Cx where x 1 3 to 15 RCLK 31 16 Pins C16 through C31 shorted to pins B16 through B31 RCLK 31 16 grounded respectivel 1 544 MHz provision to TCLK 0 and TCLK 2 inputs of FREEDM 32P672 TCLK 15 0 Pins AO and A2 shorted to pins BO and B2 respectively Bx shorted to Cx where x 1 3 to 15 TCLK 31 16 Pins C16 through C31 shorted to pins B16 through B31 respectivel Pin B R2 shorte
23. 4m 0 lt lt 7 not used the unused TD and RD pins should not be shorted For example if only link O is used for 8 192 Mbit s H MVIP mode then only RDO and TDO should be shorted by a jumper The remaining RD and TD header pins should not be shorted 3 9 _ BERT Signal Verification Configure links O and 2 for unchannelized 52 MHz or 1 544 MHz or 2 048 MHz mode Hardware provision for 52 MHz or 1 544 MHz or 2 048 MHz clock at RCLK 0 and TCLK 0 of the FREEDM 32P672 chip is made for BERT signal PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 41 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 k Aaa 5 DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL verification test Also RBCLK and TBCLK are shorted respectively to RCLK 2 and TCLK 2 Loopback of data on link 0 is enabled in hardware Hardware configuration is done by shorting header pins corresponding to TBD and RBD with header pins corresponding to TD 2 and RD 2 respectively The idea is to make link 2 to emulate the BERT data which may then be looped back externally by link 0 The jumper settings for BERT signal verification test are shown in Table 24 Table 24 Configuration for BERT signal verification test odd ames sr SETTINGS Jumper over pins B SYSCLK veru to diu 0 Pins BO B1 B2 RMVCK S3 0 grounded and B3 shorted to pins CO C1 C2 and C
24. DER A n shorted to pin B n TCLK n connected to 16 lt n lt 31 FREEDM 32P672 16 lt lt 31 Pin C n shorted to pin TCLK n grounded 16 lt n lt 31 16 lt lt 31 PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 18 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 k T rc nnr ss DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL A B C TCLK 31 16 lt T1 E1 TCLK 15 0 grounded H MVIP Mod TCLK 15 0 enabled Non Mode Figure 15 Jumper settings for TCLK 31 16 P14 PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 19 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 y sn 5 DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL 2 14 Jumper settings for Data loopback on links 2 through 31 Data loopback can be performed on a per link basis on links 2 through 31 The jumper settings for loopback on these links are listed in Table 13 Figure 16 shows the jumper settings for loopback on all the links from 2 to 31 Table 13 Jumper settings for data loopback on links 2 through 31 HEADER JUMPER SETTING CONFIGURATION Pins in row n shorted with each Loopback on link n other where 16 lt n lt 31 where 16 lt n x 31 Pins in row n shorted with each Loopback on link n
25. E 1 DEVELOPMENT KIT BOARD USER MANUAL TABLE 20 SIMULTANEOUS LOOPBACK OF UNCHANNELIZED 52 MBIT S DATA ON LINKS 0 THROUGH 2 erste uter a xar meet aee Bus 33 TABLE 21 SIMULTANEOUS LOOPBACK OF UNCHANNELIZED MIXED DATA 35 TABLE 22 CONFIGURATION FOR UNCHANNELIZED 2 048 MBIT S H MVIP DATA EOOPBAGHK tti haves c aeree oie ation ur nia a 38 TABLE 23 CONFIGURATION FOR UNCHANNELIZED 8 192 MBIT S H MVIP DATA LOOPBACK i ea eret ae ure tag id ecu SUR 40 TABLE 24 CONFIGURATION FOR BERT SIGNAL VERIFICATION TEST 42 PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNALUSE v RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 pHuE EPI SM n DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL 1 OVERVIEW The FREEDM 32P672 Development Kit consists of an add on PCI card that can be used to test the functionality of the FREEDM 32P672 chip The PCI card consists of all the necessary components used for testing the various functions of the FREEDM 32P672 device This document provides the necessary information for configuring the FREEDM 32P672 Development Kit Board Rev 2 0 jumper settings 1 1 Features e The Development Kit supports a 33 66
26. ED 2 048 MBIT S H MVIP DATA LOOPBAGCGK walikusqa kai 38 3 8 CONFIGURATION FOR UNCHANNELIZED 8 192 MBIT S H MVIP DATA LOOPBACK eroe 40 3 9 BERT SIGNAL VERIFICATION 41 4 HOW TO PROCEED WITH THE TEST 44 PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE ii RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 pHuE EPI SM n DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL LIST OF FIGURES FIGURE 1 FREEDM 32P672 DEVELOPMENT KIT BOARD DIAGRAM 3 FIGURE 2 3 3V SELECTION HEADER P16 s 4 FIGURE 3 LEDS ON THE FREEDM 32P672 DEVELOPMENT KIT 4 FIGURE 4 JUMPER SETTING FOR SYSCLK 3 5 FIGURE 5 JUMPER SETTINGS FOR RMVCK 3 0 5 6 FIGURE 6 JUMPER SETTING FOR TMVCK 3 0 6 7 FIGURE 7 JUMPER SETTINGS FOR ENABLING OF RMV8FPC TMV8FPC TMV8DG AND RINV GDC edt vts Qo as qe qe 9 FIGURE 8 JUMPER SETTINGS FOR RFP8B AND TFP8B 9 9 FIGURE 9 JUMPER SETTINGS FOR RFPB 3 0 P8 10 FIGURE 10JUMPER SETTINGS FOR TFPB 3 0 1 11 FIGURE 11 JUM
27. FPB for each link group can be configured independently The jumper settings on header P8 to achieve these configurations are listed in Figure 9 They are also listed in Table 6 OJO CJ OJO 10 C B A RFPB lt 3 3V RFPB 3 0 lt GND Note RFPB for each link group can be independently configured with a single shorting jumper Figure 9 Jumper settings for RFPB 3 0 P8 For channelized 2 048 Mbit s H MVIP mode external RFPB 3 0 has to be provided by means of a wire to board connector plugged into pins of columns A and B on header P8 The ground plugs on the wire to board connector should mate with the ground pins column A on header P8 PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 10 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 y SMW DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL Table 6 Jumper settings for RFPB 3 0 HEADER JUMPER SETTINGS CONFIGURATION Pin A n shorted to pin RFPB n grounded 0 lt lt 3 0xnx3 ens 2 o Mbit s H MVIP mode Pin C n shorted to pin B n RFPB n pulled high 3 3 V 0 lt n lt 3 0 lt lt 3 Unchannelized 2 048 Mbit s mode on link 2 8 Jumper settings for TFPB 3 0 TFPB 3 0 should be pulled
28. FREEDM 32P672 pP pg DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL C15 shorted to pins BO through B15 respectivel P11 RCLK 31 16 Pins C16 through RCLK 31 16 grounded C31 shorted to pins B16 through B31 respectivel P13 TCLK 15 0 Pins CO through TCLK 15 0 grounded C15 shorted to pins BO through B15 respectivel P14 TCLK 31 16 Pins C16 through TCLK 31 16 grounded C31 shorted to pins B16 through B31 respectivel P7 RCL52 2 0 No shorting jumper placed on this header E ii 0 No shorting jumper placed on this header umi RD 15 2 Pins A2 through Loopback on links 2 through A15 shorted to pins 15 B2 through B15 respectivel TD Pins A16 through Loopback on links 16 through RD 31 16 A31 shorted to pins 31 B16 through B31 respectivel P2 TD RD 1 0 TDO shorted to Loopback on links 0 and 1 RDO TD1 shorted to RD1 Note 1 4 096 MHz oscillator should be placed in socket OSC 2 Note 2 If all the link groups are not configured for unchannelized 2 048 Mbit s H MVIP mode unused RMVCK and TMVCK should be grounded No shorting jumpers should be used over unused RD and TD For example if link group 0 alone is configured for unchannelized 2 048 Mbit s H MVIP mode 4 096 MHz clock should be provided to RMVCK 0 only Hence on header P5 pin BO should be shorted to AO whereas pins B1 B2 and B3 sho
29. K is provided by means of a wire to board connector plugged into pins of rows B and C on header P6 The ground plugs on the wire to board connector should mate with the ground pins row C on header P6 2 5 Jumper settings for TMV8DC RMV8DC TMV8FPC and RMV8FPC provision The RMV8DC input to the FREEDM 32P672 chip can either be grounded or provided with a 16 384 MHz clock from an external source by means of a wire to board connector Similarly the TMV8DC input to the FREEDM 32P672 chip can either be grounded or provided with a 16 384 MHz clock from an external source The RMV8FPC and TMV8FPC pins of the chip can either be grounded or provided with frame pulse clock signals from an external source The jumper settings on header P4 to achieve these configurations are shown in Figure 7 They are also listed in Table 4 In non H MVIP or 2 048 Mbit s H MVIP mode TMV8DC and RMV8DC should be grounded To ground these inputs pins in row D should be shorted to corresponding pins in row C on header P4 Also RMV8FPC and TMV8FPC should be grounded by shorting pins in row B to the corresponding pins in row A For 8 192 Mbit s H MVIP mode external TMV8DC RMV8DC TMV8FPC and RMV8FPC should be provided by means of a wire to board connector plugged into pins on header P4 The ground plugs on the wire to board connector should mate with the ground pins rows A and C on header P4 Note that this mode is not presently supported in software GND A G
30. M 32P672 chip can be independently enabled Figure 12 Table 9 Jumper settings for enabling of RCLK 15 0 P12 HEADER settings for enabling of RCLK 15 0 JUMPER SETTING CONFIGURATION HEADER LIA n shorted to pin B n 0 lt lt 15 RCLK n connected to FREEDM 32P672 0 lt lt 15 Pin C n shorted to RCLK n grounded 0 lt n lt 15 0 lt n lt 15 PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 14 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 y sn 5 DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL For channelized non H MVIP mode externally gapped RCLK 15 0 should be provided by means of a wire to board connector plugged into pins of rows B and C on header P12 The ground plugs on the wire to board connector should mate with the ground pins row C on header P12 2 11 Jumper settings for enabling of RCLK 31 16 RCLK 31 16 should be grounded when unchannelized H MVIP mode is used on links 16 through 31 If one or more links from 16 through 31 are used for receiving non H MVIP traffic the corresponding receive link clocks i e RCLK n where 16 lt n 31 should be enabled The jumper settings on header P11 for enabling RCLK 31 16 are listed in Table 10 Figure 13 shows the jumper settings for enabling all 16 receive link clocks from RCLK 31 through RCLK 16 Table 10 HEADER
31. ND A O RMV8FPC B TMV8FPC 2 cC GND C GND cO O RMV8DC D TMV8DC p O RMV8DC GND RMV8DC EXTERNAL TMV8DC GND TMV8DC EXTERNAL RMV8FPC GND RMV8FPC EXTERNAL TMV8FPC GND TMV8FPC EXTERNAL PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 8 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 y sn 5 DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL 2 6 Figure 7 Jumper settings for enabling of RMV8FPC TMV8FPC TMV8DC and RMV8DC P4 Table 4 Jumper settings for enabling of TMV8FPC TMV8DC and RMV8DC HEADER JUMPER SETTING CONFIGURATION Pins in row A shorted to TMV8DC and RMV8DC grounded corresponding pins in row TMV8FPC and RMV8FPC grounded Pins in row C shorted to Non 8 192 Mbit s H MVIP mode corresponding pins in row D 16 384 MHz clock provided to Wire to board connector RMV8DC and TMV8DC 4 096 MHz plugged into pins on header clock provided to RMV8FPC and P4 TMV8FPC Note The falling edges of RMV8FPC and TMV8FPC should be aligned respectively with the falling edges of RMV8DC and TMV8DC with no more than 10 ns skew Jumper settings for TFP8B and RFP8B TFP8B and RFP8B should be pulled down to ground when unchannelized 8 192 Mbit s H MVIP mode is not used Both TFP8B and RFP8B should be pulled high for unchannelized 8 192 Mbit s H MVIP mode The jumper settings on header P9 to
32. PER SETTINGS FOR SELECTION OF RCLK 2 0 AND T ties 13 FIGURE 12JUMPER SETTINGS FOR ENABLING OF RCLK 15 0 P12 14 FIGURE 13JUMPER SETTINGS FOR ENABLING OF RCLK 31 16 P11 16 FIGURE 14JUMPER SETTINGS FOR ENABLING OF TCLK 15 0 P13 17 FIGURE 15JUMPER SETTINGS FOR TCLK 31 16 14 19 FIGURE 16JUMPER SETTINGS FOR DATA LOOPBACK ON LINKS 2 TO 3121 FIGURE 17JUMPER SETTINGS FOR LOOPBACK CROSS CONNECT ON LINKS Q AND 1P 2 oM d e nM NIE tn LN 22 FIGURE 18JUMPER SETTINGS FOR BERT DATA EMULATION 15 22 FIGURE 19JUMPER SETTINGS FOR BERT CLOCK EMULATION P7 23 PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 pHuE EPI SM n DEVELOPMENT KIT BOARD USER LIST OF TABLES TABLE 1 JUMPER SETTING FOR SYSCLK sese 5 TABLE 2 JUMPER SETTINGS FOR RMVCK 3 0 6 TABLES JUMPER SETTING FOR 3 0 7 TABLE 4 JUMPER SETTINGS FOR ENABLING OF RMV8FPC TMV8FPC TMV8DG ze neds e temo Aha Ra 9 TABLE 5 JUMPER SETTINGS FOR RFP8B AND 8 9 TABLE 6 J
33. RELEASED 2 PMC Sierra Inc PM2352 FREEDM 32P672 ya s as DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL PM7380 FREEDM 32P672 DEVELOPMENT KIT USER MANUAL RELEASED ISSUE 1 DECEMBER 2000 PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 pHuE EPI SM n DEVELOPMENT KIT BOARD USER 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL CONTENTS 1 e ua M UD IM 1 1 1 1 2 HARDWARE 2 245 VORTAGE SELECTION vs bd u 4 22 SYSCLK JUMPER SETTING oe wees 5 2 3 JUMPER SETTING FOR RMVCK 3 0 PROVISION 5 24 JUMPER SETTING FOR TMVCK 3 0 PROVISION 6 2 5 JUMPER SETTINGS FOR TMV8DC RMV8DC TMV8FPC AND RMV8FPC PROVISION eerte 8 2 6 JUMPER SETTINGS FOR TFP8B AND 9 2 7 JUMPER SETTINGS FOR 0 10 2 8 JUMPER SETTINGS FOR 0 11 2 9 JUMPER SETTINGS FOR SELECTION OF RCLK 2 0 AND Ap SA LA ea des UR 12 2 10 JUMPER SETTINGS FOR ENABLING OF RCLK 15 0
34. UMPER SETTINGS FOR 3 0 11 TABLE7 JUMPER SETTINGS FOR 3 0 11 TABLE 8 JUMPER SETTINGS FOR SELECTION OF RCLK 2 0 AND TOLKE OT NOMEN 13 9 JUMPER SETTINGS FOR ENABLING OF RCLK 15 0 14 TABLE 10 JUMPER SETTINGS FOR ENABLING OF RCLK S1 16 15 TABLE 11 JUMPER SETTINGS FOR 15 0 18 TABLE 12 JUMPER SETTINGS FOR ENABLING 31 16 18 TABLE 13 JUMPER SETTINGS FOR DATA LOOPBACK ON LINKS 2 TAROUGH 3 a oe dod dete ace snot 20 TABLE 14 JUMPER SETTINGS FOR LOOPBACK CROSS CONNECT ON Bier pu M 22 TABLE 15 JUMPER SETTINGS FOR BERT CLOCK EMULATION 23 TABLE 16 OSCILLATOR PLACEMENT IN SOCKETS 23 TABLE 17 CONFIGURATION FOR THE PCI INTERFACE TEST 25 TABLE 18 CONFIGURATION FOR SIMULTANEOUS LOOPBACK OF E1 DATA ON 32 EIR d an aun ana 29 TABLE 19 CONFIGURATION FOR 16 T1 E1 UNCHANNELIZED LOOPBACK 31 PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE iv RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 pu Was s Wwts cmYm DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSU
35. d to RBCLK Pin B RO shorted to CO TCLK 2 grounded RBCLK shorted to RCLK 2 TBCLK shorted to TCLK 2 TCL52 2 0 Pin B T2 shorted to TBCLK Pin B TO shorted to pin CO TD RD 15 2 TBD shorted to TD 2 RBD shorted to D RD 31 16 through 31 RDO Note 1 544 MHz clock is used on links 0 and 2 for this particular test case BERT Emulation by link 2 NM PROPRIETARY AND CONFIDENTIAL PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 43 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 pHuE EPI SM n DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL 4 HOW TO PROCEED WITH THE TEST CASES Prior to plugging the card into the slot the user has to place all the oscillators in the appropriate sockets as mentioned in section 2 17 The user also has to select the voltage source as mentioned in section 2 Tables in section 3 of the manual only mention the jumper settings for each test case The user should go through section 2 to know how the jumpers are placed over the headers The bitmap image of the Development Kit provided in section 2 can be used to locate the positions of the headers Ground marks are provided on the PCB to indicate the position of ground pins on the various headers These ground marks are aligned with the rows or columns carry
36. ectivel respectively where select 2 links to provision y link to be disable the third operated at 52 MHz The pins Bz shorted to pins Cz where z link to be disabled RCL52 2 0 Pins A RO A R1 52 MHz selection for and A R2 shorted RCLK 2 0 to pins B RO B R1 and B R2 respectively Columns 0 1 and TCL52 2 0 Pins B TO B T1 52 MHz selection for and B T2 shorted TCLK 2 0 to pins A TO A T1 and A T2 respectively Columns 0 1 and 2 bin B2 respectivel RD 31 16 through 31 RDO TD1 shorted PROPRIETARY AND CONFIDENTIAL PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 34 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 HA es DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL 1 Note 1 All unused and TCLK should be grounded by placing shorting jumpers over pins of columns B and C of the unused links Shorting jumpers need not be placed over receive transmit links 3 through 31 RD 31 3 and TD 31 3 If not all three RCLK and TCLK are used unused RCLK and TCLK should be grounded Note 2 If simultaneous cross connect of data on links O and 1 is to be performed TDO should be shorted to RD1 whereas TD1 should be shorted to RDO on header P2 Note 3 Software support is provided for 52Mbit s data loopback on only 2 of the 3 possible l
37. ing only ground pins PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 44 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 k m O S mVVr r _ 5 DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL NOTES PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 45 RELEASED 2 w PMC Sierra Inc PM2352 FREEDM 32P672 a 4 DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL CONTACTING PMC SIERRA INC PMC Sierra Inc 8555 Baxter Place Burnaby BC Canada V5A 4V7 Tel 604 415 6000 604 415 6200 Document Information document 2pmc sierra com Corporate Information info pmc sierra com Application Information apps 2pmc sierra com 604 415 4533 Web Site http www pmc sierra com None of the information contained in this document constitutes an express or implied warranty by PMC Sierra Inc as to the sufficiency fitness or suitability for a particular purpose of any such information or the fitness or suitability for a particular purpose merchantability performance compatibility with other parts or systems of any of the products of PMC Sierra Inc or any portion thereof referred to in this document PMC Sierra Inc expressly disclaims all representations and warranties of any kind regarding the contents or use of the informa
38. inks RCLK and TCLK inputs for the third link should be disabled Also SYSCLK can be connected to PCICLKO output of the FREEDM 32P672 chip provided that PCI frequency is 33 MHz 3 6 X Configuration for unchannelized Mixed DS3 T1 E1 data loopback Links 0 through 2 can be configured for supporting DS 3 data The jumper settings for simultaneous loopback of Mixed DS3 T1 E1 is shown in Table 21 Table 21 Simultaneous loopback of unchannelized Mixed DS3 T1 E1 data SIGNAL JUMPER CONFIGURATION ACHIEVED SETTINGS m Jumper over pins B SYSCLK set to 40 MHz passes A 0 Pins B1 B2 RMVCK 3 0 grounded and B3 shorted to pins CO C1 C2 and C3 respectively TMVCK 3 0 Pins BO B1 B2 TMVCK 3 0 grounded and B3 shorted to pins CO C1 C2 and C3 respectively RMV8DC amp Pins in row C RMV8DC amp TMV8DC pr faoc shorted to pins in grounded row D respectively amp Pins rowA RMV8FPC amp TMV8FPC TMV8FPC shorted to pins in grounded row B respectively PB 3 0 Pins 0 2 and RFPB 3 0 grounded PROPRIETARY AND CONFIDENTIAL PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 35 RELEASED DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 PM2352 FREEDM 32P672 DEVELOPMENT KIT BOARD USER MANUAL TFPB 3 0 RFP8B amp TFP8B RCLK 15 0 TCLK 15 0 TCLK 31 16 E ui A3 shorted to pins BO B1 B2 and B3 respectivel
39. links by using shorting jumpers PROPRIETARY AND CONFIDENTIAL PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 28 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 sarqrrssTssqA K7Haau __ DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL appropriately over headers provided on the PCI card Table 18 shows the jumper settings for performing loopback on all the 32 links Table 18 Configuration for simultaneous loopback of E1 data on 32 links CLER 7 SETTINGS i wl Jumper over pins SYSCLK connected to only for 33 MHz operation eli 0 Pins BO B1 B2 RMVCKT 3 0 grounded and B3 shorted to pins CO C1 C2 and C3 respectivel TMVCK S3 0 Pins BO B1 B2 TMVCK 3 0 grounded and B3 shorted to pins CO C1 C2 and C3 respectivel P4 RMV8DC amp Pins row C RMV8DC amp TMV8DC grounded TMV8DC shorted to pins in row D respectivel shorted to pinsin grounded row B respectivel 0 Pins AO A1 A2 RFPB 3 0 grounded and A3 shorted to pins BO B1 B2 and B3 respectivel TFPB 3 0 Pins AO A1 A2 TFPB 3 0 grounded and A3 shorted to pins BO B1 B2 and B3 respectivel RFP8B amp Pins in column A RFP8B and TFP8B grounded TFP8B shorted to pins in column B respectivel 12 RCLK 15 0 Pins AO through 2 048 MHz provision to A15 shorted to RCLK 15 0 inputs of pins BO through FREEDM 32P672 PROPRIETARY AND CONFIDENTIAL
40. lt GND Note Numbers written above the header represent the link groups Figure 5 Jumper settings for RMVCK 3 0 P5 Table 2 Jumper settings for RMVCK 3 0 JUMPER SETTINGS CONFIGURATION Shorting jumper over pins A n 4 096 MHz input to RMVCK n B n 0 lt n lt 3 0 lt lt 3 Unchannelized 2 048 Mbit s MVIP mode Shorting jumper over pins C n RMVCK n grounded B n 0 lt n lt 3 0 lt lt 3 Non 2 048 Mbit s H MVIP mode Note Each of the RMVCK inputs can be configured independent of the other RMVCK inputs For channelized 2 048 Mbit s H MVIP mode external RMVCK should be provided by means of a wire to board connector plugged into pins of rows B and C on header P5 The ground plugs on the wire to board connector should mate with the ground pins row C on header P5 2 4 Jumper setting for TMVCK 3 0 provision Similar to RMVCK each of the four TMVCK inputs to the FREEDM 32P672 device can be configured independently Each TMVCK input to the FREEDM PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 6 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 y sn 5 DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL 32P672 device can either be grounded or provided with a 4 096 MHz clock from an oscillator The jumper settings on header P6 to achieve these configurations
41. nder RCL52 0 2 label Pis A Tn shorted to pin B Tn 0 lt n lt 2 under TCL52 0 2 label TCLK 2 0 Pin C Tn shorted to pin B Tn 0 n 2 under TCL52 0 2 label Note Each RCLK or TCLK selection can be configured independently 2 10 Jumper settings for enabling of RCLK 15 0 RCLK 15 0 should be grounded when unchannelized H MVIP mode is used on links O through 15 If one or more links from 0 through 15 is used for receiving non H MVIP traffic the corresponding receive link clocks i e RCLK n where 0 lt n 15 should be enabled The jumper settings on header P12 for enabling RCLK 15 0 are listed in Table 9 Figure 12 shows the jumper settings for enabling all 16 receive link clocks from RCLK 15 through RCLK O PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 13 RELEASED DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 PM2352 FREEDM 32P672 DEVELOPMENT KIT BOARD USER MANUAL RCLK 2 0 lt T1 E1 DS 3 52 MHz OJO O OJO OJO C B RCLK 15 3 lt T1 E1 RCLK 15 0 enabled non H MVIP Mode o o o o A A C B RCLK 15 0 lt GND RCLK 15 0 grounded H MVIP Mode Note The pins for links from 0 through 15 are not in sequential order Each of the RCLK inputs to FREED
42. o board connector plugged into pins of rows A and B on header P1 The ground plugs on the wire to board connector should mate with the ground pins row A on header P1 2 9 Jumper settings for selection of RCLK 2 0 and TCLK 2 0 In non H MVIP mode RCLK 2 0 and TCLK 2 0 can be set to either T1 E1 clock frequency or DS 3 52 MHz clock frequency Jumper settings on header P7 to make this selection are listed in Table 8 Figure 11 shows how the jumpers are used on header P7 RCL52 0 2 TCL52 0 2 RBCLK TBCLK A T1 E1 Frequency on RCLK 2 0 and TCLK 2 0 RCL52 0 2 TCL52 0 2 Ci DS RD OD OOo I I OG B O O O O A 2 O O O R2 TO T2 RBCLK TBCLK B DS 3 52 MHz Frequency on RCLK 2 0 and TCLK 2 0 PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 12 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 sarqrrssTssqA K7Haau __ DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL Figure 11 Jumper settings for selection of RCLK 2 0 and TCLK 2 0 P7 Note The numbers TO T1 and T2 corresponding to TCL52 0 2 and RO R1 and R2 corresponding to RCL52 0 2 shown in Figure 11 respectively represent transmit and receive links 0 1 and 2 Table 8 Jumper settings for selection of RCLK 2 0 and TCLK 2 0 HEADER JUMPER SETTINGS CONFIGURATION 0 n 2 under RCL52 0 2 label RCLK 2 0 0 lt n lt 2 u
43. o the card being plugged into the socket Table 16 Oscillator placement in sockets FREQUENCY OSC 1 OSC 3 44 736 MHz Unchannelized 44 736 Mbit s traffic on links 0 through 2 OSC 4 1 544 MHz Unchannelized T1 on links 16 through 31 2 048 MHz Unchannelized E1 on links 16 through 31 OSC 5 40 MHz SYSCLK for FREEDM 32P672 PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 23 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 y a _ DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL Note Clocks are not provisioned to the clock inputs of the FREEDM 32P672 chip simply by placing the oscillators in the appropriate sockets Frequency selection and clock provision has to be done by means of jumpers as mentioned in earlier sections PROPRIETARY AND CONFIDENTIAL PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 24 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 k a a 5 DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL 3 CONFIGURATIONS FOR THE TEST CASES 3 1 Configuration for PCI Interface Test Table 17 lists the required configuration for the PCI Interface Test Table 17 Configuration for the PCI Interface Test LI ee SETTINGS Jumper over pins SYSCLK connected to and C PCICLKO only for 33 MHz operation 0 Pins
44. pectively TFPB 3 0 Pins AO A1 A2 and TFPB 3 0 grounded A3 shorted to pins BO B1 B2 and B3 respectively P3 5 P A v RFP8B amp Pins in column C RFP8B and TFP8B pulled high TFP8B shorted to pins in column B respectively P12 RCLK 15 0 Pins CO through RCLK 15 0 grounded C15 shorted to pins PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 40 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 pupu HA t DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL 250 NN respectivel P11 RCLK 31 16 Pins C16 through RCLK 31 16 grounded C31 shorted to pins B16 through B31 respectivel P13 TCLK 15 0 Pins CO through TCLK 15 0 grounded C15 shorted to pins BO through B15 respectivel P14 TCLK 31 16 Pins C16 through TCLK 31 16 grounded C31 shorted to pins B16 through B31 respectivel P7 RCL52 2 0 No shorting jumper placed on this header P7 TCL52 2 0 No shorting jumper placed on this header P15 TD RD 15 2 Pins A4 A8 and Loopback on links 4 8 and 12 A12 shorted to pins B4 B8 and B12 respectivel P10 TD Pins A16 A20 A24 Loopback on links 16 20 24 RD 31 16 and A28 shorted to and 28 pins B16 B20 B24 and B28 respectivel TD RD 1 0 TDO shorted to Loopback on link 0 RDO Note If all the links in the group
45. s AO A2 RFPB 3 0 grounded A3 shorted to pins BO B1 B2 and B3 respectively RFP8B amp Pins in column A RFP8B and TFP8B grounded TFP8B shorted to pins in column B respectivel RCLK 15 0 Pins 0 through X 1 544 MHz provision to TFPB 3 0 Pins AO A1 A2 and TFPB 3 0 grounded A3 shorted to pins BO B1 B2 and B3 respectivel P12 PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 31 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 apup aaa 4 DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL A15 shorted to pins RCLK 15 0 inputs of BO through B15 FREEDM 32P672 respectivel P11 RCLK 31 16 Pins A16 through 2 048 MHz provision to A31 shorted to pins RCLK 31 16 inputs of B16 through B31 FREEDM 32P672 respectivel P13 TCLK 15 0 Pins AO through 1 544 MHz provision to A15 shorted to pins TCLK 15 0 inputs of BO through B15 FREEDM 32P672 respectivel P14 TCLK 31 16 Pins A16 through 2 048 MHz provision to A31 shorted to pins TCLK 31 16 inputs of B16 through B31 FREEDM 32P672 respectivel P7 RCL52 2 0 Pins B RO B R1 1 544 MHz selection for and B R2 shorted RCLK 2 0 to pins C RO C R1 and C R2 respectively Columns 0 1 and P7 TCL52 2 0 Pins B TO B T1 1 544 MHz selection for and B
46. s for achieving these configurations are shown in Figure 2 REG 3 3 REG 3 3 o PCI 3 3 3 A B Figure 2 3 3V Selection Header P16 There are three LED s near the upper right corner on the topside of the Development Kit board Plugging the Development Kit board into the PCI slot causes the green LED indicating 5 V to light upon power up The two other LED s will light only if the 3 3 V source is selected Figure 3 shows the location of these LED s on the board yellow LED 3 3 V red LED 2 5V green LED 53 FREEDM 32P672 Development Kit top side Figure 3 LED s on the FREEDM 32P672 Development Kit PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 4 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 k a a 5 DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL 2 2 SYSCLK Jumper Setting The SYSCLK input of the FREEDM 32P672 chip can be provided with either a 40 MHz clock from an oscillator or the PCICLKO clock output of the FREEDM 32P672 chip provided that a 33 MHz PCI bus is in use The jumper settings on header P3 to achieve these configurations are shown in Figure 4 The jumper settings are also listed in Table 1 A B C A B C SYSCLK lt 40 MHz SYSCLK lt PCICLKO Figure 4 Jumper setting for SYSCLK P3 Table 1 Jumper setting for SYSCLK HEARERS JUMPER SETTING CONFIGURATION
47. s will be similar to those shown in Table 18 except for the unused RCLK TCLK RD and TD Unused RCLK and TCLK should be grounded by placing shorting jumpers PROPRIETARY AND CONFIDENTIAL PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 30 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 y SMW nB 5 DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL over pins of columns B and C of the unused links Unused RD and TD need not be shorted 3 4 Configuration for 16 T1 16 E1 unchannelized loopback mode With 1 544 MHz oscillator placed in socket OSC 1 and 2 048 MHz oscillator placed in OSC 4 simultaneous loopback of 16 unchannelized T1 links links O 15 and 16 unchannelized E1 links links 16 31 be performed The jumper settings for this loopback are shown in Table 19 Table 19 Configuration for 16 T1 E1 unchannelized loopback m SETTINGS Jumper over pins SYSCLK 2 to illl 0 Pins BO B1 B2 RMVCK S3 0 grounded and B3 shorted to pins CO C1 C2 and C3 respectivel TMVCK S3 0 Pins BO B1 B2 TMVCK 3 0 grounded and B3 shorted to pins CO C1 C2 and C3 respectivel pr we shorted to pins in grounded row D respectivel re amp Pins in RMV8FPC amp TMV8FPC shorted to pins in grounded sm B respectively 0 Pin
48. shorted to pins TCLK 31 16 inputs of B16 through B31 FREEDM 32P672 respectivel RCL52 2 0 Pins B RO 1 1 544 MHz selection for and B R2 shorted RCLK 2 0 to pins C RO C R1 and C R2 respectively Columns 0 1 and TCL52 2 0 Pins B TO B T1 1 544 MHz selection for and B T2 shorted TCLK 2 0 to pins C TO C T1 and C T2 respectively Columns 0 1 and 2 TD RD 15 2 Jumpers not used No loopback on links 2 through 15 P10 TD Jumpers not used No loopback on links 16 RD 31 16 through 31 TD RD 1 0 No loopback on links 0 and 1 3 2 Configuration for unchannelized T1 loopback mode Each of the 32 transmit receive links can be configured independently to transmit receive unchannelized T1 data This is done by the software Loopback can be performed on any of these 32 links by using shorting jumpers appropriately over headers provided on the PCI card Table 18 shows the jumper settings for performing loopback on all the 32 links Table 18 Configuration for simultaneous loopback of T1 data on 32 links HEADER SIGNAL JUMPER CONFIGURATION ACHIEVED PROPRIETARY AND CONFIDENTIAL PMC SIERRA AND FOR ITS CUSTOMERS INTERNAL USE 26 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 apup 991 DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL SETTINGS WE
49. tion including but not limited to express and implied warranties of accuracy completeness merchantability fitness for a particular use or non infringement In no event will PMC Sierra Inc be liable for any direct indirect special incidental or consequential damages including but not limited to lost profits lost business or lost data resulting from any use of or reliance upon the information whether or not PMC Sierra Inc has been advised of the possibility of such damage 2000 PMC Sierra Inc PMC 2001840 Issue date December 2000 PROPRIETARY AND CONFIDENTIAL TO PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE
50. uld be shorted to pins C1 C2 and respectively i e RMVCK 3 1 grounded Also pins corresponding to TD 31 8 and RD 31 8 are not shorted to each other PROPRIETARY AND CONFIDENTIAL PMC SIERRA INC AND FOR ITS CUSTOMERS INTERNAL USE 39 RELEASED 2 1 PMC Sierra Inc PM2352 FREEDM 32P672 y sn 5 DEVELOPMENT KIT BOARD USER MANUAL PMC 2001840 ISSUE 1 DEVELOPMENT KIT BOARD USER MANUAL 3 8 Configuration for unchannelized 8 192 Mbit s H MVIP data loopback Unchannelized H MVIP data at 8 192 Mbit s can be transmitted received by the FREEDM 32P672 chip on links 4m 0 lt lt 7 only The configuration for loopback of 8 192 Mbit s H MVIP data on links 4m is shown in Table 23 Table 23 Configuration for unchannelized 8 192 Mbit s H MVIP data loopback SETTINGS SYSCLK Jumper over pins B SYSCLK connected to pg and C PCICLKO only for 33 MHz operation RMVCKT 3 0 Pins BO B1 B2 RMVCK 3 0 grounded and B3 shorted to pins CO C1 C2 and C3 respectively TMVCK S3 0 Pins BO B1 B2 TMVCK 3 0 grounded and B3 shorted to pins CO C1 C2 and C3 respectively RMV8DC amp Wire to board 16 384 MHz provision to TMV8DC connector plugged RMV8DC amp TMV8DC into pins of rows C and D RMV8FPC amp Wire to board 4 096 MHz provision to TMV8FPC connector plugged RMV8FPC 8 TMV8FPC into pins of rows A and B RFPB 3 0 Pins AO A1 A2 and RFPB 3 0 grounded A3 shorted to pins BO B1 B2 and B3 res
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