Draft User Manual Ver 2.0
Contents
1. 6 jeb Te 8 DAL H20 P4 10 SD_D10 3 NOob lr DATO 3 IN OUT I O Memory Card Interface Data 0 4 These are the data lines for the SD connector They could be both input and output for the MCU depending on the data flow direction CMD OUT Output Memory Card Interface Command This is a command sent form the processor to the memory card and as such it is output from the processor CLK OUT Output Memory Card Interface Clock This signal is output from the MCU and synchronizes the data transfer between the memory card and the MCU Composite video Composite video J16 Signal Name Signal Name V_USBI LVDS port connector J8 A The signals that are coming out from the connector ARE NOT DISPLAY PORT SIGNALS regardless of the fact that the connector is the same UNUSED PIN HEADERS PORT extension Pind 1 3 P17 m02 T002 4 P24 AN4 OO P30 INTP3 SCK00 SCLOO F o DTH P23 ANI3 8_ P70 PCLBUZ1 P22 ANI2 9 P21 ANI1 AVreem 10 P20 ANIO AVrere O n SCKO1 SCLO1 SCLAO SDAO1 SDAAO P122 X2 EXCLK P137 INTPO P121 X1 LCD extension J9 RZ A1H Pin int 10 1 Signal Name P3 0 LCDO CLK P3 1 LCDO TCONO DE P3 8 LCDO DATAO B1 P3_12 LCDO_DATA4 B5 P3_14 LCDO DATA6 G1 P4_1 LCDO DATA9 G4 P4 4 LCDO DATA12 R2 P4_6 LCDO DATA14 R4 P3 10 LCDO DATA2 B3 P4 3 LCDO DATA11 R1 LA LA N Gn HIN KA P4_7 LCDO_DATA15 R5 P4 O LCDO DATAS G3 18 9 P3 15 LCDO DATA7 G2 0 J10 RZ2. A1H ind Pink P1A RIC2SCL 4 8B P1_Z RIICISCL R TPI 3 RIICISBA ooo P1_S RIICZSDA 8 P4 6 RIIC3SCL oo P4 5 LCDO DATA13 R3 N Pint ENE U KA SDRAM extension Pin Pin PR3 A A PAI P8_5 A13 PB AID PR AM5 PB AI Un LA l KA lA IKA 1 KA glajw v LO 1 9 J12 RZ A1H ind Pin P63 D3 A LD P6_5 D5 6 PGADA S P6 7 D7 DS LA l KAI KA l KA l KA d l Un l fe NI Wo KA PORT extension Pin Pin 909 GND LA Un LA l KA IKA I KA l eR glajw i v ON UW Pint J14 R Signal Name Signal Name ETT gt L C 5 P8100 6 P8 8 3 7 pasa 8 PB9 RxD3 ERIE aa L L KONNA 13 pod a4 P90 S MECHANICAL DIMENSIONS 105 0 4 1 J2 Ethernet s m SE CES gt all MW LS 8 VK RZ A1 all 74 0 2 9 Design amp Fab by iii lait J8 LVDS port M 2x USB standard A R63 RENESAS RL78 G1C ese FA ia 3 3V 24 24 22 20 00 120 61 137 GND _ 16 17 30 70 21 01 62 60 122121 3 oll Ee Cee Se J1 58 7 DC DC in 61 63 65 66 68 610612614 58 NC 80 B2 B4 86 714712710 76 74 72 NC NC 88 89 812814 90 1 18 60_62 64 67 69 611613615713715 81 83 85 87 711 79 77 75 73 71 NC NC 810811813815 91 NC RES TE CONNECTIVITY 5 98 7 Dimensions are in mm inch AVAILABLE DEMO SOFTWARE 1 FREERTOS TM DEMO PROJECT PORTED FOR IAR AND BUILT FOR VK RZ A1H development board 2 CycloneTCP PROJECT PORTED FOR IAR AND BUILT FOR VK RZ A1H deve
3. RZ A1H board use MCU R7S721000VCBG from RENESAS ELECTRONICS with these features e Power supply voltage VDD 3 0 to 3 6 V e Operating ambient temperature TA 40 to 85 C e Max CPU clock Ib 400 MHz For more information please visit www renesas eu BLOCK DIAGRAM DC DC 2x SPI flash Converter Abit I O Unused Pins Unused Pins AP3512 mode Juv U LVDS Port CPU LSI lt Micro SD Card RL78 G1C RZ A1H Mini B lt USB lt gt UART gt UART ch 3 Standard A Function Host Function EPROM 24C02 x KTC ch 0 lt Composite video T CAN ch 1 RJ45 LAN 10 100 E1 Emulator SMSC LAN8710A 1 CAN Infineon JTAG SDRAM 32 64 MB TLE6250 debuger A54C32W165A EXTERNAL SDRAM BASE ADDRESSES SDRAM CS2 ORIGIN 0x08000000 LENGTH 64MB SDRAM CS3 ORIGIN 0x0C000000 LENGTH 64MB SDRAM C52 mirror ORIGIN 0x48000000 LENGTH 64MB SDRAM CS3 mirror ORIGIN 0x4C000000 LENGTH 64MB A SDRAM is accessed with 16bit data width A A14 amp A15 are used for bank switching SCHEMATICS Please refer to CD for high quality pictures BOARD REFERENCE DESIGNATORS VK RZ A1 l J 2 fY Design amp Fab by kien ddaa gt x LIX 2x USB standard A R63 LVDS port TYCO CONNECTIVITY USB mini B
4. USB X1 crystal resonator MD CLKS m SSCG circuit OFF MD_CLKS sn SSCG circuit ON JTAG Debugger settings JTAG modefi AL Lc UN CAN Termination CAN modet EXTERNAL CONNECTORS DESCRIPTION PWR J1 Signal Name Pin Signal Name 2 3 The power input should be 5VDC E1 Emulator 5pin connector 4 TOOL JTAG 20pin connector JTAG J15 Signal Name Signal Name CAN 3pin connector Signal Name CAN_L CTX1 is connected to P5 10 pint A7 of R7S721000VCBG CRX1 is connected to P5_9 pin B7 of R7S721000VCBG A Termination Jumper JP3 Ethernet connector RJ45 type J2 A Transformer and integrated LEDS are connected controlled to PHY interface LAN8710A A Respective signals from PHY are connected to MII interface of R7S721000VCBG USB devices USB mini B J3 Signal Name Signal Name 2 _ GND A Pin 4 ID is disconnected V_USB1 Output USB device power D is connected to UDMO pin 23 of R5F1OKBC D is connected to UDPO pin 24 of R5F10KBC USB standard A J6 lower USB standard A J6 upper Signal Name Signal Name Signal Name Signal Name 5V 5V 2 D GND ND Both USB are configured as hosts lower D is connected to DMO pin AA11 of R7S721000VCBG lower D is connected to DPO pin Y 11 of R7S721000VCBG upper D is connected to DM1 pinHAA9 of R7S721000VCBG upper D is connected to DP1 pin Y9 of R7S721000VCBG Micro SD card slot MicroSD J4 O a VODs
5. codec unit capture engine unit pixel format converter e interrupt controller modules general I O ports The kit supports e Ethernet e LVDS Port e up to 128 MB SDRAM o Mini SD card connector e Composite video connector e one USB UART converter e two USB communication channels e 20 pins JTAG programing and debugging interface All this along with the DC DC power supply on board and connected to pin headers unused pins of R5F1OKBC 8 R7S721000VCBG allow you to build a diversity of powerful applications to be used in a wide range of embedded tasks BOARD FEATURES MCU RL78 G1C R5F10KBC e LSI RZ A1H R7S721000VCBG e USB Mini B device connector RL78 G1C e 2xUSB Standard A device connectors RZ A1H e CAN connectors Infineon TLE 6250 e LVDS Port connector RZ A1H e Composite video connector RZ A1H e Micro SD card connector RZ A1H e SDRAM 64 MB 2x32MB RZ A1H e Ethernet RJ 45 10 100Mb MAC RZ A1H e PHY SMSC LAN8710A e 20 pins Debug programming connector JTAG e _ 1 push RESET button e Power connector for DC DC 5V e FR 4 1 6 mm Green White solder mask component print e Dimensions 105 0mm x 74 0mm ELECTROSTATIC WARNING The VK RZ A1H R7S721000VCBG board is shipped in protective anti static packaging The board must not be subject to high electrostatic potentials General practice for working with static sensitive devices should be applied when working with this board PROCESSOR FEATURES The VK
6. J3 Composite video 1 18V 3 3V H A GN D fo as 21 ce EX 61 63 65 66 68 610612614 58 m a 82 84 S AF 37 76 a 72 89 812814 0 1 18 6 2 64 67 69 61161361571371 179 77 7 71 NC NC 810811813815 a NC RES H T 5 f N 5 re POWER SUPPLY CIRCUIT 0 A mn Ie on oc aN o NO ao O 9 SRZ NN ON NN VK RZ A1H is powered by 5 VDC applied at the power jack VK RZ A1H could also be powered by USB Mini B connector The consumption of VK RZ A1H may vary and the maximum is 3 3V 450mA CLOCK CIRCUITS Quartz Generator 13 3333 MHz is connected to EXTAL pin AA14 Quartz crystal 32 768KHz is connected to RTC_X1 RTC_X2 pins AA7 Y7 Quartz crystal 4 0000MHz is connected to RTC_X3 RTC_X4 pins V10 V11 Quartz crystal 48 0000MHz is connected to USB_X1 USB_X2 pins A13 Y13 Quartz crystal 27 0000MHz is connected to VIDEO_X1 VIDEO_X2 pins W21 V20 Quartz crystal 25 0000MHz is connected to Ethernet Phy SMSC LAN8710A XTAL1 XTAL2 pinst 5 4 PUSH BUTTONS H JUMPERS CONFIGURATION m Connected Disconnected BOOT configuration BOOT modet JP4 JP5 JP6 Boot from CSO 16 bit bus width 1 Boot from CSO 32 bit bus width Boot from SPI 3 multi I O cho P9 2 P9 5 SD card cho P4 10 P4 15 Boot from 5 Lll MMC card cho P5 10 P5 15 Clock settings CLK modet JP7 _JP8 CLK source from MD_CLK EXTAL crystal resonator CLK source from MD CLK
7. VK RZ A1H Development Board User manual T ZNTS RE 16 1 STOTIS TIZ NE 19 NG Ne 3V45V dL na ga gt 710 76 74 72 gt NC 88 89 812814 90 1 18 5 79 7 810811813815 91 NC RES C Rev 1 0 Dec 10 2014 Copyright c Vekatech Ltd All right reserved INTRODUCTION VK RZ A1 is a starter kit which uses MCU R7S721000VCBG from Renesas Electronics This powerful MCU is actually LSI single chip microcontroller that includes an ARM Cortex A9 processor along with the integrated peripheral functions required to configure a system The core includes a 32 KB L1 instruction cache 32 KB L1 data cache e 128 KB L2 cache Integrated various on chip peripheral functions and interfaces such as e 10 MB large capacity RAM 128 KB are shared by the data retention RAM e data retention RAM e multi function timer pulse unit 2 OS timer realtime clock e motor control PWM timer e UART UART with FIFO I2C SPI SPI multi I O bus controller CAN LIN serial sound interface sound generator CD ROM decoder e A D converter SCUX e media local bus SD host interface MMC host interface e NAND flash memory controller e IEBus controller Renesas SPDIF interface e Ethernet controller EthernetAVB e USB 2 0 host function e digital video decoder video display controller 5 e dynamic range compression image renderer image renderer for display e display out comparison unit e Renesas graphics processor for OpenVG e JPEG
8. lopment board 3 u boot Linux PORTED FOR GCC AND BUILT FOR VK RZ A1H development board
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