SNLA201 - Texas Instruments
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1. lowers the differential impedance requiring a lower value termination resistor Again the termination resistor s value chosen should match the loaded back plane impedance Note that loads less than 50 Ohms reduce the output signal swing below 350 mV compromising noise margins The typical capacitance of the DS92LV16 serial Bus LVDS inputs and outputs is about 5 pF 60 70 Rioap 2 Backplane Stubs No Stub Hider Stub Hider Minimize stubs ein multidrop multipoint applications Connectors e appropriate connectors e low skew low noise pin assignment Terminate backplane properly e value equals loaded differential impedance e adjust value s for best signal quality Stripline 1 DC Plane 1 DC Mane ALS Minimize s and adjust W for proper differen tial impedance Good e balanced Good e radiused corners e beveled corners BAD esharp 90 corners BAD e unbalanced layer change BAD e symmetry imbalance BAD e crosstalk BAD e path skew e pair not coupled BAD e path skew The LVDS pair should be treated as one signal Avoid unbalancing influences and keep TTL lines away from the LVDS pair PCB Recommendations General Printed Circuit Board PCB Recommendations W Use at least 4 PCB board layers Bus LVDS signals ground power and TTL signals E Minimize any resulting stub lengths In a point to point bus the resulting stub Is2. locking to random data are viable synchronization methods Either may be employed and in fact some systems may choose to employ both methods Once Lock is Acheived After the receiver is locked it will stay locked regardless of data pattern fixed with or without RMTs random periodic SYNC patterns or a mix of these patterns The receiver loses lock and enters the acquire lock state only after it detects two consecutive clock 0 1 bit errors Once locked the data between the clock bits do not affect the receiver s PLL Interconnect Jitter Budget Interconnect Jitter Budget Interconnect jitter budget is the amount of interconnect loading that can occur on the link before bit errors occur and is simply the ideal receiver noise margin teym specification The latest DS92LV16 datasheets specify both left and right IRNMI Indicating how much jitter the receiver can tolerate on either side of the ideal bit edge before bit errors occur The try y Specifications also allow the construction of an eye mask to validate the application s signal quality Jitter sources include Ml External Noise This includes excessive power supply noise cross talk etc W Interconnect Effects Inter symbol interference ISI attenuation etc E Clock Jitter excessive jitter on the serializer transmit clock TCLK Validating Signal Quality In conjunction with bit error rate test BERT measurements eye pattern mea surements are a good way to va
3. the transmit block to latch in the DIN 0 15 parallel bus and run the transmitter s PLL The TCLK input is LVTTL LVCMOS compatible The TCLK clock input tolerates jitter of 80 ps RMS allowing the use of non telecom datacom grade clock sources The receiver output clock RCLK can also be fed back to TCLK and data retransmitted as an external loopback or repeater though only two hops total are recommended before filtering out accumulated clock jitter Excessive jitter especially in the range of 200 kHz 2 MHz can appear on the serial outputs reducing link noise margins Be careful not to confuse RMS and peak to peak jitter For a typical clock sig nal with mostly random jitter i e gaussian distribution the jitter tolerance of 80 ps RMS is by definition approximately 1128 ps peak to peak ata 1012 bit error rate BER If TCLK is interrupted the chipset will go through the resynchronization proce dure upon reapplication of valid TCLK Receiver Reference Clock RefCLK The receiver reference clock is an LVITL LVCMOS compatible input and is used by the receiver to establish receiver PLL lock and prevent locking to a false harmonic Therefore the RefCLK characteristics are not very critical and the RefCLK frequency need only be within 5 of the TCLK frequency of the transmitter from which the chip is receiving data Unless a loopback test is being performed this RefCLK frequency need not be the same frequency as the chip s own TCL
4. 13 Unused Bits Low CIk0 Unused bits ted LOW place here Example showing two unused bits pulled high and two unused bits pulled low to avoid RM Ts Vec 8 KO 100 2 5 kQ An example of external faisafe biasing for the DS92LV16 See application note AN 1194 and LVDS Owners Manual sections 4 6 2 3 for details 11 Evaluating the DS92LV16 Evaluation Board 7 The DS92LV16 evaluation kit provides the ability to evaluate the DS92LV16 over AMP Z Pack cables 1 meter cable included or any user supplied intercon nect modified to connect to the boards The user manual can be downloaded from the web at www national com lvds and the kit itself ordered from autho rized distributors as part number BLVDS16EVK subject to availability Probing Bus LVDS Signals LVDS signals are high speed low swing signals Improper probing can result in deceiving results since the probe and or scope can filter high speed copo nents of the signal Using a 21 GHz bandwidth scope such as the Agilent 86100 or Tektronix 694C and a high speed differential probe such as the DS92LV16 eval kit order number BLVDS16EVK Tektronix P6247 8 or P6330 is highly recommended LVDS drivers are not com patible with 50 Ohm probes ES dai Ton eee eee ee aj 2 2 1m DL E E Z PRBS pattern at serializer output Note the embedded low high clock 0 1 bits OA A Tektronix 1GHz P6247 dif
5. D EDEDED EX IK developed in conjunction with major 8b 10b Coding Scheme Two 10 bit Codes telecommunications customers who desired features not provided by common 8b 10b datacom SerDes chipsets Instead of scram CTN DINT X DIN2 X DINS X DINA X DINS DING X DIN7 DING DINS X DIN1OXDIN1TX DINT2XDIN13X DINTAX DINTSX DINT6 _CIk0 bling each byte into a new 10 bit code as DS92LV16 Coding Scheme 16 bits plus Embedded Clock Bits with 8b 10b coding the Bus LVDS SerDes coding scheme frames each data word with DS92LV16 embedded clock coding scheme showing 16 data bits plus clock 0 1 bits two embedded clock bits one high and one low These embedded clock bits create a rising edge transition which provides precise timing and framing information to the receiver on every clock cycle The resulting benefits of the Bus LVDS SerDes architecture include E Lock to random data for true hot plug capability lock can be achieved without interrupting traffic with PLL training patterns and without a loss of lock feedback path from receiver to transmitter W The relaxed 5 RefCLK frequency specification means the receiver does notrequire a pre Periodic cise reference clock source to recover data reliably Embedded Clock Transition W Jitter tolerant TCLK transmit clock input eliminates the requirement to use a high grade tele com datacom transmit clock source and also simplifies external loopback operations WE Non byte oriented bus widths
6. DS92LV16 HA Texas INSTRUMENTS Literature Number SNLA201 e Bus LVDS SerDes Architecture October 2002 page 3 e Bus Topologies page 4 ee ia ho Nace aan hal Ae bead hd be e Backplanes at y pagen 3 e PCB Recommendations page 6 e Cables amp Connectors page a n A Se f a Seer ce acy ec a a E a aes e ae e Power amp Ground pages 8 9 e Clocking page 10 fi 5 A a TE a ai me e e i So da a Dee nr Sa a NT Pa SRS ca e Inputs Outputs et a E e Evaluating the DS92LV16 page 12 a Se a ene See s a a ee eo e A ae RCE Name joa sat ES oe ee Bee E oo e Loopback Testing page 13 toe n e Lock to Random Data vs Sync Patterns aot e ion A ee oe page 14 SCC an ous i OWE OM j pages 15 1 e Troubleshooting page 18 AEP 0d SETAE obs e Additional Resources Serializing N j de Simple page 19 a Www natignal com Ivds Flexible Clocking e Independent Tx amp Rx channels e 25 80 MHz each e Separate power downs Line amp Local Loopbacks Receiver Locks to Random Data Local Clocking e Tx clock Rx RefCLK can differ by up to 5 2 Power Down Data In 16 LVTTL Data Out 16 LVTTL 9 nck RxCLKOUT Power Down Introduction The DS92LV16 is a member of National s robust and easy to use B
7. K signal since the transmit and receive blocks are fully independent i e upstream and downstream data rates are independent The relaxed RefCLK specs mean that the RefCLK signal can be generated locally using a common low cost clock source In fact the RefCLK signal could even be removed once the receiver is locked though this is not recom mended Receiver Output Clock RCLK The receiver output clock is an LVCMOS output whose rising edge is aligned to the middle of the receiver output data ROUT 0 15 The subsequent ASIC FPGA device should latch in ROUT 0 15 data meeting the ASIC s FPGA s input setup and hold times Output jitter for RCLK is not specified on the datasheet since it depends on the jitter of the incoming data and the TCLK clock source Inputs amp Outputs Unused LVTTL Inputs Unused LVTTL inputs may be left floating or tied high or low The device datasheet indicates the presence of pull down devices to bias unused pins These internal impedances tend to be in the 200 kOhm range and may be overridden with lower value pull up resistors if desired If not using the full 16 bits of the payload careful attention needs to be taken to avoid disrupting the random lock feature These unused bits will still be transmitted so in order for the receiver to maintain random data lock capability care must be taken not to create a situation where the unused bits cause a repetitive multiple low high transitions RMTs Avoid th
8. also be employed if desired The backplane should be designed with sufficient bandwidth to support the desired data rate For example for 1 Gbps 500 MHz a media bandwidth of 1 5 GHz is typically required Multidrop In some instances the DS92LV16 may be used in multidrop backplanes driving a 2 4 receiver loads Actual performance depends on the bandwidth of the interconnect Pay close attention on minimizing stub lengths connector plus trace to lt 2 cm Depending on data rate National s LVDS DS90LV001 or other future stub hider chips should used to reduce stub lengths seen by the sig nal on the backplane Receiver loads should be widely spaced to reduce the transmission segment to stub length ratio and or placed far away from the transmitter to allow the edge rate to be slowed by the interconnect before reaching the first stub Due to fast edge rates the DS92LV16 is typically not recommended for driving more than a few multidrop loads Termination Termination is required Choose the termination resistor value Ry to match the loaded differential impedance of the transmission line In a point to point backplane the termination value is typically 100 Ohms If a smaller output sig nal swing is desired the line may be terminated at both the transmitter output as well as the receiver input reducing the effective load seen by the transmit ter by half In a multidrop backplane the added capacitive loading of the extra receivers
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10. e filter If employed a separate pie filter is rec ommended for each PLL to minimize the voltage drop due to series resistance Separate board power planes for each PVDD are typi cally not required AVDD AGND LVDS Supply The AVDD pins the DS92LV16 has 4 AVDD pins supply the LVDS ciruits Due to the nature of the DS92LV16 design large currents are not drawn through these pins and a 0 1 uF capacitor is sufficient for these pins If space is available a 0 01 uF capacitor may be used in parallel with the 0 1 uF capacitor for additional high frequency filtering Connect the AGND ground to the cable ground to provide a Power amp Ground continued return path for any common even mode currents Most of the LVDS current is odd mode and returns within the pair though a small amount of odd mode cur rent may be present due to coupled noise and the cable ground should return through a low impedance path to AGND Power Dissipation Transmitter Receiver DVDD DGND Digital Supply The DVDD pins supply the digital portion of the device and also the receiver out put drivers The receiver DVDD is more critical than the transmitter DVDD because it must power the receiver outputs during multiple output switching a conditions Four DS92LV16 receiver outputs are powered by each DVDD pin Frequency MHz suggesting that a minimum local bypass capacitance of 28 nF is required This EN is calculated by taking 4 times the maximum short circuit current 4
11. e mode with a high speed gt 1 GHz high impedance gt 100 kQ differential probe The TCLK signal should be used as the trigger Eye Pattern Full eye pattern captured by the scope set to variable persistence mode 3 Use the vertical cursor function of the scope to place a vertical cursor over the average OV differential crossing point of the clock 0 bit clock 1 bit low to high transition This cursor position is now the ideal time point to which all other positions will be referenced ldeal Waveform DIM fo 1X 2 3 K 4X 5 KX 6X7 KX 8 KX 9 XK 0 KX MX 2X BK 4X BX 16 co fns 248 18 fng na Bng Tns Sns Y Wrs Mas as Bag Yas Pas Cng Vag Bag Clock Period 1 TELK Ideal bit edge positions are always multiples of T 18 away from the ideal clock0 clock1 low to high transition Align ideal waveform fo eye pattern here AM AMO A EA BT AD AD OO 2 13 A 5 AA 1118 2 18 3448 418 5 18 6 18 118 8 18 9 18 10 18 Mag 12 18 Big 14 18 15 18 1648 Tag 18 18 Clock Period 1 TCLK The receiver jitter margin for any bit on the eye pattern can be calculated based on its ideal bit edge positions 16 Note These eye patterns are computer generated for clarity Interconnect Jitter Budget continued 4 Select the bit eye pattern in which to place the receiver input jitter mask The worst case bit i e the bit with the most closed eye is
12. ed in the datasheet When the deserializer s LOCK pin goes high the receiver has locked to the incoming data stream and valid data appears at the receiver outputs Lock to Random Data The receiver will also lock to random data without external system interven tion providing a powerful plug amp go system capability not provided by most SerDes chipsets In order to achieve this the receiver looks for a consistent low high transition caused by the clock 0 1 bits If there are two data bits con sistently stuck low high over multiple clock cycles known as a repetitive multiple transition or RMT the receiver will not lock until these bits change and the receiver recognizes the unique embedded clock low to high transi tion Sending SYNC Patterns versus Lock to Random Data Sending SYNC patterns has the advantage that the receiver lock time is guar anteed to be less than tpgp max This can be useful in some systems and the sending of SYNC patterns can be achieved by controlling the SYNC pin through system logic or by feeding back the LOCK pin to the SYNC pin The receiver will lock to random data without system intervention though the lock time will depend on the data pattern This feature is useful in systems in which there is no quick or easy feedback path from receiver to transmitter or in systems which cant afford to interrupt data flow by sending special training patterns Both lock modes sending SYNC patterns and the
13. ferential probe Note two i p a probe contacts and polarity indication in probe tip E E detail E a o 12 SYNC pattern at serializer output Loopback Testing The line and local loopback modes allow the designer to isolate and test selected portions of the system Local Loopback Asserting the LOCAL_LE pin high connects the parallel LVTTL data bus DIN 0 15 internally to the receiver output ROUT 0 15 This mode includes all the functional blocks of the SerDes pair except the Bus LVDS input and output structures the transmitter Bus LVDS outputs are in TRI STATE Switching the DS92LV16 to local loopback mode therefore means the receiver will relock to the loopback data and RefCLK must be within 5 of the local TCLK frequen cy The local loopback mode allows the local card to verify it is sending receiving and processing data properly Line Loopback The DS92LV16 will enter the line loopback mode when the LINE_LE pin is brought high This connects the Bus LVDS transmitter output DO pins inter nally to the receiver input RIN pins and to the parallel LVTTL data bus ROUT 0 15 This loopback test mode includes the serializer deserializer blocks The line loopback mode allows the system to verify that the board to board links are operating properly Low Cost Crystal MMY VS A A A E GA i Due to the relaxed clocking requirements of the DS92LV16 external line loop back withi
14. is by tying bits high at the LSB inputs starting with DINO and bits tied low at the MSB inputs inputs ending with DIN16 Floating Bus LVDS Receiver Inputs amp Failsafe In the event that the DS92LV16 receiver is disconnected from the backplane cable the internal failsafe circuitry is designed to reject a certain amount of differential noise about 10mV from being interpreted as data or clock This seems like a very small threshold but balanced closely coupled LVDS lines tend to pick up noise as common mode not differential The CMOS ROUT 0 15 outputs of the DS92LV16 deserializer will be TRI STATE when the incoming serial data is removed and the receiver loses lock Additional failsafe biasing can be implemented externally see application note AN 1194 and LVDS Owners Manual sections 4 6 2 3 at the expense of two additional resistors Receiver CMOS Output Drive The receiver CMOS outputs are specified at 9 mA This is typically sufficient to drive 2 3 LVTTL LVCMOS loads If more loads will be driven especially at higher clock speeds a logic buffer is recommended Note that depending on actual configuration number of loads stub lengths segment distances etc the receiver output bus may need to be treated as a transmission line and proper LVTTL LVCMOS termination techniques employed Ciki Unused Bits High DIN2 X DIN3 X DIN4 X DINS X DING X DIN7 Unused bits tied HIGH place here DING X DIN9 X DIN10 X DIN11 X DIN12 X DIN
15. l pull the input to a valid state E Termination of the Bus LVDS signals is required The termination resistor value should match the differential impedance of the transmission line 100 Ohm is a typical value for point to point applications It is better err with too large a termination resistor than too small E Isolate TTL CMOS signals from Bus LVDS signals placing them at least 3s or 2w away whichever is larger This will help to prevent them from coupling onto the LVDS lines These are just a few common practices that should be followed when design ing PCBs for LVDS signaling General application guidelines are available in the LVDS Owner s Manual and other documents at www national com lvds Cables amp Connectors Cables The DS92LV16 can be used over a wide variety of balanced cables depending on distance and signal quality requirements In general twinax or twisted pair cables are recommended E Typical Connections can be made using category 5 CAT5 twisted pair eth ernet cable with RJ 45 connectors See graph at right for typical data rate ver sus cable distance E Higher Speed Links AMP Z PACK cables or other twinax cables can be used El Higher Pincount SCSI type cables and connectors or LVDS type cable assemblies such as the 3M MDR and Amphenol SKEWCLEAR systems are commonly used W Very Short Distances lt 0 3 m flex circuit following correct PCB layout or unbalanced ribbon cable
16. lidate the robustness of a high speed link While BER tests generally produce a pass fail result viewing the eye pattern at the receiver inputs gives a more qualitative indication of how much margin a given link has The amount of eye opening around the receiver input jitter mask is a qualitative measure of the links noise margin The receiver input jitter mask is constructed in the following steps 1 Make sure the link is operating and sending the desired pattern normally a PRBS pattern Ideal Bit Width ns at Common Frequencies Miz _ns MHz 30 1 852 50 30 72 1 808 52 33 1 684 61 44 35 1 581 62 5 38 8 1 432 66 39 44 1 409 18 88 40 1 389 80 Ideal Bit Width 1 TCLK frequency important Make calculations to the nearest picosecond Ideal Waveform relative to stop start edge Ideal Strobe Position Receiver Sampling Window Receiver Threshold tanmi right tRNMI left l 1 l l I l l l l 1 I l I l 1 I 1 I 1 J I l l l tpit 7 tpit left right I l 1 l J l 1 l 1 l l l 1 l i l 1 l l l 1 i I I l I l This section of the design guide shows how to construct a receiver input jitter mask This eye pattern is computer generated for clarity Interconnect Jitter Budget continued 2 Capture the entire eye pattern at the receiver inputs using a high bandwidth oscilloscope in variable persistenc
17. may even be used If running multiple Bus LVDS pairs in the same cable assembly use individual ly shielded pairs to minimize crosstalk between the pairs At least one ground conductor should be used in the cable connecting to the DS92LV16 analog grounds AGNDs to provide a known low impedance return path for com mon mode currents A termination resistor Rj placed as close as possible to the receiver inputs in point to point applications is required The resistor value should be chosen to match the differential impedance of the cable Connectors Connectors with differential conductors offer the highest performance but are not necessary in typical lower speed or short distance applications For sin gle ended connectors keep LVDS pins away from other signals particularly TTL CMOS LVTITL LVCMOS signals The and signals of a pair should be routed on the same row in multi row connectors to help minimize skew For high speed applications gt 800 Mbps using differential optimized connectors is recommended e Length ji ji ii ueni ro WI Less than 10 4 error rate under typical conditions over CATS ethernet cable and RJ45 connectors Typical CAT5 ethernet cable length versus fre quency CAT5 ethernet cable with RJ 45 connectors Twinax type cable assembly Power amp Ground General Recommendations A solid power ground system is the foundation on which a reliable interco
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19. n an FPGA or ASIC can also easily be performed to test portions of the system logic in addition to the DS92LV16 and interconnect TCLK ANNA hi DA 1010111 1 manaman 10 w i i IF z o al W i il I PLL amp Serial te JE Timing i Recovery Mi RCLK 0 Ir AN Local loopback mode po TUU arallel to Serial Input Latch TCLK ROUTI0 15 sak RCLK Line loopback mode 13 TRI STATE oming B DLH1011 DLHO100 LHOOO LH1101 LHO11 0 ILH100 DLHO111 L H 1011 DLHO100 1LHO0O DLH110 1 1LHO11 0 ILH100 yLHO11 H Start Bit L Stop Bit Incoming data stream arranged in 18 bit words showing no RMTs Receiver will aqcuire lock g 0 i 0 1 1 0 1 0 1 0 1 1 0 oSo o02 00 0 0 00 20 000 0 000 e ee a a r m H Start Bit L Stop Bit RAMIS Incoming data stream with RIMT s RMT s must dis appear before the receiver can acquire lock 14 Lock to Random Data vs SYNC Patterns SYNC Patterns SYNC patterns H1111111100000000L where H is the clock 1 bit high and L is the clock 0 bit low are sent automatically by the transmitter when the SYNC pin is held high The receiver will lock to this pattern within a guaran teed time see tpsp specifi
20. nnect system is built Design circuit board layout and stack up for the system to provide noise free power to the device Good layout practice will separate high frequency and high level inputs and outputs to minimize unwanted stray noise pickup feedback and interference Power system performance may be greatly improved by using thin dielectrics 4 to 10 mils for power ground sandwiches This increases the intrinsic capacitance of the PCB power system which improves power supply filtering especially at high frequencies making the value and placement of external bypass capaci tors less critical External bypass capacitors should include both RF ceramic and tantalum electrolytic types Use RF capacitors in the range of 0 001 uF to 0 1 uF Use tantalum capacitors in the range of 2 2 uF to 10 uF The voltage rating of tantalum capacitors should be at least 3 5 preferred times the power supply voltage being used It is recommended practice to use two vias at each power ground pin as well as all RF bypass capacitor terminals Dual vias reduce the interconnect inductance by up to half thereby extending the effective range of bypass components Locate RF capacitors as close as possible to the supply pins and use wide low impedance traces not 50 Ohm traces Surface mount capacitors are recommended due to lower parasitics When using multiple capacitors per supply pin locate the smallest value closest to the supply pin A bulk capac itor is recommended a
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22. r PDF Fama sianal integrit and val IETA of Bus L echnology in heavily ae backplanes DesignCon99 Paper is oS SEE ae co ooyr ne EE S Na sr ral sem ation The LVDS Owners Manualteaches what LVDS is how it works what its at advantages are how to design with tt It should be part of every high speed interconnect designer s library The LVDS Owners Manual can be down loaded from the web at www national com lvds or ordered from one of owners National s sales representatives Manual i 2nd Edition Summer 2000 RAPIDESIGNER Slide Rule National Semiconductor s Transmission Line RAPIDESIGNER Slide Rule makes PCB stripline and microstrip transmission line calculations quick and easy The slide rule is available in both metric and English unit versions Instructions and equations are given in application note AN 905 Contact Information See back cover for contact information or visit www national com contacts Information Web e Visit our web site at www national com lvds for more techni cal information For sample orders please click on the product name under Product Folder Email Phone Fax Americas Email support nsc com Phone 1 800 272 9959 Fax 1 800 737 7018 Europe E NC Email europe support nsc com e g b t Phone Deutsch 49 0 69 9508 6208 I a I S English 44 0 870 24 0 2171 acai Fran ais 33 0 1 41 91 87 90 milliwatts Fax 49 0 180 530 85 86 A
23. r relevance E Power Supply Noise Excessive supply noise especially on the PLL supply PVCC can add jitter to the transmitter serial output and affect the receiver data sampling Keep supply noise under 100 mV peak to peak on the PVCC pins W Transmit Clock Minimize excessive cycle to cycle jitter on the transmit clock TCLK in the range or 200 kHz 2 MHz which can add jitter to the trans mitter serial output W Serial Bus Should follow LVDS PCB layout and backplane recommenda tions using proper termination avoiding long stubs and assuring the termina tion resistor is close to the receiver input W Parallel Bus The parallel LVITL signals should not violate any setup and hold times and should be free from excessive overshoot undershoot High speed line e controlled impedance Ss D 2 N ES 2 is pe gt pu Qa j Termination close to Rx input Output Latch Serial to Parallel a Timing A Recovery Additional Technical Resources National National Semiconductor LVDS Feature Web Site ed me y fo MY Sign On Create Personal Preferences Notifications Languages Bill of Materials WEBENCH mple Private Site e LVDS Solutio s for Enel sh Uni st RAPIDESIGNER www national com lvds is a one stop shop for device information and techni cano ps cal information such as application notes white papers the LVDS Owner s gt a Manual evaluation board doc
24. recommended The ideal crossing points on either side of the nth data bit will be n T 18 and n 1 T 18 away from the ideal stop start crossing point set in step 3 where T is period of the TCLK frequency 16 data bits plus 2 clock bits 18 bits 5 Calculate the ideal bit edges being careful to avoid rounding errors and place a cursor at both ideal bit edges of the selected bit 6 Add tRNMI le t to the ideal left bit edge and tRNMI ri ht to the right ideal edge to get the positions of the receiver input jitter Dask 7 The height of the jitter mask is the receiver s differential input threshold VTH Vr This is typically 50 mV though the datasheet value of 100 mV can be used if a more conservative estimate is desired 8 The receiver input jitter mask should now look like a box inside the eye of the bit The white area shown in green in the diagram at right around the box is the relative noise margin of the link As long as the captured eye open ing stays out of this noise margin box the chipset should operate error free Alternative Jitter Measurements The taNMI left right SPecs can also be used to get a quantitative estimate of remaining jitter margin The quantity try my jitter tgym of the worst case side see diagram at right is the percentage jitter margin left before bit errors are expected to occur The total amount of jitter budget available for the interconnect i e how much jitter budge
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26. such as 10 bits are available Simple passive i 5 E termination Y No receiver to transmitter feedback required Bus LVDS Bus LVDS Y Non critical 7 l RefCLK 5 Efficient coding a e only 2 extra bits per 10 or 16 bit word Y e no bandwidth loss to idle comma characters Wide frequency range jitter tolerant TxCLK oe Plug amp Go live insertion ATA DATA DATA DATA DATA DATA I r Multidrop capability JDE CODE CODE E DC balanced coding for opto modules AC coupling 8b 10b 8b 10b Loss of word alignment feedback and or periodic comma character transmissions Overview comparing the DS92LV16 to 8b 10b SerDes architectures 3 The DS92LV16 is designed mainly for point to point applications but you may also use it for multidrop interconnects under certain circumstances Point to Point The DS92LV16 can deliver the full 1 28 Gbps payload in each direction over point to point backplanes and cables distance depends on cable quality transmission speed etc This performance is also possible when driving mul tiple receivers through a low jitter LVDS to LVDS switch distribution chip in a distributed point to point configuration In all point to point applications you must place a termination resistor close to each receiver input Multidrop The DS92LV16 may be used in limited multidrop also known as point to multi point backplane applications driving a few recei
27. t is allowed for the cable or backplane is calculated similarly by subtracting maximum transmitter deterministic jitter tp y from receiver ideal noise margin try mI Jitter budget left side tRNMI left 1DJIT max Jitter budget right side tRNMI right DJIT min tp yy min is a negative number Note These eye patterns are computer generated for clarity Ideal Waveform relative to stop start edge Ideal Strobe Position Receiver Threshold Sampling Window tRNMI i right tanmi left 7 tpit left right Receiver input jitter eye mask construction noise margin area Receiver Sampling Window Qualitative analysis of interconnect margin green Jitter Tolerance Margin Jitter Margin Receiver A Z Receiver Sampling Window a Sampling Window Ideal Waveform Bit Edge The trym specs can also be used around the ideal bit position to guage the percentage of jitter margin left before bit errors could occur 17 Good bypassing e Vcc noise lt 100 mV peak to peak Meet setup amp hold times Minimize low frequency cycle to cycle input clock jitter Watch output loading e possible transmission line 18 Troubleshooting Troubleshooting The DS92LV16 is a robust easy to use SerDes and application issues should be rare If application problems do occur the causes can normally be traced to a few simple easy to check areas listed in orde
28. t the point of power entry This Is typically in the range of 50 uF to 100 uF and will smooth low frequency noise Some devices have separate power ground pins for different portions of the circuits to isolate switching noise effects between differ ent blocks Connecting these to separate power ground planes on the PCB is typically not required Pin description tables typically describe which blocks are connected to which power ground pins In some cases an external filter may be used to provide clean power to sensitive circuits such as PLLs DS92LV16 Recommendations General device specific bypassing recommendations are given below Actual best practice depends on other board and system level criteria including board density power rail and power supply type and the supply needs of other integrated circuits on the board PVDD PGND PLL Supply The PVDD pins the DS92LV16 has 2 PVDD pins supply the PLL circuits PLLs require a clean supply less than 100 mV noise peak to peak for the minimization of jitter PVDD noise in the frequency range 200 KHZ to 5 MHz can increase jitter and reduce noise margins Certain power supplies may have switching frequencies or high harmonic content in this range If this is the case filtering of this noise spectrum may be required A notch filter response is best to provide stable VDD suppression of the noise band and good high fre quency response clock fundamental This may be accomplished with a CRC or CLC pi
29. ties may be subject to additional restrictions Resale of Tl products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Tl products are not authorized for use in safety critical applications such as life support where a failure of the Tl product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications Tl products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by Tl as military grade or enhanced plastic Only products designated by Tl as
30. typically the distance between the termination resistor and the receiver input pins of the DS92LV16 Place the small surface mount resistor as close to the receiver input pins as possible In a limited multidrop bus the termination Is typically at the far end of the bus only The resulting stubs are from the main line to the receiver inputs and these distances should be minimized MW Segment impedance matching in a backplane point to point bus the location of the serializer and deserializer is less critical More important is matching the impedance of all transmission line segments These imped ances should be matched within 10 of the nominal value E Controlled impedance differential traces of 100 Ohms are typically recom mended for Bus LVDS signals Edge coupled microstrip edge coupled stripline or broadside coupled stripline differential traces may be used These traces should be closely coupled i e s should be minimized to ensure cou pled noise will appear as common mode which is rejected by the receiver This has the added benefit that closely coupled lines that are excited with odd mode transmission tend to radiate less electromagnetic energy Ml Treatthe LVDS pair as one signal avoiding influences that cause imbal ances within the pair see diagram at left Minimize skew within the pair Maintain balance W Leave unused Bus LVDS receiver inputs open floating the internal fail safe in the DS92LV16 wil
31. umentation IBIS models frequently asked ES e IBIS Interface Models questions online seminar materials and much more o aos LYDS Application Note Selection Guide LYDS FAQs A dozen Frequently Asked Questions and Answers on LYDS Bus LYDS SER DES FAQs Frequently Asked Questions and Answers on the Serializer Deserializer Bus LVDS chipsets asheets Applic atio INTERFACE Da tasheets en Bea lie tio n Notes CDROM o Design Guides What s New B gt January a 2001 a sign Guide NEW 2a a Na ana nal Sem anaua EDITION LVDS O AG a naive Spas ed uide Bu itn Bete st EIST Capability te 10 1 LVDS Se Chipset LYDS White Paper PDF Format Gigabit Backplane Design Simulation a onductor easurement the unabridged story val oF LVDS pe rfo ormance DesignCon2001 Paper large PDF poner rin ite Sara wative Package Design Mbyte andon eRe e SI a at Des nea n 2001 BLVDS White Pa r PDF Format A S gt October 2 a SCAN9ZLV090 National of iah S Spa ad Differ ential Se ernical neue First to add Bout paan ary SCAN Test Ba ee e Des ignca n2000 pabili lity to o Low Voltage Differential Sic fan alin ag LVDS BLYDS White Pa PDE corms E Bus une 29 zopa ps92Ly1023 122 an National LVDS Expal ne E Applica emici enduct belly nm Voltage Differentia Sn alin 9 LVDS Se elize De mializer Chip Set far Internet 000 Pa F DesignCot n20 and Wir cles ie In fra str uctur e Syst LVDS Owner s Manual Bios whe Pape
32. us LVDS serializer deserializer SerDes family already popular in a wide variety of tele com datacom industrial and commercial backplane cable interconnect applications The DS92LV16 is similar to the original 10 bit Bus LVDS SerDes products but provides a wider 16 bit data bus payload The DS92LV16 is very flexible and performs over a wide 25 80 MHz frequen cy range Both the transmit clock and receiver reference clock have high jitter tolerance allowing the use of low cost clock sources The serializer and deserializer sections are fully independent and can be operated at different frequencies This is useful when upstream and downstream rates are not bal anced In addition the serializer and deserializer blocks can be powered down independently if only one transmission direction is needed The receiver locks to random data eliminating the need to interrupt normal traffic with PLL training patterns after hot plug events The usual loss of lock feedback path from receiver to transmitter is also not required Line and local loopback test modes allow the designer to segregate portions of the system to facilitate system diagnostics 400 1280 Mbps each direction gt lt a oy Input Latch Parallel to Serial Output Latch Serial to Parallel PLL amp Clock o Timing a Recovery Bus LVDS SerDes Architecture The Bus LVDS SerDes architecture was DED EDEDED EDEDED SX KK EDEDE
33. ver loads The output struc ture is a modified Bus LVDS type circuit that regulates the Vop output differ ential voltage over a narrow range of loads The driver expects to see a 100 Ohm load but may also operate with loads as low as 50 Ohms with reduced voltage swing The number of receivers allowed depends upon the bandwidth of the interconnecting path the spacing of the nodes and also the length of the resulting stubs The DS92LV16 s fast Bus LVDS output edge rates are opti mized for the high throughput of the part thus stub length must be minimized mechanically or electrically using stub hider buffer devices See the Backplane section for more information Tipica Bus Performance Bus Topologies Applications Point to Point Cable or Backplane Ds921y16 Mu EST A Backplane or casio AJA Pes AA sb Distributed Point to Point Cables or Backplane Switch or Splitter e g DSSOCP04 DS90CP22 DS92LV16 DS9OLV110 etc ES F eS E DSG IH DS92LV16 Match segment Zo s amp RT impedances within 10 10 missmatch 5 reflection Minimize stub lengths 3 Use appropriate connector pin assignment amp routing Backplanes Point to Point The DS92LV16 achieves the maximum 1 28 Gbps performance in controlled 100 Ohm differential impedance point to point or distributed point to point FR 4 backplanes though other backplane materials such as GETEK Rogers or hybrids may
34. x 85 mA 340 mA multiplying by the output rise time 4 ns and then dividing by the max imum allowed VDD droop assume 50 mV and yields 27 2 nF Rounding up a standard 0 1 uF is selected for each DVDD pin DS92LV16 typical total lp y versus frequency 3 3 V 25 C Power Up Sequencing The DS92LV16 does not require a specific power up sequence Best practice Is power up all VDD pins together apply clocks RefCLK amp TCLK and then bring PWDN powerdown pins high to enable the transmit and or receive channels The chip has a power on reset POR circuitry which holds the outputs in TRI STATE until the supply is above approximately 2 5V Since all VDD pins PVDD AVDD amp DVDD are related internally they must be powered up and down together 3 3 0 Config Config2 3 3 Y Optional AVDD DS92LV16 reno Typical connection diagram showing power supply bypassing Employ suffi cient bypassing to ensure lt 100 mV peak to peak noise on supply pins espe cially PVDD Each DVDD pin should have separate bypass capacitance Clocking a E E E SAME N Jitter Frequency Hz TCLK jitter tolerated versus jitter frequency before bit errors occurred on DS921V16 to DS92LV16 link Tested under typical conditions Maximum RMS TCLK input jitter tolerance versus jitter frequency under typical conditions Transmit Clock TCLK The transmit clock TCLK rising edge is used by
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