User Manual - Connect Tech Inc.
Contents
1. Connect Tech Inc Embedded Computing Experts PCI 104 to PC 104 Adapter User Manual x Connect Tech Inc 2 tg PCI 104 to PC 104 Adapter Gil vw conrectiech com Li vlt E Les ie wn ca ca em T Du 1 bk m d EI emm ER Ae SS P LJ L d Lr AE l 1 Lam Fe os AE A E ad Connect Tech Inc 42 Arrow Road Guelph Ontario NIK 1S6 Tel 519 836 1291 Toll 800 426 8979 North America only Fax 519 836 4878 Email sales connecttech com support connecttech com Web www connecttech com CTIM 00108 Revision 0 00 November 16 2012 CTs Connect Tech Inc PCI 104 to PC 104 Adapter User s Manual Limited Lifetime Warranty Connect Tech Inc provides a lifetime warranty for all of our products Should this product in Connect Tech Inc s opinion fail to be in good working order during the warranty period Connect Tech Inc will at its option repair or replace this product at no charge provided that the product has not been subjected to abuse misuse accident disaster or non Connect Tech Inc authorized modification or repair You may obtain warranty service by delivering this product to an authorized Connect Tech Inc business partner or directly to Connect Tech Inc along with proof of purchase Product returned to Connect Tech Inc must be pre authorized by Connect Tech Inc with an RMA Return Material Authorization number marked on the outside of the package and sent prepaid insured and packaged for s2. 22 er eo se ae arya 1s 14 13 2 a iw 9 x x x x x x x x x Page 12 of 19 Date June 22 2012 CTs Connect Tech Inc PCI 104 to PC 104 Adapter User s Manual Interrupt Control Registers INT STATUS 0x00 ISR o o l ooe To o o oe o ts INT ENABLE 0x04 irais moa mo mou om woe ER EE ee EES Offset 0x00 10 0 Interrupt Enable Register IER The Interrupt Enable Register IER is used to enable the detection of the connected PC 104 ISA interrupt lines Writing a 1 to the desired IRQ will enable the detection of that IRQ when an enabled interrupt is detected the PCI 104 to PC 104 Adapter will update the interrupt status register and generate a PCI interrupt Offset 0x04 10 0 Interrupt Status Register ISR The Interrupt Status Register ISR is used to display the current state of enabled PC 104 IRQ lines When a PCI interrupt is generated by the PCI 104 to PC 104 Adapter this 32bit register Bar 0 offset 0x00 can be read to indicate which IRQ is generating the interrupt Interrupt Generation Two configuration bits within the BARO MISC_CMD register BARO offset 0x10 bits 3 2 control the adapter s interrupt mode 0x10 M CM e 00 PCI interrupt generation of detected and enabled IRQ lines with status register output default Upon the detection of an enabled IRQ interrupt the PCI interrupt is driven low The Interrupt Status Register ISR BARO reg 0x00 ca
3. EEP_WR This bit initiates a write operation to the EEPROM When set to 1 the PCI 104 to PC 104 Adapter will write the current values of the configuration registers into the EEPROM After the write is complete the EEPROM write complete bit will be set high BARO offset OxOC bit 31 and the heartbeat LED will blink more rapidly Offset 0x0C 31 EEKPROM Write Complete EEP_RST When a write operation is initiated by setting the EEP_WR bit the PCI 104 to PC 104 Adapter will write a 1 to this bit to indicate the write has completed In addition to this bit being set the heartbeat LED will blink more rapidly Once the write complete has been set another EEPROM write will not occur until a 0 is written back to the EEPROM write start bit The LED will also continue to blink rapidly until the EEP_ WR bit is set back to 0 Miscellaneous Command Configuration Register MISC_CMD 0x10 MISC_CMD 5 wm wi 2 nu wm os s 7 e s_ oOo 1 IT o 1 0 GPIO Direction Register GPIO_DIR Used to control the direction of the Digital I O For more information regarding the GPIO_DIR register please see the GPIO section of the manual 3 2 Interrupt Mode Register INT MODE Used to set the interrupt mode for the Adapter For more information regarding this mode see the Interrupt Generation section of the manual 4 Transmit FIFO trigger Setting TX_FIFO The PCI 104 to PC 104 Adapter uses an i
4. PC 104 Adapter operates as a Single function PCI device and therefore the card implements one interrupt located on the INTA signal of the PCI Bus The interrupt is driven from multiple maskable IRQ sources from within the FPGA The Interrupt Enable Register IER is used to enable the detection of the 11 PC 104 IRQ lines and generate the corresponding PCI Interrupt Refer to the Interrupt Control section below for further details Revision 0 00 Page 8 of 19 Date June 22 2012 CL Connect Tech Inc PCI 104 to PC 104 Adapter User s Manual PC 104 ISA Host Interface The Default I O Address Windows allow PCI I O space accesses to be translated into PC104 ISA bus accesses at three commonly used I O ranges 0x100 Ox1 FF BAR1 0x200 Ox2FF BAR2 and 0x300 0x3FF BAR3 If PC 104 transactions are required at address ranges outside of these three ranges the BASE_ADDR register must be set to a new base address value To keep the new custom settings consistent at reset and system start up the new setting s must be written to the on board EEPROM More information on writing to the EEPROM can be found in the EEPROM Interface Registers section of the manual PC 104 ISA VO and Memory Window Configuration Default Starting Offsets ISA I O Space Default Configuration ISA Memory Space Default Configuration BAR1 256K RARA 16M BASE ADDR 1 0x100 BAR2 256K BASE _ADDR_2 0x200 BAR3 256K BASE ADDR_3 0x300 Revision 0 00 Pa
5. compliant Jumpers not required for configuration or board detection PC 104 Bus Interface PC 104 Host system interface 8 and 16 bit I O and Memory data transfer PCI burst writes fully supported Automatic separation of 32bit PCI data into separate 8 16 bit PC 104 bus transactions 4 Interrupt modes including PCI driven interrupt structure with Interrupt enable disable and status registers On board EEPROM interface for loading of default or custom configuration on system start up reset DMA operations are not supported Digital I O optional Channels 16 bit bidirectional I O Input Output Ranges Hardware selectable 3 3V or 5V TTL CMOS Output Drive High Current 24mA Controller FPGA Register Controlled Device No jumpers needed Custom logic available upon request Operating 40 to 85 Degrees Celsius ae 3 775 x 3 550 PC 104 Compliant e PCI PCI 104 e ISA PC 104 Software e Device can be controlled directly from a memory and I O mapped register set in any Compatibility operating system Warranty and e Lifetime Warranty Support e Free Technical Support Revision 0 00 Page 7 of 19 Date June 22 2012 CL Connect Tech Inc PCI Device Information The PCI 104 to PC 104 Adapter has a PCI interface with 5 BAR s Base Address Registers with the following characteristics PCI 104 to PC 104 Adapter User s Manual BARU and BAR4 are Memory mapped BARI BAR2 and BAR3 are in PCI I O space Byte Word or Dw
6. write DWord 0x00000000 to offset 0x08 set all GPIO signals high write DWord Ox0O000FFFF to offset 0x08 GPIO Operation Pseudo Code Example B In this example we will set GPIOO 7 as inputs and GPIO8 15 as outputs then we will read the GPIO inputs setup GPIO directions write DWord 0x00000001 to offset 0x10 read GPIO signals status GPIO inputs read Word at offset 0x0C Revision 0 00 Page 19 of 19 Date June 22 2012
7. 0x10 0x00008000 LED off GPIO 1 16 output interrupt mode 00 TX FIFO 512 ISA 10 BASE 1 0x100 ISA IO BASE 2 0x200 ISA IO BASE 3 0x300 Revision 0 00 Page 11 of 19 Date June 22 2012 PCI 104 to PC 104 Adapter User s Manual CL Connect Tech Inc Device Registers BARU Command Control Status Registers These registers provide the complete control and operation of the Adapter All registers are accessed as Dwords 32 bits only Address Offset Hex e interrupt IRQ Enable Disable Register Seat Register Description Register Name ISR IER ISA IO BASE 3 BAR3 I O Base Address Register R W Read or Write unused bits are ignored on write and return zero s on read RO Read only unused bits return zero s BARU Detailed View en E 0 29 28 a7 25 EE EE EE E EE EE aa TS TS T TSTS Ta s 2 1 0 oxo4 ER D a oea EE TTT TTT aa TS TS T TSTS Ta TSTST mos RE a T em om BREET s T TS TS T TR TS T T 2 TSTS Ta T 5 T 3 T T sr GPIO INPUT GPIO A RENE EE EE EE EE EE EE 5 TS TS T TR TS TS T 3 TSTS T x10 wer cun a 90 29 28 27 asa aT s Ta TSTS T o e e a e TS a 0x14 BASE ADDR 0 BARE ADDR 0 0x18 BASE_ADDR_1 rafe BASE_ADDR 3 Revision 0 00 st E T 20 28 27 26 25 24 25 22 e a5 a 13 ajajaj 9 x x xix x x x x x BASE_ADDR_1 ea E K 28 27 26 25 24 28 22 er EE EE a5 i a ajajaj 9 x x x x x x x x x EE 28 27 26 25 24 23
8. Created Revision 0 00 Page 4 of 19 Date June 22 2012 CL Connect Tech Inc PCI 104 to PC 104 Adapter User s Manual Customer Support Overview If you experience difficulties after reading the manual and or using the product contact the Connect Tech Inc reseller from which you purchased the product In most cases the reseller can help you with product installation and difficulties In the event that the reseller is unable to resolve your problem our highly qualified support staff can assist you Our support section is available 24 hours a day 7 days a week on our website at www connecitech com sub support support asp See the contact information section below for more information on how to contact us directly Our technical support is always free Contact Information We offer three ways for you to contact us Mail Courier You may contact us by letter at Connect Tech Inc Technical Support 42 Arrow Road Guelph ON Canada NIK 1S6 Email Internet You may contact us through the Internet Our email and URL addresses on the Internet are sales connecttech com support connecttech com www connecttech com Ri G www facebook com connecttechinc www twitter com connecttechinc Note Please go to the Download Zone or the Knowledge Database in the Support Center on the Connect Tech Inc website for product manuals installation guides device driver software and technical tips Submit your technical support questions
9. afe shipment Connect Tech Inc will return this product by prepaid ground shipment service The Connect Tech Inc lifetime warranty is defined as the serviceable life of the product This is defined as the period during which all components are available Should the product prove to be irreparable Connect Tech Inc reserves the right to substitute an equivalent product if available or to retract lifetime warranty if no replacement is available The above warranty is the only warranty authorized by Connect Tech Inc Under no circumstances will Connect Tech Inc be liable in any way for any damages including any lost profits lost savings or other incidental or consequential damages arising out of the use of or inability to use such product Copyright Notice The information contained in this document is subject to change without notice Connect Tech Inc shall not be liable for errors contained herein or for incidental consequential damages in connection with the furnishing performance or use of this material This document contains proprietary information that is protected by copyright All rights are reserved No part of this document may be photocopied reproduced or translated to another language without the prior written consent of Connect Tech Inc Copyright 2012 by Connect Tech Inc Trademark Acknowledgment Connect Tech Inc acknowledges all trademarks registered trademarks and or copyrights referred to in this document as the
10. cts to the PCI 104 bus a full listing of the pinout of the connector is found in the table below Pn O OA O O OB CTD LI QND LI Reseved LJ Am 2 w a2 T Ly AD04 AD03 G AD06 G JI ADO AD08 AD10 G ADIS Reserved G G hm Q E M66EN AD12 3 3V U PERR 3 3V GND PERR STOP LOCK 2 TRDY 13 FRAME GD IRDY Reserved Q Z J DEVSEL 3 3V C BE2 ADI8 AD17 Q Ca J Q AD19 3 3V IDSEL2 IDSEL3 ND ND ND AD20 AD23 AD22 IDSELO IDSELI AN ND 5V G C BE3 VU 20 GND EECH AD25 AD28 Q Z J J ren ren v AD27 AD31 U GNTO ii AD30 pSV ADU 4 CIKO _ U t REQI Un G 5 GNT2 a as CLKO G Weem CLK3 5V INTB 0 GNT3 2 lt Die CLK Q Z J D05 GND GND ADI6 3 3V GND 5V 5V ND d dck RST INTC GND dt ug Revision 0 00 Page 16 of 19 Date June 22 2012 CL C onnect Tech Inc PCI 104 to PC 104 Adapter User s Manual PCI 104 Stack Position Selection The following PCI signals INTA INTB INTC INTD CLKO CLK1 CLK2 CLK3 IDSELO IDSEL1 IDSEL2 IDSEL3 are selected by using the rotary switch or jumper block optionally installed on the PCI 104 to PC 104 Adapter board J1 RSW1 Selections need to match the stack location of the PCI 104 to PC 104 Adapter in your PCI 104 stack See the table below for more details Rotary Stack Locat
11. ge 18 of 19 Date June 22 2012 CTs C onnect Tech Inc PCI 104 to PC 104 Adapter User s Manual GPIO Voltage Selection Jumper J2 GPIO Operation The GPIO operation on the Xtreme I O ADC DAC is directly controlled via 3 registers GPIO_OUT GPIO_IN and GPIO MISC_CMD The register GPIO_OUT at offset OxOC will set the state of any GPIO pins that are set to outputs The register GPIO_IN at offset 0x10 will contain the current state of any the GPIO pins that are set to inputs Any pins that are set to outputs will read a zero value The input output directions of the GPIO bits are controlled via the GPIO MISC_CMD register at offset 0x14 GPIO OUTPUT Register offset 0x08 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o GPIO INPUT Register offset 0x0C Reserved GPIO INPUT LE DEENEN GIO INPUT S 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Note Each bit corresponds to the GPIO signal on the connector IE bit O GPIOO and bit 9 GPIO9 GPIO MISC_CMD Register offset 0x10 0x10 GPIO_DIR up Ou E GE GPIOO 7 or GPIO8 15 0 OUTPUTS GPIOO 7 or GPIO8 15 1 INPUTS GPIO Operation Pseudo Code Example A In this example we will set all the GPIO to outputs and the switch all GPIO signals from low to high setup GPIO directions write DWord 0x00000000 to offset 0x10 set all GPIO signals low
12. ge 9 of 19 Date June 22 2012 CL Connect Tech Inc PCI 104 to PC 104 Adapter User s Manual PC 104 Transactions IO Reads Writes PCI Base Address Registers BARs 1 2 and 3 each map to a configurable 256 byte address space Reads and writes to this offset are translated into PC 104 ISA transactions at the BASE ADDR_1 BASE _ADDR_2 and BASE_ADDR_3 register values whose defaults are 0x100 0x200 and 0x300 The base address register is fully customizable and can be set in the range of OxOOXX to OxFFXX Note Any values in the lower register byte are ignored by the card and are therefore labelled as X Pseudo Code Example default settings Existing code that writes to ISA I O space outb 0x308 FF Will now be written to BAR3_ BASE ADDRESS IO_ADDR BASE_ADDR_3 In the case of BAR3_BASE_ ADDRESS being assigned I O space by the host system at 9C00 outb Ox9C08 FF Memory Reads Writes PCI Base Address Register 4 maps the entire 16M of ISA memory space 0x00 0000 OxFF FFFF Reads and writes to this BAR are translated into PC 104 ISA memory reads writes at the same corresponding address Pseudo Code Ex default settings Existing code that writes to ISA memory space mem_write OxABOO000 FF Will now be written to BARA BASE ADDRESS MEM_ADDR In the case of BAR3_BASE ADDRESS being assigned Memory mapped space by the host system at OxDB020000 mem_write OxDBADOO00 FF 16 bit ISA LO and Memory
13. ion Switch PCI INT PCI CLK PCI IDSEL Setting ADD ON 4 Dome eee INTA CLKO IDSELO _ ESNS INTB CLK IDSEL1 INTC CLK2 IDSEL2 LED Indicators The PCI 104 to PC 104 Adapter has 2 indicator LEDs as shown below LED D3 is the heartbeat indicator the LED should flash on and off continuously to indicate the PCI 104 to PC 104 Adapter is operating properly LED D2 is intended for user configuration and testing and it is directly mapped to MISC_CMD register offset 0x10 Bit 15 D3 PCI 104 to PC 104 Adapter Heartbeat D2 User LED Mapped to MISC CMD REG Bit 15 If LED D3 is not flashing at all times when the PCI 104 to PC 104 Adapter is powered up please contact Connect Tech Technical Support support connecttech com Revision 0 00 Page 17 of 19 Date June 22 2012 CTs Connect Tech Inc PCI 104 to PC 104 Adapter User s Manual GPIO Digital I O Optional build Overview The PCI 104 to PC 104 Adapter has an optionally populated 16 bits of bi directional GPIO that can be configured to operate with 3 3V or 5V logic levels The upper and lower 8 bytes GPIOO GPIO7 lower GPIO8 GPIO15 upper can be set to either inputs or outputs independently GPIO Connector P3 Pinout Pinout Table Connector Location Pinout Diagram Left Side View of Board PC 7104 25 4 PCl 104 Top TE KA Top J3 B Connector Connector P A 24 E PCI 104 Bottom Connector Revision 0 00 Pa
14. ire ISA memory address range 0x00 0000 0xFF FFFF An on board EEPROM is used to store these settings loading them at system start up Theory of Operation The PCI 104 to PC 104 Adapter uses 4 PCI Base Address Registers BARs to translate PCI transactions onto the PC 104 bus architecture Three of these BARs are used for PC 104 I O operations and one is used for PC 104 memory access e In order to comply with the PCI I O space BAR size requirements PCI I O accesses are translated to ISA I O accesses using one of three 256 byte 8 wide address windows located in three separate BARs Any PCI Read Write operations executed to these BARs are translated by the PCI 104 to PC 104 Adapter to PC 104 Read Write Operations at the BARs specific I O Address Offset Starting offsets of these address windows can be configured via the adapters configuration register set e PCI Memory accesses are translated to ISA memory accesses using a 16Mb 24 wide memory mapped window The entire ISA memory space is mapped into the PCI memory space Serial IO BARI Configuration OxXX00 Registers OxXXFF IO BAR 0xXX00 Interrupt OxXXFF Enable Status Source IO BAR3 Registers OxXX00 Ox XX FF MEMORY 0x00 0000 OxFF FFFF GPIO Registers GPIO Header optional Revision 0 00 Page 6 of 19 Date June 22 2012 CL Connect Tech Inc PCI 104 to PC 104 Adapter User s Manual Product Features Form Factor PCI 104 Fully PCI 2 0 bus
15. n then be read to indicate which interrupt is active and needs servicing Writing a 1 back to the active bit in the status register will clear the interrupt Note PC 104 IRQ signals are edge triggered to avoid stuck IRQ signals the status register bit will only be cleared if a 1 is written and the IRQ is no longer active logic high e 01 IRQ interrupt direct pass through PCI interrupt clears once enabled IRQ is cleared In this mode the detection of an enabled IRQ interrupt will still trigger the PCI interrupt with the ISR indicating which IRQ line is generating the interrupt However once the interrupt is serviced and the IRQ becomes inactive the PCI interrupt is cleared without writing back to the ISR e 10 Reserved This setting is reserved for future interrupt implementations do not use e 11 Interrupts disabled In this mode all PC 104 interrupts are ignored The IER is ignored and ISR does not update upon detection of any IRQ interrupts Revision 0 00 Page 13 of 19 Date June 22 2012 CTs Connect Tech Inc PCI 104 to PC 104 Adapter User s Manual EEPROM Interface Registers wos VEER GPIO OUTPUT son om io 29 2827 25 25 24 23 22 21 20 a9 a8 a7 a6 5 24 13 22 2 20 9 e 7 6 5 4 312 210 eerser GPIO_IN 0 29 28 27 26 25 24 23 22 21 20 19 48 47 26 15 14 13 12 11 10 9 8 7 6 5 4 3 2 2 0 Offset 0x08 31 EEPROM Write Start
16. nternal TX FIFO which can be set to use a 128 or 512 trigger Bit 4 of the MISC CMD register BARO offset 0x10 can be used to change this setting from its default set to 0 512 Changing to the 128 Dword trigger will reduce throughput but decrease the worst case PC 104 read wait time In most cases it is best to leave this set to 0 15 User LED LED This bit controls the User LED See the LED Indicators section for location and other info Revision 0 00 Page 14 of 19 Date June 22 2012 CTs Connect Tech Inc PCI 104 to PC 104 Adapter User s Manual PC 104 I O Base Address Registers BARO offset 0x14 0x18 0x1C 0x14 ee T BASE_ADDR_0 Coa eeaeee ce 0x18 BASE ADD EE EE EE EE EE EE EE s TS TSTST S LS exe xe Ox1C ee BASE ADR 2 SE EE EE EE ae s TSTS TS T TSTS TTS TSTS TSTS TSTST Offset 0x14 0x18 0x1C 15 0 Base Address Registers BASE_ADDR The value of the BASE ADDR registers is used to indicate the base address value that the PC 104 bus will perform read write operations Only the upper byte is used by the PCI 104 to PC 104 Adapter allowing a base address setting from 0x0000 0xFF00 enabling a 256 byte address range ex setting 0x0000 gives a range of 0x0000 0x00FF setting OxFFOO enables a range of OxFFOO OxFFFF PCI 104 Information Revision 0 00 Page 15 of 19 Date June 22 2012 CL Connect Tech Inc PCI 104 to PC 104 Adapter User s Manual PCI 104 Connector Pinout P6 Connector P6 is conne
17. ord accesses unless indicated otherwise in the details below PCI Bars Bar Number Sie bytes em Configuration registers used to modify and retrieve configuration info for PC 104 and EEPROM interfaces GPIO configuration and data is also in the BARO register bank Accessed as Dwords only Register configuration below Elon CLUE 3 three EE 4 four MEM_BAR mapped directly to ISA Memory Address space PCI Device Information The PCI 104 to PC 104 Adapter will have the following properties in a PCI system iD Tae Comments OOOO 0x1400 The ID for this board assembly Sub Class Other bridge device interface ooo o O Below is the output from the lspci utility in Linux with a PCI 104 to PC 104 Adapter installed in the system 02 00 0 Bridge 0680 Connect Tech Inc Device 12c4 1400 rev 41 Subsystem Connect Tech Inc Device 12c4 0000 Control I O Mem BusMaster SpecCycle MemWINV VGASnoop ParErr Stepping SERR FastB2B DisINTx Status Cap 66MHz UDF FastB2B ParErr DEVSEL slow gt TAbort lt TAbort lt MAbort gt SERR lt PERR INTx Interrupt pin A routed to IRQ 5 Region Region Region Region Region PCI Interrupt 0 1 2 3 4 Memory at I O ports I O ports I O ports Memory at feaf0000 32 bit non prefetchable size 64K at df00 size 256 at de00 size 256 at dd00 size 256 fd000000 32 bit non prefetchable size 16M The PCI 104 to
18. property of their respective owners Not listing all possible trademarks or copyright acknowledgments does not constitute a lack of acknowledgment to the rightful owners of the trademarks and copyrights mentioned in this document Revision 0 00 Page 2 of 19 Date June 22 2012 CTs Connect Tech Inc PCI 104 to PC 104 Adapter User s Manual Table of Contents EIRaMSE AEH LOESCH 2 67T eU yl elu 9 NOTCE sosiete aea EER O Aaaa EARRA Aaaa ANERER 2 Trademark Acknowl dgmi siiip eaa a aa NEEE aR 2 Taler C ONEN E 3 REVISTO TIS TONN EE 4 Customer Support Overview sssssssssssrnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn ennenen ennenen 5 Contact IMO MaG so a a areee er re center Are eerste 5 Jee Te de 1 oean E E E entre etre eres ret 6 Theory Of ele OCH Le 6 Produc 9 PO TI D PCI Device M Le yut EE 8 SEN 8 PGI Device elt e ss scccasvscvzccssccaessasscntssoscanedacoadeacdcsnaxeod seeandscaganne Caused a Saanecceoansedesgaupecencensedsbeidocomdaaoemendes 8 Region 4 Memory at fd000000 32 bit non prefetchable size 16M 8 Seite EE 8 PC 104 ISA Host LC TE 9 PC 104 ISA I O and Memory Window Configuration Default Starting COftsetsl eee 9 PO IOn Re Eer 10 O RSS TIE 10 Kaino y Reda SINOS EE 10 16 bit ISA UO and Memory reads writes PCI Burst Wrtes see 10 EEPROM Et 11 Writing Custom Configuration Settings to the Serial EEPROM sse eee 11 PCI 104 to PC 104 Adapter Default Gettmgs sse eee 11 DVICE UE 12 BARO Command Con
19. reads writes PCI Burst Writes If the PC 104 device supports 16bit communications and there is sufficient data available then the PCI 104 to PC 104 Adapter will perform a 16bit operation The adapter automatically determines if the device can support 16 bit transfers no user input is necessary to implement this feature PCI burst writes are also fully supported by the adapter and are split into the necessary number of PC 104 bus transfers automatically Revision 0 00 Page 10 of 19 Date June 22 2012 CL Connect Tech Inc PCI 104 to PC 104 Adapter User s Manual EEPROM Interface Writing Custom Configuration Settings to the Serial EEPROM The PCI 104 to PC 104 Adapter uses an on board serial EEPROM to load its configuration at boot system reset Writing to the EEPROM write bit at any time will write the current values of the configuration registers into the EEPROM An EEPROM write complete bit as well as a rapidly blinking LED indicates a successful write The PCI 104 to PC 104 Adapter is pre loaded with default setting to cover the most commonly used PC 104 I O ranges Ox100 Ox1 FF 0x200 Ox2FF 0x300 0x3FF but can be customized to cover any 256 byte range For register description see the EEPROM Register section of the manual The PCI 104 to PC 104 Adapter s default register settings are below PCI 104 to PC 104 Adapter Default Settings Register Nane Name Address Offset Default Value a ENABLE 0x04 0x00000000 all disabled MISC_CMD
20. to our customer support engineers via the Support Center on the Connect Tech Inc website Telephone Facsimile Technical Support representatives are ready to answer your call Monday through Friday from 8 30 a m to 5 00 p m Eastern Standard Time Our numbers for calls are Telephone 800 426 8979 North America only Telephone 519 836 1291 Live assistance available 8 30 a m to 5 00 p m EST Monday to Friday Facsimile 519 836 4878 online 24 hours Revision 0 00 Page 5 of 19 Date June 22 2012 CTs Connect Tech Inc PCI 104 to PC 104 Adapter User s Manual Introduction The Connect Tech PCI 104 to PC 104 Adapter enables testing and development of a PC 104 ISA peripheral card in a PCI 104 PCI host environment allowing PCI 104 only systems SBCs to include PC 104 bus peripherals in their system Direct mapping from PCI 104 to PC 104 space allows existing PC 104 code to be moved to the PCI space with minimal code changes The PCI 104 to PC 104 Adapter maps PCI reads writes to ISA I O and Memory address space supporting 8 16 and 32 bit reads writes as well as PCI burst writes A PCI driven interrupt controller allows for the enabling and disabling of all 11 PC 104 IRQ lines transmitting detected IRQ interrupts as a single PCI interrupt with status register A fully customizable range of I O addresses translates 8 16 32bit PCI I O space reads writes to 8 16bit ISA I O reads writes Another PCI memory mapped register covers the ent
21. trol Status Registers sss eee eee eee 12 BARO Detaled ET 12 LEEFER sI 13 Offset 0x00 10 0 Interrupt Enable Register ER 13 Offset 0x04 10 0 Interrupt Status Register ISH eee 13 LEAT Generat E 13 EEPROM Interface Registers sse eee 14 Offset 0x08 31 EEPROM Write Start EER Wi 14 Offset 0x0C 31 EEPROM Write Complete EEP_RST sse 14 Miscellaneous Command Configuration Register MISC CM 14 1 0 GPIO Direction Register GPIO_ DIRI sss 14 3 2 Interrupt Mode Register INT NODE 14 4 Transmit FIFO trigger Setting TX ElkO 14 fo RE a E CAR RE 14 PC 104 I O Base Address Registers BARO offset 0x14 0xX18 Di 15 Offset 0x14 0x18 0x1C 15 0 Base Address Registers BASE _ADDR ee 15 SE 9 COMMECION PIQUE s E 16 PCI 104 Stack Position Selection cccceeeseeeseeeeeeeenseeeeeeeanseeeeeeeaaseeeseoeaaseeeseoeasseeesooaaseeessooanneees 17 LED CG OS EN 17 Revision 0 00 Page 3 of 19 Date June 22 2012 CTs Connect Tech Inc PCI 104 to PC 104 Adapter User s Manual GPIO Digital I O Optional build ccceesneseeececenaseeececcnaseeececonasseececonasseenecenassescecnnassessess 18 DEA E EEE IEA EAE A AAE I eege 18 GPIO Connector P3 PINOUT EE 18 PINOUT T E 18 Pinout Diagram Left Side View of Board 18 VO CANO I EE 19 Revision History Revision Date Author s Changes om June 22 2012 Rob Callaghan Initial Manual Revision
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