Home

LPC185x/3x/2x/1x - NXP Semiconductors

image

Contents

1. Pin name 2 Description j t8 8 x e S eels PE 15 E13 21 N R Function reserved PU CTOUT 0 SCTimer PWM output 0 Match output 0 of timer 0 I2C1 SCL I C1 clock input output this pin does not use a specialized 1 C pad SDRAM clock enable GPIO7 15 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PF 0 D12 159 21 OL I O SSPO SCK Serial clock for SSPO PU GP_CLKIN General purpose clock input to the CGU R Function reserved R Function reserved R Function reserved R Function reserved R Function reserved 2S1 TX MCLK 1251 transmit master clock PF 1 11 I N R Function reserved PU R Function reserved lO SSPO SSEL Slave Select for SSPO R Function reserved GPIO7 16 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PF 2 Dii 168 BI N Function reserved PU TXD Transmitter output for USART3 lO SSPO MISO Master In Slave Out for SSPO R Function reserved GPIO7 17 General purpose digital input output pin R Function reserved R Function reserv
2. Pin name 2 Description A o e le Ig E 3 amp 5 3 LS P6 3 P15 79 113 l O GPIO3 2 General purpose digital input output pin PU o USBO PPWR VBUS drive signal towards external charge pump or power management unit indicates that VBUS must be driven active HIGH Add a pull down resistor to disable the power switch at reset This signal has opposite polarity compared to the USB PPWR used on other NXP LPC parts R Function reserved CS1 LOW active Chip Select 1 signal R Function reserved T2_CAP2 Capture input 2 of timer 2 R Function reserved R Function reserved P6 4 R16 F6 80 1114 21 IN l O GPIOS 3 General purpose digital input output pin PU CTIN 6 SCTimer PWM input 6 Capture input 1 of timer 3 U0_TXD Transmitter output for USARTO CAS LOW active SDRAM Column Address Strobe R Function reserved R Function reserved R Function reserved R Function reserved P6 5 P16 F9 82 117 21 N GPIO3 4 General purpose digital input output pin PU CTOUT 6 SCTimer PWM output 6 Match output 2 of timer 1 UO RXD Receiver input for USARTO LOW active SDRAM Row Address Strobe R Function reserved R Function reserved R Function reserved R Functio
3. 0 16 32 48 64 80 96 0 20 40 60 80 100 120 mA mA Conditions VDD REG 3V3 Vpp 0 3 3 V high drive Conditions VpD REG 3V3 3 3 V ultra EHD 0 2 high drive EHD 0x3 Fig 22 High drive pins typical HIGH level output voltage Voy versus HGH level output current LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 101 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 20 002aah422 Ipu pA 0 105 25 40 20 40 60 80 0 1 2 3 VI V Conditions Vpp o 3 3 V Simulated data over process and temperature Fig 23 Pull up current ly versus input voltage Vi 120 002aah418 pA 40 C 90 25 105 60 30 0 0 1 2 3 V Conditions Vppiio 3 3 V Simulated data over process and temperature Fig 24 Pull down current ly versus input voltage V LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 AII rights reserved Product data sheet Rev 5 1 17 November 2015 102 of 155 NXP Semico
4. Table 11 Static characteristics continued Tamb 40 C to 105 unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit lDD 10 I O supply current deep sleep mode lt 0 1 power down mode 0 1 deep power down mode lt 0 1 IDDA Analog supply current pin VDDA 9 0 4 deep sleep mode pA power down mode 9 0 4 pA deep power down 9 0 007 mode uA RESET pin Vin HIGH level input 8 0 8x Vps 5 5 V voltage 0 35 ViL LOW level input voltage 8 0 0 3 Vps V 0 1 Vhys hysteresis voltage 8 10 05 x Vps V 0 35 Standard I O pins normal drive strength Ci input capacitance 2 pF lu LOW level leakage Vi 0 V on chip pull up 3 nA current resistor disabled ILH HIGH level leakage Vi on chip 3 nA current pull down resistor disabled Vi 5 V Tamb 25 C 0 5 nA V 5 V Tamb 105 C 40 nA loz OFF state output Vo 0V to 3 nA current on chip pull up down resistors disabled absolute value Vi input voltage pin configured to provide 0 5 5 V a digital function gt 24 20V 0 P 3 6 V Vo output voltage output active 0 Vpb o V Vin HIGH level input 0 7 x 5 5 V voltage LOW level input voltage 0 0 3 x V Vpp 0 Vhys hysteresis voltage 0 1 x V Vpp 0 Vou HIGH level output lon 6 mA Vpp lo V voltage 0 4 VoL LOW
5. 0 0 1 0 2 0 3 0 4 0 5 0 6 VoL V Conditions VDD REG 3V3 Vpp 0 3 3 V high drive EHD 0 2 Fig 21 High drive pins typical LOW level output current lo versus LOW level output voltage VoL 002aah361 m m 40 25 ia 85 C 105 C 15 10 5 0 01 02 04 05 06 V Conditions VpD REG 3V3 Vpp lo 3 3 V medium drive EHD 0 1 002aah363 lo 60 40 C 25 C mA 85 45 105 30 15 0 0 0 1 0 2 0 3 0 4 0 5 0 6 VoL V Conditions Vpp REG 3v3 Vpp o 3 3 V ultra high drive EHD 0x3 LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 100 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 36 002aah364 36 002aah367 V 32 40 C 25 C 85 C 105 C 2 8 24 2 0 4 8 12 16 20 24 0 8 16 24 32 40 48 loH mA mA Conditions Vpp REG 3V3 3 3 V normal drive Conditions VDD REG 3V3 Vpp o 3 3 V EHD 0 0 medium drive EHD 0 1 002aah368 36 002aah369
6. 132 RIC oscillator nex ero 134 XTAL and RTCX Printed Circuit Board PCB layout guidelines 134 Standard I O pin configuration 134 Reset pin configuration 135 Suggested USB interface solutions 135 Package outline 138 Soldering 142 AbbreviationS 146 References ls kn onn ukuras 147 Revision 148 Legal 152 Data sheet status 152 5 152 152 Trademarks 153 Contact information 153 21 32 bit ARM Cortex M3 microcontroller CONTENIS dew umque na oe 154 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2015 All rights reserved For more information please visit http Awww nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 17 November 2015 Document identifier LPC185X_3X_2X_1X
7. 1 Clock to the I2S bus interface BASE APB1 CLK 150 MHz peripheral clock to the I2S bus interface PCLK BASE APB1 CLK 12 125 clock cycle time Tey cik 79 2 ns corresponds to the SCK signal in the S bus specification LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 109 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 12Sx_TX_SCK twH tw 125 TX SDA tva 12Sx_TX_WS lt twa Fig 27 S bus timing transmit Toy clk tf 002aag497 12S5x_RX_SCK twH 12 _ _5 0 tsu D gt th D Y 129 RX WS tsu D tsu D Fig 28 125 timing receive Toy clk gt tf je 002aag498 11 11 USART interface LPC185X 3X 2X 1X Table 26 USART dynamic characteristics Tamp 40 to 105 C 2 4 V lt Vpp REG 3V3 lt 3 6 V 2 7 V lt VppvI0 3 6 V 20 pF EHS 1 for all pins Simulated values Symbol Parameter Min Max Unit USART master in synchronous mode tsu D data input set up time 26 6 ns th D data input hold time 0 ns twa data output valid time 0 10 4 ns USART slave in synchronous mode tsu D data input set up time 2 4 ns th D data input hol
8. 61 Nested Vectored Interrupt Controller NVIC 61 Features iu asc e Ry 61 Interrupt 62 Event router 62 Global Input Multiplexer Array GIMA 62 Features usu au eub aly RUE RE enn 62 On chip static 62 On chip flash memory 63 EEPROM s ihi du eee ore See aa lt a 63 Boot ROM ELA 63 Memory mapping 65 One Time Programmable OTP memory 67 General Purpose I O GPIO 67 Fates oi RP dae be 67 AHB 67 State Configurable Timer PWM SCTimer PWM 67 lt 68 General Purpose 68 Eeat res i io mco se eben 68 SPI Flash Interface SPIFI 69 Features sie Ra 69 SD MMC card interface 70 External Memory Controller EMC 70 Feat res dene eet 70 High speed USB Host Device OTG interface USBO ces ur eet de eee he eek 71 FeatUle5 i sare cR wie sudden suds ae aa Ae na 71 High speed USB Host Device interface with ULPI 1 72 FOatures aou coed s Oy a Be 72 LCD 72 Feat les coss dinidan na nin anae 72 7
9. All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 98 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 10 3 Electrical pin characteristics 002aah358 002aah359 M 15 ET 3 6 25 C m d 85 105 9 6 3 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 6 12 18 24 30 36 V mA Conditions Vpp REG 3V3 Vpp Io 3 3 Conditions Vpp REG 3V3 Vpp o 3 3 V Fig 19 Standard I O pins typical LOW level output Fig 20 Standard I O pins typical HIGH level output current Io versus LOW level output voltage voltage Vo versus HIGH level output current VoL LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 AII rights reserved Product data sheet Rev 5 1 17 November 2015 99 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 002aah360 lor 19 40 425 C mA 12 85 105 9 6 3 0 0 0 1 0 2 0 3 0 4 0 5 0 6 VoL V Conditions Vpp REG 3V3 3 3 V normal drive EHD 0x0 2aah362 40 002aah36
10. eis bn eine ede ot Goa 78 Windowed WatchDog Timer WWDT 78 78 Analog 79 Analog to Digital Converter 79 79 Digital to Analog Converter DAC 79 79 Peripherals in the RTC power domain 79 RIC ss tarto karie eas ee aA a 79 se 79 Event monitor recorder 80 Features ewe ewe RR 80 Alarm 80 System 80 Configuration registers CREG 80 System Control Unit SCU 81 Clock Generation Unit CGU 81 Internal RC oscillator IRC 81 PLLOUSB for 81 PLLOAUDIO for audio 81 System PLET 82 Reset Generation Unit RGU 82 Power 82 Code security Code Read Protection CRP 83 continued gt gt NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 154 of 155 NXP Semiconductors LPC185x 3x 2x 1x 7 21 8 9 10 10 1 10 2 10 3 10 4 11 11 1 11 2 11 3 11 4 11 5 11 6 11 7 11 8 11 9 11 10 11 11 11 12 11 13 11 14 11 15 11 16 11 17 11 18
11. TE LPC185x 3x 2x 1x Bus 32 bit ARM Cortex M3 MCU up to 1 MB flash and 136 kB SRAM Ethernet two High speed USB LCD EMC Rev 5 1 17 November 2015 Product data sheet 1 General description The LPC185x 3x 2x 1x are ARM Cortex M3 based microcontrollers for embedded applications The ARM Cortex M3 is a next generation core that offers system enhancements such as low power consumption enhanced debug features and a high level of support block integration The LPC185x 3x 2x 1x operate at CPU frequencies of up to 180 MHz The ARM Cortex M3 CPU incorporates a 3 stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals The ARM Cortex M3 CPU also includes an internal prefetch unit that supports speculative branching The LPC185x 3x 2x 1x include up to 1 MB of flash 136 kB of on chip SRAM 16 kB of EEPROM memory a quad SPI Flash Interface SPIFI a State configurable Timer PWM SCTimer PWM subsystem two High speed USB controllers Ethernet LCD an external memory controller and multiple digital and analog peripherals For additional documentation related to the LPC18xx parts see Section 17 References 2 Features and benefits Processor core ARM Cortex M3 processor version r2p1 running at CPU frequencies of up to 180 MHz ARM Cortex M3 built in Memory Protection Unit MPU supporting eight reg
12. 20V 0 3 6 V Vo output voltage output active 0 V Vin HIGH level input 0 7 x 5 5 V voltage LOW level input voltage 0 0 3 x V Vpb o Vhys hysteresis voltage 0 1 x V Vpb o loa pull down current Vi 12 62 uA 13 14 lou pull up current Vi 0V 12 62 pA 13 14 VpD O lt V lt 5V 10 LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 89 of 155 LPC185x 3x 2x 1x NXP Semiconductors 32 bit ARM Cortex M3 microcontroller Table 11 Static characteristics continued Tamb 40 C to 105 unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit I O pins high drive strength standard drive mode ILH HIGH level leakage Vi on chip 3 nA current pull down resistor disabled Vi 5 Vi Tamb 25 C 0 6 nA Vi 5 Vi Tamb 105 C 65 nA lou HIGH level output Vou 0 4 V 4 mA current lo LOW level output Voi 0 4 V 4 mA current lous HIGH level short circuit drive HIGH connected to 10 32 mA output current ground lots LOW level short circuit drive LOW connected to 10 32 mA output current VpD o I O pins high drive strength medi
13. GPIO1 10 General purpose digital input output pin PU External boot pin see Table 5 CTOUT 3 SCTimer PWM output Match output of timer 0 BAUD Baud pin for USARTS 0 External memory address line 0 R Function reserved R Function reserved R Function reserved R Function reserved P2 10 G16 E8 104 146 BI IN GPIOO 14 General purpose digital input output pin PU CTOUT 2 SCTimer PWM output 2 Match output 2 of timer 0 102 TXD Transmitter output for USART2 A1 External memory address line 1 R Function reserved R Function reserved R Function reserved R Function reserved P2 11 F16 9 105 148 BI IN GPIO1 11 General purpose digital input output pin PU O CTOUT 5 SCTimer PWM output 5 Match output of timer 3 U2_RXD Receiver input for USART2 A2 External memory address line 2 R Function reserved R Function reserved R Function reserved R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 17 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3
14. SSPO MISO Master In Slave Out for SSPO l O SPIFI MOSI Input 0 in SPIFI quad mode SPIFI output IOO GPIO5 10 General purpose digital input output pin SSPO MOSI Master Out Slave in for SSPO R Function reserved R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 20 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name 2 Description 3 8 5 ESSI P3 8 C10 E7 124 179 B N l R Function reserved PU R Function reserved SSPO MOSI Master Out Slave in for SSPO SPIFI CS SPIFI serial flash chip select GPIO5 11 General purpose digital input output pin lO SSPO SSEL Slave Select for SSPO R Function reserved R Function reserved P4 0 D5 l 1 1 fl N GPIO2 0 General purpose digital input output PU MCOA0 Motor control PWM channel 0 output A NMI External interrupt input to NMI R Function reserved R Function reserved O LCD_VD13 LCD data VO Serial clock input output for USARTS in
15. description continued 32 bit ARM Cortex M3 microcontroller Pin name LQFP144 LQFP208 Reset state 1 Type Description LBGA256 W TFBGA100 wo P2 12 2 0 2 c GPIO1 12 General purpose digital input output pin CTOUT 4 SCTimer PWM output 4 Match output 3 of timer 3 R Function reserved External memory address line 3 R Function reserved R Function reserved R Function reserved U2 UCLK Serial clock input output for USART2 in synchronous mode P2 13 C16 10 108 156 PU GPIO1 13 General purpose digital input output pin CTIN 4 SCTimer PWM input 4 Capture input 2 of timer 1 R Function reserved EMC A4 External memory address line 4 R Function reserved R Function reserved R Function reserved 1 0 U2 DIR RS 485 EIA 485 output enable direction control for USART2 P3_0 F13 8 112 161 PU 1 0 12S0_RX_SCK 125 receive clock It is driven by the master and received by the slave Corresponds to the signal SCK in the S bus specification 12S0_RX_MCLK 125 receive master clock 1 0 12S0_TX_SCK Transmit Clock It is driven by the master and received by the slave Corresponds to the signal SCK in the S bus specification 12S0_TX_MCLK 125 tr
16. GPIOO 7 General purpose digital input output pin ISP entry pin If this pin is pulled LOW at reset the part enters ISP mode or boots from an external source see Table 4 and Table 5 CTOUT 1 SCTimer PWM output 1 Match output 3 of timer 3 1 0 U3_UCLK Serial clock input output for USART3 in synchronous mode 9 External memory address line 9 Function reserved Function reserved T8 MATS Match output 3 of timer R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 16 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Pin name 2 Description 9 g lt 3 amp a 3 lg SNE gt gt ene 2_8 J16 C6 98 140 2 R Function reserved External boot pin see Table 5 PU CTOUT 0 SCTimer PWM output 0 Match output 0 of timer 0 DIR RS 485 EIA 485 output enable direction control for USART3 A8 External memory address line 8 GPIOS 7 General purpose digital input output pin R Function reserved R Function reserved R Function reserved P2 9 H16 B10 102 144 2 IN
17. General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE 10 E14 154 121 N R Function reserved PU CTIN 3 SCTimer PWM input Capture input 1 of timer 1 U1_DTR Data Terminal Ready output for UART1 Can also be configured to be an RS 485 EIA 485 output enable signal for UART1 D29 External memory data line 29 l O GPIO7 10 General purpose digital input output pin R Function reserved R Function reserved R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 49 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Pin name Description Reset state 1 TFBGA100 LQFP144 LQFP208 Type LBGA256 1 1 1 2 Function reserved CTOUT_12 SCTimer PWM output 12 Match output 3 of timer 3 U1_TXD Transmitter output for UART1 030 External memory data line 30 GPIO7 11 General purpose digital input output pin PE 11 0 2 c Ol R Function reserved R Function reserved R Function reserved PE_12 D15 21 N l R Function reserved PU O CTOUT 11 SCTime
18. Capture input 2 of timer 0 P8_7 K1 5 45 PU GPIO4 7 General purpose digital input output pin USB1_ULPI_STP ULPI link STP signal Asserted to end or interrupt transfers to the PHY R Function reserved LCD_VD4 LCD data LCD_PWR LCD panel power enable R Function reserved R Function reserved TO_CAP3 Capture input 3 of timer 0 LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 33 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name 2 Description 38 5 ES Ie IS ee P8 8 L1 49 B N l R Function reserved PU USB1_ULPI_CLK ULP link CLK signal 60 MHz clock generated by the PHY R Function reserved R Function reserved R Function reserved R Function reserved O CGU OUTO CGU spare clock output 0 1251 TX MCLK 1251 transmit master clock P9 0 T1 59 N GPIO4 12 General purpose digital input output pin PU MCABORT Motor control PWM LOW active fast abort R Function reserved R
19. TRACEDATA O0 Trace data bit 0 GPIO7 19 General purpose digital input output pin Function reserved R Function reserved R Function reserved Al ADC1 4 ADC1 and ADCO input channel 4 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 52 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name TFBGA100 LQFP144 LQFP208 Reset state 1 Type Description I LBGA256 PF 6 1 1 5 0 2 Function reserved U3_DIR RS 485 EIA 485 output enable direction control for USARTS 1 0 SSP1_MISO Master In Slave Out for SSP1 TRACEDATA 1 Trace data bit 1 1 0 GPIO7 20 General purpose digital input output pin Function reserved R Function reserved 1 0 12S1_TX_SDA 1251 transmit data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification Al ADC1_3 ADC1 and ADCO input channel Configure the pin as GPIO input and use the ADC function select register
20. 68 mW Ippav3 analog supply current 3 3 V on pin USBO_VDDA3V3_DRIVER 8 total supply current 18 mA during transmit 31 mA during receive 14 mA with driver tri stated 14 mA Ippp digital supply current 7 mA Full speed low speed mode Peons power consumption 2 15 mW Ippa ava analog supply current 3 3 V on pin USBO_VDDA3V3_DRIVER total supply current 3 5 mA during transmit 5 mA during receive 3 mA with driver tri stated 3 mA Ippp digital supply current 3 mA Suspend mode Ippaava analog supply current 3 3 V 24 with driver tri stated 24 with functionality enabled 3 mA Ippp digital supply current 30 VBUS detector outputs Vin threshold voltage for VBUS valid 4 4 V for session end 0 2 0 8 V for A valid 0 8 2 V for B valid 2 4 V Vhys hysteresis voltage for session end 150 10 mV A valid 200 10 mV B valid 200 10 mV 1 Characterized but not implemented as production test 2 Total average power consumption 3 The driver is active only 20 of the time LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 123 of 155 NXP Semiconductors LPC185x 3x 2x 1x 11 15 Ethernet 32 bit ARM Cortex M3 microcontroller Table 33 Dynamic chara
21. Function reserved P6 1 R15 G5 74 107 Bl IN l O GPIOS 0 General purpose digital input output pin PU DYCS1 SDRAM chip select 1 Serial clock input output for USARTO in synchronous mode lO 1250 WS Receive Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the S bus specification R Function reserved T2_CAPO Capture input 2 of timer 2 R Function reserved R Function reserved P6 2 L13 J9 78 11 B l O GPIO3 1 General purpose digital input output pin PU CKEOUT1 SDRAM clock enable 1 DIR RS 485 EIA 485 output enable direction control for USARTO 1250 SDA 125 Receive data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification R Function reserved T2_CAP1 Capture input 1 of timer 2 R Function reserved R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 26 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller
22. Rev 5 1 17 November 2015 82 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller LPC18xx VDDIO to I O pads vss to core REGULATOR to memories VDDREG peripherals oscillators MAIN POWER DOMAIN to RTC domain I peripherals RESET WAKE UP RESET CONTROL WAKEUPO 1 2 3 BACKUP REGISTERS RTCX1 RTCX2 REAL TIME CLOCK ALARM ULTRA LOW POWER VBAT REGULATOR to RTC I O pads Vps VDDA VSSA VPP USBO_VDDA3V3_DRIVER USBO_VDDA3V3 002aag305 Fig 9 LPC185x 3x 2x 1x Power domains The LPC185x 3x 2x 1x support four reduced power modes Sleep Deep sleep Power down and Deep power down The LPC185x 3x 2x 1x can wake up from Deep sleep Power down and Deep power down modes via the WAKEUP 3 0 pins and interrupts generated by battery powered blocks in the RTC power domain 7 20 10 Code security Code Read Protection CRP CRP enables different levels of security so that access to the on chip flash and use of the JTAG and ISP can be restricted CRP is invoked by programming a specific pattern into a dedicated flash location IAP commands are not affected by CRP LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 83 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Ther
23. 7 20 7 20 1 LPC185X 3X 2X 1X 32 bit ARM Cortex M3 microcontroller Dedicated battery power supply pin RTC power supply is isolated from the rest of the chip Calibration counter allows adjustment to better than 1 sec day with 1 sec resolution Periodic interrupts can be generated from increments of any field of the time registers Alarm interrupt can be generated for a specific date time Event monitor recorder The event monitor recorder allows recording and creating a time stamp of events related to the WAKEUP pins Sensors report changes to the state of the WAKEUP pins and the event monitor recorder stores records of such events The event recorder can be powered by the backup battery The event monitor recorder can monitor the integrity of the device and record any tampering events Features Supports three digital event inputs in the VBAT power domain An event is defined as a level change at the digital event inputs For each event channel two timestamps mark the first and the last occurrence of an event Each channel also has a dedicated counter tracking the total number of events Timestamp values are taken from the RTC Runs in VBAT power domain independent of system power supply The event recorder monitor can therefore operate in Deep power down mode Low power consumption Interrupt available if system is running Aqualified event can be used as a wake up trigger State of event i
24. Fig 32 External static memory read write access PB z 0 LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 118 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller EMC_An tcsLAV tes toEHANV E E EMC_CSn 4 csLoEL 4 OE OELOEH lt tCSLBLSL tCSHOEH tCSLBLSL EMC_BLSn CSHBLSH tcsLwEL tWELWEH t EMC_WE tam gt BLSHDNV 4 CSHEOR t gt 4 5 CSLDV t CSLSOR h D WEHDNV EMC Dn SOR EOR EOW 002aag700 Fig 33 External static memory read write access PB z 1 LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 AII rights reserved Product data sheet Rev 5 1 17 November 2015 119 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 29 32 bit ARM Cortex M3 microcontroller Dynamic characteristics Dynamic external memory interface Simulated data over temperature and process range C 10 pF for EMC_DYCSn EMC RAS EMC CAS EMC WE An C 9 pF for Dn C 5 pF for DQMOUTn EMC_CLKn CKEOUTn Tamb 40 C to 105 C 24Vx Vpp REG 3V3 lt 3 6 V Vpp 0 3 3 V 10 RD 1 see LPC18xx User manual
25. Function reserved R Function reserved CRS Ethernet Carrier Sense MII interface R Function reserved SSPO SSEL Slave Select for SSPO 9_1 N6 66 l O GPIO4 13 General purpose digital input output pin PU 2 Motor control PWM channel 2 output A R Function reserved R Function reserved lO 12S0_TX_WS Transmit Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the S bus specification ENET_RX_ER Ethernet receive error MII interface R Function reserved SSPO MISO Master In Slave Out for SSPO P9 2 N8 70 121 GPIO4 14 General purpose digital input output pin PU MCOB2C Motor control PWM channel 2 output B R Function reserved R Function reserved 12S0_TX_SDA 125 transmit data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification ENET_RXD3 Ethernet receive data 3 MII interface R Function reserved lO SSPO MOSI Master Out Slave in for SSPO LPC185X_3X_2X_1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 34 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pi
26. Table 8 Thermal characteristics Symbol Parameter Min Typ Max Unit Titmax maximum junction 125 C temperature Table 9 Thermal resistance LQFP packages Symbol Parameter Conditions Thermal resistance in C W 15 LQFP144 LQFP208 thermal resistance 4 5 in x 4 in still 38 31 from junction to air ambient Single layer 4 5 in x 3 in 50 39 still air Rmo thermal resistance 11 10 from junction to case Table 10 Thermal resistance value BGA packages Symbol Parameter Conditions Thermal resistance in C W 15 96 LBGA256 TFBGA100 thermal resistance from 4 5 in x 4in 29 46 junction to ambient still air 8 layer 4 5 in x 24 37 still air Rime thermal resistance from 14 11 junction to case All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 86 of 155 NXP Semiconductors LPC185x 3x 2x 1x 10 Static characteristics 32 bit ARM Cortex M3 microcontroller Table 11 Static characteristics Tamb 40 C to 105 unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Supply pins input output supply 2 4 3 6 V voltage Vpp REG 3V3 regulator supply voltag
27. and SDRAM devices LCD controller with DMA support and a programmable display resolution of up to 1024H x 768V Supports monochrome and color STN panels and TFT color panels supports 1 2 4 8 bpp Color Look Up Table CLUT and 16 24 bit direct pixel mapping SD MMC card interface Eight channel General Purpose DMA controller can access all memories on the AHB and all DMA capable AHB slaves Up to 164 General Purpose Input Output GPIO pins with configurable pull up pull down resistors All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 2 of 155 NXP Semiconductors LPC185x 3x 2x 1x 3 Applications 32 bit ARM Cortex M3 microcontroller GPIO registers are located on the AHB for fast access GPIO ports have DMA support Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins Four general purpose timer counters with capture and match capabilities One motor control PWM for three phase motor control One Quadrature Encoder Interface QEI Repetitive Interrupt timer RI timer Windowed watchdog timer Ultra low power Real Time Clock RTC on separate power domain with 256 bytes of battery
28. solder paste deposit Ed solder land plus solder paste occupied area solder resist DIMENSIONS in mm O O O i0 Tec Generic footprint pattern SL SP SR Hx Hy 1 00 0 450 0 450 0 600 17 500 17 500 SS Sey see detail X Refer to the package outline drawing for actual layout KRI SSO 09090 090999 lt gt 1 lt x lt gt 5 Oy 6 KS 096 05090000 995059 nte 006000009 05905050500 090590007 Nt lt gt s SONS 9000 xD eO 600059 Xo K TX e 6 KS bs 05 5 lt gt o ox Ae SS 9050 5 5 oS 99 5 ES gS gt gt 6 RS ees Ate t 90 0 RS ee e detail X Sot740 2 fr Fig 53 Reflow soldering for the LBGA256 package LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 142 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Footprint information for reflow soldering of TFBGA100 package solder land 2 solder resist DIMENSIONS in mm N solder paste deposit Generic footprint pattern EEH Refer to the
29. 1251 transmit master clock CLK2 014 K6 99 141 PU EMC_CLK3 SDRAM clock 3 CLKOUT Clock output pin R Function reserved R Function reserved SD SD MMC card clock EMC_CLK23 SDRAM clock 2 and clock 3 combined 12S0_TX_MCLK 125 transmit master clock 1251 SCK Receive Clock It is driven by the master and received by the slave Corresponds to the signal SCK in the S bus specification CLK3 P12 PU EMC CLK2 SDRAM clock 2 CLKOUT Clock output pin R Function reserved R Function reserved R Function reserved CGU OUT 1 CGU spare clock output 1 R Function reserved 1251 SCK Receive Clock It is driven by the master and received by the slave Corresponds to the signal SCK in the S bus specification LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 55 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Pin name 2 Description 2 s g lt lt 19 lg e SERAIS NIS ele Debug pins DBGEN L4
30. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination For example a bidirectional port requires one stream for transmit and one for receives The source and destination areas can each be either a memory region or a peripheral for master 1 but only memory for master 0 7 15 2 1 LPC185X 3X 2X 1X Features Eight DMA channels Each channel can support a unidirectional transfer 16 DMA request lines Single DMA and burst DMA request signals Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request The DMA burst size is set by programming the DMA Controller Memory to memory memory to peripheral peripheral to memory and peripheral to peripheral transfers are supported All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 68 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Scatter or gather DMA is supported through the use of linked lists This means that the source and destination areas do not have to occupy contiguous areas of memory Hardware DMA channel priority AHB slave DMA programming interface The DMA Controller is programmed by writing to the DMA control registers over the AHB slave interface Two AHB bus masters for transferring data These interfaces transfer da
31. General purpose digital input output pin CAN1 TD CAN 1 transmitter output R Function reserved R Function reserved PE 1 N14 12 PU R Function reserved R Function reserved R Function reserved 1 0 EMC_A19 External memory address line 19 GPIO7 1 General purpose digital input output pin CAN1 RD receiver input R Function reserved R Function reserved PE 2 M14 115 PU ADCTRIGO ADC trigger input 0 CANO RD CAN receiver input R Function reserved A20 External memory address line 20 GPIO7 2 General purpose digital input output pin R Function reserved R Function reserved R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 47 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name TFBGA100 LQFP144 LQFP208 Reset state 1 Type Description LBGA256 N 1 PE 3 2 0 2 c R Function reserved CANO TD CAN transmitter output ADCTRIG1 ADC trigger
32. General purpose digital input output pin R Function reserved R Function reserved R Function reserved PD 3 P4 l 2 N Function reserved PU CTOUT_6 SCTimer PWM output 7 Match output 2 of timer 1 EMC_D17 External memory data line 17 R Function reserved GPIO6 17 General purpose digital input output pin R Function reserved R Function reserved R Function reserved LPC185X_3X_2X_1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 43 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Pin name 2 Description j t8 8 3 B EI 5 e fag PD 4 T2 l BN l R Function reserved PU CTOUT 8 SCTimer PWM output 8 Match output 0 of timer 2 018 External memory data line 18 R Function reserved l O GPIO6 18 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PD 5 Pe l l Function reserved PU CTOUT 9 SCTimer PWM output 9 Match output of timer 3 019 External memory data lin
33. LCD VDO P4 1 UD O P4 1 UD 0 P4_1 UD 0 LCD LP P7 6 LCDLP P7 6 LCDLP P7 6 LCDLP LCD ENAB P4 6 LCDENAB P4 6 LCDENAB P4 6 LCDENAB LCDM LCDM LCDM LCDM LCD FP P4 5 LCDFP P4 5 LCDFP P4 5 LCDFP LCD DCLK P4 7 LCDDCLK P4 7 LCDDCLK P4 7 LCDDCLK LCD LE P7 0 LCDLE P7 0 LCDLE P7 0 LCDLE LCD PWR P7 7 CDPWR P7 7 LCDPWR P7 7 LCDPWR GP CLKIN PF 4 LCDCLKIN PF 4 LCDCLKIN PF 4 LCDCLKIN Table 40 LCD panel connections for STN dual panel mode External pin 4 bit mono STN dual panel 8 bit mono STN dual panel Color STN dual panel LPC18xxpin LCD function LPC18xx LCD function LPC18xx LCD function used used used LCD VD 23 16 LCD VD15 PB 4 LD 7 PB 4 LD 7 LCD_VD14 PB_5 LD 6 PB 5 LD 6 LCD VD13 PB 6 LD 5 PB 6 LD 5 LCD VD12 P8 3 LD 4 P8 3 LD 4 LCD VD11 P4 9 LD 3 P4 9 LD 3 4_9 LD 3 LCD_VD10 P4_10 LD 2 P4_10 LD 2 P4 10 LD 2 LCD VD9 P4 8 LD 1 P4 8 LD 1 P4 8 LD 1 LCD VD8 P7_5 LD 0 P7_5 LD 0 P7_5 LD 0 LCD_VD7 UD 7 P8 4 UD 7 LCD_VD6 P8 5 UD 6 P8 5 UD 6 LCD VD5 P8 6 UD 5 P8 6 UD 5 LCD VD4 P8 7 8 7 UD 4 LCD_VD3 P4 2 UD 3 P4 2 UD 3 P4 2 UD S3 LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 130 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 40 LCD pane
34. U1_DCD Data Carrier Detect input for UART1 R Function reserved lO GPIO6 10 General purpose digital input output pin R Function reserved R Function reserved lO SD DAT4 SD MMC data bus line 4 PC 12 L6 21 N R Function reserved PU R Function reserved O 1 Data Terminal Ready output for UART1 Can also be configured to be an RS 485 EIA 485 output enable signal for UART1 R Function reserved GPIO6 11 General purpose digital input output pin R Function reserved 1250 TX SDA 125 transmit data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification SD DAT5 SD MMC data bus line 5 PC 13 Mi 21 N l R Function reserved PU R Function reserved O U1_TXD Transmitter output for UART1 R Function reserved l O GPIO6 12 General purpose digital input output pin R Function reserved lO 1250 TX WS Transmit Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the S bus specification lO SD DAT6 SD MMC data bus line 6 PC 14 N1 BIN l R Function reserved PU R Function reserved U1 RXD Receiver input for UART1 R Function reserved l O GPIO6 13 General purpose digital input output pin R Function reserved TX ER E
35. damage to the device Limiting values are stress ratings only and proper operation of the device at these or any other conditions above those given in the Recommended operating conditions section if present or the Characteristics sections of this document is not warranted Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms unless otherwise agreed in a valid written individual agreement In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 152 of 155 NXP Semiconductors LPC185x 3x 2x 1x Export control This document as well as the item s described he
36. index area 2 4 6 8 10 12 14 16 0 5 10 mm scale DIMENSIONS mm are the original dimensions SOT740 2 n UNIT max A1 A2 b D E e e1 e2 v w y y 045 11 0 55 17 2 172 mm 155 O25 Qo 095 dea deg a 18 15 025 04 012 0 35 OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC JEITA PROJECTION ISSUEDATE 05 06 46 MS ET did u EET Q 05 08 04 Fig 49 Package outline of the LBGA256 package LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 138 of 155 NXP Semiconductors LPC185x 3x 2x 1x TFBGA100 plastic thin fine pitch ball grid array package 100 balls body 9 x 9 x 0 7 mm 32 bit ARM Cortex M3 microcontroller SOT926 1 T B A Pd ball A1 index area E detail X Y e 1 Ov CI A B gt 4 b n e 1 2 i J H G F 4 E D c bal
37. the signal level EHS 1 for all pins Simulated values Symbol Parameter Conditions Min Typ Max Unit tlag lag time continuous transfer mode 0 5 x 1 5 ns SPI mode CPOL 0 0 SPI mode CPOL 0 Tey clk 1 5 ns CPHA 1 SPI mode CPOL 1 0 5 x 1 5 ns 0 SPI mode CPOL 1 Toy clk 1 5 ns CPHA 1 synchronous serial 1 5 ns frame mode microwire frame format 0 5 x Toy clk ns ta delay time continuous transfer mode 0 5 x ns SPI mode CPOL 0 0 SPI mode CPOL 0 n a ns CPHA 1 SPI mode CPOL 1 0 5 Toy ck ns 0 SPI mode CPOL 1 n a ns CPHA 1 synchronous serial T oy clk ns frame mode microwire frame format n a ns 1 SSPCLKDIV x 1 SCR x CPSDVSR The clock cycle time derived from the SPI bit rate Toy is a function of the main clock frequency fmain the SSP peripheral clock divider SSPCLKDIV the SSP SCR parameter specified in the SSPOCRO register and the SSP CPSDVSR parameter specified in the SSP clock prescale register 2 2 12 x Toy Pcug LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 114 of 155 NXP Semiconductors LPC185x 3x 2x
38. 0 1 1 Boot from external static memory such as NOR flash using CSO and an 8 bit data bus EMC 16 bit 0 1 0 0 Boot from external static memory such as NOR flash using CSO and a 16 bit data bus EMC 32 bit 0 1 0 1 Boot from external static memory such as NOR flash using CSO and a 32 bit data bus LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 63 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 4 Boot mode when OTP BOOT_SRC bits are programmed Boot mode BOOT SRC BOOT_SRC BOOT_SRC BOOT_SRC Description bit 3 bit 2 bit 1 bit 0 USBO 0 1 1 0 Boot from USBO USB1 0 1 1 1 Boot from USB1 SPI SSP 1 0 0 0 Boot from SPI flash connected to the SSPO interface on P3_3 function SSPO SCK 6 function SSPO_SSEL P3 7 function SSPO MISO and 8 function SSPO MOSIJ lI USART3 1 0 0 1 Enter ISP mode using USARTS functions on pins P2 3 and P2 4 1 Remark Pin functions for SPIFI and SSPO boot are different LPC185X 3X 2X 1X The boot loader programs the appropriate pin function at reset to boot using either SSPO or SPIFI Table 5 mode when OPT BOOT SRC bits are zero Boot mode Pins Description P2 9 P2 8 P1 2 P1
39. 0 5 ns th D data input hold time 0 8 2 2 ns Write cycle parameters taav data output valid delay time 3 8 0 5 x Toc 6 2 0 5 x Toyo NS tha data output hold time 0 5 x Toy clk 0 7 0 5 ns LPC185X 3X 2X 1X Table 30 Dynamic characteristics Dynamic external memory interface EMC CLK 3 0 delay values Tamb 40 to 105 C 23 3 V 10 2 4 V lt VppinEaj ava x 3 6 V Symbol Parameter Conditions Min Typ Max Unit ta delay time delay value 1 CLKn DELAY 0 0 0 0 0 0 0 ns CLKn DELAY 1 1 0 4 0 5 0 8 ns CLKn DELAY 2 1 0 7 1 0 1 7 ns CLKn DELAY 3 1 1 1 1 6 2 5 ns CLKn DELAY 4 1 1 4 2 0 3 3 ns CLKn DELAY 5 1 1 7 2 6 4 1 ns CLKn_DELAY 6 1 2 1 3 1 4 9 ns CLKn DELAY 7 1 2 5 3 6 5 8 ns 1 Program the delay values in the EMCDELAYCLK register see the LPC18xx User manual The delay values must be the same for all SDRAM clocks EMC_CLKn CLKO DELAY CLK1 DELAY CLK2 DELAY CLK3 DELAY All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 120 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller EMC_CLKn delay gt 0 EMC_CLKn delay 0 EMC DYCSn EMC RAS EMC CAS EMC WE EMC_CKEOUTn _ 22 0 EMC_DQMOUTn
40. 0000 0x1A08 0000 0x1A04 0000 0x1A00 0000 0x1800 0000 0x1400 0000 0x1041 0000 0x1040 0000 0x1008 A000 0x1008 0000 0x1000 8000 0x1000 0000 LPC185x 3x 2x 1x 4GB Al l A reserved OxFFFF FFFF 0xE010 0000 ARM private bus reserved SS reserved 3 reserved E reserved 16 MB static external memory CS3 16 MB static external memory CS2 16 MB static external memory CS1 16 MB static external memory CSO S reserved APB peripherals 2 BN reserved 3 reserved 256 kB flash B APB peripherals 1 reserved 256 kB flash B reserved 256 kB flash A 256 flash A APB peripherals 0 reserved clocking reset peripherals RTC domain peripherals reserved AHB peripherals 1 GB 256 MB dynamic external memory DYCS1 128 MB dynamic external memory DYCSO reserved 32 MB AHB SRAM bit banding reserved 16 kB EEPROM memory reserved 4x 16 kB AHB SRAM ANC i local SRAM flash SPIFI data ROM external static memory banks 256 MB shadow memory area reserved 64 MB SPIFI data reserved 64 kB ROM i i i f i i i i i i i i i i i reserved S i i i i i i i i i i i i i i i 32 8 local SRAM reserved 32 kB local SRAM LPC185x 3x 2x 1x Memory mapping overview 0 000 0000 0x8800 0000 0x8000 0000 0x7000 0000 0x6000 0000
41. 1 USARTO LOW LOW LOW LOW Enter ISP mode using USARTO pins P2 Oand P2 1 SPIFI LOW LOW LOW HIGH Boot from Quad SPI flash connected to the SPIFI interface on 3 to 81 EMC 8 bit LOW LOW HIGH LOW Boot from external static memory such as NOR flash using CSO and an 8 bit data bus EMC 16 bit LOW LOW HIGH HIGH Boot from external static memory such as NOR flash using CSO and a 16 bit data bus EMC 32 bit LOW HIGH LOW LOW Boot from external static memory such as NOR flash using CSO and a 32 bit data bus USBO LOW HIGH LOW HIGH Boot from USBO USB1 LOW HIGH HIGH LOW Boot from USB1 SPI SSP LOW HIGH HIGH HIGH Boot from SPI flash connected to the SSPO interface on P3 3 function SSPO SCK 6 function SSPO SSEL P3 7 function SSPO0 MISO and P3 8 function SSPO MOSIJI USART3 HIGH LOW LOW LOW Enter ISP mode using USARTS pins P2_3 and P2_4 1 The boot loader programs the appropriate pin function at reset to boot using either SSPO or SPIFI Remark Pin functions for SPIFI and SSPO boot are different All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 64 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 7 12 Memory mapping Fig 7 0x2000 0000 0x1F00 0000 0x1E00 0000 0x1D00 0000 0x1C00 0000 0x1B08 0000 0x1B04 0000 0x1B00
42. 12 13 13 1 13 2 13 3 13 4 13 5 13 6 13 7 14 15 16 17 18 19 19 1 19 2 19 3 19 4 20 Emulation and debugging 84 Limiting values 85 Thermal characteristics 86 Static characteristics 87 Power consumption 94 Peripheral power consumption 97 Electrical pin characteristics 99 BOD and band gap static characteristics 103 Dynamic characteristics 104 Flash EEPROM memory 104 Wake up 105 External clock for oscillator slave mode 105 Crystal 106 IRC oscillator 106 oscillator 106 GPOLKIIN 107 Rus 107 12 108 125 109 USART 110 SSP 112 External memory 117 USB interface 122 Etheffet i o sr E ee RE ECCE o 124 SB MMOQO a ood ee RR Im ers 125 eee 125 cede du 126 ADC DAC electrical characteristics 127 Application information 130 LCD panel signal usage 130 Crystal
43. 15 9 7 15 9 1 7 16 7 16 1 7 16 1 1 7 16 2 7 16 2 1 7 16 3 7 16 3 1 7 16 4 7 16 4 1 7 16 5 7 16 5 1 7 16 6 7 16 6 1 7 17 7 17 1 7 17 1 1 7 17 2 7 17 3 7 17 3 1 7 17 4 7 17 4 1 7 17 5 7 17 5 1 7 18 7 18 1 7 18 1 1 7 18 2 7 18 2 1 7 19 7 19 1 7 19 1 1 7 19 2 7 19 2 1 7 19 3 7 20 7 20 1 7 20 2 7 20 3 7 20 4 7 20 5 7 20 6 7 20 7 7 20 8 7 20 9 7 20 10 All information provided in this document is subject to legal disclaimers Ethernet 73 c site acai RR ERR 73 Digital serial peripherals 73 enter ELEMENTS 73 Featules os oed REX UR RR 74 USART sees ig ker t V s 74 Fealtutes cosas sue bre bibe 74 SSP serial I O controller 74 Feat tes 75 I C bus interface 75 75 125 interface 75 76 IR 76 76 Counter timers and motor control 77 General purpose 32 bit timers external event COUNTED ewe eek cd 77 Features is cnr ecu pa ue 77 Motor control PWM 77 Quadrature Encoder Interface QEI 77 Features week aad whe ius 77 Repetitive Interrupt RI timer 78
44. 1x 32 bit ARM Cortex M3 microcontroller Toy clk SCK CPOL 1 SSEL tlead MOSI CPHA 0 lud c DATA VALID MSB DATA VALID MSB MOSI CPHA 1 MISO CPHA 1 Fig 30 SSP master timing in SPI mode MISO CPHA 0 aS DATA VALID LSB SCK CPOL 0 DATA VALID MSB DATA VALID MSB DATA VALID MSB DATA VALID MSB aaa 013462 LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 115 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Toy clk SCK CPOL 0 SCK CPOL 1 MISO CPHA 0 ta tha DATA VALID MSB MOSI CPHA 0 DATA VALID MSB DATA VALID DATA VALID LSB IDLE DATA VALID MSB MISO CPHA 1 tay DATA VALID LSB DATA VALID MSB lt tha DATA VALID MSB DATA VALID DATA VALID MSB MOSI 1 DATA VALID LSB DATA VALID DATA VALID MSB IDLE DATA VALID MSB aaa 014942 Fig 31 SSP slave timing in SPI mode LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 AII rights reserved Product data sheet Rev 5 1 17
45. 2 7 V Vppa ava 3 6 V l 0 8 LSB 2 4 V Vppa ava lt 2 7 V 1 0 LSB Eg gain error 2 7 V Vppa ava 3 6 V 0l 0 3 2 4 V VppA ava lt 2 7 V 1 0 C load capacitance 200 pF RL load resistance 1 kQ ts settling time 2 0 4 us 1 In the DAC CR register bit BIAS 0 see the LPC 18xx user manual 2 Settling time is calculated within 1 2 LSB of the final value LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 129 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 13 Application information 13 1 LCD panel signal usage Table 39 LCD panel connections for STN single panel mode External 4 bit mono STN single panel 8 bit mono STN single panel Color STN single panel LPC18xxpin LCD function LPC18xx pin LCD function LPC18xx pin LCD function used used used LCD VD 23 8 LCD VD7 P8 4 UD 7 P8 4 UD 7 LCD_VD6 P8 5 UD 6 P8 5 UD 6 LCD VD5 P8 6 UD 5 P8 6 UD 5 LCD VD4 P8 7 UD 4 P8 7 UD 4 LCD VD3 P4 2 UD 3 P4 2 UD 3 P4 2 UD S3 LCD VD2 P4 3 UD 2 P4 3 UD 2 P4 3 UD 2 LCD VD1 P4 4 UD 1 P4 4 UD 1 P4 4 UD 1
46. 7 16 1 1 Features Maximum UART data bit rate of 8 MBit s 16 B Receive and Transmit FIFOs Register locations conform to 16C550 industry standard Receiver FIFO trigger points at 1 B 4 B 8 B and 14 B Built in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values Auto baud capabilities and FIFO control mechanism that enables software flow control implementation Equipped with standard modem interface signals This module also provides full support for hardware flow control auto CTS RTS Support for RS 485 9 bit EIA 485 mode UART1 DMA support 7 16 2 USART Remark The LPC185x 3x 2x 1x contain three USARTs In addition to standard transmit and receive data lines the USARTs support a synchronous mode and a smart card mode The USARTS include a fractional baud rate generator Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz 7 16 2 1 Features Maximum UART data bit rate of 8 MBit s 16 B Receive and Transmit FIFOs Register locations conform to 16C550 industry standard Receiver FIFO trigger points at 1 B 4 B 8 B and 14 B Built in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values Auto baud capabilities and FIFO control mechanism that enables software flow control implementation Support for RS 485 9 bit EIA 4
47. ARM Cortex M3 microcontroller TEST DEBUG INTERFACE ARM CORTEX M3 System l code D code HIGH SPEED PHY ETHERNET USBO USB1 0 1 masters slaves 256 512 kB FLASHA 256 512 kB FLASH B 64 kB ROM 32 kB LOCAL SRAM 40 kB LOCAL SRAM 32 kB AHB SRAM 16 kB AHB SRAM SPIFI EXTERNAL MEMORY CONTROLLER AHB REGISTER INTERFACES AHB MULTILAYER MATRIX master slave connection Fig 6 AHB multilayer matrix master and slave connections APB RTC DOMAIN PERIPHERALS 16 SRAM 002 544 7 5 Nested Vectored Interrupt Controller NVIC The NVIC is part of the Cortex M3 The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts 7 5 1 Features Controls system exceptions and peripheral interrupts On the LPC185x 3x 2x 1x the NVIC supports 53 vectored interrupts Eight programmable interrupt priority levels with hardware priority level masking Relocatable vector table LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 61 of 155 NXP
48. EMC D 31 0 write D 31 0 read delay 0 EMC D 31 0 read delay 0 register Fig 34 SDRAM timing o XL X C EMC CLKn delay tg programmable CLKn_DELAY ta qv ta ta xv ta ta pe ld xv lt 4 tsu D mr th D 002aag703 For the programmable EMC_CLK 3 0 clock delays CLKn_DELAY see Table 30 Remark For SDRAM operation set CLKO DELAY CLK1 DELAY CLK2 DELAY CLK3_DELAY in the EMCDELAYCLK LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 121 of 155 NXP Semiconductors LPC185x 3x 2x 1x 11 Table 31 14 USB interface 32 bit ARM Cortex M3 microcontroller Dynamic characteristics USBO and USB1 pins full speed 50 pF Roy 1 5 on D to unless otherwise specified 3 0 V lt lt 3 6 V Symbol Parameter Conditions Min Typ Max Unit t rise time 10 96 to 90 96 4 0 20 0 ns tr fall time 10 96 to 90 96 4 0 20 0 ns tFRFM differential rise and fall time tr t 90 111 11 matching Vcns output signal crossover voltage 1 3 2 0 V tFEOPT source SEO interval of EOP see Figure 35 160 175 ns tFpEoP source jitter for differential transition see Figure 35 2 5 ns to SEO transition Uni receiver jitter to n
49. EMC D10 External memory data line 10 R Function reserved U1 TXD Transmitter output for UART1 T1 MAT2 Match output 2 of timer 1 R Function reserved R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 25 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Pin name 2 Description 2 g lt lt 9 2 Ek E a o 2 GO G fals 2 area ese P5 7 R12 65 91 2 IN GPIO2 7 General purpose digital input output pin PU 2 Motor control PWM channel 2 output A 011 External memory data line 11 R Function reserved U1 RXD Receiver input for UART1 1 Match output of timer 1 R Function reserved R Function reserved P6 0 M12 H7 73 105 B IN R Function reserved PU 1280 MCLK 125 receive master clock R Function reserved R Function reserved lO 1250 SCK Receive Clock It is driven by the master and received by the slave Corresponds to the signal SCK in the S bus specification R Function reserved R Function reserved R
50. External memory data line 12 R Function reserved U1_DSR Data Set Ready input for UART1 T1_CAPO Capture input 0 of timer 1 R Function reserved R Function reserved 39 55 PU 1 0 GPIO2 10 General purpose digital input output pin MCI2 Motor control PWM channel 2 input 1 0 EMC_D13 External memory data line 13 R Function reserved U1_DTR Data Terminal Ready output for UART1 Can also be configured to be an RS 485 EIA 485 output enable signal for UART1 T1_CAP1 Capture input 1 of timer 1 R Function reserved R Function reserved P5 2 R4 46 63 PU GPIO2 11 General purpose digital input output pin 1 Motor control PWM channel 1 input 014 External memory data line 14 R Function reserved U1_RTS Request to Send output for UART1 Can also be configured to be an RS 485 EIA 485 output enable signal for UART1 T1_CAP2 Capture input 2 of timer 1 Function reserved R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 24 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description contin
51. Figure 38 Table 23 Dynamic characteristic I O pins 1 added e Parameter corrected for high drive pins changed from 2 pF to 5 2 pF See Table 11 Internal pull up resistor configuration added for RESET WAKEUPn and ALARM pins See Table 3 Description of DEBUG pin updated Input range for PLL1 corrected 1 MHz to 25 MHz See Section 7 20 7 System PLL1 Signal polarity corrected for pins EMC_CKEOUT and EMC_DQMOUT Both signals are active HIGH Updated USART timing figure See Figure 29 USART timing Updated USART Dynamic characteristics table See Table 26 USBO VBUS changed to input only See Table 3 Pin description e SPIFI output timing parameters Table 36 corrected to apply to Mode 0 twa changed to 3 2 ns tho changed to 0 6 ns e Parameter tcs i wg with condition PB 1 corrected WAITWEN 1 Tey cik added See Table 28 Dynamic characteristics Static asynchronous external memory interface e Parameter tcsi gis with condition PB 0 corrected WAITWEN 1 x Tey cik added See Table 28 Dynamic characteristics Static asynchronous external memory interface Removed restriction on C CAN bus usage See CAN 1 errata in Ref 2 Updated Figure 30 SSP master timing in SPI mode and Figure 31 SSP slave timing in SPI mode Changed the flash erase time ter to 100ms See Table 15 Updated Dynamic characteristics USBO and USB1 pins full speed Se
52. Figure 39 3 The integral non linearity Ei is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors See Figure 39 4 The offset error Eo is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve See Figure 39 5 The gain error is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error and the straight line which fits the ideal transfer curve See Figure 39 6 The absolute error is the maximum difference between the center of the steps of the actual transfer curve of the non calibrated ADC and the ideal transfer curve See Figure 39 7 Tamb 25 C 8 Input resistance depends on the sampling frequency fs Rj 2 1 fs x Cia LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 127 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller offset gain error error Eo EG 1023 1022 1021 H 1020 1019 1018 a E code out 6 e 5 L 4L 2 e qk 1LSB ideal o wl ue li 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 102
53. November 2015 116 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 28 11 13 External memory interface Dynamic characteristics Static asynchronous external memory interface 22 pF for EMC_Dn 20 pF for all others Tamp 40 C to 105 C 2 4 V lt Vppieay ava lt 3 6 V 2 7 V lt Vopii0 x 3 6 V values guaranteed by design the values in the table have been calculated with WAITTURN 0x0 in STATICWAITTURN register Timing parameters are given for single memory access cycles In a normal read operation the EMC changes the address while CS is asserted which results in multiple memory accesses 32 bit ARM Cortex M3 microcontroller WAITWEN 1 Tey clk WAITWEN 1 Toy elk Symbol 1 Conditions Min Typ Max Unit Read cycle parameters tosav CS LOW to address valid 3 1 1 6 ns time CSLOEL cs LOW to OE LOW time 2 0 6 Tey clk x 1 34 Toy clk x ns WAITOEN WAITOEN 5_ CS LOW to BLS LOW time 1 0 7 1 8 ns toeLoeH OE LOW to OE HIGH time 2 0 6 0 4 5 WAITRD WAITRD WAITOEN 1 x WAITOEN 1 x Tey clk Tey clk tam memory access time 16 ns WAITRD WAITOEN 1 x Tey clk th D data input hold time 16 ns tcsHBLsH CS HIGH to BLS HIGH time PB 1 0 4 1 9 ns tcsHoeH CS HIGH to OE HIGH time 0 4 1 4 ns toeHaANv OE HIGH
54. PHY e Supports all full speed USB compliant peripherals Supports interrupts Supports Start Of Frame SOF frame length adjust This module has its own integrated DMA engine e USB interface electrical test software included in ROM USB stack LCD controller Remark The LCD controller is only available on parts LPC185x LCD is not available on parts LPC183x LPC182x and LPC181x The LCD controller provides all of the necessary control signals to interface directly to various color and monochrome LCD panels Both STN single and dual panel and TFT panels can be operated The display resolution is selectable and can be up to 1024 x 768 pixels Several color modes are provided up to a 24 bit true color non palettized mode An on chip 512 byte color palette allows reducing bus utilization that is memory size of the displayed data while still supporting many colors The LCD interface includes its own DMA controller to allow it to operate independently of the CPU and other system functions A built in FIFO acts as a buffer for display data providing flexibility for system timing Hardware cursor support can further reduce the amount of CPU time required to operate the display Features AHB master interface to access frame buffer Setup and control via a separate AHB slave interface Dual 16 deep programmable 64 bit wide FIFOs for buffering incoming display data Supports single and dual panel monochrome Super Twiste
55. configured as output high drive 215 2 5 3 9 ns mode EHD 0x2 tr rise time pin configured as output ultra high 2151 2 8 4 7 ns drive mode EHD 0x3 tr fall time pin configured as output ultra high 215 2 4 3 4 ns drive mode EHD 0x3 tr rise time pin configured as input A 0 3 1 3 ins tr fall time pin configured as input AH 0 2 1 2 ns I O pins high speed tr rise time pin configured as output EHS 1 23 350 670 ips tr fall time pin configured as output EHS 1 23 450 730 ps tr rise time pin configured as output EHS 0 23 1 0 1 9 ins tr fall time pin configured as output EHS 0 12113 1 0 2 0 ins tr rise time pin configured as input A 0 3 1 3 ins tf fall time pin configured as input 41 0 2 1 2 1 Simulated data All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 107 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 2 Simulated using 10 cm of 50 Q PCB trace with 5 pF receiver input Rise and fall times measured between 80 and 20 of the full output signal level 3 The slew rate is configured in the system control block in the SFSP registers using the EHS bit See the LPC43xx user manual 4 C 20 pF Rise and fall times measured between 90 and 10 of the full input sign
56. current condition lO SSP1 SSEL Slave Select for SSP1 R Function reserved 80 SD MMC card power monitor output P1 6 T4 K4 49 67 BI GPIO1 9 General purpose digital input output pin PU CTIN 5 SCTimer PWM input 5 Capture input 2 of timer 2 R Function reserved WE LOW active Write Enable signal R Function reserved EMC_BLSO LOW active Byte Lane select signal 0 R Function reserved SD SD MMC command signal P1 7 T5 G4 50 69 2 N GPIO1 0 General purpose digital input output PU U1 DSR Data Set Ready input for UART1 CTOUT 13 SCTimer PWM output 13 Match output 3 of timer 3 DO External memory data line 0 USBO0 PPWR VBUS drive signal towards external charge pump or power management unit indicates that VBUS must be driven active HIGH Add a pull down resistor to disable the power switch at reset This signal has opposite polarity compared to the USB PPWR used on other NXP LPC parts R Function reserved R Function reserved R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 10 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcont
57. in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 37 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name TFBGA100 LQFP144 LQFP208 Reset state 1 Type Description gt LBGA256 wo 1 PB 3 2 0 2 c R Function reserved USB1 ULPI 06 ULPI link bidirectional data line 6 LCD VD20 LCD data R Function reserved GPIO5 23 General purpose digital input output pin CTOUT 8 SCTimer PWM output 8 Match output 0 of timer 2 R Function reserved R Function reserved PB 4 B11 180 PU R Function reserved USB1 ULPI D5 ULPI link bidirectional data line 5 LCD VD15 LCD data R Function reserved GPIO5 24 General purpose digital input output pin CTIN 5 SCTimer PWM input 5 Capture input 2 of timer 2 R Function reserved R Function reserved PB 5 A12 181 PU R Function reserved USB1 ULPI D4 ULPI link bidirectional data line 4 LCD VD14 LCD data R Function reserved GPIO5 25 General purpose digital input output pin CTIN 7 SCTimer PWM input 7 LCD PWR LCD panel power enable R Function re
58. in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 32 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name TFBGA100 LQFP144 Reset state 1 Type Description S LBGA256 2 LQFP208 P8 4 2 0 2 c GPIO4 4 General purpose digital input output pin USB1 ULPI D1 ULPI link bidirectional data line 1 R Function reserved LCD VD7 LCD data LCD VD16 LCD data R Function reserved R Function reserved TO Capture input 0 of timer 0 P8 5 J1 5 40 121 IN PU GPIO4 5 General purpose digital input output pin USB1_ULPI_D0O ULPI link bidirectional data line 0 R Function reserved LCD_VD6 LCD data LCD_VD8 LCD data R Function reserved R Function reserved TO_CAP1 Capture input 1 of timer 0 P8_6 K3 43 PU GPIO4 6 General purpose digital input output pin USB1_ULPI_NXT ULPI link NXT signal Data flow control signal from the PHY R Function reserved LCD_VD5 LCD data LCD_LP Line synchronization pulse STN Horizontal synchronization pulse TFT R Function reserved R Function reserved TO_CAP2
59. input output pin PU USBO PWR FAULT Port power fault signal indicating overcurrent condition this signal monitors over current on the USB bus external circuitry required to detect over current condition R Function reserved 12 Motor control PWM channel 2 input R Function reserved R Function reserved R Function reserved 0 MATO Match output 0 of timer 0 P8 1 H5 l 34 BI IN GPIO4 1 General purpose digital input output pin PU USBO IND1 USBO port indicator LED control output 1 R Function reserved MCI1 Motor control PWM channel 1 input R Function reserved R Function reserved R Function reserved TO_MAT1 Match output 1 of timer 0 P8 2 K4 36 BI IN GPIO4 2 General purpose digital input output pin PU USBO INDO USBO port indicator LED control output 0 R Function reserved MCIO Motor control PWM channel 0 input R Function reserved R Function reserved R Function reserved 0 MAT2 Match output 2 of timer 0 P8 3 J3 37 121 GPIO4 3 General purpose digital input output pin PU VO USB1 ULPI D2 ULPI link bidirectional data line 2 R Function reserved O LCD_VD12 LCD data O LCD_VD19 LCD data R Function reserved R Function reserved 0 MATS Match output 3 of timer 0 LPC185X 3X 2X 1X All information provided
60. level output lo 6 mA 0 4 V voltage HIGH level output Vou 0 4 V 6 mA current LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 88 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 11 Static characteristics continued Tamb 40 C to 105 unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit loL LOW level output VoL 0 4 V 6 mA current lous HIGH level short circuit drive HIGH connected to 10 87 mA output current ground lois LOW level short circuit drive LOW connected to 10 77 mA output current lod pull down current Vi 5V 12 93 pA 13 14 lou pull up current Vi 0V 12 62 pA 13 14 Vpp o Mi 5V 10 Rs series resistance on I O pins with analog 200 Q function analog function enabled I O pins high drive strength Ci input capacitance 5 2 pF lu LOW level leakage Vi 0 V on chip pull up 3 nA current resistor disabled loz OFF state output Vo 0V to 3 nA current on chip pull up down resistors disabled absolute value Vi input voltage pin configured to provide a digital function Vpp o 2 2 4 V 0 5 5 V
61. normal read operation the EMC changes the address while CS is asserted which results in multiple memory accesses 32 bit ARM Cortex M3 microcontroller Symbol 1 Conditions Min Typ Max Unit 1 BLS LOW to BLS HIGH time 0 21 0 9 0 1 ns WAITWR WAITWR WAITWEN 1 x WAITWEN 1 x Tey clk Toy cll tstsHeow BLS HIGH to end of write 0 21 1 9 0 5 ns time 5 tgisupuv BLS HIGH to data invalid 0 2 2 5 Tey clk 1 4 Toyclk ns time tcsHEOW CS HIGH to end of write 5 2 0 x 0 ns time tatsHpnv BLS HIGH to data invalid PB 1 2 5 1 4 ns time tWEHANV WE HIGH to address invalid 1 0 9 Tey clk 24 Tey clk ns time 1 2 3 4 Start Of Read SOR longest of tcsi tcsLoeL tcsLBLsL End Of Write EOW earliest of address not valid or EMC_BLSn HIGH Parameters specified for 40 of Vppiioy for rising edges and 60 of Vpp oy for falling edges 1 CCLK see LPC18xx User manual End Of Read EOR longest of tCSHOEH toEHANv tcSHBLSH EMC An tcsLav toEHANV lCSHEOW EMC CSn tCSLOEL BEEN lt toELOEH EMC_OE t BLSHEOW tcsLBLSL tBLSLBLSH ene EMC BLSn EMC WE fam tcsLDv lt tcsHEOR M4 tcsLsoR gt acum EMC Dn SOR EOR EOW 002aag699
62. of 155 NXP Semiconductors LPC185x 3x 2x 1x 7 17 7 17 1 7 17 1 1 7 17 2 7 17 3 7 17 3 1 LPC185X 3X 2X 1X 32 bit ARM Cortex M3 microcontroller Counter timers and motor control General purpose 32 bit timers external event counter Remark The LPC185x 3x 2x 1x include four 32 bit timer counters The timer counter is designed to count cycles of the system derived clock or an externally supplied clock It can optionally generate interrupts generate timed DMA requests or perform other actions at specified timer values based on four match registers Each timer counter also includes two capture inputs to trap the timer value when an input signal transitions optionally generating an interrupt Features A 32 bit timer counter with a programmable 32 bit prescaler Counter or timer operation Two 32 bit capture channels per timer that can take a snapshot of the timer value when an input signal transitions A capture event can also generate an interrupt Four 32 bit match registers that allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Up to four external outputs corresponding to match registers with the following capabilities Set LOW on match Set HIGH on match Toggle on match Do nothing on match e Up to two match registers can be used to ge
63. over current condition LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 15 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name LQFP208 Reset state 1 Type Description TFBGA100 A LBGA256 eo LQFP144 pra wo A P2 5 3 UZ c R Function reserved CTIN 2 SCTimer PWM input 2 Capture input 2 of timer 0 USB1 VBUS Monitors the presence of USB1 bus power Note This signal must be HIGH for USB reset to occur ADCTRIG1 ADC trigger input 1 1 0 GPIO5 5 General purpose digital input output pin R Function reserved T3_MAT2 Match output 2 of timer 3 USBO INDO USBO port indicator LED control output 0 P2 6 K16 G9 95 137 PU R Function reserved 1 0 UO DIR RS 485 EIA 485 output enable direction control for USARTO 1 0 EMC_A10 External memory address line 10 USBO INDO USBO port indicator LED control output 0 1 0 GPIO5 6 General purpose digital input output pin CTIN_7 SCTimer PWM input 7 T3_CAP3 Capture input 3 of timer 3 EMC_BLS1 LOW active Byte Lane select signal 1 P2_7 H14 C10 96 138 PU
64. package 144 leads body 20 x 20 x 1 4 mm SOT486 1 LPC1815JET100 TFBGA100 Plastic thin fine pitch ball grid array package 100 balls body 9 x 9 x 0 7 mm SOT926 1 LPC1813JBD144 LQFP144 Plastic low profile quad flat package 144 leads body 20 x 20 x 1 4 mm SOT486 1 LPC1813JET100 TFBGA100 Plastic thin fine pitch ball grid array package 100 balls body 9 x 9 0 7 mm SOT926 1 LPC1812JBD144 LQFP144 Plastic low profile quad flat package 144 leads body 20 x 20 x 1 4 mm SOT486 1 LPC1812JET100 TFBGA100 Plastic thin fine pitch ball grid array package 100 balls body 9 x 9 x 0 7 mm SOT926 1 LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 4 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 4 1 Ordering options Table 2 Ordering options EE c 5 4 m sies E zw TES Esdr z 2 8 85 amp 9 5 5 g 9 9 E 5 o 5 B 9 ge E 35 3 o 3S 9 LPC1857FET256 1 MB 512kB 512 136kB yes yes yes yes yes yes yes 8 F 164 LPC1857JET256 1 MB 512 512 136kB yes yes yes yes yes yes yes 8 J 164 LPC1857JBD208 1 MB 512kB 512kB 136kB yes yes yes yes yes yes yes 8 J 142 LPC1853FE
65. pin LCD VD22 LCD data CAN1 TD transmitter output R Function reserved P4 9 L2 48 B N R Function reserved PU TIN 6 SCTimer PWM input 6 Capture input 1 of timer 3 O LCD VD11 LCD data R Function reserved GPIO5 13 General purpose digital input output pin 015 LCD data CAN1 RD receiver input R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 23 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name TFBGA100 Reset state 1 Type Description lt LBGA256 wo 1 P4 10 LQFP144 LQFP208 2 0 2 c R Function reserved CTIN 2 SCTimer PWM input 2 Capture input 2 of timer 0 LCD VD10 LCD data R Function reserved 1 0 GPIO5 14 General purpose digital input output pin LCD_VD14 LCD data R Function reserved R Function reserved P5_0 37 53 PU 1 0 GPIO2 9 General purpose digital input output pin MCOB2 Motor control PWM channel 2 output B 012
66. pin is configured as input WAKEUP1 A10 UU BIA External wake up input can raise an interrupt and can cause wake up from any of the low power modes A pulse with a duration of at least 45 ns wakes up the part Input 1 of the event monitor No internal pull up is enabled when this pin is configured as input WAKEUP2 C9 11 BIA External wake up input can raise an interrupt and can cause wake up from any of the low power modes A pulse with a duration of at least 45 ns wakes up the part Input 2 of the event monitor This pin does not have an internal pull up WAKEUP3 D8 OIA Cg External wake up input can raise an interrupt and can cause wake up from any of the low power modes A pulse with a duration of at least 45 ns wakes up the part This pin does not have an internal pull up ADC pins ADCO 0 2 6 8 8 ADC input channel 0 Shared between 10 bit ADCO 1 and ADC1 0 DAC 1 ADCO 1 1 2 4 81 AE ADC input channel 1 Shared between 10 bit ADCO 1 ADC1 1 1 ADCO 2 A4 B3 143 206 181 ADC input channel 2 Shared between 10 bit ADCO 1 ADC1 2 1 ADCO 3 B5 139 200 Bl ADC input channel 3 Shared between 10 bit ADCO 1 ADC1 3 IA ADCO 4 C6 138 199 81 ADC input channel 4 Shared between 10 bit ADCO 1 ADC1 4 IA ADCO 5 B3 144 208 Bl ADC input channel 5 Shared between 10 bit ADCO 1 ADC1 5 1 ADCO 6 A5 142 204 8 ADC input channel 6 Shared be
67. provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 13 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name LQFP208 Reset state 1 Type Description A TFBGA100 lt LBGA256 c LQFP144 P1 20 0 2 0 2 c GPIOO 15 General purpose digital input output pin SSP1 SSEL Slave Select for SSP1 R Function reserved ENET TXD1 Ethernet transmit data 1 RMII MII interface TO CAP2 Capture input 2 of timer 0 R Function reserved R Function reserved EMC D11 External memory data line 11 P2 0 T16 G10 75 108 121 IN PU Function reserved UO TXD Transmitter output for USARTO See Table 4 for ISP mode 1 0 EMC_A13 External memory address line 13 USB0_PPWR VBUS drive signal towards external charge pump or power management unit indicates that VBUS must be driven active HIGH Add a pull down resistor to disable the power switch at reset This signal has opposite polarity compared to the USB_PPWR used on other NXP LPC parts GPIO5 0 General purpose digital input output Function reserved T3_CAPO Capture input 0 of timer ENET_MDC
68. receive 4 bit to 16 bit frame Connected to the GPDMA I C bus interface Remark The LPC185x 3x 2x 1x contain two 2 interfaces The I C bus is bidirectional for inter IC control using only two wires a Serial Clock line SCL and a Serial Data line SDA Each device is recognized by a unique address and can operate as either a receiver only device for example an LCD driver or a transmitter with the capability to both receive and send information such as memory Transmitters and or receivers can operate in either master or slave mode depending on whether the chip has to initiate a data transfer or is only addressed The I C bus interface is multi master bus and can be controlled by more than one bus master connected to it Features 12 0 is a standard I2C bus compliant bus interface with open drain pins I2CO also supports Fast mode plus with bit rates up to 1 Mbit s e C1 uses standard l O pins with bit rates of up to 400 kbit s Fast I C bus Easy to configure as master slave or master slave Programmable clocks allow versatile rate control Bidirectional data transfer between masters and slaves Multi master bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mech
69. reference REF currents and voltages VDDA B4 B2 137 198 Analog power supply and ADC reference voltage VBAT B10 C5 127 184 RTC power supply 3 3 V on this pin supplies power to the RTC VDDREG F10 E4 94 1135 Main regulator power supply F9 5 131 188 L8 F4 59 195 L7 25 82 33 VPP E8 12 programming voltage VDDIO D7 F10 5 6 12 F I O power supply E12 K5 36 52 F7 41 57 F8 71 102 G10 77 1110 H10 107 155 J6 111 160 J7 141 202 K7 L9 L10 N7 N13 LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 AII rights reserved Product data sheet Rev 5 1 17 November 2015 58 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Pin name 2 Description A o e le Ig E N 4 3 S D gt gt amp z VSS G9 C8 13 Ground H7 D4 J10 D5 J11 G8 K8 J3 J6 VSSIO C4 l 4 5 13 Ground D13 40 56 G6 76 109 G7 109 157 G8 H8 H9 J8 J9 K9 K10 M13 P7 P13 VSSA B2 C2 135 196 Analog ground 1 neutral input buffer disabled no extra VDDIO current consumption if the input is driven midway between supplies set the EZI bit in the SFS register to enable the input buffer input OL output driving LOW OH out
70. reserved USB1 ULPI NXT ULPI link NXT signal Data flow control signal from the PHY R Function reserved ENET RX ER Ethernet receive error MII interface 1 0 GPIO6 8 General purpose digital input output pin Function reserved T3_MAT2 Match output 2 of timer 3 SD_POW SD MMC power monitor output PC_10 M5 N PU R Function reserved USB1_ULPI_STP ULPI link STP signal Asserted to end or interrupt transfers to the PHY U1_DSR Data Set Ready input for UART1 R Function reserved GPIO6 9 General purpose digital input output pin R Function reserved T3_MAT3 Match output 3 of timer 3 SD_CMD SD MMC command signal LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 41 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name 2 Description ip o e ie E 8 E S S3 gale PC 11 L5 BON l R Function reserved PU USB1 ULPI DIR ULPI link DIR signal Controls the ULP data line direction
71. supply voltages changed to 0 5 V n Table 7 LPC1857 53 v 3 20120711 Preliminary data sheet LPC1857 53 v 2 Modifications Data sheet status changed to preliminary AES removed Available on parts LPC18Sxx only e Minimum value of V for conditions USBO pins USBO DP USBO DM USBO VBUS USBO pins USBO ID USBO_RREF and USB1 pins USB1 DP USB1 DM changed to 0 3 V in Table 6 Dynamic characteristics of the SD MMC controller updated in Table 29 Dynamic characteristics of the LCD controller updated in Table 30 Dynamic characteristics of the SSP controller updated in Table 22 Section 10 2 added Table 8 Thermal resistance value BGA packages added Description of pins USB1 DP and USB1 DM updated in Table 3 Editorial updates Parameters li and renamed to lj and liu in Table 9 LPC1857 53 v 2 20120515 Objective data sheet LPC1857_53 v 1 LPC1857_53 v 1 20111214 Objective data sheet LPC185X_3X_2X_1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 151 of 155 NXP Semiconductors LPC185x 3x 2x 1x 19 Legal information 32 bit ARM Cortex M3 microcontroller 19 1 Data sheet status Document status 1l2 Product status Definition Objective short data sheet Development This document contains data from t
72. synchronous mode R Function reserved P4 1 Al 3 3 B N GPIO2 1 General purpose digital input output PU CTOUT 1 SCTimer PWM output 1 Match output 3 of timer 3 LCD VD0 LCD data R Function reserved R Function reserved O LCD VD19 LCD data TXD Transmitter output for USARTS3 ENET COL Ethernet Collision detect MII interface 1 ADCO and ADC1 input channel 1 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC P4 2 D3 l 8 12 IN VO GPIO2 2 General purpose digital input output pin PU CTOUT 0 SCTimer PWM output 0 Match output 0 of timer 0 O LCD VD3 LCD data R Function reserved R Function reserved O LCD VD12 LCD data U3 RXD Receiver input for USART3 R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 21 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name TFBGA100 LQFP208 Reset state 1 Type Description LBGA256 N LQFP144 P4 3 5 UZ c 2 3 General purpose digital input output pin CTOUT 3 SCTimer PWM output 3 Match out
73. with a Current Controlled Oscillator CCO The multiplier can be an integer value from 1 to 32 The CCO operates in the range of 156 MHz to 320 MHz This range is possible through an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency The output divider can be set to divide by 2 4 8 or 16 to produce the output clock Since the minimum output divider value is 2 it is insured that the PLL output has a 50 duty cycle The PLL is turned off and bypassed following a chip reset After reset software can enable the PLL The program must configure and activate the PLL wait for the PLL to lock and then connect to the PLL as a clock source The PLL settling time is 100 ps Reset Generation Unit RGU The RGU allows generation of independent reset signals for individual blocks and peripherals Power control The LPC185x 3x 2x 1x feature several independent power domains to control power to the core and the peripherals see Figure 9 The RTC and its associated peripherals the alarm timer the CREG block the OTP controller the back up registers and the event router are located in the RTC power domain The main regulator or a battery supply can power the RTC A power selector switch ensures that the RTC block is always powered on All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet
74. 0x4400 0000 0x4200 0000 0x4010 2000 0x4010 1000 0x4010 0000 400 8000 0x400F 4000 Ox400F 2000 0x400F 1000 0x400F 0000 0x400E 0000 0x400D 0000 0x400C 0000 0x400B 0000 0x400A 0000 0x4009 0000 0x4008 0000 0 4006 0000 0x4005 0000 0x4004 0000 0x4001 2000 0x4000 0000 0x3000 0000 0x2800 0000 0x2400 0000 0x2200 0000 0x2004 4000 0x2004 0000 0x2001 0000 0x2000 0000 0x1000 0000 0x0000 0000 002aag545 LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 65 of 155 Lep 19npoJd GLOZ J9qUI9AON ZL L S sieuirejosip joefqns s jueuunoop siu uoneuuojul 991 JO 99 XL XZ XE XS810d1 pamasa syu SLOZ N8 dXN 0x400F 0000 0x400E 5000 0x400E 4000 0x400E 3000 0x400E 2000 0x400E 1000 0x400E 0000 0x400C 8000 0x400C 7000 0x400C 6000 0x400C 5000 0x400C 4000 0x400C 3000 0x400C 2000 0x400C 1000 0x400C 0000 0x400B 0000 0x400A 5000 0x400A 4000 0x400A 3000 0x400A 2000 0x400A 1000 0x400A 0000 0x4008 A000 0x4008 9000 0x4008 8000 0x4008 7000 0x4008 6000 0x4008 5000 0x4008 4000 0x4008 3000 0x4008 2000 0x4008 1000 0x4008 0000 Fig 8 GIMA SSP1 reserved C_CAN1 1251 1250 12 0 motor control PWM GPIO GROUP interrupt GPIO GROUP
75. 105 unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit I O pins high drive strength ultra high drive mode lu HIGH level leakage Vi on chip 3 nA current pull down resistor disabled Vi 5 V Tamb 25 C 0 6 nA Vi 2 5 Vi Tamb 105 C 63 HIGH level output Vou 0 4 V 20 mA current lot LOW level output 0 4 V 20 mA current lous HIGH level short circuit drive HIGH connected to 10 165 mA output current ground lois LOW level short circuit drive LOW connected to 10 156 mA output current Vpp I0 l O pins high speed Ci input capacitance 2 pF lu LOW level leakage Vi 0 V on chip pull up 3 nA current resistor disabled ILH HIGH level leakage Vi on chip 3 nA current pull down resistor disabled Vi 5 Vi Tamb 25 C 0 5 nA V 5 V Tamb 105 C 40 nA loz OFF state output Vo 0 Vto Vpp oy 3 nA current on chip pull up down resistors disabled absolute value Vi input voltage pin configured to provide a digital function gt 2 4 0 5 5 V 0 V 0 3 6 V Vo output voltage output active 0 Vpb o V Viu HIGH level input 0 7 x 5 5 V voltage Vpb o LOW level input voltage 0 0 3 x V Vpp 0 Vhys hysteresis voltage 0 1 x V Vpp 0 Vou HIGH level output lou 8 mA Vpp o V voltage 0 4 Vor LOW level output lo 8 0 4 V voltage lou HIGH level
76. 2015 70 of 155 NXP Semiconductors LPC185x 3x 2x 1x 7 15 6 7 15 6 1 LPC185X 3X 2X 1X 32 bit ARM Cortex M3 microcontroller Read and write buffers to reduce latency and to improve performance 8 16 32 data and 24 address lines wide static memory support 16 bit and 32 bit wide chip select SDRAM memory support Static memory features include Asynchronous page mode read Programmable Wait States Bus turnaround delay Output enable and write enable delays Extended wait Four chip selects for synchronous memory and four chip selects for static memory devices Power saving modes dynamically control CKE and CLKOUT to SDRAMs Software controlled dynamic memory self refresh mode Controller supports 2048 to A10 4096 AO to 11 and 8192 to 12 row address synchronous memory parts Those are typically 512 MB 256 MB and 128 MB parts Separate reset domains allow auto refresh through a chip reset if desired Note Synchronous static memory devices synchronous burst mode are not supported High speed USB Host Device OTG interface USBO Remark USBO is available on the following parts LPC185x LPC 183x LPC182x USBO is not available on the LPC181x parts The USB OTG module allows the part to connect directly to a USB host such as a PC in device mode or to a USB device in host mode Features On chip UTMI compliant high speed transceiver PHY Complies with Universal Serial Bus s
77. 25 Receive data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification TD CAN transmitter output USB1 INDO USB1 Port indicator LED control output 0 l O GPIOB 9 General purpose digital input output pin R Function reserved O VD14 LCD data R Function reserved P3 3 B14 A7 118 169 A N R Function reserved Pu n R Function reserved lO SSPO SCK Serial clock for SSPO SCK Serial clock for SPIFI O CGU OUT1 CGU spare clock output 1 R Function reserved 1250 TX MCLK 125 transmit master clock lO 1251 TX SCK Transmit Clock It is driven by the master and received by the slave Corresponds to the signal SCK in the specification LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 19 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Pin name 2 Description 9 ux g S lt N a E s o 2 GO G fals 2 ej Je P3 4 A15 B8 119 171 1 GPIO1 14 General purpose digital input output pin PU R Functi
78. 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 124 of 155 NXP Semiconductors LPC185x 3x 2x 1x 11 16 SD MMC Table 34 pins Simulated values 32 bit ARM Cortex M3 microcontroller Dynamic characteristics SD MMC Tamb 40 C to 105 24V lt Vpp REG 3V3 3 6 02 7 lt Vpp o lt 3 6 V 20 pF Simulated values SAMPLE DELAY 0x9 DRV_DELAY 0x6 in the SDDELAY register sampled at 90 and 10 of the signal level EHS 1 for SD_CLK pin EHS 0 for SD_DATn and SD_CMD Fig 37 SD MMC timing 002aag204 Symbol Parameter Conditions Min Unit folk clock frequency on pin SD_CLK data transfer mode 52 MHz tsu D data input set up time pins SD_DATn as inputs 52 ns on pins SD as inputs 7 ns th D data input hold time on pins SD_DATn as inputs 0 2 ns on pins SD_CMD as inputs 1 ns tav data output valid delay pins SD DATn as outputs 15 7 ns time on pins SD CMD as outputs 15 9 ns tha data output hold time on pins SD_DATn as outputs 3 5 ns on pins SD_CMD as outputs 3 5 l ns lt gt SD_CLK f Sy y ta av o 355A O yv SD_DATn SD_CMD I SD DATn l 11 17 LCD Table 35 Dynamic characteristics LCD Tamb 40 to 105 C 24V lt Vpp R
79. 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 140 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller LQFP144 plastic low profile quad flat package 144 leads body 20 x 20 x 1 4mm SOT486 1 22 1 detail X DIMENSIONS mm are the original dimensions UNIT Ai A2 bp 1 45 1 35 Note 1 Plastic or me al protrusions of 0 25 mm maximum per side are not included REFERENCES OUTLINE OJETIN ISSUE DATE VERSION IEC JEDEC JEITA SOT486 1 136E23 MS 026 03 02 20 Fig 52 Package outline of the LQFP100 package LPC185X_3X_2X_1X Product data sheet All information provided in this document is subject to legal disclaimers Rev 5 1 17 November 2015 NXP B V 2015 All rights reserved 141 of 155 NXP Semiconductors LPC185x 3x 2x 1x 15 Soldering 32 bit ARM Cortex M3 microcontroller Footprint information for reflow soldering of LBGA256 package SOT740 2 ZZ solder WY solder land
80. 3 Ethernet transmit data 3 MII interface R Function reserved UO TXD Transmitter output for USARTO P9 6 L11 72 103 21 1 0 4 11 General purpose digital input output pin PU MCOB1 Motor control PWM channel 1 output USB1 PWR FAULT USB1 Port power fault signal indicating over current condition this signal monitors over current on the USB1 bus external circuitry required to detect over current condition R Function reserved R Function reserved ENET COL Ethernet Collision detect MII interface R Function reserved UO RXD Receiver input for USARTO LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 35 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name 2 Description j i8 E IER ISTIS PA 0 L12 l 126 BN R Function reserved PU R Function reserved R Function reserved R Function reserved R Function reserved 1251 1251 receive master clock O CGU_OUT1 CGU spare clock out
81. 3x 2x 1x 12 ADC DAC electrical characteristics 32 bit ARM Cortex M3 microcontroller Table 37 ADC characteristics VppA ava Over specified ranges Tamb 40 C to 105 C unless otherwise specified cycles Symbol Parameter Conditions Min Max Unit Via analog input voltage 0 VpDA 3V3 V Cia analog input capacitance 2 pF Ep differential linearity error 2 7 V VppA ava lt 3 6 V 0 8 LSB 2 4 V Vppa ava lt 2 7 V 1 0 LSB integral non linearity 2 7 V Vppa ava 3 6 V 3 0 8 LSB 2 4 V Vppa ava lt 2 7 V 1 5 LSB Eo offset error 2 7 V Vppa ava 3 6 V i4 10 405 LSB 2 4 V Vppa ava lt 2 7 V 0 15 LSB Ec gain error 2 7 V Vppa ava lt 3 6 V 5 0 3 2 4 V Vppa ava lt 2 7 V 0 35 absolute error 2 7 V Vppa ava 3 6 V 6 3 LSB 2 4 V lt Vppa ava lt 2 7 V 4 LSB Rysi voltage source interface see Figure 40 1 7 xfakapc x KQ resistance Cia Ri input resistance 1 2 MQ fakApc ADC clock frequency 45 MHz fs sampling frequency 10 bit resolution 11 clock 400 kSamples s cycles 2 bit resolution 3 clock 1 5 MSamples s 1 The ADC is monotonic there are no missing codes 2 The differential linearity error Ep is the difference between the actual step width and the ideal step width See
82. 4 gt Via LSB offset error LSBideai E o 11882 VpDA 3v3 VSSA 1024 002aaf959 1 Example of an actual transfer curve 2 The ideal transfer curve 3 Differential linearity error Ep 4 Integral non linearity 5 Center of a step of the actual transfer curve Fig 39 10 bit ADC characteristics LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers Product data sheet Rev 5 1 17 November 2015 NXP B V 2015 All rights reserved 128 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Rysi LPC18xx 1 1 L i Eas 2kO analog pin n ADC1 n 2 2 multiplexed pin ADC COMPARATOR Rs 1 vex Vss 77 002aag697 Rs lt 1 7 x feik apc Cia 2 Fig 40 ADC interface to pins Table 38 DAC characteristics VppA ava Over specified ranges Tamb 40 C to 105 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Ep differential linearity error 2 7 V Vppa ava 3 6 V j 0 8 LSB 2 4 V lt 2 7 V 1 0 LSB Ei agi integral non linearity code 0 to 975 n 1 0 LSB 2 7 V lt Vppa ava 3 6 V 2 4 V lt Vppa ava lt 2 7 V 1 5 LSB Eo offset error
83. 55 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 4 Ordering information Table 1 Ordering information Type number Package Name Description Version LPC1857FET256 LBGA256 Plastic low profile ball grid array package 256 balls body 17 17 x 1 mm SOT740 2 LPC1857JET256 LBGA256 Plastic low profile ball grid array package 256 balls body 17 x 17 x 1 mm SOT740 2 LPC1857JBD208 LQFP208 Plastic low profile quad flat package 208 leads body 28 x 28 x 1 4 mm SOT459 1 LPC1853FET256 LBGA256 Plastic low profile ball grid array package 256 balls body 17 x 17 x 1 mm SOT740 2 LPC1853JET256 LBGA256 _ Plastic low profile ball grid array package 256 balls body 17 x 17 x 1 mm SOT740 2 LPC1853JBD208 LQFP208 Plastic low profile quad flat package 208 leads body 28 x 28 x 1 4 mm SOT459 1 LPC1837FET256 LBGA256 Plastic low profile ball grid array package 256 balls body 17 x 17 x 1 mm SOT740 2 LPC1837JET256 LBGA256 Plastic low profile ball grid array package 256 balls body 17 x 17 x 1 mm SOT740 2 LPC1837JBD144 LQFP144 Plastic low profile quad flat package 144 leads body 20 x 20 x 1 4 mm SOT486 1 LPC1837JET100 TFBGA100 Plastic thin fine pitch ball grid array package 100 balls body 9 x 9 x 0 7 mm SOT926 1 LPC1833FET256 LBGA256 Plastic low profile ball grid array package 256 balls body 17 x 17 x 1 mm S
84. 5x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name TFBGA100 LQFP144 Reset state 1 Type Description PF_9 LBGA256 LQFP208 3 5 UZ c R Function reserved UO DIR RS 485 EIA 485 output enable direction control for USARTO CTOUT 1 SCTimer PWM output 1 Match output 3 of timer 3 R Function reserved GPIO7 23 General purpose digital input output pin R Function reserved R Function reserved R Function reserved ADC1 2 ADC1 and ADCO input channel 2 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC PF 10 205 PU R Function reserved UO TXD Transmitter output for USARTO R Function reserved R Function reserved GPIO7 24 General purpose digital input output pin R Function reserved SD WP SD MMC card write protect input R Function reserved ADCO 5 ADCO ADC1 input channel 5 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC PF 11 A2 207 PU R Function reserved UO RXD Receiver input for USARTO R Function reserved R Function reserved GPIO7 25 General purpose digital input output pin R Fu
85. 6 7 ns time tha data output hold SPI mode 1 7 E ns time tlead lead time continuous transfer mode Toy clk 3 3 Toy clk 8 2 ns SPI mode CPOL 0 CPHA 0 SPI mode CPOL 0 0 5 x Tey ck 3 3 0 5 x Toyo 8 2 ns CPHA 1 SPI mode CPOL 1 Toy clk 3 3 Toy clk 8 2 ns CPHA 0 SPI mode CPOL 1 0 5 x Toy clk 3 3 l 0 5 x Tey clk 8 2 ins CPHA 1 synchronous serial 0 5 x 3 3 0 5 x Teyck 8 2 ns frame mode microwire frame format Toy clk 3 3 Toy clk 8 2 ns tlag lag time continuous transfer mode 0 5 x z ns SPI mode CPOL 0 CPHA 0 SPI mode CPOL 0 Toy clk ns CPHA 1 SPI mode CPOL 1 0 5 x Tey clk ns CPHA 0 SPI mode CPOL 1 Toy clk ns CPHA 1 synchronous serial Toy clk ns frame mode microwire frame format 0 5 Toy clk ns LPC185X_3X_2X_1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 112 of 155 LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller NXP Semiconductors Table 27 Dynamic characteristics SSP pins in SPI mode Tamb 40 C to 105 C 2 4 V lt Vpp REG 3V3 S3 6V 2 7Vs VppvI0 lt 8 6 V 20 pF sampled at 10 and 90 of the signal level EHS 1 for all pins Simulated values Symbol Paramete
86. 61 Vi input voltage on pins USBO DP USBO DM USBO VBUS Vpp lo 224V 0 5 5 V 0 V 0 3 6 V Rpa pull down resistance on pin USBO_VBUS 48 64 80 kQ Vic common mode input high speed mode 50 200 500 mV voltage full speed low speed 800 2500 mV mode chirp mode 50 600 mV Vi dit differential input voltage 100 400 1100 mV USB1 pins USB1 DP USB1 DM 6 loz OFF state output 0V Vi 33V 16 10 uA current LPC185X_3X_2X_1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 92 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 11 Static characteristics continued Tamb 40 C to 105 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit VBus bus supply voltage 17 5 25 V Vpi differential input D D 0 2 V sensitivity voltage VcM differential common includes range 0 8 2 5 V mode voltage range Vith rs se single ended receiver 0 8 5 2 0 V switching threshold voltage VoL LOW level output of 1 5 to 3 6 V 0 18 V voltage for low full speed Vou HIGH level output R of 15 to GND 2 8 3 5 V voltage driven for low full speed Cirans transceiver capacitance pin to GND 20 pF ZpRv driver output with 33 Q series resi
87. 822JET100 512kB 512kB 104kB no yes no 4 J 49 LPC1817JBD144 1MB 512kB 512 4136kB no no no yes 8 J 83 LPC1817JET100 1 MB 512kB 512 4136kB no no no no no 4 J 49 LPC1815JBD144 768 kB 384kB 384 136 no no no yes 8 J 83 LPC1815JET100 768kB 384 384 136 no no no no no 4 J 49 LPC1813JBD144 512kB 256 256kB 104kB no no no yes 8 J 83 LPC1813JET100 512kB 256 256 104 no no 4 J 49 LPC1812JBD144 512kB 512kB 104 no no no yes 8 J 83 LPC1812JET100 512kB 512kB 104 no no 4 J 49 1 J 40 C to 105 C F 40 to 85 LPC185X_3X_2X_1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 5 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 5 Block diagram SWD TRACE PORT JTAG LPC185x 3x 2x 1x 64 kB ROM 32 kB LOCAL SRAM 40 kB LOCAL SRAM TEST DEBUG INTERFACE ETHERNET 32 kB AHB SRAM 10 100 usB1 1 MAC HOST LCD 1 SD 16 kB ARM IEEE 1588 DEVICE MMC 16 kB AHB SRAM CORTEX M3 16 kB EEPROM 512 256 kB FLASH A masters 512 256 kB FLASH B I slaves a BRIDGE EMC HS GPIO C 9 ALARM TIMER SCT BACKUP REGISTERS POWER MODE CONTRO
88. 85 mode e USARTS includes an IrDA mode to support infrared communication All USARTs have DMA support Support for synchronous mode at a data bit rate of up to 8 Mbit s e Smart card mode conforming to 1507816 specification 7 16 3 SSP serial I O controller LPC185X 3X 2X 1X Remark The LPC185x 3x 2x 1x contain two SSP controllers The SSP controller can operate on a SPI 4 wire SSI or Microwire bus It can interact with multiple masters and slaves on the bus Only a single master and a single slave can communicate on the bus during a given data transfer The SSP supports full duplex All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 74 of 155 NXP Semiconductors LPC185x 3x 2x 1x 7 16 3 1 7 16 4 7 16 4 1 7 16 5 LPC185X 3X 2X 1X 32 bit ARM Cortex M3 microcontroller transfers with frames of 4 bit to 16 bit of data flowing from the master to the slave and from the slave to the master In practice often only one of these data flows carries meaningful data Features Maximum SSP speed in full duplex mode of 25 Mbit s for transmit only 50 Mbit s master and 15 Mbit s slave Compatible with Motorola SPI 4 wire Texas Instruments SSI and National Semiconductor Microwire buses Synchronous serial communication Master or slave operation Eight frame FIFOs for both transmit and
89. 85x and LPC183x Ethernet is not available on parts LPC182x and LPC181x Features 10 100 Mbit s DMA support Power management remote wake up frame and magic packet detection Supports both full duplex and half duplex operation Supports CSMA CD Protocol for half duplex operation Supports IEEE 802 3x flow control for full duplex operation Optional forwarding of received pause control frames to the user application in full duplex operation Back pressure support for half duplex operation Automatic transmission of zero quanta pause frame on deassertion of flow control input in full duplex operation Support for IEEE 1588 time stamping and IEEE 1588 advanced time stamping IEEE 1588 2008 v2 Digital serial peripherals UART Remark The LPC185x 3x 2x 1x contain one UART with standard transmit and receive data lines UART1 also provides a full modem control handshake interface and support for RS 485 9 bit mode allowing both software address detection and automatic address detection using 9 bit mode UART1 includes a fractional baud rate generator Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 73 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller
90. A6 28 41 B JTAG interface control signal Also used for boundary scan use the part in functional mode connect this pin in one of the following ways Leave DBGEN open The DBGEN pin is pulled up internally by a 50 resistor Tie DBGEN to VDDIO Pull DBGEN up to VDDIO with an external pull up resistor TCK SWDCLK J5 H2 27 38 B I Test Clock for JTAG interface default or Serial Wire SW clock TRST M4 B4 29 42 2l Test Reset for JTAG interface TMS SWDIO K6 C4 30 44 Test Mode Select for JTAG interface default or SW debug data input output TDO SWO K5 31 46 B Test Data Out for JTAG interface default SW trace output TDI J4 G3 26 35 1 Test Data In for JTAG interface USBO pins USBO_DP F2 E1 18 26 Bl l O USBO bidirectional D line Do not add an external series resistor USBO DM G2 2 20 28 l l O USBO bidirectional D line Do not add an external series resistor USBO VBUS F1 21 29 8 VBUS pin power on USB cable This pin includes an internal 7 pull down resistor of 70 typical 30 USBO ID H2 F1 22 30 Bl l Indicates to the transceiver whether connected as an A device USBO ID LOW or B device USBO ID HIGH For use with OTG this pin has an internal pull up resistor USBO RREF H1 F3 24 32 HB 12 0 kO accuracy 1 96 on board resistor to ground for current reference USB1 pins USB1 DP F12 9 89 129 B l USB1 bidirectional D line A
91. B LCDM LCDM LCDM LCDM LCDM LCD_FP P4_5 LCDFP P4 5 LCDFP P4 5 LCDFP P4 5 LCDFP LCD DCLK P4 7 LCDDCLK P4 7 LCDDCLK P4 7 LCDDCLK 4 7 LCDDCLK LCD LE P7 0 LCDLE P7 0 LCDLE P7 0 LCDLE P7 0 LCDLE LCD PWR 7 7 LCDPWR P7 7 LCDPWR P77 LCDPWR P77 LCDPWR GP_CLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN LPC185X_3X_2X_1X 13 2 Crystal oscillator The crystal oscillator is controlled by the XTAL_OSC_CTRL register in the CGU see LPC18xx user manual The crystal oscillator operates at frequencies of 1 MHz to 25 MHz This frequency can be boosted to a higher frequency up to the maximum CPU operating frequency by the PLL The oscillator can operate in one of two modes slave mode and oscillation mode n slave mode couple the input clock signal with a capacitor of 100 pF Cc in Figure 41 with an amplitude of at least 200 mV RMS The XTAL2 pin in this configuration can be left unconnected External components and models used in oscillation mode are shown in Figure 42 and in Table 42 and Table 43 Since the feedback resistance is integrated on chip only a crystal and the capacitances Cx1 and Cx2 need to be connected externally in case of fundamental mode oscillation L CL and Rs represent the fundamental frequency Capacitance Cp in Figure 42 represents the parallel package capacitance and must not be larger than 7 pF Parameters Fc CL Rs and CP are supplied by the crystal manufacturer Tabl
92. EEN3 PB_4 GREEN5 PB 4 GREEN4 PB 4 GREEN7 LCD VD14 PB_5 GREEN2 5 GREEN4 PB 5 GREEN3 PB 5 GREEN6 LCD VD13 PB_6 GREEN1 6 GREEN3 PB 6 GREEN2 6 GREEN5 LCD VD12 P8 3 GREENO P8 GREEN2 P8 3 GREEN1 P8 3 GREEN4 LCD VD11 P4 9 GREEN1 P4 9 GREENO P49 GREEN3 LCD_VD10 P4 10 GREENO P4 10 intensity P4 10 GREEN2 LCD VD9 P4 8 GREEN1 LCD VD8 l P7 5 GREENO LCD VD7 P8 4 RED3 P8 4 RED4 P8 4 RED4 P8 4 RED7 LCD VDe P8 5 RED2 P8 5 RED3 P8_5 RED3 P8_5 RED6 LCD VD5 P86 RED1 P8 6 RED2 P8 6 RED2 P8 6 RED5 LCD VD4 P8 7 REDO P8 7 RED1 8_7 RED1 8_7 RED4 LCD VD3 l P4 2 REDO P4 2 REDO P4 2 RED3 LCD VD2 P4 3 intensity P4 3 RED2 LCD VD1 P4 4 RED1 LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 131 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 41 LCD panel connections for TFT panels External TFT 12 bit 4 4 4 TFT 16 bit 5 6 5 mode 16 bit 1 5 5 5 mode TFT 24 bit pin mode LPC18xx LCD LPC18xx LCD LPC18xxpin LCD LPC18xx LCD pin used function used function used function pin used function LCD VDO P4 1 REDO LCD LP P7 6 LCDLP P7 6 LCDLP P7 6 LCDLP P7 6 LCDLP LCD ENAB P4 6 LCDENAB P4 6 LCDENAB P4 6 LCDENAB P4 6 LCDENA
93. EG 3V3 lt 3 6 V 2 7 V lt Vpp i0 lt 3 6 V 20 pF Simulated values Symbol Parameter Conditions Min Typ Max Unit folk clock frequency on pin LCD_DCLK 50 MHz ta av data output valid 17 ns delay time tha data output hold time 85 ns LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 125 of 155 NXP Semiconductors LPC185x 3x 2x 1x 11 18 SPIFI LPC185X 3X 2X 1X Table 36 Dynamic characteristics SPIFI Tamb 40 C to 105 C 2 4 V lt Vpp REG 3V3 S3 6V 2 7V lt VppvI0 lt 3 6 V C 20 pF Sampled at 90 and 10 of the signal level EHS 1 for all pins Simulated values 32 bit ARM Cortex M3 microcontroller Symbol Parameter Min Max Unit Tey clk clock cycle time 9 6 ns tps data set up time 3 2 ns data hold time 0 ns twa data output valid time 3 2 ns tha data output hold time 0 6 ns SPIFI_SCK SPIFI data out DATA VALID DATAVALID SPIFI data in DATA VALID 002aah409 Fig 38 SPIFI timing Mode 0 All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 126 of 155 NXP Semiconductors LPC185x
94. EMC_CLKn delays CLKO_DELAY CLK1_DELAY CLK2_DELAY CLK3_DELAY 0 Symbol Parameter Min Typ Max Unit Tey clk clock cycle time 8 4 ns Common to read and write cycles ta DYcsv dynamic chip select valid delay time 3 14 0 5 x 5 1 0 5 x NS th DYCS dynamic chip select hold time 0 3 0 5 x Tog 0 9 0 5 x ns ta RASV row address strobe valid delay time 3 14 0 5 x Toa 14 9 0 5 x NS th RAS row address strobe hold time 0 5 0 5 x Toy 1 1 0 5 ns ld CASV column address strobe valid delay time 2 9 0 5 4 6 0 5 x NS th cas column address strobe hold time 0 3 0 5 Toyck 0 9 0 5 ns tawev write enable valid delay time 3 2 0 5 x Toyck 5 9 0 5 x NS th we write enable hold time 1 3 0 5 Toa 1 4 0 5 x Toy ns ta pamoutv DQMOUT valid delay time 3 14 0 5 x 5 0 0 5 x NS DQMOUT hold time 0 2 0 5 Tog 0 8 0 5 ns la Av address valid delay time 3 8 0 5 x Toa 6 3 0 5 Tog NS thia address hold time 0 3 0 5 x Toy 0 9 0 5 ns taickEouTv CKEOUT valid delay time 3 14 0 5 x Tog 5 1 0 5 x NS thicKEouT CKEOUT hold time 0 5 x Toy ctk 0 7 0 5 ns Read cycle parameters tsu D data input set up time 1 5
95. Ethernet MIIM clock P2_1 N15 G7 81 116 PU R Function reserved UO RXD Receiver input for USARTO See Table 4 for ISP mode EMC A12 External memory address line 12 USBO PWR FAULT Port power fault signal indicating overcurrent condition this signal monitors over current on the USB bus external circuitry required to detect over current condition GPIO5 1 General purpose digital input output pin R Function reserved T3 CAP1 Capture input 1 of timer R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 14 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name 2 Description Sie Vs S lt lt 9 lt o a A 3 o e 6G 8 2 2_2 M15 F5 84 121 Bl N R Function reserved PU yo UO UCLK Serial clock input output for USARTO in synchronous mode A11 External memory address line 11 USBO IND1 USBO port indicator LED control output 1 GPIO5 2 General purpose digital input output pin CTIN_6 SC
96. H time Toy clk 0 4 Toy clk x 0 6 ns lcLcx clock LOW time Tey cik 0 4 Toy clk x 0 6 ns 1 Parameters are valid over operating temperature range unless otherwise specified Toy clk 002aag698 Fig 25 External clock timing with an amplitude of at least Vijgus 200 mV LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 105 of 155 NXP Semiconductors LPC185x 3x 2x 1x 11 4 11 5 11 6 LPC185X 3X 2X 1X 32 bit ARM Cortex M3 microcontroller Crystal oscillator Table 19 Dynamic characteristic oscillator Tamb 40 to 105 C over specified ranges 2 4 V lt VppinEay ava lt 3 6 Symbol Parameter Conditions Min Typ 2 Max Unit Low frequency mode 1 20 2 51 lji per period jitter time 5 MHz crystal 31 13 2 ps 10 MHz crystal 6 6 ps 15 MHz crystal 4 8 ps High frequency mode 20 25 MHz 6l lji per period jitter time 20 MHz crystal 3141 4 3 ps 25 MHz crystal 3 7 1 Parameters are valid over operating temperature range unless otherwise specified 2 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages 3 Indicates RMS period jitter 4 PLL induced jit
97. Hz 800 18 pF 18 pF 20 MHz 800 39 pF 39 pF 100 0 47 pF 47 pF LPC1xxx 002aae835 Fig 41 Slave mode operation of the on chip oscillator LPC18xx L XTAL1 XTAL2 CL Op XTAL 4 4 L Rs Cxi Cx2 002aag031 Fig 42 Oscillator modes with external crystal model used for Cy4 Cx2 evaluation All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 133 of 155 NXP Semiconductors LPC185x 3x 2x 1x 13 3 13 4 13 5 LPC185X 3X 2X 1X 32 bit ARM Cortex M3 microcontroller RTC oscillator In the RTC oscillator circuit only the crystal and the capacitances Crtcx and Crtcxe need to be connected externally Typical capacitance values for Cgrcx and are Catcxt 2 20 typical 4 pF An external clock can be connected to RTCX1 if RTCX2 is left open The recommended amplitude of the clock signal is Viigws 100 mV to 200 mV with a coupling capacitance of 5 pF to 10 pF LPC18xx RTCX1 RTCX2 XTAL i CRTCX1 CRTOX2 002aah066 Fig 43 RTC 32 kHz oscillator circuit XTAL and RTCX Printed Circuit Board PCB layout guidelines Connect the crystal on the PCB as close as possible to the oscillator input and output pins of the chip Take care that the load capacitors Cx4 Cx2 and in case of thi
98. L TIMER2 10 bit ADCO CONFIGURATION REGISTERS 10 bit ADC1 EVENT ROUTER OTP MEMORY RTC OSC 12 MHz IRC EVENT MONITOR RTC POWER DOMAIN connected to DMA 002aah225 1 Not available on all parts See Table 2 Fig 1 LPC185x 3x 2x 1x block diagram LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 6 of 155 NXP Semiconductors LPC185x 3x 2x 1x 6 Pinning information 32 bit ARM Cortex M3 microcontroller 6 1 Pinning LPC185x 3xFET256 ball A1 index area 2 4 6 8 10 12 14 16 1 3 5 7 9 11 13 15 002aag541 Transparent top view Fig 2 Pin configuration LBGA256 package ball A1 index area LPC183x 2x 1xFET100 123 4 6 6 T 8 9 10 OOOOOOOOO QOODOOOOGO OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO OQOOOOOOO0O OOOOOOOOO c T0mmooucmx 002aah356 Transparent top view Fig 3 Pin configuration TFBGA100 package LPC1857 53FBD208 002aag543 Fig 4 Pin configuration LQFP208 package LPC183x 2x 1xFBD144 O 002aah357 Fig5 Pin configuration LQFP144 package 6 2 Pin description On the LPC185x 3x 2x 1x digital pins are grouped into 16 ports named PO to P9 and PA to PF with up to 20 pins used per port Each digital
99. LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 48 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name 2 Description 3 8 5 3 amp z lo Eee f PE 7 F15 149 21 N R Function reserved PU CTOUT 5 SCTimer PWM output 5 Match output 3 of timer 3 U1_CTS Clear to Send input for UART1 EMC_D26 External memory data line 26 GPIO7 7 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE_8 F14 l 150 BI N R Function reserved PU O CTOUT_4 SCTimer PWM output 4 Match output of timer 3 U1_DSR Data Set Ready input for UART1 D27 External memory data line 27 GPIO7 8 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE 9 E16 152 21 l R Function reserved PU CTIN 4 SCTimer PWM input 4 Capture input 2 of timer 1 U1_DCD Data Carrier Detect input for UART1 EMC_D28 External memory data line 28 GPIO7 9
100. O USBO port indicator LED control output 0 GPIO5 16 General purpose digital input output pin T2 MAT1 Match output 1 of timer 2 R Function reserved R Function reserved Pe 9 J15 F8 97 139 PU GPIO3 5 General purpose digital input output pin R Function reserved R Function reserved DYCSO0 SDRAM chip select 0 R Function reserved T2 MAT2 Match output 2 of timer 2 R Function reserved R Function reserved P6 10 H15 100 142 PU GPIO3 6 General purpose digital input output pin MCABORT Motor control PWM LOW active fast abort R Function reserved EMC_DQMOUT1 Data mask 1 used with SDRAM and static devices R Function reserved R Function reserved R Function reserved R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 28 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name LQFP144 Reset state 1 Type Description LBGA256 Q TFBGA100 6_11 gt LQFP208 2 0 2 c GPIO3 7 General purpose
101. O interrupt GPIO interrupts QEI gt gt peripherals LPC185x 3x 2x 1x APB3 peripherals APB2 peripherals APB1 gt ue reserved high speed GPIO ARM private bus reserved peripheral bit band alias region reserved reserved reserved APB3 peripherals reserved reserved APB1 peripherals reserved APBO peripherals APBO peripherals E i uM reserved clocking reset peripherals RTC domain peripherals reserved AHB peripherals SRAM flash EEPROM memories SPIFI data ROM external memory banks 256 MB memory shadow area LPC185x 3x 2x 1x Memory mapping peripherals 0x4400 0000 0x4010 2000 J 0x400D 0000 APB2 peripherals 0x400B 0000 De d OxFFFF FFFF eA external memories and e 0x6000 0000 0x4200 0000 0x4010 1000 0x4010 0000 0x400F 8000 Ox400F 4000 0x400F 2000 Ox400F 1000 Ox400F 0000 0x400E 0000 0x400C 0000 0x400A 0000 0x4009 0000 0x4008 0000 0 4006 0000 0 4005 0000 Lene 0x4004 0000 0 4001 2000 wo l 0x4000 0000 0x1000 0000 0x0000 0000 clocking reset control peripherals RTC domain peripherals AHB peripherals reserved RGU CCU2 CCU1 CGU 40 9npuooliul9S dXN reserved RTC event monitor OTP controller event router CREG power mode control backup registers alarm timer ethernet reserved EE
102. OT740 2 LPC1833JET256 LBGA256 Plastic low profile ball grid array package 256 balls body 17 x 17 x 1 mm SOT740 2 LPC1833JBD144 10 144 Plastic low profile quad flat package 144 leads body 20 x 20 x 1 4 mm SOT486 1 LPC1833JET100 TFBGA100 Plastic thin fine pitch ball grid array package 100 balls body 9 x 9 x 0 7 mm SOT926 1 LPC1827JBD144 LQFP144 Plastic low profile quad flat package 144 leads body 20 x 20 x 1 4 mm SOT486 1 LPC1827JET100 TFBGA100 Plastic thin fine pitch ball grid array package 100 balls body 9 x 9 0 7 mm SOT926 1 LPC1825JBD144 LQFP144 Plastic low profile quad flat package 144 leads body 20 x 20 x 1 4 mm SOT486 1 LPC1825JET100 TFBGA100 Plastic thin fine pitch ball grid array package 100 balls body 9 x 9 x 0 7 mm SOT926 1 LPC1823JBD144 LQFP144 Plastic low profile quad flat package 144 leads body 20 x 20 x 1 4 mm SOT486 1 LPC1823JET100 TFBGA100 Plastic thin fine pitch ball grid array package 100 balls body 9 x 9 x 0 7 mm SOT926 1 LPC1822JBD144 LQFP144 Plastic low profile quad flat package 144 leads body 20 x 20 x 1 4 mm SOT486 1 LPC1822JET100 TFBGA100 Plastic thin fine pitch ball grid array package 100 balls body 9 x 9 x 0 7 mm SOT926 1 LPC1817JBD144 LQFP144 Plastic low profile quad flat package 144 leads body 20 x 20 x 1 4 mm SOT486 1 LPC1817JET100 TFBGA100 Plastic thin fine pitch ball grid array package 100 balls body 9 x 9 0 7 mm SOT926 1 LPC1815JBD144 LQFP144 Plastic low profile quad flat
103. P B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 45 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name Reset state 1 TFBGA100 LQFP144 Type Description 2 LBGA256 LarFP208 PD 12 2 Function reserved 0 2 c R Function reserved _ 52 LOW active Chip Select 2 signal R Function reserved GPIO6 26 General purpose digital input output pin R Function reserved CTOUT 10 SCTimer PWM output 10 Match output 3 of timer 3 R Function reserved PD 13 14 97 BIN R Function reserved PU CTIN 0 SCTimer PWM input 0 Capture input 0 of timer 0 1 2 8 EMC BLS2 LOW active Byte Lane select signal 2 R Function reserved GPIO6 27 General purpose digital input output pin R Function reserved CTOUT 13 SCTimer PWM output 13 Match output 3 of timer 3 R Function reserved PD 14 R13 99 2 IN a R Function reserved PU R Function reserved EMC_DYCS2 SDRAM chip select 2 R Function reserved GPIO6 28 General purpose digital input output pin R Function reserved CTOUT 11 SCTimer PWM output 11 Match output 3 of timer 2 R F
104. P1 R Function reserved O SD SD MMC reset signal for MMC4 4 card P14 T3 J2 47 64 N I O GPIOO 11 General purpose digital input output pin PU CTOUT_9 SCTimer PWM output 9 Match output 3 of timer 3 R Function reserved EMC_BLSO LOW active Byte Lane select signal 0 USBO INDO USBO port indicator LED control output 0 SSP1 MOSI Master Out Slave in for SSP1 EMC_D15 External memory data line 15 SD_VOLT1 SD MMC bus voltage select output 1 LPC185X_3X_2X_1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 9 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name 2 Description 2 g lt 9 S 2 Ek E Sa o 2 D ee ese P1_5 R5 24 48 65 B IN l O GPIO1 8 General purpose digital input output pin PU CTOUT 10 SCTimer PWM output 10 Match output 3 of timer 3 R Function reserved CS0 LOW active Chip Select 0 signal USBO PWR FAULT Port power fault signal indicating overcurrent condition this signal monitors over current on the USB bus external circuitry required to detect over
105. PC185x 3x 2x 1x LPC185X 3X 2X 1X 11 7 11 8 32 bit ARM Cortex M3 microcontroller GPCLKIN Table 22 Dynamic characteristic GPCLKIN Tamb 25 C 2 4 V lt Vppiggay ava 3 6 V Symbol Parameter Min Typ Max Unit GP CLKIN input frequency 25 MHz pins Table 23 Dynamic characteristic I O pins Tamb 40 C to 105 C 2 7 V x x 3 6 V Symbol Parameter Conditions Min Typ Unit Standard I O pins normal drive strength tr rise time pin configured as output EHS 1 28 4 0 25 ns tr fall time pin configured as output EHS 1 1213 0 9 2 5 ins tr rise time pin configured as output EHS 0 213 4 9 4 3 ns tr fall time pin configured as output EHS 0 23 1 9 4 0 ins tr rise time pin configured as input 4 0 3 1 3 ins fall time pin configured as input A 0 2 1 2 ns 1 0 pins high drive strength tr rise time pin configured as output standard 1215 4 3 7 9 ins drive mode EHD 0 0 tr fall time pin configured as output standard 215 4 7 8 7 ins drive mode EHD 0x0 tr rise time pin configured as output medium 215 3 2 5 7 ns drive mode EHD 0x1 tr fall time pin configured as output medium 215 3 2 5 5 ins drive mode EHD 0x1 tr rise time pin configured as output high drive IIS 2 9 4 9 ns mode EHD 0x2 tr fall time pin
106. PROM controller flash B controller flash A controller reserved LCD USB1 USBO SD MMC 0x4006 0000 0x4005 4000 0x4005 3000 0x4005 2000 0x4005 1000 0x4005 0000 0x4004 7000 0x4004 6000 0x4004 5000 0x4004 4000 0x4004 3000 0x4004 2000 0x4004 1000 0x4004 0000 0x4001 2000 0x4001 0000 0x4000 F000 0x4000 E000 0x4000 D000 0x4000 C000 0x4000 9000 0x4000 8000 0x4000 7000 0x4000 6000 0x4000 5000 0x4000 4000 0x4000 3000 0x4000 2000 0x4000 1000 0x4000 0000 002aag546 19 041u050491UI JJ X91102 WHV 19 6 X 2 6 9819 NXP Semiconductors LPC185x 3x 2x 1x 7 13 7 14 7 14 1 7 15 7 15 1 LPC185X 3X 2X 1X 32 bit ARM Cortex M3 microcontroller One Time Programmable OTP memory The OTP provides 64 bit 256 bit of memory for general purpose use General Purpose I O GPIO The LPC185x 3x 2x 1x provides 8 GPIO ports with up to 31 GPIO pins each Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers Pins may be dynamically configured as inputs or outputs Separate registers allow setting or clearing any number of outputs simultaneously The value of the output register may be read back as well as the current state of the port pins All GPIO pins default to inputs with pull up resistors enabled and input buffer disabled on reset The input buffer must be turned on in the system control block SFS register before the GPIO input c
107. RTS Request to Send output for UART1 Can also be configured to be an RS 485 EIA 485 output enable signal for UART1 ENET_TXD3 Ethernet transmit data 3 MII interface GPIO6 2 General purpose digital input output pin Function reserved R Function reserved SD VOLT1 SD MNC bus voltage select output 1 ADC1 0 ADC1 and ADCO input channel 0 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC PC 4 FA 16 PU R Function reserved USB1 ULPI D4 ULPI link bidirectional data line 4 R Function reserved ENET TX EN Ethernet transmit enable RMII MII interface GPIO6 3 General purpose digital input output pin R Function reserved CAP1 Capture input 1 of timer 3 SD DATO SD MMC data bus line O N PU R Function reserved USB1 ULPI D3 ULP link bidirectional data line 3 R Function reserved ENET TX ER Ethernet Transmit Error MII interface GPIO6 4 General purpose digital input output pin R Function reserved T3 CAP2 Capture input 2 of timer 3 SD DAT1 SD MMC data bus line 1 PC 6 H6 22 N PU R Function reserved USB1 ULPI D2 ULPI link bidirectional data line 2 R Function reserved ENET RXD2 Ethernet receive da
108. Semiconductors LPC185x 3x 2x 1x 7 5 2 7 6 7 7 7 7 1 7 8 LPC185X 3X 2X 1X 32 bit ARM Cortex M3 microcontroller Non Maskable Interrupt NMI Software interrupt generation Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but can have several interrupt flags Individual interrupt flags can also represent more than one interrupt source Event router The event router combines various internal signals interrupts and the external interrupt pins WAKEUPT 3 0 to create an interrupt in the NVIC if enabled In addition the event router creates a wake up signal to the ARM core and the CCU for waking up from Sleep Deep sleep Power down and Deep power down modes Individual events can be configured as edge or level sensitive and can be enabled or disabled in the event router The event router can be battery powered The following events if enabled in the event router can create a wake up signal from sleep deep sleep power down and deep power down modes and or create an interrupt e External pins WAKEUPO 1 2 3 and RESET Alarm timer RTC 32 kHz oscillator running The following events if enabled in the event router can create a wake up signal from sleep mode only and or create an interrupt WWDT BOD interrupts e C_CANO 1 and interrupts e Ethernet USBO USB1 signals e Selected outputs of combined timers SCTimer PWM and timer0 1 3 Remark Any interrup
109. T256 512kB 256kB 256kB 136kB yes yes yes yes yes yes yes 8 F 164 LPC1853JET256 512kB 256 256kB 136 yes yes yes yes yes 8 J 164 LPC1853JBD208 512kB 256 256 136 yes yes yes yes yes 8 J 142 LPC1837FET256 1 MB 512kB 512 4136kB yes yes yes yes yes yes 8 F 164 LPC1837JET256 1 MB 512kB 512 4136kB yes lyes yes yes yes 8 J 164 LPC1837JBD144 1 MB 512kB 512 4136kB yes yes yes yes es no 8 J 83 LPC1837JET100 1 512kB 512 136kB yes yes yes no no 4 J 49 LPC1833FET256 512kB 256 256kB 136 yes yes yes yes yes 8 F 164 LPC1833JET256 512kB 256kB 256kB 136 yes lyes yes yes yes 8 J 164 LPC1833JBD144 512kB 256 256kB 136 yes yes yes yes es no 8 J 83 LPC1833JET100 512kB 256 256kB 136kB yes yes yes no no 4 49 LPC1827JBD144 1 MB 512kB 512 4136kB no yes no no yes 8 J 83 LPC1827JET100 1 MB 512kB 512 136 no yes no 4 J 49 LPC1825JBD144 768 kB 384kB 384 136 no yes no no yes 8 J 83 LPC1825JET100 768kB 384 384 136 no yes jno no no 4 49 LPC1823JBD144 512kB 256 256 104 no yes yes 8 J 83 LPC1823JET100 512kB 256kB 256 104kB no yes no 4 J 49 LPC1822JBD144 512kB 512kB 104kB no yes no no yes 8 J 83 LPC1
110. Timer PWM input 6 Capture input 1 of timer 3 T3_CAP2 Capture input 2 of timer 3 CS1 LOW active Chip Select 1 signal P2 3 J12 08 87 127 BI N R Function reserved PU 12C1_SDA 2C1 data input output this pin does not use a specialized I C TXD Transmitter output for USART3 See Table 4 for ISP mode CTIN 1 SCTimer PWM input 1 Capture input 1 of timer 0 Capture input 1 of timer 2 GPIOB 3 General purpose digital input output pin R Function reserved 3 MATO Match output 0 of timer USBO0 PPWR VBUS drive signal towards external charge pump or power management unit indicates that VBUS must be driven active HIGH Add a pull down resistor to disable the power switch at reset This signal has opposite polarity compared to the USB PPWR used on other NXP LPC parts P2 4 Kt1 D9 88 128 BI N l Function reserved PU yo 12C1_SCL I C1 clock input output this pin does not use a specialized I C U3 RXD Receiver input for USART3 See Table 4 for ISP mode CTIN 0 SCTimer PWM input 0 Capture input 0 of timer 0 1 2 3 GPIO5 4 General purpose digital input output pin R Function reserved 3 MAT1 Match output 1 of timer USBO PWR FAULT Port power fault signal indicating overcurrent condition this signal monitors over current on the USB bus external circuitry required to detect
111. able EEPROM memory The EEPROM memory is divided into 128 pages The user can access pages 1 through 127 Page 128 is protected Boot ROM The internal ROM memory is used to store the boot code of the LPC 185x 3x 2x 1x After a reset the ARM processor will start its code execution from this memory The boot ROM memory includes the following features The ROM memory size is 64 kB Supports booting from external static memory such as NOR flash SPI flash quad SPI flash USBO and USB1 Includes API for OTP programming Includes a flexible USB device stack that supports Human Interface Device HID Mass Storage Class MSC and Device Firmware Upgrade DFU drivers The default boot source is the flash memory Several other boot modes are available if P2_7 is LOW on reset depending on the values of the OTP bits BOOT_SRC If the OTP memory is not programmed or the BOOT bits are all zero the states of the boot pins P2 9 2 8 P1 2 andP1 1 determine the boot mode Table 4 Boot mode when OTP BOOT bits are programmed Boot mode BOOT SRC BOOT SRC BBOOT SRC BOOT_SRC Description bit 3 bit 2 bit 1 bit 0 Pin state 0 0 0 0 The reset state of P1 1 P1 2 P2 8 and P2 9 pins determines the boot source See Table 5 USARTO 0 0 0 1 Enter ISP mode using USARTO functions on pins P2_0 and P2 1 SPIFI 0 0 1 0 Boot from Quad SPI flash connected to the SPIFI interface using pins P3 3 to P3 8 EMC 8 bit 0
112. al level 5 The drive modes are configured in the system control block in the SFSP registers using the EHD bit See the LPC18xx user manual 11 9 I C bus Table 24 Dynamic characteristic I2C bus pins Tamb 40 to 105 C 24V lt Vpp REG 3V3 lt 3 6 Symbol Parameter Conditions Min Max Unit fscL SCL clock frequency Standard mode 0 100 kHz Fast mode 0 400 kHz Fast mode Plus 0 1 MHz tr fall time of both SDA and 300 ns SCL signals Standard mode Fast mode 20 0 1 x Og 300 ns Fast mode Plus 120 ns LOW period of the SCL clock Standard mode 4 7 us Fast mode 1 3 us Fast mode Plus 0 5 us tHIGH HIGH period of the SCL clock Standard mode 4 0 us Fast mode 0 6 us Fast mode Plus 0 26 us tHD DAT data hold time 213171 Standard mode 0 us Fast mode 0 us Fast mode Plus 0 us tsu DAT data set up time 8119 Standard mode 250 ns Fast mode 100 ns Fast mode Plus 50 ns 1 Parameters are valid over operating temperature range unless otherwise specified See the I C bus specification UM10204 for details 2 tHD DAT is the data hold time that is measured from the falling edge of SCL applies to data in transmission and the acknowledge 3 device must internally provide a hold time of at least 300 ns for the SDA signal with respect to the Vj4 min of the SCL signal to bridge the undefined region of the fal
113. al to the SCTimer PWM but the last three can use match conditions from either counter All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 67 of 155 NXP Semiconductors LPC185x 3x 2x 1x 7 15 1 1 32 bit ARM Cortex M3 microcontroller Clock selection Inputs Events Outputs Interrupts Features Two 16 bit counters or one 32 bit counter Counters clocked by bus clock or selected input Up counters or up down counters State variable allows sequencing across multiple counter cycles The following conditions define an event a counter match condition an input or output condition a combination of a match and or and input output condition in a specified state Events control outputs interrupts and DMA requests Match register 0 can be used as an automatic limit Inbi directional mode events can be enabled based on the count direction Match events can be held until another qualifying event occurs Selected events can limit halt start or stop a counter Supports 8 inputs 16 outputs 16 match capture registers 16 events 32 states Match register 0 to 5 support a fractional component for the dither engine 7 15 2 General Purpose DMA The DMA controller allows peripheral to memory memory to peripheral peripheral to peripheral and memory to memory transactions
114. alid RMII MII interface P1 17 M8 H10 66 93 PU 1 0 GPIOO 12 General purpose digital input output pin 1 0 U2_UCLK Serial clock input output for USART2 in synchronous mode R Function reserved MDIO Ethernet MIIM data input and output TO CAP3 Capture input 3 of timer 0 CAN1 TD CAN1 transmitter output R Function reserved R Function reserved P1 18 N12 J10 67 95 N PU GPIOO 13 General purpose digital input output pin U2 DIR RS 485 EIA 485 output enable direction control for USART2 R Function reserved ENET TXDO Ethernet transmit data 0 RMII MII interface TO MATS Match output 3 of timer 0 CAN1 RD CANI receiver input R Function reserved EMC D10 External memory data line 10 P1 19 K9 68 96 PU ENET TX CLK ENET REF CLK Ethernet Transmit Clock MII interface or Ethernet Reference Clock RMII interface SSP1 SCK Serial clock for SSP1 R Function reserved R Function reserved CLKOUT Clock output pin R Function reserved 12S0_RX_MCLK 125 receive master clock 1 0 12S1_TX_SCK Transmit Clock It is driven by the master and received by the slave Corresponds to the signal SCK in the S bus specification LPC185X 3X 2X 1X All information
115. an be read Features Accelerated GPIO functions GPIO registers are located on the AHB so that the fastest possible I O timing can be achieved Mask registers allow treating sets of port bits as a group leaving other bits unchanged All GPIO registers are byte and half word addressable Entire port value can be written in one instruction Bit level set and clear registers allow a single instruction set or clear of any number of bits in one port Direction control of individual bits e Up to eight GPIO pins can be selected from all GPIO pins to create an edge or level sensitive GPIO interrupt request Two GPIO group interrupts can be triggered by any pin or pins in each port AHB peripherals State Configurable Timer PWM SCTimer PWM subsystem The SCTimer PWM allows a wide variety of timing counting output modulation and input capture operations The inputs and outputs of the SCTimer PWM are shared with the capture and match inputs outputs of the 32 bit general purpose counter timers The SCTimer PWM can be configured as two 16 bit counters or a unified 32 bit counter In the two counter case in addition to the counter value the following operational elements are independent for each half State variable Limit halt stop and start conditions Values of Match Capture registers plus reload or capture control values In the two counter case the following operational elements are glob
116. anism to suspend and resume serial transfer The l C bus can be used for test and diagnostic purposes All 12 controllers support multiple address recognition and a bus monitor mode 125 interface Remark The LPC185x 3x 2x 1x contain two 125 interfaces All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 75 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller The 125 provides a standard communication interface for digital audio applications The S bus specification defines a 3 wire serial bus using one data line one clock line and one word select signal The basic 125 connection has one master which is always the master and one slave The I S bus interface provides a separate transmit and receive channel each of which can operate as either a master or a slave 7 16 5 1 Features The interface has separate input output channels each of which can operate in master or slave mode Capable of handling 8 bit 16 bit and 32 bit word sizes Mono and stereo audio data supported The sampling frequency can range from 16 kHz to 192 kHz 16 22 05 32 44 1 48 96 192 kHz Support for an audio master clock e Configurable word select period in master mode separately for I2S bus input and output Two 8 word FIFO data buffers are provided one for tran
117. ansmit master clock SSPO SCK Serial clock for SSPO R Function reserved R Function reserved R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 18 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name 2 Description S lt 9 3 8 Ek EIL i eae P3 1 G11 F7 114 163 l IN 12S0_TX_WS Transmit Word Select It is driven by the PU master and received by the slave Corresponds to the signal WS in the S bus specification lO 12S0_RX_WS Receive Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the S bus specification CANO_RD CAN receiver input USB1_IND1 USB1 Port indicator LED control output 1 GPIO5 8 General purpose digital input output pin R Function reserved VD15 LCD data R Function reserved 2 F11 G6 116 166 PI OL I O 1250 TX SDA 125 transmit data It is driven by the PU transmitter and read by the receiver Corresponds to the signal SD in the S bus specification lO 1250 SDA 1
118. ated in Table 11 Static characteristics for the following conditions Active mode CCLK 12 MHz Ipp aeGy ava changed from 9 3 mA to 10 mA Active mode CCLK 60 MHz Ipp REGy ava changed from 26 mA to 28 mA Active mode CCLK 120 MHz Ipp nEay sva changed from 46 mA to 51 mA Active mode CCLK 180 MHz Ipp nEay sva changed from 66 mA to 74 mA Sleep mode CCLK 12 MHz Ipp REG ava changed from 6 2 mA to 8 8 mA Figure 10 to Figure 13 updated General purpose OTP size corrected LPC185X 3X 2X 1X v 4 20121031 Preliminary data sheet Modifications Removed TFBGA180 package Parts LPC183x LPC182x and LPC181x added LQFP144 and TFBGA100 packages added e T2105 C data added in Figure 19 to Figure 22 e Changed symbol names and parameter names in Table 21 e Parameter updated for condition V 5 V and Tamb 25 C 105 C in Table 11 Power consumption data added in Section 10 1 LPC1857 53 v 3 2 Modifications SPIFI dynamic characteristics added in Section 11 16 IRC accuracy corrected to 2 for Tamb 40 C to 0 C and Tamb 85 C to 105 C Pull up and Pull down current data Figure 23 and Figure 24 updated with data for Tamb 105 C e SCT dither engine added SCT bi directional event enable features added See Section 7 15 1 SPIFI maximum data rate changed to 52 MB per second e Recommendation for Vgar use added The recommended operating co
119. ation provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 145 of 155 NXP Semiconductors LPC185x 3x 2x 1x 16 Abbreviations 32 bit ARM Cortex M3 microcontroller LPC185X 3X 2X 1X Table 44 Abbreviations Acronym Description ADC Analog to Digital Converter AHB Advanced High performance Bus APB Advanced Peripheral Bus API Application Programming Interface BOD BrownOut Detection BGA Ball Grid Array CAN Controller Area Network CMAC Cipher based Message Authentication Code CSMA CD Carrier Sense Multiple Access with Collision Detection DAC Digital to Analog Converter DMA Direct Memory Access EOP End Of Packet ETB Embedded Trace Buffer ETM Embedded Trace Macrocell GPIO General Purpose Input Output IRC Internal RC IrDA Infrared Data Association JTAG Joint Test Action Group LCD Liquid Crystal Display LSB Least Significant Bit LQFP Low Quad Flat Package MAC Media Access Control MCU MicroController Unit MIIM Media Independent Interface Management n c not connected OTG On The Go PHY PHYsical layer PLL Phase Locked Loop PWM Pulse Width Modulator RMII Reduced Media Independent Interface SDRAM Synchronous Dynamic Random Access Memory SPI Serial Peripheral Interface SSI Serial Synchr
120. bit ARM Cortex M3 microcontroller Fig 18 002aah379 100 a IBAT pA 80 60 40 20 0 4 0 2 0 0 2 0 6 0 4 VBar Vpp REG 3v3 V Conditions Vpp REG 3V3 3 0 V Vgar 2 6 V to 3 6 V CCLK 12 MHz Remark The recommended operating condition for the battery supply is Vpp REGy3v3 gt Vgar 0 2 V Typical battery supply current in Active mode 10 2 Peripheral power consumption The typical power consumption at T 25 C for each individual peripheral is measured as follows 1 Enable all branch clocks and measure the current Ipp REG 3v3 2 Disable the branch clock to the peripheral to be measured and keep all other branch clocks enabled 3 Calculate the difference between measurement 1 and 2 The result is the peripheral power consumption Table 12 Peripheral power consumption Peripheral Branch clock Ipp REGy 3v3 in mA Branch clock Branch clock frequency 48 MHz frequency 96 MHz I2C1 _ 1261 0 01 0 01 1260 CLK APB1 1260 0 01 0 02 DAC CLK APBS3 DAC 0 01 0 02 ADCO CLK APB3 ADCO 0 07 0 07 ADC1 CLK APB3 ADC1 0 07 0 07 CANO CLK APB3 CANO 0 17 0 17 CAN1 CLK APB1 CAN1 0 16 0 15 MOTOCON CLK_APB1_MOTOCON 0 04 0 04 125 APB1 125 0 09 0 08 CLK_SPIFI 1 14 2 29 CLK_M3_SPIFI GPIO CLK_M3_GPIO 0 72 1 43 LPC185X_3X_2X_1X All informatio
121. ch output 3 of timer 3 R Function reserved LCD_VD16 LCD data LCD_VD4 LCD data 0 Trace data bit 0 R Function reserved R Function reserved ADCO 4 ADCO and ADC1 input channel 4 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 30 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name TFBGA100 LQFP144 LQFP208 Reset state 1 Type Description gt LBGA256 P7_5 1 wo wo 5 0 2 13 General purpose digital input output pin CTOUT_12 SCTimer PWM output 12 Match output 3 of timer 3 R Function reserved LCD VD8 LCD data LCD_VD23 LCD data 1 Trace data bit 1 R Function reserved R Function reserved 3 ADCO and ADC1 input channel Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC P7 6 C7 134 194 121 IN PU GPIO3 14 General purpose digital inp
122. conductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 002aah410 1 6 IDD REG 3V3 mA 1 2 0 8 0 4 40 0 40 80 120 temperature C Conditions Vpp REG 3V3 Vpb o 3 3 V Fig 14 Typical supply current versus temperature Deep sleep mode 002aah412 300 IDD REG 3V3 pA 240 180 120 60 40 0 40 80 120 temperature C Conditions VpD REG 3V3 3 3 Fig 15 Typical supply current versus temperature in Power down mode 002aah424 25 Ipp REGy 3v3ylBAT pA 20 15 10 IBAT IDD REG 3V3 40 20 0 20 40 60 80 100 120 temperature C Conditions Vpp REG 3V3 Vpb o 3 3 V Vpp REG 3v3 0 4 V Fig 16 Typical supply current versus temperature in Deep power down mode 002aah415 30 IBAT uA 25 20 40 20 0 20 40 60 80 100 120 temperature C Conditions Vgar 3 6 V Vpb REG 3V3 not present Fig 17 Typical battery supply current versus temperature LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 96 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32
123. conductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name g S 3 Description 8 E S S3 P1 1 R2 K2 42 58 HN GPIOO 8 General purpose digital input output pin External PU boot pin see Table 5 O CTOUT 7 SCTimer PWM output 7 Match output of timer 1 A6 External memory address line 6 R Function reserved R Function reserved SSPO MISO Master In Slave Out for SSPO R Function reserved D13 External memory data line 13 P1 2 R3 43 60 2 IN l O 1 0 9 General purpose digital input output pin External PU boot pin see Table 5 O CTOUT_6 SCTimer PWM output 6 Match output 2 of timer 1 A7 External memory address line 7 R Function reserved R Function reserved SSPO MOSI Master Out Slave in for SSPO R Function reserved 014 External memory data line 14 P1 3 P5 Jf 44 61 N I O GPIOO 10 General purpose digital input output pin PU CTOUT 8 SCTimer PWM output 8 Match output 0 of timer 2 R Function reserved LOW active Output Enable signal USBO IND1 USBO port indicator LED control output 1 SSP1 MISO Master In Slave Out for SS
124. ct the USBn VBUS pins to VBUS on the USB connector The voltage divider ratio should be such that the USB VBUS pin will be greater than 0 7VDDIO to indicate a logic HIGH while below the 3 6 V allowable maximum voltage For the following operating conditions VBUS max 5 25 V VDDIO 3 6 V the voltage divider should provide a reduction of 3 6 V 5 25 V or 0 686 V For bus powered devices a regulator powered by USB can provide 3 3 V to VDDIO whenever bus power is present and ensure that power to the USBn VBUS pins is always present when the 5 V VBUS signal is applied See Figure 47 Remark Applying 5 V to the USBn VBUS pins for a short time while the regulator ramps up might compromise the long term reliability of the part but does not affect its function LPC18xx VDDIO R2 R3 rh USBn VBUS VBUS gt USB B connector aaa 013015 Fig 46 USB interface on a self powered device where USBn VBUS 5 V LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 136 of 155 NXP Semiconductors LPC185x 3x 2x 1x LPC185X 3X 2X 1X 32 bit ARM Cortex M3 microcontroller LPC18xx VDDREG REGULATOR USBn_VBUS VBUS USB B connector aaa 013016 Fig 47 USB i
125. cteristics Ethernet Tamb 40 to 105 C 2 4 V lt Vpp nea ava 3 6 V 2 7 V lt Vopao x 3 6 V Values guaranteed by design Symbol Parameter Conditions Min Max Unit RMII mode folk clock frequency for RX CLK 50 MHz clock duty cycle 50 50 set up time for ENET_TXDn ENET_TX_EN 2 4 ns ENET_RXDn _ DV th hold time for ENET_TXDn ENET_TX_EN 12 2 ns ENET_RXDn _ ENET RX DV MII mode folk clock frequency for TX CLK 25 MHz clock duty cycle 50 50 96 set up time for ENET_TXDn ENET_TX_EN 102 4 ns ENET TX th hold time for ENET_TXDn ENET_TX_EN 12 2 ns ENET TX folk clock frequency for UE 25 MHz clock duty cycle 50 50 tsu set up time for ENET_RXDn ENET_RX_ER 12 4 ns ENET RX DV th hold time for ENET_RXDn ENET_RX_ER mz 2 ns ENET RX DV 1 Output drivers can drive a load 25 pF accommodating over 12 inch of PCB trace and the input capacitance of the receiving device 2 Timing values are given from the point at which the clock signal waveform crosses 1 4 V to the valid input or output level ENET RX CLK ENET TX CLK ENET RXD n ENET RX DV ENET RX ER ENET TXD n ENET TX EN ENET TX ER Fig 36 Ethernet timing 002aag210 LPC185X 3X
126. d Nematic STN displays with 4 bit or 8 bit interfaces Supports single and dual panel color STN displays e Supports Thin Film Transistor TFT color displays Programmable display resolution including but not limited to 320 x 200 320 x 240 640 x 200 640 x 240 640 x 480 800 x 600 and 1024 x 768 Hardware cursor support for single panel displays All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 72 of 155 NXP Semiconductors LPC185x 3x 2x 1x 7 15 9 7 15 9 1 7 16 7 16 1 LPC185X 3X 2X 1X 32 bit ARM Cortex M3 microcontroller 15 gray level monochrome 3375 color STN and 32 K color palettized TFT support e 1 2 or 4 bits per pixel bpp palettized displays for monochrome STN 1 2 4 or 8 bpp palettized color displays for color STN and TFT 16 bpp true color non palettized for color STN and TFT 24 bpp true color non palettized for color TFT Programmable timing for different display panels 256 entry 16 bit palette RAM arranged as a 128 x 32 bit RAM Frame line and pixel clock signals AC bias signal for STN data enable signal for TFT panels Supports little and big endian and Windows CE data formats LCD panel clock can be generated from the peripheral clock or from a clock input pin Ethernet Remark The ethernet controller is available on parts LPC1
127. d mode I C bus system but the requirement tgu par 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line tymax tsu pAr 1000 250 1250 ns according to the Standard mode I C bus specification before the SCL line is released Also the acknowledge timing must meet this set up time tSU DAT 709 SDA is tHD DAT SCL S 1 f SNO OHNE 1 SCL 002aaf425 Fig 26 I C bus pins clock timing 11 10 l S bus interface Table 25 Dynamic characteristics I2S bus interface pins Tamb 40 C to 105 C 24V lt Vpp REG 3V3 8 6V 27Vx Vpp o lt 3 6 V C 20 pF Conditions and data refer 1250 and 1251 pins Simulated values Symbol Parameter Conditions Min Typ Max Unit common to input and output tr rise time 4 ns tr fall time 4 ns twH pulse width HIGH on pins 125 TX SCK 36 ns 125 RX SCK twe pulse width LOW on pins I28Sx TX SCK 36 ns 125 RX SCK output twa data output valid time on pinl2Sx TX SDA H 4 4 ns on pin l28x TX WS 4 3 ns input tsu D data input set up time 25 0 ns on pin l28x RX WS 0 20 ns thio data input hold time on pin l2Sx SDA 3 7 ns on pin l28x RX WS 3 9 ns
128. d time 0 ns twa data output valid time 4 3 24 3 ns All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 110 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller SCLK FES 1 SCLK FES 0 twa TXD START BIT1 RXD aaa 016717 Fig 29 USART timing LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 111 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 11 12 SSP interface Table 27 Dynamic characteristics SSP pins in SPI mode Tamb 40 to 105 C 2 4 V lt Vppiggay ava lt 3 6 V 2 7 V lt Vppiio 3 6 V 20 pF sampled at 10 and 90 of the signal level EHS 1 for all pins Simulated values Symbol Parameter Conditions Min Typ Max Unit SSP master Tey clk clock cycle time full duplex mode 1 25 5 106 S when only transmitting 1 51 108 S tps data set up time in SPI mode 12 2 ns tpH data hold time in SPI mode 3 6 ns tva data output valid in SPI mode
129. dd an external series resistor of 33 2 96 USB1 DM G12 E10 90 130 B l USB1 bidirectional D line Add an external series resistor of 33 2 96 I2C bus pins l2C0_SCL 115 D6 92 132 10 F 1 clock input output Open drain output for I2C bus compliance 1260 SDA 116 E6 93 133 019 F I O I C data input output Open drain output for I2C bus compliance Reset and wake up pins RESET D9 B6 128 185 11 I External reset input A LOW on this pin resets the device causing I O ports and peripherals to take on their default states and processor execution to begin at address 0 This pin does not have an internal pull up LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 56 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name 2 Description eae E lt amp 3 8 EE es ele WAKEUPO A9 4 130 187 UIA I External wake up input can raise an interrupt and can cause wake up from any of the low power modes A pulse with a duration of at least 45 ns wakes up the part Input 0 of the event monitor No internal pull up is enabled when this
130. dically service it within a programmable time window Features Internally resets chip if not periodically reloaded during the programmable time out period Optional windowed operation requires reload to occur between a minimum and maximum time period both programmable Optional warning interrupt can be generated at a programmable time prior to watchdog time out Enabled by software but requires a hardware reset or a watchdog reset interrupt to be disabled Incorrect feed sequence causes reset or interrupt if enabled e Flag indicate watchdog reset Programmable 24 bit timer with internal prescaler All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 78 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Selectable time period from Tcy WDCLk x 256 x 4 to Tcy wDCLk x 224 x 4 in multiples of Tcy WDCLK x 4 The Watchdog Clock WDCLK uses the IRC as the clock source 7 18 Analog peripherals 7 18 1 Analog to Digital Converter Remark The LPC185x 3x 2x 1x contain two 10 bit ADCs All input channels are shared between ADCO and ADC1 7 18 1 1 Features 10 bit successive approximation analog to digital converter Input multiplexing among 8 pins Power down mode Measurement range 0 to VDDA Sampling frequency up to 400 kSamples s Bu
131. digital input output pin R Function reserved R Function reserved EMC CKEOUTO SDRAM clock enable 0 R Function reserved T2_MAT3 Match output 3 of timer 2 R Function reserved R Function reserved P6 12 G15 103 145 121 IN PU GPIO2 8 General purpose digital input output pin CTOUT 7 SCTimer PWM output 7 Match output of timer 1 R Function reserved EMC DQMOUTO Data mask 0 used with SDRAM and static devices R Function reserved R Function reserved R Function reserved R Function reserved P7 0 B16 110 158 PU GPIO3 8 General purpose digital input output pin CTOUT 14 SCTimer PWM output 14 Match output 2 of timer 3 R Function reserved LCD LE Line end signal R Function reserved R Function reserved R Function reserved R Function reserved P7 1 C14 113 162 PU 1 0 GPIO3 9 General purpose digital input output pin CTOUT_15 SCTimer PWM output 15 Match output 3 of timer 3 1250 TX WS Transmit Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the 2S bus specification LCD VD19 LCD data LCD VD7 LCD data R Function reserved U2 TXD Transmitter output fo
132. driven 8 Transparent analog pad Not 5 V tolerant 9 Pad provides USB functions It is designed in accordance with the USB specification revision 2 0 Full speed and Low speed mode only Open drain 5 V tolerant digital I O pad compatible with I2C bus Fast Mode Plus specification This pad requires an external pull up to 10 provide output functionality When power is switched off this pin connected to the I2C bus is floating and does not disturb the 12C lines 11 5 V tolerant pad with 20 ns glitch filter provides digital I O functions with open drain output with weak pull up resistor and hysteresis 12 On the LQFP208 package VPP is internally connected to VDDIO 13 On the LQFP208 package VSSIO and VSS are connected to a common ground plane LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 59 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 7 Functional description LPC185X 3X 2X 1X 7 1 7 2 7 3 Architectural overview The ARM Cortex M3 includes three AHB Lite buses the system bus the I code bus and the D code bus The l code and D code core buses allow for concurrent code and data accesses from different slave ports The LPC185x 3x 2x 1x use a multi layer AHB matrix to connect the ARM Cortex M3 buses and other bus masters to perip
133. duct data sheet Rev 5 1 17 November 2015 22 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Pin name Description TFBGA100 LQFP144 LQFP208 Type 1 LBGA256 Z Reset state P4 6 GPIO2 6 General purpose digital input output pin CTOUT 4 SCTimer PWM output 4 Match output 3 of timer 3 z 0 2 o6 LCD ENAB LCDM STN AC bias drive or TFT data enable input R Function reserved R Function reserved R Function reserved R Function reserved R Function reserved P4 7 H4 14 21 B LCD DCLK LCD panel clock PU GP CLKIN General purpose clock input to the CGU R Function reserved R Function reserved R Function reserved R Function reserved lO 1251 TX SCK Transmit Clock It is driven by the master and received by the slave Corresponds to the signal SCK in the S bus specification lO 1250 TX SCK Transmit Clock It is driven by the master and received by the slave Corresponds to the signal SCK in the S bus specification P4 8 E2 l 15 23 B N l R Function reserved PU CTIN_5 SCTimer PWM input 5 Capture input 2 of timer 2 O LCD_VD9 LCD data R Function reserved GPIO5 12 General purpose digital input output
134. e 1 2 4 3 6 V 3 3 V VDDA 3V3 analog supply voltage pin VDDA 24 3 6 V 3 3 V on pins 3 0 3 3 3 6 V USBO VDDA3V3 _ DRIVER and USBO VDDAS3V3 battery supply voltage 11 2 4 3 6 V Voprog pf polyfuse programming pin VPP for OTP 2 7 3 6 V voltage lorog pt polyfuse programming jon pin VPP OTP 30 mA current programming time lt 1 6 ms Ipp REG 3V3 regulator supply current Active mode code 3 3 V while 1 executed from RAM all peripherals disabled PLL1 enabled CCLK 12 MHz 1 10 mA CCLK 60 MHz 4 28 120 MHz 51 CCLK 180 MHz 74 mA Ipp REG 3V3 regulator supply current all peripherals disabled 3 3 V sleep mode HIIS 8 8 mA deep sleep mode 145 uA power down mode 23 pA deep power down mle 0 05 uA mode deep power down 3 0 uA mode VBAT floating IBAT battery supply current Veat 3 0 V 1 0 1 Vpp REG 3v3 3 3 V IBAT battery supply current Deep power down mode RTC running Vop REGy 3va floating Vear 3 3 V 3 0 uA Vpp REG 3V3 Vear 3 3 V 1 5 uA LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 87 of 155 LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller NXP Semiconductors
135. e master and received by the slave Corresponds to the signal WS the S bus specification 1 0 12S1_TX_WS Transmit Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the 2S bus specification M2 G1 34 50 PU 1 0 GPIOO 1 General purpose digital input output pin SSP1_MOSI Master Out Slave in for SSP1 ENET COL Ethernet Collision detect MII interface R Function reserved R Function reserved R Function reserved ENET TX EN Ethernet transmit enable RMII MII interface I281 TX SDA 1251 transmit data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification P1_0 P2 H1 38 54 PU 1 0 GPIOO 4 General purpose digital input output pin CTIN_3 SCTimer PWM input 3 Capture input 1 of timer 1 5 External memory address line 5 Function reserved R Function reserved SSPO SSEL Slave Select for SSPO R Function reserved 012 External memory data line 12 LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 8 of 155 NXP Semi
136. e 19 R Function reserved l O GPIO6 19 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PD 6 R6 l 68 B N l R Function reserved PU CTOUT_10 SCTimer PWM output 10 Match output 3 of timer 3 D20 External memory data line 20 R Function reserved l O GPIO6 20 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PD 7 T6 72 B N l R Function reserved PU CTIN_5 SCTimer PWM input 5 Capture input 2 of timer 2 D21 External memory data line 21 R Function reserved GPIO6 21 General purpose digital input output pin R Function reserved R Function reserved R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 44 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name TFBGA100 LQFP144 Reset state 1 Type Description 2 LBGA256 3 LQFP208 PD_8 2 0 2 c R Function reserved CTIN 6 SCTimer PWM input 6 Capture input 1 of timer 3 EMC D22 External memory data line 22 R Function reserv
137. e 42 components parameters low frequency mode Recommended values for Cyx y in oscillation mode crystal and external Fundamental oscillation Maximum crystal series External load capacitors frequency resistance Hs Cx2 2 MHz lt 200 0 33 pF 33 pF lt 200 Q 39 pF 39 pF lt 200 0 56 pF 56 pF 4 MHz lt 2009 18 pF 18 pF lt 200 Q 39 pF 39 pF lt 200 0 56 pF 56 pF 8 MHz lt 200 0 18 pF 18 pF lt 200 Q 39 pF 39 pF All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 132 of 155 NXP Semiconductors LPC185x 3x 2x 1x LPC185X 3X 2X 1X 32 bit ARM Cortex M3 microcontroller Table 42 Recommended values for Cx1 x2 in oscillation mode crystal and external components parameters low frequency mode Fundamental oscillation Maximum crystal series External load capacitors frequency resistance Rs Cx 12 MHz 160 0 18 pF 18 pF 1600 39 pF 39 pF 16 MHz 1200 18 pF 18 pF 800 33 pF 33 pF 20 MHz 100 0 18 pF 18 pF 800 33 pF 33 pF Table 43 Recommended values for Cx1 x2 in oscillation mode crystal and external components parameters high frequency mode Fundamental oscillation Maximum crystal series External load capacitors Cx frequency resistance Rs Cx2 15 M
138. e Table 31 Updated Dynamic characteristics SD MMC table See Table 34 Updated Table 2 Motor control PWM instead of PWM Added a remark to Table 31 Updated Table 13 BOD static characteristics 1 Removed BOD interrupt levels 0 and 1 removed Reset levels 0 and 1 They are not applicable LPC185X 3X 2X 1X v 4 1 20140506 Product data sheet LPC185X 3X 2X 1Xv 4 LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 149 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 45 Revision history continued Document ID Release date Data sheet status Change notice Supersedes Modifications e Parameter t e retention time for EEPROM updated in Table 15 e Parameter added for pins USBO_VDDA3V3_DRIVER and USBO VDDASV3 in Table 11 e Parameter name Ipp apc changed to Ippa in Table 11 Minimum wake up time from sleep mode added in Table 16 e Data for Ipp oy added in Table 11 Data sheet status changed to Product data sheet RC specifications corrected in Table 19 Dynamic characteristic IRC oscillator and Section 2 Accuracy changed to 3 over the entire temperature range Bandgap characteristics removed Section 13 7 Suggested USB interface solutions added Ipp REG 3v3 upd
139. e are three levels of the Code Read Protection e In level CRP1 access to the chip via the JTAG is disabled Partial flash updates are allowed excluding flash sector 0 using a limited set of the ISP commanas This level is useful when CRP is required and flash field updates are needed CRP1 does prevent the user code from erasing all sectors e In level CRP2 access to the chip via the JTAG is disabled Only a full flash erase and update using a reduced set of the ISP commands is allowed n level CRP3 any access to the chip via the JTAG pins or the ISP is disabled This mode also disables the ISP override using P2 7 pin If necessary the application code must provide a flash update mechanism using the IAP calls or using the reinvoke ISP command to enable flash update via USARTO See Table 5 CAUTION If level three Code Read Protection CRP3 is selected no future factory testing can be performed on the device 7 21 Emulation and debugging Debug and trace functions are integrated into the ARM Cortex M3 Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions The ARM is configured to support up to eight breakpoints and four watch points LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 84 of 155 NXP Semic
140. ed GPIO6 22 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PD 9 Tib l 84 121 IN PU R Function reserved CTOUT_13 SCTimer PWM output 13 Match output 3 of timer 3 1 0 EMC_D23 External memory data line 23 R Function reserved GPIO6 23 General purpose digital input output Function reserved R Function reserved R Function reserved PD 10 11 86 PU R Function reserved CTIN 1 SCTimer PWM input 1 Capture input 1 of timer 0 Capture input 1 of timer 2 EMC BLS3 LOW active Byte Lane select signal 3 R Function reserved GPIO6 24 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PD 11 N9 88 PU R Function reserved R Function reserved EMC CS3 LOW active Chip Select 3 signal R Function reserved GPIO6 25 General purpose digital input output pin USB1 ULPI DO ULPI link bidirectional data line 0 CTOUT_14 SCTimer PWM output 14 Match output 2 of timer 3 R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NX
141. ed R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 AII rights reserved Product data sheet Rev 5 1 17 November 2015 51 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name TFBGA100 LQFP144 LQFP208 Reset state 1 Type Description LBGA256 E PF 3 2 0 2 c R Function reserved U3 RXD Receiver input for USART3 SSPO MOSI Master Out Slave in for SSPO R Function reserved GPIO7 18 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PF 4 D10 4 120 172 21 OL PU SSP1 SCK Serial clock for SSP1 GP CLKIN General purpose clock input to the CGU TRACECLK Trace clock R Function reserved R Function reserved R Function reserved 1250 TX MCLK 125 transmit master clock 12S0_RX_SCK 125 receive clock It is driven by the master and received by the slave Corresponds to the signal SCK in the S bus specification PF 5 E9 190 PU R Function reserved UCLK Serial clock input output for in synchronous mode SSP1_SSEL Slave Select for SSP1
142. eripheral clocks disabled Fig 11 Typical supply current versus temperature in active mode All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 94 of 155 NXP Semiconductors LPC185x 3x 2x 1x LPC185X 3X 2X 1X 32 bit ARM Cortex M3 microcontroller aaa 013046 100 IDD REG 3V3 a mA 90 C 80 60 40 20 12 36 60 84 108 132 180 156 frequency MHz Conditions active mode entered executing code while 1 from SRAM 3 3 V system PLL enabled IRC enabled all peripherals disabled all peripheral clocks disabled Fig 12 Typical supply current versus core frequency in active mode code executed from SRAM aaa 013047 20 IDD REG 3V3 mA 15 10 40 20 0 20 40 60 80 100 120 temperature C Conditions Vpp REG ava 3 3 V internal pull up resistors disabled system PLL disabled IRC enabled all peripherals disabled all peripheral clocks disabled CCLK 12 MHz Fig 13 Typical supply current versus temperature in sleep mode All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 95 of 155 NXP Semi
143. erty of their respective owners I C bus logo is a trademark of NXP Semiconductors N V For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 153 of 155 NXP Semiconductors LPC185x 3x 2x 1x 21 Contents 32 bit ARM Cortex M3 microcontroller OuRBWD 7 5 1 7 5 2 7 6 7 7 7 7 1 7 8 7 9 7 10 7 11 7 12 7 13 7 14 7 14 1 7 15 7 15 1 7 15 1 1 7 15 2 7 15 2 1 7 15 8 7 15 3 1 7 15 4 7 15 5 7 15 5 1 7 15 6 7 15 6 1 7 15 7 7 15 7 1 7 15 8 7 15 8 1 LPC185X 3X 2X 1X General 1 Features and benefits 1 lt Ordering 4 Ordering 5 Block diagram 6 Pinning 7 PINNING cum Bde TIT 7 Pin description 7 Functional description 60 Architectural overview 60 ARM Cortex M3 60 System Tick timer 60 AHB multilayer
144. es no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 will cause permanent
145. ext transition 18 5 418 5 ns ture receiver jitter for paired transitions 10 to 90 9 9 ns teopri EOP width at receiver must reject as 40 ns EOP see Figure 35 tEoPR2 EOP width at receiver must accept as 1 82 ns EOP see Figure 35 1 Characterized but not implemented as production test Guaranteed by design Remark If only USBO HS USB is used the pins VDDREG and VDDIO can be at different voltages within the operating range but should have the same ramp up time If USB1 FS USB is used the pins VDDREG and VDDIO should be a minimum of 3 0 V and be tied together differential data lines TPERIOD a differential data to crossover point extended eo SEO EOP skew n x TPERIOD tFDEOP Fig 35 Differential data to EOP transition skew and EOP width us source EOP width tFEOPT receiver EOP width teopri 2 002aab561 LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 122 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 32 Static characteristics USBO PHY pins Symbol Parameter Conditions Min Max Unit High speed mode Pons power consumption 2
146. he objective specification for product development Preliminary short data sheet Qualification This document contains data from the preliminary specification Product short data sheet Production This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 19 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the loca
147. herals Flexible connections allow different bus masters to access peripherals that are on different slave ports of the matrix simultaneously ARM Cortex M3 processor The ARM Cortex M3 is a general purpose 32 bit microprocessor which offers high performance and low power consumption The ARM Cortex M3 offers many new features including a Thumb 2 instruction set low interrupt latency hardware division hardware single cycle multiply interruptable continuable multiple load and store instructions automatic state save and restore for interrupts tightly integrated interrupt controller with wake up interrupt controller and multiple core buses capable of simultaneous accesses Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously Typically while one instruction is being executed its successor is being decoded and a third instruction is being fetched from memory The ARM Cortex M3 processor is described in detail in the Cortex M3 Technical Reference Manual System Tick timer SysTick The ARM Cortex M3 includes a system tick timer SYSTICK that is intended to generate a dedicated SYSTICK exception at a 10 ms interval All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 60 of 155 NXP Semiconductors LPC185x 3x 2x 1x 7 4 AHB multilayer matrix 32 bit
148. igh speed controller PLLO accepts an input clock frequency from an external oscillator in the range of 14 kHz to 25 MHz The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator CCO The CCO operates in the range of 4 3 MHz to 550 MHz PLLOAUDIO for audio The audio PLL PLLOAUDIO is a general purpose PLL with a small step size This PLL accepts an input clock frequency derived from an external oscillator or internal IRC The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator CCO A sigma delta converter modulates the PLL divider ratios to obtain the desired All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 81 of 155 NXP Semiconductors LPC185x 3x 2x 1x 7 20 7 7 20 8 7 20 9 LPC185X 3X 2X 1X 32 bit ARM Cortex M3 microcontroller output frequency The output frequency can be set as a multiple of the sampling frequency fs to 32 x fs 64 x fs 128 x fs 256 x fs 384 x fs 512 x fg and the sampling frequency f can range from 16 kHz to 192 kHz 16 22 05 32 44 1 48 96 192 kHz Many other frequencies are possible as well using the integrated fractional divider System PLL1 The PLL1 accepts an input clock frequency from an external oscillator in the range of 1 MHz to 25 MHz The input frequency is multiplied up to a high frequency
149. imer PWM output 15 Match output of timer 3 04 External memory data line 4 R Function reserved R Function reserved R Function reserved lO SD DAT2 SD MMC data bus line 2 LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 11 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name g S 8 Description 8 E S S3 P1 12 R9 K7 56 78 2 N l O GPIO1 5 General purpose digital input output pin PU U1 DCD Data Carrier Detect input for UART1 R Function reserved D5 External memory data line 5 TO_CAP1 Capture input 1 of timer 0 R Function reserved R Function reserved SD_DAT3 SD MMC data bus line P1_13 R10 H8 60 8 GPIO1 6 General purpose digital input output pin PU U1 TXD Transmitter output for UART1 R Function reserved 06 External memory data line 6 TO_CAPO Capture input 0 of timer 0 R Function reserved R Function reserved SD_CD SD MMC card detect input P1_14 R11 J8 61 85 B l O GPIO1 7 General p
150. in the SCU to select the ADC PF_7 B7 193 PU R Function reserved BAUD Baud pin USART3 SSP1_MOSI Master Out Slave in for SSP1 TRACEDATA 2 Trace data bit 2 GPIO7 21 General purpose digital input output pin Function reserved R Function reserved 12S1_TX_WS Transmit Word Select It is driven by the master and received by the slave Corresponds to the signal WS the S bus specification ADC1_7 ADC1 and ADCO input channel 7 or band gap output Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC PF 8 E6 zs PU R Function reserved UO UCLK Serial clock input output for USARTO in synchronous mode CTIN 2 SCTimer PWM input 2 Capture input 2 of timer 0 TRACEDATA S Trace data bit 3 GPIO7 22 General purpose digital input output pin R Function reserved R Function reserved R Function reserved Al ADCO 2 ADCO and ADC1 input channel 2 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 53 of 155 NXP Semiconductors LPC18
151. input 1 1 0 EMC_A21 External memory address line 21 GPIO7 3 General purpose digital input output pin Function reserved R Function reserved R Function reserved PE 4 120 121 IN PU R Function reserved NMI External interrupt input to NMI R Function reserved 1 0 EMC_A22 External memory address line 22 GPIO7 4 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE_5 N16 122 PU R Function reserved CTOUT 3 SCTimer PWM output 3 Match output 3 of timer 0 U1 RTS Request to Send output for UART1 Can also be configured to be an RS 485 EIA 485 output enable signal for UART1 1 0 EMC_D24 External memory data line 24 GPIO7 5 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE 6 M16 124 PU R Function reserved CTOUT 2 SCTimer PWM output 2 Match output 2 of timer 0 U1 RI Ring Indicator input for UART1 1 0 EMC_D25 External memory data line 25 GPIO7 6 General purpose digital input output pin R Function reserved R Function reserved R Function reserved
152. input voltage exceeds Vpp o 15 The parameter value specified is a simulated value excluding bond capacitance 16 For USB operation 3 0 V lt Vpp qoy x 3 6 V Guaranteed by design 17 Vpp 0 present 18 Includes external resistors of 33 O 1 96 on D and D LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 93 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 10 1 Power consumption LPC185X 3X 2X 1X 100 aaa 013045 IDD REG 3V3 mA 80 180 MHz ee SS Ee 60 120 MHz a ee 40 60 MHz 20 12 MHz 0 2 2 2 4 2 6 2 8 3 3 2 3 4 3 6 Vpp REGy 3v3 V Conditions Tamp 25 C executing code while 1 from SRAM system PLL enabled IRC enabled all peripherals disabled all peripheral clocks disabled Fig 10 Typical supply current versus regulator supply voltage Vpp nEc sva in active mode 100 aaa 013044 IDD REG 3V3 mA 80 180 MHz 60 120 MHz 40 60 MHz 20 12 MHz 0 40 20 0 20 40 60 80 100 120 temperature C Conditions Vpp REq 3v3 3 3 V executing code while 1 from SRAM internal pull up resistors disabled system PLL enabled IRC enabled all peripherals disabled all p
153. ions ARM Cortex M3 built in Nested Vectored Interrupt Controller NVIC Non maskable Interrupt NMI input JTAG and Serial Wire Debug serial trace eight breakpoints and four watch points Enhanced Trace Module ETM and Enhanced Trace Buffer ETB support System tick timer On chip memory Up to 1 MB on chip dual bank flash memory with flash accelerator 16 kB on chip EEPROM data memory 136 kB SRAM for code and data use Multiple SRAM blocks with separate bus access 64 kB ROM containing boot code and on chip software drivers 64 bit 256 bit of One Time Programmable OTP memory for general purpose use Clock generation unit NXP Semiconductors LPC185x 3x 2x 1x LPC185X 3X 2X 1X 32 bit ARM Cortex M3 microcontroller Crystal oscillator with an operating range of 1 MHz to 25 MHz 12 MHz internal RC oscillator trimmed to 3 accuracy over temperature and voltage 1 5 96 accuracy for Tamb 0 C to 85 C Ultra low power RTC crystal oscillator Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high frequency crystal The second PLL can be used with the High speed USB the third PLL can be used as audio PLL Clock output Configurable digital peripherals State Configurable Timer PWM SCTimer PWM subsystem on AHB Global Input Multiplexer Array GIMA allows to cross connect multiple inputs and outputs to event drive
154. l A1 index area X 0 2 5 mm scale DIMENSIONS mm are the original dimensions A UNIT Ay A2 b D E e 1 2 w y y 0 4 0 8 0 5 9 1 9 1 mm 1 2 0 65 04 89 89 0 8 7 2 7 2 0 15 0 05 0 08 0 1 OUTLINE REFERENCES EUROPEAN VERSION JEITA PROJECTION Sane DATE 05 42 09 SOT926 1 05 12 22 Fig 50 Package outline of the TFBGA100 package LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 139 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller LQFP208 plastic low profile quad flat package 208 leads body 28 x 28 x 1 4 mm SOT459 1 detail X 1 index DIMENSIONS mm are the original dimensions UNIT A1 A2 bp 1 45 1 35 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION JEITA PROJECTION SOT459 1 136E30 MS 026 Ed Q 2 ISSUE DATE Fig 51 Package outline of the LQFP208 package LPC185X 3X
155. l NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevail Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer unless NXP Semiconductors and customer have explicitly agreed otherwise in writing In no event however shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet 19 3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract
156. l connections for STN dual panel mode External pin 4 bit mono STN dual panel 8 bit mono STN dual panel Color STN dual panel LPC18xx pin LCD function LPC18xx pin LCD function LPC18xx pin LCD function used used used LCD VD2 P4 3 UD 2 P4_3 UD 2 P4_3 UD 2 LCD_VD1 P4 4 UD 1 P4 4 UD 1 P4 4 UD 1 LCD_VDO P4 1 UD 0 P4_1 UD 0 P4 1 UD O LCD LP P7 6 LCDLP P7 6 LCDLP P7 6 LCDLP LCD ENAB P4 6 LCDENAB P4 6 LCDENAB P4 6 LCDENAB LCDM LCDM LCDM LCDM LCD FP P4 5 LCDFP P4 5 LCDFP P4 5 LCDFP LCD DCLK P4 7 LCDDCLK P4 7 LCDDCLK P4 7 LCDDCLK LCD LE P7 0 LCDLE P7 0 LCDLE P7 0 LCDLE LCD PWR P7 7 LCDPWR P7 7 LCDPWR P7 7 LCDPWR GP CLKIN PF 4 LCDCLKIN PF 4 LCDCLKIN PF 4 LCDCLKIN Table 41 LCD panel connections for TFT panels External TFT 12 bit 4 4 4 TFT 16 bit 5 6 5 mode 16 bit 1 5 5 5 mode 24 bit pin mode LPC18xx LCD LPC18xx LCD LPC18xxpin LCD LPC18xx LCD pin used function used function used function pinused function LCD VD23 PB O0 BLUES PB 0 BLUE4 PB 0 BLUE4 BLUE7 LCD_VD22 PB_1 BLUE2 PB 1 BLUES PB 1 BLUES BLUE6 LCD VD21 PB2 BLUE1 PB 2 BLUE2 PB 2 BLUE2 BLUE5 LCD VD20 PB 3 BLUEO PB 3 BLUE1 PB 3 BLUE1 BLUE4 LCD_VD19 P7_1 BLUEO P7_1 BLUEO BLUES LCD VD18 P7 2 intensity BLUE2 LCD VD17 P7 3 BLUE1 LCD VD16 P74 BLUEO LCD VD15 PB_4 GR
157. lder land occupied area DIMENSIONS in mm P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy 0 500 0 560 31 300 31 300 28 300 28 300 1 500 0 280 0 400 28 500 28 500 31 550 31 550 Fig 55 Reflow soldering for the LQFP208 package LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 144 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Footprint information for reflow soldering of LQFP144 package SOT486 1 a Hx Gx P2 gt Ad ip pm Tz ipa wa 1 x i i i IZ IZ E A Li A A A A i L 22 LZ mE ZZA 2221 1 ZA 222 1 1 ZZA ZA Hy Gy Z ae Za 222 cel me 22 E TEES Za 222 Mas TL ro Es 7777 ZZ ZA f 1 Y C 1 A L D2 8x _ D1 a Bx gt lt gt Generic footprint pattern Refer to the package outline drawing for actual layout A solder land occupied area DIMENSIONS in mm P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy 0 500 0 560 23 300 23 300 20 300 20 300 1 500 0 280 0 400 20 500 20 500 23 550 23 550 ore Fig 56 Reflow soldering for the LQFP144 package LPC185X 3X 2X 1X All inform
158. le 2 Ordering options TFBGA100 packages do not support ULPI interface Updated SSP slave and SSP master values in Table 27 Dynamic characteristics SSP pins in SPI mode Updated footnote 2 to Tey cik 2 12 Tey PCLk removed tyq data output valid time in SPI mode minimum value of 3 x 1 PCLK from SSP slave mode added units to ty delay time for SSP slave and master mode Added GPCLKIN section and table See Section 11 7 GPCLKIN and Table 22 Dynamic characteristic GPCLKIN LPC185X 3X 2X 1X v 5 20150429 Product data sheet LPC185X 3X 2X 1X v 4 1 LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 148 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 45 Revision history continued Document ID Release date Data sheet status Change notice Supersedes Modifications e Minimum operating voltage changed from 2 2 V to 2 4 V for Vpb lo Vopa 3va Var in Table 11 Updated Dynamic characteristics SSP pins in SPI mode See Table 27 Updated Dynamic characteristics SD MMC See Table 34 SPIFI timing data restated for CL 20 pF in Table 36 Dynamic characteristics SPIFI SPIFI timing diagram corrected and specified for mode 0 See Table 36 and
159. ler Increments decrements depending on direction Programmable for 2x or 4x position counting Velocity capture using built in timer Velocity compare function with less than interrupt Uses 32 bit registers for position and velocity Three position compare registers with interrupts Index counter for revolution counting Index compare register with interrupts Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement Digital filter with programmable delays for encoder input signals Can accept decoded signal inputs clk and direction Repetitive Interrupt RI timer The repetitive interrupt timer provides a free running 32 bit counter which is compared to a selectable value generating an interrupt when a match occurs Any bits of the timer compare function can be masked such that they do not contribute to the match detection The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals Features 32 bit counter Counter can be free running or be reset by a generated interrupt 32 bit compare value 32 bit compare mask An interrupt is generated when the counter value equals the compare value after masking This mechanism allows for combinations not possible with a simple compare Windowed WatchDog Timer WWDT The purpose of the watchdog is to reset the controller if software fails to perio
160. ling edge of SCL 4 Cp total capacitance of one bus line in pF If mixed with Hs mode devices faster fall times are allowed 5 The maximum t for the SDA and SCL bus lines is specified at 300 ns The maximum fall time for the SDA output stage t is specified at 250 ns This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA SCL bus lines without exceeding the maximum specified t 6 In Fast mode Plus fall time is specified the same for both output stage and bus timing If series resistors are used designers should allow for this when considering bus timing 7 The maximum tgup par could be 3 45 us and 0 9 us for Standard mode and Fast mode but must be less than the maximum of typ pAr or tvp ack by a transition time This maximum must only be met if the device does not stretch the LOW period ti ow of the SCL signal If the clock stretches the SCL the data must be valid by the set up time before it releases the clock 8 tSU DAT is the data set up time that is measured with respect to the rising edge of SCL applies to data in transmission and the acknowledge LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 108 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 9 Fast mode I C bus device can be used in a Standar
161. litch filter rejects pulses of typical 12 ns width Fig 44 Standard I O pin configuration with analog input ESD VSSIO 002aah028 13 6 Reset pin configuration ESD 20 ns RC reset auircH FILTER Fig 45 Reset pin configuration 002aag702 13 7 Suggested USB interface solutions The USB device can be connected to the USB as self powered device see Figure 46 or bus powered device see Figure 47 LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 135 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller On the LPC185x 3x 2x 1x USBn_VBUS pins are 5 V tolerant only when VDDIO is applied and at operating voltage level Therefore if the USBn VBUS function is connected to the USB connector and the device is self powered the USBn VBUS pins must be protected for situations when VDDIO 0 V If VDDIO is always at operating level while VBUS 5 V the USBn VBUS pin can be connected directly to the VBUS pin on the USB connector For systems where VDDIO can be 0 V and VBUS is directly applied to the USBn VBUS pins precautions must be taken to reduce the voltage to below 3 6 V which is the maximum allowable voltage on the USBn VBUS pins in this case One method is to use a voltage divider to conne
162. n name TFBGA100 LQFP144 Type 1 Description LBGA256 Z Reset state o a LQFP208 2 P9 3 0 2 GPIO4 15 General purpose digital input output MCOAO Motor control PWM channel 0 output A USB1 IND1 USB1 Port indicator LED control output 1 R Function reserved Function reserved ENET_RXD2 Ethernet receive data 2 MII interface R Function reserved TXD Transmitter output for USART3 P9 4 N10 92 BN Function reserved PU MCOBO Motor control PWM channel 0 output B USB1 INDO USB1 Port indicator LED control output 0 R Function reserved GPIO5 17 General purpose digital input output pin TXD2 Ethernet transmit data 2 MII interface R Function reserved RXD Receiver input for USART3 P9 5 M9 69 98 B R Function reserved PU MCOA1 Motor control PWM channel 1 output A USB1 PPWR VBUS drive signal towards external charge pump or power management unit indicates that VBUS must be driven active HIGH Add a pull down resistor to disable the power switch at reset This signal has opposite polarity compared to the USB PPWR used on other NXP LPC parts R Function reserved GPIO5 18 General purpose digital input output pin ENET TXD
163. n peripherals like timers SCTimer PWM and ADCO Serial interfaces Quad SPI Flash Interface SPIFI with 1 2 or 4 bit data at rates of up to 52 MB per second 10 100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load Support for IEEE 1588 time stamping advanced time stamping IEEE 1588 2008 v2 One High speed USB 2 0 Host Device OTG interface with DMA support and on chip high speed PHY USBO One High speed USB 2 0 Host Device interface with DMA support on chip full speed PHY and ULPI interface to an external high speed PHY USB1 USB interface electrical test software included in ROM USB stack Four 550 UARTs with DMA support one UART with full modem interface one UART with IrDA interface three USARTs support UART synchronous mode and a smart card interface conforming to 1507816 specification Up to two C CAN 2 0B controllers with one channel each Two SSP controllers with FIFO and multi protocol support Both SSPs with DMA support One Fast mode Plus I C bus interface with monitor mode and with open drain pins conforming to the full I2 C bus specification Supports data rates of up to 1 Mbit s One standard I C bus interface with monitor mode and standard I O pins Two 125 interfaces with DMA support each with one input and one output Digital peripherals External Memory Controller EMC supporting external SRAM ROM NOR flash
164. n provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 97 of 155 NXP Semiconductors LPC185x 3x 2x 1x LPC185X 3X 2X 1X 32 bit ARM Cortex M3 microcontroller Table 12 Peripheral power consumption Peripheral Branch clock Ipp REG 3v3 in mA Branch clock Branch clock frequency 48 MHz frequency 96 MHz LCD CLK M3 LCD 0 91 1 82 ETHERNET CLK M3 ETHERNET 1 06 2 15 UARTO UARTO 0 24 0 43 APBO UARTO UART1 CLK_M3_UART1 0 24 0 43 APBO UART1 UART2 UART2 0 26 0 5 APB2 UART2 UART3 CLK_M3_USARTS 0 27 0 45 CLK_APB2_UART3 TIMERO CLK_M3_TIMERO 0 08 0 15 TIMER1 CLK_M3_TIMER1 0 09 0 15 TIMER2 CLK_M3_TIMER2 0 1 0 19 TIMER3 CLK_M3_TIMER3 0 08 0 16 SDIO CLK_M3_SDIO 0 66 1 17 CLK_SDIO SCTimer PWM CLK_M3_SCT 0 66 1 3 SSPO SSPO 0 13 0 23 CLK APBO SSPO SSP1 SSP1 0 14 0 27 APB2 SSP1 DMA CLK M3 DMA 1 81 3 61 WWDT WWDT 0 03 0 09 CLK_M3_QEl 0 28 0 55 USBO USBO 1 9 3 9 CLK_USBO USB1 CLK_M3_USB1 3 02 5 69 CLK USB1 RITIMER RITIMER 0 05 0 1 3 94 7 95 DIV SCU SCU 0 1 0 21 CREG CLK_M3_CREG 0 35 0 7 Flash bank A CLK_M3_FLASHA 1 47 2 97 Flash bank B CLK_M3_FLASHB 1 4 2 84
165. n reserved P6 6 L14 83 119 B l O GPIOO 5 General purpose digital input output pin PU EMC BLS1 LOW active Byte Lane select signal 1 R Function reserved USBO PWR FAULT Port power fault signal indicating overcurrent condition this signal monitors over current on the USB bus external circuitry required to detect over current condition R Function reserved T2_CAP3 Capture input 3 of timer 2 R Function reserved R Function reserved LPC185X_3X_2X_1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 27 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name TFBGA100 LQFP208 Reset state 1 Type Description LBGA256 LQFP144 prs n2 Co P6 7 2 0 2 c R Function reserved EMC_A15 External memory address line 15 R Function reserved USBO IND1 USBO port indicator LED control output 1 GPIO5 15 General purpose digital input output pin T2 MATO Match output 0 of timer 2 R Function reserved R Function reserved Pe 8 H13 86 125 121 IN PU R Function reserved EMC_A14 External memory address line 14 R Function reserved USBO IND
166. nction reserved SD VOLT2 SD MNC bus voltage select output 2 R Function reserved Al ADC1 5 ADC1 and ADCO input channel 5 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC Clock pins LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 54 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name 1 Description Z LBGA256 Z TFBGA100 amp LQFP144 amp LQFP208 CLKO 4l Reset state CLKO SDRAM clock 0 Type CLKOUT Clock output pin R Function reserved R Function reserved 1 0 SD_CLK SD MMC card clock EMC_CLK01 SDRAM clock 0 and clock 1 combined SSP1_SCK Serial clock for SSP1 ENET_TX_CLK ENET_REF_CLK Ethernet Transmit Clock MIl interface or Ethernet Reference Clock RMII interface CLK1 T10 PU EMC CLK1 SDRAM clock 1 CLKOUT Clock output pin R Function reserved R Function reserved R Function reserved CGU OUTO CGU spare clock output 0 R Function reserved 12S1_TX_MCLK
167. ndition for the battery supply is Vpp REG 3v3 gt Vegar 0 2 V See Table 11 Table note 2 Table 14 Band gap characteristics added Minimum value for parameter Vi changed to 0 V in Table 11 Static characteristics Description of ADC pins on digital analog input pins changed Each input to the ADC is connected to ADCO and ADC1 See Table 3 OTP memory size changed to 64 bit Use of C CAN peripheral restricted in Section 2 e ADC channels limited to a total of 8 channels shared between ADCO and ADC1 LPC1857 53 v 3 2 20120920 Preliminary data sheet LPC1857 53 v 3 1 Position of index sector in Figure 4 Pin configuration LQFP208 package corrected LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 150 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 45 Revision history continued Document ID Release date Data sheet status Change notice Supersedes LPC1857 53 v 3 1 20120904 Preliminary data sheet LPC1857 53 v 3 Modifications SSPO boot pin functions added in Table 5 and Table 4 Pin SSPO SCK pin 6 SSPO SSEL pin 7 SSPO MISO pin 8 SSPO MOSI Peripheral power consumption data added in Table 12 BOD de assertion levels add in Table 13 Minimum value for all
168. nductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 10 4 BOD and band gap static characteristics LPC185X 3X 2X 1X Table 13 BOD static characteristics Tamb 25 C simulated values for nominal processing Symbol Parameter Conditions Min Typ Max Unit Vin threshold voltage interrupt level 2 assertion 2 95 V de assertion 3 03 V interrupt level 3 assertion 3 05 V de assertion 3 13 V reset level 2 assertion 2 1 V de assertion 2 18 V reset level 3 assertion 2 2 V de assertion 2 28 V 1 Interrupt and reset levels are selected by writing to the BODLV1 2 bits in the control register CREGEO see the LPC18xx user manual Table 14 Band gap characteristics Vppa 3v3 over specified ranges Tamb 40 C to 105 C unless otherwise specified Symbol Parameter Min Typ Max Unit Vret bg band gap reference voltage 0 707 0 745 0 783 mV 1 Based on characterization not tested in production All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 103 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 11 Dynamic characteristics 11 1 Flash EEPROM memory Table 15 Flash characteristics Tamb 40 to 105 C unle
169. nerate timed DMA requests Motor control PWM The motor control PWM is a specialized PWM supporting 3 phase motors and other combinations Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down An abort input causes the PWM to release all motor drive outputs immediately At the same time the motor control PWM is highly configurable for other generalized timing counting capture and compare applications Quadrature Encoder Interface QEI A quadrature encoder also known as a 2 channel incremental encoder converts angular displacement into two pulse signals By monitoring both the number of pulses and the relative phase of the two signals the user code can track the position direction of rotation and velocity In addition a third channel or index signal can be used to reset the position counter The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation In addition the QEI can capture the velocity of the encoder wheel Features Tracks encoder position All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 77 of 155 NXP Semiconductors LPC185x 3x 2x 1x 7 17 4 7 17 4 1 7 17 5 7 17 5 1 LPC185X 3X 2X 1X 32 bit ARM Cortex M3 microcontrol
170. nterface on a bus powered device Remark If the VBUS function of the USB1 interface is not connected configure the pin function for GPIO using the function control bits in the SYSCON block VDDIO LPC18xx R2 USBn_VBUS VBUS _ USB B connector aaa 013017 Fig 48 USB interface if the USB operates in OTG mode Remark In OTG mode it is important to be able to detect the VBUS level and to charge and discharge VBUS This requires adding active devices that disconnect the link when VDDIO is not present All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 137 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 14 Package outline LBGA256 plastic low profile ball grid array package 256 balls body 17 x 17 x 1mm detail X T ball A1 index area L E A Y zi 1 gt e 1 2 e b 4 Sv 00000 100000 ball A1 1
171. nterrupts accessible by software through GPIO Alarm timer The alarm timer is a 16 bit timer and counts down at 1 kHz from a preset value generating alarms in intervals of up to 1 min The counter triggers a status bit when it reaches 0x00 and asserts an interrupt if enabled The alarm timer is part of the RTC power domain and can be battery powered System control Configuration registers CREG The following settings are controlled in the configuration register block BOD trip settings Oscillator output DMA to peripheral muxing Ethernet mode Memory mapping All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 80 of 155 NXP Semiconductors LPC185x 3x 2x 1x 7 20 2 7 20 3 7 20 4 7 20 5 7 20 6 LPC185X 3X 2X 1X 32 bit ARM Cortex M3 microcontroller Timer USART inputs Enabling the USB controllers In addition the CREG block contains the part identification and part configuration information System Control Unit SCU The system control unit determines the function and electrical mode of the digital pins By default function 0 is selected for all pins with pull up enabled For pins that support a digital and analog function the ADC function select registers in the SCU enable the analog function A separate set of analog I Os for the ADCs and the DAC as well as most USB pin
172. on reserved R Function reserved lO SPIFI_SIO3 I O lane for SPIFI U1 TXD Transmitter output for UART1 lO 1250 TX WS Transmit Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the 2S bus specification 12S1_RX_SDA 1251 Receive data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification LCD VD13 LCD data P3 5 C12 B7 121 173 Bl GPIO1 15 General purpose digital input output pin PU us R Function reserved R Function reserved VO SPIFI SIO2 I O lane 2 for SPIFI U1 RXD Receiver input for UART1 1250 TX SDA 125 transmit data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the 2 specification lO 1281 RX WS Receive Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the S bus specification LCD_VD12 LCD data P3 6 B13 7 122 174 l l O GPIOO 6 General purpose digital input output pin PU R Function reserved lO SSPO SSEL Slave Select for SSPO VO SPIFI MISO Input 1 in SPIFI quad mode SPIFI output 101 R Function reserved SSPO MISO Master In Slave Out for SSPO R Function reserved R Function reserved P3 7 C11 D7 123 176 l R Function reserved PU R Function reserved
173. onductors LPC185x 3x 2x 1x 8 Limiting values 32 bit ARM Cortex M3 microcontroller Table 7 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 Symbol Parameter Conditions Min Max Unit Vpp REG 3v3 regulator supply voltage jon pin VDDREG 0 5 3 6 V 3 3 V input output supply on pin VDDIO 0 5 3 6 V voltage VppA 3V3 analog supply voltage on pin VDDA 0 5 3 6 V 3 3 V VBAT battery supply voltage on pin VBAT 0 5 3 6 V Vorog pf polyfuse programming pin VPP 0 5 3 6 V voltage Vi input voltage when 2 2 4 V 1 0 5 5 5 V 5 V tolerant digital I O pins ADC DAC pins and digital I O 0 5 V pins configured for an analog function USBO pins USBO DP 0 3 5 2 V USBO DM USBO VBUS USBO pins USBO ID 0 3 3 6 V USBO RREF USB1 pins USB1 DP and 0 3 5 2 V USB1 DM Ipp supply current per supply pin 3 100 Iss ground current per ground pin 100 llatch I O latch up current 0 5Vppiio lt lt 1 5Vpp 0 100 lt 125 C Tstg storage temperature 65 150 Ptot pack total power dissipation based on package heat transfer 1 5 Ww per package not device power consumption Vesp electrostatic discharge human body model all pins 5 2000 V voltage 1 The following applies to the limiting values a This product includes circuitry de
174. onous Interface SSP Synchronous Serial Port TCP IP Transmission Control Protocol Internet Protocol TTL Transistor Transistor Logic UART Universal Asynchronous Receiver Transmitter ULPI UTMI Low Pin Interface All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 146 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 44 Abbreviations continued Acronym Description USART Universal Synchronous Asynchronous Receiver Transmitter USB Universal Serial Bus UTMI USB 2 0 Transceiver Macrocell Interface 17 References 1 LPC18xx User manual UM10430 http www nxp com documents user manual UM10430 pdf 2 LPC18xx Errata sheet http www nxp com documents errata sheet ES LPC18XX pdf LPC185X 3X 2X 1X Product data sheet All information provided in this document is subject to legal disclaimers Rev 5 1 17 November 2015 NXP B V 2015 All rights reserved 147 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 18 Revision history Table 45 Revision history Document ID Release date Data sheet status Change notice Supersedes LPC185X 3X 2X 1X v 5 1 20151117 Product data sheet 2015110041 LPC185X 3X 2X 1X v 5 Modifications Updated Tab
175. or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors mak
176. output Vou Vpp 0 0 4V 8 mA current LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 91 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 11 Static characteristics continued Tamb 40 C to 105 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit loL LOW level output Voi 0 4 V 8 mA current lous HIGH level short circuit drive HIGH connected to 10 86 mA output current ground lots LOW level short circuit drive LOW connected to 10 76 mA output current VDp 10 lod pull down current Vi 12 62 pA 13 14 lou pull up current Vi 0V 12 62 pA 13 14 VppvIo lt V lt 5V 0 Open drain I2C0 bus pins Vin HIGH level input 0 7 x V voltage Vpb o ViL LOW level input voltage 0 0 14 0 3 x V Vpb o Vhys hysteresis voltage 0 1 x V Vpp 0 VoL LOW level output lois mA 0 4 V voltage lii input leakage current Vpb o m 4 5 E uA Vi 5V 10 uA Oscillator pins Vi XTAL1 input voltage on pin 0 5 1 2 V XTAL1 Vo XTAL2 output voltage on pin 0 5 1 2 V XTAL2 Cio input output 15 0 8 pF capacitance USBO 1
177. package outline drawing for actual layout 1 4 solder land plus solder paste SL SP SR Hx Hy 0 80 0 330 0 400 0 480 9 400 9 400 Fig 54 Reflow soldering for the TFBGA100 package RKO 5 5 0104 Ae 669 SKK 0000 RS 665 OOS C00 o S LEK 009 RSS 00000000 oe n oo SS A g Se lt gt 09 SxS 5 x 90 5 ox lt gt NS GK detail X SOT926 1 sot926 1_fr LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 143 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Footprint information for reflow soldering of LQFP208 package SOT459 1 a Hx Gx P2 gt Ad ip pm Tz teal i i i IZ IZ E A Li A A A A i i E L 22 LZ E EE ZZA 2221 1 ZA 222 1 1 ZZA ZA sos cs Hy ZZ ae Za 222 I escas 2 224 d Za 222 mE TL Es 7777 ZZ ZA f 1 Y C 1 A EET ETET L D2 8x _ D1 a Bx gt lt gt Generic footprint pattern Refer to the package outline drawing for actual layout A so
178. pecification 2 0 Complies with USB On The Go supplement Complies with Enhanced Host Controller Interface Specification Supports auto USB 2 0 mode discovery Supports all high speed USB compliant peripherals Supports all full speed USB compliant peripherals Supports software Host Negotiation Protocol HNP and Session Request Protocol SRP for OTG peripherals Supports interrupts Supports Start Of Frame SOF frame length adjust This module has its own integrated DMA engine USB interface electrical test software included in ROM USB stack All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 71 of 155 NXP Semiconductors LPC185x 3x 2x 1x 7 15 7 7 15 7 1 7 15 8 7 15 8 1 LPC185X 3X 2X 1X 32 bit ARM Cortex M3 microcontroller High speed USB Host Device interface with ULPI USB1 Remark USB1 is available on the following parts LPC185x and LPC183x USB1 is not available on the LPC182x and LPC181x parts The USB1 interface can operate as a full speed USB host device interface or can connect to an external ULPI PHY for High speed operation Features Complies with Universal Serial Bus specification 2 0 Complies with Enhanced Host Controller Interface Specification Supports auto USB 2 0 mode discovery Supports all high speed USB compliant peripherals if connected to external ULPI
179. pin can support up to eight different digital functions including General Purpose I O GPIO selectable through the SCU registers The pin name is not indicative of the GPIO port assigned to it The parts contain two 10 bit ADCs ADCO and ADC1 The input channels of ADCO and ADC1 on dedicated pins and multiplexed pins are combined in such a way that all channel 0 inputs named ADCO 0 and ADC1_0 are tied together and connected to both channel LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 7 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 Pin description 32 bit ARM Cortex M3 microcontroller 0 on ADCO and channel 0 on ADC1 channel 1 inputs named ADCO 1 and ADC1_1 are tied together and connected to channel 1 on ADCO and ADC1 and so forth There are eight ADC channels total for the two ADCs Pin name LBGA256 TFBGA100 LQFP144 LQFP208 Reset state 1 Description Multiplexed digi ital pins _0 L3 n A N GPIOO 0 General purpose digital input output pin SSP1_MISO Master In Slave Out for SSP1 ENET RXD1 Ethernet receive data 1 RMII MII interface R Function reserved R Function reserved R Function reserved 1250 TX WS Transmit Word Select It is driven by th
180. powered backup registers Event recorder with three inputs to record event identification and event time can be battery powered Alarm timer can be battery powered Analog peripherals One 10 bit DAC with DMA support and a data conversion rate of 400 kSamples s Two 10 bit ADCs with DMA support and a data conversion rate of 400 kSamples s Up to eight analog channels total Each analog input is connected to both ADCs Unique ID for each device Power Single 3 3 V 2 4 V to 3 6 V power supply with on chip internal voltage regulator for the core supply and the RTC power domain RTC power domain can be powered separately by a 3 V battery supply Four reduced power modes Sleep Deep sleep Power down and Deep power down Processor wake up from Sleep mode via wake up interrupts from various peripherals Wake up from Deep sleep Power down and Deep power down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain Brownout detect with four separate thresholds for interrupt and forced reset Power On Reset POR Available in LQFP208 LBGA256 LQFP144 and TFBGA100 packages Industrial W RFID readers Consumer e Metering White goods LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 3 of 1
181. put 1 R Function reserved PA 1 J14 l 134 B IN l O GPIO4 8 General purpose digital input output pin PU QEI IDX Quadrature Encoder Interface INDEX input R Function reserved 102 TXD Transmitter output for USART2 R Function reserved R Function reserved R Function reserved R Function reserved PA 2 K15 136 BI N GPIO4 9 General purpose digital input output pin PU QEI PHB Quadrature Encoder Interface PHB input R Function reserved U2_RXD Receiver input for USART2 R Function reserved R Function reserved R Function reserved R Function reserved PA_3 Hii l 147 BI N GPIO4 10 General purpose digital input output pin PU QEI PHA Quadrature Encoder Interface PHA input R Function reserved R Function reserved R Function reserved R Function reserved R Function reserved R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 36 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Pin name 2 Description le E 3 lt kg S 3 E es iL PA_4 G13 151 121 N R Function reser
182. put 3 of timer 0 LCD VD2 LCD data R Function reserved R Function reserved LCD VD21 LCD data U3 BAUD Baud pin for USART3 R Function reserved Al ADCO 0 ADCO and ADC1 input channel 0 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC P4 4 B1 l 9 14 5 N PU 1 0 GPIO2 4 General purpose digital input output pin CTOUT 2 SCTimer PWM output 2 Match output 2 of timer 0 LCD VD1 LCD data R Function reserved R Function reserved LCD VD20 LCD data DIR RS 485 EIA 485 output enable direction control for USARTS R Function reserved AO DAC DAC output Configure the pin as GPIO input and use the analog function select register in the SCU to select the DAC P4 5 D2 10 15 PU 1 0 GPIO2 5 General purpose digital input output pin CTOUT 5 SCTimer PWM output 5 Match output 3 of timer 3 LCD FP Frame pulse STN Vertical synchronization pulse TFT R Function reserved R Function reserved R Function reserved R Function reserved R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Pro
183. put driving HIGH AI O analog input output inactive PU pull up enabled weak pull up resistor pulls up pin to VDDIO F floating Reset state reflects the pin state at reset without boot code operation 2 5Vtolerant pad with 15 ns glitch filter 5 V tolerant if VDDIO present if VDDIO not present do not exceed 3 6 V provides digital I O functions with TTL levels and hysteresis normal drive strength 3 5V tolerant pad with 15 ns glitch filter 5 V tolerant if VDDIO present if VDDIO not present do not exceed 3 6 V providing digital I O functions with TTL levels and hysteresis high drive strength 4 5V tolerant pad with 15 ns glitch filter 5 V tolerant if VDDIO present if VDDIO not present do not exceed 3 6 V providing high speed digital I O functions with TTL levels and hysteresis 5 5 V tolerant pad providing digital I O functions with TTL levels and hysteresis and analog input or output 5 V tolerant if VDDIO present if VDDIO not present do not exceed 3 6 V When configured as an ADC input or DAC output the pin is not 5 V tolerant For analog functionality disable the digital section of the pad by setting the pin to an input function and by disabling the pull up resistor through the corresponding SFSP register 6 5 V tolerant transparent analog pad 7 For maximum load C 6 5 uF and maximum resistance Rpa 80 the VBUS signal takes about 2 s to fall from VBUS 5 V to VBUS 0 2 V when it is no longer
184. r Conditions Min Typ Max Unit ta delay time continuous transfer mode 0 5 x Toy ns SPI mode CPOL 0 0 SPI mode CPOL 0 n a ns CPHA 1 SPI mode CPOL 1 0 5 x Tey cik ns 0 SPI mode CPOL 1 n a ns CPHA 1 synchronous serial Tey clk ns frame mode microwire frame format n a ns SSP slave PCLK Peripheral clock 180 MHz frequency Tey clk clock cycle time 2 1 11x 106 S tps data set up time in SPI mode 1 5 ns tou data hold time in SPI mode 2 ns twa data output valid in SPI mode 4 x 1 PCLK 1 ins time th data output hold SPI mode 4 5 ns time tlead lead time continuous transfer mode Toy clk ns SPI mode CPOL 0 0 SPI mode CPOL 0 0 5 x ns CPHA 1 SPI mode CPOL 1 Tey clk x ns 0 SPI mode CPOL 1 0 5 x Toy clk ns CPHA 1 synchronous serial 0 5 x a ns frame mode microwire frame format Toy cll 3 ns LPC185X 3X 2X 1X Product data sheet All information provided in this document is subject to legal disclaimers Rev 5 1 17 November 2015 NXP B V 2015 All rights reserved 113 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 27 Dynamic characteristics SSP pins in SPI mode Tamb 40 to 105 C 2 4 V lt Vpp REG 3V3 lt 3 6 V 2 7 V lt VppvI0 lt 8 6 V 20 pF sampled at 10 and 90 of
185. r PWM output 11 Match output 3 of timer 2 U1 RXD Receiver input for UART1 031 External memory data line 31 GPIO7 12 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE 13 214 l 121 N Function reserved PU CTOUT_14 SCTimer PWM output 14 Match output 2 of timer 3 12 1 50 I C1 data input output this pin does not use a specialized I C EMC_DQMOUT3 Data mask used with SDRAM and static devices l O GPIO7 13 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE 14 C15 21 N l R Function reserved PU R Function reserved R Function reserved EMC_DYCS3 SDRAM chip select l O GPIO7 14 General purpose digital input output pin R Function reserved R Function reserved R Function reserved LPC185X_3X_2X_1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 50 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller
186. r USART2 R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 29 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name TFBGA100 LQFP144 LQFP208 Reset state 1 Description gt LBGA256 1 o 7 2 2 0 2 c GPIO3 10 General purpose digital input output pin CTIN_4 SCTimer PWM input 4 Capture input 2 of timer 1 12S0_TX_SDA 125 transmit data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification LCD_VD18 LCD data LCD VD6 LCD data R Function reserved U2 RXD Receiver input for USART2 R Function reserved P7 3 C13 117 1167 PU GPIO3 11 General purpose digital input output pin CTIN 3 SCTimer PWM input 3 Capture input 1 of timer 1 R Function reserved LCD VD17 LCD data LCD VD5 LCD data R Function reserved R Function reserved R Function reserved P7_4 C8 132 189 PU 1 0 GPIO3 12 General purpose digital input output pin CTOUT_13 SCTimer PWM output 13 Mat
187. ral offering support for asynchronous static memory devices such as RAM ROM and NOR flash In addition it can be used as an interface with off chip memory mapped devices and peripherals Table 6 EMC pinout for different packages Function LBGA256 TFBGA100 LQFP208 LQFP144 A A 23 0 EMC A 13 0 A 23 0 EMC A 15 0 D EMC_DJ 31 0 DJ7 0 D 15 0 EMC D 15 0 BLS EMC BLS 3 0 EMC BLSO BLS 1 0 EMC_BLSJ1 0 cs EMC_CS 3 0 EMC_CSO EMC_CS 1 0 EMC CS 1 0 OE EMC OE EMC OE EMC OE EMC OE WE EMC WE EMC WE EMC WE EMC WE CKEOUT EMC_ EMC_ EMC_ EMC_ CKEOUT 3 0 CKEOUT 1 0 CKEOUT 1 0 CKEOUT 1 0 CLK EMC_CLK 3 0 EMC CLKO EMC CLKO EMC CLKO EMC CLKO1 CLK3 EMC CLK3 EMC CLK3 EMC CLK23 EMC CLKO 1 EMC CLKO1 EMC CLKO1 EMC CLK23 EMC CLK23 EMC CLK23 DQMOUT EMC_ E EMC_ EMC_ DQMOUT 3 0 DQMOUT 1 0 DQMOUT 1 0 DYCS EMC_ EMC DYCS 1 0 EMC DYCS 1 0 EMC DYCS 1 0 DYCS 3 0 CAS EMC CAS EMC CAS EMC CAS EMC CAS RAS EMC RAS EMC RAS EMC RAS EMC RAS Features Dynamic memory interface support including single data rate SDRAM Asynchronous static memory device support including RAM ROM and NOR flash with or without asynchronous page mode Low transaction latency All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November
188. rd overtone crystal usage have a common ground plane Also connect the external components to the ground plain To keep the noise coupled in via the PCB as small as possible make loops and parasitics as small as possible Choose smaller values of Cx and if parasitics increase in the PCB layout Ensure no high speed or high drive signals are near the RTCX1 2 signals Standard I O pin configuration Figure 44 shows the possible pin modes for standard I O pins with analog input function Digital output driver enabled disabled Digital input Pull up enabled disabled e Digital input Pull down enabled disabled Digital input Repeater mode enabled disabled Digital input Input buffer enabled disabled Analog input The default configuration for standard I O pins is input buffer disabled and pull up enabled The weak MOS devices provide a drive capability equivalent to pull up and pull down resistors All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 134 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller VDDIO enable output driver data output from core 1 slew rate bit EHS input buffer enable bit EZI data input to core filter select bit ZIF pull up enable bit EPUN pull down enable bit EPD analog I O The g
189. rein may be subject to export control regulations Export might require a prior authorization from competent authorities Non automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified the product is not suitable for automotive use It is neither qualified nor tested in accordance with automotive testing or application requirements NXP Semiconductors accepts no liability for inclusion and or use of non automotive qualified products in automotive equipment or applications In the event that customer uses the product for design in and use in automotive applications to automotive specifications and standards customer a shall use the product without NXP Semiconductors warranty of the product for such automotive applications use and specifications and b 20 Contact information 32 bit ARM Cortex M3 microcontroller whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s own risk and c customer fully indemnifies NXP Semiconductors for any liability damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications 19 4 Trademarks Notice All referenced brands product names service names and trademarks are the prop
190. roller Pin name g S 8 Description ef S 3 a P1 8 R7 H5 51 71 B N GPIO1 1 General purpose digital input output pin PU U1 DTR Data Terminal Ready output for UART1 O CTOUT 12 SCTimer PWM output 12 Match output 3 of timer 3 D1 External memory data line 1 R Function reserved R Function reserved R Function reserved 80 SD MMC bus voltage select output 0 P1 9 T7 J5 52 73 2 N WO GPIO1 2 General purpose digital input output PU RTS Request to Send output for UART1 CTOUT 11 SCTimer PWM output 11 Match output 3 of timer 2 D2 External memory data line 2 R Function reserved R Function reserved R Function reserved lO SD DATO SD MMC data bus line 0 P1 10 R8 H6 53 75 2 WO GPIO1 3 General purpose digital input output pin PU U1 RI Ring Indicator input for UART1 CTOUT 14 SCTimer PWM output 14 Match output 2 of timer 3 D3 External memory data line R Function reserved R Function reserved R Function reserved lO SD DAT1 SD MMC data bus line 1 P1 11 T9 J7 55 77 B VO GPIO1 4 General purpose digital input output pin PU U1 CTS Clear to Send input for UART1 O CTOUT_15 SCT
191. rst conversion mode for single or multiple inputs e Optional conversion on transition on ADCTRIGO or ADCTRIG1 pins combined timer outputs 8 or 15 or the PWM output MCOA2 Individual result registers for each A D channel to reduce interrupt overhead DMA support 7 18 2 Digital to Analog Converter DAC 7 18 2 1 Features 10 bit resolution Monotonic by design resistor string architecture Controllable conversion speed Low power consumption 7 19 Peripherals in the RTC power domain 7 19 1 RTC The Real Time Clock RTC is a set of counters for measuring time when system power is on and optionally when it is off It uses little power when the CPU does not access its registers especially in the reduced power modes A separate 32 kHz oscillator clocks the RTC The oscillator produces a 1 Hz internal time reference and is powered by its own power supply pin VBAT 7 19 1 1 Features Measures the passage of time to maintain a calendar and clock Provides seconds minutes hours day of month month year day of week and day of year Ultra low power design to support battery powered systems Uses power from the CPU power supply when it is present LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 79 of 155 NXP Semiconductors LPC185x 3x 2x 1x 7 19 2 7 19 2 1 7 19 3
192. s are located on separate pads and are not controlled through the SCU In addition the clock delay register for the SDRAM EMC_CLK pins and the registers that select the pin interrupts are located in the SCU Clock Generation Unit CGU The Clock Generator Unit CGU generates several base clocks The base clocks can be unrelated in frequency and phase and can have different clock sources within the CGU One CGU base clock is routed to the CLKOUT pins The base clock that generates the CPU clock is referred to as CCLK Multiple branch clocks are derived from each base clock The branch clocks offer flexible control for power management purposes All branch clocks are outputs of one of two Clock Control Units CCUs and can be controlled independently Branch clocks derived from the same base clock are synchronous in frequency and phase Internal RC oscillator IRC The IRC is used as the clock source for the WWDT and or as the clock that drives the PLLs and the CPU The nominal IRC frequency is 12 MHz The IRC is trimmed to 1 5 96 accuracy for Tamb 0 C to 85 C and 3 accuracy for Tamb 40 C to 0 C and Tamb 85 C to 105 Upon power up or any chip reset the LPC185x 3x 2x 1x use the IRC as the clock source The boot loader then configures the PLL1 to provide a 96 MHz clock for the core and the PLLOUSB or PLLOAUDIO as needed if an external boot source is selected PLLOUSB for USBO PLLO is a dedicated PLL for the USBO H
193. served PB 6 A6 l PU R Function reserved USB1 ULPI D3 ULPI link bidirectional data line 3 LCD VD13 LCD data R Function reserved GPIO5 26 General purpose digital input output pin CTIN 6 SCTimer PWM input 6 Capture input 1 of timer 3 LCD VD19 LCD data R Function reserved Al ADCO 6 and ADC1 ADCO input channel 6 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 38 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name TFBGA100 LQFP144 Reset state 1 Type Description Y LBGA256 LQFP208 5 0 2 c R Function reserved USB1 ULPI ULPI link CLK signal 60 MHz clock generated by the PHY R Function reserved 1 0 ENET_RX_CLK Ethernet Receive Clock MII interface LCD_DCLK LCD panel clock R Function reserved R Function reserved SD CLK SD MMC card clock Al ADC1 1 ADC1 and ADCO input channel 1 Configure the pin as input USB and use the ADC f
194. signed for the protection of its internal devices from the damaging effects of excessive static charge Nonetheless it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum b Parameters are valid over operating temperature range unless otherwise specified All voltages are with respect to Vss unless otherwise noted 2 Including voltage on outputs in 3 state mode 3 The peak current is limited to 25 times the corresponding maximum current 4 Dependent on package type 5 Human body model equivalent to discharging a 100 pF capacitor through a 1 5 kQ series resistor LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 85 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 9 Thermal characteristics The average chip junction temperature T can be calculated using the following equation T Tamo Pp Ring ay 1 Tamb ambient temperature C Rina the package junction to ambient thermal resistance C W e sum of internal and I O power dissipation The internal power dissipation is the product of Ipp REG 3v3 and Vpp REG 3v3 The I O power dissipation of the I O pins is often small and many times can be negligible However it can be significant in some applications
195. smit and one for receive Generates interrupt requests when buffer levels cross a programmable boundary Two DMA requests controlled by programmable buffer levels The DMA requests are connected to the GPDMA block Controls include reset stop and mute options separately for 1 S bus input and 125 output 7 16 6 C CAN Remark The LPC185x 3x 2x 1x contain two C CAN controllers Controller Area Network CAN is the definition of a high performance communication protocol for serial data communication The C CAN controller is designed to provide a full implementation of the CAN protocol according to the CAN Specification Version 2 0B The C CAN controller can build powerful local networks with low cost multiplex wiring by supporting distributed real time control with a high level of reliability 7 16 6 1 Features LPC185X 3X 2X 1X Conforms to protocol version 2 0 parts A and B Supports bit rate of up to 1 Mbit s Supports 32 Message Objects Each Message Object has its own identifier mask Provides programmable FIFO mode concatenation of Message Objects Provides maskable interrupts Supports Disabled Automatic Retransmission DAR mode for time triggered CAN applications Provides programmable loop back mode for self test operation All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 76
196. ss otherwise specified Vpp ReG 3v3 2 4 V to 3 6 V for read operations Vpp REG 3v3 2 7 V to 3 6 V for erase program operations Symbol Parameter Conditions Min Typ Max Unit Nendu endurance sector erase program 10000 cycles page erase program page 1000 cycles in large sector page erase program page 10000 cycles in small sector tret retention time powered 10 years unpowered 10 years ter erase time page sector or multiple 100 ms consecutive sectors torog programming 1 1 ms time 1 Number of erase program cycles 2 Programming times are given for writing 512 bytes from RAM to the flash Data must be written to the flash in blocks of 512 bytes Table 16 EEPROM characteristics Tamb 40 to 105 C Vpp REay ava 2 7 V to 3 6 V Symbol Parameter Conditions Min Typ Max Unit fork clock frequency 800 1500 1600 kHz Nendu endurance 100 000 cycles tret retention time Tamb 40 C to 85 C 20 years 85 C lt Tamb lt 105 C 10 ta access time read 120 ns erase program 1 99 ms folk 1500 kHz erase program 1 87 gt ms folk 1600 kHz twait wait time read RPHASE1 35 ns read RPHASE2 70 ns write PHASE1 20 ns write PHASE2 40 ns write PHASE3 10 ns 1 See the LPC18xx user man
197. stor 18 36 44 1 Q impedance for driver steady state drive which is not high speed capable 1 2 9 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages The recommended operating condition for the battery supply is Vpp REGy ava gt Vgar 0 2 V Special conditions for Vpp Reay 3v3 apply when writing to the flash and EEPROM See Table 16 and Table 15 Pin VPP should either be not connected when OTP does not need to be programmed or tied to pins VDDIO and VDDREG to ensure the same ramp up time for both supply voltages Vpp REG 3v3 3 3 V 3 3 V Tamb 25 PLL1 disabled IRC running CCLK 12 MHz Vear 3 6 V Tamb 40 C to 105 C Vpp o Vopa 3 6 V over entire frequency range CCLK 12 MHz to 180 MHz in active mode sleep mode deep sleep mode power down mode and deep power down mode Vps corresponds to the output of the power switch see Figure 9 which is determined by the greater of Vaar and Vpp Reg 3v3 VppA 3V3 3 3 V Tamb 25 10 Allowed as long as the current limit does exceed the maximum current allowed by the device 11 To Vss 12 The values specified are simulated and absolute values 13 The weak pull up resistor is connected to the Vpp oy rail and pulls up the I O pin to the Vpp oy level 14 The input cell disables the weak pull up resistor when the applied
198. t can wake up the ARM Cortex M3 from sleep mode if enabled in the NVIC Global Input Multiplexer Array GIMA The GIMA routes signals to event driven peripheral targets like the SCTimer PWM timers event router or the ADCs Features Single selection of a source Signal inversion Can capture a pulse if the input event source is faster than the target clock Synchronization of input event and target clock Single cycle pulse generation for target On chip static RAM The LPC185x 3x 2x 1x support up to 136 SRAM with separate bus master access for higher throughput and individual power control for low power operation All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 62 of 155 NXP Semiconductors LPC185x 3x 2x 1x 7 9 7 10 7 11 32 bit ARM Cortex M3 microcontroller On chip flash memory The LPC185x 3x 2x 1x contain up to 1 MB of dual bank flash program memory With dual bank flash memory the user code can write or erase one flash bank while reading the other flash bank without interruption A two port flash accelerator maximizes the flash performance In System Programming ISP and In Application Programming IAP routines for programming the flash memory are provided in the Boot ROM EEPROM The LPC185x 3x 2x 1x contain up to 16 kB of on chip byte erasable and byte programm
199. ta 2 MII interface GPIO6 5 General purpose digital input output pin R Function reserved T8 CAP3 Capture input of timer SD DAT2 SD MMC data bus line 2 LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 40 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 Pin description continued 32 bit ARM Cortex M3 microcontroller Pin name TFBGA100 LQFP144 LQFP208 Reset state 1 Type Description PC 7 9 LBGA256 2 0 2 c R Function reserved USB1 ULPI D1 ULPI link bidirectional data line 1 R Function reserved ENET RXD3 Ethernet receive data 3 MII interface GPIO6 6 General purpose digital input output pin R Function reserved T8 MATO Match output 0 of timer SD DAT3 SD MMC data bus line PC 8 N4 2 PU Function reserved USB1 ULPI ULPI link bidirectional data line 0 R Function reserved ENET RX DV Ethernet Receive Data Valid RMII MII interface GPIO6 7 General purpose digital input output pin R Function reserved T8 MAT1 Match output 1 of timer SD CD SD MMC card detect input PC 9 K2 PU R Function
200. ta when a DMA request goes active Master 1 can access memories and peripherals master 0 can access memories only 32 bit AHB master bus width e Incrementing or non incrementing addressing for source and destination Programmable DMA burst size The DMA burst size can be programmed to more efficiently transfer data Internal four word FIFO per channel Supports 8 16 and 32 bit wide transactions Big endian and little endian support The DMA Controller defaults to little endian mode on reset Aninterrupt to the processor can be generated on a DMA completion or when a DMA error has occurred e Raw interrupt status DMA error DMA count raw interrupt status can be read prior to masking 7 15 3 SPI Flash Interface SPIFI 7 15 3 1 LPC185X 3X 2X 1X The SPI Flash Interface allows low cost serial flash memories to be connected to the ARM Cortex M3 processor with little performance penalty compared to parallel flash devices with higher pin count After a few commands configure the interface at startup the entire flash content is accessible as normal memory using byte halfword and word accesses by the processor and or DMA channels Simple sequences of commands handle erasure and programming Many serial flash devices use a half duplex command driven SPI protocol for device setup and initialization and then move to a half duplex command driven 4 bit protocol for normal operation Different serial flash
201. ter is not included 5 Select HF 0 in the XTAL_OSC_CTRL register 6 Select HF 1 in the XTAL_OSC_CTRL register IRC oscillator Table 20 Dynamic characteristic IRC oscillator 2 4 V lt VppREG 3v3 lt 3 6 V Symbol Parameter Conditions Min Typ Max Unit fosec internal RC 40 C lt Tamb lt 0 C 12 0 395 120 11204396 MHz oscillator lt 85 C 112 0 1 5 120 12 041 596 MHz frequency 85 C lt Tamb 105 112 0 3 96 120 11204396 MHz 1 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages RTC oscillator See Section 13 3 for connecting the RTC oscillator to an external clock source Table 21 Dynamic characteristic RTC oscillator Tamb 40 C to 105 24V lt Vpp REG 3V3 lt 3 6 V or 2 4 lt Vgar 3 6 1 Symbol Parameter Conditions Min Typ Unit fi input frequency 32 768 kHz ICC osc oscillator supply 280 800 nA current 1 Parameters are valid over operating temperature range unless otherwise specified 2 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 106 of 155 NXP Semiconductors L
202. thernet Transmit Error MII interface SD DAT7 SD MMC data bus line 7 LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 AII rights reserved Product data sheet Rev 5 1 17 November 2015 42 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name 2 Description le E dE qe ee eels PD 0 N2 BN l R Function reserved PU CTOUT 15 SCTimer PWM output 15 Match output 3 of timer 3 EMC_DQMOUT2 Data mask 2 used with SDRAM and static devices R Function reserved l O GPIO6 14 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PD 1 P1 l 2 N R Function reserved PU R Function reserved EMC_CKEOUT2 SDRAM clock enable 2 R Function reserved l O GPIO6 15 General purpose digital input output pin 80 SD MMC power monitor output R Function reserved R Function reserved PD 2 Ri l 21 l Function reserved PU CTOUT_7 SCTimer PWM output 7 Match output 3 of timer 1 D16 External memory data line 16 R Function reserved l O GPIO6 16
203. to address invalid PB 1 2 0 2 6 ns tcsHEOR CS HIGH to end of read B 2 0 0 ns time tcstson CS LOW to start of read A 0 1 8 ns time Write cycle parameters tesLav CS LOW to address valid 3 1 1 6 ns time tcsLpv CS LOW to data valid time 3 1 1 5 ns tcstweL CS LOW to WE LOW time PB 1 1 5 0 2 ns WAITWEN 1 WAITWEN 1 X Tey clk Tey clk tcstptsL CS LOW to BLS LOW time PB 1 0 7 3 1 8 ns twetweH WE LOW to WE HIGH time PB 1 2 0 6 0 4 ns WAITWR WAITWR WAITWEN 1 x WAITWEN 1 x Tey clk Toy cll tweupwv WEHIGH to data invalid 1 2 0 9 2 3 ns time twEHEOW WE HIGH to end of write PB 1 2 0 4 Toy clk 0 3 Toy clk ns time 5 tcstatsL_ CS LOW to BLS LOW 0 0 7 1 8 ns LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 117 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 28 Dynamic characteristics Static asynchronous external memory interface continued 22 pF for EMC_Dn 20 pF for all others Tamp 40 C to 105 C 2 4 V lt Vppieay ava lt 3 6 V 2 7 V lt Vppio 3 6 V values guaranteed by design the values in the table have been calculated with WAITTURN 0 0 in STATICWAITTURN register Timing parameters are given for single memory access cycles In a
204. tween 10 bit ADCO 1 ADC1 6 IA ADCO 7 C5 136 197 81 ADC input channel 7 Shared between 10 bit ADCO 1 ADC1 7 1 RTC pins RTC ALARM 11 129 186 101 controlled output RTCX1 8 5 125 182 Bl Input to the RTC 32 kHz ultra low power oscillator circuit RTCX2 B8 B5 126 183 8 Output from the RTC 32 kHz ultra low power oscillator circuit SAMPLE B9 o O Event monitor sample output Crystal oscillator pins XTAL1 D1 B1 12 18 B Input to the oscillator circuit and internal clock generator circuits LPC185X_3X_2X_1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 57 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Pin name 2 Description se 9 zz s g lt 3 amp a e le ele XTAL2 E1 C1 19 19 B l Output from the oscillator amplifier Power and ground pins USBO VDDA F3 D1 16 24 Separate analog 3 3 V power supply for driver 3V3 DRIVER USBO G3 D2 17 25 USB 3 3 V separate power supply voltage _VDDA3V3 USBO VSSA 19 27 Dedicated analog ground for clean reference for termination _TERM resistors USBO_VSSA G1 F2 23 31 Dedicated clean analog ground for generation of
205. ual how to program the wait states for the different read RPHASEx and erase program phases PHASEx LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 104 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller 11 2 Wake up times Table 17 Dynamic characteristic Wake up from Deep sleep Power down and Deep power down modes Tamb 40 C to 105 C Symbol Parameter Conditions Min Max Unit twake wake up time from Sleep mode 21 3x Toyo 5 ns from Deep sleep and 12 51 uS Power down mode from Deep power down mode 200 HS after reset 200 Hus 1 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages 2 Teyi 1 CCLK with CCLK CPU clock frequency 11 3 External clock for oscillator in slave mode Remark The input voltage on the XTAL1 2 pins must be x 1 2 V see Table 11 For connecting the oscillator to the XTAL pins also see Section 13 2 and Section 13 4 Table 18 Dynamic characteristic external clock Tamb 40 to 105 C over specified ranges Symbol Parameter Conditions Min Max Unit fosc oscillator frequency 1 25 MHz clock cycle time 40 1000 ns clock HIG
206. ued 32 bit ARM Cortex M3 microcontroller Pin name TFBGA100 Reset state 1 Description ci LBGA256 Q LQFP144 3 LQFP208 5 2 0 2 c GPIO2 12 General purpose digital input output pin MCIO Motor control PWM channel 0 input EMC_D15 External memory data line 15 R Function reserved U1 RI Ring Indicator input for UART1 T1 CAP3 Capture input of timer 1 R Function reserved R Function reserved P54 P9 57 80 2 PU GPIO2 13 General purpose digital input output MCOBO Motor control PWM channel 0 output B 1 0 EMC_D8 External memory data line 8 R Function reserved U1_CTS Clear to Send input for UART1 T1_MATO Match output 0 of timer 1 R Function reserved R Function reserved P5_5 P10 58 81 N PU 1 0 GPIO2 14 General purpose digital input output pin MCOA1 Motor control PWM channel 1 output A 1 0 EMC_D9 External memory data line 9 R Function reserved U1_DCD Data Carrier Detect input for UART1 T1_MAT1 Match output 1 of timer 1 R Function reserved R Function reserved P5_6 T13 63 89 N PU GPIO2 15 General purpose digital input output pin MCOB1 Motor control PWM channel 1 output
207. um drive mode ILH HIGH level leakage Vi on chip 3 nA current pull down resistor disabled Vi 5 Vi Tamb 25 C 0 7 nA Vi 5 Vi Tamb 105 C 70 nA lou HIGH level output Vou 0 4V 8 mA current lo LOW level output VoL 0 4 V 8 mA current lous HIGH level short circuit drive HIGH connected to 10 65 output current ground lois LOW level short circuit drive LOW connected to 10 63 mA output current I O pins high drive strength high drive mode ILH HIGH level leakage Vi on chip 3 nA current pull down resistor disabled Vi 5 V Tamb 25 0 6 E nA Vi 2 5 V Tamb 105 C 63 nA HIGH level output Vpp o 0 4V 14 current lot LOW level output VoL 0 4 V 14 mA current lous HIGH level short circuit drive HIGH connected to 10 113 mA output current ground lois LOW level short circuit drive LOW connected to 10 110 mA output current Vpp Io LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 90 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 11 Static characteristics continued Tamb 40 C to
208. unction reserved PD 15 T15 ho B R Function reserved PU R Function reserved 1 0 EMC_A17 External memory address line 17 R Function reserved GPIO6 29 General purpose digital input output pin SD WP SD MMC card write protect input CTOUT 8 SCTimer PWM output 8 Match output 0 of timer 2 R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 46 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name TFBGA100 LQFP144 LQFP208 Reset state 1 Type Description 2 LBGA256 AR 1 1 AR PD 16 2 0 2 c R Function reserved R Function reserved EMC_A16 External memory address line 16 R Function reserved GPIO6 30 General purpose digital input output pin SD_VOLT2 SD MMC bus voltage select output 2 CTOUT_12 SCTimer PWM output 12 Match output 3 of timer 3 R Function reserved PE 0 P14 106 PU R Function reserved R Function reserved R Function reserved 1 0 EMC_A18 External memory address line 18 GPIO7 0
209. unction select register in the SCU to select the ADC PC 1 E4 9 2 PU 1 0 USB1_ULPI_D7 ULPI link bidirectional data line 7 R Function reserved U1_RI Ring Indicator input for UART1 ENET_MDC Ethernet MIIM clock GPIO6 0 General purpose digital input output pin R Function reserved T3_CAPO Capture input 0 of timer SD VOLTO SD MMC bus voltage select output 0 PC 2 F6 2 13 N PU USB1 ULPI D6 ULPI link bidirectional data line 6 R Function reserved U1 CTS Clear to Send input for UART1 ENET TXD2 Ethernet transmit data 2 MII interface GPIO6 1 General purpose digital input output pin R Function reserved R Function reserved SD RST SD MMC reset signal for MMC4 4 card LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 39 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name TFBGA100 LQFP144 LQFP208 Reset state 1 Type Description d LBGA256 1 1 k 5 0 2 c USB1 ULPI D5 ULPI link bidirectional data line 5 R Function reserved U1_
210. urpose digital input output pin PU U1 RXD Receiver input for UART1 R Function reserved 07 External memory data line 7 0 MAT2 Match output 2 of timer 0 R Function reserved R Function reserved R Function reserved P1 15 T12 K8 62 87 IN l O GPIOO 2 General purpose digital input output pin PU U2 TXD Transmitter output for USART2 R Function reserved ENET RXDO Ethernet receive data 0 RMII MII interface 0 MAT1 Match output 1 of timer R Function reserved D8 External memory data line 8 R Function reserved LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 12 of 155 NXP Semiconductors LPC185x 3x 2x 1x Table 3 description continued 32 bit ARM Cortex M3 microcontroller Pin name Reset state 1 Type Description LBGA256 TFBGA100 LQFP144 LQFP208 1_16 2 0 2 c GPIOO 3 General purpose digital input output pin U2_RXD Receiver input for USART2 R Function reserved ENET_CRS Ethernet Carrier Sense MII interface TO MATO Match output 0 of timer 0 Function reserved 09 External memory data line 9 DV Ethernet Receive Data V
211. ut output pin CTOUT 11 SCTimer PWM output 1 Match output 3 of timer 2 R Function reserved LCD LP Line synchronization pulse STN Horizontal synchronization pulse TFT R Function reserved TRACEDATA 2 Trace data bit 2 R Function reserved R Function reserved P7 7 B6 140 201 PU GPIO3 15 General purpose digital input output pin CTOUT 8 SCTimer PWM output 8 Match output 0 of timer 2 R Function reserved LCD PWR LCD panel power enable R Function reserved TRACEDATA S Trace data bit ENET MDC Ethernet MIIM clock R Function reserved ADC1 6 ADC1 and ADCO input channel 6 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC LPC185X 3X 2X 1X All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 31 of 155 NXP Semiconductors LPC185x 3x 2x 1x 32 bit ARM Cortex M3 microcontroller Table 3 description continued Pin name 2 Description le E 9 gale P8 0 E5 2 BI IN l O GPIO4 0 General purpose digital
212. ved PU CTOUT 9 SCTimer PWM output 9 Match output 3 of timer 3 R Function reserved A23 External memory address line 23 l O GPIO5 19 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PB 0 B15 l 164 BI N R Function reserved PU O CTOUT 10 SCTimer PWM output 10 Match output 3 of timer 3 LCD_VD23 LCD data R Function reserved GPIO5 20 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PB 1 14 175 BI N R Function reserved PU USB1 ULPI DIR ULPI link DIR signal Controls the ULP data line direction O LCD_VD22 LCD data R Function reserved GPIO5 21 General purpose digital input output pin O CTOUT 6 SCTimer PWM output 6 Match output 2 of timer 1 R Function reserved R Function reserved PB 2 B12 177 BI N R Function reserved PU USB1 ULPI D7 ULPI link bidirectional data line 7 O LCD_VD21 LCD data R Function reserved GPIO5 22 General purpose digital input output pin CTOUT 7 SCTimer PWM output 7 Match output of timer 1 R Function reserved R Function reserved LPC185X 3X 2X 1X All information provided
213. vendors and devices accept or require different commands and command formats SPIFI provides sufficient flexibility to be compatible with common flash devices and includes extensions to help insure compatibility with future devices Features Interfaces to serial flash memory in the main memory map Supports classic and 4 bit bidirectional serial protocols Half duplex protocol compatible with various vendors and devices Quad SPI Flash Interface SPIFI with 1 2 or 4 bit data at rates of up to 52 MB per second Supports DMA access All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Product data sheet Rev 5 1 17 November 2015 69 of 155 NXP Semiconductors LPC185x 3x 2x 1x 7 15 4 SD MMC card interface The SD MMC card interface supports the following modes 7 15 5 7 15 5 1 LPC185X 3X 2X 1X Secure Digital memory SD version 3 0 e Secure Digital I O SDIO version 2 0 Consumer Electronics Advanced Transport Architecture CE ATA version 1 1 Multimedia Cards MMC version 4 4 External Memory Controller EMC Remark The EMC is available on all LPC185x 3x 2x 1x parts The following memory bus widths are supported LBGA256 packages 32 bit TFBGA100 packages 8 bit LQFP208 packages 16 bit LQFP144 packages 16 bit 32 bit ARM Cortex M3 microcontroller The LPC185x 3x 2x 1x EMC is a Memory Controller periphe

Download Pdf Manuals

image

Related Search

Related Contents

  Disto classic 4 - Diemme strumenti  Guide d`encadrement - Emploi  BENDIX 03-RV-1 User's Manual  Cisco Systems 7920 IP IP Phone User Manual  Targus 10.2" A7 Netbook Slipcase  

Copyright © All rights reserved.
Failed to retrieve file