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Application Note Interfacing the TMS320C6X DSP to the PCI bus

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1. R W BURST RDY r C EE Le LEBA data C CLKBAen dat ee OEBA dat 2 2 2 OEBA ad be NX 1 LEBA ad be EMIF to EPC Write Cycle Notes D SETUP gt 2 SETUP must be bigger or equal to two The write cycle demonstrates the max case for CLKOUTI which is 200 MHz and the max case for local EPC max local clk which is 50 MHz SETUP period just be at least 2 SETUP 2 SETUP 2 would give ARDY which is asynchronously out put enabled by CEO a reasonable delay time 10 ns to be asserted low before the STROBE period starts Also maintain the same order of operation meaning after LCLK 0 open the address and byte enable buffers even though the AWE signal would be already asserted and on LCLK 1 start the cycle on EPC side by asserting LREQ and the other control 20 AN EC6 02 0100 2000 V3 Semiconductor Corp Read and Write Waveforms and Waveform Notes EMIF to EPC Write Waveform signal Don t shave off a cycle by opening the address and byte enable buffers and LREQ on the same clock Otherwise you would need to take into consideration the PLD clock to out the buffers delay time and the EPC s address and byte enables setup time On 50 MHz LCLK that is not feasible 2 LCLK 0 CEO is asserted On the rising edge of LCLK 0 PLD detects EMIF is in the SET UP period for an EMIF to EPC access cycle or in the STROBE period if SETUP is less than six If LBGNT is not asserted
2. STARTCY EMIF EPC WAITARDY EMIF STROBE EMIF WAITA4B2B signal EPC HPI CS EPC HPI NS signal NOT LAST signal MASK signal MASK PAR constant constant constant constant constant type EMIF EPC STATE is EPC HPI IDLE EPC HPI STARTCY EPC HPI STROBEl EPC HPI STROBE2 EPC HPI DEASTROB std_ulogic std ulogic std ulogic std ulogic std ulogic std ulogic logic logic logic logic logic logic logic logic logic std std u std u u std u std u ogic ogic vector ogic vector ogic vector ogic vector ogic vector std u std std u std u std u std u ogic_vector ogic_vector ogic_vector ogic_vector ogic_vector ogic_vector ogic_vector 3 3 3 3 3 3 3 downto downto downto downto downto downto downto downto downto downto downto downto std ulogic vector 2 std ulogic std ulogic std ulogic std ulogic vector 2 std ulogic vector 2 std ulogic vector 2 std ulogic vector 2 std ulogic vector 2 IDLE downto downto downto downto downto downto EPC OPEN BUF EMIF EPC WAITA4RDY EMIF STROBE EMIF EPC B2B begin 000 001 2 011 110 0000 0001 2 0101 i2 0111 2 1000 0010 0 000 001 2 011 010 100 32 AN EC6 02 0100 2000 V3 Semiconductor Corp PLD Source
3. meaning EPC is not granted the bus EMIF can access the EPC bus by enabling the address and byte enables buffers Otherwise EMIF is held in the STROBE period with wait states inserted 1 LBGNT is not asserted meaning EPC has not granted the bus to EPC access can proceed The Address and byte enable buffers open to access EPC s address and byte enables buses If the EPC is granted the bus wait cycles are inserted waiting for LBGNT to go idle EMIF remains in the STROBE period with ARDY low 1 AWE is asserted a write cycle starts on the rising edge of LCLK 1 by asserting LREQ BURST R W The data buffers are also opened to allow a data path from to the EPC data bus LCLK 3 Data has been written to the EPC on the rising edge of LCLK 3 RDY was asserted low by the EPC ARDY went high after the rising edge of LCLK 3 for half a clock A single strobe is enough in the STROBE period to end the STROBE period To the EPC the end of the cycle is on the rising edge of LCLK 3 Data address and the byte enable buffers are locked The control signal to the EPC is tristated For the EMIF keep the following relationship for any design frequency or programming STROBE HOLD SETUP gt TLCK Examplel STROBE 1 HOLD 1 SETUP 3 LCLK 50 MHz CLKOUT1 200MHZ 5x5 25 gt 20 Example2 STROBE 1 HOLD 1 SETUP 6 LCLK 50 MHz CLKOUT1 200MHZ 8 5 40 gt 20 Note RDY clock to out is 14
4. BURSTb are indicated by a lower case b at the end of the signal name active low signals are converted to active high when used in the logic generation portion of the VHDL code Active low signals are indicated by an overline LBGNT throughout the rest of this document Top level signals pass through an I O buffer stage as shown in Figure 4 Signal Names in Relation to I O Buffering This converts everything to positive true logic and also converts weak input highs lows H L to l 0 All VHDL core logic is written in positive true logic That is an active low signal such as TS called TSb in VHDL is converted to an active high equivalent as in Figure 4 and then used by the core logic in the active high sense TSi means TS is active Figure 4 Signal Names in Relation to I O Buffering Active Low SiGAb D SIGAi Input Active SIGCb Low I O Active High I O Active High sicB p gt SIGBi Input VHDL Core Logic SIGD Active Low with High Z E siceb Active High with High Z IF 2000 V3 Semiconductor Corp AN EC6 02 0100 29 PLD Source Code VHDL Code 6 2 VHDL Code library use IEEE std logic 1164 all1 The objective of this VHDL code is to interface TI 5320 6 DSP to PCI bus via Semiconductor V360EPC PCI bridge following the High Performance Design shown in Figure 1 port RESETb
5. Code VHDL Code Take the external I O and create active high signals for internal use EPC Interface Inputs RESETi lt not to x01 RESETbD LBREQi lt not to_x01 LBREQb LREQi lt not to_x01 LREQb RDYi lt not to x01 RDYb BURSTi lt not to x01 BURSTb EPC RWi lt to 01 RWb A2i lt to x01 A2 A18i lt to x01 A18 Alsi lt to_x01 A19 A30i lt to_x01 A30 EPC Interface Outputs LBGNTb lt not to x01 LBGNTo LREQb lt not to xOl LREQo when LREQoe 1 else Z RWb lt to 01 RWo when EPC RWoe 1 else Z RDYb lt not to xOl RDYo when RDYoe 1 else Z BURSTb lt not to_x01 BURSTo when BURSToe 1 else Z HPI interface Inputs HCNTL lt To 01 StdlogicVector HCNTLo when HCNTLoe 1 RWb lt not to 01 RWo when HPI RWoe 1 HDSb lt not to x01 HDSo HCSb lt not to x01 HCSo HRDYi lt not to x01 HRDYb EPC to SRAM access EMIF HOLDAi lt not to 01 HOLDAbD 0 lt not to x01 CE0b 11 lt not to 01 15 1 lt not to x01 AOEb AWEi lt not to x01 AWEb AREi lt not to x01 ARED EMIF Interface Outputs EMIF HOLDb lt not to xO1 EMIF HOLDOo CE1b lt not to xOl CEl1o when CEloe 1 else Z ARDY lt to xOl ARDYo when ARDYoe 1 AOEb lt not to_x01 AOEo when AOEoe 1 else Z AWEb lt not to_x
6. Corp 2348G Walsh Avenue Santa Clara CA 95051 7 SEMICONDUCTOR Phone 408 988 1050 Fax 408 988 2601 ye THE EMBEDDED INTELLIGENCE COMPANY Toll Free 800 488 8410 US and Canada Femi co http www vcubed com 2000 V3 Semiconductor Corp AN EC6 02 0100 1 Overview PCI bridge for this application Two possible designs are shown in the figures that follow Figure 1 illustrates a high performance application where the PCI agent can access the HPI interface at the same time the EMIF is accessing its external bus The buffers between the two buses provide isolation These buffers are very useful when this type of concurrence is crucial for high performance Figure 2 illustrates a simple design where HPI and EMIF concurrence is not important to the application As shown in Figure 1 the accesses the PCI bus through the EPC Accesses from the to EPC can easily be accomplished by enabling the buffers to the EMIF to EPC direction Accesses from the V360EPC to the EMIF external bus to shared memory may also be accomplished by enabling the buffers to the other direction EPC to This application uses three SNS4ABT16601 18 bit buffers from Texas Instruments See Interconnection The buffers are enabled for either EPC SRAM access or EMIF EPC access For EPC SRAM access the EMIF relinquishes its external bus HOLD HOLDA protocol In the case of access the EMIF waits until the EPC relinqui
7. OxX7FFF8 for the HPIC address X bits 31 20 in the address bus OxX7FFFC for the HPIA address 0xX80000 for the HPID first address up to 1 MB data burst access The EPC max burst size is 1 KB burst accesses more than 1 KB is broken into 1 KB bursts If the DMA is set to transfer 128 KB 8 bytes or less of address control and data starting from HPIC the EPC breaks the transfers into 1 KB bursts 0 0000 is the first address in 1 Mb sequential addresses for non incremental access HPIC and HPIA can be any combination of addresses A19 18 00 or 18 01 Accessing and be a burst of two if the addresses are sequential access HPID for up to 1 Mbit burst size is possible in a separate access the breaks the transfer into 1 KB bursts From a system level a programmer can set the EPC s DMA to transfer any amount of data up to 1 MB 26 AN EC6 02 0100 2000 V3 Semiconductor Corp Programming PCI to HPI The access to the HPI interface registers is determined by HNCTLI1 0 pins according to the following table Table 7 HPI Interface HCNTL1 HCNTLO Description 0 0 Access to HPIC 0 1 Access to HPIA 1 0 Access to HPID with HPIA increment 1 1 Access with HPID HPIA is not affected A30 determines whether the access is to HPI or SRAM A19 A18 and A2 determine whether the access is to HPIC HPIA HPID with increment or HPID with no increment NOT
8. The PLD Tcov typically 5 ns Program the strobe to 2 where the data is valid and enough set up time is provided for ARDY LREQ is de asserted as the cycle has ended on the EPC side The address and the byte enable buffers are closed OEAB LEAB ad be after this clock cycle as well The data buffer output enable is de asserted synchronously with LCLK 4 to disable buffering C ARDY is tristated to high Z asynchronously with CEO de assertion CEO EMIF output is de asserted after seven minus the HOLD period clocks in the Waveform HOLD 2 so the CEO is de asserted on CLKOUT1 25 25 20 5 7 2 5 After the HOLD period if there is a back to back cycle CEO is not de asserted and the SETUP period for the next access starts immediately after HOLD 9 ARDY is asynchronously asserted low with CEO assertion in order to prevent EMIF from proceeding in the STROBE period without getting synchronized with the EPC 2000 V3 Semiconductor Corp AN EC6 02 0100 19 Read Write Waveforms Wavetform Notes EMIF to EPC Write Waveform 4 4 EMIF to EPC Write Waveform EMIF to EPC Write Cycle Write parameters SET 3 STROBE 1 HOLD 1 O 1 2 4 6 8 10 12 14 16 18 20 22 24 26 CLKOUT1 ome 0 6 BE 3 0 lt ED 31 0 EA ED AOE ios strobe ARE Fe 9 m ARDY T _ LBREQ LREQ N S LA31 2 BWE 3 0 LD 31 0
9. connected to the PLD R W The EPC s read not write input output pin This pin is directly connected to the PLD BWE 3 0 The EPC s byte enables input output pins These pins are connected to the EMIF byte enable pins through the buffers for PCI to SRAM or EMIF to PCI accesses BWEO and BWE3 are connected to the HPI s and BLE inputs BWEO is BLE 0 and BWE3 is HBE 1 LD 31 0 The EPC s input output data bus The lower 16 bits are connected directly to the HPI data bus via HD 15 0 LD 31 0 are connected to the data bus through latching buffers for EMIF to PCI or PCI to SRAM accesses LA 31 2 The EPC s address bus input output pins A30 is connected to the PLD and is used to decode accesses from PCI to HPI A19 A18 and A2 are also used to decode the type of access to the HPI See Section 5 0 Programming The lower address LA 21 2 are connected through the buffers to EMIF EA 21 2 external bus LCLK The local clock input pin is the same clock connected to the data latching buffers and to the PLD There is no relationship between the TMS320C6x DSP clocks CLKOUT1 CLKOUT2 and this clock they are completely asynchronous 2000 V3 Semiconductor Corp AN EC6 02 0100 9 Interconnection HPI Interface Interconnect 3 2 HPI Interface Interconnect HCNTL 1 0 The 5 control inputs pins Any access to the HPI must be to one of it s three registers HPI
10. data buffers are 5 ns Before asserting CS for the next write strobe a set up of 20 ns is required The EPC to SRAM waveform shows 1 LCLK inserted before asserting CS 20 ns at 50 MHz The CE STROBE period must be 8 10 ns minimum following IDT71V416 SRAM data sheet 12 LCLK accomplishes the task max delay time for the address byte enables and the data on the first write cycle is Tcov pld Control signals to output valid for the buffers is typically 11 ns 2000 V3 Semiconductor Corp AN EC6 02 0100 17 Read Write Waveforms Wavetform Notes EMIF to EPC Read Waveform 4 3 EMIF to EPC Read Waveform EMIF to EPC Read Cycle CLKOUT1 CE0 BE 3 0 ED 31 0 EA AOE ARE AWE ARDY LCLK LBREQ LBGNT LREQ LA31 2 BWE 3 0 LD 31 0 R W BURST RDY LEAB data CLKABen data OEAB data OEBA ad be LEBA ad be Write parameters SET UP 6 STROBE 3 2 HOLD 2 3 Oo 1 2 4 6 8 10 12 14 ser uP e 1 1 4 om gt EMIF to EPC Read Cycle Notes D SETUP gt 2 SETUP must be bigger or equal to two The read cycle demonstrates the max case for CLKOUTI which is 200 MHz and the max case for local EPC max local clk which is 50 MHz SETUP period must be at least 2 SETUP 2 SETUP 2 would give ARDY which is asynchronously enabled by CEO a reasonable delay time 10 ns to be asserted low before the STROBE period starts Also m
11. for PCI master PCI target or PCI master and target applications It is not typical for a PCI host application For a host application LRST is programmed as an input The host s reset output is connected to the EMIF reset input as well as all other system reset pins including the EPC s LRST input LRST output is connected to the PLD reset input and to the EMIF reset input as shown in Figure 3 LBREG LBREG is the EPC s local bus request output pin In the course of PCI to local access through one of the two apertures or a DMA from PCI to local the EPC requests the local bus by asserting the LBREG output signal A local arbiter grants the EPC the local bus by asserting LBGNT input LREQ LREO is the EPC s local request input output pin When the EPC is the local bus master the EPC drives this pin for the whole access period When the EPC is the local bus target the local bus master drives this pin LREO is connected to the PLD LREO I O The PLD drives this pin for EMIF to PCI accesses after the PLD grants the local bus LBGNT is high Otherwise this pin is tristated or driven by the EPC LBGNT The EPC s local bus grant input pin When LBGNT is asserted the EPC is the local bus master and can drive all local bus data address and control signals RDY The EPC s ready input output pin RDY is directly connected to the PLD RDY I O pin For EPC to EMIF accesses the RDY pin is an input The EPC is local bus master the EMIF is local bus target For EM
12. in this application are three SNS4ABT16601 SN74ABT16601 18 bit Universal Bus Transceiver with 3 state outputs from Texas Instruments Note In Table 5 below the AB direction is EPC to EMIF and BA is EMIF to EPC Table 5 Transceiver Function Table A Input B Output AB AB AB A B x H x x X 7 x L H x L L x L H x H H H L L X X Bo H L L X X Bo L L L rising edge L L L L L rising edge H H L L L L X Bo L L L H x Bob a Output level before the indicated steady state input condition were established b Outputlevel before the indicated steady state input conditions were established provided that CLKAB was low before LEAB went low c The shading indicates functionality used in this application note 2000 V3 Semiconductor Corp AN EC6 02 0100 3 Read Write Waveforms Wavetform Notes EPC to SRAM Read Wavetform 4 1 EPC to SRAM Read Waveform EPC to SRAM Read Cycle ice ca EE qe qup pd uy 454 L ESP Lp I f p LBGNT LREQ LA31 2 LD 31 0 BE 3 0 3 070 BE 3 0 1 R W ES emmmm BURST EzzEZEEEEE Dao f X f QGEEEES HOLD i f WE AWE L BHE BLE 3 1 OE NL CS CE1 e A 17 0 D 31 0 OEAB ad be LEAB ad be OEB
13. opens to access the EPC s address and byte enable buses OEAB ad be LEAB ad be If the EPC is granted the bus wait state cycles are inserted waiting for LBGNT to go idle i e not asserted EMIF remains in the STROBE period with ARDY low and the buffers closed When LBGNT goes idle maintain the same order of operation as step 1 1 ARE is asserted a read cycle has started on the EMIF side A read cycle starts on the rising edge of LCLK 1 by asserting LREQ BURST R W The data buffers also open to allow data path from EPC to EMIF data bus Data is latched on the rising edge of each LCLK CLKBAen is asserted Note that if the address and the byte enables buffers were not opened note 1 2 they could be opened also here after the rising edge of LCLK 1 In this case the delay time for the address and the byte enables before the rising edge of Iclk 2 is Tcov pld tpd max ad and be buffers to output EPCtsu ad be 5 6 13 24 ns typically still safe for 40 2 or less For higher frequencies maintain the same order of operation as explained in note 1 and that is the safest design LCLK 3 Data is ready to read from the EPC RDY is asserted on the rising edge of LCLK 3 The data has been latched in the data buffer Latching is disabled CLKBAen is de asserted after this clk The max data delay time from clk to output on the latching buffer the data buffer is 5 2 ns The setup time for ARDY strobe is 5 ns
14. to data valid is 12 ns minimum This is a TI feature 2 DSP data HOLD time after STROBE high is 12 ns This is a TI feature 9 The EPC s data SETUP time is 8 ns This is V3 requirement STROBE HSTRB minimum assertion or de assertion duration time is 2 CLKOUTI cycles At f 200 MHz CLKOUTI 5 ns The assertion or the de assertion period in this design is 1 at least which is 20 ns minimum f 50 MHz EPC max speed HCS HPI Chip select is asserted to start an access when the EPC has been given the bus LBGNT is asserted and the EPC has started the cycle LREO is asserted Only a cycle after LREO is asserted can the PLD determine if the access is to HPI or to SRAM On LCLK 3 the access address is driven on LA 31 2 therefore PLD can decode the access to HPI On LCLK 6 HRDY is asserted therefor we can assert RDY for EPC to read the data on LCLK 7 On LCLK 7 RDY is asserted data is read to the EPC and RDY and HDS signals are de asserted to end the current read cycle There is no race condition between HDS and RDY so PLD delay time is more than enough hold time for the data HRDY might be de asserted on the de assertion of HDS after the transfer of second halfword HRDY might be de asserted on the assertion of HDS in the beginning of a read or a write cycle the first halfword 2000 V3 Semiconductor Corp AN EC6 02 0100 23 Read Write Waveforms Wavetform Notes EPC to HPI Write Waveform 4
15. 01 AWEo when AWEoe 1 else Z Buffers Interface LEBA_DATA lt to xOl LEBA DATAo DATAb lt not to x01 OEBA DATAOo CLKABEN DATAb lt not to 01 DATAo LEAB DATA lt to xOl LEAB DATAOo OEAB lt not to 01 LEAB AD BE lt to xOl LEAB AD OEAB AD BEb lt not to 01 AD BEo 2000 V3 Semiconductor Corp AN EC6 02 0100 33 PLD Source Code VHDL Code LEBA AD BE lt to 01 AD OEBA AD BEb lt not to 01 AD BEo ttt HHE HHE This is the core logic using all active high signals E AE EAE AE AE AE AE E AE FE AE AE AE AE E AE FE AE FE AE FE AE AE AE AE FE AE FE AE FE AE AE E AE FE AE AE E AE AE AE E AE E AE AE AE AE AE AE FE AE FE AE AE E AE AE AE AE AE AE AE FEAE AEAEE EEEE Buffers control OEAB AD lt SRAM CS 1 LEAB AD BEo lt SRAM CS 1 OEBA AD
16. 0100 2000 V3 Semiconductor Corp PLD Source Code VHDL Code Update EPC to SRAM EPC to HPI and EMIF to EPC state machines UPDATE STATES process CLK RESETi begin if RESETi 1 then EPC SRAM CS lt SRAM IDLE EMIF EPC CS lt EMIF EPC IDLE EPC HPI CS EPC HPI IDLE elsif CLK event and CLK 1 then EPC SRAM CS lt EPC SRAM NS EMIF EPC CS lt EMIF EPC 5 EPC HPI CS lt EPC HPI NS end if end process UPDATE STATES to SRAM EMIF HOLDo lt EPC SRAM CS 0 or EPC SRAM CS 1 or EPC SRAM CS 2 1 lt EPC SRAM 5 2 MASK keep asserting 1 for reads strobe for half clock for writes CEloe lt EMIF_HOLDo and EMIF_HOLDAi lt SRAM 5 1 AWEoe lt SRAM 5 1 RDYo lt EPC_SRAM_CS 2 or to SRAM EPC HPI CS 1 and not EPQ HPI CS 0 strobe2 state EPC to HPI RDYoe lt LBGNTo LACH process EPC RWi EMIF_HOLDAi begin if EMIF HOLDAi 0 then lt RWi AWEo lt not EPC RWi end if end process LACH EPC SRAM STM process EPC_SRAM_CS LBREQi LBGNTo LREQi EMIF_HOLDo EMIF_HOLDAi BURSTi A30i assert RDY for EPC and strobe data on first half cycle a write IEPC to SRAM process open buffers and HOLD EMIF from driving it s external bus is requesting the bus constant EPC SRAM IDLE std logic vector 000 constant EPC SRAM ARB std lo
17. 6 EPC to HPI Write Waveform A0 2 EPC to HPI Write Cycle 0 1 2 3 4 5 6 ry 8 9 10 11 12 13 14 15 16 LBREQ ES qm xg Ej z eje 6 lt amp x ic z iz Z Q s a m li lt amp gt d a m E ma 2 r r o 24 AN EC6 02 0100 2000 V3 Semiconductor Corp Programming EPC to HPI Write Waveform EPC to HPI Write Cycle Notes D STROBE HSTRB minimum assertion or de assertion duration time is 2 CLKOUTI cycles At f 200 MHz CLKOUTI 5 ns The assertion and the de assertion of HDS is 1 which is 20 ns minimum f 50 MHz EPC max speed The HOLD time after strobe low is 2 ns The signals strobe on the falling edge of HDS are HCNTL HHWIL HR W SETUP time for the signals strobe is1 ns from the falling edge of HDS Data and byte enables strobe is on the rising edge of HDS The HOLD time required is 1 ns HDS is negatively gated with LCLK 5 so the rising edge of HDS is on the falling edge of LCLK 5 5 which provides 10 less Tcov pld HOLD time HCS HPI Chip select is asserted to start an access when the EPC has been given the bus LBGNT is asserted and the EPC has started the cycle LREQ is asserted Only a cycle after LREQ is asserted can the PLD determine if the access is to HPI or to SRAM On LCLK 3 the access address is driven on LA 31 2 therefore PLD can decode the access to the HPI 5 0 Pr
18. A data 2 __ lt __ LEBA data ee 4 6 02 0100 2000 V3 Semiconductor Corp Read and Write Waveforms and Waveform Notes EPC to SRAM Read Waveform EPC to SRAM Read Cycle Notes D At LCLK 2 after the EPC has granted the BUS LBGNT is asserted low the EPC starts the cycle by asserting LREQ and driving the address bus On the rising edge of LCLK 3 the PLD decodes the address to the HPI or SRAM access according to the aperture programming When it decodes SRAM access the HOLD signal to EMIF control is asserted low When the EMIF is ready to give up the external bus it asserts HOLDA asynchronously to LCLK At LCLK 4 the EPC has granted the external bus HOLDA asserted low Since it is a read access the address byte enables are opened for the EPC to SRAM data path The data buffers are opened for the SRAM to EPC data path The WE signal is de asserted high the OE output enable is asserted low The maximum address access time for IDT71V416 SRAM is 15 ns The delay time from the time the buffer is opened until the output is stable for TI 18 bit universal transceiver bus SN54ABT16601 SN74ABT16601 is 6 ns max worst case The worst case scenario for the data to be ready is 21 ns plus the PLD s CLK to OUT typically 5 ns totalling 26 ns Therefore you should sample data on the rising edge of LCLK 6 not LCLK 5 giving almost the entire cycle as margin In an application where a slower LCLK is used
19. Application Note Interfacing the 5320 6 DSP to the PCI bus using the V360EPC Controller 1 0 Objective This application note describes how to interface Texas Instrument s TMS320C62x C67x Digital Signal Processor DSP to the PCI bus using the V360EPC Enhanced PCI Controller from V3 Semiconductor Throughout this document references are made to the operation of the V360EPC and TMS320C6201 Basic familiarity with these devices is assumed If you do not have the relevant data sheets or User s Manual for the V360EPC you may download them from the V3 Semiconductor web site at http www vcubed com products chips epc htm 2 0 Overview The TMS320C62x C67x has two independent interfaces the Host Processor Interface HPI and the External Memory Interface EMIF On the EMIF bus we have used asynchronous SRAM as shared memory between the DSP and PCI Other memories such as SDRAM and SBSRAM can also be accessed by the DSP via the EMIF bus A PCI bus agent is able to access both the shared memory SRAM and the DSP s internal memory CPU internal memory Accessing the SRAM is accomplished by using the EMIF external bus An access to the internal memory is accomplished by accessing the HPI The DSP is able to access the shared memory through its EMIF interface It is also able to access a PCI slave agent through the same interface The V360EPC bridge from V3 semiconductor provides the highest performance V3 Semiconductor
20. C HPIA or HPID HCNTL input pins decode which of the three registers is being accessed These two pins are directly connected to the PLD HCNTL 1 0 output pins For more details see Section 5 0 Programming HHWIL The 5 halfword input pin It indicates whether the first or the second halfword is being transferred An internal control register bit determines whether the first or the second halfword is placed into the most significant halfword of a word In a 16 bit region the EPC s BWE1 behaves like A1 low for the first 16 bits in a word and high for the second halfword which means they can be directly connected HR W The 5 read not write input Although this pin be directly connected to the EPC s R W it needs to be driven from the PLD for this application HDS1 HDS2 The data strobe input signals Either signal asserted together with the assertion of HCS can generate an internal strobe signal Both of them are not necessary to generate the strobe signal This is why one of them is driven from the PLD and the other is disabled by a pull up resistor For this application HDS1 is driven from PLD and HDS2 is pulled high Note HSTRB is the strobe signal not HDS1 HDS2 When HDS1 is asserted there is delay before HSTRB is asserted Refer to the HPI internal signal description in User s Manual HCS The chip select input pin HCS has to be asserted to access the HPI This p
21. Company is a registered trademark of V3 Semiconductor Motorola is a trademark or registered trademark of Motorola Inc other trademarks are the property of their respective owners V3 Semiconductor reserves the right to make changes to its products or specifications at any time without notice i n order to improve design or performance and to supply the best possible product V3 does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a V3 product The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent patent rights or other rights of V3 Semiconductor 2000 V3 Semiconductor Corp AN EC6 02 0100 39
22. E Program BE OMODE 1 in register for normal 202 mode operation Aperture Programming Example PCI BASE 0x5A500008 Prefetch is on PCI MAPI 0xA5A00003 Aperurel size is 1 MB aperture and register are enabled PCI BASEO 0x80000008 PCI 0x400000A3 or since we are using A30 to decode access we may also use 00000 3 the A31 value is don t care AperureO size is 1 GB aperture and register are enabled LB SIZE 0x00300000 We have programmed the region to be 16 bit unpacked The reason it should be unpacked is that accesses must be comprised of two 16 bit accesses the higher bytes and the lower bytes in a word This is true even if one half of the word either the higher 16 bit or the lower 16 bit has no data to deliver The internal data boundary is 32 bits one Word so the first access is the higher or the upper half of the word upper or lower is programmable in the DSP In packed mode the halfword which does not have data is deleted and another halfword from the next word replaces it This packing feature uses the maximum 16 bit bus bandwidth however we cannot use this feature in this design because the DSP internal bus has a 32 bit not a 16 bit word boundary 2000 V3 Semiconductor Corp AN EC6 02 0100 27 Programming PCI to SRAM 5 2 5 3 to SRAM Aperture 0 is dedicated to PCI to SRAM accesses There are no EPC programming issues that are not mentioned in Secti
23. IF to EPC accesses the RDY pin is an output Please see the EPC to HPI Read Waveform EPC to HPI Write Waveform EPC to SRAM Read Waveform and EPC to SRAM Write Waveform to see when this pin is driven by the PLD 8 AN EC6 02 0100 2000 V3 Semiconductor Corp Interconnection V360EPC Local bus Interface Signals Connection For EMIF to PCI write cycles the EPC has large write FIFOs which can queue up to 256 words in a sustained burst The RDY signal is asserted for as long as 1 KB burst transfer This feature provides higher performance local and PCI bus bandwidth For read cycles the has an 8 word prefetch FIFO dedicated to each aperture 16 words for both apertures The two apertures have posted read cycles at the same time While a read access is in the ready stage i e RDY is being asserted and data is driven from the prefetch buffer of one aperture the other aperture posted read cycle may be in the read prefetch stage on the PCI bus When the first read access finishes the second read access continues without the EPC dropping LBREQ thus providing back to back access RDY is de asserted to end the first access then driven again for the second read access This feature is called multiple posted reads BURST The EPC s burst input output pin This pin is driven high for non burst accesses and low for a burst access For burst access it is driven high just one word prior to the last data in the burst This pin is directly
24. LBREOb LBGNTb LREQb RDYb BURSTb EPC_RWb A2 18 19 HCNTL HPI_RWb HDSb HCSb HRDYb EMIF_HOLDb EMIF_HOLDAb CEOb 1 ARDY AOEb AWED AREb in in in zout inout inout inout inout in sin zout out zout std std std std std std std std std std std std Std std std std std ogic ogic ogic ogic ogic ogic ogic ogic ogic ogic ogic ogic ogic vector 1 downto 0 ogic can be directly connected ogic ogic ogic Q p a I LEBA DATA OEBA DATAb for EMIF to EPC reads rout zout std logic std logic latching register is included in this case only and CLKABEN DATAb out LEAB DATA out std logic std logic 30 AN EC6 02 0100 2000 V3 Semiconductor Corp DATAb OEAB AD LEBA AD BE OEBA AD BEb end ti epc out std logic out std logic out std logic out std logic out std logic Inputs signa signa signa signa signa signa signa Outputs signa signa signa signa signa signa signa signa signa signa signa signa signa signa signa signa Inputs signa signa signa signa signa signa Outputs signa signa signa RESETi LBREQi LREQi RDYi BURSTi EPC RWi A2i A18i A19i A30i LBGNTo LREQo LREQoe BURSTo BURST
25. ROBE EMIF_EPC_WAIT4B2B case EMIF_EPC_CS is when EMIF_EPC_IDLE gt if CEOi and EMIF has priority AREi AWEi CEOi not LBGNTo RDYi LBGNTo LREQ BURST R W buffers enable Wait for ready during the cycle or check if there is back to back access after the end of the cycle ADD BE buffer enable std_ulogic_vector 0000 std_ulogic_vector 0001 std ulogic vector 0101 std ulogic vector 0111 std ulogic vector 1000 ulogic vector 0010 1 then no need to check that LBREQ is asserted EMIF EPC NS EMIF EPC OPEN BUF else EMIF EPC NS EMIF EPC IDLE end if when EMIF EPC OPEN BUF gt read cycel NS EMIF EPC STARTCY if AREi 1 then EPC RWo lt 1 elsif AWEi 1 then RWo lt 0 write cycle EMIF_EPC_NS lt EMIF_EPC_STARTCY else strobe has not been asserted yet SETUP is too long 36 AN EC6 02 0100 2000 V3 Semiconductor Corp PLD Source Code VHDL Code EMIF EPC NS EMIF EPC OPEN BUF end if when EMIF EPC STARTCY gt EMIF NS EMIF EPC WAITARDY when EMIF_EPC_WAIT4RDY gt if RDYi 1 then EMIF EPC NS lt EMIF STROBE else EMIF NS lt WAITA4RDY wait for EPC to assert RDY end if when EMIF EPC STROBE gt if AWEi or AREi 1 then write or read for read access strobe i
26. aintain the same order of operation when using SETUP period less than 6 since SETUP period won t be detectable for sure Meaning after LCLK 0 open the address and byte enable buffers even though the ARE signal would be already asserted and on LCLK 1 start the cycle on EPC side by asserting LREO and the other control signals Don t shave off a cycle by opening the address AN EC6 02 0100 2000 V3 Semiconductor Corp Read and Write Waveforms and Waveform Notes EMIF to EPC Read Waveform byte enable buffers and LREQ on the same clock Otherwise you would need to take into consideration the PLD clock to out the buffers delay time and the EPC s address and byte enables setup time On 50 MHz LCLK that is not feasible Note If you want to detect the SETUP period for sure choose SETUP 6 or bigger for the same frequencies 2 LCLK 0 CEO is asserted On the rising edge of LCLK 0 PLD detects EMIF is in the SET UP period for an EMIF to EPC access cycle or in the STROBE period if you choose 2 SETUP 6 less than six but bigger or equal to 2 If LBGNT is not asserted meaning EPC has not granted the bus EMIF can access the EPC bus by enabling the address and byte enables buffers Otherwise EMIF is held the in the STROBE period with wait states inserted and the address and byte enable buffers closed LCLK 1 If LBGNT is not asserted the EPC has not granted the bus EMIF to EPC access can proceed The address and byte enable buffer
27. al addresses of HPIC HPIA and then continue the sequential addresses up to 1 Mbit 125 KB of HPID by using the DSP s address increment feature In total 128 KB of sequential data address are needed following the HPIC and HPIA addresses You can also access 128 KB of the processor internal memory without address increments in a sustain burst fashion Single cycles are always able to access any of the registers In order to achieve full performance of the DSP as described above use the 1 MB aperture size The 1 MB aperture size is the minimum available Use 256 KB for incremented or non incremented addresses and 2 addresses for HPIC and HPIA registers 512 KB 8 bytes is be used Table 6 Address Decoding describes how to design the system Table 6 Address Decoding A30 A19 A18 A3 2 Register Aperture 0 0 x x 0 HPIC Aperture 1 0 0 x x 1 HPIA Aperture 1 0 0 x x 0 HPIC Aperture 1 0 0 x x 1 HPIA Aperture 1 0 1 0 x x HPID with increment b Aperture 1 0 1 1 x x HPID with no increment Aperture 1 1 x x x x 2 0 You may select bit from A20 to A31 to determine accesses to HPI or SRAM Choosing A30 provides maximum flexibility if a 1 GB SRAM aperture is to be used see the Aperture Programming Example on page 27 For best performance with longer burst accesses the addresses of HPIC HPIA and HPID should be sequential especially when using the following address increments
28. ddress register followed by accesses to the HPID For further information about the HPI please refer to TMS320C6201 C6701 Peripheral Reference Guide literature number SPRU190 from Texas Instruments Table 2 describes all of the HPI interface signals Table 2 HPI Interface Signals Signal Description HD 15 0 16 bit data bus R W Read not write signal 4 AN EC6 02 0100 2000 V3 Semiconductor Corp Overview TMS320C6x Overview Table 2 HPI Interface Signals Signal Description HDST HDS12 Strobe signals 24 22 e either of these HCS Acts like chip select Controls strobe signals functions in conjunction with HDS1 and HDS2 strobe signals HAS Address latch enable could be tied high see the TI datasheet HBE 1 0 Byte enables HRDY Host Asynchronous ready output HINT Host interrupt output EMIF External Memory Interface The External Memory Interface is used by the CPU to interface off chip memory The EMIF supports a variety of external devices e Synchronous burst SRAM SBSRAM running at 1 x and 1 2 x CPU clock rate e Synchronous DRAM SDRAM running at 1 2 x CPU clock rate e Asynchronous devices including asynchronous SRAM ROM and FIFOs The EMIF responds to requests on the external bus from four requesters e The program memory controller that services the CPU program fetches on the DSP e The data mem
29. gic vector 001 ask for EMIF bus assert HOLD and wait for HOLDA mE constant EPC SRAM WAIT std logic vector 011 E constant SRAM STROBE logic vector 110 constant EPC SRAM END std logic vector 010 begin case EPC SRAM CS is when EPC SRAM IDLE if LBREQi and LBGNTo and LREQi and A30i 1 then Access to SRAM EPC SRAM NS lt SRAM ARB else EPC SRAM NS lt EPC SRAM wait until LREQ is asseted to start cycle end if when EPC SRAM ARB gt if EMIF HOLDAi 1 then EPC SRAM NS EPC SRAM WAIT 2000 V3 Semiconductor Corp AN EC6 02 0100 35 PLD Source Code VHDL Code else EPC_SRAM_NS lt end if when EPC_SRAM_WAIT gt EPC_SRAM_NS lt when EPC_SRAM_STROBE gt if BURSTi 1 then EPC SRAM NS else EPC SRAM NS end if when EPC SRAM END gt EPC SRAM NS when others SRAM SRAM STROBE EPC SRAM WAIT EPC SRAM IDLE EPC SRAM IDLE EPC SRAM NS EPC SRAM IDLE end case end process EPC SRAM STM LREQo LREQoe BURSTo BURSToe EPC_RWoe ARDYo ARDYoe EMIF STM ARDY constant constant constant constant constant constant begin lt EMIF_EPC_CS 2 lt not LBGNTo lt 0 lt not LBGNTo lt not LBGNTo lt EMIF_EPC_CS 3 lt CEOi process EMIF_EPC_CS EMIF_EPC_IDLE EMIF_EPC_OPEN_BUF EMIF_EPC_STARTCY EMIF_EPC_WAIT4RDY EMIF_EPC_ST
30. gnal Type Description Ready Active high asynchronous ready input used to insert wait ARDY l states for slow memories and peripherals AOE Active low output enable AWE Active low output write strobe ARE Active low read strobe AN EC6 02 0100 2000 V3 Semiconductor Corp Overview TMS320C6x Overview Figure 3 TMS320C6201 to V360EPC Interconnection LRST LBREQ LBGNT LREQ RDY BURST R Wb BWE 3 0 LD 15 0 V360EPC EA 21 2 BE 2 3 SM 2000 V3 Semiconductor Corp AN EC6 02 0100 7 Interconnection V360EPC Local bus Interface Signals Connection 3 0 Interconnection The interface between the TMS320C6201 and the V360EPC is shown in Figure 3 TMS320C6201 to V360EPC Interconnection The full description of the signal connections follows 3 1 V360EPC Local bus Interface Signals Connection LRST LRST is the EPC s reset input output LRST can be initialized to either input by pulling the RDIR pin low or output by pulling the RDIR pin high In this application LRST is initialized to be an output on the local bus This is typical
31. in is directly connected to the PLD HAS The HPT s address latch enable input pin For this application this input is disabled by a pull up resistor HRDY The 5 ready output pin This pin is directly connected to the PLD AN EC6 02 0100 2000 V3 Semiconductor Corp 3 3 Interconnection EMIF Interface Interconnect HBE 1 0 The HPT s byte enable inputs For a write access it determines which byte to write in a halfword For a read access the HPI reads 16 bits regardless of the byte enable value HBE 0 is connected to BWEO and HBE 1 is connected to HD 15 0 The HPT s 16 bit data bus I O It is directly connected to LD 15 0 EMIF Interface Interconnect The EMIF has three control signal groups Asynchronous Memory controller SBSRAM e SDRAM Note This application note only describes the Asynchronous Controller connections no other memory devices are being used on the EMIF bus Connecting additional memory devices SDRAM or 5 5 will not affect the design provided they are mapped to different CE space not CEO or CEI HOLD The EMIF s bus request input An external device can request the EMIF bus by asserting this input For an EPC to SRAM access the PLD asserts this input This pin is directly connected to the PLD HOLDA The EMIF s bus acknowledge output In order to enable an external bus master to use the EMIF bus the EMIF relinquishes its bus tristates all its out
32. less than 40 MHz you may strobe data on the rising edge of LCLK 5 However it is better to have the cycle as margin in case of slower SRAMs buffers or PLD On LCLK 6 data is read to the EPC RDY is asserted On a burst it takes on the worst case EPC 15 ns max delay time for the next address and byte enables to be stable The delay time from change in the input to the output of the address and byte enable buffers is 5 ns maximum for 18 bit universal transceiver bus SN54ABT16601 SN74ABT16601 The maximum address access time for the IDT71V416 SRAM is 15 ns Worse case is that it takes 35 ns for the subsequent data to be ready to strobe Therefore strobe data on the rising edge of LCLK 8 not LCLK 7 unless LCLK is less than 28 MHz 2000 V3 Semiconductor Corp AN EC6 02 0100 IS Read Write Waveforms Wavetform Notes EPC to SRAM Write Waveform 4 2 EPC to SRAM Write Waveform EPC to SRAM write cycle ex I LILI LLU UDO UD LBREQ LBGNT Lud LRA v LA31 2 LD 31 0 D X D BE 3 0 RW a ES BURST NEEEENNEDOO 07 annum 7 t oe ij HOLD A ACE CS CE1 sO V 17 0 D 31 0 OEAB ad be data X LEAB ad be data 16 6 02 0100 2000 V3 Semiconductor Corp Read and Write Waveforms and Waveform Notes EPC to SRAM Write Waveform EPC to SRAM Write Cycle Notes D Afte
33. lt EMIF EPC CS 0 LEBA AD BEo lt EMIF EPC CS 0 DATAo lt EPC SRAM 5 1 and not EPC RWi or AREi AOEi 01 LEAB DATAo lt EPC SRAM CS 1 and not EPC RWi CLKABEN DATAo EMIF EPC CS 2 and EPC RWo OEBA DATAo lt EPC SRAM CS 1 and EPC RWi or EMIF EPC CS 2 and EPC RWo LEBA DATAo lt EPC SRAM CS 1 and not EPC RWi or EMIF EPC CS 2 and not EPC RWo Arbitration process EMIF can always access EPC s local EMIF to EPC buffers direction and isolation control EPC to SRAM EPC to SRAM EMIF to EPC EMIF to EPC EPC to SRAM EMIF to EPC EPC to SRAM EMIF to EPC EPC to SRAM EMIF to EPC EPC to SRAM EMIF to EPC bus read and write read and write AB direction on writes read AB on writes only read clocking latch only write write If EMIF does not need to access EPC s local bus and EPC needs to access local bus for HPI or SRAM accesses the arbiter grants the EPC the local bus ARB process CLK RESETi variable ARB NS std ulogic begin if RESETi 1 then ARB CS lt 0 elsif CLK event and case ARB CS is when 0 gt if LBREQi and not CE0i 1 ARB NS 1 else ARB NS 0 end if when 1 gt if LBREQi 0 then ARB NS 0 else ARB NS 1 end if when others ARB_NS 0 end case CLK 1 then then end if ARB_CS lt ARB_NS end process ARB 34 AN EC6 02
34. miconductor Corp 6 02 0100 37 PLD Source Code VHDL Code HCNTLo lt 10 without increment end if else if 21 1 then HCNTLo lt 01 1 HCNTLo lt 00 end if end if process hcntl decoding HPI RWo lt EPC RWi directly connected HPI RWoe lt HCSo constant EPC IDLE std ulogic vector 000 m constant EPC HPI STARTCY std ulogic vecto 001 constant EPC 1 std_ulogic_vecto 011 constant EPC HPI STROBE2 ulogic vecto O10 constant EPC HPI DEASTROB std ulogic vector 100 EPC HPI STM process EPC HPI CS LBGNTo LREQi BURSTi EPC RWi HRDYi NOT LAST A30i begin case EPC HPI CS is when EPC HPI IDLE gt if LREQi and LBGNTo and not A30i 1 then Access to HPI HPI NS lt EPC STARTCY else EPC HPI NS EPC HPI IDLE end if when EPC HPI STARTCY gt EPC HPI NS lt EPC_HPI_STROBE1 when EPC_HPI_STROBE1 gt when when if HRDYi 1 then EPC HPI NS EPC HPI STROBE2 else HPI NS lt EPC_HPI_STROBE1 end if EPC HPI STROBE2 gt EPC HPI NS EPC HPI DEASTROB De assert strobe if BURSTi 1 then NOT LAST lt 1 there is another 16 bit transfer else NOT LAST 0 last 16 bit transfer end if HPI DEASTROB gt if NOT LAST 1 then another 16 bit transfer a sec
35. ns max Tcov max 14 ns see the EPC data sheet plus the PLD delay enables us to use asynchronous ARDY assertion with RDY assertion on 50 MHz Thus ARDY is asserted high for 1 clock after the cycle has ended on the EPC side CEO is de asserted after 3 CLKOUT1 clocks from the end of the HOLD period when HOLD is greater than 0 and 4 clocks if HOLD 0 In the waveform HOLD 1 so the CEO is de asserted on CLKOUTI 20 20 17 3 After the HOLD period if there is a back to back cycle CEO is not de asserted and the SETUP period for the next access starts immediately after HOLD ARDY is asynchronously asserted low with CEO assertion in order to prevent the EMIF from proceeding in the STROBE period without getting synchronized with the EPC ARDY is tristated to high Z asynchronously with de assertion 2000 V3 Semiconductor Corp AN EC6 02 0100 21 Read Write Waveforms Wavetform Notes EPC to HPI Read Waveform 4 5 EPC to HPI Read Waveform 17 16 15 14 13 12 11 10 j E E o gt o oO e I a na 2 x gjg 8 E j s S 2 ic 12 z oO 5 2 Z ul aia d I I 22 AN EC6 02 0100 2000 V3 Semiconductor Corp Read and Write Waveforms and Waveform Notes EPC to HPI Read Waveform Read Cycle Notes D STROBE low
36. oe EPC_RWo EPC_RWoe HRDYi HCNTLo HCNTLoe HPI RWo HPI RWoe HDSo HCSo HOLDAi CEOi AREi CEli AOEi AWEi EMIF_HOLDo ARDYo ARDYoe 25 25 is s s 25 25 std u std u std u std u std_u std_u std u std std ulogic std ulogic std ulogic std ulogic std ulogic std ulogic std ulogic std ulogic std ulogic std ulogic std ulogic std ulogic std ulogic std ulogic std ulogic std ulogic td ulogic td ulogic vector 1 downto 0 td ulogic td ulogic td ulogic td ulogic td ulogic Directly connected logic logic logic logic logic logic logic logic logic PLD Source Code VHDL Code 2000 V3 Semiconductor Corp AN EC6 02 0100 3l PLD Source Code VHDL Code signal CElo signal CEloe signal signal signal AWEo signal AWEoe signa signa signa signa signa signa signa signa signa LEBA_DATAo OEBA_DATAo CLKABEN_DATAo LEAB_DATAo OEAB_DATAo LEAB_AD_BEo OEAB_AD_BEo LEBA_AD_BEo OEBA_AD_BEo std_u std_u std u std u std std_u std_u std u reta u Signal ARB CS Signal EPC SRAM 5 SRAM NS constant constant constant constant EPC SRAM IDLE EPC SRAM ARB EPC SRAM WAIT SRAM STROBE signal EPC CS EMIF EPC NS constant constant constant constant constant constant EMIF IDLE EMIF EPC OPEN BUF EMIF
37. ogramming Programming the EPC and TMS320C6 involves programming a number of registers This chapter describes only those which have a direct effect on the hardware design of this application The V360EPC has two programmable apertures to access the local bus from PCI and two programmable apertures to access PCI from the local bus This application accesses two peripherals on the local bus from PCI the HPI the DSP s Host Processor Interface and SRAM memory Other memory peripherals residing on the EMIF bus like SDRAM or SBSRAM may be accessed from PCI This application uses the asynchronous SRAM interface since it is the most common application For SRAM accesses define one PCI to Local aperture for HPI and the other as a PCI to Local aperture Both apertures are identical there is no advantage to using one or the other 1 PCI accesses HPI through aperture 1 2 PCI accesses SRAM through aperture 0 Bit 30 on the local bus determines which aperture is accessed See Table 6 Address Decoding on page 26 2000 V3 Semiconductor Corp AN EC6 02 0100 25 Programming PCI to HPI 5 1 PCI to HPI Maintain the EPC burst for best performance and maximum utilization of the local bus when EPC is accessing HPI Use the following burst format HPIA HPID HPID HPID up to 1Mbyte data Where HPIC is the control register HPIA is the address register and HPID is the data register This access format is possible if you use two sequenti
38. on 5 1 to HPI EMIF to PCI For EMIF to PCI accesses CEO is mapped for EMIF to PCI memory space and is mapped to SRAM memory space When EMIF wants to access PCI it drives CEO low and drives the address bus EA 21 2 The EMIF address bus EA 21 2 is connected to LA 21 2 through the address buffers The EPC s LA 22 31 higher address bits are not being used when the EPC is the target so pull these bits up With the pull ups in place address decoding of LB BASEO or LB BASE depends on bit 21 The address decoding uses a minimum aperture size of 1 MB which decodes the address bits 31 20 Bits 31 22 are pulled high leaving bit 21 for decoding a 1 aperture If you need a 2 MB aperture enable bit A30 as an output bit instead of pulling it high Then drive it when the PLD decodes an access to the EPC CEO is being driven This application uses a 1 MB Local to PCI aperture size LB BASEn so LA 31 22 is pulled up When EA 21 1 the EPC decodes an access to PCI through the aperture LB BASEO LB BASEO OxFFF00000 28 AN EC6 02 0100 2000 V3 Semiconductor Corp PLD Source Code VHDL Conventions 6 0 PLD Source Code 6 1 The following source code is written in VHDL VHDL Conventions There are some conventions that have been used in writing the VHDL equations that help to make them more readable Signal names are all in upper case except as outlined below Signals that are active low TSb BWEb
39. ond in a one word or the first in a next word transfer when EPC HPI NS lt EPC HPI 5 1 else EPC HPI NS EPC HPI IDLE end if others gt EPC HPI NS EPC HPI IDLE end case end process EPC HPI STM MASK PAR EPC HPI CS 1 and not EPC HPI CS 0 or EPC SRAM CS 2 MASK a half a cycle of the strobe for writes when accessing SRAM or HPI HALF process CLK EPC HPI CS 0 EPC HPI CS 1 38 AN EC6 02 0100 2000 V3 Semiconductor Corp Conclusion VHDL Code begin if CLK event and CLK 0 then if MASK PAR and not EPC RWi 1 then When strobe and the cycle is write MASK lt 0 else MASK lt 1 end if end if end process HALF end behavior 7 0 Conclusion The V360EPC PCI Bridge Controller is highly recommended as both PCI master and target bridge for high performance DSP applications For EMIF External Memory Interface to PCI the V36OEPC acts as a local bus target and at the same time as PCI master For PCI to HPI Host Processor Interface or PCI to a shared memory residing on the EMIF bus SRAM in this application the EPC acts as PCI target and as the local bus master Using isolation buffers allows concurrent accesses between PCI to HPI and EMIF to it s external memory devices With a small 32 microcell PLD the V360EPC easily connects the TMS320C6x DSP EMIF and HPI interfaces to the PCI bus V3 Semiconductor 2000 The Embedded Intelligence
40. ory controller that services CPU data fetches on the DSP e The DSP s DMA controller e An external shared memory device The last option allows access to the shared memory from the PCI bus An external device can request the external bus from EMIF by asserting HOLD input In this application note the V360EPC requests the external bus to access SRAM When the EMIF is ready it asserts HOLDA All EMIF control and data outputs are tristated at this stage The EMIF has both generic shared signals and specific control signals to accommodate each external device Table 3 shows the shared signals for all external devices Four programmable memory spaces can be accessed through CE 3 0 chip enable For the current application program the EMIF CE Space Control Register so that CEO corresponds to SRAM memory and CE1 corresponds to the PCI bus local to PCI accesses 2000 V3 Semiconductor Corp AN EC6 02 0100 5 Overview TMS320C6x Overview Table 3 EMIF Shared Signals Signal Type Description ED 31 0 y o 32 bit data input output from external memories and peripherals 21 2 External address output CE 3 0 Active low chip select for memory for the four memory spaces BE 3 0 Byte enables The signals listed in Table 4 are specific to the asynchronous external device interface and are in addition to the shared signals shown in Table 3 above Table 4 EMIF Asynchronous Interface Signals Si
41. puts and asserts HOLDA This pin is directly connected to the PLD ED 31 0 The EMIF s 31 bit data bus I O This pin is connected to LD 31 0 through the data buffers EA 21 2 The EMIF s 19 bit address bus output This is connected to LA 21 2 through the address buffers BE 3 0 The EMIF s 4 bit byte enables output These pins are connected to BWE 3 0 through byte enable buffers 2000 V3 Semiconductor Corp AN EC6 02 0100 Interconnection EMIF Interface Interconnect CE 3 0 The EMIFs chip enable output PCI is mapped to CE0 and SRAM is mapped to CEO is connected to the PLD and 1 is connected to the SRAM chip enable and are not mapped in this application They are optional and may be mapped to SDRAM SBSRAM or a second PCI aperture RESET Chip reset input This pin is directly connected to LRST output ARDY The EMIF asynchronous ready output This pin is directly connected to the PLD AOE The EMIF asynchronous output enable This pin is directly connected to the SRAM s OE pin and to the PLD AWE The EMIF s asynchronous write enable output This pin is directly connected to the SRAM s W R pin ARE The EMIF asynchronous read enable output This pin is directly connected to the PLD AN EC6 02 0100 2000 V3 Semiconductor Corp Read and Write Waveforms and Waveform Notes EMIF Interface Interconnect 4 0 Read and Write Waveforms and Waveform Notes The buffers used
42. r Enhanced PCI Controller The eine V360EPC can act as PCI bus master PCI slave or PCI host bridge In this application the DSP acts as the PCI master controlling the PCI bus through Local Bus the EMIF bus The EPC acts as the EMIF target on the EPC s local bus HPI The EPC is a PCI target when an agent on PCI bus is accessing the HPI interface or the shared memory For the shared memory accesses the EPC requests the EMIF external bus the EMIF relinquishes the bus when it is ready The DSP is Eel Ter EE Dae Eis parked on the EMIF bus unless an external master like the EPC requests ownership of the bus TMS320C6x E 2 o 2 o E The EPC has two programmable apertures for accesses from PCI to the local bus One aperture is programmed to access the HPI while the other is programmed to access the shared memory The apertures are size programmable for up 2 Gbytes They are also bus size programmable to 8 16 or 32 bit bus size For accessing the HPI which is a 16 bit wide bus an aperture can comfortably be programmed to 16 bit bus in the SIZE register Accesses to the SRAM can be programmed to 32 bit bus wide which is the default setting in the registers An access to the aperture can be as long as a 1 KB burst The V360EPC has 640 bytes of programmable FIFOs to accommodate bursts An access from PCI to local or local to PCI may also be established with the same aperture performance levels thro
43. r LCLK 2 Where EPC has granted the BUS LBGNT is asserted low EPC starts the cycle by asserting LREO and driving the address bus On the rising edge of LCLK 3 the PLD decodes the address to HPI or SRAM access according to the aperture programming When it decodes SRAM access HOLD to EMIF control is asserted high When the EMIF is ready to give up the external bus it asserts back HOLDA asynchronous to LCLK On LCLK 4 EPC has granted the external bus HOLDA is asserted high Since it is a write access the address byte enables and data buffers are opened for EPC to SRAM data and address paths The WE write signal is asserted low OE output enable is de asserted high it is not a read cycle After LCLK 4 CE is sequentially driven high for one cycle and gate NOT with the in the next cycle CE ends its sequential behavior when the access ends on LCLK 8 On LCLK 8 BURST is de asserted high and RDY is asserted low indicating the end of access On LCLK 6 data has already been written to SRAM RDY is asserted in order to end the cycle for the next write cycle in a burst access or to end the access if it s not a burst In this case it s a burst access the address and the data of the next write cycle is driven by the EPC Ona burst it takes worst case Tcov EPC 15 ns delay time for the next address byte enables and the data to be stable The delay time from change in the input to output valid for the address byte enables and
44. s deasserted EMIF EPC NS lt EPC WAITA4B2B else EMIF EPC NS EMIF EPC STROBE Remain in the strobe state the strobe has not finished yet more strobes are required this would happen if strobe 1 for writes strobe gt 3 for reads end if when EMIF_EPC_WAIT4B2B gt if CEOi 1 then end of access EPC NS lt EMIF EPC IDLE elsif AREi or AWEi 1 then another strobe is strobed do another access to EPC EMIF EPC NS lt EPC OPEN BUF else EMIF EPC NS EMIF EPC WAIT4B2B HOLD is too long or EMIF is waiting to exit a read cycle seven minus HOLD before CE is deasserted end if when others EPC NS lt EMIF EPC IDLE end case end process EMIF EPC 5 5 lt HPI 5 1 and MASK HDSo lt 5 1 FPC_RWi read strobe or EPC HPI CS 0 HPI 5 1 or EPC HPI CS 1 not EPC HPI 5 0 and CLK Second strobe a read de assert after half a cycle HCSo lt EPC HPI CS 2 All the state apart from the IDLE state or EPC HPI CS 1 or EPC HPI CS 0 HCNTLoe lt HCSo HCNTLo lt 19 amp 181 and A19i or 0 amp 21 and not 19 hcntl decoding process A19i A18i A2i Decoding the HPIA HPIC HPID begin if A19i 1 then if 181 1 then HCNTLo lt 11 with increment else 2000 V3 Se
45. shes the local bus if the EPC is currently accessing the HPI bus otherwise buffers may be opened immediately Figure 1 High Performance Design Using Buffers When the buffers are closed the following is true The buffers are tristated on both buses The EPC HPI access is enabled when the EPC requests it and the EMIF is not requesting it V360EPC e The EMIF to external bus is enabled by default Local Bus Because concurrence is not needed the design shown in Figure 2 omits this option When the PCI agent requires access to the HPI the EPC sends a request Buffers TMS320C6x to the EMIF to relinquish its external bus In this design there is no need for buffers Em to isolate the two buses as only one master at a time is driving the bus HPI External Memory Interface Data Bus In an application where PCI to HPI accesses are limited the design shown in Figure 2 is easier and more cost effective SDRAM to implement Please note the following SBSHAM PCI to HPI also holds the EMIF bus as does HOLDA e access to any of its local bus memory peripherals SRAM SDRAM or SBSRAM holds the EPC from accessing HPI or SRAM The EPC does not get LBGNT until the EMIF is done 2 AN EC6 02 0100 2000 V3 Semiconductor Corp 2 1 Overview V360EPC Overview Figure 2 Direct Connect Design e Waveforms for the direct connect design variation are not included PCI Bus V360EPC Overview EPC stands fo
46. ugh either of the EPC s two DMA engines Setting the DMA channels allows large blocks of data to be transferred to the shared memory or to the CPU s internal memory space The EPC has two programmable apertures for accesses from local to PCI PCI space can be mapped to CEO in the EMIF memory space An EMIF access to the CEO region is decoded as local to PCI access by the EPC You may program other regions in the EMIF space to be decoded as local to PCI access by using the other local to PCI aperture For example CEO local to PCI aperureO CE2 local to PCI apertuel The V360EPC has demultiplexed address and data buses which follow the AMD29k interface protocol The EPC can run at up to 50 MHz up 40 MHz at 3 3 volts It is bootable through the EEPROM the PCI bus or the local processor The EPC is fully compliant with the PCI 2 1 Target Specification and is Hot Swap Capable according to the PICMG M Hot Swap Specification 2000 V3 Semiconductor Corp AN EC6 02 0100 3 Overview TMS320C6x Overview 2 2 TMS320C6x Overview The TMS320C6x has two independent interfaces the HPI Host Processor Interface and the EMIF External Memory Interface HPI Host Processor Interface The HPI is a target only asynchronous interface through which the host processor accesses the CPU s internal memory space In this application the host processor could be a PCI agent which accesses the HPI through the V360EPC PCI bridge The HPI is a 16 bit wide data b
47. us HD 15 0 Note Due to the 32 bit word structure of the DSP architecture all transfers with the host consist of two consecutive 16 bit halfwords The HPI accesses to the internal CPU space are through three registers the HPIA Host Processor Interface Address register the HPID Host Processor Interface Data register and the HPIC Host Processor Interface Controller register An access to any of the registers must consist of two consecutive 16 bit accesses The HPI does not have an address bus instead it has an address register HPIA The address register HPIA provides the address for any transfer from the HPI to the internal memory space The HPIA can be programmed to increment for each access to the HPID The data from the HPID register and the address from the HPIA register is transferred to the internal CPU memory space through the DMA auxiliary channel Both the data and address registers can only be accessed through the HPI interface The HPIC controller register can be accessed through either the HPI or the DSP s CPU Two pins HCNTL 1 0 determines which HPI register is accessed according to Table 1below Table 1 Access to HPI Registers HCNTL 1 0 Description 00 Access to HPIG 01 Access to HPIA 10 Access to HPID with HPIA postincrement 11 Access to HPID without HPIA postincrement To read or write to the internal memory a typical access should start with setting the HPIC register followed by the HPIA a

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