Home

MN15G0202/0402 LSI User`s Manual

1. NSTRUCTON Mnemonic Operation Gode Cycle Machine Code L load e LSC 1 17 43 load increment Y lt lt 1 e 1 2 21 43 LDCY load decrement Y A M X Y Y Y 1 e 1 2 125 44 LD da load direct lt e 2 2 1F da 44 LX load from X AX e 1 1 44 45 LY load from Y Ac Y e 1 1 45 45 LI load immediate Acn to pile up instructions 1 1 Fn 46 LYI load Y immediate Yen 1 1 10 46 LEAI mn load EA immediate lt lt 2 2 76 mn 47 LXYI mn load XY immediate 2 2 77 mn 47 LBD da load byte direct E M da 1 A lt M da 2 2 48 da 48 ST store lt 157 49 STICY store increment Y M X Y A Y Y 1 1 2 122 49 STDCY store decrement Y M X Y A Y Y 1 1 2 126 50 STD da store direct M da lt A 2 2 53 da 50 STE store to E EcA 1 1 56 51 STX store to X 1 1 54 51 STY store to Y 1 1 55 52 STBD da store byte direct M da 1 lt E M da lt A 2 2 49 da 52 exchange lt gt M X Y 1 1 47 53 S EXD da exchange direct A lt gt M da 2 2 43 da 53 8 exchange E 1 1 46 54 5 exchange SE E o 0 2 1 1 42 54 2 EXSX exchange SX X o SX E gt M 0 0 sul sce peri 55 S EXSY exchange SY Y lt gt SY E gt M 0 1
2. ROM read out Instruction decode JMP CALL RET RETI interrupt 1 PC load Ed RAM address RAM Sis out RAM write 1 SP 1 Figure 2 1 2 Machine Cycle and CPU Basic Timing Clock Generator 3 Chapter 2 Basic CPU 2 2 Register Set This LSI has register for operation for pointer and for store for operation 3 0 accumulator A register 3 0 accumulator expansion register E register for pointer T 4 3 0 IRU IRL IR instruction register IRU IR upper 3 0 IRL IR lower X register 3 0 Y register 13 12 11 8 7 4 3 0 PCu PCh PCI PC program counter PCu PC upper PCh PC high PCm PC middle PCI PC low 3 0 SX stack register for X register 3 0 SY stack register for Y register 3 0 SE stack register for E register 114 0 SP stack pointer for store SB special buffer TB temporaly buffer Figure 2 2 1 CPU Control Registers 4 Register Set Chapter 2 Basic CPU A register This register can be used generally for all operations Accumulator expansion register E register This register can be used generally for operation At transfer instruction of 8 bit data this register can be used for upper 4 bits or RAM odd address ex STBD stor
3. Figure 6 2 2 Conversion Data Storage Buffer 0 ADBUFO 070 A D Conversion Data Storage Buffer 1 ADBUF1 The upper 8 bits from the result of A D conversion are stored to this register 7 6 5 4 3 2 1 0 ADBUF1 ADBUF9 ADBUF8 ADBUF7 ADBUF6 ADBUF5 ADBUF4 ADBUF3 ADBUF2 at reset XXXXXXXX Figure 6 2 3 Conversion Data Buffer 1 ADBUF1 x 072 VI 6 Control Registers 6 3 Chapter 6 A D Converter Operation Here is a description of A D converter circuit setup procedure 1 Set the analog pins Set the analog input pin to input mode by the port 2 port 3 direction control register P23DIR and set the port 2 port 3 output structure register P23PLU to 0 to select pull up resistor OFF Setup for the port 2 port 3 direction control register P23DIR should be done before analog voltage is put to pins Set the A D conversion input pin Select the analog input pin from AD3 to ADO by the ADCHS1 to ADCHSO flag of the A D converter control register ADCTRO Select the A D converter clock Select the A D converter clock by the ADCK flag of the A D converter control register ADCTRO Depending on the resonator the converter clock TAD should not be under 800 ns Set the sample hold time Set the sample hold time by the ADSH1 ADSHO flag of the A D converter control register ADCTRO The sample hold time sho
4. A interrupt request acceptance service routine starts O When the interrupt factor is generated in execution of 3 cycles instruction the interrupt acceptance is started after 3 cycles instruction is completed 1 cycle 5 3 cycles instruction 52 instruction etc A interrupt request acceptance service routine starts O When the interrupt factor is generated in execution of EDI instruction and the next instruction 1 2 or 3 cycles instruction the interrupt acceptance is started after the instruction max 5 cycles is completed 1 cycle H H EDI instruction 2 cycles instruction i 2 1 JMP instruction etc interrupt request acceptance service routine starts 2 1 The contents of PC and FS in main program are pushed to the stack area 2 The starting address of the interrupt service routine is set to PC 3 IF and IE of the accepted interrupt are reset Overview 9 Chapter 4 Interrupts Binterrupt Acceptance Start and Finish at multiple interrupts Here is the example of acceptance at multiple interrupts OWhen the interrupt factor is generated in execution of instruction at the beginning of the interrupt service routine the interrupt acceptance is started after the instruction is completed except when the next instruction to JMP instruction is EDI instruction
5. 32 929 nr EE 34 5 9 1 Operation EE V 34 5 9 2 Setup Example aea toe om a idet eege 35 Chapter 6 A D Converter E e EE VI 2 6 1 1 Lee EE VI 2 6 1 2 cos op tee rro emen i eene VI 3 6 2 Control Registers ei Ed Nee ipte VI 4 6 2 1 Registers PM VI 4 6 2 2 Control Registers s c te PERDU RE e etre dei VI 5 6 2 3 IRC RE 6 6 3 Operatiom EE VI 7 6 3 1 pte be pte recepte it ERR VI 9 6 3 2 Setup Example neat nU enteren eite wes VI 11 6 3 3 t Ure aeui VI 12 iv contents 7 Zero Cross Detection 7 1 7 2 2 7 1 1 ieee ee Nie AR VII 2 7 1 2 Block Di gram VII 3 7 1 3 EE tp e reet 4 Control Registers ce e e e tr rn ee Eed 5 Chapter 8 Watchdog Timer 8 1 8 2 Uiverview eddi dE EEN ee kd VIII 2 8 1 1 QOVERVICW geesde EE VIII 2 8 1 2 Block Dia gram 22 42 ane tr ie eeh Eeer es VIII 3 Control RePistets t i iios eee estne tete e ledere eredi eroe 4 Chapter 9 Automatic Reset 9 1 CVV ELVIS Wisin avait novit de RU US IX 2 9 1 1 2 9 1 2 Electrical Characteristics esee IX 3 Chapter 10 Appendices 10 1 10 2 10 3 10 4 10 5 10 6 EPROM ee Veet oats caste bee ies Locus UR SE Eus S
6. P1DATA Port 1 output data 0 Low Vss level is output 1 High Von level is output At reading pin s status is read Port 0 Port 1 Data Register PORTO1 x 000 R W 7 6 5 4 3 2 1 0 PO1DIR P1DIR3 P1DIR2 P1DIR1 P1DIRO PODIR3 PODIR2 PODIR1 PODIRO at reset 00000000 PODIR Port 0 direction control 0 Input mode output Hiz 1 Output mode 1 P1DIR Port 1 direction control 0 Input mode output Hiz 1 Output mode 1 1 It becomes special port output when the pin function is switched Port 0 Port 1 Direction Control Register PO1DIR x 010 R W 7 6 5 4 3 2 1 0 015 1503 P1SC2 P1SC1 P1SCO at reset 0000XXXX P1SC Port 1 output structure control 0 CMOS output 1 N ch open drain Figure 3 2 1 Port 0 Port 1 Registers Port 0 1 9 Chapter3 Ports 3 2 3 Block Diagram Port output data PODIRO x 000 gt Port input data lt Input i DHE E 777 nstruction gt Figure 3 2 2 Block Diagram P00 A m P01 P03 Port output data PODIR1 3 zm x 000 E Port input data Input instruction PWMEn J PWM output gt Figure 3 2 3 Block Diagram P01 P02 P03 Port output data Output structure control
7. TM3CK2 TM3CK1 TM3CKO at reset XXX00000 BEEF TM3CK TM3CK1 TM3CKO timer 3 count clock 0 0 X fsys 2 0 1 0 fosc 1 X 1 fosc 26 0 1 1 fosc 214 timer 3 count enable 0 disable timer 1 enable timer TM3CAS timer 2 timer 3 cascade connection 0 OFF 1 ON Figure 5 2 4 Timer 3 Mode Register TM3MD 04 R W Timer Mode Control Register MODCNT 7 6 5 4 3 2 1 0 MODCNT N 2 2 PWMOSO 5 at reset PWMOSO timer output 0 timer 2 output 1 timer 3 output Figure 5 2 5 Timer Mode Control Register MODCNT 05 R W V 12 8 Bit Timer Control Registers Output Control Register TCOCNT TCOCNT 7 6 5 4 3 2 1 TCOE RMOEN RMDTY RMOS TCOS 2305 Chapter 5 Timers at reset 000X000X 2305 timer 2 timer 3 output 0 timer 2 1 timer 3 TCOS timer output buzzer output 0 buzzer output 1 timer 2 timer 3 output RMOS TCO output 0 timer output 1 remote control output RMDTY remote control output duty 0 1 2 duty 1 1 3 duty RMOEN remote control output enable 0 output low level 1 output carrier TCOE timer output enable 0 port output data 1 TCO TCOE RMOS TCOS
8. Figure 2 4 2 CPU Mode Register CPUM x 030 R W Table 2 4 1 Status of Operation Mode Operation clock System clock 200 OSCH OSC2 fosc NORMAL Oscillation fosc 8 or fosc 4 Operate HALT Oscillation fosc 8 or fosc 4 Stop STOP Stop Stop Stop Clock Switching II 15 Chapter 2 Basic CPU 2 5 Back Up Mode There are two back up mode to save electric consumption They can be controlled by program HALT mode The system clock is supplied It is recovered by a reset or by an interrupt STOP mode The division circuit for the system clock is stopped so that the electric consumption is more saved It is recovered by a reset or by an interrupt Table 2 5 1 Description STOP HALT Functions STOP HALT Operation status 1 System clock System clock oscillation circuit stop oscillation circuit operates dividing circuit for system clock operates Timer count operates Mode setup WI instruction is executed WI instruction is executed soon after EDI instruction soon after instruction is done refer to ex except EDI is done refer to ex Recover ex STOP mode usage example interrupt reset same as a normal interrupt same as a normal reset When IRQ1 interrupt 1 is generated it is recovered from STOP mode To stable the operation more than 1 NOP should be inserted after EDI WI instructions EDI 0 4 WI NOP I
9. Set the analog input pin P23DIR x 012 P2DIRO 0 Select the analog input pin ADCTRO 074 bp1 0 ADCHS1 0 00 Select the A D conversion clock ADCTRO 074 bp4 ADCK 1 Set the sample and hold time ADCTRO x 074 bp6 5 ADSH1 0 01 Set the A D ladder resistance ADCTRO 074 bp3 ADLADE 1 Start the A D conversion ADCTRO x 074 bp7 ADST 1 Complete the A D conversion ADBUFO x 070 ADBUF1 x 072 Set P20 ADO pin to the input mode by the port 2 port 3 direction control register P23DIR Select ADO to the analog input pin by the ADCHS1 0 flag of the A D converter control register ADCTRO Select fsys 2 to the A D conversion clock by the ADCK flag of the A D converter control register ADCTRO Set TAD x 6 to the sample and hold time by the ADSH1 ADSHO flag of the A D converter control register ADCTRO Set the ADLADE flag of the A D converter control register ADCTRO to 1 to send a current to the ladder resistance for the A D conversion Set the ADST flag of the A D converter control register ADCTRO to 1 to start the A D conversion The ADST flag of the A D control register ADCTRO is cleared to 0 as the A D conversion is completed The result is stored to the A D buffer ADBUFO 1 VI 11 Operation Chapter 6 A D Converter 6 3 3 Cautions A D conversion can be damaged by noise easily hence antinoise t
10. an input or output P10 PWMOO Output structure can Each bit can be set 11 PWMO be selected CMOS ron P12 2 ao individually on each output P13 PWMOS pub bit E SCH Each bit can be set Pull up resistor can be 2 CMOS Port 2 P22 AD2 VO lindividually as either Input set individually on No resistor individually on each output P23 AD3 an input or output each bit bit P30 NSYNC 0 2 Each bit can be set Pull up resistor can be 2 SCH CMOS Port 3 kevi VO lindividually as either Input set individually on No resistor individually each an input or output each bit y P 2 bit BZ key2 Overview 3 Chapter 3 Ports 3 1 3 Port Status at Reset Table 3 1 2 Port Status at Reset Port VO mode Pull up resistor Port 0 Input mode Port 1 Input mode Port 2 Input mode No pull up resistor Port 3 Input mode No pull up resistor Y P30 NSYNC key0 outputs the system clock 50 at internal reset m 4 Overview Chapter 3 Ports 3 1 4 Port Disposal at Unused Disposal of unused pins should be considered the status at reset Table 3 1 3 shows the disposal Table 3 1 3 Disposal of Unused Pins Pin s type Port Unused pin Port 0 OPEN Port 1 OPEN VO pin Port 2 OPEN Port 3 Pull up or pull down should be added 1 1 When the internal resistor is used the thr
11. interrupt control register 1 17 R W Readable Writable W Writable only Control Registers IV 15 Chapter 4 Interrupts 4 2 2 Interrupt Control Registers 7 6 5 4 3 2 1 0 IRQM IFIRQ3E IFIRQ2E IFIRQ1E z z 2 at reset 000XXXXX IFIRQ1E IRQ1 IF flag clear operation 0 continue 1 clear IFIRQ2E 2 IF flag clear operation 0 continue 1 clear IFIRQ3E IRQ3 IF flag clear operation 0 continue 1 clear Note Register is cleared to 0 after flag is cleared IRQ Mode Register IRQM x 032 W 7 6 5 4 3 2 1 0 IRQCO MASKIR1 IRQ1SEO reserved reserved at reset 0000 21 reserved set always 0 IRQ1SEO IRQ1 interrupt edge switch 0 falling 1 rising MASKIR1 IRQ1 interrupt edge mask 0 mask 1 enable Interrupt Control Register 0 IRQCO x 034 R W Figure 4 2 1 Interrupt Control Register 1 2 IV 16 Control Registers Chapter 4 Interrupts 7 6 5 4 3 2 1 0 IRQC1 MASKIR3 IRQ3SE IRQ3S1 IRQ3S0 at reset XXXX0000 IRQ3S1 IRQ3S0 IRQ3 interrupt source 0 0 key interrupt 0 1 ACZ interrupt 1 0 timer 3 interrupt 1 1 No use IRQ3SE IRQ3 interrupt edge switch 0 falling 1 rising MASKIR3 IRQ3 interrupt mask 0 mask 1 en
12. x eoo Output structure control register P3SCO Direction control register 3 E P3DIRO E 1 J gt 5 RESET L S 777 7 7 Port input data lt ga keyO input 11 RESET At internal reset L After reset release H Figure 3 3 4 Block Diagram P30 Port2 3 M 15 Chapter3 Ports Pull up control P3PLU1 GH SS A AN A x P31 Output structure control register P3SC1 Direction control register e gt P3DIR1 Port output data ACZ interrupt 777 zero cross detection circuit Port input data 4 e RESET Te At internal reset L After reset release r input 4 9 211 key1 input 4 Figure 3 3 5 Block Diagram P31 Pull up control P3PLU2 p 1 Port output see TCO BZ output 5 gt Ee gt x CO Output structure control register P3SC2 5 Direction control register gt e a P3DIR2 21 i 777 777 Port input data tee A eys input RESET 2 5 At internal reset L After reset release H F
13. I 12 Special Function Registers R W Readable Writable Readable only W Writable only Chapter 1 Overview 1 6 Electrical Characteristics 1 This LSI user s manual describes the standard specification Please ask our sales offices for its own product specifications MN15G0202 MN15G0402 Contents Structure CMOS integrated circuit Application General purpose Function CMOS 4 bit single chip microcontroller 1 6 1 Absolute Maximum Ratings 2 3 Vss 0V Parameter Symbol Rating Unit 1 Power supply voltage Von 0 3 to 7 0 V 2 Input clamp current ACZ lc 0 5 to 40 5 mA 0 3 to 0 3 3 VO pin voltage Vio except ACZ V 4 PO loL peak 40 5 Peak output Other than PO loL peak 20 current 6 all loH peak 10 7 PO loL avg 15 8 Average output other ten PO lorew 10 current 1 mA 9 all loH avg 2 10 trout 60 2 11 Total output Other than PO oz 20 60 1 13 Other than PO 20 14 Power dissipation 180 85 C mW 15 Ambient operating temperature Topr 40 to 85 16 Storage temperature Tstg 55 to 125 1 Applied to any 100 ms period 2 Connect at least one bypass capacitor of 0 1uF or larger between the power supply pin and the ground near the LSI for latch up prevention 8 The absolute maximum ratings are the limit values beyond whic
14. Version Chapter 10 Appendices 10 1 2 Cautions on Use EPROM Version differs from the MN15G0202 MN15G0402 in some of its electrical characteristics The user should be aware of the following cautions 1 Due to device characteristics of the MN15GP0402SJ a writing test cannot be performed on all bits Therefore the reliability of data writing may not be 10096 ensured 2 When a program is written verify that Von power supply 6 V is connected before applying the Ver power supply 12 5 V Disconnect the Ver supply before disconnecting the supply 3 Ver should never exceed 13 5 V including overshoot 4 a device is removed while a Ver of 412 5 V is applied device reliability may be damaged 5 At do not change Vpp from Vi to 12 5 V or from 12 5 V to 6 After a program is written screening at a high temperature storage is recommended before mounting Program Read 2 High temperature storage 125 C 48H Mounting D i EPROM Version X 3 Chapter 10 Appendices 10 1 3 Differences between Mask ROM version and version The differences between the 4 bit microcontroller MN15G0202 MN15G0402 Mask ROM vers and the microcontroller with internal EPROM are as follows MN15G0202 MN15G0402 ROM version MN15GP0402 EPROM version Operating ambient temperature 40 C to 85 C 20 C to 70 C Operating voltage 3 0 V to 5 5 V 0 50 us at 8 MH
15. eg 8 55 5 LBXY 2 load byte pointed by XY register 2 1 1 1 4 2 56 LBDC z da load byte direct control register EA lt CR z da 2 2 12 8 2 4 56 STBXY 2 store byte pointed by XY register CR z X Y EA 1 1 5 2 57 STBDC z da store byte direct control register CR z da EA 2 2 12 2 9 57 PSHEA push E A SP SP 2 M SP EA I 11 1 68 58 PSHXY push X Y SP lt SP 2 M SP lt XY 1 1 69 59 POPEA pop E A 8 8 5 2 1111 ec 60 POPXY pop X Y XY lt M SP SP SP 2 61 m n load and modify E Ec E amp m n 2 2 33mn 62 mn load and modify X Xc X amp m n 191212 32 62 RMD da reset memory direct 0 2 2 37 da 63 WTSB write SB SB EA 1 1 80 RDSB read SB 58 1 11 1 84 WTTB write TB 1 1 82 RDBC read BC EA TB 1 1 85 WTSP write SP SPEA 1 1 05 66 RDSP read SP EASP 1 1 104 66 RDTBL read table lt 1 2 0 67 add lt e o 1 1 10 68 AD da add direct 2 2 18da 68 add with carry e o 111 69 ACD da add direct with carry AcA M da CF e j 2 2 19 0 69 Al n add immediate AcA n e jo 1 Dn 70 S subtract lt e jo 1 12 71 gt 50 da subtract direct e e 2 2 1 7 5 SB subtract with bor
16. tor and output structure control register PnSC that controls output structure Table 3 1 4 Port Control Registers List Register Address R W Function Page PORTO 000 R W 0 port 1 data register Ill 9 1 PO DI 010 R W Port 0 port 1 direction control register IIl 9 P01SC 028 R W 1 output structure control register IIl 9 PORT23 x 002 R W Port 2 port 3 data register 13 Port 2 P23DIR 012 R W Port 2 port 3 direction control register ll 13 Pot3 P23PLU 022 R W Port 2 3 pull up resistor control register Il 13 P23SC X02A R W Port 2 port 3 output structure control register Ill 14 R W Readable Writable Y Access to x 010 to x 02A can be available only by 8 bit m Overview III 7 Chapter3 Ports 3 2 Port 0 1 3 2 1 Description Port Setup Each bit can be set individually as either an input or output by the port 0 port 1 direction control register PO1DIR The control flag of the port 0 port 1 direction control register PO1DIR is set to 1 for output mode and 0 for input mode To read input data of pin set the control flag of the direction control register PO1DIR to or set the output configuration to N ch open drain by the output structure control register PO1SC and set the port 0 port 1 data register PORTO1 to 1 to select Hi z output then read the value of the por
17. 12 lt 06 4 7 lt 05 DO P12 port output data Em 1 13 lt 06 4 P13 port output data Figure 5 1 3 Timer Output Block Diagram mhRemote Control Circuit Block Diagram 1 2 timer 2 output or timer 3 output duty gt 1 3 duty RMDTY x 06A synchronous circuit gt remote control output T RMOEN 08 Figure 5 1 4 Remote Control Output Block Diagram 6 Overview Chapter5 Timers Buzzer Output Block Diagram BZCK1 BZCKO 06 TCOS 4 06 RMOS M Y 06 Uu iM 1 06 fosc 1024 1 2 1 2 X 5 i 32 2 t control gt X U timer output A P32 port output data Figure 5 1 5 Buzzer Output Block Diagram Overview V 7 Chapter 5 Timers 5 2 8 Bit Timer Control Registers Each of timer 2 and timer 3 consists of the binary counter TMnBC and the compare register TMnOC And they are controlled by the mode register TMnMD 5 2 1 Registers Table 5 2 1 8 bit Timer Control Registers register address R W function page TM2BC 044 timer 2 binary counter V 10 2 054 R W timer 2 compare register V 9 TM2MD 04 R W timer 2 mode register V 11 MODCNT X 05E R W timer mode control r
18. HALT mode 20 5 0 V oe 08 mA Vpp 5 V 4 504 2 1 2 3 0 10 0 25 C 5 V STOP mode 40 to 85 6 Voo 5 V i 25 C Vpp 5 V d pee Ta 40 C to 85 Automatic reset current 8 consumption 2 Vpp 5 V 4 0 8 0 2 Measured under conditions of no load Ta 25 The automatic reset current consumption 10010 indicates the consumption normally spent in automatic reset circuit when automatic reset is used in mask option So if automatic reset circuit is selected each rating is added The supply current during operation 1001 is measured under the following conditions After reset is released and the oscillation is set to NORMAL mode the I O pin is fixed at and a 8 MHz square wave of amplitude Von Vss is input to the OSC1 pin The supply current during operation is measured under the following conditions After reset is released and the oscillation is set to NORMAL mode the UO pin is fixed at and a 4 2 square wave of amplitude Von Vss is input to the OSC1 pin The supply current during HALT mode 1053 is measured under the following conditions After reset is released and the oscillation is set to HALT mode the pin is fixed at and a 4 MHz square wave of amplitude Vss is input to the OSC1 pin During STOP mode The supply current 004 1005 and Ippe are app
19. 2305 2 2 output 1 0 0 buzzer output 1 0 1 0 timer 2 output 1 0 1 1 timer 3 output X 1 0 X unused remote control output base cycle is timer 2 1 1 1 0 output 1 1 1 1 remote control output base cycle is timer 3 output 0 X X X P32 port data output Figure 5 2 6 Timer Output Control Register TCOCNT x 06A R W 8 Bit Timer Control Registers 13 Chapter 5 Timers Buzzer Output Control Register BZCTR 7 6 5 4 3 2 1 0 BZCTR BZCK1 BZCKO PWME13 PWME12 PWME11 PWME10 at reset XX000000 PWME10 PWM output enable to port 10 0 port output data 1 enable PWME11 PWM output enable to port 11 0 port output data 1 enable PWME12 PWM output enable to port 12 0 port output data 1 enable PWME12 PWM output enable to port 13 0 port output data 1 enable 2 2 BZCK1 buzzer output frequency 0 X fosc 1024 4 kHz fosc 4 MHz 1 0 fosc 2048 2 kHz fosc 4 MHz 1 1 fosc 4096 1 kHz fosc 4 MHz Figure 5 2 7 Buzzer Output Control Register BZCTR x 06C R W 14 8 Timer Control Registers Chapter5 Timers 5 3 8 Bit Timer Operation 5 3 1 Operation The timer operation can constantly generate interrupts 8 Bit Timer Operation Timer 2 Timer 3 The generation cycle of timer interrupts is set by the clock source selection and the setting value of the compare r
20. 50 01 1 19 Output high voltage Vous loH 0 5 mA Vpp 5 0 V 4 5 4 9 Von 20 Output low voltage 01 15 5 0 V Vss 0 4 1 0 VO pin P20 ADO P21 AD1 P22 AD2 P23 AD3 as port 21 Input high voltage 0 8 5 22 Input low voltage ViL4 Vss 0 2 23 Input current l4 1 2 50 140 200 24 leakage current 1 5 ie ag OFF 0 01 1 25 Output high voltage loH 0 5 5 0 V 4 5 4 9 26 Output low voltage lo 23 5 5 0 V Vss 0 1 0 5 Electrical Characteristics Chapter 1 Overview 40 to 85 2 0 V to 5 5 2 to 5 5 V Vss 0 V Rating Parameter Symbol Condition Unit MIN TYP MAX VO P30 NSYNC keyO P31 NIRQ ACZ key1 P32 TCO BZ key2 as PS0 NSYNC keyO P31 NIRQ key1 P32 TCO BZ key2 schmitt input 27 Input high voltage Vus 0 8 V 28 low voltage 5 Vss 0 1Vpp Pull up resistor ON 29 current l5 Vi 1 5 V 5 0 V 50 140 200 u Pull up resistor OFF 30 leakage current 15 Veo V to Vou 0 01 1 31 Output high voltage Vous 0 5 mA Vpp 5 0 V 4 5 4 9 V 32 Output low voltage Vos 3 5 5 0 V Vss 0 1 0 5 Note When P30 NSYNC keyO pins are used output voltage should be over 0 8 VDD at timing signal NSYNC out
21. 6 16 00 us 32 00 0 TAD 18 28 00 us 56 00 1 Reserved s lBuilt in Ladder Resistance Control The ADLADE flag of the ADCTRO register is set to 1 to send a current to the ladder resistance for A D conversion As A D converter is stopped the ADLADE flag of the ADCTRO register is set to 0 to save the power consumption Table 6 3 4 A D Ladder Resistance Control ADLADE A D ladder resistance control 0 A D ladder resistance OFF A D conversion stop A D ladder resistance ON A D converison stand by RAD Conversion Starting Setup A D conversion starting is set by the ADST flag of the ADCTRO register The ADST flag of the ADCTRO register is set to 1 to start A D conversion The ADST flag of the ADCTRO register is set to 1 during A D conversion then cleared to 0 as the A D conversion is completed VI 10 Operation Table 6 3 5 A D Conversion Starting ADST A D conversion activation factor 0 A D conversion completed or stopped 1 A D conversion started or in progress Chapter 6 A D Converter 6 3 2 Setup Example A D Converter Setup Example by Registers A D conversion is started by setting registers The analog input pins are set to ADO the conversion clock is set to fsys 2 and the sample and hold time is set to TAD x 6 An example setup procedure with a description of each step is shown below Setup Procedure Description
22. PanaNSeries TheOnetoWatch for Constant Innovation Making the Future ComeAlive MICROCOMPUTER MN15G MN15G0202 0402 L SI User s Manual Pub No 20302 020E Panasonic PanaXSeries is a trademark of Matsushita Electric Industrial Co Ltd The other corporation names logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations Request for your special attention and precautions in using the technical information 1 2 3 4 5 and semiconductors described in this book An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this book and controlled under the Foreign Exchange and Foreign Trade Law is to be exported or taken out of Japan The contents of this book are subject to change without notice in matters of improved function When finalizing your design therefore ask for the most up to date version in advance in order to check for any changes We are not liable for any damage arising out of the use of the contents of this book or for any infringement of patents or any other rights owned by a third party No part of this book may be reprinted or reproduced by any means without written permission from our company This book deals with standard specification Ask for the latest individual Product Standard or Specifications in advance for more detailed inf
23. X 04E dEr V 12 eg Timer 3 count clock connection Special Function Registers List X 11 Chapter 10 Appendices MN15G0202 Special Function Registers List 2 2 Bit Symbol Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TM20C7 TM20C6 TM20C5 20 4 TM20C3 TM20C2 2 1 20 0 054 2 V 9 Timer 2 Compare Register 7 6 5 4 2 1 TM3OCO x056 V 9 Timer 3 Compare Register PWMOSO 05 MODCNT Timer V 12 Output Selection TCOE RMOEN RMDTY RMOS TCOS TC230S Remote Remote Timer 2 X06A TCOCNT ae Control Control TCO output yea Timer 3 V 13 Output Output Duty Selection Output Enable Enable Selection Selection Selection BZCK1 BZCKO PWME13 PWME12 PWME11 PWME10 x06C BZCTR Port 13 Port 12 Port 11 Port 10 V 14 Buzzer Output Frequency Output PWM Output PWM Output PWM Output Selection Enable Enable Enable Enable WDTCLR XOGE WDCTR Clear VIII 4 Watchdog Timer ADBUF1 ADBUFO X070 ADBUFO A D Conversion Data VI 6 Storage Buffer 1 0 ADBUF9 ADBUF8 ADBUF7 ADBUF6 ADBUF5 ADBUF4 ADBUF3 ADBUF2 072 ADBUF1 VI 6 A D Conversion Data Storage Buffer 9 2 ADST ADSH1 ADSHO ADCK ADLADE ADCHS1 ADCHSO A D E x074 ADCTRO C Sample
24. and interrupt 1 IRQ1 is generated at the falling edge An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Set the pin P23DIR x 012 bp5 PSDIR1 0 Select the interrupt source IRQCO x 034 bp4 150 0 Select the interrupt edge IRQCO x 034 bp6 JRQ1SEO 20 Enable the interrupt edge IRQCO x 034 bp7 MASKIR1 1 Clear the interrupt request flag 032 bp5 IFIRQIE 1 Enable the interrupt 1 1 Set the P3DIR1 flag of the port 2 port 3 direction control register P23DIR to for P31 NIRQ to set to input mode If necessary add pull up resistor t Chapter 3 Ports Select interrupt 1 as the interrupt source by the IRQ1SO flag of the interrupt control register 0 IRQCO Set the IRQ1SEO flag of the interrupt control register 0 IRQCO to 0 to select the interrupt edge to the falling edge Enable the interrupt edge by the 1 flag of the interrupt control register 0 IRQCO Set the IFIRQ1E flag of the IRQ mode register IRQM to 1 to clear the interrupt 1 request flag Execute EDI instruction to enable interrupt 1 IV 13 Overview Chapter 4 Interrupts Key Interrupt setup procedure P30 P31 P32 P30 key 0 is input pulse to generate at the falling edge An example setup procedure with a description of each step is shown below Setup Procedure Descriptio
25. 1 cycle no acceptance no acceptance gt gt gt lt gt nterrupt 2 cycles instruction request 2 1 JMP instruction A 2 1 interrupt JMP instruction request acceptance service routine starts acceptance service routine starts OWhen the interrupt factor is generated in execution of instruction at the beginning of the interrupt service routine Instructions is EDI the interrupt acceptance is started after the next instruction to EDI is completed 1 cycle no acceptance no acceptance d lt gt 1 4 2 cycles instruction interrupt request 2 instruction EDI instruction 3 2 cycles instruction 2 D A interrupt JMP instruction request acceptance service routine starts service routine starts 2 1 The contents of PC and FS in main program are pushed to the stack area 2 The starting address of the interrupt service routine is set to PC 3 IF and IE of the accepted interrupt are reset 8 EDI instruction that does not disable an interrupt IV 10 Overview Chapter4 Interrupts OWhen two interrupt factors are generated at the same time the interrupt with higher priority is accepted 1 cycle no acceptance no acceptance 2 cycles instruction JMP instruction disable ED interrupt 2 enable EDI interrupt 2 2
26. 17 Chapter 5 Timers 5 4 8 Bit Timer Pulse Output 5 4 1 Operation TCO or port 1 can output pulse signal with arbitrary frequency WTimer Pulse Output Operation timer 2 timer 3 The output signal has the twice cycle to the set value in the compare register TMnOC Table 5 4 1 shows output pins Table 5 4 1 Event Count Input Clock timer 2 timer 3 TCO output P32 TCO output P32 P10 P13 pins P10 P13 pins pulse output pin iCount Timing of Timer Pulse Output Timer 2 Timer 3 FSH UH I TMnEN flag compare register interrupt request flag TCO output Figure 5 4 1 Count Timing of Timer Pulse Output Timer 2 Timer 3 TCO outputs the signal with twice cycles to the set value in the compare register When the binary counter reaches the value of the compare register the binary counter is cleared to x 00 then TCO output timer output is reversed Inversion of timer output is changed at the rising edge of the count clock This is happened to form the waveform inside of the micro controller for precise output cycle V 18 8 Bit Timer Pulse Output Chapter5 Timers 5 4 2 Setup Example Eimer Pulse Output Setup Example Timer 2 Timer 3 TCO outputs a 50 kHz pulse by timer 2 To output a 50 kHz select fosc as a clock source and set the 1 2 cycle 100 kHz to the timer 2 compare register Operation is at fosc 4 MHz An exam
27. 2 Automatic reset circuit When it is used Used check the applicable item 3 2 V to 4 4 V Reset voltage Unused VRSTL2 1 6V to 2 5 V Vnsn2 cannot be selected at tc the instruction execution time 2 ps Option I 25 Chapter 2 Basic CPU 2 Basic CPU 2 1 Clock Generator 2 1 1 Clock Generator This LSI has internal oscillator circuit for generating system clock OSC1 OSC2 This circuit requires external oscillators and capacitors Connect a crystal or ceramic oscillator Figure 2 1 1 to it Also connect the Vss pin to a thick ground line with shortest possible distance to prevent noise and to stable oscillation The best value of capacitor depends on oscillator refer to the value specified by each manufacturer a To minimize distortion mount the oscillator and capacitor as close as possible to the pins Oscillator circuit connection Figure 2 1 1 provides oscillator circuit connections Figure 2 1 1 Oscillator circuit connection 2 Clock Generator 2 Basic CPU 2 1 2 CPU Basic Timing Source oscillation generates 4 clocks S0 S1 S2 S3 to form machine cycle state At 4 0 MHz 1 machine cycle is 1 0 us at divided by 4 and 2 0 us at divided by 8 Machine cycle S3 50 51 52 53 50 51 Fetch cycle n Fetch cycle 1 Execution cycle n 1 Execution cycle n Execution cycle 1
28. 39 01 Jaran Sri Perkasa 2 1 Taman Tampoi Utama Tampoi 81200 Johor Bahru Johor Malaysia Tel 07 241 3822 Fax 07 241 3996 CHINA SALES OFFICE Panasonic SH Industrial Sales Shenzhen Co Ltd PSI SZ 74 107 International Business amp Exhibition Centre Futian Free Trade Zone Shenzhen 518048 Tel 755 359 8500 Fax 755 359 8516 Panasonic Industrial Shanghai Co Ltd PICS 1F Block A Development Mansion 51 Ri Jing Street Wai Gao Qiao Free Trade Zone Shanghai 200137 Tel 21 5866 6114 Fax 21 5866 8000 THAILAND SALES OFFICE Panasonic Industrial Thailand Ltd PICT 252 133 Muang Thai Phatra Complex Building 31st Fl Rachadaphisek Rd Huaykwang Bangkok 10320 Tel 02 6933407 Fax 02 6933423 KOREA SALES OFFICE Panasonic Industrial Korea Co Ltd PIKL Group Bldg 11th 191 Hangangro 2ga Youngsans ku Seoul 140 702 Korea Tel 82 2 795 9600 Fax 82 2 795 1542 PHILIPPINES SALES OFFICE National Panasonic Sales Philippines NPP 102 Laguna Boulevard Laguna Technopark Sta Rosa Laguna 4026 Philippines Tel 02 520 3150 Fax 02 843 2778 230501 Printed in JAPAN
29. 4 EDI 4 0 IRQ2 EDI 0 2 EDI 2 0 IRQ3 EDI 0 1 EDI 1 0 Interrupt request flag IF is set to 1 by an interrupt request and cleared to 0 by the interrupt accep tance This flag is managed by hardware but can be reset by software IRQ mode register IRQM can reset the request flag Interrupt enable flag IE is the flag that enables interrupts in the group This flag is valid when it is 1 IV 2 Overview Chapter4 Interrupts 4 1 2 Block Diagram EDI instruction enable disable MASKIR1 IRQ1SEO Y IRQ1 mask edge Pa circuit switch input 5 c m timer 2 interrupt interrupt lt 3 9 IRQS lt timer 3 interrupt 2 24 2 i lt 5 z 4 H P31 key interrupt lt circuit x E P32 IRQ3S1 1 1 MASKIR3 20350 KEY EN IRQM register IF clear flag edge switch ACZ interrupt IRQ3SE Figure 4 1 1 Interrupt Block Diagram Overview IV 3 Chapter 4 Interrupts 4 1 3 Operation iinterrupt Processing Sequence For interrupts other than reset input the interrupt processing sequence consists of interrupt request interrupt acceptance and hardware processing After acceptance the program counter PC and the flag status FS are saved onto the stack and execution branches to the starting address specified by the corresponding
30. 5 ml jump if non carry if CF 0 PCmm PCII 2 2 6B ml 101 T if CF 1 lt 2 JBZ bp ml jump if bit zero if 0 1 2 2 7 8 bp ml 102 if A bp 1 2 JBNZ bp jump if bit nonzero if A op 1 5 2 2 7 C bp ml 102 if A bp 0 lt 2 n ml compare Y and jump if Yzn POmm PCII 2 2 Bn ml 103 if Yn lt 2 NOP no operation lt 1 3111 100 103 OLN p n input Ac PORT p amp n 2 2 73pn 104 S OUT pn output PORT p lt A amp n _ 2 2 72 pn 104 DOUT p n reset output lt amp n 1 1212 62pn 105 9 SOUT pn set output PORT p PORT p n 2 2 66 pn 105 o WI wait for interrupt SP SP 4 lt 1 1 11 1 4A 106 S RC reset carry lt 0 0 1 1 103 107 5 50 set carry lt 1 1 1 1 107 107 2 EDI m n enable disable interrupt IECIE amp m n 2 2 5B mn 108 5 up to RAM BANK 0 1 1111 111 UPXI up to X1 RAM BANK 1 1 11411 150 111 LUX load UPX BANK FF A es 112 Note Page refers to the corresponding page in the Instruction Manual X 8 Instruction Set Chapter 10 Appendices 10 3 Instruction Map MN15G SERIES INSTRUCTION MAP 0 1 2 3 4 5 6 7 8 9 B C NOP der CPL Rc RbsP WTSP MWwPLuw sc R
31. 8 as source clock An example setup procedure with a description of each step is shown below Setup Procedure Description Stop the counter TM2MD 04 bp3 TM2EN 0 TM3MD 04 bp3 TM3EN 0 Select the normal lower timer operation TM2MD 04 bp4 TM2PWM 0 Set the cascade connection 04 bp4 1 Select the count clock source TM2MD 04 bp2 0 2 2 0 001 Set the interrupt generation cycle x 056 09 20 054 x C3 Set the interrupt source IRQC1 036 bp1 0 51 0 10 Clear the interrupt request flag IRQM x 032 bp7 IFIRQ3E 21 1 Set the TM2EN flag of the timer 2 mode register TM2MD to 0 the TM3EN flag of the timer 3 mode register to 0 to stop timer 2 and timer 3 counting Set the TM2PWM flag of the TM2MD register to 0 to select the normal timer 2 operation Set the TM3CAS flag of the TM3MD register to 1 to connect timer 2 and timer 3 in cascade connection Set fsys 8 as clock source by the TM2CK2 0 flag of the TM2MD register Set the interrupt generation cycle x 09C3 2500 cycles 1 to the timer 3 compare register timer 2 compare register TM3OC 2 At that time timer 3 binary counter timer 2 binary counter TM2BO are initialized to x 0000 Set the IRQ3S1 0 flag of the interrupt control register 1 IRQC1 to 10 to set timer
32. Block Diagram Chapter 1 1 3 1 Overview Table 1 3 1 Functions on Blocks Name Block Description EE Controls CPU block operations in response to the result CPU MN150G decoded by the instruction decoder and interrupt controller requests Read Only Memory can be used as an area where Buzzer output Timer controller HOM instructions that CPU executes are stored Memory data Random Access Memory can be used as an data area RAM where data that are needed on program execution are stored and as the stack area Timer 2 3 Used as timer operation timer pulse output PWM output cascade connection remote control carrier output buzzer output A D converter A D controller Includes a set of A D converter with 10 bits resolution Analog input is switched channel 0 to 3 ADO to AD3 by software External interrupt Interrupt controller Controls interrupt by interrupt request flag IF and interrupt enable flag IE Port 0 Port 1 Port 2 Port 3 VO controller Port 0 port 1 port 2 port 3 are VO port Clock generator Clock generator Connect resonator to OSC1 OSC2 to generate systemclock Watchdog timer Error detector Counts watchdog timer When counter is overflow output L from NRST pin and reset Automatic reset Low voltage detector When low voltage is detected output L from NRST pin and reset Block Diagram Overview 1 5 Cha
33. Change the 1 4 duty cycle PWM output waveform The 1 4 duty cycle PWM output waveform is output from the TCO output pin at 128 Hz output from the TCO output pin at 244 Hz by using timer 2 by using timer 2 Change The oscillation is at low frequency oscillation The oscillation is fosc 4 MHZ fx at fosc 32 768 kHz Setup procedure Setup procedure Change 4 Select the count clock source 4 Select the count clock source TM2MD x 04C TM2MD 04 bp2 0 TM2CK2 0 100 bp2 0 TM2CK2 0 111 Discription Discription 4 Select fosc as clock source by the 4 Select fosc 64 as clock source by the TM2CK2 0 flag of the TM2MD register TM2CK2 0 flag of the TM2MD register IX 3 Change Table 9 1 2 Electrical Characteristics _2 Delete These include the MN15G0202 MN15G0402 variants MN15GP0402SJ and PX AP15G0402 SY The PX AP15G0402 is sealed in a ceramic package with a window Written data can be Underlined parts are deleted erased by exposing the physical chip to intense ultraviolet radiation Erasing Data in Windowed Package PX AP15G0402 SY Warning Warning Change Ga 15G0402 SY is not available for engi The PX AP15G0402 SY with windowed neering sample now ceramic package is not supplied X 3 Delete Chapter 10 1 2 Cautions on Use Discription 1 is deleted 4 Delete Chapter 10 1 3 Erasing Data in Win dowed Package PX AP15G0402 SY x 5 Delete Chapter 10 1 4 Differences between Ma
34. IV 15 4 2 2 Interrupt Control Registers essere IV 16 Chapter5 Timers 5 1 oibus MP dee See De d e die ege ege 2 5 1 1 Functions nor oec ep ep V 3 5 1 2 Block hee ettet 4 8 bit Timer Control Registers A V 8 contents 5 2 1 8 5 2 2 Compare Registers EES V 9 5 2 3 Binary Counters eed mei 10 5 2 4 Timer Control Re sisters oie t teen pep ents peer dl V 11 5 3 8 Bit Timer Operation ret eerie aE EEEE 15 5 3 1 Opera ON e sue V 15 5 3 2 Setup Example eet tt t dtt eae etes V 17 5 4 8 Timer Pulse Output 18 5 4 1 OperatiOn EE 18 5 4 2 Setup Example 2 nt eh predetto NEEN ENEE 19 5 5 8 PWM Output esie ENEE 21 5 5 1 Operation b dif pete teme 21 5 5 2 E DE OT 23 5 6 8 Timer Cascade Connection seen eene 25 5 6 1 Operation noto RU pir V 25 5 6 2 setup ose an ee ep eerie 26 5 7 Remote Control Career Output 28 5 7 1 Operation 28 5 7 2 Setup Example sepe ea bed 29 5 8 High Precision PWM Output V 31 5 8 1 RI e EE 31 5 8 2 Setup Examples 2
35. and Hold Time Conversion AD Ladder A D Conversion Input VI 5 onversion Resistance Setup Clock Selection Status Selection Selection X 12 Special Function Registers List Chapter 10 Appendices 10 6 5 10 61 General Usage iConnection of VDD pin and VSS of the and Vss pins are external Connect them directly to the power source and ground Put them on printed circuit board after the location of LSI package pin is considered Incorrect connection may lead a fusion and break a microcontroller iCautions for Operation 1 Ifyou install the product close to high field emissions under the cathode ray tube shield the package surface to ensure normal performance 2 X Operation temperature should be well considered Each product has different condition For example if the operation temperature is over the condition its operation may be executed wrongly 3 Operation voltage should be also well considered Each product has different operating range the operation voltage is over the operating range the length of its life may be shortened If the operation voltage is below the operating range it operation may be executed wrongly Circuit Setup X 13 Chapter 10 Appendices 10 6 2 Unused Pins mUnused Functions Unused functions should be set as operation is off 3 Port 3 is input pin in the initial status So if the input is unstable both of the Pch transistor an
36. gt JUUUUUUUL E Figure 5 7 3 Output Wave Form of TCO Output Pin Setup Procedure Description Disable the remote control carrier output TCOCNT x 06A bp6 0 Stop the counter TM2MD 04 bp3 2 0 Select the base cycle setting timer TCOCNT 06 TC230S 0 bp2 TCOS 1 Select the carrier output duty TCOONT 06 bp5 RMDTY 1 Set the output pin P23DIR x 012 bp6 PSDIR2 1 TCOCNT x 06A bp3 RMOS 1 bp7 TCOE 1 Set the RMOEN flag of the timer output control register TCOCNT to 0 to disable the remote control carrier output Set the TM2EN flag of the timer 2 mode register TM2MD to 0 to stop the timer 2 counting Set the timer 2 as a base cycle setting timer by the TC23OS flag and TCOS flag of the TCOCNT register Set the RMDTY flag of the TCOCNT register to 1 to select 1 3 duty Set the P3DIR2 flag of the port 2 port direction control register P23DIR to 1 to set P32 for output mode Set the RMOS flag and TCOE flag of the TCOONT register to 1 V 29 Remote Control Career Output Chapter 5 Timers Setup Procedure Description Select the normal timer operation TM2MD 04 bp4 TM2PWM 0 Select the count clock source TM2MD 04 bp2 0 TM2CK2 0 100 Set the base cycle of remote control carrier 2 054 x 6C Enable the remote control carrier outp
37. interrupt JMP instruction request acceptance interrupt 1 interrupt 1 service routine starts acceptance interrupt 1 interrupt 2 service routine i starts Interr dans interrupt 2 interrupt 2 OWhen two interrupt factors are generated at the same time the interrupt with higher priority is accepted If the second interrupt is not disabled in the program the operation is switched to accept the second one 1 cycle y no accpetance no accpetance gt lt gt 2 cycles instruction 2 JMP instruction 2 cycles instruction D i 4 JMP instruction interrupt request acceptance 1 interrupt 1 interrupt 1 Service routine start acceptance interrupt 1 interrupt 2 Service interrupt Acceptance of interrupt 2 routine request interrupt 2 is started here if the instruction after JMP instruction is any instruction except for EDI instruction interrupt 2 52 1 The contents of PC and FS in main program are pushed to the stack area 2 The starting address of the interrupt service routine is set to PC 3 IF and IE of the accepted interrupt are reset This example shows the case when the interrupt 2 is not disabled after the interrupt with higher priority the interrupt 1 is accepted first Therefore during the service routine of the interrupt 1 only 3 instruc tions JMP EDI 2
38. interrupt vector After the interrupt service routine the program counter and the flag status are restored the contents to the point at which execution was interrupted 3 Interrupt serice routine Main program Interrupt request flag and interrupt enable flag are cleared at head 2 K Hardware processing Save up PC FS 1 Interrupt 4 machine cycles 4 machine cycles 5 4 R Hardware processing estart Restore PSW FS up lt Figure 4 1 2 Interrupt Processing Sequence IV 4 Overview 1 Acceptance Operation The interrupt service routine is started when the interrupt is accepted by branching the program to the head of the interrupt service routine after an interrupt factor is generated First of all if an interrupt factor is generated the interrupt request flag IE with the corresponding level is set At that time if the interrupt enable flag is set and it is corresponded to the IF flag the generated interrupt factor can be accepted Acceptance operation is similar to the operation on CALL instruction On the acceptance cycle the program counter PC and the flag status FS are written to the stack They are pushed onto the stack Then the starting address of the interrupt service routine corresponded to the each factor is set to the program counter And reset the IE flag and IF flag with the corresponded level to the interrupt acceptance Each inter
39. voltage is supplied before Vdd is on a latch up occurs and causes the destruction of micro controller by a large current flow input input protection resistance forward current generates Figure 10 6 5 VDD and Input Pin Voltage i The Relation between VDD and Reset Input Voltage After power supply is on reset pin voltage should be low for sufficient time before rising in order to be recognized as a reset signal Power voltage Reset pins Low level Under input voltagg Enough time is necessary to recognize as reset Figure 10 6 6 Power Supply and Reset Input Voltage X 16 Circuit Setup Chapter 10 Appendices 10 6 4 Power Supply Circuit Cautions for Setting Power Supply Circuit The CMOS logic microcontroller is high speed and high density So the power circuit should be de signed taking into consideration of AC line noise ripple caused by LED driver Figure 10 6 7 shows an example for emitter follower type power supply circuit BAn Example for a Circuit of VDD Supply Emitter follower type Set condensors for noise filter near microcomputer power pins F VD Microcomputer Vs Figure 10 6 7 An Example for a Circuit of VDD Supply Emitter follower type For noize filter Circuit Setup X 17 Record of Changes MN15G0202 0402 LSI User s Manual Record of Changes First Edition to Second Edition 1 3 Details of Changes P
40. 002 PORT23 R W 2 port data register Il 13 X010 PO1DIR R W 0 port 1 direction control register Il 9 012 P23DIR R W 2 port direction control register Il 13 022 P23PLU R W 2 port 3 pull up resistor control register Il 13 x028 015 R W 1 output structure control register Ill 9 x02A 235 R W 2 port 3 output structure control register Il 14 x030 R W CPU mode register 1 15 x032 W mode register IV 16 x034 IRQCO R W Interrupt 0 control register IV 16 x036 IRQC1 R W Interrupt 1 control register IV 17 x038 KEYONT R W interrupt 1 control register IV 17 2 R W ACZ control register VII 5 044 TM2BC Timer 2 binary counter V 10 x046 Timer 3 binary counter V 10 x04C TM2MD R W Timer 2 mode register V 11 X04E R W Timer 3 mode register V 12 x054 20 R W Timer 2 compare register V 9 x056 DAN Timer 3 compare register V 9 05 R W Timer mode control register V 12 6 R W Timer output control register V 13 x06C 2 R W Buzzer output control register V 14 X06E WDCTR W Watchdog timer control register VIIL 4 070 ADBUFO converter data storage buffer 0 VI 6 x072 ADBUF1 converter data storage buffer 1 VI 6 x074 ADCTRO R W control register VI 5
41. 13 Power supply voltage 100 _ 14 Electrical Characteristics Chapter 1 Overview 40 to 85 2 0 V to 5 5 V Vnsr 12 to 5 5 V Vss 0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX Operation speed 3 0 V to 5 5 V 14 i At automatic reset 98 18 2 4 5 5 V Gel Instruction execution time ie At automatic reset 10 18 US 2 0 V VnsrL12 to 5 5 V 16 High oscillation 2 0 16 At automatic reset VpD Vh about 1 5 V t status of high D tabl unstable ti d high unstable genetalbott operation mode SC unstable H unstable Figure 1 6 1 Automatic Reset Voltage I 15 Electrical Characteristics Chapter 1 Overview 40 to 85 2 0 V to 5 5 V Vnsr 12 to 5 5 V Vss 0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX Oscillation High oscillation 17 Oscillation frequency 0 5 8 0 MHz 18 Cu 2 0 V to 5 5 V 30 0 External capacitors to 5 5 pF 19 C12 figure 1 6 2 30 0 20 Internal feedback resistor Rr1 500 0 1 When automatic reset is available OSCH 05602 Figure 1 6 2 Oscil
42. 1500402 4 128 nibble Mask ROM version MN15GP0402SJ 4 128 nibble EPROM version Table 1 1 2 Differences in Models Parameter MN15G0202 MN15G0402 MN15GP0402SJ Power supply voltage 2 0 V to 5 5 V 2 0 5 5 V 2 3 V to 5 5 V Ambient operating temperature 40 C to 85 C 40 C to 85 C 20 C to 70 C Mask option Automatic reset circuit 1 unused 2 Automatic reset 1 3 Automatic reset 2 1 unused 2 Automatic reset 1 3 Automatic reset 2 1 unused For mask option refer to 1 8 Option I 2 Overview Chapter 1 Overview 1 2 Hardware Functions Table 1 2 1 Basic Specification Model 1500202 MN15G0402 MN15GP0402 ROM version Mask ROM version EPROM version ROM 2 KB 4KB 4 128 nibble 128 nibble 128 nibble Package 20SOP Machine cycle When automatic reset is not used 0 50 us 8 MHz divided by 4 3 0 V to 5 5 V 1 00 us 4 MHz divided by 4 2 4 V to 5 5 V 2 00 us 4 MHz divided by 8 2 0 V to 5 5 V When automatic reset circuit 1 is used 0 50 us 8 MHz divided by 4 Vostra 0 5 5 V 1 00 us 4 MHz divided by 4 Vas 5 5 V 2 00 us 4 MHz divided by 8 Vast 5 5 V When automatic reset circuit 2 is used 2 00 us 4 MHz divided by 8 Vost 10 5 5 V Back up mode HALT mode STOP mode Ambient operating temperature 40 to 85 20 to 70 for 15 0402 Interrupts 3 levels I
43. 2PWM 0 Select the count clock source TM2MD 04 bp2 0 TM2CK2 0 001 Set the generation cycle 2 x 054 x F9 Clear the interrupt request flag IRQM x 032 bp5 IFIRQ2bE 1 Enable the interrupt Start the timer TM2MD 04 bp3 TM2EN 1 7 Set the TM2EN flag of the timer 2 mode register TM2MD to 0 to stop the counting of timer 2 Set the TM2PWM flag of the TM2MD register to 0 to select the normal timer operation Set the TM2CK2 0 flag of the TM2MD register to 001 to select fsys 8 as a clock source Set the interrupt generation cycle to the timer 2 compare register 2 It is divided by 250 so set the value to 249 GEO At that time the timer 2 binary counter TM2BO is cleared to 00 Set the IFIRQ2E flag of the IRQ mode register IRQM to 1 to clear the interrupt 2 request flag Execute EDI instruction to enable interrupt 2 t Chapter 4 Interrupts 4 1 1 Set the TM2EN flag of the TM2MD register to 1 to start the timer 2 The TM2BC starts to count up from x00 When the TM2BC reaches the setting value of the 2 register the interrupt 2 request flag is set at the next count clock then the value of the TM2BC becomes x 00 and restart to count up When the TMnEN flag of the TMnMD register is changed at the same time to other bit binary counter may start to count up by the switching operation 8 Bit Timer Operation
44. 3 as an interrupt source Set the IFIRQ3E flag of the IRQ mode register IRQM to 1 to clear the interrupt 3 request flag V 26 8 Bit Timer Cascade Connection Chapter 5 Timers Setup Procedure Description 8 Enable the interrupt 9 Start the upper timer operation TM3MD 04 bp3 1 10 Start the lower timer operation TM2MD 04 bp3 2 1 8 Execute EDI instruction to enable interrupt 3 IRQ3 9 Setthe TMSEN flag of the TM3MD register to 1 to start timer 3 10 Set the TM2EN flag of the TM2MD register to 1 to start timer 2 TM2BC counts up from x 0000 as a 16 bit timer When TM2BC reaches the set value of TM3OC 2 register the interrupt 3 request flag is set at the next count clock and the value of TM3BC TM2BC becomes x 0000 and restarts count up When any data is set to the compare register set data to both of TM3OC and TM2OC HM Hu Start the upper timer operation before the lower timer operation 8 Bit Timer Cascade Connection 27 Chapter 5 Timers 5 7 5 7 1 Remote Control Carrier Output Operation Carrier pulse for remote control can be generated of Remote Control Carrier Output Timer 2 Timer 3 Remote control carrier pulse is generated with output signal of timer 2 or timer 3 Duty cycle is selected from 1 2 1 3 At output to por
45. A D Converter 6 2 6 2 1 VI 4 Control Registers Registers Table 6 2 1 Converter Control Registers Register Address R W Function Page ADBUFO x 070 R conversion data storage buffer 0 VI 6 ADBUF1 x072 R conversion data storage buffer 1 VI 6 ADCTRO 074 RAW A D control register VI 5 P23DIR 012 RAW Port 2 port 3 direction control register Il 13 Control Registers Chapter 6 A D Converter 6 2 2 Control Registers BA D Converter Control Register ADCTRO 7 6 5 4 3 2 1 0 ADCTRO ADST ADSH1 ADSHO ADLADE ADCHS1 ADCHSO at reset ADCHS ADCSHO A D conversion input selection 0 ADO 1 AD1 0 AD2 1 ADLADE A D ladder resistance connection 0 no connected 1 connected ADCK A D conversion clock selection 0 fsys 1 fsys 2 ADSH1 ADSHO Sample and hold time 0 0 2 0 1 Tao x 6 1 0 Tao x 18 1 1 Reserved ADST A D conversion status 0 Stop 1 start Figure 6 2 1 Control Register ADCTRO x 074 R W Control Registers VI 5 Chapter 6 A D Converter 6 2 3 Data Buffers RAD Conversion Data Storage Buffer 0 ADBUFO The lower 2 bits from the result of A D conversion are stored to this register 7 6 5 4 3 2 1 0 ADBUFO ADBUF1 ADBUFO at reset
46. ACZ input by the ACZ1IN flag of the ACZ control register ACZCNT 3 Set the ACZ interrupt Set the interrupt source by the interrupt control register 1 IRQC1 Set the IRQ3S1 0 flag to 01 to select the ACZ input Select the interrupt edge by the IRQSSE flag and set the MASKIR3 flag to 1 to enable the interrupt edge mask Enable the interrupt 3 IRQ3 by the EDI instruction Chapter 4 4 2 Interrupt Control Register 4 Overview Chapter 7 A C Zero Cross Detector 7 2 Control Registers 7 6 5 4 3 2 1 0 ACZCNT E NSYNCS ACZIIN reserved at reset XXXXX000 reserved Set always to 211 P31 input data 0 port input 1 ACZ input NSYNCS P30 output data 0 port latch data output 1 NSYNC output ACZ Control Register ACZCNT x 03A R W Table 7 2 1 Zero Cross Detection Control Register Control Registers 5 Chapter8 Watchdog Timer Chapter 8 Watchdog Timer 8 1 Overview 8 1 1 Overview This LSI has a watchdog timer to detect errors in program The watchdog timer always counts and outputs the low level for reset after 216 counts of machine cycle Therefore the watchdog timer is restarted several times during programing to detect errors Restarting is done by writing 1 to the WDTCLR flag of the watchdog timer control register WDCTR Y The watchdog timer is stopped at HALT mo
47. Chapter 10 Appendices 10 1 Version 10 1 1 Overview EPROM version is microcontroller which was replaced the mask ROM of the MN15G0202 MN15G0402 with an electronically programmable EPROM These include the MN15G0202 MN15G0402 variants MN15GP0402SJ and PX AP15G0402 SY The MN15GP0402SJ is sealed in plastic Once data is written to the internal PROM it cannot be erased The PX AP15G0402 is sealed a ceramic package with a window Written data can be erased by exposing the physical chip to intense ultraviolet radiation Setting the EPROM version to EPROM mode functions as a microcomputer are halted and the internal EPROM can be programmed For EPROM pin connection refer to figure 19 1 2 Programming Adapter Connection The specification for writing to and reading from the internal EPROM are possible by using a dedicated programming adapter supplied by Panasonic Lab Site from Data I O after down loading them The EPROM Version is described on the following items Cautions on use of the internal EPROM Erasing Data in Windowed Package PX AP15G0402 SY Differences between mask ROM vers and EPROM vers Writing to the Microcomputer with internal EPROM Cautions on handling a ROM writer MN15GP0402S J is available only for engineering sample now Mask option is high speed H oscillation no auto reset 1 The PX AP15G0402 SY with windowed ceramic package is not supplied 2
48. Each bit can be set individually the output configuration by the port 1 output structure control register P23SC Set the control flag of the port 1 output structure control register P23SC to 1 for N ch open drain and to 0 for CMOS output ilSpecial Function Pin Setup P20 to P23 are used as analog input pin ADO to AD3 General port at reset Set pin to input mode by the port 2 port 3 direction control register P23DIR and set the port 2 port 3 output structure control register P23PLU to 0 to select pull up resistor OFF P30 is used as system clock synchronous output NSYNC General port at reset NSYNC output outputs the synchronous signal of the system clock at internal reset P31 is used as interrupt input NIRQ AC zero cross detection input ACZ General port at reset NIRQ is input pin of interrupt 1 Set P31 to input mode At operation the initial status is P31 but the ACZONT register can switch NSYNC output port data output AC zero cross detection input ACZ is input pin of AC zero cross circuit ACZCNT register can switch port input data ACZ input Port2 3 11 Chapter3 Ports P32 is used as timer output TCO and as buzzer output BZ General port at reset TCO is timer output pin TCOCNT register can switch timer output port data output BZ is buzzer output pin BZCTR register can switch buzzer output port data output Also P30 P31 and P32 are used as key interrupt When key interru
49. G12 8FP Tel 1344 85 3773 Fax 1344 85 3853 FRANCE SALES OFFICE Panasonic Industrial Europe G m b H PIEG Paris Office 270 Avenue de President Wilson 93218 La Plaine Saint Denis Cedex Tel 14946 4413 Fax 14946 0007 B ITALY SALES OFFICE Panasonic Industrial Europe G m b H PIEG Milano Office Via Lucini N19 20125 Milano Tel 2678 8266 Fax 2668 8207 TAIWAN SALES OFFICE Panasonic Industrial Sales Taiwan Co Ltd PIST Head Office 6th Floor Tai Ping amp First Building No 550 Sec 4 Chung Hsiao E Rd Taipei 10516 Tel 2 2757 1900 Fax 2 2757 1906 Kaohsiung Office 6th Floor Hsien 1st Road Kaohsiung Tel 7 223 5815 Fax 7 224 8362 Matsushita Electric Industrial Co Ltd 2001 HONG KONG SALES OFFICE Panasonic Shun Hing Industrial Sales Hong Kong Co Ltd PSI HK 11 F Great Eagle Centre 23 Harbour Road Wanchai Hong Kong Tel 2529 7322 Fax 2865 3697 SINGAPORE SALES OFFICE Panasonic Semiconductor of South Asia PSSA 300 Beach Road 16 01 The Concourse Singapore 199555 Tel 390 3688 Fax 390 3689 MALAYSIA SALES OFFICE Panasonic Industrial Company Malaysia Sdn Bhd Head Office Tingkat 16B Menara PKNS PJ No 17 Jalan Yong Shook Lin 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 03 79516606 Fax 03 79516656 Penang Office Suite 20 17 MWE PLAZA No 8 Lebuh Farquhar 10200 Penang Malaysia Tel 04 2625550 Fax 04 2619989 Johore Sales Office
50. I 16 Back Up Mode Chapter 2 Basic CPU There are 2 interrupts that can be recovered from STOP mode Interrupt 1 IRQ1 Interrupt 3 IRQ3 except timer 3 ex HALT mode usage example EDI 0 7 Even any interrupt is generated that can be recovered from HALT mode instructions except EDI WI There are 3 interrupts that can be recovered from HALT mode Interrupt 1 IRQ1 Interrupt 2 IRQ2 Interrupt 3 IRQ3 1 More than 1 NOP should be inserted after WI instruction In cross assembler we offer NOP is automatically inserted Back Up Mode 17 Chapter 2 Basic CPU 2 5 1 Cautions on Back Up Mode W O port Pull up resistance for pins at high impedance should be set by the software with corresponding the voltage level of external circuit at backup to save the electric consumption at port Set the voltage level of the input port to H level or L level If the level is middle micro controller spend much more the electric consumption mRecover from STOP mode If the power supply voltage is less than 1 8 V at recover RAM data after recover may be damaged In this case reset by the external circuit II 18 Back Up Mode 2 6 Reset 2 6 1 Reset Operation Chapter 2 Basic CPU The CPU contents are reset when the NRST pin is pulled to low from external or outputs L level by overflow of watchdog timer by low voltage detector of auto reset circuit When a reset is generate
51. IME I 7 1 4 1 Pins Configuration ys eto eth e n ee petes I 7 1 4 3 Pin E nctions 1 8 Special Function Registers eese nennen renes 1 11 1 5 1 Register onte perraro PERO RP RR 1 11 1 5 2 Special Function Registers I 12 Electrical Characteristics s och tte eer erepto I 13 1 6 1 Absolute Maximum Ratings I 13 1 6 2 Operating Conditions 14 1 6 3 DC Characteristics e 1 18 1 6 4 A D Converter Characteristics I 22 External ERRORI GERI EE I 23 I 24 1 8 1 Mask Option cedere edem pee teneas I 24 1 8 2 Mask Option Form Ver 009 I 25 Chapter2 Basic CPU contents 2 1 2 2 2 3 Clock EEN 2 2 1 1 Clock Generator P ore ote e counties II 2 2 1 2 CPU Basic Timing ongoing teens II 3 Register Set iiec e eei lege E hn ole edt 4 Memory e eH eere a oo 8 2 3 1 ROM Address Space 2 8 2 3 2 ROM Address Space 4 II 10 2 3 3 RAM Address Spaces ie evene epe II 12 2 3 4 Stacked Area ie epp Ste te edere Pepe ep rr II 13 Clock Switching eene e pt t hec eed Ape II 14 2 4 1 Glock Switching oi
52. M2MD register to TM2MD x 04C 1 to start timer 2 bp3 2 1 8 Bit Timer Pulse Output 19 Chapter 5 Timers TM2BC counts up from x00 When TM2BC reaches the setting value of the TM2OC register and is cleared to x 00 output signal is reversed then TM2BC count up is restarted from 00 The timer pulse output at TMnOC x 00 has the same waveform at TMnOC x 01 If any data is written to the compare register during the binary counter is stopped timer output is reset to H 20 8 Bit Timer Pulse Output Chapter5 Timers 5 5 8 Bit PWM Output TCO or port 1 outputs the PWM waveform with generating the PWM basic component that is decided by the timing that the binary counter reaches the set value of the compare register and the overflow timing of the binary counter 5 5 1 Operation BOperation of 8 Bit PWM Output Timer 2 The PWM waveform with an arbitrary duty cycle is generated by setting the duty cycle of PWM H period to the timer 2 compare register TM2OC The cycle is the period from the full count to the overflow of the 8 bit timer Table 5 5 1 shows PWM output pins Table 5 5 1 Timer Pulse Output Pins timer 2 TCO output pin P32 P10 P13 pins PWM output pin iCount Timing of PWM Output at normal Timer 2 2 flag compare register binary 1 o Y 01 zx N 00 01 Lui N co
53. OL ROR Bo RDTBL EA mPCDda _ ZF CF ACF ZF CF ZF CF ZF4CF ZF A SB O o T PAD da PACD da PSBD daOD da PXD da da da CF ZF CF ZF CF ZF CF ZF ZF ZF ZF ZFICF 2 Zig CF ZEgCF 24 Icy sticy DcY LDCY STDCY ET STBD 2 ZF ZE ZE 4 JMPEAPMDdaP bpda _ 7 b ZF ZEN 26 4 EXSX EXSY EXSE PEXDdaLxX Lv EX RUBY E nl ZF ZF UPXO LUX PSTD dalSTX 5 STE 97 5 ICEA DCEA Drm c c CF CF PCMD daPROUT au DCM PSHEA 2 POPXY Z DC mi CF ZF CF ZE ZF CF ZE 4 4 geg Nim Een T uns JBNZ bpm A A 4 wrB EE EEN EEN 4 EEN GAEE HIS 4 EE A EE EE EE e Ee ZF 4 EES EV ea EE el ei ee EN EENS EE 1 byte 1 cycle instruction J 1 byte 2 cycles instruction 2 bytes 2 cycles instruction 3 bytes 3 cycles instruction Instruction Map 9 Chapter 18 Appendices 10 4 Differences between MN1500 and MN15G Table 10 4 1 Differences between MN1500 bank vers linear vers And MN15G MN1500 series b
54. Setup Example BPWM Output Setup Example Timer 2 The 1 4 duty cycle PWM output waveform is output from the TCO output pin at 244 Hz by using timer 2 The oscillation is at low frequency oscillation fx at fosc 4 MHz Cycle period of PWM output wave form is decided by the overflow of the binary counter H period of the PWM output waveform is decided by the setting value of the compare register An example setup procedure with a description of each step is shown below TCO output 244 Hz Figure 5 5 4 Output Waveform of TCO Output Pin Setup Procedure Description 1 Stop the counter TM2MD 04 bp3 TM2EN 20 2 Setthe special function pin to the output mode TCOONT 06 bp1 2305 0 bp2 5 1 bp3 RMOS 0 bp7 TCOE 1 P23DIR x 012 bp6 PSDIR2 1 3 Select the PWM operation TM2MD x 04C bp4 2 1 4 Select the count clock source TM2MD 04 bp2 0 206 2 0 111 1 Set the TM2EN flag of the timer 2 mode register TM2MD to 0 to stop the timer 2 counting Set the TCOE flag of the timer output control register TCOCNT to 1 to set P32 pin to the special function pin Set the timer 2 as output source by the 230 flag the TCOS flag and the RMOS flag Set the PSDIR2 flag of the port 2 port direction control register P23DIR to 1 to set output mode _ Chapter 3 Ports If it necessary add pull up re
55. a output can be selected by the ACZCNT register These can be used as key interrupt input ACZ 18 Input P31 AC zero cross AC zero cross detection circuit input pin NIRQ detection input AC zero cross detection circuit is connected to ACZ key1 interrupt input and P31 input circuit P31 ACZ input port input can be selected by the ACZCNT register These can be used as key interrupt input BZ 20 Output P32 Buzzer output Buzzer output pin TCO Buzzer output port data output can be selected by the key2 BZCTR register When not used for buzzer output this can be used as normal port This can be used as Key interrupt input NIRQ 19 Input P31 Interrupt input Interrupt 1 IRQ1 input pin ACZ When not used for interrupt input this can be used as key1 normal port This can be used as key interrupt input TCO 20 Output P32 Timer output Timer output pins BZ Timer output port data output can be selected by the key2 TCOCNT register When not used for timer output this pin can be used as normal port This can be used as key interrupt input 1 9 Pin Description Chapter 1 Overview Table 1 4 3 Pin Function Summary 3 3 Name Pin VO Dual Function Function Description NO 0 18 Input P30 Key interrupt input Key interrupt input NSYNC Each bit can be set individually as either an enable or 19 1 disable by the KEYONT register NIRQ When not used for key i
56. able Interrupt Control Register 1 IRQC1 x 036 R W 7 6 5 4 3 2 1 0 at reset X000XXXX KEYOEN Enable of key interrupt keyO 0 mask 1 enable KEY1EN Enable of key interrupt key1 0 mask 1 enable KEY2EN Enable of key interrupt key2 0 mask 1 enable Key Interrupt Control Register 1 KEYCNT 038 R W Figure 4 2 2 Interrupt Control Register 2 2 Control Registers IV 17 Chapter 5 Timer Chapter 5 Timers 5 1 8 Timer This LSI contains two general 8 bit timers Timer 2 Timer 3 The general 8 bit timers can be used as a 16 bit timer on cascade connection Fosc or fsys can be selected as clock source of each timer by using output from prescaler Also remote control output circuit is built in P32 TCO pin can output pulse signal for each timer At output to P32 TCO pin set output mode by the port 2 port 3 direction control register P23DIR and select the timer output by the timer output control register TCOCNT x 06A At output to P10 PWMOO P13 PWMOS pin set output mode by the port 0 port 1 direction control register PO1DIR and set the port 0 port 1 data register PORTO1 to 1 to output Select PWM output by the buzzer output control register BZCTR 06 V 2 Overview 5 1 1 Functions Table 5 1 1 shows functions th
57. age Definition m m Previous Edition First Edition New Edition Second Edition chade Product name 3 MN15GP0402 MN15GP0402SJ 1 2 Delete Table 1 1 2 Differences in Models Mask Option Oscillation circuit 1 3 Delete Machine Cycle When automatic reset is not used 122 5 32 768 kHz divided by 4 When automatic reset circuit 1 is used 2 0 V to 5 5 V When automatic reset circuit 2 is used 1 4 Delete Mask Option Oscillation is selected from high low RC Port NRST input 1 ports 2x Key input 3 ports for NSYNC output NIRQ Addition input ACZ input timer output and buzzer output too PWM output 4 ports Table 1 3 1 Functions on Blocks 1 5 Delete Clock generator Clock generator Block Underlined part is deleted Connect resonator to 5 1 05 2 to generate system clock At RC oscillation in mask option connect RC to external to generate system clock 1 8 Delete Table 1 4 1 Pin Function Summary 1 3 OSC1 OSC2 Underlined part is deleted Connect these oscillation pins to oscillators for clock operation Feedback resistor is built in Not connected at RC oscillation NRST After reset is cleared internal reset is cleared after 2 counts of OSC input clock at high Underlined part is deleted oscillation and 27 counts of OSC input clock at low RC oscillation RAA 5 Specifications figures and warnings on g Chapter 1 4 1 Operating Conditions low oscillation and RC oscillation a
58. al oscilla tors and capacitors Connect a crystal or ceramic oscillator Figure 2 1 1 a When RC oscillation is selected the circuit require external capacitors and resistors Oscillation frequency may be changed by capacitors Oscillator circuit connection b is resistors temperature and voltage or so Figure deleted 2 1 1 b 1 3 Delete Chapter 2 1 2 CPU Basic Timing At 4 0MHz at high speed oscillation 1 machine cycle is 1 0 us at divided by 4 and 2 0 us at divided by 8 At 32 kHz at low speed oscillation THE part 15 06660 1 machine cycle is 122 us at divided by 4 250 at divided by 8 ll 14 Delete Chapter 2 4 1 Clock Switching At fosc 4 0 MHz instruction cycle is 1 0 us at divided by 4 and 2 0 us at divided by 8 Underlined part is deleted And at fosc 32 kHz 125 us at divided by 4 MN15G0202 0402 LSI User s Manual Record of Changes First Edition to Second Edition 3 3 Details of Changes Page Definition Previous Edition First Edition New Edition Second Edition 120 bed B Timing of reset release PES After the NRST pin becomes there is 2 pulse counts of OSC input clock fosc at Underlined part is deleted high speed oscillation 27 pulse counts at low speed oscillation RC oscillation till the internal reset is released V 23 m PWM Output Setup Example Timer 2
59. am in 3 to the address from microcomputer address x 0000 to the final address of the internal ROM The internal ROM space of this LSI is from 0000 t Chapter 2 2 2 Memory Space 1 This writer has no internal ID codes of Silicon Signature and Intelligent Identifier of the auto device selection command of ROM writer If the auto device selection command is to be executed for this writer the device is likely damaged Therefore never use this command iWhen the writing is disabled When the writing is disabled check the following points 1 Check that the device is mounted correctly on the socket pin bending connection failure 2 Check that the erase check result is no problem 3 Check that the adapter type is identical to the device name 4 Check that the dedicated device for writing is used 5 Check that the data is correctly transferred to the ROM writer 6 Recheck the check points 1 2 and 3 provided on the above paragraph of Cautions on Handling the ROM writer eee Please contact the nearest semiconductor design center See the attached sales office table when the writing is disabled even after the above check points are confirmed and the device is replaced with another one 6 EPROM Version 10 2 Instruction Set Chapter 10 Appendices
60. ank vers linear vers MN15G series Data in units of 8 bits is written to the special buffer SB Data in units of 8 bits is read from WTSB WTSB RDSB serial interface function is RDSB R operated the special buffer SB SBTIN SBTIN Instruction SBTEX SBTEX WTTC WTTC WTTB WTTB Data in units of 8 bits is written to timer function is operated the temporary buffer TB Data in units of 8 bits is read from the temporary buffer TB External interrupt Interrupt 1 Interrupt factor Timer interrupt Interrupt 2 Serial interrupt Interrupt 3 X 10 Differences between MN1500 and MN15G 10 5 Special Function Registers List Chapter 10 Appendices MN15G0202 Special Function Registers List 1 2 Bit Symbol Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P13DATA P12DATA P11DATA P10DATA PO3DATA PO2DATA PO1DATA POODATA 000 1 lll 9 Port 1 VO Data Port 0 VO Data P32DATA P31DATA P30DATA P23DATA P22DATA P21DATA P20DATA x 002 PORT23 ll 13 Port 3 Data Port 2 VO Data P1DIR3 P1DIR2 P1DIR1 P1DIRO PODIR3 PODIR2 PODIR1 PODIRO 010 P0O1DIR lll 9 Port 1 Direction Control Port 0 Direction Cont
61. apter 6 A D Converter DE Chapter 6 A D Converter 6 1 Overview This LSI has an A D converter with 10 bits resolution That has a built in sample hold circuit and soft ware can switch channel 0 to 3 ANO to AN3 to analog input As A D converter is stopped the power consumption can be reduced by a built in ladder resistance 6 1 1 Functions Table 6 1 1 shows the A D converter functions Table 6 1 1 A D Converter Functions A D input pins 4 pins Pins ADS to ADO Resolution 10 bits Conversion time 12 0 us at fosc 4 MHz divided min by 4 Input range Vss to VDD Save power Built in Ladder Resistance comsumption ON OFF VI 2 Overview Block Diagram Chapter 6 A D Converter ADCTRO ADBUF1 ADBUFO ADCHSO 2 ADBUF2 10 0 51 ADBUF3 ADBUF4 ADLADE ADBUF5 ADCK ADBUF6 ADSHO ADBUF7 ADSH1 A D conversion ADBUF8 ADBUFO gt control ADBUF9 ADBUF1 2 2 VDD ES A D conversion Hata upper 8bit e ADO Vv ge Sample 10 bits A D MUX gt 2 gt and hold converter x y A D conversion data AD3 lower 2bits Vss i aoo fsys 1 2 MUX 0 0 1 6 MUX 1 2 1 18 Figure 6 1 1 Converter Block Diagram Overview VI 3 Chapter 6
62. at can be used with each timer Chapter5 Timers Table 5 1 1 Timer Functions timer 2 timer 3 8 bit 8 bit interrupt 2 interrupt 3 interrupt factor IRQ2 8 bit timer operation independent timer pulse output remote control carrier output PWM output interrupt factor interrupt 3 IRQ3 16 bit timer operation cascade connection timer pulse output high precision PWM output fsys 2 fsys 2 fsys 8 fosc fsys 32 fosc 25 fsys 128 fosc 2 4 clock source fosc fosc 4 fosc 16 fosc 64 fosc machine clock oscillation input fsys system clock 4 Chapter 2 2 4 Clock Switching built in ohter prescaler 7 steps Overview V 3 Chapter 5 Timers 5 1 2 Block Diagram 2 Block Diagram S2 internal clock 1 2 gt M 6 bit prescaler U 1 4 ue 64 4 fosc X M U 24 x 1 i gt Sa Read Write 1 compare register 20 054 timer 2 interrupt the match 2 tm2cmp 1 2 gt M gt timer 2 output 8 bit counter WW ge gt 4 gt X TM2BC x044 gt circuit Y f Read count 7 contro circuit lt TM2PWM 1 TM2EN TM2CK2 TM2CK1 o
63. c ert OUO II 14 2 4 2 CPU Mode eee cedes II 15 2 6 Back Up Mode 2e onse geo PRO up e ERU OU RES II 16 2 5 1 Cautions on Back Up Mode essere 18 Reset zzii iere nd heeieiestui ES II 19 2 6 1 Reset Operation eine a tei de II 19 Chapter 3 Ports 3 1 3 2 3 3 OVerVIe Wise ead Mai 2 3 1 1 Port E EE RE E 2 3 1 2 Port Functions inocente eu e HR UR 3 3 1 3 Port Status at 222 221 2 2 M 4 3 1 4 Port Disposal at 010864 ed te tee iere tien II 5 3 1 5 Setup Example 5 5 m gin SE III 6 3 1 6 Contro Registers iO UHR er rues 7 8 3 2 1 Description 8 3 2 2 UE 9 3 2 3 Block Diagram nete nO De dtes III 10 Port 2 Port ea ete t RUM a eae 11 3 3 1 ois 11 3 3 2 Registers i eere erm De qe RES III 13 3 3 3 Block Di gr m ENEE Ee See 15 Chapter 4 Interrupts 4 1 4 2 VEL VIC Wises i ote p d ERREUR REDE EDO REOR IV 2 4 1 1 E nctions 23 2 o er eio eege IV 2 4 1 2 Block Dia Sram eee t eee ited ceases IV 3 4 1 3 Operation asa ies ea A ed EE 4 4 1 4 Interrupt Flag Set p IV 13 Control Registers ito n e itp 15 4 2 1 Registers Past eege teen
64. cycles instruction are executed then the operation is switched to the acceptance of the interrupt 2 Overview IV 11 Chapter 4 Interrupts OWhen an interrupt factor with high priority is generated at the acceptance operation at 1st cycle it is regarded as a multiple interrupt and the interrupt with higher priority is accepted no acceptance 1 cycle 2 cycles instruction 52 instruction interrupt request interrupt interupt2 request service routine interrupt 1 starts interrupt 1 OWhen an interrupt factor with high priority is generated at the acceptance operation at 2nd cycle the first interrupt is accepted no acceptance 1 cycle no acceptance lt lt gt 4 2 cycles instruction 2 JMP instruction Disable EDI interrupt 1 Enable EDI interrupt 1 2 interrupt 4 JMP instruction request interrupt i x interrupt 2 request X Service routine interrupt 1 starts acceptance interrupt 2 interrupt 1 Service routine starts interrupt 1 1 The contents of PC and FS in main program are pushed to the stack area 2 The starting address of the interrupt service routine is set to PC 3 IF and IE of the accepted interrupt are reset 2 IV 12 Overview 4 1 4 BNIRQ External Interrupt Setup Example Setup Example Chapter 4 Interrupts P31 NIRQ pin is input pulse
65. d registers and data memory is initialized Y Auto reset circuit is mask option Table 2 6 1 Initial Value of Register Memory Register Memory Symbol Initial value 1 Program counter PC 0 2 accumulator A 0 3 E register E 0 4 X register X 0 5 Y register Y 0 6 Carrier flag 0 7 Zero flag ZF 0 8 Special buffer SB indefinite 9 Temporary buffer TB indefinite 10 RAM indefinite 11 Stack pointer SP 0 12 Interrupt flag IF 0 13 Interrupt disable disable 14 Port data register 1 15 Port control register 0 16 Control register CR 0 1 Some registers can not be set to 0 For detail refer to instructions of each register Reset II 19 Chapter 2 Basic CPU Binitiating a reset The CPU contents are reset when the NRST pin is pulled to low from external or outputs L level by overflow of watchdog timer low voltage detector of auto reset circuit For stable reset the NRST pin should keep L for more than 1 machine cycle i Timing of reset release After the NRST pin becomes there is 27 pulse counts of input clock fosc The period from counting to overflow is called oscillation stabilization wait time This period is automatically inserted at reset release at recover from STOP mode This is happened because if the internal reset is released when source oscillation of the system clock is unstable m
66. d Nch transistor of the input inverter are operated so that the through current is happened and the electricity consumption is wasted the power inside of chip can be damaged by noise Pull up or pull down should be added when they are not used Note The above is in the case of the initial status input If the pin s direction is switched to output set them open P3 pin some 10 kQ input 4 AA input lt Hv some 10 P3 pin Figure 10 6 1 Port 3 input output Figure 10 6 2 Port 3 output through current current Pch input pin input Nch 0 5 input voltage 5 V Input Inverter Organization Input Inverter Characteristics Figure 10 6 3 Input Inverter Organization and Characteristics X 14 Circuit Setup WPort 0 port 1 port 2 Chapter 10 Appendices The initial status of port 1 port 2 and port 3 is input pin but gate is opened only at the execution of input instruction so that the through current cannot be happened As they are not used they should be open nevertheless of pin s direction output control data OPEN input input instruction OPEN input instruction Figure 10 6 4 OPEN input instruction Nch data OPEN input input instruction Port 0 Port 1 Port 2 Circuit Setup X 15 Chapter 10 Appendices 10 6 3 Power Supply mThe Relation between Power Supply and Input Pin Voltage Input pin voltage should be supplied only after power supply is on If the input
67. d back resistor is buit in If the clock is an external input connect it to OSC1 and leave OSC2 open NRST 17 vO Reset input pin Reset by inputting L to NRST pin Schmitt After reset is cleared internal reset is cleared after 214 counts of OSC input clock The output configuration is N ch open drain Reset can be selected by watchdog timer or low voltage detector 1 by automatic reset circuit 1 Autoreset circuit is mask option 5 vO VO port 0 Parallel data port P01 6 Each bit can be set individually as either an input or 2 7 output by the PO1DIR register P03 8 The output configuration is N ch open drain At reset the input mode high impedance output is selected P10 9 VO PWMOO VO port 1 Parallel data port P11 10 PWMO 1 Each bit can be set individually as either an input or P12 11 PWMO2 output by the PO1DIR register P13 12 The output configuration is CMOS push pull or N ch open drain Each bit can be switched individually by the P01SC register At reset the input mode high impedance output is selected They can be also used for PWM output PWMOO to 3 P20 13 VO ADO VO port 2 Parallel data port P21 14 AD1 Each bit can be set individually as either an input or P22 15 AD2 output by the P23DIR register P23 16 AD3 A pull up resistor for each bit can be selected individually by the P23PLU register The output configuration is CMOS push pull or N ch open drain Each bit can be sw
68. d in instruction code indicates the branched address for no condition or of subroutine Directly specified address is 12 bit PCh PCm PCI an arbitrary address can be speci fied address 2 ex JMPL CALLL instruction Address that is directly specified in instruction code indicates the branched address for no condition or for subroutine PCu should be set to 0 llSpecial address zero page x 0000 to x O0FF ex CALS instruction Address that is specified in instruction code indicates the branched address for subroutine by 16 byte in zero page E Accumulator indirectly address ex JMPEA instruction Address that is specified in 4 bit of E register upper address and in 4 bit of A register lower address indirectly indicates the branched address for no condition That is branched in the same page Cautions the branch instruction with condition JC JZ JNZ JBZ JBNZ CYIJ Conditional branch instruction is branched to the address that is indicated in 2 byte of instruction in the same page if condition is set At the border of page jump address is to the next page Address Machine code 000 015 1 oFE 6F OFF 15 lt PCh PC8 to PC11 100 lt 2 is changed here 115 lt 3 1FF As shown the above example if JC instruction is located from x OFE to x OFF it is branched to the address that is indicated in 2 when condition is set And whe
69. ddress can be specified by program counter E register or accumulator 1 page for 256 byte and ROM is divided by maximum 8 pages address in page ex JZ JNZ instruction Address that is directly specified in instruction code indicates the branched address in the same page x 000 x 020 as 2 1 JZ 20 as 2 0 II 8 Memory Space 2 Basic CPU address 1 ex JMP CALL instruction Address that is directly specified in instruction code indicates the branched address for no condition or of subroutine Directly specified address is 12 bit PCh PCm PCI an arbitrary address can be speci fied address 2 ex JMPL CALLL instruction Address that is directly specified in instruction code indicates the branched address for no condition or for subroutine PCu should be set to 0 llSpecial address in zero page x 0000 to x O0FF ex CALS instruction Address that is specified in instruction code indicates the branched address for subroutine by 16 byte in zero page Accumulator indirectly address ex JMPEA instruction Address that is specified in 4 bit of E register upper address and in 4 bit of A register lower address indirectly indicates the branched address for no condition That is branched in the same page Cautions on the branch instruction with condition JC JZ JNZ JBZ JBNZ CYIJ Conditional branch instruction is bra
70. de STOP mode gt Clear the watchdog restart timer main program Figure 8 1 1 Flow Chart VIII 2 Overview 8 1 2 Block Diagram fsys S2 reset input R 216 4 jl clear instruction Chapter 8 Watchdog Timer NRST X lt Figure 8 1 2 Watchdog Timer Block Diagram Overview VIII 3 Chapter 8 Watchdog Timer 82 Control Registers 7 6 5 4 3 2 1 0 WDCTR S 1 WDTCLR at reset 8 WDTCLR clear the watchdog timer 0 operate 1 clear Watchdog Timer Control Register WDCTR 06 W Figure 8 2 1 Watchdog Timer Control Register 4 Control Registers Chapter 9 Automatic Reset Chapter 9 Automatic Reset 9 1 Overview 9 1 1 Overview This LSI has 2 sets of auto reset circuit that detect low voltage mask option When low voltage VRSTL is detected the NRST pin becomes automatically L level for reset And if the power supply voltage reaches the reset release voltage VRSTH the NRST pin becomes by the hardware and reset is released When the auto reset circuit 2 is used the machine cycle should be more than 2 Y When the power is supplied take enough time for the reset pin voltage to be realized as reset signal VoD Vh about 1 5 V MN MN I status of high unstable i ope
71. e available MN1500 Series Instruction Manual Describes the instruction set MN1500 Series Cross assembler User s Manual Describes the assembler syntax and notation MN1500 Series Source Code Debugger User s Manual Describes the use of source code debugger gt MN1500 Series PanaX Series Installation Manual Describes the installation of cross assembler and source code debugger and the procedure for bringing up the in circuit emulator iaWhere to Send Inquires We welcome your questions comments and suggestions Please contact the semiconductor design center closest to you See the last page of this manual for a list of addresses and telephone numbers About This Manual 2 About This Manual 3 Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Overview Basic CPU Ports Interrupts Timers A D Converter AC Zero Cross Detection Watchdog Timer Automatic Reset Chapter 10 Appendices ii Contents Chapter 1 Overview 1 1 1 2 1 3 1 4 1 6 1 7 1 8 sas I 2 1 1 1 Product Summary tret err p ee census Fe eee de I 2 Hardware endete I 3 Block Diagram s dera Se escena pepe dae ete ed eee I 5 1 3 1 ONVeEVIe Ws oca a eee tee ie ae eie ee EAE ee aote I 5 1 3 2 Block Diagram tao heo are I 6 Pin Description ze EROR RE suite E T
72. e byte direct M da 1 lt EM da lt A Data in E register and accumulator are transferred to the address in RAM specified directly da Data in E register is transferred to odd address da 1 data in accumulator is transferred to even address da register IR This register reads out the instruction that CPU is going to execute from ROM and latches iProgram counter This register controls the execution order of instructions in program memory PCu should be set to 0 Register Set 5 Chapter 2 Basic CPU WX register This register is 4 bit register indirectly specifies RAM area It specifies upper 4 bits of RAM address X Y WY register This register is 4 bit register indirectly specifies RAM area It specifies lower 4 bits of RAM address X Y Stack register for X register SX This is RAM for X register to stack It can be used as normal RAM RAM address X 0 0 iStack register for Y register SY This is RAM for Y register to stack It can be used as normal RAM RAM address X 0 0 Stack register for E register SE This is RAM for E register to stack It can be used as normal RAM RAM address X 0 2 II 6 Register Set Chapter 2 Basic CPU iFlag status Two flags CF and ZF reflect operation s results reflects LI instruction execution status CF Carry Flag The carry flag is set when ALU operation results is an overflow or an underflow Othe
73. eas e XN Pe e tes X 2 10 1 1 TEE 2 10 1 2 Cautions on EE 3 10 1 3 Differences between Mask ROM version and EPROM version X 4 10 14 Writing to Microcomputer with Internal EPROM X 5 10 1 5 Cautions on Operation of ROM Writer 2 X 6 IMStPUCTION Set reete X 7 Instruction Map sce EE X 9 Differences between MN1500 and 15 6 X 10 Special Function Registers List 11 E E 13 10 6 1 Usage phie i snt aen EE E E 13 10 6 2 Unused EE X 14 10 6 3 Power Supply ideae ep de Pe Retro EES X 16 10 6 4 Power Supply Circuit enne X 17 V contents Chapter 1 Overview Chapter 1 Overview 1 1 Overview This LSI is 4 bit single chip microcomputer The MN15G0202 has an internal 2 KB of ROM and 128 nibble of RAM and the MN15G0402 has an internal 4 KB of ROM and 128 nibble of RAM Peripheral functions include 2 sets of 8 bit timer counters They can be used as 16 bit counter on cascade connec tion 10 bit A D converter AC zero cross detection circuit buzzer output circuit and LED driver pins 1 1 1 Product Summary This manual describes the following models of the MN15GXX02 series These products have identical functions Table 1 1 1 Product Summary Model ROM Size RAM Size Classification MN15G0202 2 128 nibble Mask ROM version
74. egister in advance If the binary counter TMnBC reaches the setting value of the compare register an interrupt request is generated at the next count clock then binary counter is cleared and counting up is restarted from 00 Table 5 3 1 shows clock source that can be selected by timer Table 5 3 1 Clock Source Timer 2 Timer 3 at Timer Operation source timer2 timer3 8 bit 8 bit fosc 4 fosc 2 _ fosc 4 y fosc 16 3 fosc 64 2 y 4 fosc 2 4 5 4 fsys 2 4 fsys 8 4 fsys 32 Y fsys 128 y 8 Bit Timer Operation 15 Chapter 5 Timers iBCount Timing of Timer Operation Timer 2 Timer 3 Binary counter counts up with selected clock source as a count clock The basic operation of the whole function of 8 bit timer is as follows count clock TMnEN flag compare register binary counter interrupt request flag MN a OF 22202 B Figure 5 3 1 Count Timing of Timer Operation Timer 2 Timer 3 If the value is written to the compare register during the TMnEN flag is stopped 0 the binary counter is cleared to 00 at the writing cycle If the TMnEN flag is operated 1 the binary counter is started to count The counter starts to count up at the falling edge of the count clock If the binary counter reaches the value of the compare register the interrupt request flag is set at
75. egister V 12 x06A R W timer output control register V 13 PO1DIR x 010 port 0 port 1 direction control register P23DIR 012 port 2 port 3 direction control register BZCTR 06 buzzer output control register TM3BC 046 timer 3 binary counter TM3OC x 056 timer 3 compare register TM3MD 04 timer 3 mode register timer 3 TCOCNT x06A timer output control register PO1DIR 010 R W 0 port 1 direction control register Ill 9 P23DIR 012 R W 2 port 3 direction control register ll 13 BZCTR 06 R W buzzer output control register V 14 R W Readable Writable Readable only V 8 8 Bit Timer Control Registers Chapter 5 Timers 5 2 2 Compare Registers Compare register is register that the value compared to the binary counter is set Timer 2 Compare Register TM2OC 7 6 5 4 3 2 1 0 TM20C TM20C7 TM20C6 TM20C5 2004 TM20C3 TM20C2 TM20C1 TM20C0 at reset XX X X XXXX Timer 2 Compare Register TM2OC x 054 R W 3 Compare Register 7 6 5 4 3 2 1 0 TM30C 30 7 TM30C6 TM30C5 TM30C4 TM30C3 2 TM3OC1 TM30C0 at reset X X X XXX X X Timer 3 Compare Register TM3OC x 056 R W Figure 5 2 1 Compare Register 8 Bit Timer Control Registers V 9 Chapter 5 Timers 5 2 3 Binary Counters Binary counter is 8 bit up counter Binary coun
76. eration Chapter 6 A D Converter 6 3 1 Setup Binput Pins of A D Converter Setup Input pins for A D converter is selected by the 51 to 0 flag of the ADCTRO register Table 6 3 1 Input Pins of A D Converter Setup ADCHS1 ADCHSO A D pin 0 ADO pin 1 AD1 0 AD2 i 1 AD3 pin of A D Converter Setup The A D converter clock is set by the ADCK flag of the ADCTRO register Set the A D converter clock more than 1 Table 6 3 2 shows the machine clock fosc and the A D converter clock TAD calculated as fsys fosc 4 Table 6 3 2 A D Conversion Clock and A D Conversion Cycle A D conversion cycle TAD ADCK conversion clock at fosc 4 MHz at fosc 8 MHz divided by 4 divided by 4 500 00 ns 0 fsys 1 00 us no usable 1 fsys 2 2 00 us 1 00 us For the system clock fsys refer to Chapter 2 2 4 Clock Switching Operation VI 9 Chapter 6 A D Converter a Sampling Time Ts of A D Converter Setup The sampling time of A D converter is set by the ADSH1 to 0 flag of the ADCTRO register The sampling time of A D converter depends on external circuit so set the right value by analog input impedance Table 6 3 3 Sampling Time of A D Conversion and A D Conversion Time Sampling time A D conversion time 15 at TAD 1 00 us at TAD 2 00 0 TAD x2 12 00 us 24 00 us 1 TAD
77. h the LSI may be damaged and proper operation is not assured They do not assure operation Electrical Characteristics I 13 Chapter 1 Overview 1 6 2 Operating Conditions 40 to 85 2 0 V to 5 5 V Vnsm 12 5 5 V 5 0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX Power supply voltage 1 105058 MHz divided by 4 30 55 No automatic reset 2 105654 MHz divided by 4 24 55 No automatic reset 3 Wane 105654 MHz divided by 8 20 S 55 Power supply voltage No automatic reset V lt 8 MHz divided by 4 4 lt 4 MHz divided by 4 VRSTL1 5 5 Automatic reset 5 fosc lt 4 MHz divided by 8 VRSTL1 _ 55 Automatic reset VRSTL2 1 Automatic reset circuit 2 cannot be selected in mask option Note 1 and is applied when automatic reset circuit is selected in mask option They are voltage to activate reset by detecting power supply voltage Automatic reset circuit 1 Power supply detection level VRSTH1 VRSTL1 3 20 3 70 V figure 1 6 1 Hysteresis width Vh 0 05 0 20 9 Power supply voltage 100 _ _ E change Automatic reset circuit 2 10 Power supply detection 5 220 240 Vnsn2 1 80 2 05 V figure 1 6 1 12 Hysteresis width Vh 0 05 0 15 2
78. icro controller may be wrongly operated After oscillation stabilization wait time is finished internal reset is released and program is started from the address x 0000 4 This LSI starts form NORMAL mode VDD NRST Internal reset Oscillation stabilization wait time Figure 2 6 1 Reset Released Sequence At internal reset P30 NSYNC key 0 pin outputs the system clock 50 When the auto reset circuit is selected in mask option the circuit that has enough time of L level pulse should be used II 20 Reset Chapter 3 Portts Chapter3 Ports 3 1 Overview 3 1 1 Port Diagram There are four ports port 0 port 1 port 2 and port 3 Each port is assigned to its corresponding special function register area in memory P20 ADO Porto lt lt gt ET qe Port 2 lt P22 AD2 P23 AD3 lt _ gt lt lt P10 PWMOO Port 1 P11 PWMO1 P30 NSYNC keyO P12 PWMO2 P31 NIRQ ACZ key1 Port 3 lt gt P13 PWMO3 P32 TCO BZ key2 Figure 3 1 1 Functions 2 Overview Chapter3 Ports 3 1 2 Port Functions Table 3 1 1 Port Functions Dual VO control Pull up resistor Output structure control Port WO function Function at reset Function at reset Function at reset EG E Each bit can be set Port 0 PO2 VO lindividually as either Input
79. igure 3 3 6 Block Diagram P32 16 Port2 3 Chapter 4 Interrupts Chapter 4 Interrupts 4 1 Overview 4 1 1 Functions This LSI has interrupt 1 IRQ 1 interrupt 2 IRQ 2 and interrupt 3 IRQ 3 Interrupt controller stops the executing program flow by the interrupt request and at that time push program counter PC and flag status FS to the stack and controls the execution starting of the inter rupt service routine depending on each interrupt factor JMP instruction at the starting address can specify the head address of the interrupt service routine Table 4 1 1 Interrupt Service Routine Starting Address Interrupt factor Vector address Priority High CPU reset RESET 000 Ig Interrupt 1 IRQ1 x00A Interrupt 2 IRQ2 x 00C Interrupt 3 IRQ3 x0OE Tr Interrupt is accepted by the interrupt controller if only both of the interrupt request flag IE and the interrupt enable flag IF are set Once an interrupt is accepted the interrupt service routine is executed But other interrupt enable flag is not masked If multiple interrupts are accepted at the same time the execution is done in order of priority decided in the hardware The highest priority is interrupt 1 IRQ1 then interrupt 2 IRQ2 then interrupt Table 4 1 2 shows the program example of interrupt enable disable Table 4 1 2 Program Example for Interrupt Setup setup enable disable interrupt IRQ1 EDI 0
80. ion on the head address of the interrupt service routine 3 to 4 machine cycles interrupt is disabled IV 6 Overview Chapter4 Interrupts Stack at interrupt Stack level at acceptance and at recover are changed as much as the program counter PC and the flag status FS are pushed or popped At normal interrupt PC and FS are pushed so that 4 nibble of the stack area RAM is needed There fore the value of SP is on the decrement for 4 at acceptance and on the increment for 4 at recover Recover operation is done by RETI instruction RETI instruction restore the contents of FS PC that are pushed onto the stack area RAM and the exclusive stack area on the acceptance cycle After the value of the stack area that SP indicates are read out SP is on the increment During interrupt service routine After recovery from interrupt Address Address 1 0 1 0 FB FA FB FA PCI FD FC FF FE FS PCh FF FE RAM area RAM area the address that SP indicates Figure 4 1 5 Operation of Stack Pointer Overview IV 7 Chapter 4 Interrupts Binterrupt Acceptance Start and Finish The interrupt acceptance is not available at the following timing 1 During interrupt is disabled 2 Atthe 1st cycle of 2 cycles instruction 3 1st 2nd cycle of 3 cycles instruction 4 When the interrupt factor is generated in e
81. itched individually by the P23SC register At reset the input mode is selected and pull up resistors are disabled high impedance output P20 ADO P21 AD1 P22 AD2 and P23 AD3 dual functions I 8 Pin Description Chapter 1 Overview Table 1 4 2 Pin Function Summary 2 3 Name Pin vO Dual Function Function Description NO P30 18 VO NSYNC VO pot 3 Parallel data VO port Schmitt Each bit can be set individually as either an input or P31 19 NIRQ output by the P23DIR register ACZ A pull up resistor for each bit can be selected key1 individually by the P23PLU register P32 20 TCO The output configuration is CMOS push pull or N ch BZ open drain Each bit can be set individually by the key2 P23SC register At reset the input mode is selected and pull up resistors are disabled high impedance output but P30 outputs system clock during the internal reset P30 NSYNC P31 NIRQ ACZ and P32 TCO BZ are dual functions These can be used as key interrupt input ADO 13 Input P20 Analog input pin Analog input pins for 4 channels AD1 14 P21 Set pin s direction to input by the P23DIR resister AD2 15 P22 When not used for analog input these pins can be used AD3 16 P23 as normal port NSYNC 18 Output P30 Systemclock At internal reset synchronous signal of system clock is synchronous output output At operation the initial status is port but NSYNC output port dat
82. l TM2CKO TM2MD x 04C tm3cmp 5 timer 3 04 Figure 5 1 1 Timer 2 Block Diagram V 4 Overview Chapter5 Timers i Timer 3 Block Diagram S2 internal clock 1 2 fosc gt D U fosc 26 _ gt X fosc 214 tm2cmp timer 2 Read Write 1 gt gt M compare register U timer 3 interrupt TM30C x 056 La X 7 thejmatch detection tm3cmp T I 8 bit counter 1 2 timer 3 output 4 JS U 046 TM3CK1 y X o Head M PE TM3MD tm2ff U x 04E timer 2 TM2PWM x 04C X syncrst 1 Figure 5 1 2 Timer 3 Block Diagram Overview 5 Chapter 5 Timers Eimer Output Block Diagram buzzer Buzzer output timer 2 Timer 2 output timer 3 Timer 3 output RMOS 06 i 06 gt M M gt 2 2 remote 8 4 control gt t circuit TCOS M 06 P32 port output data U 1 2305 P10 PWMOO 06 Seel M P10 port output data P11 PWMO1 U 4 11 06 0 D P11 port output data P12 PWMO2 PWMOSO
83. lation Connect the external capacitor suits the used pin When crystal oscillator or ceramic oscilla 1 tor is used frequency is changed depending on the condenser rate Therefore please L consult the manufacturer the external capacitors suits the used pin I 16 Electrical Characteristics Chapter 1 Overview Ta 40 to 85 Vpp 2 0 V to 5 5 V VnsrL12 5 5 V Vss 0 V Parameter Symbol Conditions Rating Unit External clock input OSC 1 OSC2 is unconnected 21 Clock frequency fosci 0 5 8 0 MHz 22 High level pulse width 56 figure 1 6 3 1 23 Low level pulse width twit 56 z ns 24 Rise time twrt 20 figure 1 6 3 25 Fall time twit 5 20 The clock duty cycle should be 45 to 55 96 twh1 twl1 gt lt gt gt P twr lt twf1 twc1 gt Figure 1 6 3 OSC1 Timing Chart External clock input Electrical Characteristics I 17 Chapter 1 Overview 1 6 3 DC Characteristics 40 to 85 2 2 0 V to 5 5 V VnsmL12 to 5 5 V Vss 0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX Power supply current 1 fosc 8 0 MHz divided by 8 1 1 5 0 V 15 3 0 Power supply current mA 2 i5 fosc 4 0 MHz divided by 8 z 12 25 Vpp 5 0 V Supply current during fosc 4 0 MHz divided by 8
84. lied to the circuit other than the auto reset circuit The supply current during STOP mode IpD4 005 are measured under the following conditions After reset is released and the oscillation is set to lt STOP modes the I O pin is fixed at the ACZ is fixed at 1 2 and the OSC1 is unconnected The supply current during STOP mode 056 007 are measured under the following conditions After reset is released and the oscillation is set to lt STOP modes the I O pin is fixed at and the OSC1 is unconnected Electrical Characteristics Chapter 1 Overview 40 to 85 2 0 V to 5 5 V VnsrL12 to 5 5 V Vss 0 V Rating Parameter Symbol Condition Unit MIN TYP MAX Input Schmitt input Pull up resistor built in 9 Input high voltage 0 8 Von 10 Input low voltage Vii Vss 0 15 Von 5 11 current li 50 140 200 VO to open drain output 12 Input high voltage 0 8 13 Input low voltage V2 Vss 0 2Vpp i 14 leakage current Vi 0 V to Von 50 01 ti 15 Output low voltage loL 15 mA Vpp 5 0 V Vss 0 4 1 0 V VO pin P10 PWMOO to P13 PWMOS 16 Input high voltage 0 8 Von 17 Input low voltage Vss 0 2 i 18 leakage current Vi 0 V to
85. ll up resistor OFF 1 Pull up resistor ON 1 1 When L outputs to pins pull up resistor is OFF on hardware Port 2 Port 3 Pull up Resistor Control Register P23PLU x 022 R W Figure 3 3 1 Port 2 Port 3 Registers 1 2 2 3 III 13 Chapter3 Ports 7 6 5 4 3 2 1 0 P23SC 2 1 25 3 25 2 25 1 25 0 at reset X0000000 P2SC Port 2 output structure control 0 CMOS output 1 N ch open drain P3SC Port 3 output structure control 0 CMOS output 1 N ch open drain Port 2 Port 3 Output Structure Control Register P23SC x 02A R W Figure 3 3 2 Port 2 Port 3 Registers 2 2 14 Port 2 3 Chapter 3 Ports 3 3 3 Block Diagram Pull up control 2 P2PLUO 3 p Va Port output data ma OH A e X P20 P23 Output structure control register 25 0 3 m Direction control register gt gt e gt P2DIRO 3 mE 777 7 7 Port input data C E 1 Input instruction ll Analog input data lt lt Figure 3 3 3 Block Diagram P20 P21 P22 P23 Port output data lt Pull up control C P3PLUO 7 NSYNC output gt lt em d Li piura O pD TT 222
86. n 1 Set the pin P23DIR x 012 bp5 PSDIRO 0 2 Select the interrupt source x 038 bp4 KEYOEN 1 IRQC1 x 036 bp1 0 IRQ3S1 0 00 bp2 IRQSSE 0 bp3 MASKIRS 1 3 Clear the interrupt request flag 032 bp7 1 4 Enable the interrupt 3 1 4 Set the P3DIRO flag of the port 2 port direction control register P23DIR to for P30 key 0 to set to input mode If necessary add pull up resistor t Chapter 3 Ports Set the KEYOEN flag of the key interrupt control register 1 KEYCNT to 1 to select the key interrupt key O as the interrupt source by the interrupt control register 1 IRQC1 register Set the IFIRQSE flag of the IRQ mode register IRQM to 1 to clear the interrupt 3 request flag Execute EDI instruction to enable interrupt 3 IV 14 Overview Chapter4 Interrupts 4 2 Control Registers 4 2 1 Registers List There are 4 registers to control interrupt operation the IRQ mode register IRQM the interrupt control register 0 IRQCO the interrupt control register 1 IRQC1 and the key interrupt control register 1 KEYONT Table 4 2 1 Interrupt Control Registers Register Address R W Function Page IRQM 032 W mode register IV 16 IRQCO 034 RAW Interrupt control register 0 IV 16 IRQC 1 x 036 R W Interrupt control register 1 IV 17 KEYONT 038 R W
87. n condition is not set it is executed the instruction of the address x 115 that is indicated in Memory Space II 11 Chapter 2 Basic CPU RAM Address Space 2 3 3 lower address 4 bit 25 25 2 E c lt en e ul gt Oe ost ot oo et D OO upper address 4 bit Figure 2 3 3 RAM Address Space Memory Space 12 2 3 4 Stack Area Chapter 2 Basic CPU Stack area is allocated from x CO to x FF in RAM area Stacked area is used for program counter flag status ZF CF accumulator E X Y registers to stack at CALL instruction PSH instruction and at interrupt When the whole area is not used as stacked area it can be used as a normal RAM If only CALL instruction is used the maximum 16 levels can be used Figure 2 3 4 shows the status of stack area when CALL PSH instructions and interrupt sequence are executed x F1 to x FO x F3 to x F2 X F5 to x F4 x F7 to x F6 x F9 to x F8 to x FA x FD to x FC X FF to x FE odd address even address 312111013 211 10 PCI CF ZF PCI CF ZF Figure 2 3 4 Status of Stacked Area ESP Stack Pointer shows at reset Also stacked data is used from x FF t
88. nched to the address that is indicated in 2 byte of instruction in the same page if condition is set At the border of page jump address is to the next page Address Machine code 000 015 1 6F jo OFF 18 PCh PC8 to PC11 100 2 is changed here 115 lt 3 1FF As shown the above example if JC instruction is located from x OFE to x OFF it is branched to the address that is indicated in 2 when condition is set And when condition is not set it is executed the instruction of the address x 115 that is indicated in Memory Space II 9 Chapter 2 Basic CPU 2 3 2 Address Space 4 x 0000 x 000A x 000C x 000E x 0010 x OFFF RESET program starts IRQ1 interrupt service program starts IRQ2 interrupt service program starts IRQ3 interrupt service program starts User peogram area Figure 2 3 2 ROM Address Space ROM address can be specified by program counter E register or accumulator 1 page for 256 byte It is divided by maximum 16 pages address in page ex JZ JNZ instruction Address that is directly specified in instruction code indicates the branched address in the same page II 10 Memory Space x 000 x 020 x 100 as ZF 1 x OFE JZ X 20 as ZFzO 2 Basic CPU address 1 ex JMP CALL instruction Address that is directly specifie
89. nterrupt 1 IRQ1 Interrupt 2 IRQ2 Interrupt 3 IRQ3 Hardware Functions I 3 Chapter 1 Overview I 4 Timers Counters A D converter Buzzer output PWM output 3 timers Timer 2 8 Bit timer for general use Timer pulse output PWM output Remote control carrier output Clock source fsys 2 fsys 8 fsys 32 fsys 128 fosc fosc 4 fosc 16 fosc 64 Timer 3 8 Bit timer for general use Timer pulse output High precision PWM output Remote control carrier output 16 Bit cascade connection function connected to timer 2 Clock source fsys 2 fosc fosc 25 fosc 2 Watchdog timer 10 bits X 4 channels Output frequency can be selected from fosc 1024 fosc 2048 fosc 4096 Remote control output Duty cycle of 1 2 or 1 3 ACZ input Mask option Port EPROM version Emulator Process Hardware Functions 1 set Automatic reset is available General UO ports 15 ports 11 ports can be used for other func tions Buzzer output 1 ports for timer output and key input too Timer output 1 ports for buzzer output and key input too NSYNC output 1 ports for key input too ACZ input 1 ports for NIRQ input and key input too NIRQ input 1 ports for ACZ input and key input too A D converter input 4 ports Key input 3 ports for NSYNC output NIRQ input ACZ input timer output and buzzer output too PWM output 4 ports MN15GP0402SJ PX ICE1500 PX PRB15G0402 CMOS 1 3
90. nterrupt input these pins can ACZ be used as normal port key2 20 P32 TCO BZ PWMOO 9 Output P10 PWM output PWM output pins PWMO 1 10 P11 Each bit can be set individually PWM output as either PWMO2 11 P12 an enable or disable by the BZCTR register PWMOS3 12 P13 When PWM output is enabled the conjunction of the timer output selected by the MODCNT register and the port output latch data is output I 10 Pin Description Chapter 1 Overview 1 5 Special Function Registers 1 5 1 Register Map This special function registers of this LSI are located as shown below Table 1 5 1 Register 01 2 3 4 5 6 7 8 9 A B C D E F PORTO PORT1 2 PORTS 1x POIDIR P23DIR 2x P23PLU 5 P23SC 3x IRQM IRQCO DOC ACZENT 4x TM3MD 5x 2 MODCNT 6x TCOCNT BZCTR WDCTR 7 ADBUFO ADBUF1 ADCTRO 82 9x Note Access to 000 to is by 4401 O instruction on each port 8 bit Access to X010 to is by only 8 bit Special Function Registers I 11 Chapter 1 Overview 1 5 2 Special Function Registers Address Register RAN Function Page x000 PORTO1 RAW Pont 0 port 1 data register Ill 9
91. o transition voltage It indicates how much difference between the nominal value and the analog input voltage when digital output code is changed from 0 to 1 x 000 gt 001 Full scale transition voltage It indicates how much difference between the nominal value and the analog input voltage when digital output code reached the full scale x 3FE gt x 3FF 1 22 Electrical Characteristics Chapter 1 Overview 1 7 External Dimensions Package code SOP020 P 0300D 12 63 0 20 Unit mm 1 10 40 20 5 50 0 20 10 0 40 10 0 SEATING PLANE SEATING PLANE SOP020 P 0300D is Pb free package Conventional package is 50 020 0300 1 The package dimension is subjected to change Before using this product please obtain product specifications from the sales office External Dimension I 23 Chapter 1 Overview 1 8 Option 1 8 1 Mask Option This LSI has the following mask option e Automatic reset circuit setup Select automatic reset circuit from among the automatic reset circuit 1 the automatic reset circuit 2 and unused I 24 Option Chapter 1 Overview 1 8 2 Mask Option Form VER 0 05 SE No Date Model name MN15G 02 Customer Approval 1 Power supply current and voltage voltage used not used at operation Vto V HALT mode Vto V STOP mode Vto V
92. o x CO in order RET instruction flags CF ZF not recovered Only RETI instruction is recovered Bl IFF memorizes that the last instruction is LI instruction It is used to pile up instructions Memory Space II 13 2 Basic CPU 2 4 2 4 1 This LSI can be switched the system clock division factor by instruction The CLKSEL1 flag of the CPU mode register CPUM switches the division factor of the system clock Figure 2 4 1 At fosc 4 0 MHz instruction cycle is 1 0 us at divided by 4 and 2 0 us at divided by 8 NORMAL mode means the mode that CPU is operated As shown on figure 2 4 1 at reset the CLKSEL1 is 0 NORMAL mode is se Clock Switching Clock Switching lected and operation is started from the reset cycle 14 release 1 HALT fosc oscillation CPU stop NORMAL fosc oscillation CPU operate STOP fosc stop CPU stop interrupt interrupt 1 1 fosc oscillation stabilization waiting time is needed on hardware Figure 2 4 1 CPU Operation Mode and Setup Clock Switching 2 Basic CPU 2 4 2 Mode Register This is readable writable register that switches the division rate of the system clock 7 6 5 4 3 2 1 0 CPUM 2 CLKSEL1 at reset CLKSEL1 Division for system clock 0 divided by 8 1 divided by 4
93. of AC zero cross detection circuit AC zero cross detection circuit outputs the high level when the input level is at the middle and outputs the low level at other level The ACZ pin is connected to P31 input circuit too So It can be read out by program The ACZ input circuit is connected to the input clamp diode The ACZ interrupt is generated at the rising or falling edge of the AC zero cross detection output When the ACZ interrupt is used select ACZ as an interrupt source by the interrupt control register 1 IRQC1 and specify the edge and enable the interrupt 3 IRQ3 by the EDI instruction input voltage level 1 ACZ input input voltage level 2 AC zero cross detection circuit output Figure 7 1 1 A C Zero Cross Detection Circuit Timing Chart VII 2 Overview 7 1 2 Block Diagram Be A 1 2 0 gt A 777 AC zero cross detection circuit 9 gt Chapter 7 AC Zero Cross Detection ACZ interrupt gt port input data 211 Figure 7 1 2 Zero Cross Detection Circuit Block Diagram Overview VII 3 Chapter 7 Zero Cross Detection 7 1 3 Operation Setup procedure and its description are as follows BACZ 1 Set the pin s direction Set the P3DIR1 flag of the port 3 direction control register P23DIR to 0 to set P31 to input mode 2 Switch the P31 input data Select the
94. ormation required for your design purchasing and applications If you have any inquiries or questions about this book or our semiconductors please contact one of our sales offices listed at the back of this book About This Manual In this LSI manual this LSI functions are presented in the following order overview basic CPU functions interrupt functions port functions timer functions serial functions and other peripheral hardware functions Each section contains overview of function block diagram control register operation and setting example mManual Configuration Each section of this manual consists of a title summary main text key information precautions and warnings and references The layout and definition of each section are shown below Subtitle Sub subtitle smallest block in this manual Main text Key information Important information from the text About This Manual 1 Chapter2 Basic CPU 2 8 Reset Summary 2 8 1 Reset operation The CPU contents are reset and registers initialized when the NRST 27 is pulled to low W Initiating a Reset There are two methods to initiate a reset 1 Drive the NRST pin low for at least four clock cycles NRST pin should be holded low for more than 4 clock cycles 200 nS at a 20 MHz NRST pin i 4 clock cycles 200 nS a
95. ough current is happened till the setup complete Overview 5 Chapter3 Ports 3 1 5 Setup Example iSetup example A setup example of input output port by port 2 port 3 Port 3 is input port Port 2 in output port Pull up resistor is added to port 3 not to port 2 An example setup procedure with description of each step is shown below Setup Procedure Description 1 2 Control the 1 direction of port P23DIR x 012 bp6 4 PSDIR2 0 000 bp3 0 201 3 0 1111 Add pull up resistor P23PLU x 022 bp6 4 PSPLU2 0 111 bp3 0 P2PLU3 0 0000 1 Set the P3DIR2 0 flag of theP23DIR register to 000 to set port 3 to input port Set the P2DIR3 0 flag to 1111 to set port 2 to output port Set the P3PLU2 0 flag of theP23PLU register to 111 to add pull up resistor to port 3 Set the P2PLU3 0 flag to 0000 not to add pull up resistor to port 2 Port 2 outputs data when lower 4 bits of port 2 port 3 data register PORT23 are written and OUT instruction is executed The status of port 3 can be input when upper 4 bits of port 2 port 3 data register PORT23 are read and IN instruction is executed III 6 Overview 3 1 6 Control Registers Chapter 3 Ports I O port control register includes a data register PORTn that outputs data a direction control register PnDIR that controls I O direction a pull up resistor control register PnPLU that controls pull up resis
96. ple setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter 1 Set the TM2EN flag of the timer 2 mode TM2MD 704 register TM2MD to 0 to stop timer 2 bp3 2 0 counting 2 Setthe special function pin to output 2 Setthe TCOE flag of the timer 2 output TCOCNT x 06A control register TCOCNT to 1 to set P32 pin bp1 2305 0 as a special function pin Set the timer 2 as bp2 TCOS 1 output source by the TC23OS flag the RMOS bp3 RMOS 0 flag and the TCOS flag bp7 TCOE 1 Set the P3DIR2 flag of the port 2 port 3 direction control register P23DIR to 1 to set P23DIR x 012 output mode bp6 PSDIR2 1 If it needs pull up resister should be added Chapter 3 Ports 3 Select the normal timer operation 3 Setthe TM2PWM flag of the TM2MD register TM2MD 04 to 0 to select the normal timer operation bp4 TM2PWM 0 4 Select the count clock source 4 Select fosc as clock source by the TM2CK2 0 TM2MD 04 flag of the TM2MD register bp2 0 20 2 0 100 5 Setthe timer pulse output cycle 5 Setthe 1 2 of the timer pulse output cycle to 2 x 054 27 the timer 2 compare register TM2OC The value is set to be 40 1 39 27 to be 100 kHz by dividing 4 MHz At that time the timer 2 binary counter TM2BO is cleared to x 00 6 Start the timer 6 Setthe TM2EN flag of the T
97. pt input is used enable key interrupt by the key interrupt control register 1 Set pin to input mode by the port 2 3 direction control register P23DIR and add pull up resistor if necessary 12 Port 2 3 Chapter3 Ports 3 3 2 Registers 7 6 5 4 3 2 1 0 P30DATA P23DATA P22DATA P21DATA P20DATA at reset 1111111 PORT23 5 P32DATA P31DATA P2DATA Output data 0 Low Vss level is output 1 High level is output P3DATA Output data 0 Low Vss level is output 1 High Von level is output At reading pin s status is read Port 2 Port 3 Data Register PORT23 x 002 R W 7 6 5 4 3 2 1 0 P23DIR P3DIR2 P3DIR1 P3DIRO P2DIR3 P2DIR2 P2DIR1 P2DIRO at reset X0000000 P2DIR Port 2 direction control 0 Input mode output Hiz 1 Output mode 1 P3DIR Port 3 direction control 0 Input mode output Hiz 1 Output mode 1 1 It becomes special port output when the pin function is switched Port 2 Port 3 Direction Control Register P23DIR x 012 R W 7 6 5 4 3 2 1 0 P23PLU P3PLU2 P3PLU1 P3PLUO P2PLU3 P2PLU2 P2PLU1 P2PLUO at reset X0000000 P2PLU Port 2 pull up control 0 Pull up resistor OFF 1 Pull up resistor ON 1 P3PLU Port 3 pull up control 0 Pu
98. pter 1 Overview 1 3 2 NRST lt lt EE E I 6 B Block Diagram Oscillation stabilization wait time Watchdog timer Automatic reset CPU MN150G 2 4 128 nibble H D V U UU mU 0 55 Di D D D zB S zx lt OSC2 OSC Clock generator A D converter il Timer 2 3 8 bit x 2 Buzzer output External interrupt Port 3 0 LOv Led cav eed QV eed O eX ONASN O d LAeWZOV OMUIN LEd eKexzg oo L ced Figure 1 3 1 Block Function Diagram lock Diagram Chapter 1 Overview 1 4 Pin Description 1 4 1 Pin Configuration VDD 20 P32 TCO BZ key2 5 1 19 lt P31 NIRQ ACZ key1 OSC2 18 P30 NSYNC keyO VSS 17 NRST 16 9 P23 AD3 1 15 P22 AD2 P02 14 lt P21 AD1 13 lt gt P20 ADO P10 PWMOO 9 12 lt P13 PWMO3 P11 PWMO1 lt gt 10 11 lt P12 PWMO2 Figure 1 4 1 Pin Configuration 20SOP Top view Pin Description I 7 Chapter 1 Overview 1 4 2 Pin Functions Table 1 4 1 Pin Function Summary 1 3 Name Pin VO Dual Function Function Description No Vss 4 Power supply pin Apply 2 0 V to 5 5 V to and 0 V to Vss VDD 1 OSC1 2 Input Clock input pin Comnect these oscillation pins to oscillators for clock OSC2 3 Output Clock output pin operation Fee
99. put Input PS31 NIRQ ACZ key1 as input 33 high voltage VpHH Vpp 0 5 34 Input low voltage Ve 4 5 V to 5 5 V Vss 1 5 35 Input high voltage figure 1 6 4 15 Von 36 low voltage Vo Vss 0 5 37 Inputleakage current 0 V to 0 01 1 38 Input clamp current ie Vi 0 V 500 39 Rise time trs 30 figure 1 6 4 US 40 Fall time tis 30 1 20 Electrical Characteristics Chapter 1 Overview Figure 1 6 4 Zero cross Detection Circuit Operation Electrical Characteristics I 21 Chapter 1 Overview 1 6 4 A D Converter Characteristics 40 to 85 2 0 V to 5 5 V Vnsr 12 to 5 5 V Vss 0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX 1 Resolution 10 Bits 2 Non linearity error 5 0 V Vss 0 0 V 3 LSB fosc 8 MHz divided by 8 3 Differential non linearity 0 _ 3 LSB error 4 Zero transition voltage Vop 5 0 V 10 30 mV 5 Fukscaewansiionvotage Vest KSE 4950 4980 mV 6 A D conversion time fosc 8 MHz divided by 8 12 0 28 0 US 7 Sampling time Ts Tan 1 0 us 2 0 18 0 us 8 Analog input voltage Via Vss 5 V Analog input leakage When channel OFF S current 0 V to SE 1 Hs 10 Ladder resistance 10 30 100 Zer
100. r 3 Timer 2 and timer 3 are combining to be a 16 bit timer Cascading timer is operated at clock source of timer 2 which are lower 8 bits Table 5 6 1 Timer Functions at Cascade Connection timer 2 timer 3 16 bit interrupt factor interrupt 3 IRQ3 timer operation output P10 P13 high precision PWM 4 output fsys 2 fsys 8 fsys 32 fsys 128 clcok source fosc fosc 4 fosc 16 fosc 64 fosc machine clock oscillation for operation fsys system clock At cascade connection the binary counter and the compare register are operated as a 16 bit regis ter At operation set the TMnEN flag of the mode register for both of the upper 8 bit timer timer 3 and lower 8 bit timer timer 2 to 1 to be operated Also select the clock source by the lower 8 bit timer Other setup and count timing is the same to the 8 bit timer at independently operation When timer 2 and timer 3 are used in cascade connection an interrupt request flag is used with timer 3 Timer pulse output of timer 2 is H fixed output 8 Bit Timer Cascade Connection 25 Chapter 5 Timers 5 6 2 Setup Example iCascade Connection Timer Setup Example Timer 2 Timer 3 Setting example of timer function that an interrupt is constantly generated by cascade connection of timer 2 and timer 3 as a 16 bit timer is shown below An interrupt is generated every 1 2500 cycles by selecting fsys
101. r A amp A M X Y le 1 1 14 81 5 00 da or direct A lt A M da 2 2 1C da 81 e exclusive or amp M X Y 1 1 15 82 XD da exclusive or direct AA amp M da e 2 2 1D da 82 a ROL rotate left i 3210 1 1 08 85 8 lt A 8 rotate right 3210 1 1 09 SLEA shift left byte 3210 3210 1 2 58 lt lt lt 0 84 52852 resetbit memory direct 0 2 2 3 8 bp da 85 58 S SBMD Set bit memory direct M da bp lt 1 0 2 2 3 C bp da 85 JMP hml jump PChe h PCmem PCI I 2 2 Ah ml 86 JMPL uhml jump long PCucu lt PCI I 3 3 06 00 11 88 JMPEA jump by EA PCI A 1 1 36 89 CALL hml call SP lt SP 4 M SP lt PC 2 CF ZF LIFF 1 2 2 9h ml PChh PCmm PCII i CALLL uhml call long SPSP 4 M SP PC 2 CF ZF LIFF 1 3 3 O0A uh ml PCuu PChh POmm PCII 33 CALS s call short SPSP 4 M SP PC 2 CF ZF LIFF 2 8688 lt 0 8 5 0 RET return SP lt SP 4 E 1 2 34 RETI return from interrupt 2 SP SP44 1 2 35 JZ ml jump if zero if ZF 1 POmem PCI I 2 2 6E ml 100 w if ZF 0 PC PC 2 B JNZ ml jump if nonzero if ZF 0 PCII 2 2 6A ml 100 8 if ZF 1 lt 2 8 JC ml jump if carry if CF 1 PCII 2 2 6F ml 101 S if CF 0 lt 2
102. ransaction should be operated BAntinoise transaction For A D input analog input pin add condenser near the VSS pins of micro controller VDD Vss Power supply Set near the Vss pin Figure 6 3 2 Converter Recommended Example For high precision of A D conversion the following cautions on A D converter should be kept 1 1 The input impedance of A D input should be under 500 kO and the external capacitor C more than 1000 pF under 1 7 2 The A D conversion frequency should be set with consideration of R C 3 Atthe A D conversion if the output level of micro controller is changed or the peripheral added circuit is switched to ON OFF the A D conversion may work wrongly because the analog input pins and power pins do not fix At the check of the setup confirm the waveform of analog input pins 4 Start the A D conversion after A D ladder resistance is connected and about 1 ms is taken Equivalent circuit block that outputs analog signal microcontroller R AAN i A D input pin S ILE 777 77 E e Vss 1 mF2 gt 1000 pF lt 500 kW 1 That value is for reference A D Converter Recommended Example VI 12 Operation Chapter Zero Cross Detection Chapter 7 Zero Cross Detection 7 1 Overview 7 1 1 Overview This LSI has a set of AC zero cross detection circuit The ACZ pin is the input pin
103. ration mode high unstable generalport status of 1 NRST on Unstable 1 unstable Figure 9 1 1 Automatic Reset Voltage IX 2 Overview Chapter 9 Automatic Reset 9 1 2 Electrical Characteristics 40 to 85 Vpp 2 0 V to 5 5 V VnsrL12 5 5 V Vss 0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX Power supply voltage 1 Vbp4 1 fosc lt 8 MHz divided by 4 2 55 Automatic reset Power supply voltage V fosc x 4 MHz divided by 8 VRSTL1 2 Vops 5 5 Automatic reset VRSTL2 1 Automatic reset 2 can not be selected in mask option Automatic reset circuit 1 3 Power supply detection 39 4 40 4 evel Vastu 3 20 3 70 figure 9 1 1 V 5 width Vh 0 05 0 20 6 Power supply voltage At AV 1 00 Change Automatic Reset circuit 2 7 Power supply detection Vasi 5 2 20 2 40 a level Vnsn2 180 205 V figure 9 1 1 9 Hysteresis width Vh 0 05 0 15 5 10 Power supply voltage At 1 00 ms V change Power supply current T Automatic reset current libi Vop 5 0 V 4 8 uA consumption 2 2 indicates the consumption normally spent in automatic reset circuit So if automatic reset is selected each rating is added Overview IX 3 Chapter 10 Appendices
104. re 1 18 deleted Tables relevant to deletion in the specification are changed MN15G0202 0402 151 User s Manual Record of Changes First Edition to Second Edition 2 3 Details of Changes Page Definition Previous Edition First Edition New Edition Second Edition 1 19 Delete Chapter 1 6 3 DC Characteristics Specifications and warnings on low oscillation and RC oscillation are deleted Tables relevanat to deletion in the specifica tion are changed Addition During STOP mode The supply current 1004 IDD5 and IDD6 are applied to the circuit other than the auto reset circuit 1 24 Change Chapter 1 7 External Dimensions Package code SOP020 P 0300 Package code SOP020 P 0300D Addition Warnings 25 Delete Chapter 1 8 1 Mask Option 1 Oscillation circuit setup Change Chapter 1 8 2 Option Check List Ver 0 04 Chapter 1 8 2 Option Check List Ver 0 05 1 26 Delete 3 Automatic reset circuit 2 OSC oscillation circuit is deleted VrstLz cannot be selected at RC oscillation and at tc the instruction execution time 2 Underlined part is deleted us Chapter 2 1 1 Clock Generator 1 2 Delete mios OSC oscillation can be selected from high speed low speed RC by mask option When Underlined part is deleted high speed oscillation or low speed oscillation is selected these circuits require extern
105. register to 1 to select the PWM operation Set the TM3CAS flag of the TM3MD register to 1 to connect timer 2 and timer 3 in cascade connection Set the P1DIRO flag of the port 0 port 1 direction control register PO1DIR to 1 to set P10 for output mode Set the P10DATA flag of the port 0 port 1 data register PORTO1 to 1 to output Enable the PWM output to port 10 by the PWME 10 flag of the BZCTR register and select the timer 2 output by the PWMOSO flag of the MODONT register Set fosc as clock source by the TM2CK2 0 flag of the TM2MD register Set 55 to the timer 2 compare register 2 to set the PWM duty 32 High Precision PWM Output Chapter5 Timers Setup Procedure Description 7 Setthe PWM cycle 7 SetxAA to the timer 3 compare register 056 to set the PWM cycle 8 Start the timer 3 operation 8 Setthe flag of the TM3MD register to TM3MD 04 1 to start the timer 3 bp3 1 9 Start the timer 2 operation 9 Setthe TM2EN flag of the TM2MD register to TM2MD 04 1 to start the timer 2 bp3 2 1 High Precision PWM Output V 33 Chapter 5 Timers 5 9 Buzzer Output 5 9 1 Operation Clock that the source oscillation fosc is divided by 1024 2048 4096 can be output to pin mBuzzer Output Operation Buzzer output frequency is selected by the BZCK1 0 flag of the b
106. register bes 50 Direction control register PO1DIR DHE E 213 777 Port input data 10 Por 0 1 Input instruction Figure 3 2 4 Block Diagram P10 P11 P12 P13 Chapter3 Ports 3 3 Port 2 3 3 3 1 Description ilGeneral Port Setup Each bit can be set individually as either an input or output by the port 2 port direction control register P23DIR The control flag of the port 2 port 3 direction control register P23DIR is set to 1 for output mode and for input mode To read input data of pin set the control flag of the direction control register P23DIR to 0 or set the output configuration to N ch open drain by the output structure control register P23SC and set the port 2 port 3 data register PORT23 to 1 to select Hi z output then read the value of the port 2 port 3 data register PORT23 Y To read input data the pin s status should be read not the value of the PORT23 register m To output data to pin set the control flag of the direction control register P23DIR to 1 and write the value of the port 2 port 3 data register PORT23 Each bit can be set individually if pull up resistor is added or not by the pull up resistor control register P23PLU Set the control flag of the pull up resistor control register P23PLU to 1 to add pull up resistor
107. rol P3DIR2 P3DIR1 P3DIRO P2DIR3 P2DIR2 P2DIR1 P2DIRO 012 P23DIR lll 13 Port 3 Direction Control Port 2 Direction Control P3PLU2 P3PLU1 P3PLUO P2PLUS P2PLU2 P2PLU1 P2PLUO x022 P23PLU lll 13 Port 3 Pull up Control Port 2 Pull up Control P1SC3 P1SC2 P1SC1 1 0 028 015 lll 9 Port 1 Output Structure Control P3SC2 P3SC1 P3SCO P2SC3 25 2 P2SC1 25 0 02 P23SC 14 Port 3 Output Structure Control Port 2 Output Structure Control CLKSEL1 x 030 CPUM System clock ll 15 division Switching IFIRQ3E IFIRQ2E IFIRQ1E X032 IRQM Clear Clear DOS Clear IRQ1 M 16 flag flag flag MASKIR1 IRQ1SEO reserved reserved x 034 IRQCO IRQ1 interrupt road FM mx IV 16 edge mask switching MASKIR3 IRQ3SE IRQ3S1 IRQ3SO X 036 IRQC1 IRQ3 interrupt IV 17 interrupt edge interrupt source mask Switching 2 KEEN KEYOEN 038 Enable Key interrupt 17 0 to key2 NSYNCS ACZAIN reserved XO3A ACZONT P30 output P31 input VIL 5 data data Set to switching switching TM2BC7 TM2BC6 TM2BC5 TM2BC4 TM2BC3 2 2 TM2BC1 2 044 TM2BC V 10 Timer 2 binary counter TM3BC7 TM3BC6 TM3BC5 TM3BC4 TM3BC3 TM3BC2 046 TM3BC V 10 Timer 3 binary counter TM2PWM TM2EN 2 2 TM2CK1 TM2CKO X04C TM2ND Timer 2 PWM Timer 2 count T 11 Selection enable imer 2 count clock TM3CAS TM3EN TM3CK2 TM3CK1
108. row Ac A M X Y CF eje 1 13 72 2 SBD da subtract direct with borrow lt e e 2 2 1 72 2 A M X Y FS ejo 1 1 73 3 CD da compare direct A M da FS e e 2 2 004 73 mn compare byte immediate EA mn FS e 9 2 2 74 5 compare immediate A n FS e o 1 1 74 ICM increment memory lt 1 e o 1 6 75 ICMD da increment memory direct M da lt M da 1 e 2 2 leide 75 Note Page refers to the corresponding page in the Instruction Manual But marked instruction should be refered to chapter 10 4 Instruction Set X 7 Chapter 10 Appendices NSTRUCTON Mnemonic Operation ats ae Cycle Machine Code Page lt 1 WO 1 20 76 5 increment byte lt 1 1 1112 5 76 DCM decrement memory M X Y lt M X Y 1 1 1 64 77 2 DCMD decrement memory direct M da lt M da 1 e 2 2 65 77 DCY decrement Y Yey 1 1 1 24 78 8 DCEA decrement byte lt 1 1 2 78 a complement 1911 1 02 79 AA amp M X Y 1 1 16 80 ND and direct amp M da 2 2 1 80 o
109. rupt service routine should be used with JMP instruction at the starting address of the pro gram if necessary main program 10 main program 11 main program 12 main program 13 main program 14 main program 15 7 the start of the interrupt service routine 1 interrupt program 1 taco KE Figure 4 1 3 interrupt program 2 2 the end of the routine Chapter4 Interrupts The starting address of the interrupt service routine is set to PC here Also PC and FS of main program is pushed to the stack PC and FS of the stacked area are popped Interrupt Operation 5 Overview Chapter 4 Interrupts ex IRQ2 absolute address LABEL PSHXY x 000C JMP LABEL were PSHEA interrupt service routine POPEA POPXY EDI 0 2 RETI Figure 4 1 4 Interrupt Sequence Example Winterrupt return operation RETI instruction Return from Interrupt is used on return operation to the former program This instruc tion is similar to the RET instruction RET that is used on return operation from subroutine RETI instruction return the contents of the program counter PC and the flag status FS that are pushed onto the stack area RAM Then the program is returned to the status before the interrupt is generated For interrupt response speed it takes 4 cycles after the interrupt factor is generated till the interrupt is accepted If there is EDI instruct
110. rwise it is reset ZF Zero Flag The zero flag is set when ALU operation results is zero Otherwise it is reset LIFF Load Immediate Flag This memorizes that the last instruction is instruction It is used to Instruction LIFF Description NOP 0 no execution LI 5 0 Set 5 to accumulator LI 8 1 no execution LI 9 1 no execution OUT 0 X F 0 Output 5 to port 0 ilStack Pointer SP This is a 8 bit register that indicates address of stack area in data RAM Stack area is used for PC to stack at subroutine call and at interrupt 7 6 0 111 0 always 1 always 0 iSpecial Buffer SB This register can input output data by 8 bits by RDSB WTSB instruction between E register and A register mTemporary Buffer SB This register can input output data by 8 bits by RDBC WTTB instruction between E register and A register Register Set 7 Chapter 2 Basic CPU 2 3 Memory Space This LSI has independently an instruction memory area ROM that stores instructions and a data memory area RAM include stack area that stores data ROM can be used as a memory for stable data such as table data 2 3 1 ROM Address Space 2 KB x 0000 RESET program starts x 000A IRQ1 interrupt service program starts x 000C 2 interrupt service program starts 000 IRQ3 interrupt service program starts x 0010 User program area x 07FF Figure 2 3 1 Address Space ROM a
111. sistor Set the TM2PWM flag of the TM2MD register to 1 to select the PWM operation Select tosc 64 as clock source by the 2 2 0 flag of the TM2MD register 8 Bit PWM Output V 23 Chapter 5 Timers Setup Procedure Description b Setthe period of PWM H output b Setthe H period of PWM output to the timer 2 054 x 40 2 compare register TM2OC The setting value is set to 256 4 64 40 because it should be the 1 4 duty of the full count 256 At that time the timer 2 binary counter TM2BC is initialized to 00 6 Start the timer operation 6 Set the TM2EN flag of the TM2MD register to TM2MD 04 1 to operate timer 2 bp3 2 1 TM2BC counts up from x 00 PWM source waveform outputs till TM2BC reaches the setting value of the TM2OC register and outputs L after that Then TM2BC continues counting up and PWM source waveform outputs H again once overflow is happened and TM2BC restarts counting up from x 00 TCO outputs the PWM source waveform with 1 count clock delay The initial setting of PWM output is changed from L output to H output at the selection of PWM operation by the TM2PWM flag of the TM2MD register 24 8 Bit PWM Output Chapter5 Timers 5 6 8 Bit Timer Cascade Connection 5 6 1 Operation Cascading timers 2 and 3 forms a 16 bit timer 8 Bit Timer Cascade Connection Operation Timer 2 Time
112. sk ROM version and EPROM version Mask option Oscillation circuit MN15G0202 0402 LSI User s Manual July 2001 2nd Edition Issued by Matsushita Electric Industrial Co Ltd Matsushita Electric Industrial Co Ltd Semiconductor Company Matsushita Electric Industrial Co Ltd Nagaokakyo Kyoto 617 8520 Japan Tel 075 951 8151 http www panasonic co jp semicon SALES OFFICES U S A SALES OFFICE Panasonic Industrial Company PIC New Jersey Office 2 Panasonic Way Secaucus New Jersey 07094 Tel 201 392 6173 Fax 201 392 4652 Milpitas Office 1600 McCandless Drive Milpitas California 95035 Tel 408 945 5630 Fax 408 946 9063 Chicago Office 1707 Randall Road Elgin Illinois 60123 7847 Tel 847 468 5829 Fax 847 468 5725 Atlanta Office 1225 Northbrook Parkway Suite 1 151 Suwanee Georgia 30174 Tel 770 338 6940 Fax 770 338 6849 San Diego Office 9444 Balboa Avenue Suite 185 San Diego California 92123 Tel 619 503 2940 Fax 619 715 5545 CANADA SALES OFFICE Panasonic Canada Inc PCI 5700 Ambler Drive Mississauga Ontario LAW 2T3 Tel 905 624 5010 Fax 905 624 9880 GERMANY SALES OFFICE Panasonic Industrial Europe G m b H PIEG Munich Office Hans Pinsel Strasse 2 85540 Haar Tel 89 46159 156 Fax 89 46159 195 U K SALES OFFICE Panasonic Industrial Europe Ltd PIEL Electric component Group Willoughby Road Bracknell Berkshire R
113. t select the base timer output by the timer output control register x 06A and set the remote control output by the RMOS flag base cycle of timer base cycle of timer timer output P32 TCO 1 2 duty P32 TCO 1 3 duty Figure 5 7 1 Duty cycle of Remote Control Carrier Output Signal iCount Timing of Remote Control Carrier Output Timer 2 Timer 3 base cycle of timer timer output output ON RMOEN output OFF P32 TCO 1 3 duty A Figure 5 7 2 Count Timing of Remote Control Carrier Output Function Timer 2 Timer 3 A Even if the RMOEN flag is off when the carrier output is high the carrier waveform is held by the synchronous circuit 4 When the RMOEN flag is changed do not change the base cycle and its duty at the same time If they are changed at the same time the carrier waveform is not output properly Y Buzzer output cannot be set as the base cycle of remote control 28 Remote Control Career Output 5 7 2 Setup Example Chapter 5 Timers Remote Control Carrier Output Setup Example Timer 2 Timer 3 Here is the setting example that the TCO pin outputs the 1 3 duty carrier pulse signal with H period of 36 7 kHz by using timer 2 The source clock of timer 2 is set as fosc 8 MHz An example setup procedure with a description of each step is shown below base cycle of timer 2 TCO output 1 3 duty base cycle of timer 2 36 7 kHz lt
114. t 0 port 1 data register PORTO 1 Y To read input data the pin s status should be read not the value of the PORTO register m To output data to pin set the control flag of the direction control register PO1DIR to 1 and write the value of the port 0 port 1 data register 1 Each bit can be set individually the output configuration by the port 1 output structure control register 01 Set the control flag of the port 1 output structure control register 150 to 1 for N ch open drain and to 0 for CMOS output Y The output structure of port 0 is N ch open drain When the port 0 1 register is written to 1 it becomes high impedance output ilSpecial Function Pin Setup P10 to P13 are used as PWM output pin General port at reset Each bit can be set individually if the PWM output is enabled or not by the buzzer output control register BZCTR When it is enabled the conjunction of the port 1 output data and the timer output that the timer control input control register MODCNT selects is output to pin 8 0 1 Chapter 3 3 2 2 Registers 7 6 5 4 3 2 1 0 PORTO1 P13DATA P12DATA P11DATA P10DATA 2 1 at reset 11111111 Ports PODATA Port 0 output data 0 Low Vss level is output 1 Hiz is output 1 1 The output configuration is N ch open drain
115. t a 20 MHz Figure 2 8 1 Minimum Reset Pulse Width 2 Setting the 2 7 flag of the 2 register to 0 outputs low level at P27 NRST pin And transfering to reset by program software reset can be executed If the internal LSI is reset and register is initiated the P2OUT7 flag becomes 1 and reset is released Introduction to the section References Chapter 4 4 4 2 Registers On this LSI the starting mode is NORMAL mode that high oscillation is the base clock References for the main text Precautions and warnings Y enough low level time at sudeen unconnected And reset can be generated even if its pulse When the power voltage low circuit is connected to NRST pin circuit that gives pulse for P is low level as the oscillation clock is under 4 clocks take notice of noise 44 Reset Precautions are listed in case Be sure to read these of lost functionality or damage Desired Information This manual provides three methods for finding desired information quickly and easily 1 Consult the index at the front of the manual to locate the beginning of each section 2 Consult the table of contents at the front of the manual to locate desired titles 3 Chapter names are located at the top outer corner of each page and section titles are located at the bottom outer corner of each page iRelated Manuals Note that the following related documents ar
116. ter is cleared to 00 if any data is written to this counter during counting is stopped 2 Binary Counter TM2BC 7 6 5 4 3 2 1 0 TM2BC TM2BC7 TM2BC6 TM2BC5 TM2BC4 2 03 TM2BC2 TM2BC1 TM2BC0 atreset X X X X XXXX Timer 2 Binary Counter TM2BC x 044 R 3 Binary Counter TM3BC 7 6 5 4 3 2 1 0 TM3BC TM3BC7 TM3BC6 5 TM3BC4 TM3BC3 TM3BC2 TM3BC1 TM3BC0 at reset X X X XXXXX Timer 3 Binary Counter TM3BC x 046 R Figure 5 2 2 Binary Counter 10 8 Bit Timer Control Registers 5 2 4 2 Mode Register TM2MD TM2MD Timer Control Registers 6 5 4 3 2 1 0 2 2 TM2CK2 TM2CK1 TM2CKO Chapter 5 Timers at reset XXX00000 OL TM2CK2 TM2CK1 TM2CK timer 2 count clock 0 fsys 2 0 1 fsys 8 0 0 fsys 32 1 1 fsys 128 0 fosc 0 1 fosc 4 0 fosc 16 1 1 fosc 64 TM2EN tiemr 2 count enable 0 disable timer 1 enable timer TM2PWM timer 2 PWM function 0 timer pulse output 1 PWM output Figure 5 2 3 Timer 2 Mode Register TM2MD x 04C R W 8 Bit Timer Control Registers 11 Chapter 5 Timers 3 Mode Register TM3MD 7 6 5 4 3 2 1 0 TM3MD TM3CAS
117. the next count clock then the binary counter is cleared to x 00 and the counting is restarted Even if the compare register is rewritten during the TMnEN flag is enabled 1 the binary counter is not changed If the TMnEN flag is stopped 0 the binary counter is stopped If the binary counter reaches the value of the compare register the interrupt request flag is set at the next count clock then the binary counter is cleared So set as follows the setting value of the compare register the count till the interrupt request is generated 1 If the compare register is set the smaller than the binary counter during the count operation the binary counter counts up till the overflow If the interrupt is used the timer interrupt request flag should be cleared before timer is started The timer n interrupt request generation at TMnOC 00 has the same waveform at TMnOC 01 16 8 Timer Operation Chapter5 Timers 5 3 2 Setup Example Timer Operation Setup Example Timer 2 Timer 3 Timer 2 can generate the constant interrupt Interrupt is generated in every 250 counts by selecting fsys 8 as a clock source An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM2MD 04 bp3 2 20 Select the normal timer operation TM2MD 04 bp4 TM
118. uld be based on analog input impedance Set the A D ladder resistance Set the ADLADE flag of the A D converter control register ADCTRO to 1 and through current to the ladder resistance for A D conversion Y 2 to 5 are not in order can be operated simultaneously Start the A D conversion Set the ADST flag of the A D control register ADCTRO to 1 to start the A D conversion A D conversion After sampling with the sample and hold time set in 4 A D conversion is decided in comparison with MSB in order Complete the A D conversion When A D conversion is finished the ADST flag is cleared to 0 and the result of the conversion is stored to the A D buffer ADBUFO 1 Operation VI 7 Chapter 6 A D Converter ADST i Y A D conversion start 1 1 A D conversion complete gt lt 1 sampling hold bit 9 bit 8 bit 0 comparisoncompariso compariso B 48 p 2 ch gt determine determine determine determine bit 9 bit 8 bit 1 bit 0 1 1 gt Figure 6 3 1 Timing of A D Conversion Ts TAD x 2 To read out the value of the A D conversion A D conversion should be done several times to prevent noise by confirming the match of the level by program or by using the average value VI 8 Op
119. unt Timing of High Precision PWM Output Y The set value in the timer 3 compare register should be bigger than the one in the timer 2 compare register TM2OC High Precision PWM Output 31 Chapter 5 Timers 5 8 2 Setup Example mHigh Precision PWM Output Setup Example Timer 2 Timer 3 High precision PWM output waveform is output to P10 pin by cascading timer 2 and timer 3 Then fosc is selected as clock source and each data is set to both of the timer 2 compare register 200 and the timer 3 compare register TM3OC An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM2MD 04 bp3 TM2EN 0 TM3MD 04 bp3 TM3EN 0 2 Select the lower timer PWM operation TM2MD 04 bp4 TM2PWM 1 3 Set the cascade connection 04 bp4 5 1 4 Set the output pin PO1DIR 010 bp6 P1DIRO 21 PORTO1 000 bp4 PIODATA 1 BZCTR 06 bpO PWME10 1 MODONT 05 bp2 PNMOSO 0 5 Select the count clock source TM2MD 04 bp2 0 TM2CK2 0 100 6 Setthe PWM duty 2 054 55 1 Set the 2 flag of the timer 2 mode register TM2MD and the flag of the timer 3 mode register TM3MD to 0 to disable the timer 2 and timer 3 counting Set the TM2PWM flag of the TM2MD
120. unter waveform of PWM source A TCO output PWM output 1 setup time for compare register PWM basic component overflow of binary counter Figure 5 5 1 Count Timing of PWM Output at normal PWM source waveform A is H while counting up from x 00 to the value stored in the compare register B is L after the match to the value in the compare register then the binary counter continues counting up till the overflow C is again if the binary counter is overflown The PWM output from pin outputs the PWM source waveform with 1 count clock delay This is happened because the waveform is created inside to correct the output cycle 8 Bit PWM Output V 21 Chapter 5 Timers iCount Timing of PWM Output when the compare register is 00 Timer 2 is the count timing when the compare register is set to x 00 TM2EN flag compare register uo Kec SIEGE Ale counter H TCO output PWM output Figure 5 5 2 Count Timing of PWM Output when compare register is x 00 00 When TM2EN flag is stopped 0 PWM output is H iBCount Timing of PWM Output when the compare register is x FF Timer 2 Here is the count timing when the compare register is set to x FF TM2EN flag compare register uo GG counter TCO output PWM output Figure 5 5 3 Count Timing of PWM Output when compare register is x FF ER V 22 8BitPWM Output Chapter 5 Timers 5 5 2
121. ut TCOONT x 06A bp6 1 10 Start the timer operation TM2MD 04 bp3 TM2EN 1 10 Set the TM2PWM flag of the TM2MD register to 0 to select the normal timer operation Select fosc as clock source by the TM2CK2 0 flag of the TM2MD register Set the base cycle of remote control carrier by writing x 6C to the timer 2 compare register TM2OC The set value should be 8 MHz 73 4 kHz 1 108 x 6C So 8 MHz is divided to be 73 4 kHz 2 times 36 7 kHz Set the RMOEN flag of the TCOCNT register to 1 to enable the remote control carrier output Set the TM2EN flag of the TM2MD register to 1 to stop the timer 2 counting TM2BC counts up from 00 Timer 2 outputs the base cycle pulse set in TM2OC Then the 1 3 duty remote control carrier pulse signal is output V 30 Remote Control Career Output Chapter5 Timers 5 8 High Precision PWM Output 5 8 1 Operation PWM waveform is generated by setting the PWM duty to the timer 2 compare register TM2OC and setting the PWM cycle to the timer 3 compare register TM3OC Port outputs H till the value of the 8 bit binary counter reaches the set value in the timer 2 compare register then outputs L till the value reaches the set value in the timer 3 compare register and the counter is cleared timer output PWM output 1 1 1 1 timer2 1 compare register timer 3 compare register Figure 5 8 1 Co
122. uzzer output control register BZCTR and set the TCOE flag the RMOS flag and the TCOS flag of the timer output control register TCOCNT Set P32 to output mode The pulse with frequency that selected by the buzzer output pin P32 BZ is output Y The initial value of buzzer output the duration till the first rising and falling are indefinite m 34 Buzzer Output 5 9 2 Setup Example mBuzzer Output Setup Example The buzzer output pin P32 TCO BZ outputs clock that the source oscillation fosc is divided by 2048 An example setup procedure with a description of each step is shown below Chapter5 Timers Setup Procedure Description Stop the buzzer output 06 bp7 TCOE 0 Set the pin P23DIR x 012 bp6 2 1 Select the buzzer output frequency BZCTR 06 bp5 4 20 1 0 10 Start the buzzer output operation TCOONT 06 bp2 5 0 bp3 RMOS 0 bp7 BZOE 1 Set the TCOEN flag of the timer output control register to 0 to stop the buzzer output Set the P3DIR2 flag of the port 2 port direction control register P23DIR to 1 to set P32 to output mode Select fosc 2048 as buzzer output frequency by the BZCK1 0 flag of the BZCTR register Set the TCOE flag the RMOS flag and the TCOS flag of the timer output control register to start buzzer output V 35 Buzzer Output Ch
123. xecution of EDI instruction interrupt acceptance is disabled till the next instruction is completed 1 cycle EDI instruction 1 instruction 1 interrupt request lt No acceptance 5 interrupt acceptance is disabled after the interrupt is accepted till 4 cycles are completed Also if EDI instruction comes after that the acceptance is disabled till EDI instruction and the next instruction are completed 1 cycle 1 cycle acceptance JMP instruction etc acceptance JMP instruction EDI instruction an instruction 1 SSS A A the end of 4 cycles the end of 4 cycles 1 cycle d 2 cycles instruction no acceptance the end of 4 cycles At 1 cycle instruction the acceptance is disabled till 1 cycle instruction is completed At 2 cycles instruction the acceptance is disabled till 2 cycles instruction is completed At 3 cycles instruction the acceptance is disabled till 3 cycles instruction is completed IV 8 Overview Chapter4 Interrupts Here is the example for acceptance operation O When the interrupt factor is generated in execution of 2 cycles instruction the interrupt acceptance is started after 2 cycles instruction is completed 1 cycle cycles instruction 2 1 JMP instruction etc
124. z divided by 4 24 V to 5 5 V 1 00 us at 8 kHz divided by 8 2 0 V to 5 5 V 2 00 us at 4 kHz divided by 8 3 0 V to 5 5 V 0 50 us at 8 MHz divided by 4 2 4 V to 5 5 V 1 00 us at 8 kHz divided by 8 2 3 V to 5 5 V 2 00 us at 4 kHz divided by 8 Mask option Auto reset circuit 1 No auto reset 2 Auto reset circuit 1 3 Auto reset circuit 2 1 No auto reset Pin DC Characteristics Output current input current and input judge level are the same There are no other functional differences EPROM Version Chapter 10 Appendices 10 1 4 Writing to Microcomputer with Internal EPROM This LSI needs the dedicated device for writing The device should be only Data I O Lab Site can be used after down loading EPROM Version 5 Chapter 10 Appendices 10 1 5 Cautions on Operation of ROM Writer iCautions on Handling the ROM writer 1 The Ver programming voltage for the EPROM versions is 12 5 V Programming with a 21 V ROM writer can lead to damage The ROM writer specifications need the dedicated device for writing 2 Make sure that the socket adapter matches the ROM writer socket and that the chip is correctly mounted in the socket adapter Faulty connections can lead to damage 3 After cleaning all memory of the ROM writer load the program to the ROM writer Data is written to the address x 0000 to x 7FFF 4 After confirming the device type write the loaded progr

MN15G0202/0402 LSI User`s Manual

Contents

Download Pdf Manuals

Related Search

Related Contents