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1. S Function Details of Cautions E Function n amp O Pe 8 bit timer Error when timer The time from starting the timer to generation of the match signal includes an p 132 O 2 I 80 starts error of up to 1 5 clocks This is because if the timer is started while the count clock is high the rising edge may be immediately detected and the counter may be incremented refer to Figure 7 6 5 CR80 8 bit 8 bit compare register 80 CR80 can be set to OOH p 132 L compare register 80 STOP mode Before executing the STOP instruction be sure to stop the timer operation p 132 TCE80 0 8 bit timer CMP01 8 bit CMP01 cannot be rewritten during timer count operation p 135 2 H1 timer H compare register 01 5 g CMP11 8 bit In the PWM output mode be sure to set CMP11 when starting the timer count p 135 L timer H compare operation TMHE1 1 after the timer count operation was stopped TMHE1 register 11 0 be sure to set again even if setting the same value to CMP11 TMHMD1 8 bit When TMHE1 1 setting the other bits of the TMHMD1 register is prohibited p 137 timer H mode In the PWM output mode be sure to set 8 bit timer H compare register 11 p 137 register 1 CMP11 when starting the timer count operation TMHE1 1 after the timer count operation was stopped TMHE1 0 be sure t
2. ASIM6 Asynchro At startup set POWER6 to 1 and then set TXE6 to 1 To stop the operation p 187 O nous serial clear TXE6 to 0 and then clear POWERS6 to 0 interface operation At startup set POWERS to 1 and then set RXE6 to 1 To stop the operation p 187 mode register6 clear RXE6 to 0 and then clear POWERS to 0 Set POWERS6 to 1 and then set RXE6 to 1 while a high level is input to the p 187 O RxD6 pin If POWERS6 is set to 1 and RXE6 is set to 1 while a low level is input reception is started Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61 PS60 and CL6 p 187 bits Fix the PS61 and PS60 bits to O when mounting the device on LIN p 187 O Make sure that TXE6 0 when rewriting the SL6 bit Reception is always p 187 L performed with the number of stop bits 1 and therefore is not affected by the set value of the SL6 bit Make sure that RXE6 0 when rewriting the ISRM6 bit p 187 ASIS6 The operation of the PE6 bit differs depending on the set values of the PS61 p 188 Asynchronous and PS60 bits of asynchronous serial interface operation mode register 6 serial interface ASIM6 reception error The first bit of the receive data is checked as the stop bit regardless of the p 188 Status register 6 number of stop bits If an overrun error occurs the next receive data is not written to receive buffer p 188 register 6 RXB6 but discarded ASIF6 T
3. TMOO count value 0000H Timer start 2 16 bit timer counter 00 TM00 operation lt l gt lt 4 gt 16 bit timer counter 00 TMOO starts operation at the moment TMC002 and TMC003 operation stop mode are set to a value other than 0 0 respectively Set TMC002 and TMCO03 to 0 O to stop the operation Even if TMOO is read the value is not captured by 16 bit timer capture compare register 010 CRO10 During TMO0 is read the count clock is stopped Regardless of the CPU s operation mode when the timer stops the signals input to pins TI000 TI010 are not acknowledged 3 Setting of 16 bit timer capture compare registers 000 010 CRO00 CR010 120 lt l gt lt 2 gt lt 4 gt Set 16 bit timer capture compare register 000 CR000 to other than OOOOH in the clear amp start mode entered on match between TMOO and CR000 This means a 1 pulse count operation cannot be performed when this register is used as an external event counter When the clear amp start mode entered on a match between TMOO and CR000 is selected CRO00 should not be specified as a capture register In the free running mode and in the clear amp start mode using the valid edge of the T1000 pin if CROn0 is set to 0000H an interrupt request INTTMOn0 is generated when CROnO changes from 0000H to 0001H following overflow FFFFH If the new value of CROn0 is less than the value of TM00 TMO0 continues counting overflows a
4. V V V V V V V V V Note 1 Response time tio Minimum pulse width tlw Note 2 Operation stabilization wait time twat Notes 1 Time required from voltage detection to interrupt output or internal reset signal generation 2 Time required from setting LVION to 1 to operation stabilization Remarks 1 Vivio gt Vivi gt Vivi2 gt Vivis gt Vivia gt Vivis gt Vivie gt Vivi7 gt Vivis gt VLvio 2 Vpoc lt Vivim m 0 to 9 LVI Circuit Timing Supply voltage Voo Detection voltage MAX Detection voltage TYP Detection voltage MIN tLwaiT LVION 1 Time Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Ta 40 to 85 C Data retention supply voltage Release signal set time Preliminary User s Manual U17446EJ1VOUD 347 CHAPTER 21 ELECTRICAL SPECIFICATIONS TARGET VALUES Flash Memory Programming Characteristics Ta 40 to 85 C 2 7 V lt Voo lt 5 5 V Vss 0 V Parameter Conditions Supply current Voo 5 5 V Erasure count per 1 block Ta 10 to 85 C Ta 40 to 85 C Chip erase time TCERASE Ta 10 to 85 C Nerase lt 100 4 5 V lt Voo lt 5 5 V 3 5 V lt Voo lt 4 5 V 2 7 V lt Voo lt 3 5 V Ta 10 to 85 C Nerase lt 1000 4 5 V lt Voo lt 5 5 V 3 5 V lt Voo lt 4 5 V 2 7 V lt Voo lt 3 5 V
5. TMHE1 INTTMH1 o L TOH1 Interval time c Operation when C MP01 00H Count clock LILIU LILL ULUL LI d Count start 1 i f 8 bit timer counter H1 00H ne ee 4 1 1 1 1 K 1 1 1 1 1 1 CMP01 00H ee TMHE1 INTTMH1 TOH1 f i Lat a 1 1 Interval time Preliminary User s Manual U17446EJ1VOUD 141 CHAPTER 8 8 BIT TIMER H1 8 4 2 Operation as PWM output mode In PWM output mode a pulse with an arbitrary duty and arbitrary cycle can be output 8 bit timer compare register 01 CMP01 controls the cycle of timer output TOH1 Rewriting the CMP01 register during timer operation is prohibited 8 bit timer compare register 11 CMP11 controls the duty of timer output TOH1 Rewriting the CMP11 register during timer operation is possible The operation in PWM output mode is as follows TOH1 output becomes active and 8 bit timer counter H1 is cleared to 0 when 8 bit timer counter H1 and the CMP01 register match after the timer count is started TOH1 output becomes inactive when 8 bit timer counter H1 and the CMP11 register match 1 Usage In PWM output mode a pulse for which an arbitrary duty and arbitrary cycle can be set is output lt 1 gt Set each register Figure 8 8 Register Setting in PWM Output Mode i Setting timer H mode register 1 TMHMD1 TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOENI
6. on Stops operation of comparator 1 Enables operation of comparator Remarks 1 fxp Oscillation frequency of clock to peripheral hardware 2 The conversion time refers to the total of the sampling time and the time from successively comparing with the sampling value until the conversion result is output Notes 1 Even when the ADCE 0 comparator operation stopped the A D conversion operation starts if the ADCS is set to 1 However the data of the first conversion is out of the guaranteed value range so ignore it 2 Be sure to set the FR2 FR1 and FRO in accordance with the reference voltage range and satisfy Notes 3 and 4 below Example When AVrer gt 2 7 V e Set FR2 FR1 and FRO 0 1 1 or 1 1 1 e The sampling time is 11 0 ws or more and the A D conversion time is 14 0 ws or more and 100 ws or less Preliminary User s Manual U17446EJ1VOUD 165 CHAPTER 10 A D CONVERTER Notes 3 Set the sampling time as follows e AVreF gt 4 5V 1 0 us or more e AVreF gt 4 0V 2 4 us or more e AVreF gt 2 85 V 3 0 us or more e AVreF gt 2 7V 11 0 us or more 4 Set the A D conversion time as follows e AVreF gt 4 5V 3 0 us or more and less than 100 ws e AVreF gt 4 0V 4 8 ws or more and less than 100 ws e AVrer gt 2 85 V 6 0 us or more and less than 100 ws e AVreF gt 2 7V 14 0 us or more and less than 100 ws 5 The operation of the comparator is controlled by ADCS and ADCE and it takes 1 ws f
7. Remark fxr Oscillation frequency of clock to peripheral hardware Table 7 4 Interval Time of 8 Bit Timer 80 fxe 10 0 MHz TCL801 TCL800 Minimum Interval Time Maximum Interval Time Resolution 2 fxe 6 4 us 2 fxe 1 64 ms 2 fxe 6 4 us 2 ifxp 25 6 us 2 fxe 6 55 ms 2 fxP 25 6 us 2 fxp 102 us 2 fxp 26 2 ms 2 fxe 102 us 2 6 fxe 6 55 ms 2 fxpe 1 68 s 2 fxe 6 55 ms Remark fxr Oscillation frequency of clock to peripheral hardware 130 Preliminary User s Manual U17446EJ1VOUD CHAPTER 7 8 BIT TIMER 80 Count clock TM80 count value Remark CR80 TCE80 INTTM80 TO80 a a a Figure 7 5 Timing of Interval Timer Operation 1 i T To 1 1 I i 1 1 i l Count start E ees Interval time N 1 x t N 00H to FFH Preliminary User s Manual U17446EJ1VOUD 131 CHAPTER 7 8 BIT TIMER 80 7 5 Notes on 8 Bit Timer 80 1 Error when timer starts The time from starting the timer to generation of the match signal includes an error of up to 1 5 clocks This is because if the timer is started while the count clock is high the rising edge may be immediately detected and the counter may be incremented refer to Figure 7 6 Figure 7 6 Case Where Error of 1 5 Clocks Max Occurs 8 bit timer counter 80 TM80 Clear signal TCE80 WV Selected clock teese ooo Clear signal a Count pulse l j j j
8. PG FP4 GUI Software setting value example The above is a recommendation value A value may change according to the environment to be used Set up after surely performing sufficient evaluation Security settings The security setting is valid when the programming mode is set next time Therefore when the security setting command is executed exit from the programming mode then set the programming mode again After the security setting of the batch erase is set erasure cannot be performed for the device In addition even if a write command is executed data different from that which has already been written to the flash memory cannot be written because the erase command is disabled Self programming function Self programming processing must be included in the program before performing self writing If an interrupt occurs during self programming the interrupt request flag is set 1 and interrupt servicing is performed after the self programming mode is released To avoid this operation disable interrupt servicing by setting MKO and MK1 to FFH and executing the DI instruction during self programming or before a mode is shifted from the normal mode to the self programming mode with a specific sequence No instructions can be executed while a self programming command is being executed Therefore clear and restart the watchdog timer counter in advance so that t
9. Selector fe Q O ao oO ao oO gt c e 2 O g me oO D oO o z a INTLVI Reference voltage source LVIS3 LVIS2 LVIS1 LVISO LVION LVIMD LVIF Low voltage detection Low voltage detect level select register LVIS register LVIM Internal bus 256 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 17 LOW VOLTAGE DETECTOR 17 3 Registers Controlling Low Voltage Detector The low voltage detector is controlled by the following registers e Low voltage detect register LVIM e Low voltage detection level select register LVIS 1 Low voltage detect register LVIM This register sets low voltage detection and the operation mode This register can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears this register to OOHN Figure 17 2 Format of Low Voltage Detect Register LVIM Address FF50H After reset OOHNt R WNote2 Symbol lt 7 gt 6 5 4 3 2 lt 1 gt lt 0 gt LVIONN amp 3 Enabling low voltage detection operation 0 Disable operation 1 Enable operation LVIMD Low voltage detection operation mode selection 0 Generate interrupt signal when supply voltage Voo lt detection voltage Vivi 1 Generate internal reset signal when supply voltage Voo lt detection voltage Vivi LVIFNote4 Low voltage detection flag Supply voltage Voo gt detection voltage Vivi or wh
10. Supply voltage Vop Detection voltage Vivi LVIF 0 Ng Supply voltage Voo gt Detection voltage Vivi is confirmed Initialization Initialization of ports processing Notes 1 If reset is generated again during this period initialization processing is not started 2 A flowchart is shown on the next page Preliminary User s Manual U17446E 1VOUD 263 CHAPTER 17 LOW VOLTAGE DETECTOR Figure 17 6 Example of Software Processing After Release of Reset 2 2 e Checking reset source Check reset source WDTRE of RESF Yes register 1 Reset processing by watchdog timer LVIRF of RESF No register 1 Power on clear external reset generated Reset processing by low voltage detector 264 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 18 OPTION BYTE The 78K0S KB1 has an area called an option byte at address 0080H of the flash memory When using the product be sure to set the following functions by using the option byte 1 Selection of system clock source e High speed Ring OSC clock e Crystal ceramic oscillation clock e External clock input 2 Low speed Ring OSC clock oscillation e Cannot be stopped e Can be stopped by software 3 Control of RESET pin e Used as RESET pin e RESET pin is used as an input port pin P 34 4 Oscillation stabilization time on power application or after reset release e 2 HFK e 2 fx e 2 fx 2 fx Figure 18 1 Positioni
11. Ta 40 to 85 C Nerase lt 100 4 5 V lt Voo lt 5 5 V 3 5 V lt Voo lt 4 5 V 2 7 V lt Voo lt 3 5 V Ta 40 to 85 C Nerase lt 1000 4 5 V lt Voo lt 5 5 V 3 5 V lt Voo lt 4 5 V 2 7 V lt Voo lt 3 5 V Block erase time TBERASE Ta 10 to 85 C Nerase lt 100 4 5 V lt Voo lt 5 5 V 3 5 V lt Voo lt 4 5 V 2 7 V lt Voo lt 3 5 V Ta 10 to 85 C Nerase lt 1000 4 5 V lt Voo lt 5 5 V 3 5 V lt Voo lt 4 5 V 2 7 V lt Voo lt 3 5 V Ta 40 to 85 C Nerase lt 100 4 5 V lt Voo lt 5 5 V 3 5 V lt Voo lt 4 5 V 2 7 V lt Voo lt 3 5 V Ta 40 to 85 C Nerase lt 1000 4 5 V lt Voo lt 5 5 V 3 5 V lt Voo lt 4 5 V 2 7 V lt Voo lt 3 5 V Byte write time Ta 10 to 85 C Nerase lt 1000 Ta 40 to 85 C Nerase lt 1000 Internal verify TVERIFY Per 1 block Per 1 byte Blank check TBLKCHK Per 1 block Retention years Ta 10 to 85 C Nerase lt 1000 Ta 40 to 85 C Nerase lt 1000 Note Depending on the erasure count Nerase the erase time varies Refer to the chip erase time and block erase time parameters Remark When a product is first written after shipment erase write and write only are both taken as one rewrite 348
12. Xx1 P121 X2 P122 HIGH SPEED Ring OSC 19 CHAPTER 1 OVERVIEW 1 7 Functional Outline Item uP D78F 9232 uP D78F 9234 Internal Flash memory 4 KB memory High speed RAM 256 bytes Memory space 64 KB X1 input clock oscillation frequency Crystal ceramic external clock input 10 MHz Voo 2 0 to 5 5 V Ring OSC High speed oscillation Internal Ring oscillation 8 MHz TYP clock frequency Low speed for TMH1 Internal Ring oscillation 240 kHz TYP and WDT General purpose registers 8 bits x 8 registers Minimum instruction execution time 0 2 ws 0 4 us 0 8 us 1 6 us 3 2 us X1 input clock fx 10 MHz Multiplier 8 bits x 8 bits 16 bits 1 0 port Total 26 pins CMOS 1 0 24 pins CMOS input 1 pin CMOS output 1 pin e 16 bit timer event counter 1 channel e 8 bit timer timer H1 1 channel e 8 bit timer timer 80 1 channel e Watchdog timer 1 channel Timer output 2 pins PWM 1 pin A D converter 10 bit resolution x 4 channels Serial interface LIN bus supporting UART mode 1 channel Vectored External 4 interrupt sources Internal 9 Reset e Reset by RESET pin e Internal reset by watchdog timer e Internal reset by power on clear e Internal reset by low voltage detector Supply voltage Voo 2 0 to 5 5 VN Operating temperature range Ta 40 to 85 C Package 30 pin plastic SSOP Note Use this product in a vol
13. 6 4 4 Square wave output operation Setting The basic operation setting procedure is as follows lt l gt Setthe count clock by using the PRMOO register lt 2 gt Setthe CRCOO register see Figure 6 27 for the set value lt 3 gt Setthe TOC0O0 register see Figure 6 27 for the set value lt 4 gt Setany value to the CRO00 register 0000H cannot be set lt 5 gt Setthe TMCOO register to start the operation see Figure 6 27 for the set value Caution Changing the CR000 setting during TM00 operation may cause a malfunction To change the setting refer to 6 5 Cautions Related to 16 Bit Timer Event Counter 00 17 Changing compare register during timer operation Remarks 1 For the setting of the TO00 pin see 6 3 5 Port mode register 3 PM3 2 For how to enable the INTTM000 interrupt see CHAPTER 13 INTERRUPT FUNCTIONS A square wave with any selected frequency can be output at intervals determined by the count value preset to 16 bit timer capture compare register 000 CR000 The TOOO pin output status is reversed at intervals determined by the count value preset to CR000 1 by setting bit O TOEQO and bit 1 TOC001 of 16 bit timer output control register 00 TOC00 to 1 This enables a square wave with any selected frequency to be output Figure 6 27 Control Register Settings in Square Wave Output Mode 1 2 a 16 bit timer mode control register 00 TMC00 4 TMC003 TMC002 TMC001 OVFO0 mco eee es
14. CY A r A CY A r CY A saddr A CY A saddr C A addr16 U INJINI WIN A CY A addr16 CY A HL A CY A HL CY A HL byte A CY A HL byte C A yte A amp A az byte saddr byte saddr lt saddr a byte A r AcAar A saddr A amp A saddr A addr16 A lt A addr16 A HL A amp A a HL A HL byte A A HL byte A byte A amp A v byte saddr byte saddr lt saddr v byte A r AAvr A saddr A amp A v saddr A addr16 1 2 2 3 2 2 3 1 2 2 3 2 2 3 A lt A v addr16 A HL A amp A v HL A HL byte A amp A v HL byte Remark A yte A lt A w byte saddr byte saddr saddr v byte A r AcAvr A saddr A amp A x saddr A addr16 WI NIN WIN NY rR A amp A addr16 A HL bh A lt Av HL A HL byte DI Ds ay HPL PIL nT PI DITD o PIL HPILDIT AIAJ DI OI HRI _ HL DIT HP Ioa DAD oye RIL oa Fs A amp A v HL byte One instruction clock cycle is one CPU clock cycle fcpu selected by the processor clock control register PCC Preliminary User s Manual U17446EJ 1VOUD 331 CHAPTER 20 INSTRUCTION SET OVERVIEW Mnemonic Operand Clocks Operation A byte A byte saddr byte saddr
15. If so write the next transmit data second byte to the TXB6 register If data is written to the TXB6 register while the TXBF6 flag is 1 the transmit data cannot be guaranteed The communication status can be checked using the TXSF6 flag TXSF6 Transmission Status 0 Transmission is completed 1 Transmission is in progress Cautions 1 To initialize the transmission unit upon completion of continuous transmission be sure to check that the TXSF6 flag is 0 after generation of the transmission completion interrupt and then execute initialization If initialization is executed while the TXSF6 flag is 1 the transmit data cannot be guaranteed During continuous transmission an overrun error may occur which means that the next transmission was completed before execution of INTST6 interrupt servicing after transmission of one data frame An overrun error can be detected by developing a program that can count the number of transmit data and by referencing the TXSF6 flag Preliminary User s Manual U17446EJ1VOUD CHAPTER 11 SERIAL INTERFACE UART6 Figure 11 16 shows an example of the continuous transmission processing flow Figure 11 16 Example of Continuous Transmission Processing Flow Set registers Write TXB6 Transfer executed necessary number of times Read ASIF6 TXBF6 0 Yes Write TXB6 i Transmission completion interrupt occurred
16. Tcy vs Voo High speed Ring OSC Clock 60 10 S 4 22 o Guaranteed operation range o S 1 0 oO 0 95 0 47 0 23 0 1 Supply voltage Voo V Preliminary User s Manual U17446EJ1VOUD 343 CHAPTER 21 ELECTRICAL SPECIFICATIONS TARGET VALUES 2 Serial interface Ta 40 to 85 C Voo 2 0 to 5 5 V Vss 0 V UART mode UARTE6 dedicated baud rate generator output ewer SSS id sta Note Use this product in a voltage range of 2 2 to 5 5 V because the detection voltage Vpoc of the power on clear POC circuit is 2 1 V 0 1 V AC Timing Test Points Excluding X1 Input 0 8Vpp 0 8Vop gt Test points lt 0 2VoD 0 2Vop Clock Timing X1 input T1000 Timing tri a tri T1000 Interrupt Input Timing INTPO to INTP3 RESET Input Timing tR RESET 344 Preliminary User s Manual UU17446EJ1VOUD CHAPTER 21 ELECTRICAL SPECIFICATIONS TARGET VALUES A D Converter Characteristics Ta 40 to 85 C 2 7 V lt AVrer lt Voo lt 5 5 V Vss AVss 0 V Parameter Conditions Resolution Overall error s 4 0 V lt AVrer lt 5 5 V 2 7 V lt AVrer lt 4 0 V Conversion time 4 5 V lt AVrer lt 5 5 V 4 0 V lt AVrer lt 4 5 V 2 85 V lt AVrer lt 4 0 V 2 7 V lt AVreF lt 2 85 V Zero scale error 4 0 V lt AVrer lt 5 5 V 2 7
17. 1 after the timer count operation was stopped TMHE1 0 be sure to set again even if setting the same value to CMP11 Preliminary User s Manual U17446EJ1VOUD 135 CHAPTER 8 8 BIT TIMER H1 8 3 Registers Controlling 8 Bit Timer H1 The following three registers are used to control 8 Bit Timer H1 e 8 bit timer H mode register 1 TMHMD1 e Port mode register 4 PM4 e Port register 4 P4 1 8 bit timer H mode register 1 TMHMD1 This register controls the mode of timer H This register can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears this register to OOH 136 Preliminary User s Manual U17446EJ1VOUD CHAPTER 8 8 BIT TIMER H1 Figure 8 4 Format of 8 Bit Timer H Mode Register 1 TMHMD1 Address FF70H_ After reset OOH R W Symbol lt gt 6 lt 1 gt lt 5 4 3 2 0 gt TMHMD1 TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 TMHE1 Timer operation enable 0 Stop timer count operation counter is cleared to 0 Enable timer count operation count operation started by inputting clock 0 0 0 fxp 0 1 fxp 2 1 0 fxp 24 1 1 fxP 28 0 fxP 2 2 2 44 kHz 0 fri 2 1 88 kHz TYP Other than above Setting prohibited 10 MHz 2 5 MHz 625 kHz 156 25 kHz TMMD11 TMMD10 Timer operation mode Interval timer mode PWM output mode Other than above Setting prohibited TOLEV1 Timer output level
18. If a low level is input to the RESET pin before the option byte is referenced again after reset is released by the POC circuit the 78KOS KB1 is reset and is held in the reset state until a high level is input to the RESET pin P30 P31 and P43 pins Because P30 P31 and P43 are also used as external interrupt pins the corresponding interrupt request flag is set if each of these pins is set to the output mode and its output level is changed To use the port pin in the output mode therefore set the corresponding interrupt mask flag to 1 in advance Although a 1 bit memory manipulation instruction manipulates 1 bit it accesses a port in 8 bit units Therefore the contents of the output latch of a pin in the input mode even if it is not subject to manipulation by the instruction are undefined in a port with a mixture of inputs and outputs Chapter 5 PCC Processor clock control register Bits 7 to 2 and 0 must be set to 0 Preliminary User s Manual U17446EJ1VOUD APPENDIX D LIST OF CAUTIONS Chapter 5 Soft Classification Function Main clock Details of Function OSTS Oscillation stabilization time select register Cautions To set and then release the STOP mode set the oscillation stabilization time as follows Expected oscillation stabilization time of resonator lt Oscillation stabilization time set by OSTS 2 18
19. J04 1 Preliminary User s Manual U17446EJ1VOUD Target Readers Purpose Organization How to Use This Manual INTRODUCTION This manual is intended for user engineers who wish to understand the functions of the 78KOS KB1 in order to design and develop its application systems and programs The target devices are the following subseries products e 78K0S KB1 uwPD78F9232 78F9234 This manual is intended to give users on understanding of the functions described in the Organization below Two manuals are available for the 78KOS KB1 this manual and the Instruction Manual common to the 78K 0S Series 78K 0S Series Instructions 78KOS KB1 User s Manual User s Manual e Pin functions e CPU function e Internal block functions e Instruction set e Interrupts e Instruction description Other internal peripheral functions Electrical specifications target values It is assumed that the readers of this manual have general knowledge of electrical engineering logic circuits and microcontrollers To understand the overall functions of 78KOS KB1 Read this manual in the order of the CONTENTS How to read register formats For a bit number enclosed in a square the bit name is defined as a reserved word in the RA78KOS and is defined as an sfr variable using the pragma sfr directive in the CC78KOS To learn the detailed functions of a register whose register name is known See APPENDIX C REGIST
20. No Figure 19 25 lt 1 gt to lt 11 gt Abnormal VCERR and WEPRERR flags a Normal Figure 19 21 lt 6 gt Shift to normal mode lt 1 gt to lt 5 gt Abnormal terminationNote Normal termination Note Perform processing to shift to normal mode in order to return to normal processing Remark lt 1 gt to lt 6 gt in Figure 19 27 correspond to lt 1 gt to lt 6 gt in 19 8 10 2 above 312 Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY An example of a program list when the command execution time from write to internal verify should be minimized in self programming mode is shown below START MOV MKO 11111111B Masks all interrupts MOV MK1 11111111B DI ModeOnLoop MOV PFS 00H MOV PFCMD 0A5H PFCMD register control MOV FLPMC 01H FLPMC register control sets value MOV FLPMC 0FEH FLPMC register control inverts set value MOV FLPMC 01H Sets self programming mode with FLPMC register control sets value MOV A PFS CMP A 00H BNZ SModeOnLoop Checks completion of write to specific registers Repeats the same processing when an error occurs FlashWrite MOVW HL DataAdrTop Sets address at which data to be written is located MOVW DE WriteAdr Sets address at which data is to be written FlashWriteLoop MOV FLCMD 05H Sets flash control command byte write MOV A D MOV FLAPH A Sets address at which data is to be written MOV A E MOV FLAPL A
21. QB 30MC NQ 01T This target connector is used to mount on the target system Specifications of pin header on target system 0 635 mm x 0 635 mm height 6 mm Remarks 1 NP 30MC is a product of Naito Densei Machida Mfg Co Ltd For further information contact Naito Densei Machida Mfg Co Ltd TEL 81 45 475 4191 2 NSPACK30BK and YSPACK30BK are products of TOKYO ELETECH CORPORATION For further information contact Daimaru Kogyo Co Ltd Tokyo Electronics Department TEL 81 3 3820 7112 Osaka Electronics Department TEL 81 6 6244 6672 A 5 2 When using in circuit emulator QB 78KOSKX1MINI QB 78KOSKX1MINI In circuit emulator In circuit emulator for debugging hardware and software of application system using 78KOS Kx1 Series Supports integrated debugger ID78KOS QB Used in combination with AC adapter target cable and USB interface cable for connecting the host machine Specifications of pin header on target system 0 635 mm x 0 635 mm height 6 mm 355 Preliminary User s Manual U17446EJ1VOUD APPENDIX A DEVELOPMENT TOOLS A 6 Debugging Tools Software ID78KOS NS This debugger supports the in circuit emulators for the 78K OS Series ID78KOS NS is Windows supporting in circuit based software emulator IE 78KOS NS This debugger has enhanced debugging functions supporting C language By using its window IE 78KOS NS A integration function that associates the source program disassem
22. Reset function Details of Function RESF Reset control flag register Cautions Do not read data by a 1 bit memory manipulation instruction 15 18 Chapter 16 Soft Hard Soft Power on clear circuit Functions of power on clear circuit If an internal reset signal is generated in the POC circuit the reset control flag register RESF is cleared to 00H Because the detection voltage VPoc of the POC circuit is in a range of 2 1 V 0 1 V use a voltage in the range of 2 2 to 5 5 V Cautions for power on clear circuit In a system where the supply voltage Vpop fluctuates for a certain period in the vicinity of the POC detection voltage VPoc the system may be repeatedly reset and released from the reset status In this case the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action Chapter 17 Low voltage detector LVIM Low voltage detect register To stop LVI follow either of the procedures below e When using 8 bit manipulation instruction Write OOH to LVIM e When using 1 bit memory manipulation instruction Clear LVION to 0 Be sure to set bits 2 to 6 to 0 LVIS Low voltage detection level select register Bits 4 to 7 must be set to 0 When used as reset lt 1 gt must always be executed When LVIMK 0 an interrupt ma
23. byte A r A r A saddr A addr16 A saddr A addr16 WU INJINI WI dN A HL m A HL A HL byte A HL byte AX word AX CY AX word AX word AX CY AX word AX word AX word r rertl saddr saddr 1 rer l NYT NIT NIN UJUI rn saddr saddr 1 rp rperp 1 rp A 1 rp lt crp l1 CY A7 amp Ao Am 1 amp Am x 1 A 1 CY Ao amp Az Am lt Am x 1 A 1 CY amp Ao A7 amp CY Ami lt Am x 1 A 1 CY Az Ao amp CY Amn amp Am x 1 saddr bit lt 1 saddr bit Sfr bit Sfr bit 1 A bit A bite 1 4 6 4 4 8 6 6 6 6 6 4 4 4 4 4 4 2 2 2 2 6 6 4 6 PSW bit PSW bit 1 HL bit HL bit 1 saddr bit saddr bit 0 Sfr bit Sfr bit 0 A bit A bit 0 PSW bit PSW bit 0 N WIlin lwlwlrn lwlrn w lwle oO HL bit HL bit 0 CY CY lt 1 CY CY lt 0 CY CY CY Remark One instruction clock cycle is one CPU clock cycle fcpu selected by the processor clock control register PCC 332 Preliminary User s Manual U17446EJ 1VOUD Mnemonic Operand laddr16 CHAPTER 20 INSTRUCTION SET OVERVIEW Clocks Operation SP 1 PC 3 SP 2 PC 3 PC addrl6 SP SP 2 addr5 SP 1 PC 1 SP 2 lt PC
24. 1 or bit 7 POWERS and bit 5 RXE6 of ASIM6 1 Figure 11 5 Format of Asynchronous Serial Interface Operation Mode Register 6 ASIM6 1 2 Address FF90H After reset 01H R W Symbol lt 7 gt lt 6 gt lt 5 gt 4 3 2 1 0 ASIM6 POWER6 TXE6 RXE6 PS61 PS60 ISRM6 POWER6 Enabling disabling operation of internal operation clock Disable operation of the internal operation clock fixes the clock to low level and asynchronously resets the internal circuit Enable operation of the internal operation clock TXE6 Enabling disabling transmission 0 Disable transmission synchronously reset the transmission circuit 1 Enable transmission Notes 1 The output of the TxD6 pin goes high and the input from the RxD6 pin is fixed to the high level when POWER is cleared to 0 during a transmission 0 2 Asynchronous serial interface reception error status register 6 ASIS6 asynchronous serial interface transmission status register 6 ASIF6 bit 7 SBRF6 and bit 6 SBRT6 of asynchronous serial interface control register 6 ASICL6 and receive buffer register 6 RXB6 are reset 3 Operation of the 8 bit counter output is enabled at the second base clock after 1 is written to the POWERS bit 186 Preliminary User s Manual U17446EJ1VOUD CHAPTER 11 SERIAL INTERFACE UART6 Figure 11 5 Format of Asynchronous Serial Interface Operation Mode Register 6 ASIM6 2 2 RXE6 Enabling disabling reception Disable reception sy
25. 13 18 0 P43 TxD6 INTP1 P30 TIOOO INTPO O lt gt 14 17 0 P42 TOH1 P40 0 115 16 0 P41 INTP3 Caution Connect the AVss pin to Vss ANIO to ANI3 Analog input P130 Port 13 AVREF Analog reference voltage RESET Reset AVss Analog ground RxD6 Receive data INTPO to INTP 3 External interrupt input T1000 T1010 Timer input POO to P03 Port 0 TO00 TOH1 Timer output P20 to P23 Port 2 TxD6 Transmit data P30 to P34 Port 3 Vpop P ower supply P40 to P47 Port 4 Vss Ground P120 to P123 Port 12 X1 X2 Crystal oscillator X1 input clock Preliminary User s Manual U17446EJ 1VOUD 17 CHAPTER 1 OVERVIEW 1 5 78K0S Kx1 Product Lineup The following table shows the product lineup of the 78K0S Kx1 Part Number 78KOS KY1 78KOS KA1 78KOS KB1 Number of pins 16 pins 20 pins 30 pins 1 KB 2 KB 4 KB 2 KB 4KB 128 bytes 256 bytes Internal Flash memory 4 KB 8 KB memory RAM 128 bytes 256 bytes Supply voltage Voo 2 0 to 5 5 VN Minimum instruction execution time 0 20 ws 10 MHz Voo 4 0 to 5 5 V 0 33 ws 6 MHz Voo 3 0 to 5 5 V 0 40 ws 5 MHz Voo 2 7 to 5 5 V 1 0 ws 2 MHz Voo 2 0 to 5 5 V Internal high speed Ring OSC oscillation 8 MHz TYP Crystal ceramic oscillation 1 to 10 MHz System clock oscillation frequency External clock input oscillation 1 to 10 MHz Clock for TMH1 and WDT oscillation frequency Internal low speed R
26. 67 Pull up resistor option register 2 PU2 67 Pull up resistor option register 3 PU3 67 Pull up resistor option register 4 PU4 67 Pull up resistor option register 12 PU12 67 R Receive buffer register 6 RXB6 185 Receive shift register 6 RXS6 185 Preliminary User s Manual U17446EJ1VOUD 361 APPENDIX C REGISTER INDEX Reset control flag register RESF 251 T Transmit buffer register 6 TXB6 185 Transmit shift register 6 TXS6 185 W Watchdog timer enable register WDTE 152 Watchdog timer mode register WDTM 151 362 Preliminary User s Manual U17446EJ1VOUD APPENDIX C REGISTER INDEX C 2 Register Index Symbol A ADCR ADCRH ADM ADS ASICL6 ASIF6 ASIM6 ASIS6 B BRGC6 C CKSR6 CMP01 CMP11 CROOO CRO10 CR80 CRCOO F FLAPH FLAPHC FLAPL FLAPLC FLCMD FLPMC FLW 1 IFO IF1 INTMO INTM1 ISC L LSRCM LVIM LVIS 10 bit A D conversion result register 167 8 bit A D conversion result register 168 A D converter mode register 164 Analog input channel specification register 167 Asynchronous serial interface control register 6 192 Asynchronous serial interface transmission status register 6 189 Asynchronous serial interface operation mode register 6 186 Asynchronous serial interface reception error status register 6 188 Baud rate generator control r
27. AX saddrp AX lt saddrp saddrp AX saddrp AX AX rp AX rp rp AX rp AX AX rp AX erp A byte A CY A byte saddr byte saddr CY lt saddr byte A r A CY Atr A saddr A CY A saddr A addr16 A CY lt A addr16 A HL A CY A HL A HL byte A CY A HL byte A byte A CY GA byte CY saddr byte saddr CY lt saddr byte CY A r A CY A r CY A saddr A CY A saddr CY A addr16 A CY A addr16 CY A HL A CY A HL CY A HL byte A CY lt A HL byte CY Note Only when rp BC DE or HL Remark One instruction clock cycle is one CPU clock cycle fcpu selected by the processor clock control 330 A byte A CY amp A byte saddr byte saddr CY lt saddr byte A r A CY A r A saddr A CY A saddr A laddr16 A CY lt A addr16 A HL A CY A HL A HL byte register PCC DIL Ds orPlT PILED HRP ILDAIT DI oOo HPI RIL DIT PIT DIT ans wo RAR R IAJ Pl oo Rl _ R _ oJ oaoajJ oa A CY A HL byte Preliminary User s Manual U17446EJ 1VOUD Mnemonic Operand A yte CHAPTER 20 Clocks INSTRUCTION SET OVERVIEW Operation A CY amp A byte CY saddr byte saddr CY lt saddr byte
28. Because an interrupt request signal is used to clear the standby mode if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset the standby mode is immediately cleared if set Thus in the STOP mode the normal operation mode is restored after the STOP instruction is executed and then the operation is stopped for 34 ws TYP after an additional wait time for stabilizing the oscillation set by the oscillation stabilization time select register OSTS has elapsed when crystal ceramic oscillation is used Chapter 15 Reset function For an external reset input a low level for 2 ws or more to the RESET pin During reset signal generation the system clock and low speed Ring OSC clock stop oscillating When the RESET pin is used as an input only port pin P34 the 78KOS KB1 is reset if a low level is input to the RESET pin after reset is released by the POC circuit and before the option byte is referenced again The reset status is retained until a high level is input to the RESET pin The LVI circuit is not reset by the internal reset signal of the LVI circuit Timing of reset by overflow of watchdog timer The watchdog timer is also reset in the case of an internal reset of the watchdog timer Preliminary User s Manual U17446EJ1VOUD 379 APPENDIX D LIST OF CAUTIONS Chapter 15 Soft Classification Function
29. No Transfer executed necessary number of times Yes Read ASIF6 TXSF6 0 Completion of transmission processing ASIF6 Asynchronous serial interface transmission status register 6 TXBF6 Bit 1 of ASIF6 transmit buffer data flag TXSF6 Bit 0 of ASIF6 transmit shift register data flag Remark TXB6 Transmit buffer register 6 Preliminary User s Manual U17446EJ1VOUD 203 204 CHAPTER 11 SERIAL INTERFACE UART6 Figure 11 17 shows the timing of starting continuous transmission and Figure 11 18 shows the timing of ending continuous transmission Figure 11 17 Timing of Starting Continuous Transmission TxD6 TXB6 TXS6 TXBF6 TXSF6 Note When ASIF6 is read there is a period in which TXBF6 and TXSF6 1 1 Therefore judge whether writing is enabled using only the TXBF6 bit Remark TxD6 TxD6 pin output INTST6 Interrupt request signal TXB6 Transmit buffer register 6 TXS6 Transmit shift register 6 ASIF6 Asynchronous serial interface transmission status register 6 TXBF6 Bit 1 of ASIF6 TXSF6 Bit 0 of ASIF6 Preliminary User s Manual U17446EJ1VOUD CHAPTER 11 SERIAL INTERFACE UART6 Figure 11 18 Timing of Ending Continuous Transmission TxD6 INTST6 TXB6 TXS6 TXBF6 TXSF6 POWER6 or TXE6 Remark TxD6 INTST6 TXB6 TXS6 ASIF6 TXBF6 TXSF6 POWERS TXE6 TxD6 pin output Interrupt request signal Transmit buffer register 6 Tra
30. e Write 01H to FLPMC writing in this step is invalid Write OFEH inverted value of 01H to FLPMC writing in this step is invalid e Write 01H to FLPMC writing in this step is valid Check the execution result of the specific sequence using bit 0 FRPRERR of PFS Abnormal gt lt 2 gt normal gt lt 5 gt Mode shift is completed Caution Be sure to perform the series of operations described above using the user program at an address where data is not erased nor written Preliminary User s Manual U17446EJ1VOUD 291 CHAPTER 19 FLASH MEMORY Figure 19 20 Example of Shifting to Self Programming Mode Shift to self programming mode lt 1 gt Disable interrupts by setting MKO and MK1 to FFH and executing DI instruction When interrupt function is used lt 2 gt Clear PFS PFCMD A5H FLPMC 01H set value Set value is invalid lt 3 gt FLPMC OFEH inverted set value FLPMC 01H set value Set value is valid Abnormal lt 4 gt Check execution resu FPRERR flag Normal lt 5 gt Termination Caution Be sure to perform the series of operations described above using the user program at an address where data is not erased nor written Remark lt 1 gt to lt 5 gt in Figure 19 20 correspond to lt 1 gt to lt 5 gt in 19 8 4 previous page 292 Preliminary User s Manual U17446EJ1VOUD An example of the program list that shifts the mode t
31. fx 10 MHz 2 For the oscillation stabilization time of the resonator refer to the characteristics of the resonator to be used An example of software coding for setting the option bytes is shown below OPT OSEG AT 0080H DB 10010101B Sets to option byte Low Speed Ring OSC cannot be stopped Selects the high speed Ring OSC as the system clock source Uses RESET pin as bit input only port P 34 The oscillation stabilization time is minimum 27 fx Preliminary User s Manual U17446EJ 1VOUD 267 CHAPTER 19 FLASH MEMORY 19 1 Features The internal flash memory of the 78KO0S KB1 has the following features O Erase write with a single power supply O Capacity 4 KB 8 KB e Erase unit 1 block 256 bytes e Write unit 1 byte O Rewriting method e Rewriting by communication with dedicated flash programmer on board off board programming e Rewriting flash memory by user program self programming O Flash memory write prohibit function supported security function 268 Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY 19 2 Memory Configuration All the blocks can also be erased at once FFFFH Special function resister 256 bytes FFOOH FEFFH Internal high speed RAM 256 bytes FEOOH FDFFH Use prohibited Flash memory 4 8 KB 0000H The 4 8 KB internal flash memory area is divided into 16 32 blocks and can be programmed erased in block units Figure 19 1 Flash Memory M
32. os Selects count clock setting 11 is prohibited Specifies both edges for pulse width detection Setting invalid setting 10 is prohibited Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement See the description of the respective control registers for details Preliminary User s Manual U17446E 1VOUD 103 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 Figure 6 19 Configuration Diagram for Pulse Width Measurement by Free Running Counter 16 bit timer counter 00 OVFO0O TMO0 fxe gt fxp 2 e Selector fxp 2 16 bit timer capture compare TIOOO INTP0 P30 register 010 CR010 gt INTTMO010 Internal bus Figure 6 20 Timing of Pulse Width Measurement Operation by Free Running Counter and One Capture Register with Both Edges Specified lt lt a TMOO count value X0000HX0001H E T1000 pin input CR010 capture value INTTM010 H L L OVF00 a T D1 D0 xt 10000H D1 D2 x D3 D2 xt Note OVFOO must be cleared by software 104 Preliminary User s Manual U17446EJ 1VOUD il i ull g lt CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 2 Measurement of two pulse widths with free running counter When 16 bit timer counter 00 TMOO is operated in free running mode it is possible to simultaneously measure the pulse widths of the two signals i
33. 158 Preliminary User s Manual U17446EJ1VOUD Normal operation CHAPTER 9 WATCHDOG TIMER 9 4 4 Watchdog timer operation in HALT mode when low speed Ring OSC can be stopped by software is selected by option byte The watchdog timer stops counting during HALT instruction execution regardless of whether the operation clock of the watchdog timer is the system clock fx or low speed Ring OSC clock fri After HALT mode is released counting is started again using the operation clock before the operation was stopped At this time the counter is not cleared to 0 but holds its value Figure 9 8 Operation in HALT Mode CPU operation Normal operation HALT Normal operation fcpu fx or fRL Watchdog timer me oe Operating Operation stopped Operating Preliminary User s Manual U17446EJ1VOUD 159 CHAPTER 10 A D CONVERTER 10 1 Functions of A D Converter The A D converter converts an analog input signal into a digital value and consists of up to four channels ANIO to ANI3 with a resolution of 10 bits The A D converter has the following function e 10 bit resolution A D conversion 10 bit resolution A D conversion is carried out repeatedly for one channel selected from analog inputs ANIO to ANI3 Each time an A D conversion operation ends an interrupt request INTAD is generated Figure 10 1 shows the timing of sampling and A D conversion and Table 10 1 shows the sampling time and A D conversion time Figu
34. 19 8 2 Cautions on self programming FUNCTION 0 0 0 eee cette ee eeneeeeeeaeeeseeeeeeeeaeeeeeeaaeeeseeeaeeeenaeeeeneas 283 19 8 3 Registers used for self programming FUNCTION 2 0 eee cece ee ente ee eeereeeeeaeeeeeeaeeesetaaeeeenneeeeneaa 283 19 8 4 Example of shifting normal mode to self programming MOdE cceeeeeeeeenteeeeeeeeeeeeneeeeeeaes 291 19 8 5 Example of shifting self programming mode to normal MOdE cc ceeeeeeeeeenteeeeeeeeeeeeneeeeeenas 294 19 8 6 Example of block erase operation in self programming MOE ee eeeeeeeeenteeeeeeeeeeeneeeeeenes 297 19 8 7 Example of block blank check operation in self programming Mode cescceeeeeteeeeeteeeeeeees 300 19 8 8 Example of byte write operation in self programming MOE eeeceeeeeeeeeeenneeeeeeeeeeeneeeeeenes 303 19 8 9 Example of internal verify operation in self programming MOE eeceeeeenteeeeeeeeeeeenteeeeeeaes 306 19 8 10 Examples of operation when command execution time should be minimized in self programming MOEC cc cceeeceeeeeeeeeeeeeeeeeeeeneeeeeenaeeeseeeeeeesneeeesenaeeeeeenaees 309 19 8 11 Examples of operation when interrupt disabled time should be minimized in self programming MOC eee ceeeeeeeeceenneeeeeeeeeeeeeneeeseeaeeeseeeeeeesneeeenenaeeeseenaees 316 CHAPTER 20 INSTRUCTION SET OVERVIEW 2 ccccceceseesseeeeeeeeeeeeeeeseeeneeeeseeesensseeneeseeeeeeeeeees 327 20 4 OPO ration r a a ar foun
35. 2 1 V 0 1 V i Time Internal reset signal Remark The internal reset signal is active low Preliminary User s Manual U17446EJ1VOUD 253 CHAPTER 16 POWER ON CLEAR CIRCUIT 16 4 Cautions for Power on Clear Circuit In a system where the supply voltage Vop fluctuates for a certain period in the vicinity of the POC detection voltage VPoc the system may be repeatedly reset and released from the reset status In this case the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action lt Action gt After releasing the reset signal wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer and then initialize the ports Figure 16 3 Example of Software Processing After Release of Reset 1 2 e If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage Check reset The reset source power on clear WDT or LVI source Nete2 can be identified by the RESF register Power on clear 8 bit timer H1 can operate on the low speed Ring OSC clock Timer starts set to 50 ms Source fri 480 kHz MAX 2 x compare value 200 53 ms frL Low speed Ring OSC clock oscillation frequency Note 1 lt 50 ms has passed TMIFH1 1 Interrupt request is generated TMIFH1 12 i Initialization a Initialization of ports etc process
36. 2 x 33 151 515 bps Error 151515 153600 1 x 100 1 357 Preliminary User s Manual U17446EJ1VOUD CHAPTER 11 SERIAL INTERFACE UART6 3 Example of setting baud rate Table 11 4 Set Data of Baud Rate Generator Baud Rate fxe 10 0 MHz fxe 8 38 MHz fxe 4 19 MHz bps k Calculated ERR TPS63 to k Calculated ERR TPS63to k Calculated ERR Value Value Value 600 601 601 601 1200 1202 1201 1201 2400 2404 2403 2403 4800 4808 4805 4805 9600 9615 9610 9610 10400 10417 10371 10475 19200 19231 19220 19220 31250 31250 31268 31268 38400 38462 38440 38090 76800 76923 76182 77693 115200 116279 116389 116389 153600 151515 155185 149643 230400 227272 232778 232778 Remark TPS63 to TPS60 Bits 3 to 0 of clock selection register 6 CKSR6 setting of base clock fxcLke k Value set by MDL67 to MDL60 bits of baud rate generator control register 6 BRGC6 k 8 9 10 255 fxP Oscillation frequency of clock to peripheral hardware ERR Baud rate error Preliminary User s Manual U17446EJ1VOUD 213 CHAPTER 11 SERIAL INTERFACE UART6 4 Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below Caution Make sure that the baud rate error during reception is within the permissible error range by using the calculation expression shown b
37. CHAPTER 10 A D CONVERTER Figure 10 3 Format of A D Converter Mode Register ADM Address FF80H_ After reset OOH R W Symbol lt 7 gt 6 5 4 3 2 1 lt 0 gt ADCS A D conversion operation control 0 Stops conversion operation qos Starts conversion operation Reference Voltage Range 2 Note AVREF gt 4 5V Sampling Time 12 fxp Conversion Time 4 36 fxP fxe 8 MHz fxe 10 MHz Sampling Time 1 5 us Conversion Time 4 5 us Sampling Time 1 2 us Conversion Time 4 3 6 us AVREF gt 2 85 V 24lfxP 48 fxP 3 0 us 6 0 us Setting prohibited 2 4 us Setting prohibited 4 8 us AVREF gt 2 7 V 48 fxP 72 fxp Setting prohibited 6 0 us Setting prohibited 9 0 us Setting prohibited 4 8 us Setting prohibited 7 2 us AVREF gt 2 7V 88 fxp 112 fxp 11 0 us 14 0 us Setting prohibited 8 8 us Setting prohibited 11 2 ws AVrREF gt 45V 24 lfxp 72 fxp 3 0 us 9 0 us 2 4 US 7 2 US AVrREF gt 2 85 V 48 fxP 96 fxP 6 0 us 12 0 us 4 8 us 9 6 us AVREF gt 2 7 V 96 fxP 144 fxp 12 0 us 18 0 us Setting prohibited 9 6 us Setting prohibited 14 4 us AVrREF gt 2 7V 176 fxe 224 fxp 22 0 us 28 0 us 17 6 us 22 4 us ADCE Comparator operation control
38. CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 6 3 Registers to Control 16 Bit Timer Event Counter 00 The following six types of registers are used to control 16 bit timer event counter 00 16 bit timer mode control register 00 TMC00 e Capture compare control register 00 CRC00 16 bit timer output control register 00 TOC00 e Prescaler mode register 00 P RM00 e Port mode register 3 PM3 Port register 3 P3 1 16 bit timer mode control register 00 TMC00 This register sets the 16 bit timer operating mode the 16 bit timer counter 00 TM00 clear mode and output timing and detects an overflow TMCO0O0 is set by a 1 bit or 8 bit memory manipulation instruction Generation of reset signal sets the value of TMC00 to OOH Caution 16 bit timer counter 00 TM00 starts operation at the moment TMC002 and TMC003 operation stop mode are set to a value other than 0 0 respectively Set TMC002 and TMC003 to 0 0 to stop the operation 90 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 Figure 6 5 Format of 16 Bit Timer Mode Control Register 00 TMC00 Address FF60H After reset OOH R W 5 4 3 2 1 lt 0 gt TMCOO Lo o 0 o mmo TMC002 TMC001 OVF00 Symbol 7 6 TMC003 TMC002 TMCO001 Operating mode and clear mode selection Operation stop TMOO cleared to 0 TO00 inversion timing selection No change Interrupt request generation Not generated Free running
39. Oscillation frequency of system clock 3 Figures in parentheses apply to operation at fr 480 kHz MAX fx 10 MHz The operation mode of the watchdog timer WDT is switched according to the option byte setting of the on chip low speed Ring OSC oscillator as shown in Table 9 2 148 Preliminary User s Manual U17446EJ1VOUD CHAPTER 9 WATCHDOG TIMER Table 9 2 Option Byte Setting and Watchdog Timer Operation Mode Option Byte Setting Low Speed Ring OSC Cannot Be Stopped Low Speed Ring OSC Can Be Stopped by Software Watchdog timer clock Fixed to fri 1 e Selectable by software fx fr or stopped source e When reset is released frL Operation after reset Operation starts with the maximum interval Operation starts with the maximum interval 2 fat 2 fat Operation mode The interval can be changed only once The clock selection interval can be changed only selection once Features The watchdog timer cannot be stopped The watchdog timer can be stopped Notes 1 As long as power is being supplied low speed Ring OSC oscillation cannot be stopped except in the reset period 2 The conditions under which clock supply to the watchdog timer is stopped differ depending on the clock source of the watchdog timer lt 1 gt If the clock source is fx clock supply to the watchdog timer is stopped under the following conditions e When fx is stopped e In HALT STOP mode e During oscillation stabilizat
40. Other than above Setting prohibited Notes 1 If PPCC 01H the clock fxe supplied to the peripheral hardware is fx 2 2 If PPCC 02H the clock fxe supplied to the peripheral hardware is fx 2 Preliminary User s Manual U17446EJ1VOUD CHAPTER 5 CLOCK GENERATORS The fastest instruction of the 78KOS KB1 is executed in two CPU clocks Therefore the relationship between the CPU clock fceu and the minimum instruction execution time is as shown in Table 5 2 Table 5 2 Relationship Between CPU Clock and Minimum Instruction Execution Time CPU Clock fcpu Minimum Instruction Execution Time 2 fcru High speed Ring OSC clock Crystal ceramic oscillation clock at 8 0 MHz TYP or external clock input at 10 0 MHz Note The CPU clock high speed Ring OSC clock crystal ceramic oscillation clock or external clock input is selected by the option byte 2 Low speed Ring OSC mode register LSRCM This register is used to select the operation mode of the low speed Ring OSC oscillator 240 kHz TYP This register is valid when it is specified by the option byte that the low speed Ring OSC oscillator can be stopped by software If it is specified by the option byte that the low speed Ring OSC oscillator cannot be stopped by software setting of this register is invalid and the low speed Ring OSC oscillator continues oscillating In addition the source clock of WDT is fixed to the low speed Ring OSC oscilla
41. The wait time after the STOP mode is released does not include the time from the release of the STOP mode to the start of clock oscillation a in the figure below regardless of whether STOP mode was released by Reset signal generation or interrupt generation The oscillation stabilization time that elapses on power application or after release of reset is selected by the option byte For details refer to CHAPTER 18 OPTION BYTE Crystal ceramic oscillator When using the crystal ceramic oscillator wire as follows in the area enclosed by the broken lines in Figure 5 6 to avoid an adverse effect from wiring capacitance e Keep the wiring length as short as possible e Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows e Always make the ground point of the oscillator capacitor the same potential as VSS Do not ground the capacitor to a ground pattern through which a high current flows e Do not fetch signals from the oscillator Chapter 6 16 bit timer event counter 00 TMOO 16 bit timer counter 00 Even if TMOO is read the value is not captured by CRO10 During TMOO is read the count clock is stopped CROOO 16 bit timer capture compare register 000 Set CR000 to other than OOOOH in the clear amp start mode entered on match between TMOO and CROOO This means a
42. a ela 03FDH A D conversion result i ADCR 3 Riig 0003H 2c sl eee 0002H liae a Ca 0001H a a ee ea 0000H 1 1 3 2 5 3 2043 1022 2045 1023 2047 1 2048 1024 2048 1024 2048 1024 2048 1024 2048 1024 2048 Input voltage AVrer Preliminary User s Manual U17446EJ1VOUD 171 CHAPTER 10 A D CONVERTER 10 4 3 A D converter operation mode The operation mode of the A D converter is the select mode One channel of analog input is selected from ANIO to ANI3 by the analog input channel specification register ADS and A D conversion is executed 1 A D conversion operation By setting bit 7 ADCS of the A D converter mode register ADM to 1 the A D conversion operation of the voltage which is applied to the analog input pin specified by the analog input channel specification register ADS is started When A D conversion has been completed the result of the A D conversion is stored in the A D conversion result register ADCR ADCRH and an interrupt request signal INTAD is generated Once the A D conversion has started and when one A D conversion has been completed the next A D conversion operation is immediately started The A D conversion operations are repeated until new data is written to ADS If ADM or ADS is written during A D conversion the A D conversion operation under execution is stopped and restarted from the beginning If O is written to ADCS during A D conversion A D conversion is immediately stopped At thi
43. address 44 Preliminary User s Manual U17446EJ1VOUD CHAPTER 3 CPU ARCHITECTURE 3 4 4 Register addressing Function A general purpose register is accessed as an operand The general purpose register to be accessed is specified with the register specify code and functional name in the instruction code Register addressing is carried out when an instruction with the following operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the instruction code Operand format X A C B E D L H AX BC DE HL r and rp can be described with absolute names RO to R7 and RPO to RP3 as well as function names X A C B E D L H AX BC DE and HL Description example MOV A C When selecting the C register for r Instruction code 0 0 0 0 1 0 1 0 Register specify code INCW DE When selecting the DE register pair for rp Instruction code 1 0 0 0 1 0 0 0 Register specify code Preliminary User s Manual U17446EJ1VOUD 45 CHAPTER 3 CPU ARCHITECTURE 3 4 5 Register indirect addressing Function The memory is addressed with the contents of the register pair specified as an operand The register pair to be accessed is specified with the register pair specify code in the instruction code This addressing can be carried out for all the memory spaces Operand format m S Description example MOV A DE When select
44. amp start mode at the valid edge of the T1000 pin or free running mode is selected when the set value of CR000 is FFFFH and the TMO00 value changes from FFFFH to 0000H the OVF00 flag is set to 1 Even if the OVFOO flag is cleared before the next count clock is counted before TM00 becomes 0001H after the occurrence of a TMO00 overflow the OVFO00 flag is re set newly and clear is disabled The capture operation is performed at the fall of the count clock An interrupt request input INTTMOn0 however occurs at the rise of the next count clock 16 bit timer counter 00 CR000 16 bit timer capture compare register 000 CRO10 16 bit timer capture compare register 010 Preliminary User s Manual U17446E 1VOUD 91 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 92 2 Capture compare control register 00 CRC00 This register controls the operation of the 16 bit capture compare registers CRO00 CR010 CRCO00 is set by a 1 bit or 8 bit memory manipulation instruction Generation of reset signal sets the value of CRC00 to OOH Figure 6 6 Format of Capture Compare Control Register 00 CRC00 Address FF 62H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CRC002 CR010 operating mode selection 0 Operate as compare register 1 Operate as capture register CRC001 CR000 capture trigger selection 0 Capture on valid edge of T1010 pin Note 1 Capture on valid edge of T1000 pin by reverse phase CRC000 CR000 operating mode s
45. oOjejejejejojoj j o ej o ololol lol oj o o lej jolejo el oj e 0 Other than above Setting prohibited Note Retained only after a reset by LVI Caution Bits 4 to 7 must be set to 0 258 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 17 LOW VOLTAGE DETECTOR 17 4 Operation of Low Voltage Detector The low voltage detector can be used in the following two modes e Used as reset Compares the supply voltage Voo and detection voltage Vivi and generates an internal reset signal when Voo lt Vivi and releases internal reset when Vpop gt Vivi e Used as interrupt Compares the supply voltage Voo and detection voltage Vivi and generates an interrupt signal INTLVI when Vpop lt VLvi The operation is set as follows 1 When used as reset e When starting operation lt l gt Mask the LVI interrupt LVIMK 1 Set the detection voltage using bits 3 to 0 LVIS3 to LVISO of the low voltage detection level select register LVIS Set bit 7 LVION of LVIM to 1 enables LVI operation Use software to instigate a wait of at least 0 2 ms Wait until supply voltage VoD gt detection voltage Vivi at bit 0 LVIF of LVIM is confirmed Set bit 1 LVIMD of LVIM to 1 generates internal reset signal when supply voltage Vno lt detection voltage Vivi Figure 17 4 shows the timing of generating the internal reset signal of the low voltage detector Numbers lt
46. p 173 operations It is no problem if the order of lt 1 gt and lt 2 gt is reversed p 173 L lt 1 gt can be omitted However ignore the data resulting from the first p 173 conversion after lt 4 gt in this case The period from lt 5 gt to lt 8 gt differs from the conversion time set using bits 5 to p 173 3 FR2 to FRO of ADM The period from lt 7 gt to lt 8 gt is the conversion time set using FR2 to FRO Preliminary User s Manual U17446EJ1VOUD 373 APPENDIX D LIST OF CAUTIONS Chapter 10 Hard Classification Soft 374 Hard Function A D Converter Details of Function Operating current in STOP mode Cautions The A D converter stops operating in the STOP mode At this time the operating current can be reduced by clearing bit 7 ADCS and bit 0 ADCE of the A D converter mode register ADM to 0 9 20 p 176 O Input range of ANIO to ANI3 Observe the rated range of the ANIO to ANI3 input voltage If a voltage of AVreF or higher and AVss or lower even in the range of absolute maximum ratings is input to an analog input channel the converted value of that channel becomes undefined In addition the converted values of the other channels may also be affected p 176 O Conflicting operations ADCR ADCRH read has priority After the read operation the new conversion result is written to ADCR ADCRH p 176 ADM or ADS write has priority ADCR A
47. restarts WDT HALT Self programming is started MOV A PFS MOV CmdStatus A Execution result is stored in variable CmdStatus 0 normal termination other than 0 abnormal termination END Preliminary User s Manual U17446EJ1VOUD 299 CHAPTER 19 FLASH MEMORY 19 8 7 Example of block blank check operation in self programming mode An example of the block blank check operation in self programming mode is explained below lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt 6 gt lt 7 gt lt 8 gt lt Q gt Set 04H block blank check to the flash program command register FLCMD Set the number of block for which a blank check is performed to flash address pointer H FLAPH Set flash address pointer L FLAPL to OOH Write the same value as FLAPH to the flash address pointer H compare register FLAPHC Set the flash address pointer L compare register FLAPLC to FFH Clear the flash status register PFS Write ACH to the watchdog timer enable register WDTE clear and restart the watchdog timer counter Execute the HALT instruction then start self programming Execute an instruction immediately after the HALT instruction if self programming has been executed Check if a self programming error has occurred using bit 1 VCERR and bit 2 WEPRERR of PFS Abnormal lt 10 gt Normal lt 11 gt lt 10 gt Block blank check is abnormally terminated lt 11 gt Block blank check is normally
48. 00 PRMO00 is required to write to OSPT00 successively 6 When the TOEOO is 0 set the TOE00 LVS00 and LVROO at the same time with the 8 bit memory manipulation instruction When the TOEOO is 1 the LVS00 and LVROO can be set with the 1 bit memory manipulation instruction Preliminary User s Manual U17446E 1VOUD 93 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 4 Prescaler mode register 00 PRM00 This register is used to set the 16 bit timer counter 00 TMOO count clock and the T1000 T1010 pin input valid edges PRMOO is set by a 1 bit or 8 bit memory manipulation instruction Generation of reset signal sets the value of PRMOO to 00H Figure 6 8 Format of Prescaler Mode Register 00 PRMO00 Address FF61H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PRMOO ES110 ES100 ES010 ES000 ee e PRMOO1 PRMOOO ES110 ES100 T1010 pin valid edge selection Falling edge Rising edge Setting prohibited Both falling and rising edges T1000 pin valid edge selection Falling edge Rising edge Setting prohibited Both falling and rising edges Count clock selection fxr 10 MHz fxe 2 2 5 MHz fxe 2 39 06 kHz T1000 pin valid edge Remarks 1 fxr Oscillation frequency of clock supplied to peripheral hardware 2 fxe 10 MHz Note The external clock requires a pulse longer than two cycles of the internal count clock fxr Preliminary User s Manual U17446EJ 1VOUD CHAPTER
49. 1 PCu lt 00000000 addr5 1 PC lt 00000000 addr5 SP SP 2 PCH lt SP 1 PCL amp SP SP SP 2 PCH lt SP 1 PCL amp SP PSW lt SP 2 SP SP 3 SP 1 PSW SP eSP 1 SP 1 lt rpn SP 2 lt rpi SP amp SP 2 PSW amp SP SP SP 1 rp rph lt SP 1 rp lt lt SP SP amp SP 2 SP AX SP AX AX SP AX lt SP laddr16 PC addrl6 addr16 PC amp PC 2 jdisp8 AX PCHA PCLe X saddr16 PC PC 2 jdisp8 if CY 1 saddr16 PC PC 2 jdisp8 if CY 0 saddr16 PC PC 2 jdisp8 if Z 1 saddr16 2 4 4 6 8 6 6 6 6 6 6 6 6 PC amp PC 2 jdisp8 if Z 0 saddr bit addr16 ps Oo PC PC 4 jdisp8 if saddr bit 1 Sfr bit addr16 bh oO A bit addr16 PC amp PC 3 jdisp8 if A bit 1 PSW bit addr16 PC PC 4 jdisp8 if PSW bit 1 saddr bit addr16 PC PC 4 jdisp8 if saddr bit 0 Sfr bit addr16 PC PC 4 jdisp8 if sfr bit 0 A bit addr16 jd jd jd jd jd PC PC 4 jdisp8 if sfr bit 1 jd jd jd jd jd PC amp PC 3 jdisp8 if A bit 0 PSW bit addr16 PC PC 4 jdisp8 if PSW bit 0 B addr16 B B 1 then PC lt PC 2 jdisp8 if B 0 C addr16 C lt C 1 then PC PC 2 jdisp8 if C 0 saddr addr16 WININT
50. 1 gt to lt 6 gt in this figure correspond to lt 1 gt to lt 6 gt above Cautions 1 lt 1 gt must always be executed When LVIMK 0 an interrupt may occur immediately after the processing in lt 3 gt 2 If supply voltage VoD gt detection voltage Vivi when LVIM is set to 1 an internal reset signal is not generated e When stopping operation Either of the following procedures must be executed e When using 8 bit memory manipulation instruction Write 00H to LVIM e When using 1 bit memory manipulation instruction Clear LVIMD to 0 and LVION to 0 in that order Preliminary User s Manual U17446E 1VOUD 259 CHAPTER 17 LOW VOLTAGE DETECTOR Figure 17 4 Timing of Low Voltage Detector Internal Reset Signal Generation Supply voltage Vop LVI detection voltage Vivi POC detection voltage Voc 2 7 V LVIMK flag set by software LVION flag set by software Not cleared LVIF flag H 1 lt 5 gt Note 2 n LVIMD flag ii i H set by software n Not cleared Not cleared N LVIRF flag e 3 LVI reset signal Cleared by software Cleared by software POC reset signal Internal reset signal Notes 1 The LVIMK flag is setto 1 by reset signal generation 2 The LVIF flag may be set 1 3 LVIRF is bit 0 of the reset control flag register RESF For details of RESF refer to CHAPTER 15 RESET FUNCTION Remark lt 1l gt to lt 6 gt in Figure 17 4 above correspond t
51. 1 pulse count operation cannot be performed when this register is used as an external event counter However in the free running mode and in the clear amp start mode using the valid edge of T1000 pin if CROOO is set to OOOOH an interrupt request INTTMO000 is generated when CROO0 changes from 0000H to 0001H following overflow FFFFH If the new value of CROOO is less than the value of 16 bit timer counter 0 TMOO TMOO continues counting overflows and then starts counting from 0 again If the new value of CROO0 is less than the old value therefore the timer must be reset to be restarted after the value of CR000 is changed The value of CROO0 after 16 bit timer event counter 00 has stopped is not guaranteed The capture operation may not be performed for CROOO set in compare mode even if a capture trigger is input When P31 is used as the input pin for the valid edge of T1010 it cannot be used as a timer output TO00 Moreover when P31 is used as TOOO it cannot be used as the input pin for the valid edge of T1010 Preliminary User s Manual U17446EJ1VOUD 367 APPENDIX D LIST OF CAUTIONS Chapter 6 Hard Classification Soft Hard Soft Soft Hard Function 16 bit timer event counter 00 Details of Function CROOO 16 bit timer capture compare register 000 Cautions If the register read period and the input of the
52. 1 when executing the self programming command Format of flash programming mode control register FLPMC Note the following when setting the self programming mode e If an interrupt occurs during self programming the interrupt request flag is set 1 and interrupt servicing is performed after the self programming mode is released To avoid this operation disable interrupt servicing by setting MKO and MK1 to FFH and executing the DI instruction during self programming or before a mode is shifted from the normal mode to the self programming mode with a specific sequence No instructions can be executed while a self programming command is being executed Therefore clear and restart the watchdog timer counter in advance so that the watchdog timer does not overflow during self programming Refer to Table 19 11 for the time taken for the execution of self programming e f the supply voltage drops or the reset signal is input while the flash memory is being written or erased writing erasing is not guaranteed When the oscillator or the external clock is selected as the main clock a wait time of 16 ws is required from setting FLSPM to 1 to execution of the HALT instruction PFCMD Flash protect command register Disable interrupt servicing by setting MKO and MK1 to FFH and executing the DI instruction while the specific sequence is under execution FLAPH and FLAPL Flash address p
53. 152 generated If a 1 bit memory manipulation instruction is executed for WDTE an internal p 152 O reset signal is generated 372 Preliminary User s Manual U17446EJ1VOUD APPENDIX D LIST OF CAUTIONS 8 18 5 Function Details of Cautions g Function T n amp O R Watchdog When low speed In this mode operation of the watchdog timer cannot be stopped even during p 153 2 I timer Ring OSC cannot STOP instruction execution For 8 bit timer H1 TMH1 a division of the low be stopped is speed Ring OSC clock can be selected as the count source so clear the selected by watchdog timer using the interrupt request of TMH1 before the watchdog timer option byte overflows after STOP instruction execution If this processing is not performed an internal reset signal is generated when the watchdog timer overflows after STOP instruction execution When low speed In this mode watchdog timer operation is stopped during HALT STOP p 155 Ring OSC can be instruction execution After HALT STOP mode is released counting is started stopped by again using the operation clock of the watchdog timer set before HALT STOP software is instruction execution by WDTM At this time the counter is not cleared to 0 selected by but holds its value option byte 2 5 AD Sampling time The above sa
54. 6 4 3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the T1000 pin and T1010 pin using 16 bit timer counter 00 TMO0 There are two measurement methods measuring with TMOO used in free running mode and measuring by restarting the timer in synchronization with the edge of the signal input to the T1000 pin When an interrupt occurs read the valid value of the capture register check the overflow flag and then calculate the necessary pulse width Clear the overflow flag after checking it The capture operation is not performed until the signal pulse width is sampled in the count clock cycle selected by prescaler mode register 00 PRMOO and the valid level of the T1000 or T1010 pin is detected twice thus eliminating noise with a short pulse width Figure 6 17 CR010 Capture Operation with Rising Edge Specified Count clock l TMoo N 3 N 2 N 1 XN K Net Y Rising edge detection O CCC I CR010 X N INTTM010 l Setting The basic operation setting procedure is as follows lt l gt Setthe CRCO0O register see Figures 6 18 6 21 6 23 and 6 25 for the set value lt 2 gt Setthe count clock by using the PRMO0 register lt 3 gt Setthe TMCOO register to start the operation see Figures 6 18 6 21 6 23 and 6 25 for the set value Caution To use two capture registers set the T1000 and T1010 pins Remarks 1 For the setting of the T1000 or
55. 80 7 3 Register Controlling 8 Bit Timer 80 8 bit timer 80 is controlled by 8 bit timer mode control register 80 TMC80 1 8 bit timer mode control register 80 TMC80 This register is used to enable or stop the operation of 8 bit timer counter 80 TM80 and to set the count clock of TM80 This register is set by using a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears TMC80 to 00H Figure 7 4 Format of 8 Bit Timer Mode Control Register 80 TMC80 Address FFCCH After reset OOH R W Symbol lt 7 gt 6 5 4 3 2 1 0 TCE80 Control of operation of TM80 0 Stop operation clear TM80 to 00H 1 Enable operation TCL801 TCL800 Selection of count clock of 8 bit timer 80 fxe 8 0 MHz fxr 10 0 MHz 125 kHz 156 3 kHz 31 25 kHz 39 06 kHz 7 81 kHz 9 77 kHz 0 12 kHz 0 15 kHz Cautions 1 Be sure to set TMC80 after stopping the timer operation 2 Be sure to clear bits 0 and 6 to 0 Remark fxr Oscillation frequency of clock to peripheral hardware Preliminary User s Manual U17446EJ1VOUD 129 CHAPTER 7 8 BIT TIMER 80 7 4 Operation of 8 Bit Timer 80 7 4 1 Operation as interval timer When 8 bit timer 80 operates as an interval timer it can repeatedly generate an interrupt at intervals specified by the count value set in advance to 8 bit compare register 80 CR80 To use 8 bit timer 80 as an interval timer make the following setting lt 1 gt Disable the opera
56. BNZ RET MKO 11111111B MK1 11111111B FS 00H FCMD 0A5H LPMC 01H LPMC 0FEH my oF y Y LPMC 01H A PFS A 00H ModeOnLoop Masks all interrupts PFCMD register control FLPMC register control sets value FLPMC register control inverts set value Sets self programming mode via FLPMC register control sets value Checks completion of write to specific registers Repeats the same processing when an error occurs Processing to shift to normal MOV MOV MOV PFS 00H PFCMD 0A5H FLPMC 00H PFCMD register control FLPMC register control sets value Preliminary User s Manual U17446EJ1VOUD 319 320 MOV MOV MOV CMP BNZ MOV MOV EI RET FLPMC 0FFH FLPMC 00H A PFS A 00H SModeOff MKO INT_MKO MK1 INT_MK1 CHAPTER 19 FLASH MEMORY FLPMC register control inverts set value Sets normal mode via FLPMC register control sets value Checks completion of write to specific registers Repeats the same processing when an error occurs Restores interrupt mask flag Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY 2 Write to internal verify lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt 6 gt lt 7 gt lt 8 gt lt Q gt Specification of source data for write Specification of byte write command lt 1 gt to lt 4 gt in 19 8 8 Mode is shifted from normal mode to
57. D78F 9232MC T 5A4 A 30 pin plastic SSOP Standard HP D78F 9232MC S 5A4 A 30 pin plastic SSOP Standard UP D78F 9232MC R 5A4 A 30 pin plastic SSOP Standard UP D78F 9234MC T 5A4 30 pin plastic SSOP Standard UP D78F 9234MC S 5A4 30 pin plastic SSOP Standard UPD78F9234MC R 5A4 30 pin plastic SSOP Standard UP D78F 9234MC T 5A4 A 30 pin plastic SSOP Standard HP D78F 9234MC S 5A4 A 30 pin plastic SSOP Standard UP D78F 9234MC R 5A4 A 30 pin plastic SSOP Standard Remark The uwPD78F 9232MC xx 5A4 A and 78F9234MC xx 5A4 A are lead free products Xx 7T S R Please refer to Quality Grades on NEC Semiconductor Devices Document No C11531E published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications The 78K0S KB1 standard grade products are further classified as follows T General management S Management based on individual contract R Management for automotive accessories 16 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 1 OVERVIEW 1 4 Pin Configuration Top View 30 pin plastic SSOP P03 o 1 30 0 P120 P02 0 2 O AVss P01 O 3 O AVREF P00 o 4 27 0 P20 ANI0 P123 0 5 P21 ANI1 Vss P22 ANI2 Voo O P23 ANI3 P121 X1 0 18 O P130 P122 X2 0 19 22 0 P47 P34 RESET o 1 10 21 o P46 P33 0o 11 20 0 P45 P32 0 12 19 o P44 RxD6 P31 T1010 TOOO INTP2 O
58. H Tet cks12 cxstt cks10 Toev TOEN compare register compare register t 11 CMP11 01 CMP01 3 2 T Decoder Interrupt Output generator controller fxP fxp 2 gt fxp 24 g ih 8 bit timer fxp 2 3 counter H1 fxe 212 e fri 2 PWM mode signal Timer H enable signal M gt INTTMH1 TH YJWIL LIG 8 8 Y3LdYHO CHAPTER 8 8 BIT TIMER H1 1 8 bit timer H compare register 01 CMP01 This register can be read or written by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH Figure 8 2 Format of 8 Bit Timer H Compare Register 01 CMP01 Address FFOEH After reset OOH R W Symbol 7 6 5 4 3 2 1 0 Caution CMPO1 cannot be rewritten during timer count operation 2 8 bit timer H compare register 11 CMP 11 This register can be read or written by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH Figure 8 3 Format of 8 Bit Timer H Compare Register 11 CMP11 Address FFOFH_ After reset OOH R W Symbol 7 6 5 4 3 2 1 0 CMP11 can be rewritten during timer count operation If the CMP11 value is rewritten during timer operation transferring is performed at the timing at which the count value and CMP11 value match If the transfer timing and writing from CPU to CMP11 conflict transfer is not performed Caution In the PWM output mode be sure to set CMP11 when starting the timer count operation TMHE1
59. Lvsoo Lvroo Tocoo1 TOEOO OSPTO0O One shot pulse output trigger control via software 0 No one shot pulse output trigger 1 One shot pulse output trigger OSPEOO One shot pulse output operation control 0 Successive pulse output mode 1 One shot pulse output mode TOC004 Timer output F F control using match of CR010 and TMOO0 0 Disables inversion operation 1 Enables inversion operation LVS00 LVROO Timer output F F status setting 0 0 No change 0 1 Timer output F F reset 0 1 0 Timer output F F set 1 1 1 Setting prohibited TOCO001 Timer output F F control using match of CR000 and TM00 0 Disables inversion operation 1 Enables inversion operation TOE0O Timer output control 0 Disables output output fixed to level 0 1 Enables output Note The one shot pulse output mode operates correctly only in the free running mode and the mode in which clear amp start occurs at the TI000 pin valid edge In the mode in which clear amp start occurs on a match between TMO0 and CR000 one shot pulse output is not possible because an overflow does not occur Cautions 1 Timer operation must be stopped before setting other than OSPTOO 2 If LVS00 and LVROO are read 0 is read 3 OSPT00 is automatically cleared after data is set so 0 is read 4 Do not set OSPT00 to 1 other than in one shot pulse output mode 5 A write interval of two cycles or more of the count clock selected by prescaler mode register
60. Manual U17446EJ1VOUD 75 CHAPTER 5 CLOCK GENERATORS Figure 5 7 shows examples of incorrect resonator connection Figure 5 7 Examples of Incorrect Resonator Connection 1 2 a Too long wiring of connected circuit b Crossed signal lines PORT Vss x1 X2 Vss X1 X2 c Wiring near high fluctuating current d Current flowing through ground line of oscillator Potential at points A B and C fluctuates r High current O T High current TIT 76 Preliminary User s Manual U17446EJ1VOUD CHAPTER 5 CLOCK GENERATORS Figure 5 7 Examples of Incorrect Resonator Connection 2 2 e Signals are fetched Vss X1 X2 5 4 3 External clock input circuit This circuit supplies a clock from an external IC to the X1 pin If external clock input is selected by the option byte as the system clock source the X2 pin can be used as an I O port pin For details of the option byte refer to CHAPTER 18 OPTION BYTE For details of I O ports refer to CHAPTER 4 PORT FUNCTIONS 5 4 4 Prescaler The prescaler divides the clock fx output by the system clock oscillator to generate a clock fxP to be supplied to the peripheral hardware It also divides the clock to peripheral hardware fxe to generate a clock to be supplied to the CPU Remark The clock output by the oscillator selected by the option byte high speed Ring OSC oscillator crystal ceramic oscillator or ext
61. Number of Bits Manipulated After Reset Simultaneously 1 Bit 8 Bits 16 Bits a Port register 0 Port register 2 Port register 3 Port register 4 Port register 12 Port register 13 8 bit timer H compare register 01 8 bit timer H compare register 11 16 bit Multiplication result storage register L Undefined lt j lt e 7 e2 4 42 42 4 2 16 bit Multiplication result storage register H 16 bit timer counter 00 Note 2 16 bit timer capture compare register 000 anoa 16 bit timer capture compare register 010 ane 10 bit A D conversion result register Note Undefined 8 bit A D conversion result register Port mode register 0 Port mode register 2 Port mode register 3 Port mode register 4 Port mode register 12 Pull up resistance option register 0 Pull up resistance option register 2 Pull up resistance option register 3 Pull up resistance option register 4 lt azfjye2 e2 2 e 2 2 2 a Pull up resistance option register 12 67H 9AH OOH te 3 Watchdog timer mode register Watchdog timer enable register Low voltage detect register Low voltage detection level select register OOH te 4 00H Reset control flag register lt z2 j lt e 7 2 2 7 2 2 2 Low speed Ri
62. P120 to P123 constitute a 4 bit I O port port 12 Each bit of this port can be set to the input or output mode by using port mode register 12 PM12 An on chip pull up resistor can be connected to P120 and P123 by using pull up resistor option register 12 PU12 P121 and P122 also function as the X1 and X2 pins respectively For settings of alternate function refer to CHAPTER 18 OPTION BYTE Caution The P121 X1 and P122 X2 pins are pulled down during reset 2 2 6 P130 Port 13 This is a 1 bit output only port 2 2 7 RESET This pin inputs an active low system reset signal 24 Preliminary User s Manual U17446EJ1VOUD CHAPTER 2 PIN FUNCTIONS 2 2 8 X1 and X2 These pins connect an oscillator to oscillate the X1 input clock X1 and X2 also function as the P121 and P122 pins respectively For settings of alternate function refer to CHAPTER 18 OPTION BYTE Supply an external clock to X1 Caution The P121 X1 and P122 X2 pins are pulled down during reset 2 2 9 AVREF This pin inputs a reference voltage to the internal A D converter When the A D converter is not used connect this pin to Vpp 2 2 10 AVss This is the A D converter ground potential pin Even when the A D converter is not used always use this pin with the same potential as the Vss pin 2 2 11 Voo This is the positive power supply pin 2 2 12 Vss This is the ground pin Preliminary User s Manual U17446EJ1VOUD 25 CHAPTER 2 PIN FUNCTIONS 2 3 Pin I O C
63. P122 pins the conditions under which the X1 and X2 pins can be used differ depending on the selected system clock source 1 High speed Ring OSC clock P121 and P122 can be used as I O port pins 2 Crystal ceramic oscillation clock The X1 and X2 pins cannot be used as I O port pins because they are used as clock input pins 3 External clock input Because the X1 pin is used as an external clock input pin P121 cannot be used as an I O port pin Remark x don tcare RMCE Control of RESET pin 1 RESET pin is used as is gee RESET pin is used as input port pin P34 Note When clearing the RMCE to 0 connect pull up resistor Caution If a low level is input to the RESET pin after reset is released by the power on clear function and before the option byte is referenced again the 78K0S KB1 is reset and the status is held until a high level is input to the RESET pin Preliminary User s Manual U17446EJ 1VOUD CHAPTER 18 OPTION BYTE Figure 18 2 Format of Option Byte 2 2 DEFOSTS1 DEFOSTSO Oscillation stabilization time on power application or after reset release 0 2 fx 102 4 us 27 fx 409 6 us 1 0 2 fx 3 27 ms 1 2 fx 13 1 ms Caution The setting of this option is valid only when the crystal ceramic oscillation clock is selected as the system clock source No wait time elapses if the high speed Ring OSC or external clock input is selected as the system clock source Remarks 1
64. ROM and RAM capacities Program Memory Flash Memory Memory Internal High Speed RAM Part number UPD78F 9232 256 bytes uP D78F 9234 256 bytes O On chip power on clear POC circuit and low voltage detector LVI O On chip watchdog timer operable on internal low speed Ring OSC clock O I O ports 26 O Timer 4 channels e 16 bit timer event counter 1 channel e 8 bit timer 2 channels e Watchdog timer 1 channel O Serial interface UART LIN Local Interconnect Network bus supported 1 channel O On chip multiplier 8 bits x 8 bits 16 bits O 10 bit resolution A D converter 4 channels O Supply voltage Voo 2 0 to 5 5 VN O Operating temperature range Ta 40 to 85 C Note Use this product in a voltage range of 2 2 to 5 5 V because the detection voltage Vpoc of the power on clear POC circuit is 2 1 V 0 1 V 1 2 Application Fields O Automotive electronics e System control of body instrumentation system Such as power windows and keyless entry reception e Sub microcontroller of control system O Household appliances e Electric toothbrushes e Electric shavers O Toys O Industrial equipment e Sensor and switch control e Power tools Preliminary User s Manual U17446EJ 1VOUD 15 1 3 Ordering Information CHAPTER 1 OVERVIEW Part Number Package Quality Grade UPD78F 9232MC T 5A4 30 pin plastic SSOP Standard UP D78F 9232MC S 5A4 30 pin plastic SSOP Standard UP D78F9232MC R 5A4 30 pin plastic SSOP Standard UP
65. SBRT6 bit to 1 make sure that bit 7 POWER6 and bit 5 RXE6 of ASIM6 1 Moreover after setting the SBRT6 bit to 1 do not clear the SBRT6 bit to 0 before the SBF reception ends an interrupt request signal is generated The read value of the SBRT6 bit is always 0 SBRT6 is automatically cleared to 0 after SBF reception has been correctly completed Before setting the SBTT6 bit to 1 make sure that bit 7 POWER6 and bit 6 TXE6 of ASIM6 1 Moreover after setting the SBTT6 bit to 1 do not clear the SBTT6 bit to 0 before the SBF transmission ends an interrupt request signal is generated The read value of the SBTT6 bit is always 0 SBTT6 is automatically cleared to 0 at the end of SBF transmission Before rewriting the DIR6 and TXDLV6 bits clear the TXE6 and RXE6 bits to 0 Preliminary User s Manual U17446EJ1VOUD 193 CHAPTER 11 SERIAL INTERFACE UART6 7 Input switch control register ISC The input switch control register ISC is used to receive a status signal transmitted from the master during LIN Local Interconnect Network reception The input signal is switched by setting ISC This register can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears this register to OOH Figure 11 11 Format of Input Switch Control Register ISC Address FF8CH After reset OOH R W Symbol 7 6 5 4 3 2 1 0 ISC1 T1000 input source selection T1000 P30 RxD6 P44 INTPO P30 Rx
66. SP 1 PC15 to PC8 SP 1 PC15 to PC8 register pairs SP SP 2 SP SP 2 SP 2 PSW SP SP 3 34 Preliminary User s Manual U17446EJ1VOUD CHAPTER 3 CPU ARCHITECTURE 3 2 2 General purpose registers A general purpose register consists of eight 8 bit registers X A C B E D L and H In addition each register being used as an 8 bit register two 8 bit registers in pairs can be used as a 16 bit register AX BC DE and HL Registers can be described in terms of function names X A C B E D L H AX BC DE and HL and absolute names RO to R7 and RPO to RP3 Figure 3 10 General Purpose Register Configuration a Absolute names 16 bit processing 8 bit processing HL b Function names 16 bit processing 8 bit processing RP3 RP1 RPO Preliminary User s Manual U17446EJ1VOUD 35 CHAPTER 3 CPU ARCHITECTURE 3 2 3 Special function registers SFRs Unlike the general purpose registers each special function register has a special function The special function registers are allocated to the 256 byte area FFOOH to FFFFH The special function registers can be manipulated like the general purpose registers with operation transfer and bit manipulation instructions Manipulatable bit units 1 8 and 16 differ depending on the special function register type Each manipulation bit unit can be specified as follows e 41 bit manipulation Des
67. Sets address at which data is to be written MOV A HL MOV FLW A Sets data to be written MOV PFS 00H Clears flash status register MOV WDTE 0ACH Clears amp restarts WDT HALT Self programming is started MOV A PFS CMP A 00H BNZ StatusError Checks write error Performs abnormal termination processing when an error occurs INCW HL address at which data to be written is located 1 MOVW AX HL CMPW AX DataAdrBtm Performs internal verify processing Preliminary User s Manual U17446EJ1VOUD 313 BNC INCW BR FlashVerify MOVW MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV HALT MOV CMP BNZ ModeOffLoop MOV MOV MOV MOV MOV MOV CMP BNZ MOV MOV EI BR 314 FlashVerify DE FlashWriteLoop HL WriteAdr LCMD 01H FLAPHC A FLAPLC A PFS 00H WDTE 0ACH A PFS A 00H StatusError FS 00H FCMD 0A5H LPMC 00H P P FI FLPMC 0FFH FLPMC 00H A PFS A 00H ModeOf fLoop MKO INT_MKO MK1 INT_MK1 StatusNormal CHAPTER 19 FLASH MEMORY if write of all data is completed Address at which data is to be written 1 Sets verify address Sets flash control command internal verify Sets verify start address Sets verify start address Sets verify end address Sets verify end address Clears flash status register Clears amp restarts WDT Self programming is started Checks int
68. TM80 count value 00H X O1H X 02H 03H ai n Delay A rit Delay B T If the timer is started when the selected clock is high and if delay A gt delay B an error of up to 1 5 clocks occurs 2 Setting of 8 bit compare register 80 8 bit compare register 80 CR80 can be set to OOH 3 Note on setting STOP mode Before executing the STOP instruction be sure to stop the timer operation TCE80 0 132 Preliminary User s Manual U17446EJ1VOUD CHAPTER 8 8 BIT TIMER H1 8 1 Functions of 8 Bit Timer H1 8 bit timer H1 has the following functions e Interval timer e PWM output mode e Square wave output 8 2 Configuration of 8 Bit Timer H1 8 bit timer H1 consists of the following hardware Table 8 1 Configuration of 8 Bit Timer H1 Item Configuration Timer register 8 bit timer counter H1 Registers 8 bit timer H compare register 01 CMP01 8 bit timer H compare register 11 CMP11 Timer output TOH1 Control registers 8 bit timer H mode register 1 TMHMD1 Port mode register 4 PM4 Port register 4 P4 Figure 8 1 shows a block diagram Preliminary User s Manual U17446EJ1VOUD 133 YET Figure 8 1 Block Diagram of 8 Bit Timer H1 Internal bus GNOALPA9PPZLN lenuew sJasn Aseuiwul ald 8 bit timer H mode register 1 TMHMD1 igi TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOENt 8 bit timer H 8 bit timer
69. Therefore the data frame length during continuous transmission is Data frame length 11 x FL 2 fxcLke 216 Preliminary User s Manual U17446EJ1VOUD CHAPTER 12 MULTIPLIER 12 1 Multiplier Function The multiplier has the following function e Calculation of 8 bits x 8 bits 16 bits 12 2 Multiplier Configuration 1 2 16 bit multiplication result storage register 0 MULO This register stores the 16 bit result of multiplication This register holds the result of multiplication after 16 CPU clocks have elapsed MULO can be read by a 16 bit memory manipulation instruction Reset signal generation makes MULO undefined Caution Although this register is manipulated with a 16 bit memory manipulation instruction it can be also manipulated with an 8 bit memory manipulation instruction When using an 8 bit memory manipulation instruction however access the register by means of direct addressing Multiplication data registers A and B MRAO and MRBO These are 8 bit multiplication data storage registers The multiplier multiplies the values of MRAO and MRBO MRAO and MRBO can be written by an 8 bit memory manipulation instruction Reset signal generation makes these registers undefined Figure 12 1 shows the block diagram of the multiplier Preliminary User s Manual U17446EJ1VOUD 217 218 CHAPTER 12 MULTIPLIER Figure 12 1 Block Diagram of Multiplier a Internal bus Multiplication da
70. Write command Writes to the specified address range and executes a verify check of the contents Checksum Checksum command Reads the checksum of the specified address range and compares with the written data Blank check Blank check command Confirms the erasure status of the entire memory Security Security setting command Prohibits batch erase chip erase command block erase command and write command to prevent operation by third parties The 78KOS KB1 returns a response command for the command issued by the dedicated flash programmer The response commands sent from the 78KOS KB1 are listed below Table 19 7 Response Commands Acknowledges command data Acknowledges illegal command data 278 Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY 19 7 4 Security settings The operations shown below can be prohibited using the security setting command Caution The security setting is valid when the programming mode is set next time Therefore when the security setting command is executed exit from the programming mode then set the programming mode again e Batch erase chip erase Execution of the block erase and batch erase chip erase commands for entire blocks in the flash memory is prohibited Once execution of the batch erase chip erase command is prohibited all the prohibition settings can no longer be cancelled Caution After the security setting of the batch erase is set
71. ad 8 p D A converter ANI2 P22 g ib ai ANI3 P23 gt oes 4 Successive approximation register SAR gt INTAD A D conversion result register ADCR ADCRH Analog input channel specification register ADS A D converter mode register ADM Internal bus 162 Preliminary User s Manual U17446EJ1VOUD 10 1 2 3 4 5 6 7 8 CHAPTER 10 A D CONVERTER 2 Configuration of A D Converter The A D converter consists of the following hardware Table 10 2 Registers of A D Converter Used on Software Item Configuration Registers 10 bit A D conversion result register ADCR 8 bit A D conversion result register ADCRH A D converter mode register ADM Analog input channel specification register ADS Port mode control register 2 PMC2 Port mode register 2 PM2 ANIO to ANI3 pins These are the analog input pins of the 4 channel A D converter They input analog signals to be converted into digital signals Pins other than the one selected as the analog input pin by the analog input channel specification register ADS can be used as input port pins Sample amp hold circuit The sample amp hold circuit samples the input signal of the analog input pin selected by the selector when A D conversion is started and holds the sampled analog input voltage value during A D conversion D A converter The D A converter is connected between AVrer and AVs
72. after switching on the internal power supply When switching the power supply off as a rule switch off the external power supply and then the internal power supply Use of the reverse power on off sequences may result in the application of an overvoltage to the internal elements of the device causing malfunction and degradation of internal elements due to the passage of an abnormal current The correct power on off sequence must be judged separately for each device and according to related specifications governing the device INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I O pull up power supply while the device is not powered The current injection that results from input of such a signal or I O pull up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device Preliminary User s Manual U17446EJ1VOUD Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and or other countries PC AT is a trademark of International Business Machines Corporation HP9000 series 700 and HP UX are trademarks of Hewlett Packard Company SPARCstation is a trademark of SPARC International Inc Solaris and SunOS are trademarks of Sun Microsystems Inc Su
73. authorized representatives and distributors They will verify e Device availability e Ordering information e Product release schedule e Availability of related technical literature e Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth e Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country GLOBAL SUPPORT http www necel com en support support html NEC Electronics America Inc U S NEC Electronics Europe GmbH NEC Electronics Hong Kong Ltd Santa Clara California Duesseldorf Germany Hong Kong Tel 408 588 6000 Tel 0211 65030 Tel 2886 9318 800 366 9782 e Sucursal en Espa a NEC Electronics Hong Kong Ltd Madrid Spain Seoul Branch Tel 091 504 27 87 Seoul Korea Tel 02 558 3737 e Succursale Fran aise V lizy Villacoublay France NEC Electronics Shanghai Ltd Tel 01 30 67 58 00 Shanghai P R China Tel 021 5888 5400 e Filiale Italiana Milano Italy x ene NEC Electronics Taiwan Ltd Tel 0266 V94 Taipei Taiwan e Branch The Netherlands Tel 02 2719 23 Eindhoven The Netherlands Tel 040 2445845 NEC Electronics Singapore Pte Ltd Novena Square Singapore e Tyskland Filial Tel 6253 8311 Taeby Sweden Tel 08 63 80 820 e United Kingdom Branch Milton Keynes UK Tel 01908 691 133
74. bit timer counter 00 TM00 count value and an interrupt request INTTM 000 is generated if they match It can also be used as the register that holds the interval time then TMO0 is set to interval timer operation e When CRO000 is used as a capture register It is possible to select the valid edge of the T1000 pin or the TI010 pin as the capture trigger Setting of the T1000 or T1010 valid edge is performed by means of prescaler mode register 00 PRMOO refer to Table 6 2 Preliminary User s Manual U17446E 1VOUD 87 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 88 Table 6 2 CR000 Capture Trigger and Valid Edges of T1000 and T1010 Pins 1 TI000 pin valid edge selected as capture trigger CRC001 1 CRC000 1 CR000 Capture Trigger T1000 Pin Valid Edge Falling edge Rising edge Rising edge Falling edge No capture operation Both rising and falling edges CR000 Capture Trigger T1010 Pin Valid Edge Falling edge Falling edge Rising edge Rising edge Both rising and falling edges Both rising and falling edges Remarks 1 2 Cautions 1 Setting ES010 ES000 1 0 and ES110 ES100 1 0 is prohibited ES010 ES000 Bits 5 and 4 of prescaler mode register 00 PRMOO ES110 ES100 Bits 7 and 6 of prescaler mode register 00 PRMOO CRC001 CRC000 Bits 1 and 0 of capture compare control register 00 CRC00 Set CR000 to other than 0000H in the clear amp start mode en
75. capture register the capture trigger input takes precedence and the read data is undefined Also if the timer count stop and the input of the capture trigger conflict the capture data is undefined p 89 Changing the CRO10 setting during TMOO operation may cause a malfunction To change the setting refer to 6 5 Cautions Related to 16 Bit Timer Event Counter 00 17 Changing compare register during timer operation p 89 TMCOO 16 Bit Timer Mode Control Register 00 16 bit timer counter 00 TMOO starts operation at the moment TMC002 and TMCO003 operation stop mode are set to a value other than 0 0 respectively Set TMC002 and TMCO003 to 0 0 to stop the operation p 90 The timer operation must be stopped before writing to bits other than the OVFO00 flag p 91 Regardless of the CPU s operation mode when the timer stops the signals input to pins TI000 TI010 are not acknowledged p 91 Except when TI000 pin valid edge is selected as the count clock stop the timer operation before setting STOP mode or system clock stop mode otherwise the timer may malfunction when the system clock starts p 91 Set the valid edge of the TI000 pin with bits 4 and 5 of prescaler mode register 00 PRMOO after stopping the timer operation p 91 If the clear amp start mode entered on a match between TMOO and CROOO clear amp start mode at the valid ed
76. change the level of the T1000 pin or its alternate function port pin Because the external trigger is valid even in this case the timer is cleared and started even at the level of the T1000 pin or its alternate function port pin resulting in the output of a pulse at an undesired timing Preliminary User s Manual U17446E 1VOUD 115 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 Figure 6 32 Control Register Settings for One Shot Pulse Output with Software Trigger a 16 bit timer mode control register 00 TMC00 TMC003 TMC002 TMC001 OVFOO mee prs aod aca b Capture compare control register 00 CRC00 Free running mode 3 CRC002 CRC001 CRC000 oo Ree ceseeenene ERE CRO000 as compare register CR010 as compare register c 16 bit timer output control register 00 TOC00 7 OSPT00 OSPE00 TOC004 LVSOO0 LVROO TOC001 TOE0O Enables TOOO output Inverts output upon match between TMO0 and CROOO Specifies initial value of TOOO output F F setting 11 is prohibited Inverts output upon match between TMO0 and CR010 Sets one shot pulse output mode Set to 1 for output d Prescaler mode register 00 PRMO00 ES110 ES100 ES010 ES000 2 PRMO001 PRM000 PRMOO 0 1 0 1 0 1 eee oc a Selects count clock Setting invalid setting 10 is prohibited Setting invalid setting 10 is prohibited Caution Do not set 0000H to the CR000 and CR010 r
77. clear POC circuit is 2 1 V 0 1 V Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of port pins 340 Preliminary User s Manual UU17446EJ1VOUD CHAPTER 21 ELECTRICAL SPECIFICATIONS TARGET VALUES DC Characteristics Ta 40 to 85 C Von 2 0 to 5 5 V 1 Vss 0 V 2 2 Parameter Pull up resistance Conditions Vi 0V Pull down resistance P121 P122 reset stat Supply current Notes 1 SF ON Pe z fx 10 MHz Voo 5 0 V 10 Note4 Crystal ceramic oscillation external clock input oscillation operating mode When A D converter Wh Whe Wh is stopped Note 8 en A D converter is operating fx 6 MHz Voo 5 0 V 10 4 n A D converter is stopped Note 8 en A D converter is operating fx 5 MHz Voo 3 0 V 10 5 When A D converter Wh is stopped en Note 8 A D converter is operating fx 10 MHz Voo 5 0 V 10 N 4 Crystal ceramic oscillation external clock input HALT modeNte Wh When Wh When Wh en peripheral functions are stopped peripheral functions are operating fx 6 MHz Voo 5 0 V 10 N 4 en peripheral functions are stopped peripheral functions are operating fx 5 MHz Voo 3 0 V 10 5 en peripheral functions are stopped When peripheral functions are operating Note 3 High speed Ring OSC fx 8 MHz Voo
78. conflict with the timing of the match so the operation is not guaranteed in such cases To change CROn0 during timer counting follow the procedure below using an INTTMOOO interrupt If CRO10 is changed during timer counting without performing processing lt 1 gt p 124 above the value in CR010 may be rewritten twice or more causing an inversion of the output level of the TOOO pin at each rewrite 5 8 bit timer CR80 8 bit When changing the value of CR80 be sure to stop the timer operation If the p 128 2 80 compare register value of CR80 is changed with the timer operation enabled a match interrupt 5 80 request signal may be generated immediately TMC80 8 bit Be sure to set TMC80 after stopping the timer operation p 129 timer mode control register Be sure to clear bits 0 and 6 to 0 p 129 80 Interval timer When changing the value of CR80 be sure to stop the timer operation Ifthe p 130 value of CR80 is changed with the timer operation enabled a match interrupt request signal may be generated immediately If the count clock of TMC80 is set and the operation of TM80 is enabled at the p 130 same time by using an 8 bit memory manipulation instruction the error of one cycle after the timer is started may be 1 clock or more Therefore be sure to follow the above sequence when using TM80 as an interval timer Preliminary User s Manual U17446EJ1VOUD 371 APPENDIX D LIST OF CAUTIONS 7 18
79. control in default mode 0 Low level 1 High level TOEN1 Timer output control 0 Disable output 1 Enable output Cautions 1 When TMHE1 1 setting the other bits of the TMHMD1 register is prohibited 2 In the PWM output mode be sure to set 8 bit timer H compare register 11 CMP11 when starting the timer count operation TMHE1 1 after the timer count operation was stopped TMHE 1 0 be sure to set again even if setting the same value to the CMP11 register Remarks 1 fxr Oscillation frequency of clock to peripheral hardware 2 fR Low speed Ring OSC clock oscillation frequency 3 Figures in parentheses apply to operation at fxe 10 MHz fri 240 kHz TYP Preliminary User s Manual U17446EJ1VOUD 137 CHAPTER 8 8 BIT TIMER H1 2 Port mode register 4 PM4 This register sets port 4 input output in 1 bit units When using the P42 TOH1 pin for timer output clear PM42 and the output latch of P42 to 0 PM4 can be set by a 1 bit or 8 bit memory manipulation instruction Generation of reset signal sets this register to FFH Figure 8 5 Format of Port Mode Register 4 PM4 Address FF24H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM4 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 P4n pin I O mode selection n 0 to 7 Output mode output buffer on Input mode output buffer off 138 Preliminary User s Manual U17446EJ1VOUD CHAPTER 8 8 BIT TIMER H1 8 4 Operation of 8 Bit Timer H1 8 4 1 Operati
80. d Prescaler mode register 00 PRM00 ES110 ES100 ES010 ES000 PRM001 PRMO000 oa Selects count clock setting 11 is prohibited Specifies the rising edge for pulse width detection Setting invalid setting 10 is prohibited Caution Do not set the CR000 and CR010 registers to 0000H 118 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 Figure 6 35 Timing of One Shot Pulse Output Operation with External Trigger with Rising Edge Specified When TMC00 is set to 08H TMOO count starts l t l La Countclock LI ILI ILU LILI ILILILILIL TMO0 count value OOOOH YoooTHX Hooor CE CR OO CO a CR010 set value N N N N T CROO0 set value um M M M T1000 pin input A S INTTM010 l nouu INTTMO00 o TOOO pin output l Caution 16 bit timer counter 00 starts operating as soon as a value other than 00 operation stop mode is set to the TMC002 and TMC003 bits Remark N lt M Preliminary User s Manual U17446EJ 1VOUD 119 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 6 5 Cautions Related to 16 Bit Timer Event Counter 00 1 Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start This is because 16 bit timer counter 00 TMOO is started asynchronously to the count clock Figure 6 36 Start Timing of 16 Bit Timer Counter 00 TM00 Count clock
81. edge is detected immediately after the TM00 operation is enabled g Remark n 0 1 lt 2 gt The sampling clock used to remove noise differs when a T1000 valid edge is used as the count clock and when it is used as a capture trigger In the former case the count clock is fxr and in the latter case the count clock is selected by prescaler mode register 00 PRMOO The capture operation is not performed until the valid edge is sampled and the valid level is detected twice thus eliminating noise with a short pulse width 19 External event counter When reading the external event counter count value TM00 should be read 20 PPG output lt l gt Values in the following range should be set in CR000 and CRO10 0000H lt CR010 lt CR000 lt FFFFH setting CR000 to 0000H is prohibited lt 2 gt The cycle of the pulse generated through PPG output CR000 setting value 1 has a duty of CRO10 setting value 1 CR000 setting value 1 21 STOP mode or system clock stop mode setting Except when T1000 pin valid edge is selected as the count clock stop the timer operation before setting STOP mode or system clock stop mode otherwise the timer may malfunction when the system clock starts 22 P31 T1010 TOOO pin When using P31 as the input pin T1010 of the valid edge it cannot be used as a timer output pin TOOO When using P31 as the timer output pin TO00 it cannot be used as the input pin T1010 of the valid edge Preliminary
82. eee b Capture compare control register 00 CRC00 Clears and starts on match between TMO0 and CROOO 3 CRC002 CRC001 CRC000 E a CRO000 used as compare register 110 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 Figure 6 27 Control Register Settings in Square Wave Output Mode 2 2 c 16 bit timer output control register 00 TOC00 7 OSPT00 OSPE00 TOC004 LVS00 LVRO0 TOC001 TOE00 Enables TOOO output Inverts output on match between TMOO and CROOO Specifies initial value of TOOO output F F setting 11 is prohibited Does not invert output on match between TMOO and CRO10 Disables one shot pulse output d Prescaler mode register 00 PRMO00 ES110 ES100 ES010 ES000 3 2 PRMOO1 PRMO00 PRMOO 0 1 0 1 O 1 0 1 Lo o 0 1 O 1 Selects count clock Setting invalid setting 10 is prohibited Setting invalid setting 10 is prohibited Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with square wave output See the description of the respective control registers for details Figure 6 28 Square Wave Output Operation Timing countclock LJ LI PLI LJ LU LU Ld UULU l Tod count value YoooorYonorrYoooanX ANA N YoooonYooosnYoooanX Yaw ooon INTTMO00 o L c TOOO pin output Preliminary User s Manual U17446EJ 1VOUD 111 CHAPTER 6 16 BIT T
83. eke ck tee sees back Scene owt nce cu Sep a aaae oven ss ocanech cannes eseces 327 20 1 1 Operand identifiers and description Methods eee ceeeeeee sent eeeeeeeeeeeeneeeeeenaeeeeeeeeeeeenneeeeeeaas 327 20 1 2 Description of Operation COLUMN ec eee ceereeeeenneeeeeeaeeeseeeaeeeseeeeeesaeeesseaeeeeneeeeeeenaeeeeaas 328 20 173 Description of Flag Columns sc csccecc cee cena tee cesec dee edecdteeeeecseeeiuneedee a iedit 328 202 Operations Lists ciciceccets eit cecteces athe caves aa a A e Aaa aa P ste Ea a aaa Eaa EEEE niece 329 20 3 Instructions Listed by Addressing Type ssssssssssnunseunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nn 334 CHAPTER 21 ELECTRICAL SPECIFICATIONS TARGET VALUES 0 cccccesssesseeeeeeeeeeeeeeeees 337 CHAPTER 22 PACKAGE DRAWING ccceceseesseeeeeeceeeeeeeeeeeeeeeeeeeee sens seaeeeseseseseesseaeeeseseeneeeseeanes 349 APPENDIX A DEVELOPMENT TOOLS 6c 0icfeccecsticccccccecetsteseteceeredeedacesecteeteentevessdelicceetseevesseeeebaccecetverse 350 A 1 Software Package vccceiciiceis tececesccs cceesceeeseinideceseseceedes seas carssveeeaveteee cece sceenceeesueeesvenceeatereeedsesueesd 353 A 2 Language Processing Software sccccssecccesseeeeeeseenseeeenenseseseensesesaeseseseaeseeseseaeseseseanseessaes 353 Az3 COMtHON SORWANG aiia An aAA SARS ARAT ARATA AAA NENA PAA TERANA E VANIER ESENS ANNIES 354 A 4 Flash Memory Writing Tools ccesscccsseeneeseseee
84. error interrupt INTSR6 INTSRE6 is generated on completion of reception Figure 11 19 Reception Completion Interrupt Request Timing U go 3 gt lt op a 6 4 xe eee iw o iw X INTSR6 RXB6 X Cautions 1 Be sure to read receive buffer register 6 RXB6 even if a reception error occurs Otherwise an overrun error will occur when the next data is received and the reception error status will persist 2 Reception is always performed with the number of stop bits 1 The second stop bit is ignored 3 Be sure to read asynchronous serial interface reception error status register 6 ASIS6 before reading RXB6 Preliminary User s Manual U17446EJ1VOUD CHAPTER 11 SERIAL INTERFACE UART6 f Reception error Three types of errors may occur during reception a parity error framing error or overrun error If the error flag of asynchronous serial interface reception error status register 6 ASIS6 is set as a result of data reception a reception error interrupt request INTSR6 INTSRE6 is generated Which error has occurred during reception can be identified by reading the contents of ASIS6 in the reception error interrupt servicing INTSR6 INTSRE6 see Figure 11 6 The contents of ASIS6 are reset to 0 when ASIS6 is read Table 11 3 Cause of Reception Error Reception Error Cause Parity error The parity specified for transmission does not match the parity of the receive data Framing erro
85. execution If this processing is not performed an internal reset signal is generated when the watchdog timer overflows after STOP instruction execution A status transition diagram is shown below Preliminary User s Manual U17446EJ1VOUD 153 154 CHAPTER 9 WATCHDOG TIMER Figure 9 4 Status Transition Diagram When Low Speed Ring OSC Cannot Be Stopped Is Selected by Option Byte WDT clock fri Overflow time 546 13 ms MAX WDTE ACH Clear WDT counter WDT clock is fixed to frL Select overflow time settable only once WDT clock fri Overflow time 4 27 ms to 546 13 ms MAX WDT count continues HALT instruction STOP instruction Interrupt Interrupt HALT STOP WDT count continues WDT count continues Preliminary User s Manual U17446EJ1VOUD CHAPTER 9 WATCHDOG TIMER 9 4 2 Watchdog timer operation when low speed Ring OSC can be stopped by software is selected by option byte The operation clock of the watchdog timer can be selected as either the low speed Ring OSC clock or the system clock After reset is released operation is started at the maximum cycle of the low speed Ring OSC clock bits 2 1 and 0 WDCS2 WDCS1 WDCS0O of the watchdog timer mode register WDTM 1 1 1 The following shows the watchdog timer operation after reset release 1 The status after reset release is as follows e Operation clock Low speed Ring OSC clock e Cycle 2 fre 546 13 ms operat
86. flash programming mode control register FLPMC which is protected in the correct sequence writing the flash protect command register PFCMD FLPMC is not written and a protection error occurs If this happens bit O of PFS FPRERR is set to 1 When FPRERR is 1 it can be cleared to 0 by writing 0 to it Errors that may occur during self programming are reflected in bit 1 VCERR and bit 2 WEPRERR of PFS VCERR or WEPRERR can be cleared by writing 0 to them All the flags of the PFS register must be pre cleared to 0 to check if the operation is performed correctly PFS can be set with a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears PFS to OOH Figure 19 14 Format of Flash Status Register PFS Address FFA1H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 1 Operating conditions of FPRERR flag lt Setting conditions gt e If PFCMD is written when the store instruction operation recently performed on a peripheral register is not to write a specific value A5H to PFCMD e f the first store instruction operation after lt 1 gt is on a peripheral register other than FLPMC e If the first store instruction operation after lt 2 gt is on a peripheral register other than FLPMC e If a value other than the inverted value of the value to be set to FLPMC is written by the first store instruction after lt 2 gt e f the first store instruction operation after lt 3 gt is on a peripheral register other th
87. interrupt request When an unmasked interrupt request is generated the STOP mode is released After the oscillation stabilization time has elapsed if interrupt acknowledgment is enabled vectored interrupt servicing is carried out If interrupt acknowledgment is disabled the next address instruction is executed Figure 14 5 STOP Mode Release by Interrupt Request Generation 1 If CPU clock is high speed Ring OSC clock or external input clock Interrupt request _ STOP instruction lt _ Standby release et GR eee signal oe gehen eat ET Operation Operation CPU status mode STOP mode en Operation mode Oscillation Oscillation stops Oscillation System clock oscillation 2 If CPU clock is crystal ceramic oscillation clock Interrupt request _ STOP instruction Standby release i signal ee Ay Oe 8 Operation Operation Waiting for stabilization Operation CPU status mode STOP mode poo of oscillation uF mode HALT mode status System clock Oscillation Oscillation stops Oscillation Oscillation stabilization time set by OSTS Note The operation stop time is 17 ws MIN 34 ws TYP and 67 ws MAX Remark The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged Preliminary User s Manual U17446EJ 1VOUD CHAPTER 14 STANDBY FUNCTION b Release by reset signal generation When the re
88. is shown in Table 13 3 See Figures 13 8 and 13 9 for the interrupt request acknowledgment timing Table 13 3 Time from Generation of Maskable Interrupt Request to Servicing Minimum Time Maximum Time Note The wait time is maximum when an interrupt request is generated immediately before BT and BF instructions Remark 1 clock Foru fcpu CPU clock When two or more maskable interrupt requests are generated at the same time they are acknowledged starting from the interrupt request assigned the highest priority A pending interrupt is acknowledged when a status in which it can be acknowledged is set Figure 13 7 shows the algorithm of interrupt request acknowledgment When a maskable interrupt request is acknowledged the contents of the PSW and PC are saved to the stack in that order the IE flag is reset to 0 and the data in the vector table determined for each interrupt request is loaded to the PC and execution branches To return from interrupt servicing use the RETI instruction Preliminary User s Manual U17446EJ1VOUD 229 CHAPTER 13 INTERRUPT FUNCTIONS Figure 13 7 Interrupt Request Acknowledgment Processing Algorithm Yes Interrupt request generated xxlF Interrupt request flag xxMK Interrupt mask flag IE Flag to control maskable interrupt request acknowledgment 1 enable 0 disable Figure 13 8 Interrupt Request Acknowledgment Timing Example of MOV A r 8 clocks
89. low speed Ring OSC mode register LSRCM when it is specified by the option byte that its oscillation can be stopped by software Preliminary User s Manual U17446EJ1VOUD 69 CHAPTER 5 CLOCK GENERATORS 5 2 Configuration of Clock Generators The clock generators consist of the following hardware Table 5 1 Configuration of Clock Generators Item Configuration Control registers Processor clock control register PCC Preprocessor clock control register PPCC Low speed Ring OSC mode register LSRCM Oscillation stabilization time select register OSTS Oscillators Crystal ceramic oscillator High speed Ring OSC oscillator External clock input circuit Low speed Ring OSC oscillator 70 Preliminary User s Manual U17446EJ1VOUD X1 P121 oscillatorN X2 P122 CHAPTER 5 CLOCK GENERATORS Figure 5 1 Block Diagram of Clock Generators Internal bus 6 Preprocessor clock Processor clock control register PPCC control register PCC PCC1 E ee hi System clock oscillation Controller stabilization time counter c CPU clock P U Oscillation stabilization time select register OSTS STOP fcpu System clock Watchdog timer Crystal ceramia oscillation Prescaler fx fx Selector High speed Ring OSC oscillation fxP Prescaler l Selector Clock to peripheral hardware fx Low speed 8 bit timer H1 Ring OSC watchdog ti
90. mode Match between TMO0 and CR000 or match between TMOO and CR010 Match between TM00 and CR000 match between TM00 and CRO10 or T1000 pin valid edge Clear amp start occurs on valid edge of T1000 pin Clear amp start occurs on match between TMO0 and CR000 Match between TMO0 and CR000 or match between lt When operating as compare register gt Generated on match between TMOO and CR000 or match between TM00 and CR010 lt When operating as capture register gt Generated on T1000 pin and T1010 pin valid edge TMO0 and CR010 OVFO00 Match between TMO00 and CR000 match between TM00 and CRO10 or T1000 pin valid edge Overflow detection of 16 bit timer counter 00 TM00 0 Overflow not detected 1 Overflow detected Cautions 1 2 Remark TMO0OO The timer operation must be stopped before writing to bits other than the OVF00 flag Regardless of the CPU s operation mode when the timer stops the signals input to pins T1I000 T1I010 are not acknowledged Except when TI000 pin valid edge is selected as the count clock stop the timer operation before setting STOP mode or system clock stop mode otherwise the timer may malfunction when the system clock starts Set the valid edge of the T1000 pin with bits 4 and 5 of prescaler mode register 00 PRMO00 after stopping the timer operation If the clear amp start mode entered on a match between TMO00 and CROOO clear
91. of ASIF6 To initialize the transmission unit upon completion of continuous transmission be sure to check that the TXSF6 flag is O after generation of the transmission completion interrupt and then execute initialization If initialization is executed while the TXSF6 flag is 1 the transmit data cannot be guaranteed During continuous transmission an overrun error may occur which means that the next transmission was completed before execution of INTST6 interrupt servicing after transmission of one data frame An overrun error can be detected by developing a program that can count the number of transmit data and by referencing the TXSF6 flag Preliminary User s Manual U17446EJ1VOUD 377 APPENDIX D LIST OF CAUTIONS Function Serial interface UART6 Soft Classification Chapter 11 Details of Function Normal reception Cautions Be sure to read receive buffer register 6 RXB6 even if a reception error occurs Otherwise an overrun error will occur when the next data is received and the reception error status will persist 13 18 Reception is always performed with the number of stop bits 1 The second stop bit is ignored Be sure to read asynchronous serial interface reception error status register 6 ASIS6 before reading RXB6 Generation of serial clock Keep the baud rate error during transmission to within the permissible error range
92. of RXB6 and the LSB of RXB6 is always 0 If an overrun error OVE6 occurs the receive data is not transferred to RXB6 RXB6 can be read by an 8 bit memory manipulation instruction No data can be written to this register Generation of reset signal sets this register to FFH Receive shift register 6 RXS6 This register converts the serial data input to the RxD6 pin into parallel data RXS6 cannot be directly manipulated by a program Transmit buffer register 6 TXB6 This buffer register is used to set transmit data Transmission is started when data is written to TXB6 If the data length is set to 7 bits e In LSB fast transmission data is transferred to bits O to 6 of TXB6 and the MSB of TXB6 is not transmitted e In MSB fast transmission data is transferred to bits 7 to 1 of TXB6 and the LSB of TXB6 is not transmitted This register can be read or written by an 8 bit memory manipulation instruction Generation of reset signal sets this register to FFH Cautions 1 Do not write data to TXB6 when bit 1 TXBF6 of asynchronous serial interface transmission status register 6 ASIF6 is 1 2 Do not refresh write the same value to TXB6 by software during a communication operation when bit 7 POWER6 and bit 6 TXE6 of asynchronous serial interface operation mode register 6 ASIM6 are 1 or when bit 7 POWER6 and bit 5 RXE6 of ASIM6 are 1 Transmit shift register 6 TXS6 This register transmits the data transferred from TXB6 from th
93. output control register 00 Timer operation must be stopped before setting other than OSPTOO p 93 If LVSOO and LVROO are read 0 is read p 93 OSPT00 is automatically cleared after data is set so 0 is read p 93 0 Do not set OSPTOO to 1 other than in one shot pulse output mode p 93 A write interval of two cycles or more of the count clock selected by prescaler mode register 00 PRMOO is required to write to OSPTOO successively p 93 0 When the TOE0O0 is 0 set the TOE00 LVSOO and LVROO at the same time with the 8 bit memory manipulation instruction When the TOEO0 is 1 the LVS00 and LVROO can be set with the 1 bit memory manipulation instruction p 93 PRMOO Prescaler mode register 00 Always set data to PRMOO after stopping the timer operation p 95 If the valid edge of the TIO00 pin is to be set as the count clock do not set the clear start mode and the capture trigger at the valid edge of the TI000 pin p 95 In the following cases note with caution that the valid edge of the TIOnO pin is detected lt 1 gt Immediately after a system reset if a high level is input to the TIOnO pin the operation of the 16 bit timer counter 00 TMO00 is enabled If the rising edge or both rising and falling edges are specified as the valid edge of the TlOn0 pin a rising edge is detected immediately after the TMOO operation is enabled lt
94. reducing the CPU operating current Because this mode can be cleared by an interrupt request it enables intermittent operations to be carried out However select the HALT mode if processing must be immediately started by an interrupt request when the operation stop time is generated after the STOP mode is released because an additional wait time for Stabilizing oscillation elapses when crystal ceramic oscillation is used Note The operation stop time is 17 ws MIN 34 ws TYP and 67 ws MAX In either of these two modes all the contents of registers flags and data memory just before the standby mode is set are held The I O port output latches and output buffer statuses are also held Cautions 1 When shifting to the STOP mode be sure to stop the peripheral hardware operation before executing STOP instruction except the peripheral hardware that operates on the low speed Ring OSC clock 2 The following sequence is recommended for operating current reduction of the A D converter when the standby function is used First clear bit 7 ADCS and bit 0 ADCE of the A D converter mode register ADM to 0 to stop the A D conversion operation and then execute the HALT or STOP instruction 3 If the low speed Ring OSC oscillator is operating before the STOP mode is set oscillation of the low speed Ring OSC clock cannot be stopped in the STOP mode refer to Table 14 1 Preliminary User s Manual U17446EJ 1VOUD 235 CHAPTER 14 STANDBY
95. shot pulse output with software trigger Do not set the OSPTOO bit to 1 again while the one shot pulse is being output To output the one shot pulse again wait until the current one shot pulse output is completed p 115 When using the one shot pulse output of 16 bit timer event counter 00 with a software trigger do not change the level of the T1000 pin or its alternate function port pin Because the external trigger is valid even in this case the timer is cleared and started even at the level of the TI000 pin or its alternate function port pin resulting in the output of a pulse at an undesired timing p 115 O Do not set 0000H to the CR000 and CR010 registers p 116 16 bit timer counter 00 starts operating as soon as a value other than 00 operation stop mode is set to the TMC003 and TMC002 bits Preliminary User s Manual U17446EJ1VOUD p 117 O APPENDIX D LIST OF CAUTIONS 6 18 S Function Details of Cautions g Function T n amp O 2 16 bit One shot pulse Do not input the external trigger again while the one shot pulse is being p 117 U 2 T timer event output with output To output the one shot pulse again wait until the current one shot counter 00 external trigger pulse output is completed 5 Do not set the CR000 and CR
96. specifies the input port of the analog voltage to be A D converted ADS can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears this register to OOH Figure 10 5 Format of Analog Input Channel Specification Register ADS Address FF81H After reset OOH R W Symbol 7 6 5 4 3 2 1 0 Analog input channel specification Caution Be sure to clear bits 2 to 7 of ADS to 0 10 bit A D conversion result register ADCR This register is a 16 bit register that stores the A D conversion result The higher six bits are fixed to 0 Each time A D conversion ends the conversion result is loaded from the successive approximation register and is stored in ADCR in order starting from bit 1 of FF19H FF19H indicates the higher 2 bits of the conversion result and FF 18H indicates the lower 8 bits of the conversion result ADCR can be read by a 16 bit memory manipulation instruction Reset signal generation makes ADCR undefined Figure 10 6 Format of 10 Bit A D Conversion Result Register ADCR Address FF18H FF19H After reset Undefined R Caution When writing to the A D converter mode register ADM and analog input channel specification register ADS the contents of ADCR may become undefined Read the conversion result following conversion completion before writing to ADM and ADS Using timing other than the above may cause an incorrect conversion result to be read Preliminary User
97. speed Ring OSC clock selected as operating clock Operable Operation continues Operation stops A D converter Operation stops Serial interface UART6 Operation stops Power on clear circuit Always operates Low voltage detector Operable External interrupt Operable Note Cannot be stopped or Stopped by software is selected for low speed Ring OSC by the option byte for the option byte see CHAPTER 18 OPTION BYTE 240 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 14 STANDBY FUNCTION 2 STOP mode release Figure 14 4 Operation Timing When STOP Mode Is Released lt 1 gt If high speed Ring OSC clock or external input clock is selected as system clock to be supplied STOP mode is released STOP mode l System clock oscillation CPU clock P mater High speedRing OSC clock or external clock input lt 2 gt If crystal ceramic oscillation clock is selected as system clock to be supplied STOP mode is released Y STOP mode System clock ONI oscillation CPU clock o i HALT peration status za oscillation stabilization time set by OSTS Crystal ceramic oscillation clock Note The operation stop time is 17 ws MIN 34 ws TYP and 67 ws MAX The STOP mode can be released by the following two sources Preliminary User s Manual U17446EJ 1VOUD 241 242 CHAPTER 14 STANDBY FUNCTION a Release by unmasked
98. speed Ring OSC oscillator when it is selected as the source clock of WDT and the count clock of 8 bit timer H1 Figure 5 14 shows the status transition of the low speed Ring OSC oscillator Table 5 4 Operation Status of Low Speed Ring OSC Oscillator Option Byte Setting CPU Status WDT Status TMH1 Status Can be stopped by LSRSTOP 1 Operation mode Stopped Stopped software LSRSTOP 0 Operates Operates LSRSTOP 1 Standby Stopped Stopped LSRSTOP 0 Stopped Operates Cannot be stopped Operation mode Operates Standby Preliminary User s Manual U17446EJ1VOUD 83 84 CHAPTER 5 CLOCK GENERATORS Figure 5 14 Status Transition of Low Speed Ring OSC Oscillator Power application Voo gt 2 1 V 0 1 V Reset by power on clear Reset signal Select by option byte if low speed Ring OSC can be stopped or not Can be stopped Cannot be stopped Clock source of WDT is selected Clock source of by softwareNote WDT is fixed to frL Low speed Ring OSC oscillator cannot be stopped Low speed Ring OSC oscillator can be stopped LSRSTOP 1 LSRSTOP 0 Low speed Ring OSC oscillator stops Note The clock source of the watchdog timer WDT is selected from fx or fri or it may be stopped For details refer to CHAPTER 9 WATCHDOG TIMER Preliminary User s Manual U17446EJ1VOUD 6 1 16 1 2 3 4 5 6 CHAPTER 6 16
99. the watchdog timer and 8 bit timer H1 TMH1 5 1 1 System clock oscillators The following three types of system clock oscillators are used e High speed Ring OSC oscillator This circuit internally oscillates a clock of 8 MHz TYP Its oscillation can be stopped by execution of the STOP instruction If the high speed Ring OSC oscillator is selected to supply the system clock the X1 and X2 pins can be used as I O port pins e Crystal ceramic oscillator This circuit oscillates a clock with a crystal ceramic oscillator connected across the X1 and X2 pins It can oscillate a clock of 1 to 10 MHz Oscillation of this circuit can be stopped by execution of the STOP instruction e External clock input circuit This circuit supplies a clock from an external IC to the X1 pin A clock of 1 to 10 MHz can be supplied Internal clock supply can be stopped by execution of the STOP instruction If the external clock input is selected as the system clock the X2 pin can be used as an I O port pin The system clock source is selected by using the option byte For details refer to CHAPTER 18 OPTION BYTE When using the X1 and X2 pins as I O port pins refer to CHAPTER 4 PORT FUNCTIONS for details 5 1 2 Clock oscillator for interval time generation The following circuit is used as a clock oscillator for interval time generation e Low speed Ring OSC oscillator This circuit oscillates a clock of 240 kHz TYP Its oscillation can be stopped by using the
100. the SBF Synchronous Break Field transmission control function is used for transmission For the transmission operation of LIN see Figure 11 1 LIN Transmission Operation When bit 7 POWER6 of asynchronous serial interface mode register 6 ASIM6 is set to 1 the TxD6 pin outputs high level Next when bit 6 TXE6 of ASIM6 is set to 1 the transmission enabled status is entered and SBF transmission is started by setting bit 5 SBTT6 of asynchronous serial interface control register 6 ASICLE6 to 1 Thereafter a low level of bits 13 to 20 set by bits 4 to 2 SBL62 to SBL60 of ASICL6 is output Following the end of SBF transmission the transmission completion interrupt request INTST6 is generated and SBTT6 is automatically cleared Thereafter the normal transmission mode is restored Transmission is suspended until the data to be transmitted next is written to transmit buffer register 6 TXB6 or until SBTT6 is set to 1 Figure 11 22 SBF Transmission TxD6 1 4 5 INTST6 SBTT6 Remark TxD6 TxD6 pin output INTST6 Transmission completion interrupt request SBTT6 Bit5 of asynchronous serial interface control register 6 ASICL6 13 Stop weed 4 F 1 1 1 1 1 Baie behiee Poe siege se bis 1 1 1 1 1 1 1 1 1 1 9 10 See 4 208 Preliminary User s Manual U17446EJ1VOUD CHAPTER 11 SERIAL INTERFACE UART6 i SBF reception When the device is incorporated in LIN the SBF Syn
101. the order of lt 1 gt and lt 2 gt is reversed 3 lt l gt can be omitted However ignore the data resulting from the first conversion after lt A gt in this case 4 The period from lt 5 gt to lt 8 gt differs from the conversion time set using bits 5 to 3 FR2 to FRO of ADM The period from lt 7 gt to lt 8 gt is the conversion time set using FR2 to FRO Preliminary User s Manual U17446EJ1VOUD 173 10 1 2 3 CHAPTER 10 A D CONVERTER 5 How to Read A D Converter Characteristics Table Here special terms unique to the A D converter are explained Resolution This is the minimum analog input voltage that can be identified That is the percentage of the analog input voltage per bit of digital output is called 1LSB Least Significant Bit The percentage of 1LSB with respect to the full scale is expressed by FSR Full Scale Range 1LSB is as follows when the resolution is 10 bits 1LSB 1 2 1 1024 0 098 FSR Accuracy has no relation to resolution but is determined by overall error Overall error This shows the maximum error value between the actual measured value and the theoretical value Zero scale error full scale error integral linearity error and differential linearity errors that are combinations of these express the overall error Note that the quantization error is not included in the overall error in the characteristics table Quantization error When analog values are converted
102. timing of a match between 16 bit timer counter 00 TM00 and 16 bit timer capture compare register OnO CROn0 during timer counting the change timing may conflict with the timing of the match so the operation is not guaranteed in such cases To change CROn0 during timer counting follow the procedure below using an INTTM000 interrupt lt Changing cycle CR000 gt NOW BP WN Disable the timer output inversion operation at the match between TM00 and CR000 TOCO001 0 Disable the INTTM000 interrupt TMMKO000 1 Rewrite CR 000 Wait for 1 cycle of the TM0O count clock Enable the timer output inversion operation at the match between TMO00 and CR 000 TOCO001 1 Clear the interrupt request flag of INTTM 000 TMIF 000 0 Enable the INTTM000 interrupt TMMK000 0 lt Changing duty CR010 gt NOU BP WYN While interrupts and timer output inversion are disabled 1 to 4 above timer counting is continued If the value to be set in CROn0 is small the value of TM00 may exceed CROn0 Therefore set the value considering the time lapse of the timer clock and CPU clock after an INTTMO0O interrupt has been Disable the timer output inversion operation at the match between TM00 and CRO10 TOC004 0 Disable the INTTM000 interrupt TMMKO000 1 Rewrite CR 010 Wait for 1 cycle of the TM0O count clock Enable the timer output inversion operation at the match between TMO00 and CRO10 TOC004 1 Clear
103. to 1 with the ADCE bit 0 Take measures such as polling the A D conversion end interrupt request INTAD and removing the first conversion result 9 A D conversion result register ADCR ADCRH read operation When a write operation is performed to the A D converter mode register ADM and analog input channel specification register ADS the contents of ADCR and ADCRH may become undefined Read the conversion result following conversion completion before writing to ADM and ADS Using a timing other than the above may cause an incorrect conversion result to be read 10 Internal equivalent circuit The equivalent circuit of the analog input block is shown below Figure 10 21 Internal Equivalent Circuit of ANIn Pin eg E EATE O eel See Rout Rin ANIn a a i i Cout T Cw LSI internal Table 10 4 Resistance and Capacitance Values Reference Values of Equivalent Circuit 4 5 V lt AVrer lt 5 5 V 2 7 V lt AVrer lt 4 5 V Remarks 1 The resistance and capacitance values shown in Table 10 4 are not guaranteed values 2 n 0to3 3 Rout Allowable signal source impedance Rin Analog input equivalent resistance Cin Analog input equivalent capacitance Court Internal pin capacitance 178 Preliminary User s Manual U17446EJ1VOUD CHAPTER 11 SERIAL INTERFACE UART6 11 1 Functions of Serial Interface UART6 Serial interface UARTE6 has the following two modes 1 Operation stop mode This mode is used when serial co
104. used to erase a specified block Specify the block number before execution Block blank check This command is used to check if data in a specified block has been erased Specify the block number then execute this command Byte write 282 This command is used to write 1 byte data to the specified address in the flash memory Specify the write address and write data then execute this command Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY 19 8 2 Cautions on self programming function If an interrupt occurs during self programming the interrupt request flag is set 1 and interrupt servicing is performed after the self programming mode is released To avoid this operation disable interrupt servicing by setting MKO and MK1 to FFH and executing the DI instruction during self programming or before a mode is shifted from the normal mode to the self programming mode with a specific sequence No instructions can be executed while a self programming command is being executed Therefore clear and restart the watchdog timer counter in advance so that the watchdog timer does not overflow during self programming Refer to Table 19 11 for the time taken for the execution of self programming RAM is not used while a self programming command is being executed If the supply voltage drops or the reset signal is input while the flash memory is being written or erased writing erasing is not guaranteed The
105. while the INTST6 interrupt is being serviced after transmission of one data frame data can be continuously transmitted and an efficient communication rate can be realized In addition the TXB6 register can be efficiently written twice 2 bytes without having to wait for the transmission time of one data frame by reading bit O TXSF6 of asynchronous serial interface transmission status register 6 ASIF6 when the transmission completion interrupt has occurred To transmit data continuously be sure to reference the ASIF6 register to check the transmission status and whether the TXB6 register can be written and then write the data Cautions 1 The TXBF6 and TXSF6 flags of the ASIF6 register change from 10 to 11 and to 01 during continuous transmission To check the status therefore do not use a combination of the TXBF6 and TXSF6 flags for judgment Judge whether continuous transmission is possible or not by reading only the TXBF flag When the device is incorporated in a LIN the continuous transmission function cannot be used Make sure that asynchronous serial interface transmission status register 6 ASIF6 is 00H before writing transmit data to transmit buffer register 6 TXB6 Writing enabled TXBF6 Writing to TXB6 Register 0 1 Writing disabled Caution To transmit data continuously write the first transmit data first byte to the TXB6 register Be sure to check that the TXBF6 flag is 0
106. with hysteresis characteristics Input enable Type 16 B Feedback cut off P ch De m Xi enable IN OUT IN OUT VoD 3 H z Output disable Pull up enable Vpop E ou gt Er Output disable IN OUT Output Disable Preliminary User s Manual U17446EJ1VOUD 27 CHAPTER 3 CPU ARCHITECTURE 3 1 Memory Space The 78K0S KB1 can access up to 64 KB of memory space Figures 3 1 and 3 2 show the memory maps Figure 3 1 Memory Map u PD78F9232 a Se FFFFH Special function registers SFR 256 x 8 bits FFOOH FEFFH Internal high speed RAM 256 x 8 bits FEOOH FDFFH Use prohibited Data memory space OFFFH 1000H 4 OFFFH Program area 0082H 0081H Protect byte area H Option byte area Program memory Flash memory 7 8 H p y ba 4 096 x 8 bits CALLT table area 0040H Program area Vector table area y 0000H 0000H Remark The option byte and protect byte are 1 byte each 28 Preliminary User s Manual U17446EJ1VOUD CHAPTER 3 CPU ARCHITECTURE Figure 3 2 Memory Map u PD78F9234 l FFFFH Special function registers SFR 256 x 8 bits FFOOH FEFFH Internal high speed RAM 256 x 8 bits FEOOH FDFFH Use prohibited Data memory space 1FFFH 2000H 1FFFH Program area 0082H Flash memory 0081H Protect byte area Pr
107. 0 and 1 to 0 Before setting the INTMO register be sure to set the corresponding interrupt mask flag xxMKx 1 to disable interrupts After setting the INTMO register clear the interrupt request flag xxIFx 0 then clear the interrupt mask flag xxMKx 0 which will enable interrupts INTM1 External interrupt mode register 1 Be sure to clear bits 2 to 7 to 0 Before setting INTM1 set PMK3 to 1 to disable interrupts To enable interrupts clear PIF3 to 0 then clear PMK3 to 0 Interrupt request pending Interrupt requests will be held pending while the interrupt request flag registers 0 1 IFO IF1 or interrupt mask flag registers 0 1 MKO MK1 are being accessed Preliminary User s Manual U17446EJ1VOUD APPENDIX D LIST OF CAUTIONS Chapter 14 Hard Soft Classification Function Standby function Details of Function Cautions The LSRSTOP setting is valid only when Can be stopped by software is set for the low speed Ring OSC oscillator by the option byte 14 18 STOP mode When shifting to the STOP mode be sure to stop the peripheral hardware operation before executing STOP instruction except the peripheral hardware that operates on the low speed Ring OSC clock STOP mode HALT mode The following sequence is recommended for operating current reduction of the A D converter when the standby fu
108. 010 registers to 0000H p 118 16 bit timer counter 00 starts operating as soon as a value other than 00 p 119 Q operation stop mode is set to the TMC002 and TMC003 bits g Timer start errors An error of up to one clock may occur in the time required for a match signal to p 120 _ be generated after timer start This is because 16 bit timer counter 00 TM00 is started asynchronously to the count clock 5 One shot pulse One shot pulse output normally operates only in the free running mode or in p 121 K output the clear amp start mode at the valid edge of the TI000 pin Because an overflow does not occur in the clear amp start mode on a match between TMOO and CROOO one shot pulse output is not possible Capture If both the rising and falling edges are selected as the valid edges of the TIO00 p 123 operation pin capture is not performed When the CRCO001 bit value is 1 the TMOO count value is not captured inthe p 123 CROO00 register when a valid edge of the T1010 pin is detected but the input from the T1010 pin can be used as an external interrupt source because INTTMOOO0 is generated at that timing Changing With the 16 bit timer capture compare register On0 CROnO used as a p 124 C compare register compare register when changing CROnO around the timing of a match during timer between 16 bit timer counter 00 TMOO and 16 bit timer capture compare operation register OnO CROn0 during timer counting the change timing may
109. 1 136 8 bit timer mode control register 80 TMC80 129 10 bit A D conversion result register ADCR 167 16 bit timer capture compare register 000 CROOO 87 16 bit timer capture compare register 010 CRO10 89 16 bit timer counter 00 TMOO 87 16 bit timer mode control register 00 TMCO0 90 16 bit timer output control register 00 TOCOO0 93 16 bit multiplication result storage register H MULOH 37 217 16 bit multiplication result storage register L MULOL 37 217 A A D converter mode register ADM 164 Analog input channel specification register ADS 167 Asynchronous serial interface control register 6 ASICL6 192 Asynchronous serial interface operation mode register 6 ASIM6 186 Asynchronous serial interface reception error status register 6 ASIS6 188 Asynchronous serial interface transmission status register 6 ASIF6 189 B Baud rate generator control register 6 BRGC6 191 C Capture compare control register 00 CRCOO 92 Clock selection register 6 CKSR6 190 E External interrupt mode register 0 INTMO 227 External interrupt mode register 1 INTM1 228 F Flash address pointer H FLAPH 288 Flash address pointer L FLAPL 288 Flash address pointer H compare register FLAPHC 288 Flash address pointer L compare register FLAPLC 288 Flash programming command register FLCMD 287 Flash programming
110. 10 A D CONVERTER 10 4 A D Converter Operations 10 4 1 Basic operations of A D converter lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt 6 gt lt 7 gt lt 8 gt lt Q gt lt 10 gt lt 11 gt lt 12 gt Select one channel for A D conversion using the analog input channel specification register ADS Set ADCE to 1 and wait for 1 ws or longer Execute two NOP instructions or an instruction equivalent to two machine cycles Set ADCS to 1 and start the conversion operation lt 5 gt to lt 11 gt are operations performed by hardware The voltage input to the selected analog input channel is sampled by the sample amp hold circuit When sampling has been done for a certain time the sample amp hold circuit is placed in the hold state and the input analog voltage is held until the A D conversion operation has ended Bit 9 of the successive approximation register SAR is set The D A converter voltage tap is set to 1 2 AVreF by the tap selector The voltage difference between the D A converter voltage tap and analog input is compared by the voltage comparator If the analog input is greater than 1 2 AVrer the MSB of SAR remains set to 1 If the analog input is smaller than 1 2 AVrer the MSB is reset to 0 Next bit 8 of SAR is automatically set to 1 and the operation proceeds to the next comparison The D A converter voltage tap is selected according to the preset value of bit 9 as described belo
111. 10 gt Byte write processing is normally terminated Note This setting is not required when the watchdog timer is not used Caution If a write results in failure erase the block once and write to it again Preliminary User s Manual U17446EJ1VOUD 303 CHAPTER 19 FLASH MEMORY Figure 19 24 Example of Byte Write Operation in Self Programming Mode lt 1 gt Set byte write command FLCMD 05H lt 2 gt Set no of block to be written to FLAPH lt 3 gt Set address at which data is to be written to FLAPL lt 4 gt Set data to be written to FLW lt 5 gt Clear PFS lt 6 gt Clear amp restart WDT counter WDTE ACH Note lt 7 gt Execute HALT instruction lt B gt Check execution resul Abnormal VCERR and WEPRERR flags Normal lt 10 gt Normal termination Note This setting is not required when the watchdog timer is not used lt 9 gt Abnormal termination Remark lt 1 gt to lt 10 gt in Figure 19 24 correspond to lt 1 gt to lt 10 gt in 19 8 8 previous page 304 Preliminary User s Manual U17446EJ1VOUD An example of a program list that performs a byte write in self programming mode is shown below START FlashWrite MOV FLCMD 05H MOV FLAPH 07H MOV FLAPL 20H MOV FLW 10H MOV PFS 00H MOV WDTE 0ACH HALT MOV A PFS MOV CmdStatus A END Sets flash control command byte write Sets address to which data is to be written with FLAPH block 7 is spec
112. 19 7 Signal Collision RESET Pin 78K0S KB1 Dedicated flash programmer Signal collision connection signal RESET O Reset signal generator In the flash memory programming mode the signal output by the reset signal generator collides with the signal output by the dedicated flash programmer Therefore isolate the signal of the reset signal generator 19 6 3 Port pins When the flash memory programming mode is set all the pins not used for flash memory programming enter the same status as that immediately after reset If external devices connected to the ports do not recognize the port status immediately after reset the port pin must be connected to Voo or Vss via a resistor The state of the pins in the self programming mode is the same as that in the HALT mode 19 6 4 Power supply Connect the Voo pin to Voo of the flash programmer and the Vss pin to Vss of the flash programmer Supply the same other power supplies AVrer and AVss as those in the normal operation mode 276 Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY 19 7 On Board and Off Board Flash Memory Programming 19 7 1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory Figure 19 8 Flash Memory Manipulation Procedure Flash memory programming mode is set Manipulate flash memory Preliminary User s Manual U17446EJ1VOUD 277 CHAPTER 19 FLASH MEMORY 19 7 2 Flash me
113. 2 PMK2 INTP3 PIF3 PMK3 INTTM80 TMIF80 TMMK80 INTSRE6 SREIF6 SREMK6 INTSR6 SRIF6 SRMK6 INTST6 STIF6 STMK6 224 Preliminary User s Manual U17446EJ1VOUD CHAPTER 13 INTERRUPT FUNCTIONS Preliminary U4 0 72bvPT FUNCTIONS CHAPTER 13 INTERRUPT FUNCTIONS 2 Interrupt mask flag registers 0 1 MKO MK1 The interrupt mask flag is used to enable and disable the corresponding maskable interrupts MKO and MK1 are set with a 1 bit or 8 bit memory manipulation instruction Generation of reset signal sets MKO and MK1 to FFH Figure 13 3 Format of Interrupt Mask Flag Registers 0 1 MKO MK1 Address FFE4H After reset FFH R W Symbol lt 7 ADMK TMMK010 TMMKOOO TMMKH1 PMK1 PMKO LVIMK JEA Address FFE5H After reset FFH R W Symbol RDE STMK6 SRMK6 SREMK6 TMMK80 PMK3 PMK2 JEA Interrupt servicing control Enables interrupt servicing Disables interrupt servicing Caution Because P30 P31 P41 and P43 have an alternate function as external interrupt inputs when the output level is changed by specifying the output mode of the port function an interrupt request flag is set Therefore the interrupt mask flag should be set to 1 before using the output mode 226 Preliminary User s Manual U17446EJ1VOUD CHAPTER 13 INTERRUPT FUNCTIONS 3 External interrupt mode register 0 INTMO This register is used to set the valid edge of INTPO to INTP2 INTMO is set with an 8 bit memory manipulation instruction Reset sign
114. 2 and can be specified in 1 bit units PMC2 is set by using a 1 bit or 8 bit memory manipulation instruction Generation of reset signal sets PMC2 to OOH Figure 4 17 Format of Port Mode Control Register 2 Address FF84H After reset OOH R W Symbol 7 6 5 4 3 2 1 0 Specification of operation mode n 0 to 3 Port mode A D converter mode Table 4 3 Setting of Port Mode Register Port Register Output Latch and Port Mode Control Register When Alternate Function Is Used Alternate Function Pin Name P20 to P23 ANIO to ANI3 P30 T1000 INTPO TOOO T1010 INTP2 INTP3 TOH1 TxD6 INTP1 RxD6 Remark x don t care PMxx Port mode register Pxx Port register output latch of port PMC2x Port mode control register 66 Preliminary User s Manual U17446EJ1VOUD CHAPTER 4 PORT FUNCTIONS 4 Pull up resistor option registers PU0 PU2 PU3 PU4 and PU12 These registers are used to specify whether an on chip pull up resistor is connected to POO to P03 P20 to P23 P30 to P33 P40 to P47 P120 and P123 By setting PUO PU2 PU3 PU4 or PU12 an on chip pull up resistor can be connected to the port pin corresponding to the bit of PUO PU2 PU3 PU4 or PU12 PUO PU2 PU3 PU4 and PU12 are set by using a 1 bit or 8 bit memory manipulation instruction Generation of reset signal set these registers to OOH Figure 4 18 Format of Pull up Resistor O
115. 2 gt If the TMOO operation is stopped while the TIOnO pin is high level TMOO operation is then enabled after a low level is input to the TIOnO pin gt If the falling edge or both rising and falling edges are specified as the valid edge of the TlOn0 pin a falling edge is detected immediately after the TM00O operation is enabled lt 3 gt If the TMOO operation is stopped while the Tl0n0 pin is low level TMOO operation is then enabled after a high level is input to the TIOnO pin If the rising edge or both rising and falling edges are specified as the valid edge of the TlOn0 pin a rising edge is detected immediately after the TMOO operation is enabled Preliminary User s Manual U17446EJ1VOUD p 95 APPENDIX D LIST OF CAUTIONS Function 16 bit timer event counter 00 Hard Classification Chapter 6 Soft Hard Soft 370 Details of Function PRMOO Prescaler mode register 00 Cautions The sampling clock used to eliminate noise differs when a TIOOO valid edge is used as the count clock and when it is used as a capture trigger In the former case the count clock is fxp and in the latter case the count clock is selected by prescaler mode register 00 PRMOO The capture operation is not performed until the valid edge is sampled and the valid level is detected twice thus eliminating noise with a short pulse width 5 18 p 95 O When using P31 as the input pin T1010 o
116. 20H to FF1FH Immediate data or labels saddrp FE20H to FF1FH Immediate data or labels even addresses only addr16 0000H to FFFFH Immediate data or labels only even addresses for 16 bit data transfer instructions addr5 0040H to 007FH Immediate data or labels even addresses only word 16 bit immediate data or label byte 8 bit immediate data or label bit 3 bit immediate data or label Remark For symbols of special function registers see Table 3 3 Special Function Registers Preliminary User s Manual U17446EJ 1VOUD 327 CHAPTER 20 INSTRUCTION SET OVERVIEW 20 1 2 Description of Operation column RE On os w o a O Te Om Ee EAE PSW CY AC Z IE XH XL A v vi addr16 jdisp8 A register 8 bit accumulator X register B register C register D register E register H register L register AX register pair 16 bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Interrupt request enable flag Memory contents indicated by address or register contents in parentheses Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data 16 bit immediate data or label Signed 8 bit data displacement value 20 1 3 Description of Flag column Blank 0 1 x R 328 Unchanged Cl
117. 5 TXS6 Transmit shift register 6 185 W WDTE Watchdog timer enable register 152 WDTM Watchdog timer mode register 151 Preliminary User s Manual U17446EJ1VOUD 365 APPENDIX D LIST OF CAUTIONS This appendix lists cautions described in this document Classification hard soft in table is as follows Hard Soft Function Pin Configu ration Hard Classification Chapter 1 Details of Function AVss pin Cautions for microcontroller internal external hardware Cautions for software such as register settings or programs Cautions Connect the AVss pin to Vss 1 18 Pin Functions Chapter 2 P121 X1 and P122 X2 pins The P121 X1 and P122 X2 pins are pulled down during reset Chapter 3 Vector Table Address No interrupt sources correspond to the vector table address 0014H SP Stack pointer Since generation of reset signal makes the SP contents undefined be sure to initialize the SP before using the stack memory Port function lt Q Z O P121 X1 and P122 X2 pins The P121 X1 and P122 X2 pins are pulled down during reset P34 pin Because the P34 pin functions alternately as the RESET pin if it is used as an input port pin the function to input an external reset signal to the RESET pin cannot be used The function of the port is selected by the option byte For details refer to CHAPTER 18 OPTION BYTE
118. 5 0 V 10 Nte4 When A D converter Wh Ipp3 is stopped Note 7 operating mode en A D converter is operating fx 8 MHz Voo 5 0 V 10 N 4 High speed R ing OSC HALT mode When When peripheral functions are stopped peripheral functions are operating STOP mode Voo 5 0 V 10 n When When low speed Ring OSC is stopped low speed Ring OSC is operating Voo 3 0 V 10 low speed Ring OSC is stopped When low speed Ring OSC is operating Use this product in a voltage range of 2 2 to 5 5 V because the detection voltage Vroc of the power on clear POC circuit is 2 1 V 0 1 V Total current flowing through the internal power supply Voo Peripheral operation current is included however the current that flows through the pull up resistors of ports is not included Peripheral operation current is included When the processor clock control register PCC is set to OOH When the processor clock control register PCC is set to 02H When crystal ceramic oscillation clock external clock input is selected as the system clock source using the option byte When the high speed Ring OSC is selected as the system clock source using the option byte The current that flows through the AVrer pin is included Preliminary User s Manual U17446E 1VOUD 341 CHAPTER 21 ELECTRICAL SPECIFICATIONS TARGET VALUES AC Characteristics 1 Basic operat
119. 6 0 or if data is transferred to transmit shift register 6 TXS6 If data is written to transmit buffer register 6 TXB6 if data exists in TXB6 TXSF6 Transmit shift register data flag If POWER6G 0 or TXE6 0 or if the next data is not transferred from transmit buffer register 6 TXB6 after completion of transfer If data is transferred from transmit buffer register 6 TXB6 if data transmission is in progress Cautions 1 To transmit data continuously write the first transmit data first byte to the TXB6 register Be sure to check that the TXBF6 flag is 0 If so write the next transmit data second byte to the TXB6 register If data is written to the TXB6 register while the TXBF6 flag is 1 the transmit data cannot be guaranteed 2 To initialize the transmission unit upon completion of continuous transmission be sure to check that the TXSF6 flag is 0 after generation of the transmission completion interrupt and then execute initialization If initialization is executed while the TXSF6 flag is 1 the transmit data cannot be guaranteed Preliminary User s Manual U17446EJ1VOUD 189 CHAPTER 11 SERIAL INTERFACE UART6 4 Clock selection register 6 CKSR6 This register selects the base clock of serial interface UART6 CKSR6 can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH Remark CKSR6 can be refreshed the same value is written
120. 6 16 BIT TIMER EVENT COUNTER 00 Cautions 1 Always set data to PRMOO after stopping the timer operation 2 If the valid edge of the T1000 pin is to be set as the count clock do not set the clear start mode and the capture trigger at the valid edge of the T1000 pin 3 In the following cases note with caution that the valid edge of the Tl0n0 pin is detected lt 1 gt Immediately after a system reset if a high level is input to the Tl0n0 pin the operation of the 16 bit timer counter 00 TM00 is enabled If the rising edge or both rising and falling edges are specified as the valid edge of the T10n0 pin a rising edge is detected immediately after the TM00 operation is enabled lt 2 gt If the TM00 operation is stopped while the Tl0n0 pin is high level TM00 operation is then enabled after a low level is input to the Tl0n0 pin If the falling edge or both rising and falling edges are specified as the valid edge of the Tl0n0 pin a falling edge is detected immediately after the TM00 operation is enabled lt 3 gt If the TM0O0 operation is stopped while the Tl0n0 pin is low level TM00 operation is then enabled after a high level is input to the Tl0n0 pin If the rising edge or both rising and falling edges are specified as the valid edge of the T10n0 pin a rising edge is detected immediately after the TM00 operation is enabled 4 The sampling clock used to eliminate noise differs when a T1000 valid edge is used as the count clock and
121. 7 to 0 are protected Blocks 18 to 31 can be written or erased Blocks 15 to 0 are protected Blocks 16 to 31 can be written or erased Blocks 13 to 0 are protected Blocks 14 to 31 can be written or erased Blocks 11 to 0 are protected Blocks 12 to 31 can be written or erased Blocks 9 to 0 are protected Blocks 10 to 31 can be written or erased Blocks 7 to 0 are protected Blocks 8 to 31 can be written or erased Blocks 5 to 0 are protected Blocks 6 to 31 can be written or erased Blocks 3 to 0 are protected Blocks 4 to 31 can be written or erased Blocks 1 and 0 are protected Blocks 2 to 31 can be written or erased 1 All blocks can be written or erased Other than above Setting prohibited 290 Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY 19 8 4 Example of shifting normal mode to self programming mode The operating mode must be shifted from normal mode to self programming mode before performing self programming An example of shifting to self programming mode is explained below lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt Disable interrupts if the interrupt function is used by setting the interrupt mask flag registers MKO MK1 to FFH and executing the DI instruction Clear the flash status register PFS Set self programming mode using a specific sequence e Write a specific value ASH to PFCMD
122. 78KOS NS or IE 78KOS NS A Notes 1 2 Language processing software e Assembler package e C compiler package e Device file e C library source file Flash memory writing environment Note 1 Control software e Project Manager Windows version only te Flash programmer writing Flash memory adapter Flash memory e Software package Debugging software e Integrated debugger e System simulator Host machine PC or EWS Interface adapter Power supply unit In circuit emulator 3 Emulation boardNo 4 Target cable or emulation probe Pin header or conversion socket Target system The C library source file is not included in the software package The Project Manager PM plus is included in the assembler package PM plus is used only in the Windows environment All products other than the in circuit emulators IE 78KOS NS and IE 78KOS NS A are optional The in circuit emulator IE 789234 NS EM1 is provided with the target cable Preliminary User s Manual U17446EJ1VOUD 351 APPENDIX A DEVELOPMENT TOOLS Figure A 1 Development Tools 2 2 2 When using the in circuit emulator QB 78KOSKX1MINI e Software package Language processing software Debugging software e Assembler package e C compiler package e Device file e C library source file e Integrate
123. APL to 00H Sets blank check block compare number same value as that of FLAPH Fixes FLAPLC to FFH Clears flash status register Clears amp restarts WDT Self programming is started Execution result is stored in variable CmdStatus 0 normal termination other than 0 abnormal termination Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY 19 8 8 Example of byte write operation in self programming mode An example of the byte write operation in self programming mode is explained below lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt 6 gt lt 7 gt lt 8 gt lt 9 gt Set 05H byte write to the flash program command register FLCMD Set the number of block to which data is to be written to flash address pointer H FLAPH Set the address at which data is to be written to flash address pointer L FLAPL Set the data to be written to the flash write buffer register FLW Clear the flash status register PFS Write ACH to the watchdog timer enable register WDTE clear and restart the watchdog timer counter Execute the HALT instruction then start self programming Execute an instruction immediately after the HALT instruction if self programming has been executed Check if a self programming error has occurred using bit 1 VCERR and bit 2 WEPRERR of PFS Abnormal lt 9 gt Normal lt 10 gt Byte write processing is abnormally terminated lt
124. BIT TIMER EVENT COUNTER 00 Functions of 16 Bit Timer Event Counter 00 bit timer event counter 00 has the following functions Interval timer 16 bit timer event counter 00 generates interrupt requests at the preset time interval e Number of counts 2 to 65536 External event counter 16 bit timer event counter 00 can measure the number of pulses with a high low level width of a signal input externally e Valid level pulse width 16 fxp or more Pulse width measurement 16 bit timer event counter 00 can measure the pulse width of an externally input signal e Valid level pulse width 2 fxe or more Square wave output 16 bit timer event counter 00 can output a square wave with any selected frequency e Cycle 2 x 2 to 65536 x 2 x count clock cycle PPG output 16 bit timer event counter 00 can output a square wave that have arbitrary cycle and pulse width e 1 lt Pulse width lt Cycle lt FFFF 1 H One shot pulse output 16 bit timer event counter 00 can output a one shot pulse for which output pulse width can be set to any desired value Preliminary User s Manual U17446E 1VOUD 85 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 6 2 Configuration of 16 Bit Timer Event Counter 00 16 bit timer event counter 00 consists of the following hardware Table 6 1 Configuration of 16 Bit Timer Event Counter 00 Timer counter 16 bit timer counter 00 TM00 Register 16 bit timer capture compare registers 000 010 CRO00 CR010 Tim
125. Control Register 6 BRGC6 Address FF97H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 BRGC6 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 Output clock selection of 8 bit counter Setting prohibited fxcike 8 fxcike 9 fxcLke 10 fxcLke 252 fxcike 253 fxcLke 254 fxcike 255 Cautions 1 Make sure that bit 6 TXE6 and bit 5 RXE6 of the ASIM6 register 0 when rewriting the MDL67 to MDL60 bits 2 The baud rate is the output clock of the 8 bit counter divided by 2 Remarks 1 fxcixe Frequency of base clock selected by the TPS63 to TPS60 bits of CKSR6 register 2 k Value set by MDL67 to MDL60 bits k 8 9 10 255 3 x Don t care Preliminary User s Manual U17446EJ1VOUD 191 6 CHAPTER 11 SERIAL INTERFACE UART6 Asynchronous serial interface control register 6 ASICL6 This register controls the serial communication operations of serial interface UART6 ASICL6 can be set by a 1 bit or 8 bit memory manipulation instruction Generation of reset signal sets this register to 16H Caution ASICL6 can be refreshed the same value is written by software during a communication operation when bit 7 POWER6 and bit 6 TXE6 of ASIM6 1 or bit 7 POWER6 and bit 5 RXE6 of ASIM6 1 However if the SBRT6 1 and SBTT 1 are set in the refresh operation during the SBF reception SBRF6 1 or SBF transmission between the SBTT6 setting 1
126. D6 P44 8 Port mode register 4 PM4 This register sets port 4 input output in 1 bit units When using the P43 TxD6 INTP1 pin for serial interface data output clear PM43 to 0 and set the output latch of P43 to 1 When using the P44 RxD6 pin for serial interface data input set PM44 to 1 The output latch of P44 at this time may be 0 or 1 PM4 can be set by a 1 bit or 8 bit memory manipulation instruction Generation of reset signal sets this register to FFH Figure 11 12 Format of Port Mode Register 4 PM4 Address FF24H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM4 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 P4n pin I O mode selection n 0 to 7 Output mode output buffer on Input mode output buffer off 194 Preliminary User s Manual U17446EJ1VOUD CHAPTER 11 SERIAL INTERFACE UART6 11 4 Operation of Serial Interface UART6 Serial interface UARTE6 has the following two modes e Operation stop mode e Asynchronous serial interface UART mode 11 4 1 Operation stop mode In this mode serial communication cannot be executed therefore the power consumption can be reduced In addition the pins can be used as ordinary port pins in this mode To set the operation stop mode clear bits 7 6 and 5 POWERG TXE6 and RXE6 of ASIM6 to 0 1 Register used The operation stop mode is set by asynchronous serial interface operation mode register 6 ASIM6 ASIM6 can be set by a 1 bit or 8 bit memory manipulation instr
127. DCRH write is not performed nor is the conversion end interrupt signal INTAD generated p 176 O Noise countermeasures To maintain the 10 bit resolution attention must be paid to noise input to the AVrer pin and pins ANIO to ANI3 lt 1 gt Connect a capacitor with a low equivalent resistance and a high frequency response to the power supply lt 2 gt Because the effect increases in proportion to the output impedance of the analog input source it is recommended that a capacitor be connected externally as shown in Figure 10 19 to reduce noise lt 3 gt Do not switch the A D conversion function of the ANIO to ANI3 pins to their alternate functions during conversion lt 4 gt The conversion accuracy can be improved by setting HALT mode immediately after the conversion starts p 176 O ANIO P20 to ANI3 P23 The analog input pins ANIO to ANI3 are also used as input port pins P20 to P23 When A D conversion is performed with any of ANIO to ANI3 selected do not access port 2 P20 to P23 while conversion is in progress otherwise the conversion resolution may be degraded p 177 If a digital pulse is applied to the pins adjacent to the pins currently used for A D conversion the expected value of the A D conversion may not be obtained due to coupling noise Therefore do not apply a pulse to the pins adjacent to the pin undergoing A D conversion p 177 Input imped
128. EJ1VOUD CHAPTER 11 SERIAL INTERFACE UART6 c Normal transmission The TxD6 pin outputs a high level when bit 7 POWER6 of asynchronous serial interface operation mode register 6 ASIM6 is set to 1 If bit 6 TXE6 of ASIM6 is then set to 1 transmission is enabled Transmission can be started by writing transmit data to transmit buffer register 6 TXB6 The start bit parity bit and stop bit are automatically appended to the data When transmission is started the data in TXB6 is transferred to transmit shift register 6 TXS6 After that the data is sequentially output from TXS6 to the TxD6 pin When transmission is completed the parity and stop bits set by ASIM6 are appended and a transmission completion interrupt request INTST6 is generated Transmission is stopped until the data to be transmitted next is written to TXB6 Figure 11 15 shows the timing of the transmission completion interrupt request INTST6 This interrupt occurs as soon as the last stop bit has been output Figure 11 15 Normal Transmission Completion Interrupt Request Timing 1 Stop bit length 1 TxD6 output INTST6 2 Stop bit length 2 TxD6 output INTST6 Preliminary User s Manual U17446EJ1VOUD 201 202 CHAPTER 11 SERIAL INTERFACE UART6 d Continuous transmission The next transmit data can be written to transmit buffer register 6 TXB6 as soon as transmit shift register 6 TXS6 has started its shift operation Consequently even
129. ER INDEX To learn the details of the instruction functions of the 78K 0S Series Refer to 78K 0S Series Instructions User s Manual U11047E separately available To learn the electrical specifications target of the 78KOS KB1 See CHAPTER 21 ELECTRICAL SPECIFICATIONS TARGET VALUES Preliminary User s Manual U17446EJ1VOUD Conventions Data significance Higher digits on the left and lower digits on the right Active low representation xxx overscore over pin or signal name Note Footnote for item marked with Note in the text Caution Information requiring particular attention Remark Supplementary information Numerical representation Binary xxxx or xxxxB Decimal xxxx Hexadecimal xxxxH Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such Documents Related to Devices 78KO0S KB1 User s Manual This manual 78K 0S Series Instructions User s Manual U11047E Documents Related to Development Software Tools User s Manuals Document Name Document No RA78KOS Assembler Package Operation U16656E Language U14877E Structured Assembly Language U11623E CC78KOS C Compiler Operation U16654E Language U14872E ID78KOS NS Ver 2 52 Integrated Debugger Operation U16584E ID78KOS QB Ver 2 81 Integrated Debugger Operation U17287E PM plus Ver 5 20 U16934E Do
130. FEDEH FEDEH E 48 Preliminary User s Manual U17446EJ1VOUD CHAPTER 4 PORT FUNCTIONS 4 1 Functions of Ports The 78KOS KB1 has the ports shown in Figure 4 1 which can be used for various control operations Table 4 1 shows the functions of each port In addition to digital I O port functions each of these ports has an alternate function For details refer to CHAPTER 2 PIN FUNCTIONS Figure 4 1 Port Functions Port 0 Port 4 a Port 2 Port 12 4 lk re Ports Port 13 Preliminary User s Manual U17446EJ1VOUD 49 Pin Name POO to P03 CHAPTER 4 PORT FUNCTIONS Table 4 1 Port Functions Function Port 0 4 bit I O port Can be set to input or output mode in 1 bit units On chip pull up resistor can be connected by setting software After Reset Input Alternate Function Pin P20 to P23 Port 2 4 bit I O port Can be set to input or output mode in 1 bit units On chip pull up resistor can be connected by setting software ANIO to ANI3 Port 3 Can be set to input or output mode in 1 bit units On chip pull up resistor can be connected by setting software TIOOO INTPO T1010 TOOO INTP2 Input only RESET Port 4 8 bit I O port Can be set to input or output mode in 1 bit units On chip pull up resistor can be connected setting software INTP3 TOH1 TxD6 INTP 1 RxD6 Port 12 4 bit I O port Can be set to input or output mode in 1 bit units On
131. FUNCTION 14 1 2 Registers used during standby 236 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 14 STANDBY FUNCTION 14 2 Standby Function Operation 14 2 1 HALT mode 1 HALT mode The HALT mode is set by executing the HALT instruction The operating statuses in the HALT mode are shown below Caution Because an interrupt request signal is used to clear the standby mode if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset the standby mode is immediately cleared if set Table 14 2 Operating Statuses in HALT Mode Setting of HALT Mode Low S peed Ring OSC Low Speed Ring OSC Can Be Stopped Cannot Be Stopped When Low Speed Ring When Low Speed Ring OSC Oscillation Continues OSC Oscillation Stops System clock Clock supply to CPU is stopped CPU Operation stops Port latch Holds status before HALT mode was set 16 bit timer event counter 00 Operable 8 bit timer 80 Operable 8 bit timer Sets count clock to fxr to fxe 2 Operable H1 Sets count clock to fri 2 Operable Operable Operation stops Watchdog System clock selected as Setting prohibited Operation stops timer operating clock Low speed Ring OSC clock Operable Operation Operation stops selected as operating clock continues A D converter Operable Serial interface UART6 Operable Power on clear circuit Always operates Low voltage dete
132. Figures 5 10 and 5 11 show the timing chart and status transition diagram of default start by the crystal ceramic oscillator Preliminary User s Manual U17446EJ1VOUD 79 80 CHAPTER 5 CLOCK GENERATORS Figure 5 10 Timing Chart of Default Start by Crystal Ceramic Oscillator a Voo RESET H Internal reset b System clock f c i i Crystal ceramic CPU clock i 7 f oscillator clock I PGC 02H PPCC 02H tog m Option byte is read Clock oscillation 1 System clock is selected l stabilization 1 Operation stops 1 timeNote2 Notes 1 Operation stop time is 276 ws MIN 544 ws TYP and 1 074 ms MAX 2 The clock oscillation stabilization time for default start is selected by the option byte For details refer to CHAPTER 18 OPTION BYTE The oscillation stabilization time that elapses after the STOP mode is released is selected by the oscillation stabilization time select register OSTS a The internal reset signal is generated by the power on clear function on power application the option byte is referenced after reset and the system clock is selected b After high speed Ring OSC clock is generated the option byte is referenced and the system clock is c selected In this case the crystal ceramic oscillator clock is selected as the system clock If the system clock is the crystal ceramic oscillator clock it starts operating as the CPU clock after clock oscillatio
133. HP ws HPI _ HRT HR wl PIL BIL NININI NI RIT NIT WI NIN R LR fl Rl eRe saddr saddr 1 then PC PC 3 jdisp8 if saddr 0 No Operation IE lt 1 Enable Interrupt IE lt 0 Disable Interrupt Set HALT Mode SetSTOP Mode Remark One instruction clock cycle is one CPU clock cycle fcpu selected by the processor clock control register PCC Preliminary User s Manual U17446EJ 1VOUD 333 CHAPTER 20 INSTRUCTION SET OVERVIEW 20 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP INC DEC ROR ROL RORC ROLC PUSH POP DBNZ 2nd Operand laddr16 HL byte addr16 1st Operand movnete XcHNete ADD ADDC SUB SUBC AND OR XOR CMP laddr16 PSW DE HL HL byte Note Exceptr A 334 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 20 INSTRUCTION SET OVERVIEW 2 16 bit instructions MOVW XCHW ADDW SUBW CMPW PUSH POP INCW DECW 2nd Operand Ist Operand ADDW SUBW CMPW MOVW movwNee Note Only when rp BC DE or HL 3 Bit manipulation instructions SET1 CLR1 NOT1 BT BF 2nd Operand addr16 1st Operand A bit Sfr bit saddr bit PSW bit HL bit CY Preliminary User s Manual U17446EJ 1VOUD 335 CHAPTER 20 INSTRUCTION SET
134. IMER EVENT COUNTER 00 6 4 5 PPG output operations Setting 16 bit timer mode control register 00 TMC00 and capture compare control register 00 CRC00 as shown in Figure 6 29 allows operation as PPG Programmable Pulse Generator output Setting The basic operation setting procedure is as follows lt l gt lt 2 gt Set the CRCO0O register see Figure 6 29 for the set value Set any value to the CR000 register as the cycle Set any value to the CR010 register as the duty factor Set the TOC00 register see Figure 6 29 for the set value Set the count clock by using the PRMOO register Set the TMCO0 register to start the operation see Figure 6 29 for the set value Caution Changing the CRCOn0 setting during TM00 operation may cause a malfunction To change the setting refer to 6 5 Cautions Related to 16 Bit Timer Event Counter 00 17 Changing compare register during timer operation Remarks 1 For the setting of the TO00 pin see 6 3 5 Port mode register 3 PM3 2 For how to enable the INTTMO000 interrupt see CHAPTER 13 INTERRUPT FUNCTIONS 3 n Oorl In the PPG output operation rectangular waves are output from the TO00 pin with the pulse width and the cycle that correspond to the count values preset in 16 bit timer capture compare register 010 CRO10 and in 16 bit timer capture compare register 000 CR000 respectively 112 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 6 16 BIT TIMER EVE
135. INTyy is not acknowledged and multiple interrupts are not generated The INTyy request is held pending and acknowledged after the INTxx servicing is performed IE 0 Interrupt request acknowledgment disabled 232 Preliminary User s Manual U17446EJ1VOUD CHAPTER 13 INTERRUPT FUNCTIONS 13 4 3 Interrupt request pending Some instructions may keep pending the acknowledgment of an instruction request until the completion of the execution of the next instruction even if the interrupt request maskable interrupt and external interrupt is generated during the execution The following shows such instructions interrupt request pending instruction e Manipulation instruction for interrupt request flag registers 0 1 IFO IF1 e Manipulation instruction for interrupt mask flag registers 0 1 MKO MK1 Preliminary User s Manual U17446EJ1VOUD 233 CHAPTER 14 STANDBY FUNCTION 14 1 Standby Function and Configuration 14 1 1 Standby function Table 14 1 Relationship Between Operation Clocks in Each Operation Status Low S peed Ring OSC Oscillator System Clock Clock Supplied to Note 2 Peripheral Hardware Operation Mode LSRSTOP 0 LSRSTOP 1 Stopped Stopped Stopped Note 3 Oscillating Oscillating Stopped Oscillating Oscillating Notes 1 When Cannot be stopped is selected for low speed Ring OSC by the option byte 2 When itis selected that the low speed Ring OSC oscillator can be stopped by softw
136. LOCK GENERATORS Figure 5 12 Timing of Default Start by External Clock Input Voo RESET H Internal reset s b CPU clock External clock input i PCC 02H PPCC 02H Option byte is read System clock is selected Operation stops t i i m i i i i Note Operation stop time is 277 us MIN 544 us TYP and 1 075 ms MAX a The internal reset signal is generated by the power on clear function on power application the option byte is referenced after reset and the system clock is selected b The option byte is referenced and the system clock is selected Then the external clock operates as the system clock Figure 5 13 Status Transition of Default Start by External Clock Input Power application Voo gt 2 1 V 0 1 V Reset by power on clear Reset signal External clock input selected by option byte Start with PCC 02H PPCC 02H Clock division ratio variable during CPU operation Interrupt HALT Interrupt instruction stop instruction Remark PCC Processor clock control register PPCC Preprocessor clock control register 82 Preliminary User s Manual U17446EJ1VOUD CHAPTER 5 CLOCK GENERATORS 5 6 Operation of Clock Generator Supplying Clock to Peripheral Hardware 1 2 The following two types of clocks are supplied to the peripheral hardware e Clock to peripheral hardware fxp e Low speed Ring OSC clock fri Clock
137. NEC Preliminary User s Manual 78K0S KB1 8 Bit Single Chip Microcontrollers UPD78F9232 UPD78F9234 Documen t No U17446EJ1VOUDOO 1st edition Date Published April 2005 NS CP K NEC Electronics Corporation 2005 Printed in Japan MEMO 2 Preliminary User s Manual U17446EJ1VOUD NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between Vit MAX and Vin MIN due to noise etc the device may malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the input level passes through the area between Vit MAX and Vin MIN HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down circuitry Each unused pin should be connected to Voo or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device PRECAUTION AGAINST ESD A strong electr
138. NIO to ANI3 of the A D converter When using these pins as analog input pins refer to 10 6 Cautions for A D converter 5 ANIO P20 to ANI3 P23 2 2 3 P30 to P34 Port 3 P30 to P33 constitute a 4 bit I O port port 3 In addition to I O port pins P30 and p31 also have functions to input output a timer signal and input an external interrupt request signal P34 is a 1 bit input only port This pin is also used as a RESET pin For settings of alternate function refer to CHAPTER 18 OPTION BYTE When using P34 as input port pull up the P34 pin by using external resistor P30 to P33 can be set to the following operation modes in 1 bit units 1 2 Port mode P30 to P33 function as a 4 bit I O port Each bit of this port can be set to the input or output mode by using port mode register 3 PM3 In addition an on chip pull up resistor can be connected to the port by using pull up resistor option register 3 PU3 P34 functions as a 1 bit input only port Control mode P30 and P31 function to input output signals to from internal timers and to input an external interrupt request signal a INTPO and INTP2 These are external interrupt request input pins for which the valid edge rising edge falling edge or both rising and falling edges can be specified b T1000 This pin inputs an external count clock to 16 bit timer event counter 00 or a capture trigger signal to the capture registers CR000 and CR010 of 16 bit timer event c
139. NS Port mode registers PMO PM2 PM3 PM4 PM12 These registers are used to set the corresponding port to the input or output mode in 1 bit units Each port mode register can be set by a 1 bit or 8 bit memory manipulation instruction Generation of reset signal sets these registers to FFH When a port pin is used as an alternate function pin set its port mode register and output latch as shown in Table 4 3 Caution Because P30 P31 and P43 are also used as external interrupt pins the corresponding interrupt request flag is set if each of these pins is set to the output mode and its output level is changed To use the port pin in the output mode therefore set the corresponding interrupt mask flag to 1 in advance Figure 4 15 Format of Port Mode Register Address FF20H After reset FFH R W Symbol Address FF22H After reset FFH R W Symbol Address FF23H After reset FFH R W Symbol Address FF24H After reset FFH R W Symbol PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 Address FF2CH After reset FFH R W Symbol 7 PM12 64 6 5 4 3 2 1 0 Selection of I O mode of Pmn pin m 0 2 3 4 or 12 n 0 to 7 Output mode output buffer ON Input mode output buffer OFF Preliminary User s Manual U17446EJ1VOUD CHAPTER 4 PORT FUNCTIONS 2 Port registers P0 P2 P3 P4 P12 P13 These registers are used to write data to be output from the corresponding port pin to an external device connecte
140. NT COUNTER 00 Figure 6 29 Control Register Settings for PPG Output Operation a 16 bit timer mode control register 00 TMC00 4 TMC003 TMC002 TMC001 OVFOO Twco0 Geo Ip ore aca b Capture compare control register 00 CRC00 Clears and starts on match between TMO0 and CROOO 3 CRC002 CRC001 CRC000 cRCo0 fa ao ao Peo CR000 used as compare register CR010 used as compare register c 16 bit timer output control register 00 TOC00 7 OSPT00 OSPE00 TOC004 LVSOO LVROO TOC001 TOEOO Enables TOOO output Inverts output on match between TMOO and CROOO Specifies initial value of TOOO output F F setting 11 is prohibited Inverts output on match between TMOO and CRO10 Disables one shot pulse output d Prescaler mode register 00 PRM00 ES110 ES100 ES010 ES000 3 2 PRM001 PRM000 PRMOO 0 1 0 1 0 1 O Lo o 0 1 O 1 Selects count clock Setting invalid setting 10 is prohibited Setting invalid setting 10 is prohibited Cautions 1 Values in the following range should be set in CR000 and CRO10 0000H lt CR010 lt CR000 lt FFFFH 2 The cycle of the pulse generated through PPG output CR000 setting value 1 has a duty of CR010 setting value 1 CR000 setting value 1 Remark x Don tcare Preliminary User s Manual U17446E 1VOUD 113 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 Figure 6 30 Configuration Diagram o
141. OVERVIEW 4 Call instructions branch instructions CALL CALLT BR BC BNC BZ BNZ DBNZ 2nd Operand laddr16 addr5 addr16 1st Operand Basic instructions Compound instructions 5 Other instructions RET RETI NOP El DI HALT STOP 336 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 21 ELECTRICAL SPECIFICATIONS TARGET VALUES These specifications are only target values and may not be satisfied by mass produced products Absolute Maximum Ratings Ta 25 C Parameter Conditions Ratings Supply voltage 0 3 to 6 5 0 3 to 0 3 0 3 to Von 0 3 0 3 to 0 3 Input voltage POO to P03 P30 to P34 P40 to P47 P120 to 0 3 to Von 0 3 P123 P20 to 23 0 3 to AVrer 0 3 and 0 3 to Voo 0 3 Output voltage 0 3 to Voo 0 38 Analog input voltage AVss 0 3 to AVrer 0 3 and 0 3 to Von 0 3 Output current high Per pin 10 Total of pins 44 Output current low Per pin 20 Total of all pins 44 Operating ambient In normal operation mode 40 to 85 temperature During flash memory programming Storage temperature 40 to 125 Note Must be 6 5 V or lower Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and ther
142. P A 00H BNZ ModeOf fLoop Checks completion of write to specific registers Repeats the same processing when an error occurs MOV MKO INT_MKO Restores interrupt mask flag MOV MK1 INT_MK1 EI END 296 Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY 19 8 6 Example of block erase operation in self programming mode An example of the block erase operation in self programming mode is explained below lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt 6 gt lt 7 gt lt 8 gt lt Q gt Set 03H block erase to the flash program command register FLCMD Set the block number to be erased to flash address pointer H FLAPH Set flash address pointer L FLAPL to OOH Write the same value as FLAPH to the flash address pointer H compare register FLAPHC Set the flash address pointer L compare register FLAPLC to OOH Clear the flash status register PFS Write ACH to the watchdog timer enable register WDTE clear and restart the watchdog timer counter Execute the HALT instruction then start self programming Execute an instruction immediately after the HALT instruction if self programming has been executed Check if a self programming error has occurred using bit 1 VCERR and bit 2 WEPRERR of PFS Abnormal lt 10 gt Normal lt 11 gt lt 10 gt Block erase processing is abnormally terminated lt 11 gt Block erase processing is normally terminated Note This sett
143. P120 P123 P120 P123 PM120 PM123 Pull up resistor option register 12 Port register 12 Port mode register 12 Read signal Write signal Preliminary User s Manual U17446EJ1VOUD 61 CHAPTER 4 PORT FUNCTIONS Figure 4 13 Block Diagram of P121 and P122 Selector i WRpeort Internal bus P121 X1 P122 X2 Output latch P121 P122 PM121 PM122 Clock input PM12 Port mode register 12 P12 Port register 12 RD Read signal WRxx Write signal 4 2 6 Port 13 This is a 1 bit output only port Figure 4 14 shows the block diagram of port 13 62 Figure 4 14 Block Diagram of P130 RD Internal bus T WRport P13 Output latch 6 P13 Port register 13 RD Read signal WRxx Write signal Remark When a reset is input P130 outputs a low level If P130 outputs a high level immediately after reset is released the output signal of P130 can be used as a dummy CPU reset signal Preliminary User s Manual U17446EJ1VOUD CHAPTER 4 PORT FUNCTIONS 4 3 Registers Controlling Port Functions The ports are controlled by the following four types of registers e Port mode registers PMO PM2 PM3 PM4 PM12 e Port registers PO P2 P3 P4 P12 P13 e Port mode control register 2 PMC2 e Pull up resistor option registers PUO PU2 PU3 PU4 PU12 Preliminary User s Manual U17446EJ1VOUD 63 1 CHAPTER 4 PORT FUNCTIO
144. Paa R Ea E Paaa S 40 3 3 3 Table indir ct addressing sieten nan eine aaa TE NAE E ERAEN E R naa aS 40 3 3 4 Regist raddressSihg oyei ie o ae aea eE aa e aaa Eaa a A a aE E a Aaa aes 41 3 4 Operand Address Addressing sssssssessssrnennnrennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn na 42 3 4 1 Direct addressing sass sess teh enderrat aapa b apria diaa itp paie atape taii aan iaat 42 3 4 2 Short direct addreS ing 2c c aie a eee esto ee eee E 43 3 4 3 Special function register SFR addressing eee eeeeeceeneeeeeneeeeeeenaeeeseeeaeeeteeeeeesaeeeseeaeeesnneeeens 44 Preliminary User s Manual U17446EJ1VOUD 9 3 4 4 REGISTSF addresSSiNg sesaat aan ance ae iea iae rit eiden edea aataid eiia a it becsaeheitpeenss 45 3 4 5 Register indirect addressing isaning i e E i eve eee 46 3 4 6 Based addressing xcciiiscntntssisi inv on Ere een ea a ee a Sa ede 47 3 4 7 tak AUAKESSING EEEE A TE EAT A TE 48 CHAPTER 4 PORT FUNCTIONS aseena aeien eiriaa aeara e e Eren ennaa gues Aae EnA oR Paene dana taaa ina Sinia eres 49 AT FUNCtIONS OF POMS r a e a a dunesevdacceaesnsevvecuectcvaceadeunsseudcepdetecvesecctecegend 49 Aa Port COMPGUIATION oea A O A 51 4 2 1 KOI n O V E E E E EEA A E E E EA 52 4 2 2 lo p E EEEE RASA EEEE E EE N E ae ee ee ee 53 4 2 3 POM S e a he ea besa esis gerade daa evaded a aa 54 4 2 4 POWAY hes E EE eee ie dca chic hs Ae a dat i ccs Me Scat nc cae Re cc Bou en ade tach each wa sduGnatdas d
145. Preliminary User s Manual UU17446EJ1VOUD CHAPTER 22 PACKAGE DRAWING 30 PIN PLASTIC SSOP 7 62 mm 300 detail of lead end NOTE Each lead centerline is located within 0 13 mm of A 9 85 0 15 ITEM MILLIMETERS its true position T P at maximum material condition 0 45 MAX 0 65 T P 0 08 0 247 9 97 0 1 0 05 1 30 1 1 2 8 1 0 2 6 10 2 1 0 0 2 0 17 0 03 0 5 0 13 0 10 oto 3 3 0 25 0 6 0 15 S30MC 65 5A4 2 Ciaj VI ZlSf ryAlc TiO nm O O w Preliminary User s Manual U17446EJ1VOUD 349 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the 78KOS KB1 Figure A 1 shows development tools e Compatibility with PC98 NX series 350 Unless stated otherwise products which are supported by IBM PC AT and compatibles can also be used with the PC98 NX series When using the PC98 NX series therefore refer to the explanations for IBM PC AT and compatibles Windows Unless stated otherwise Windows refers to the following operating systems e Windows 98 e Windows NT Ver 4 0 e Windows 2000 e Windows XP Preliminary User s Manual U17446EJ1VOUD APPENDIX A DEVELOPMENT TOOLS Figure A 1 Development Tools 1 2 1 When using the in circuit emulator IE
146. RA78KOS CC78KOS ID78KOS NS ID78KOS QB and SM for 78KOS all sold separately Ordering numbervSxxxxDF 789234 Notes 1 Under development 2 DF789234 is a common file that can be used with the RA78KOS CC78KOS ID78KOS NS ID78KO0S QB and SM for 78KOS Remark xxxx in the part number differs depending on the operating system to be used and the supply medium USxxxxID78KOS NS USxxxxID78KO0S QB USxxxxSM789234 B Host Machine Supply Medium PC 9800 series IBM PC AT English Windows 3 5 2HD FD and compatibles Japanese Windows CD ROM English Windows USxXxxxDF789234 PC 9800 series IBM PC AT Japanese Windows 3 5 2HD FD and compatibles English Windows 356 Preliminary User s Manual U17446EJ1VOUD APPENDIX B NOTES ON TARGET SYSTEM DESIGN The following show the conditions when connecting the emulation probe to the conversion connector and conversion socket in the case using in circuit emulator IE 78KOS NS or IE 78KOS NS A Follow the configuration below and consider the shape of parts to be mounted on the target system when designing a system Figure B 1 Distance Between In Circuit Emulator and Conversion Connector When Using NP 30MC In circuit emulator IE 78KOS NS IE 78KOS NS A Target system Emulation board IE 789234 NS EM1 j sl e om g 1 1 somm gy Vena CN2 Emulation probe NP 30MC Conversion connector YSPACK30BK NSPACK30BK Rema
147. Reset Alternate Function Pin External interrupt input for which the valid edge rising edge P30 TI000 falling edge or both rising and falling edges can be specified P43 TxD6 P31 T1010 TOO0O P41 Serial data input for asynchronous serial interface P44 Serial data output for asynchronous serial interface P43 INTP1 External count clock input to 16 bit timer event counter 00 P30 INTPO Capture trigger input to capture registers CROOO and CR010 of 16 bit timer event counter 00 T1010 22 Preliminary User s Manual U17446EJ1VOUD CHAPTER 2 PIN FUNCTIONS 2 2 Pin Functions 2 2 1 POO to P03 Port 0 POO to P03 function as a 4 bit I O port POO to P03 can be set to input or output in 1 bit units using port mode register 0 PMO Use of an on chip pull up resistor can be specified by pull up resistor option register O PUO 2 2 2 P20 to P23 Port 2 P20 to P23 constitute a 4 bit I O port port 2 In addition to I O port pins these pins also have a function to input analog signals to the A D converter These pins can be set to the following operation modes in 1 bit units 1 2 Port mode P20 to P23 function as a 4 bit I O port Each bit of this port can be set to the input or output mode by using port mode register 2 PM2 In addition an on chip pull up resistor can be connected to the port by using pull up resistor option register 2 PU2 Control mode P20 to P23 function as the analog input pins A
148. S61 and PS60 bits to 0 when the device is incorporated in LIN i Even parity e Transmission Transmit data including the parity bit is controlled so that the number of bits that are 1 is even The value of the parity bit is as follows If transmit data has an odd number of bits that are 1 1 If transmit data has an even number of bits that are 1 0 e Reception The number of bits that are 1 in the receive data including the parity bit is counted If it is odd a parity error occurs ii Odd parity e Transmission Unlike even parity transmit data including the parity bit is controlled so that the number of bits that are 1 is odd If transmit data has an odd number of bits that are 1 0 If transmit data has an even number of bits that are 1 1 e Reception The number of bits that are 1 in the receive data including the parity bit is counted If it is even a parity error occurs iii 0 parity The parity bit is cleared to 0 when data is transmitted regardless of the transmit data The parity bit is not detected when the data is received Therefore a parity error does not occur regardless of whether the parity bit is O or 1 iv No parity No parity bit is appended to the transmit data Reception is performed assuming that there is no parity bit when data is received Because there is no parity bit a parity error does not occur 200 Preliminary User s Manual U17446
149. SR6 Baud rate generator control register 6 BRGC6 Asynchronous serial interface control register 6 ASICL6 00H Input select control register ISC 00H Multiplier 16 bit Multiplication result storage register MULO Undefined Data registers MRAO MRBO Undefined ister Control register MULCO oon ssid N Reset function Reset control flag register RESF Note i 00H Low voltage detector Low voltage detection register LVIM Low voltage detection level select register LVIS 00H i OH FH External interrupt mode registers INTMO INTM1 OH OH OH Flash memory Flash protect command register PFCMD Undefined Flash status register PFS on ssid Flash programming mode control register FLPMC Undefined Flash address pointer H compare register FLAPHC Note These values change as follows depending on the reset source Interrupt Request flag registers IFO IF1 Mask flag registers MKO MK1 i 0 Reset Source RESET Input Reset by POC Reset by WDT Reset by LVI Register See Table 15 2 Cleared 00H Cleared 00H Cleared 00H 250 Preliminary User s Manual U17446EJ1VOUD CHAPTER 15 RESET FUNCTION 15 1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78KOS KB1 The reset control flag register RESF is used to store which source has generated the reset request RESF can be read by an 8 bit memory manipulation instruction R
150. T1010 pin see 6 3 5 Port mode register 3 PM3 2 For how to enable the INTTMOOO or INTTMO10 interrupt see CHAPTER 13 INTERRUPT FUNCTIONS 102 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 1 Pulse width measurement with free running counter and one capture register When 16 bit timer counter 00 TMOO is operated in free running mode and the edge specified by prescaler mode register 00 PRMOO is input to the TIO0O pin the value of TMOO is taken into 16 bit timer capture compare register 010 CR010 and an external interrupt request signal INTTM010 is set Specify both the rising and falling edges by using bits 4 and 5 ES000 and ES010 of PRMOO Sampling is performed using the count clock selected by PRMOO and a capture operation is only performed when a valid level of the T1000 pin is detected twice thus eliminating noise with a short pulse width Figure 6 18 Control Register Settings for Pulse Width Measurement with Free Running Counter and One Capture Register When T1000 and CR010 Are Used a 16 bit timer mode control register 00 TMCO00 4 TMC003 TMC002 TMC001 OVFOO TwCo0 ERE 1 forfe b Capture compare control register 00 CRC00 Free running mode 3 CRC002 CRC001 CRC000 cRCo0 rele a CRO000 used as compare register CR010 used as capture register c Prescaler mode register 00 PRM00 ES101 ES100 ES010 ES000 3 2 PRMO001 PRMO00 aa ov 44 0 8 Lon
151. TMHMD1 Timer output enabled Timer output level inversion setting PWM output mode selection Count clock fent selection Count operation stopped ii Setting CMPO1 register e Compare value N Cycle setting iii Setting CMP11 register e Compare value M Duty setting Remark 00H lt CMP11 M lt CMP01 N lt FFH lt 2 gt The count operation starts when TMHE1 1 lt 3 gt The CMP01 register is the compare register that is to be compared first after count operation is enabled When the values of 8 bit timer counter H1 and the CMP01 register match 8 bit timer counter H1 is cleared an interrupt request signal INTTMH1 is generated and TOH1 output becomes active At the same time the compare register to be compared with 8 bit timer counter H1 is changed from the CMP01 register to the CMP 11 register 142 Preliminary User s Manual U17446EJ1VOUD CHAPTER 8 8 BIT TIMER H1 lt 4 gt When 8 bit timer counter H1 and the CMP11 register match TOH1 output becomes inactive and the compare register to be compared with 8 bit timer counter H1 is changed from the CMP11 register to the CMP01 register At this time 8 bit timer counter H1 is not cleared and the INTTMH1 signal is not generated lt 5 gt By performing procedures lt 3 gt and lt 4 gt repeatedly a pulse with an arbitrary duty can be obtained lt 6 gt To stop the count operation set TMHE1 0 If the setting value of the CMP01 register
152. Type Priority Interrupt Source Internal Vector Table Basic External Address Configuration Type 2 Trigger Note 3 Maskable INTLVI Low voltage detection Internal INTPO Pin input edge detection External INTP1 INTTMH1 Match between TMH1 and CMP01 Internal when compare register is specified INTTMO00 Match between TMOO and CR000 when compare register is specified T1010 pin valid edge detection when capture register is specified INTTM010 Match between TMOO and CR010 when compare register is specified T1000 pin valid edge detection when capture register is specified INTAD End of A D conversion INTP2 Pin input edge detection External INTP3 INTTM80 Match between TM80 and CR80 Internal INTSRE6 UARTE6 reception error occurrence INTSR6 End of UART6 reception INTST6 End of UART6 transmission RESET Reset input POC Power on clear LVI Low voltage detection 4 WDT WDT overflow Notes 1 Priority is the priority order when several maskable interrupt requests are generated at the same time 1 is the highest and 13 is the lowest 2 Basic configuration types A and B correspond to A and B in Figure 13 1 When bit 1 LVIMD of low voltage detection register LVIM 0 is selected 4 When bit 1 LVIMD of low voltage detection register LVIM 1 is selected be Caution No interrupt sources co
153. User s Manual U17446E 1VOUD 125 CHAPTER 7 8 BIT TIMER 80 7 1 Function of 8 Bit Timer 80 8 bit timer 80 has an 8 bit interval timer function and generates an interrupt at intervals specified in advance fxe 8 0 MHz Table 7 1 Interval Time of 8 Bit Timer 80 Minimum Interval Time 2 fxe 8 us Maximum Interval Time 2 fxe 2 05 ms Resolution 2 fxp 8 us 2 fxe 32 us 2 fxe 8 19 ms 2 fxp 32 us 2 fxp 128 us 2 fxe 32 7 ms 2 fxp 128 us 2 fxe 8 19 ms 2 4 fxp 2 01 s 2 fxe 8 19 ms fxe 10 0 MHz 2 fxp 6 4 us 2 fxe 1 64 ms 2 fxp 6 4 us 2 fxp 25 6 us 2 fxe 6 55 ms 2 fxp 25 6 us 2 fxp 102 us 2 fxe 26 2 ms 2 fxp 102 us 2 fxe 6 55 ms 2 4 fxe 1 68 s Remark fxr Oscillation frequency of clock to peripheral hardware 126 Preliminary User s Manual U17446EJ1VOUD 2 fxe 6 55 ms CHAPTER 7 8 BIT TIMER 80 7 2 Configuration of 8 Bit Timer 80 8 bit timer 80 consists of the following hardware Table 7 2 Configuration of 8 Bit Timer 80 Configuration Timer counter 8 bit timer counter 80 TM80 8 bit compare register 80 CR80 Register 8 bit timer mode control register 80 TMC80 Control register Figure 7 1 Block Diagram of 8 Bit Timer 80 8 bit compare register 80 CR80 Match INTTM80 fxp 26 fxp 28 2 8 bit timer co
154. V lt AVrer lt 4 0 V Full scale errors 4 0 V lt AVrer lt 5 5 V 2 7 V lt AVrer lt 4 0 V Integral non linearity error 1 4 0 V lt AVrer lt 5 5 V 2 7 V lt AVrer lt 4 0 V Differential non linearity error 1 4 0 V lt AVre lt 5 5 V 2 7 V lt AVrer lt 4 0 V Analog input voltage Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value Preliminary User s Manual U17446EJ1VOUD 345 CHAPTER 21 ELECTRICAL SPECIFICATIONS TARGET VALUES POC Circuit Characteristics Ta 40 to 85 C Parameter Conditions Detection voltage Power supply boot time Voo 0 V gt 2 1 V Note 1 Response delay time 1 When power supply rises after reaching detection voltage MAX Note 2 Response delay time 2 When power supply falls Minimum pulse width Notes 1 Time required from voltage detection to internal reset release 2 Time required from voltage detection to internal reset signal generation POC Circuit Timing Supply voltage Voo Detection voltage MAX Detection voltage TYP Detection voltage MIN Time 346 Preliminary User s Manual UU17446EJ1VOUD CHAPTER 21 ELECTRICAL SPECIFICATIONS TARGET VALUES LVI Circuit Characteristics Ta 40 to 85 C Parameter Conditions lt Detection voltage
155. VOUD 146 CHAPTER 8 8 BIT TIMER H1 Figure 8 9 Operation Timing in PWM Output Mode 4 4 e Operation by changing CMP11 CMP11 01H 03H CMP01 A5H einer counter H1 ORN 0 Dc Ca Cel ouk lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt 6 gt a ae oe CMP01 A5H T i i i ry EE ars St ee ee ee ee CMP11 01H x 01H 03H 03H Cc aaa wj s 9000 0 0 gt gt i lt 2 gt lt 2 gt TMHE1 INTTMH1 rr TOH1 TOLEV1 0 _ lt 6 gt lt 1 gt lt 3 gt lt 4 gt lt 5 gt l i The count operation is enabled by setting TMHE1 1 Start 8 bit timer counter H1 by masking one count clock to count up At this time the TOH1 output remains inactive when TOLEV1 0 The CMP11 register value can be changed during timer counter operation This operation is asynchronous to the count clock When the values of 8 bit timer counter H1 and the CMP01 register match the value of 8 bit timer counter H1 is cleared the TOH1 output becomes active and the INTTMH1 signal is output If the CMP11 register value is changed the value is latched and not transferred to the register When the values of 8 bit timer counter H1 and the CMP11 register before the change match the value is transferred to the CMP11 register and the CMP11 register value is changed lt 2 gt However three count clocks or more are required from when the CMP11
156. Xe Tt 3 a a 3 D gt a E a al Ne ee oat 1 oop r t 64 si a fo 2 1 T T Li i 001 l SZ Ke 5 101 peat A 001 Zero scale error at pealilnes 000 n ool i 0 1 2 3 AVREF 0 AVrer 3 AVrer 2 AVrer 1 AVReEF Analog input LSB Analog input LSB Figure 10 17 Integral Linearity Error Figure 10 18 Differential Linearity Error eee 1 Tessas 1 A y Ideal 1LSB width Ideal line a 3 3 T 3 E E aope NE i O a i SS i Differential SEA Integral linearity HA linearity error error 0 0 i 0 0 M 0 gt AVREF 0 AVREF Analog input Analog input 8 Conversion time This expresses the time from the start of sampling to when the digital output is obtained The sampling time is included in the conversion time in the characteristics table 9 Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample amp hold circuit Sampling _ time Conversion time Preliminary User s Manual U17446EJ1VOUD 175 CHAPTER 10 A D CONVERTER 10 6 Cautions for A D Converter 1 2 3 4 176 Operating current in STOP mode The A D converter stops operating in the STOP mode At this time the operating current can be reduced by clearing bit 7 ADCS and bit 0 ADCE of the A D converter mode register ADM to 0 Input range of ANIO to ANI3 Observe the rated range of the ANIO to ANI3 input voltage If a voltage
157. aae a fC ny Yr Saving PSW and PC jump r CPU MOV A r to interrupt servicing Interrupt servicing program Interrupt If an interrupt request flag xxIF is set before an instruction clock n n 4 to 10 under execution becomes n 1 the interrupt is acknowledged after the instruction under execution is complete Figure 13 8 shows an example of the interrupt request acknowledgment timing for an 8 bit data transfer instruction MOV A r Since this instruction is executed for 4 clocks if an interrupt occurs for 3 clocks after the execution starts the interrupt acknowledgment processing is performed after the MOV A r instruction is executed 230 Preliminary User s Manual U17446EJ1VOUD CHAPTER 13 INTERRUPT FUNCTIONS Figure 13 9 Interrupt Request Acknowledgment Timing When Interrupt Request Flag Is Set at Last Clock During Instruction Execution 8 clocks ga LIT LI LIY LY LY LOI LI Lo LA LY I i i Interrupt CPU NOP MOV A r Saving PSW arid PC jump servicing to interrupt servicing program Interrupt If an interrupt request flag xxIF is set at the last clock of the instruction the interrupt acknowledgment processing starts after the next instruction is executed Figure 13 9 shows an example of the interrupt request acknowledgment timing for an interrupt request flag that is set at the second clock of NOP 2 clock instruction In this case the MOV A r instruction after the NOP instruction is executed and then
158. ake the ground point of the oscillator capacitor the same potential as Vss Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator Remark For the resonator selection and oscillator constant users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation 338 Preliminary User s Manual UU17446EJ1VOUD CHAPTER 21 ELECTRICAL SPECIFICATIONS TARGET VALUES High Speed Ring OSC Oscillator Characteristics Ta 40 to 85 C Von 2 0 to 5 5 V fx 8 MHz On chip high speed Ring OSC Oscillation 2 7V lt Voo lt 5 5 V Ta 10 to 80 C frequency Ta 40 to 85 C fx 2 0 V lt Voo lt 2 7 V Notes 1 Use this product in a voltage range of 2 2 to 5 5 V because the detection voltage Vroc of the power on clear POC circuit is 2 1 V 0 1 V 2 Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time Low Speed Ring OSC Oscillator Characteristics Ta 40 to 85 C Von 2 0 to 5 5 V Vss 0 V Note Use this product in a voltage range of 2 2 to 5 5 V because the detection voltage Vroc of the power on clear POC circuit is 2 1 V 0 1 V Preliminary User s Manual U17446EJ1VOUD 339 CHAPTER 21 ELECTRICAL SPECIFICATIONS TARGET VALUES DC Characteristics Ta 40 to 85 C Voo 2 0 to 5 5 V V
159. al generation clears INTMO to OOH Figure 13 4 Format of External Interrupt Mode Register 0 INTMO Address FFECH After reset OOH R W Symbol 7 6 5 4 3 2 1 0 INTMO ES21 ES20 ES11 ES10 ES01 ES00 EE INTP2 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges INTP1 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges INTPO valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges Cautions 1 Be sure to clear bits 0 and 1 to 0 2 Before setting the INTMO register be sure to set the corresponding interrupt mask flag xxMKx 1 to disable interrupts After setting the INTMO register clear the interrupt request flag xxIFx 0 then clear the interrupt mask flag xxMKx 0 which will enable interrupts Preliminary User s Manual U17446EJ1VOUD 227 CHAPTER 13 INTERRUPT FUNCTIONS 4 External interrupt mode register 1 INTM1 INTM1 is used to specify the valid edge for INTP3 INTM1 is set with an 8 bit memory manipulation instruction Reset signal generation clears INTM1 to OOH Figure 13 5 Format of External Interrupt Mode Register 1 INTM1 Address FFEDH After reset OOH R W Symbol 7 6 5 4 3 2 1 0 INTP3 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges Cautions 1 Be sure
160. alid edge of TI000 pin is specified to be both the rising and falling edges 16 bit timer capture compare register 000 CR000 cannot perform the capture operation When the CRCO001 bit value is 1 the TMOO count value is not captured in the CR000 register when a valid edge of the T1010 pin is detected but the input from the TI010 pin can be used as an external interrupt source because INTTMO000 is generated at that timing Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement See the description of the respective control registers for details Preliminary User s Manual U17446E 1VOUD 107 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 Figure 6 24 Timing of Pulse Width Measurement Operation by Free Running Counter and Two Capture Registers with Rising Edge Specified V TMOO count value ooooHXo001HX X Do Xoo 1X X D1 XD1 1X erFFHXooo0HX K D2 Xo2 1X X vs X T1000 pin input f E E CR010 capture value te oe owce Vo es INTTMO10 i i i OVF00 i i ae Note IZ Pues i sl D1 D0 xt 10000H D1 D2 D8 D2 xt Note OVFOO must be cleared by software 4 Pulse width measurement by means of restart When input of a valid edge to the T1000 pin is detected the count value of 16 bit timer counter 00 TMO0 is taken into 16 bit timer capture compare register 010 CRO10 and then the pulse width of the signal input to the T1000 pin is measured
161. already been written to the flash memory cannot be written Preliminary User s Manual U17446EJ1VOUD 279 CHAPTER 19 FLASH MEMORY Table 19 9 shows the relationship between the security setting and the operation in each programming mode Table 19 9 Relationship Between Security Setting and Operation In Each Programming Mode Programming Mode On Board Off Board Programming Self Programming Security Setting Security Setting Security Operation Security Setting Security Operation Batch erase chip erase Possible Impossible InvalidNot Block erase Write Notes 1 Execution of each command is prohibited by the security setting 2 Execution of self programming command is possible regardless of the security setting 19 8 Flash Memory Programming by Self Writing The 78KOS KB1 supports a self programming function that can be used to rewrite the flash memory via a user program making it possible to upgrade programs in the field Caution Self programming processing must be included in the program before performing self writing Remark To use the internal flash memory of the 78KOS KB1 as the external EEPROM for storing data refer to 78KOS Kx1 EEPROM Emulation AN U17379E 19 8 1 Outline of self programming To execute self programming shift the mode from the normal operation of the user program normal mode to the self programming mode Write erase processing for the flash memory which has been set to the
162. an FLPMC e If a value other than the value to be set to FLPMC value written in lt 2 gt is written by the first store instruction after lt 3 gt Remark The numbers in angle brackets above correspond to the those in 2 Flash protect command register PFCMD lt Reset conditions gt e If 0 is written to the FPRERR flag e If the reset signal is generated 2 Operating conditions of VCERR flag lt Setting conditions gt e Erasure verification error e Internal writing verification error If VCERR is set it means that the flash memory has not been erased or written correctly Erase or write the memory again in the specified procedure Remark The VCERR flag may also be set if an erase or write protect error occurs Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY lt Reset conditions gt e When 0 is written to the VCERR flag e When the reset signal is generated 3 Operating conditions of WEPRERR flag lt Setting conditions gt e f the area specified by the protect byte to be protected from erasing or writing is specified by the flash address pointer H FLAPH and a command is executed to this area lt Reset conditions gt e When 0 is written to the WEPRERR flag e When the reset signal is generated 4 Flash programming command register FLCMD This register is used to specify whether the flash memory is erased written or verified in the self programming mode This register is set with a 1 bit or 8 bit mem
163. an be stopped by software is selected by option byte and 9 4 4 Watchdog timer operation in HALT mode when low speed Ring OSC can be stopped by software is selected by option byte A status transition diagram is shown below Preliminary User s Manual U17446EJ1VOUD 155 CHAPTER 9 WATCHDOG TIMER Figure 9 5 Status Transition Diagram When Low Speed Ring OSC Can Be Stopped by Software Is Selected by Option Byte WDT clock fat Overflow time 546 13 ms MAX WDCS4 1 WDT clock fx Select overflow time settable only once WDT clock fat Select overflow time settable only once WDT operation stops WDTE ACH Clear WDT counter WDTE ACH Clear WDT counter WDTE ACH Clear WDT counter WDT clock fx Overflow time 2 3 fx to 2 fx WDT count continues WDT clock fat Overflow time 4 27 ms to 546 13 ms MAX WDT count continues LSRSTOP 1 gon eee Ee gs LSRSTOP 0 mp WDT clock fat WDT count stops HALT instruction HALT l instruction STOP nterrupt STOB STOP instruction HALT instruction instruction instruction Interrupt Interrupt Interrupt Interrupt Interrupt STOP WDT count stops HALT WDT count stops STOP WDT count stops HALT WDT count stops 156 Preliminary User s Manual U17446EJ1VOUD CHAPTER 9 WATCHDOG TIMER 9 4 3 W
164. ance of ANIO to ANI3 pins In this A D converter the internal sampling capacitor is charged and sampling is performed for approx one sixth of the conversion time Since only the leakage current flows other than during sampling and the current for charging the capacitor also flows during sampling the input impedance fluctuates during sampling and in the other state If the shortest conversion time of the reference voltage is used to perform sufficient sampling it is recommended to make the output impedance of the analog input source 1 KQ or lower or attach a capacitor of around 0 01 uF to 0 1 uF to the ANIO to ANI3 pins see Figure 10 19 Preliminary User s Manual U17446EJ1VOUD p 177 O APPENDIX D LIST OF CAUTIONS Chapter 10 Soft Classification Function A D converter Details of Function ADIF Interrupt request flag Cautions The interrupt request flag ADIF is not cleared even if the analog input channel specification register ADS is changed Therefore if an analog input pin is changed during A D conversion the A D conversion result and ADIF for the pre change analog input may be set just before the ADS rewrite Caution is therefore required since at this time when ADIF is read immediately after the ADS rewrite ADIF is set despite the fact A D conversion for the post change analog input has not ended When A D conversion is stopped and then resumed clear ADIF before the A D conversion operat
165. and the INTST6 occurrence it triggers the SBF reception and SBF transmission again so do not set Figure 11 10 Format of Asynchronous Serial Interface Control Register 6 ASICL6 1 2 Address FF98H After reset 16H R WN Symbol ASICL6 SBRF6 SBRT6 SBTT6 SBL62 SBL61 SBL60 EA TXDLV6 SBRF6 SBF reception status flag 0 If POWERG6 0 and RXE6 0 or if SBF reception has been completed correctly 1 SBF reception in progress SBRT6 SBF reception trigger SBF reception trigger SBTT6 SBF transmission trigger SBF transmission trigger Note Bit 7 is read only 192 Preliminary User s Manual U17446EJ1VOUD CHAPTER 11 SERIAL INTERFACE UART6 Figure 11 10 Format of Asynchronous Serial Interface Control Register 6 ASICL6 2 2 SBL60 SBF transmission output width control SBF is output with 13 bit length SBF is output with 14 bit length SBF is output with 15 bit length SBF is output with 16 bit length SBF is output with 17 bit length SBF is output with 18 bit length SBF is output with 19 bit length SBF is output with 20 bit length Specification of first bit 0 MSB 1 LSB TXDLV6 Enabling disabling inverting TxD6 output 0 Normal output of TxD6 1 Inverted output of TxD6 Cautions 1 In the case of an SBF reception error return the mode to the SBF reception mode again and hold 1 the status of the SBRF6 flag Before setting the
166. apping e uPD78F9234 Taea RAE E E a 1FFFH Block 31 256 bytes 1FOOH 1EFFH Block 30 256 bytes 1E00H 1DFFH Block 29 256 bytes 1D00H 1CFFH e uPD78F9232 1000H OFFFH Block 15 256 bytes Block 15 256 bytes OFOOH OEFFH Block 14 256 bytes Block 14 256 bytes OE00H ODFFH Block 13 256 bytes Block 13 256 bytes ODOOH OCFFH 0300H 02FFH Block 2 256 bytes Block 2 256 bytes 0200H 01FFH Block 1 256 bytes 0100H OOFFH Block 0 256 bytes 0000H Block 1 256 bytes 8 KB Block 0 256 bytes 4KB Preliminary User s Manual U17446EJ1VOUD 269 CHAPTER 19 FLASH MEMORY 19 3 Functional Outline The internal flash memory of the 78K0S KB1 can be rewritten by using the rewrite function of the dedicated flash programmer regardless of whether the 78KOS KB1 has already been mounted on the target system or not on board off board programming The function for rewriting a program with the user program self programming which is ideal for an application when it is assumed that the program is changed after production shipment of the target system is provided In addition a security function that prohibits rewriting the user program written to the internal flash memory is also supported so that the program cannot be changed by an unauthorized person Refer to 19 7 4 Security settings for details on the security function Table 19 1 Rewrite Method Rewrite Me
167. apses after release of reset is selected by the option byte For details refer to CHAPTER 18 OPTION BYTE 3 3 Instruction Address Addressing An instruction address is determined by the program counter PC contents The PC contents are normally incremented 1 for each byte automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed When a branch instruction is executed the branch destination address information is set to the PC to branch by the following addressing for details of each instruction refer to 78K 0S Series Instructions User s Manual U11047E 3 3 1 Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC to branch The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes the sign bit In other words the range of branch in relative addressing is between 128 and 127 of the start address of the following instruction This function is carried out when the BR addr16 instruction or a conditional branch instruction is executed Illustration PC is the start address of PC A the next instruction of a BR instruction 15 8 7 6 0 ee ee jdisp8 15 0 ___ When S 0 indicates that all bits are 0 When S 1 o indicates
168. are oscillation of the low speed Ring OSC oscillator can be stopped by LSRSTOP 3 If the operating clock of the watchdog timer is the low speed Ring OSC clock the watchdog timer is stopped Caution The LSRSTOP setting is valid only when Can be stopped by software is set for the low speed Ring OSC oscillator by the option byte Remark LSRSTOP Bit0O of the low speed Ring OSC mode register LSRCM The standby function is designed to reduce the operating current of the system The following two modes are available 1 HALT mode HALT instruction execution sets the HALT mode In the HALT mode the CPU operation clock is stopped Oscillation of the system clock oscillator continues If the low speed Ring OSC oscillator is operating before the HALT mode is set oscillation of the clock of the low speed Ring OSC oscillator continues refer to Table 14 1 Oscillation of the low speed Ring OSC clock whether it cannot be stopped or can be stopped by software is set by the option byte In this mode the operating current is not decreased as much as in the STOP mode but the HALT mode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations 234 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 14 STANDBY FUNCTION 2 STOP mode STOP instruction execution sets the STOP mode In the STOP mode the system clock oscillator stops stopping the whole system thereby considerably
169. at the reception destination Make sure that the baud rate error during reception satisfies the range shown in 4 Permissible baud rate range during reception Permissible baud rate range during reception Make sure that the baud rate error during reception is within the permissible error range by using the calculation expression shown below Multiplier N p oO Ea Q oO x O MULO 16 bit multiplication result storage register 0 Although this register is manipulated with a 16 bit memory manipulation instruction it can be also manipulated with an 8 bit memory manipulation instruction When using an 8 bit memory manipulation instruction however access the register by means of direct addressing MULCO control register 0 Be sure to clear bits 1 to 7 to 0 Interrupt function Chapter 13 378 Vector table address No interrupt sources correspond to the vector table address 0014H IFO IF1 Interrupt request flag registers 0 1 MKO MK1 Interrupt mask flag registers 0 1 Because P30 P31 P41 and P43 have an alternate function as external interrupt inputs when the output level is changed by specifying the output mode of the port function an interrupt request flag is set Therefore the interrupt mask flag should be set to 1 before using the output mode INTMO External interrupt mode register 0 Be sure to clear bits
170. atchdog timer operation in STOP mode when low speed Ring OSC can be stopped by software is selected by option byte The watchdog timer stops counting during STOP instruction execution regardless of whether the system clock or low speed Ring OSC clock is being used 1 When the watchdog timer operation clock is the clock to peripheral hardware fx when the STOP instruction is executed When STOP instruction is executed operation of the watchdog timer is stopped After STOP mode is released operation stops for 34 ws TYP after waiting for the oscillation stabilization time set by the oscillation stabilization time select register OSTS after operation stops in the case of crystal ceramic oscillation and then counting is started again using the operation clock before the operation was stopped At this time the counter is not cleared to 0 but holds its value Figure 9 6 Operation in STOP Mode WDT Operation Clock Clock to Peripheral Hardware lt 1 gt CPU clock Crystal ceramic oscillation clock Normal Operation CPU operation operation _ STOP en stabilization time _ Normal operation fcpu Oscillation stabilization time set by OSTS register Oscillation stopped Watchdog timer Operating Operation stopped Operating lt 2 gt CPU clock High speed Ring OSC clock or external clock input Normal Operation CPU operation operation _ STOP R stopped s Normal operation fcpu Os
171. ations are available to generate a reset signal External reset input via RESET pin 2 Internal reset by watchdog timer program loop detection 3 Internal reset by comparison of supply voltage and detection voltage of power on clear POC circuit 4 Internal reset by comparison of supply voltage and detection voltage of low power supply detector LVI External and internal resets have no functional differences In both cases program execution starts at the address at 0000H and 0001H when the reset signal is input A reset is applied when a low level is input to the RESET pin the watchdog timer overflows or by POC and LVI circuit voltage detection and each item of hardware is set to the status shown in Table 15 1 Each pin is high impedance during reset signal generation or during the oscillation stabilization time just after reset release except for P130 which is low level output When a high level is input to the RESET pin the reset is released and program execution starts using the CPU clock after referencing the option byte after the option byte is referenced and the clock oscillation stabilization time elapses if crystal ceramic oscillation is selected A reset generated by the watchdog timer source is automatically released after the reset and program execution starts using the CPU clock after referencing the option byte after the option byte is referenced and the clock oscillation stabilization time elapses if crystal ceramic osci
172. been received and the SBF reception mode is restored In this case the SBRF6 and SBRT6 bits are not cleared Figure 11 23 SBF Reception 1 Normal SBF reception stop bit is detected with a width of more than 10 5 bits Roe i oR AR BPS a BE ae Be ee Re Be B05 aa dO a SBRT6 SBRF6 INTSR6 2 SBF reception error stop bit is detected with a width of 10 5 bits or less Begs cc Ae SE BEE gee AAS ob Mee Se aga ge She Gin SBRT6 OO SBRF6 INTSR6 o Remark RxD6 RxD6 pin input SBRT6 Bit 6 of asynchronous serial interface control register 6 ASICL6 SBRF6 Bit 7 of ASICL6 INTSR6 Reception completion interrupt request Preliminary User s Manual U17446EJ1VOUD 209 CHAPTER 11 SERIAL INTERFACE UART6 11 4 3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8 bit programmable counter and generates a serial clock for transmission reception of UART6 Separate 8 bit counters are provided for transmission and reception 1 Configuration of baud rate generator 210 Base clock The clock selected by bits 3 to 0 TPS63 to TPS60 of clock selection register 6 CKSR6 is supplied to each module when bit 7 POWERS6 of asynchronous serial interface operation mode register 6 ASIM6 is 1 This clock is called the base clock and its frequency is called fxcLke The base clock is fixed to low level when POWER6 0 Transmission counter This counter sto
173. bit length in one data frame are specified by asynchronous serial interface operation mode register 6 ASIM6 Whether data is communicated with the LSB or MSB first is specified by bit 1 DIR6 of asynchronous serial interface control register 6 ASICL6 Whether the TxD6 pin outputs normal or inverted data is specified by bit O TXDLV6 of ASICL6 198 Preliminary User s Manual U17446EJ1VOUD CHAPTER 11 SERIAL INTERFACE UART6 Figure 11 14 Example of Normal UART Transmit Receive Data Waveform 1 Data length 8 bits LSB first Parity Even parity Stop bit 1 bit Communication data 55H 1 data frame 2 Data length 8 bits MSB first Parity Even parity Stop bit 1 bit Communication data 55H 1 data frame l 3 Data length 8 bits MSB first Parity Even parity Stop bit 1 bit Communication data 55H TxD6 pin inverted output i 1 data frame 5 Data length 8 bits LSB first Parity None Stop bit 1 bit Communication data 87H I 1 data frame Preliminary User s Manual U17446EJ1VOUD 199 CHAPTER 11 SERIAL INTERFACE UART6 b Parity types and operation The parity bit is used to detect a bit error in communication data Usually the same type of parity bit is used on both the transmission and reception sides With even parity and odd parity a 1 bit odd number error can be detected With zero parity and no parity an error cannot be detected Caution Fix the P
174. ble display and memory display Integrated debugger with trace results the trace results can be displayed corresponding to the source program It is used with a device file DF789234 sold separately Ordering number wSxxxxID78KOS NS ID78K0S QB This debugger supports the in circuit emulators for the 78KOS Kx1 Series ID78KOS QB is supporting in circuit Windows based software emulator Provided with the debug function supporting C language source programming disassemble QB 78KOSKX1 MINI display and memory display are possible This is used with the device file DF789234 sold Integrated debugger separately It is provided with the in circuit emulator QB 78KOSKX1MINI Ordering number SxxxxID78KO0S QB not for sale SM for 78KOS 1 This is a system simulator for the 78K OS series SM for 78KOS is Windows based software System simulator This simulator can execute C source level or assembler level debugging while simulating the operations of the target system on the host machine By using SM for 78KOS the logic and performance of the application can be verified independently of hardware development Therefore the development efficiency can be enhanced and the software quality can be improved This simulator is used with a device file DF 789234 sold separately Ordering number wSxxxxSM789234 B DF789234N This is a file that has device specific information Device file It is used with the
175. by clearing TMOO and restarting the count The edge specification can be selected from two types rising or falling edges by bits 4 and 5 ES000 and ES010 of prescaler mode register 00 PRMOO Sampling is performed at the interval selected by prescaler mode register 00 PRMOO and a capture operation is only performed when a valid level of the TI000 pin is detected twice thus eliminating noise with a short pulse width 108 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 Figure 6 25 Control Register Settings for Pulse Width Measurement by Means of Restart with Rising Edge Specified a 16 bit timer mode control register 00 TMC00 4 TMC003 TMC002 TMC001 OVFOO Tuco e eee e aTe b Capture compare control register 00 CRC00 Clears and starts at valid edge of T1000 pin 7 6 5 4 3 CRC002 CRC001 CRC000 CRO000 used as capture register Captures to CR000 at inverse edge to valid edge of TIOOON CR010 used as capture register c Prescaler mode register 00 PRM00 ES110 ES100 ES010 ES000 3 PRM001 PRM000 oe eer Selects count clock setting 11 is prohibited Specifies rising edge for pulse width detection Setting invalid setting 10 is prohibited Note If the valid edge of TI000 pin is specified to be both the rising and falling edges 16 bit timer Preliminary User s Manual U17446E 1VOUD 109 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00
176. by software during a communication operation when bit 7 POWER6 and bit 6 TXE6 of ASIM6 1 or bit 7 POWER6 and bit 5 RXE6 of ASIM6 1 Figure 11 8 Format of Clock Selection Register 6 CKSR6 Address FF96H After reset OOH R W Symbol 7 6 5 4 3 2 1 0 CKSR6 0 0 0 0 TPS63 TPS62 TPS61 TPS60 TPS60 Base clock fxcike selection fxr 10 MHz fxe 2 5 MHz fxp 2 2 5 MHz fxp 2 1 25 MHz fxp 2 625 kHz fxp 2 312 5 kHz fxp 2 156 25 kHz fxp 2 78 13 kHz fxp 2 39 06 kHz fxp 2 19 53 kHz fxe 2 9 77 kHz 1 fxe 2 4 89 kHz 0 0 0 0 Other than above Setting prohibited Caution Make sure POWER6 0 when rewriting TPS63 to TPS60 Remarks 1 Figures in parentheses are for operation with fxe 10 MHz 2 fxp Oscillation frequency of clock to peripheral hardware 190 Preliminary User s Manual U17446EJ1VOUD CHAPTER 11 SERIAL INTERFACE UART6 5 Baud rate generator control register 6 BRGC6 This register sets the division value of the 8 bit counter of serial interface UART6 BRGC6 can be set by an 8 bit memory manipulation instruction Generation of reset signal sets this register to FFH Remark BRGC6 can be refreshed the same value is written by software during a communication operation when bit 7 POWER6 and bit 6 TXE6 of ASIM6 1 or bit 7 POWERS and bit 5 RXE6 of ASIM6 1 Figure 11 9 Format of Baud Rate Generator
177. capture trigger conflict when CROOO0 is used as a capture register the capture trigger input takes precedence and the read data is undefined Also if the count stop of the timer and the input of the capture trigger conflict the capture trigger is undefined 3 18 p 88 Changing the CROO0 setting may cause a malfunction To change the setting refer to 6 5 Cautions Related to 16 Bit Timer Event Counter 00 17 Changing compare register during timer operation p 88 CR010 16 bit timer capture compare register 010 In the free running mode and in the clear amp start mode using the valid edge of the T1000 pin if CRO10 is set to OOOOH an interrupt request INTTM010 is generated when CR010 changes from 0000H to 0001H following overflow FFFFH p 89 If the new value of CRO10 is less than the value of 16 bit timer counter 0 TMOO TMOO continues counting overflows and then starts counting from 0 again If the new value of CRO10 is less than the old value therefore the timer must be reset to be restarted after the value of CRO10 is changed p 89 The value of CR010 after 16 bit timer event counter 00 has stopped is not guaranteed p 89 The capture operation may not be performed for CRO10 set in compare mode even if a capture trigger is input p 89 If the register read period and the input of the capture trigger conflict when CR010 is used as a
178. chip pull up resistor can be connected only to P120 and P123 by setting software Port 13 1 bit output only port Note For settings of alternate function refer to CHAPTER 18 OPTION BYTE Caution The P121 X1 and P122 X2 pins are pulled down during reset Remarks 1 P121 and P122 can be allocated when the high speed Ring OSC is selected as the system clock 2 P122 can be allocated when an external clock is selected as the system clock 50 Preliminary User s Manual U17446EJ1VOUD CHAPTER 4 PORT FUNCTIONS 4 2 Port Configuration Ports consist of the following hardware units Table 4 2 Configuration of Ports Item Configuration Control registers Port mode registers PMO PM2 PM3 PM4 PM12 Port registers PO P2 P3 P4 P12 P13 Port mode control register 2 PMC2 Pull up resistor option registers PUO PU2 PU3 PU4 PU12 Ports Total 26 CMOS I O 24 CMOS input 1 CMOS output 1 Pull up resistor Total 22 Preliminary User s Manual U17446EJ1VOUD 51 CHAPTER 4 PORT FUNCTIONS 4 2 1 Port0 Port 0 is a 4 bit I O port with an output latch Each bit of this port can be set to the input or output mode by using port mode register 0 PMO When the POO to PO3 pins are used as an input port an on chip pull up resistor can be connected in 1 bit units by using pull up resistor option register 0 PUO This port is also used as the analog input pins of the internal A D converter Generation
179. chronous Break Field reception control function is used for reception For the reception operation of LIN see Figure 11 2 LIN Reception Operation Reception is enabled when bit 7 POWERS of asynchronous serial interface operation mode register 6 ASIM6 is set to 1 and then bit 5 RXE6 of ASIM6 is set to 1 SBF reception is enabled when bit 6 SBRT6 of asynchronous serial interface control register 6 ASICL6 is set to 1 In the SBF reception enabled status the RxD6 pin is sampled and the start bit is detected in the same manner as the normal reception enable status When the start bit has been detected reception is started and serial data is sequentially stored in the receive shift register 6 RXS6 at the set baud rate When the stop bit is received and if the width of SBF is 11 bits or more a reception completion interrupt request INTSR6 is generated as normal processing At this time the SBRF6 and SBRT6 bits are automatically cleared and SBF reception ends Detection of errors such as OVE6 PE6 and FE6 bits 0 to 2 of asynchronous serial interface reception error status register 6 ASIS6 is suppressed and error detection processing of UART communication is not performed In addition data transfer between receive shift register 6 RXS6 and receive buffer register 6 RXB6 is not performed and the reset value of FFH is retained If the width of SBF is 10 bits or less an interrupt does not occur as error processing after the stop bit has
180. chronous serial Asynchronous serial T 7 i fxp 28 interface operation mode interface reception error Baud rate Asynchronous serial interface Receive buffer register 6 fxp 24 i register 6 ASIM6 status register 6 ASIS6 generator control register 6 ASICL6 RXB6 5 S nee g Reception unit l fxP 27 wml Al eI AAA A ENG E o fxr 28 Internal bus fxe 2 fxP 2 pF tf KN KAN KN eee eee ee eee SG ee eee fxp 2 Baud rate generator Clock selection Asynchronous serial Baud rate Asynchronous serial interface Transmit buffer register 6 BRGCS register 6 CKSR6 status register 6 ASIF6 generator control register 6 ASICL6 TXB6 8 8 Registers Transmit shift register 6 INTST6 Transmission control TXS6 Note Selectable with input switch control register ISC Transmission unit 9LYVN AOVAYNSALNI IWINAS LL YALdVHO 1 2 3 4 CHAPTER 11 SERIAL INTERFACE UART6 Receive buffer register 6 RXB6 This 8 bit register stores parallel data converted by receive shift register 6 RXS6 Each time 1 byte of data has been received new receive data is transferred to this register from receive shift register 6 RXS6 If the data length is set to 7 bits data is transferred as follows e In LSB first reception the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0 e In MSB first reception the receive data is transferred to bits 7 to 1
181. cillation stopped Watchdog timer Operating Operation stopped Operating Note The operation stop time is 17 us MIN 34 us TYP and 67 us MAX Preliminary User s Manual U17446EJ1VOUD 157 2 When the watchdog timer operation clock is the low speed Ring OSC clock fri when the STOP instruction is executed When the STOP instruction is executed operation of the watchdog timer is stopped After STOP mode is released operation stops for 34 us TYP and then counting is started again using the operation clock before the CHAPTER 9 WATCHDOG TIMER operation was stopped At this time the counter is not cleared to 0 but holds its value Figure 9 7 Operation in STOP Mode WDT Operation Clock Low Speed Ring OSC Clock Normal CPU operation _operation as lt 1 gt CPU clock Crystal ceramic oscillation clock STOP Operation stopped ote Oscillation stabilization time i mr a 7 Oscillation stabilization time set by OSTS register O fRL Watchdog timer 5 Oscillation stopped Operating Operation stopped Operating lt 2 gt CPU clock High speed Ring OSC clock or external clock input CPU operation Operation _ _ Normal Operation Normal operation fcpu fRL Watchdog timer STOP i stopped Oscillation stopped Operating Operation stopped Operating Note The operation stop time is 17 ws MIN 34 ws TYP and 67 ws MAX
182. ck If the count value is read during operation input of the count clock is temporarily stopped and the count value at that point is read Figure 6 2 Format of 16 Bit Timer Counter 00 TM00 Address FF12H FF13H After reset OOOOH R Symbol FF13H FF12H The count value is reset to 0000H in the following cases lt l gt Atreset signal generation lt 2 gt If TMC003 and TMC002 are cleared lt 3 gt If the valid edge of T1000 is input in the clear amp start mode entered by inputting the valid edge of T1000 lt 4 gt If TM00 and CR000 match in the clear amp start mode entered on a match between TMO0 and CR000 lt 5 gt If OSPTOO is set to 1 in the one shot pulse output mode Cautions 1 Even if TMOO is read the value is not captured by CR010 2 During TMOO0 is read the count clock is stopped 16 bit timer capture compare register 000 CRO00 CRO00 is a 16 bit register which has the functions of both a capture register and a compare register Whether it is used as a capture register or as a compare register is set by bit 0 CRC000 of capture compare control register 00 CRCOO CRO000 is set by 16 bit memory manipulation instruction Reset signal generation clears this register to OOOOH Figure 6 3 Format of 16 Bit Timer Capture Compare Register 000 CR000 Address FF14H FF15H After reset OOOOH R W Symbol FF15H FF14H A e When CR000 is used as a compare register The value set in CR000 is constantly compared with the 16
183. ck blank check command lt 1 gt to lt 5 gt in 19 8 7 lt 6 gt Mode is shifted from normal mode to self programming mode lt 1 gt to lt 5 gt in 19 8 4 lt 7 gt Execution of block blank check command Error check lt 6 gt to lt 11 gt in 19 8 7 lt 8 gt Mode is shifted from self programming mode to normal mode lt 1 gt to lt 5 gt in 19 8 5 316 Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY Figure 19 28 Example of Operation When Interrupt Disabled Time Should Be Minimized from Erasure to Blank Check Erasure to blank check Figure 19 22 lt 1 gt Specify block erase command lt 1 gt to lt 5 gt Figure 19 20 lt 2 gt Shift to self programming lt 1 gt to lt 5 gt mode lt 3 gt Execute block erase command Figure 19 22 lt lt 6 gt to lt 11 gt Abnormal VCERR and WEPRERR flags Normal eee 7 lt 4 gt Shift to normal mode Figure 19 23 J lt 5 gt Specify block blank lt 1 gt to lt 5 gt check command Figure 19 20 lt 6 gt Shift to self programming lt 1 gt to lt 5 gt mode lt 7 gt Execute block blank check command Figure 19 23 lt lt 6 gt to lt 11 gt lt gt Check execution resu Abnormal VCERR and WEPRERR flags Normal Figure 19 21 J lt 8 gt Shift to normal mode lt 1 gt to lt 5 gt Normal termination Abnormal terminationNe Note Perform processing to shift to normal mode in order to return to normal proc
184. cknowledged Remark Interval time N 1 xt N 0001H to FFFFH settable range When the compare register is changed during timer count operation if the value after 16 bit timer capture compare register 000 CR000 is changed is smaller than that of 16 bit timer counter 00 TM00 TMOO continues counting overflows and then restarts counting from 0 Thus if the value M after the CR000 change is smaller than that N before the change it is necessary to restart the timer after changing CR 000 Figure 6 13 Timing After Change of Compare Register During Timer Count Operation N M N gt M CR000 N X i M TMO0 count value x 1 C x aes FFFFH 0000H 0001H 0002H Remark N gt X gt M 98 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 6 4 2 External event counter operation Setting The basic operation setting procedure is as follows lt l gt Setthe CRC0O register see Figure 6 14 for the set value lt 2 gt Setthe count clock by using the PRMOO register lt 3 gt Setany value to the CRO00 register 0000H cannot be set lt 4 gt Setthe TMCOO register to start the operation see Figure 6 14 for the set value Remarks 1 For the setting of the T1000 pin see 6 3 5 Port mode register 3 PM3 2 For how to enable the INTTM000 interrupt see CHAPTER 13 INTERRUPT FUNCTIONS The external event counter counts the number of external clock pulses to be input to the T1000 pin wi
185. compare register FLAPHC Flash address pointer H Flash address pointer L FLAPL Match Unmatch compare register FLAPL Flash address pointer L Flash write buffer register APLC FLW ZN A WEPRERR VCERR FPRERR ey Flash status register PFS Internal bus L8Z AYOWSW HSV14d 6b YALdVHO CHAPTER 19 FLASH MEMORY Figure 19 11 Self Programming State Transition Diagram User program Normal mode Specific sequence Operation setting Operation setting Register for Self i d PL ROJ amn oag self programming Self programming command execution by HALT instruction Self programming command completion error 1 Flash memory control block hardware Self programming command under execution l L L l I Operation reference l l L Flash memory Table 19 11 Self Programming Controlling Commands Command Name Internal verify Function This command is used to check if data has been correctly written to the flash memory After data has Time Taken from HALT Instruction Execution to Command Execution End Internal verify for 1 block internal verify command executed once 6 8 ms been written to the memory specify the block number the start address and the end address then execute this command Internal verify for 1 byte 27 us Block erasure This command is
186. converter operation MOE eiui iieii niei iadi iaeiiai aiii 172 10 5 How to Read A D Converter Characteristics Table cccccssseeeeseeneeeseeeeeenseeeeeenseseeenees 174 10 6 Cautions for A D Converter ccccceesenne reece eeeeeeeeneeeeeeeneeeeseeeeeeeseeeeeeeseeeeesaseeeeeeeaseeneeenneeneeennes 176 CHAPTER 11 SERIAL INTERFACE UART6 000 cccccceeeeeceeeceeeeeseeeee cece eeeeenseeaneeeesesesensseeneeeeeeeeeeeeees 179 11 1 Functions of Serial Interface UARTG cccceessneeeeeeeneeeeeeeneeeeseeneeeeeseeeeeeaseeneeeaseeneeensenneeenaes 179 11 2 Configuration of Serial Interface UARTE cccccceceeseneeeeeseneeeeseeeeeenseceeeeeaseeneeenseeneeenseeneeenees 183 11 3 Registers Controlling Serial Interface UARTE ccccceeseneeeeseeeeeeeseeeeeenseeeeeeenseeneeensseneeenees 185 11 4 Operation of Serial Interface UARTE ccccceceeeeeeeee cess ee eeeseeeneeeeeseeeseeeeeseeeeeseeesneeeeeneeees 195 11 4 1 Operation Stop MOC isian obeeed een E aE aa A A E ER a eaa AE A E aiani 195 Preliminary User s Manual U17446EJ1VOUD 11 11 4 2 Asynchronous serial interface UART MOdE ccccceeeceecee cece eeeeeeeeaeeeeeeeeeseeaeaeeeeeeeseenenaeees 196 11 4 3 Dedicated baud rate generator 2 cece cece cece ee eeeceeaeee cece eeeeaaeeeeeeeeeseeaaeaeceeeeeseeneaeeeeeeeeeeeees 210 CHAPTER 12 MULTIPLIER ciin a success cued evcnsucecdde sucdededstuetecssncectstetencenssurtenssctteys 217 12 1 Multiplie
187. cribes a symbol reserved by the assembler for the 1 bit manipulation instruction operand sfr bit This manipulation can also be specified with an address e 8 bit manipulation Describes a symbol reserved by the assembler for the 8 bit manipulation instruction operand sfr This manipulation can also be specified with an address e 16 bit manipulation Describes a symbol reserved by the assembler for the 16 bit manipulation instruction operand When specifying an address describe an even address Table 3 3 lists the special function registers The meanings of the symbols in this table are as follows e Symbol Indicates the addresses of the implemented special function registers It is defined as a reserved word in the RA78KOS and is defined as an sfr variable using the pragma sfr directive in the CC78KOS Therefore these symbols can be used as instruction operands if an assembler or integrated debugger is used e R W Indicates whether the special function register can be read or written R W Read write R Read only W Write only e Number of bits manipulated simultaneously Indicates the bit units 1 8 and 16 in which the special function register can be manipulated e After reset Indicates the status of the special function register when a reset signal is generated 36 Preliminary User s Manual U17446EJ1VOUD CHAPTER 3 CPU ARCHITECTURE Table 3 3 Special Function Registers 1 3 Address Special Function Register SFR Name
188. ctor Operable External interrupt Operable Note Cannot be stopped or Stopped by software is selected for low speed Ring OSC by the option byte for the option byte see CHAPTER 18 OPTION BYTE Preliminary User s Manual U17446EJ 1VOUD 237 CHAPTER 14 STANDBY FUNCTION 2 HALT mode release The HALT mode can be released by the following two sources a Release by unmasked interrupt request When an unmasked interrupt request is generated the HALT mode is released If interrupt acknowledgement is enabled vectored interrupt servicing is carried out If interrupt acknowledgement is disabled the next address instruction is executed Figure 14 2 HALT Mode Release by Interrupt Request Generation Interrupt HALT request instruction Wait Standby release signal Status of CPU Operating mode HALT mode ul Wait st Operating mode System clock Oscillation oscillation Remarks 1 The broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged 2 The wait time is as follows e When vectored interrupt servicing is carried out 11 to 13 clocks e When vectored interrupt servicing is not carried out 3 to 5 clocks 238 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 14 STANDBY FUNCTION b Release by reset signal generation When the reset signal is generated HALT mode is released and then as in the case with a normal reset operati
189. cuments Related to Development Hardware Tools User s Manuals Document Name Document No IE 78KOS NS In Circuit Emulator U13549E IE 78KOS NS A In Circuit Emulator U15207E QB 78KOSKX1MINI In Circuit Emulator U17272E Caution The related documents listed above are subject to change without notice Be sure to use the latest version of each document for designing Preliminary User s Manual U17446EJ1VOUD 7 Documents Related to Flash Memory Writing PG FP4 Flash Memory Programmer User s Manual U15260E PG FPL2 Flash Memory Programmer User s Manual U17307E Other Related Documents Document Name Document No SEMICONDUCTOR SELECTION GUIDE Products and Packages X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892E Note See the Semiconductor Device Mount Manual website http www necel com pkg en mount index html Caution The related documents listed above are subject to change without notice Be sure to use the latest version of each document for designing 8 Preliminary Users Manual U17446EJ1VOUD CONTENTS CHAPTER 1 OVERVIEW a ae aae aeaa a heas e araa Aa a dh a a A a E aa aaa Na a a r ANa oa daa aa ada aaa 15 LI Features aiae A A A a A 15 1 2 Application F eA S a
190. d as an input port pin the function to input an external reset signal to the RESET pin cannot be used The function of the port is selected by the option byte For details refer to CHAPTER 18 OPTION BYTE 56 Preliminary User s Manual U17446EJ1VOUD CHAPTER 4 PORT FUNCTIONS If a low level is input to the RESET pin before the option byte is referenced again after reset is released by the POC circuit the 78K0S KB1 is reset and is held in the reset state until a high level is input to the RESET pin 4 2 4 Port4 Port 4 is a 8 bit I O port with an output latch Each bit of this port can be set to the input or output mode by using port mode register 4 PM4 When the P40 to P47 pins are used as an input port an on chip pull up resistor can be connected in 1 bit units by using pull up resistor option register 4 PU4 The P41 to P44 pins can also be used for external interrupt request input serial interface data I O and timer output Generation of reset signal sets port 4 to the input mode Figures 4 8 to 4 11 show the block diagrams of port 4 Internal bus PU40 PU45 to PU47 Figure 4 8 Block Diagram of P40 P45 to P47 D F Voo q WRpeort PU4 P4 PM4 RD WRxx Write signal Output latch Ts A P40 P45 to P47 P40 P45 to P47 H PM45 to PM47 Port register 4 Port mode register 4 Read signal Pull up resistor optio
191. d debugger e System simulator Note 1 Control software e Project Manager Windows version only te 2 Host machine PC or EWS Interface adapter Power supply unit Flash memory writing environment In circuit emulator te 3 QB 78KOSMINI Flash programmer Debug adapter Flash memory writing adapter Flash memory Target cable or emulation probe Target system Notes 1 The C library source file is not included in the software package 2 The Project Manager PM plus is included in the assembler package PM plus is used only in the Windows environment 3 The in circuit emulator QB 78KOSKX1MINI is provided with the integrated debugger ID78KOS QB the flash memory programmer PG FPL2 a power supply unit and a target cable Other products are optional 352 Preliminary User s Manual U17446EJ1VOUD APPENDIX A DEVELOPMENT TOOLS A 1 Software Package SP78K0S This is a package that bundles the software tools required for development of the 78K 0S Series Software package The following tools are included RA78KOS CC78KOS ID78KOS NS etc Part number uSxxxxSP78K0S Remark xxxx in the part number differs depending on the operating system to be used LSxxxxSP78KOS PC 9800 series IBM PC AT Japanese Windows and compatibles English Windows A 2 Language Proc
192. d to the chip When a port register is read the pin level is read in the input mode and the value of the output latch of the port is read in the output mode POO to P03 P20 to P23 P30 to P34 P40 to P47 P120 to P123 and P130 are set by using a 1 bit or 8 bit memory manipulation instruction Generation of reset signal sets these registers to OOH Figure 4 16 Format of Port Register Address FFOOH After reset OOH Output latch R W Symbol 7 6 5 4 3 2 1 0 e o o o o r P Pm Po Address FF02H After reset OOH Output latch R W Symbol 7 6 5 4 3 2 1 0 oe o o o le elm ili Address FFO3H After reset OOH Output latch R W Symbol 7 6 5 4 3 2 1 0 s oe er pw Address FF04H After reset OOH Output latch R W Symbol 7 6 5 4 3 2 1 0 P4 Address FFOCH After reset OOH Output latch R W Symbol 7 6 5 4 3 2 1 0 Address FFODH After reset OOH Output latch R W Symbol 7 6 5 4 3 2 1 0 mat ae ES a e a a m 0 2 3 4 12 or 13 n 0 7 Controls of output data in output mode Input data read in input mode Output 0 Input low level Output 1 Input high level Note Because P34 is read only its reset value is undefined Preliminary User s Manual U17446EJ1VOUD 65 CHAPTER 4 PORT FUNCTIONS 3 Port mode control register 2 PMC2 This register specifies the port mode or A D converter mode Each bit of the PMC2 register corresponds to each pin of port
193. diNg cccccececeeeeeeeee cece ee eeeeeeaeaeeeeeeeeceeseaaeceeeeeseeeaaaeaeeeeesesencueaeeeeeeneeaeees 233 CHAPTER 14 STANDBY FUNCTION 0s ccccevcs seccetsscceeseetect cendctcnteestectenebstececendvicnteestecreqnvsnaeeeesteceetseeteers 234 14 1 Standby Function and Configuration ccccccsseccessecceeeeeeeeeeeeeeseseseeeseeesseeseeeseeeseeeseenseeseeee 234 141 1 Standby TUNCHOM seipie tes chtps dank cg oe take erana ainat iaidd tapii daiten 234 14 1 2 Registers used during standby ecccccceeceeeeeeeeeeee cece ee seee aces ce eeeecegeaeaaeaeceseeeseeeaeaeeeeeeeeeeeees 236 14 2 Standby Function Operation cceccccccesssenceceseeeeeeeseeeseeesneeseeeseeeseseseeeseeeseeeseseseaeseesseenseeesenaes 237 14 2 1 HALT MO siainen a ee E a ae aeaa geeesnndatee eae a a iiaa aat 237 14 22 O aoe EE E E E E E E ee 240 CHAPTER 15 RESET FUNCTION i ccccccsscccetestenceneieeeneetseieeesdsteerervaeceegevslenseetsebtesereanceegeveleneastanaeeervesieds 244 15 1 Register for Confirming Reset SOUFCe ssssessesennunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nna 251 CHAPTER 16 POWER ON CLEAR CIRCUIT cccccesseeeseseeeeeeeeeeeeeeeeeeseseseeeeeeeeseanseseseenseeeseeneeeesaes 252 16 1 Functions of Power on Clear Circuit ccccccssecceeeeeeeeeeeeeeneeeeseeseeeseeeseeesseaeseeeseanseseseeneeeeseaes 252 16 2 Configuration of Power on Clear Circuit ccccccessenceeeeeeeeeeeeseeeeeeeseenseeeseeeseeeeseansese
194. dware Statuses After Reset Acknowledgment 1 2 Program counter PC Note Contents of reset vector table 0000H and 0001H are set Program status word PSW a ECCE nn A Fort mode registers PMO Pvz 0PM Pw o fe Fron mode contoregster MC2 SSOSCSCS S S S Pup resistor orion eis Puo PUR PUB PUA pU O o Posarem OOO OOOO S Preprocessor soek ontolregitr P6Q To Se ee E Mode control register 00 TMC00 Prescaler mode register 00 PRMOO Capture compare control register 00 CRC00 Timer output control register 00 TOCOO0 8 bit timer 80 Timer counter 80 TM80 Compare register CR80 Undefined Mode control register 80 TMC80 8 bit timer H1 Compare registers CMP01 CMP11 lt lt Mode register 1 TMHMD1 oe 16 bit timer 00 Timer counter 00 TM00 0000H Capture compare registers 000 010 CR000 CR010 0000H Watchdog timer Mode register WDTM C eT ee Notes 1 Only the contents of PC are undefined while reset is being generated and while the oscillation stabilization time elapses The statuses of the other hardware units remain unchanged 2 The status after reset is held in the standby mode Preliminary User s Manual U17446EJ1VOUD 249 CHAPTER 15 RESET FUNCTION Table 15 1 Hardware Statuses After Reset Acknowledgment 2 2 Asynchronous serial interface reception error status register 6 ASIS6 Asynchronous serial interface transmission error status register 6 ASIF6 Clock select register 6 CK
195. e LVION flag set by software 1 13 gt i i INTLVI i i LVIIF flag I I lt 6 gt Note2 Cleared by software Internal reset signal Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 The LVIF and LVIIF flags may be set 1 Remark lt 1 gt to lt gt in Figure 17 5 above correspond to lt 1 gt to lt gt in the description of when starting operation in 17 4 2 When used as interrupt Preliminary User s Manual U17446E 1VOUD 261 CHAPTER 17 LOW VOLTAGE DETECTOR 17 5 Cautions for Low Voltage Detector In a system where the supply voltage Voo fluctuates for a certain period in the vicinity of the LVI detection voltage Vivi the operation is as follows depending on how the low voltage detector is used lt 1 gt When used as reset The system may be repeatedly reset and released from the reset status In this case the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action 1 below lt 2 gt When used as interrupt Interrupt requests may be frequently generated Take action 2 below In this system take the following actions lt Action gt 1 When used as reset After releasing the reset signal wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer and then initialize the ports see Figure 17 6 2 When used as interrupt Perform the processi
196. e TxD6 pin as serial data Data is transferred from TXB6 immediately after TXB6 is written for the first transmission or immediately before INTST6 occurs after one frame was transmitted for continuous transmission Data is transferred from TXB6 and transmitted from the TxD6 pin at the falling edge of the base clock TXS6 cannot be directly manipulated by a program Preliminary User s Manual U17446EJ1VOUD 185 CHAPTER 11 SERIAL INTERFACE UART6 11 3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following nine registers e Asynchronous serial interface operation mode register 6 ASIM6 e Asynchronous serial interface reception error status register 6 ASIS6 e Asynchronous serial interface transmission status register 6 ASIF6 e Clock selection register 6 CKSR6 e Baud rate generator control register 6 BRGC6 e Asynchronous serial interface control register 6 ASICL6 e Input switch control register ISC e Port mode register 4 PM4 e Port register 4 P4 1 Asynchronous serial interface operation mode register 6 ASIM6 This 8 bit register controls the serial communication operations of serial interface UART6 This register can be set by a 1 bit or 8 bit memory manipulation instruction Generation of reset signal sets this register to 01H Remark ASIM6 can be refreshed the same value is written by software during a communication operation when bit 7 POWER6 and bit 6 TXE6 of ASIM6
197. e count clock is supplied in the HALT STOP mode while low speed Ring OSC operates LSRSTOP 0 Preliminary User s Manual U17446EJ1VOUD APPENDIX D LIST OF CAUTIONS Chapter 18 Hard Classification Function Details of Function Selection of system clock source Cautions Because the X1 and X2 pins are also used as the P121 and P122 pins the conditions under which the X1 and X2 pins can be used differ depending on the selected system clock source 1 High speed Ring OSC clock P121 and P122 can be used as O port pins 2 Crystal ceramic oscillation clock The X1 and X2 pins cannot be used as I O port pins because they are used as clock input pins 3 External clock input Because the X1 pin is used as an external clock input pin P121 cannot be used as an I O port pin 16 18 Control of RESET pin If a low level is input to the RESET pin after reset is released by the power on clear function and before the option byte is referenced again the 78KOS KB1 is reset and the status is held until a high level is input to the RESET pin Oscillation stabilization time on power application or after reset release The setting of this option is valid only when the crystal ceramic oscillation clock is selected as the system clock source No wait time elapses if the high speed Ring OSC or external clock input is selected as the system clock source O e oO os Q x O
198. e register 00 PRMOO after stopping the timer operation 10 One shot pulse output One shot pulse output normally operates only in the free running mode or in the clear amp start mode at the valid edge of the T1000 pin Because an overflow does not occur in the clear amp start mode on a match between TMO00 and CR000 one shot pulse output is not possible 11 One shot pulse output by software lt l gt Do not set the OSPTOO bit to 1 again while the one shot pulse is being output To output the one shot pulse again wait until the current one shot pulse output is completed lt 2 gt When using the one shot pulse output of 16 bit timer event counter 00 with a software trigger do not change the level of the T1000 pin or its alternate function port pin Because the external trigger is valid even in this case the timer is cleared and started even at the level of the TI000 pin or its alternate function port pin resulting in the output of a pulse at an undesired timing lt 3 gt Do notset the 16 bit timer capture compare registers 000 and 010 CR000 and CR 010 to 0000H Preliminary User s Manual U17446E 1VOUD 121 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 12 One shot pulse output with external trigger lt l gt Do not input the external trigger again while the one shot pulse is being output To output the one shot pulse again wait until the current one shot pulse output is completed lt 2 gt Do notset the 16 bit timer capt
199. ean dein EA E 57 4 2 5 POMS csi EEE AS aia chai EAE E EE bhets A EE E E E N E E 60 4 2 6 POM TS A E E entice E tees ote E A ET A E E AE A E T 62 4 3 Registers Controlling Port Functions sssssussesnunnnnnnnnnnnnnnnnnnnnnnnnnnnnunnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nenne 63 A 4 Operation of Port FUMCUION aeieea ieia s aaa aaea re Ea a ea aa ae ea aeaaea ae haai 68 4 4 1 Writing to VO iportsiececiai eta Meena ee en e eee Wi a g tas 68 4 4 2 Reading from l O ports aiian Sik ee eee a eed eevee oad ee eee 68 4 4 3 Operations On O porte PE EEEE desea teens seesducs tae zssceeeapsecedssaeceenssoeedndaagssdevenieastees 68 CHAPTER 5 CLOCK GENERATORS bivcsscccccesecetevcees ct eceneenccueuea steeteeenenseesuscctteceeesseeveetcentuecs dteseececioeess 69 5 1 Functions of Clock Generators 2 ccccceceeeee cece eee eens eeeeeeeeee ee seeeeeaeee sees ene sens seaeeeseeeseseessaneeeeeeens 69 5 1 1 System clock oscillators istin eee yee cones ted cee aei sche scedts e ekaia 69 5 1 2 Clock oscillator for interval time generation eee ee eeeeeeeeeeeeeeenneeeeeeeeeeeeeneeeeeesaeeeeeneaeeeenaeeeeaaes 69 5 2 Configuration of Clock Generators ccessececeeeeeeeeeeeneneeeeseeeseeeseeeseeeseaeseeseseaeseeeseansesesenseeeneaes 70 5 3 Registers Controlling Clock Generators cecescccesseeceeeeeeeeeeeseeeeeeeseeeseeeeseaeseeeseaeseeeneneeeeseaes 72 5 4 System Clock Oscillators ccsic cccccscctecesiceecdesedecdevedececerevdeecesesitenee
200. eared to 0 Setto 1 Set cleared according to the result Previously saved value is stored Preliminary User s Manual U17446EJ 1VOUD 20 2 Operation List Mnemonic Operand r yte CHAPTER 20 INSTRUCTION SET OVERVIEW Clocks Operation r lt byte saddr byte saddr lt byte sfr byte sfr lt byte A r p Aer rA 4 rA A saddr A lt saddr saddr A saddr A A sfr A amp sfr sfr A sfr A A addr16 A lt addr16 laddr16 A addr16 A PSW byte PSW lt byte A PSW A lt PSW PSW A NTN wl wy wl ni nt ny i rn PSW lt A A DE m A lt DE DE A m DE A A HL A amp HL HL A HL A A HL byte A HL byte HL byte A HL byte A Notes 1 Remark A X Aox A r 2 DILPIL DIDI DAI ADI aI as AIAI oaJ ojoj RAI HR HR SS Aer A saddr A saddr A sfr A amp sfr A DE A DE A HL A amp HL A HL byte Exceptr A Exceptr A X One instruction clock cycle is one CPU clock cycle fcpu selected by the processor clock control register PCC A HL byte Preliminary User s Manual U17446EJ 1VOUD Mnemonic Operand rp word CHAPTER 20 INSTRUCTION SET OVERVIEW Clocks Operation rp lt word
201. earing TXE6 and RXE6 to 0 to set the operation stop mode To start the operation set POWER6 to 1 and then set TXE6 and RXE6 to 1 UART mode Take relationship with the other party of communication into consideration when setting the port mode register and port register Parity types and operation Fix the PS61 and PS60 bits to O when the device is incorporated in LIN Continuous transmission The TXBF6 and TXSF6 flags of the ASIF6 register change from 10 to 11 and to 01 during continuous transmission To check the status therefore do not use a combination of the TXBF6 and TXSF6 flags for judgment Judge whether continuous transmission is possible or not by reading only the TXBF flag When the device is incorporated in a LIN the continuous transmission function cannot be used Make sure that asynchronous serial interface transmission status register 6 ASIF6 is OOH before writing transmit data to transmit buffer register 6 TXB6 TXBF6 during Continuous Transmission Bit 1 of ASIF6 To transmit data continuously write the first transmit data first byte to the TXB6 register Be sure to check that the TXBF6 flag is 0 If so write the next transmit data second byte to the TXB6 register If data is written to the TXB6 register while the TXBF6 flag is 1 the transmit data cannot be guaranteed TXSF6 during Continuous Transmission Bit 0
202. ecifications Since this is the source file its working environment does not depend on any particular operating system Part number uwSxxxxCC78K0S L Notes 1 DF789234 is a common file that can be used with RA78KOS CC78KOS ID78KOS NS ID78KOS QB and SM for 78KOS 2 CC78KOS L is not included in the software package SP78KOS Preliminary User s Manual U17446EJ1VOUD 353 APPENDIX A DEVELOPMENT TOOLS Remark xxxx in the part number differs depending on the host machine and operating system to be used USxxxxRA78K0S USxxxxCC78KOS USXxxxCC78KO0S L Host Machine Supply Media PC 9800 series IBM PC AT Japanese Windows and compatibles English Windows HP9000 series 700 HP UX Rel 10 10 SPARCstation SunOS Rel 4 1 4 Solaris Rel 2 5 1 USxxxxDF789234 PC 9800 series IBM PC AT Japanese Windows 3 5 2HD FD and compatibles English Windows A 3 Control Software PM plus This is control software designed so that the user program can be efficiently developed Project manager in the Windows environment With this software a series of user program development operations including starting the editor build and starting the debugger can be executed on PM plus lt Caution gt PM plus is included in the assembler package RA78KOS It can be used only in the Windows environment A 4 Flash Memory Writing Tools Flashpro4 FL PR4 PG FP4 Flash prog
203. ed suv chic EAE S ssteefeceeeluecevsbecceeseces 270 19 4 Writing with Flash Programmer ssssnusseennnnunnunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnn 271 19 5 Programming Environment ssessessesnueeennnnnnnnnnnnnnnnnnnnnnnnnnnnnnunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nennen 272 19 6 Pin Connection ON Board ccceccecccceseeeneeeeeneeeeeeeneeseeeeeeeseeeeeeeseeeeseaeseeeseaeseseneaeseseseenseeseseensneeees 274 19 61 XP ANG X2 PINS aiene nne aae aa RAAE AEA aaa aa n AEAEE E hA AT AEE AA AEE 274 196 2 RESET Pili aara a a a a a a a 275 19 6 3 POrt PINS imanni an o a ea pinnae a a a o o iaai 276 19 64 P wer Supply eeestis a aa vaa aana aa eaat aa naia a a 276 19 7 On Board and Off Board Flash Memory Programming ssssnunsssnnnnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnna 277 19 7 Controlling NaS himMmemMO iy ieii eaea iea a aa ienei 277 19 7 2 Flash memory programming Mode eeeeceeeeeeeeeeeeeeeeeneeeeeeaeeeeeeaeeesneeeeeenaeeeeeeaeeeenneeeeneaa 278 19 7 3 Communication COMMANAS eect eeteee eee eeceeaeeeeeeeeeeeeaeeeseeaaeeeseneaeeesaaeeeseeaeeeseneeeeeenaeaeeaas 278 AOA Security SSUINGS 2 xiis sce cccn copes a a aa cebu dicdecttuds vee da a tet 279 19 8 Flash Memory Programming by Self Writing cccccccesseeeeeeseeneeeeseeeeeenseeeeeeenseeneeenseeeeenees 280 19 8 1 Outline of Self programming eee eeeeeeee eee eeeeenneeeceeeeeeeeaeeeeeeaaeeeeeneeeeeeaaeeeseeaeeeseeeeeeeeneeeeeaas 280
204. eesesesenseseenenens 153 9 4 1 Watchdog timer operation when low speed Ring OSC cannot be stopped is selected by option byte oo ee eee eeeeneeeeeeeeeeeeeaeeeeesaaeeeseeeaeeesneeeeseaeeeenenaees 153 9 4 2 Watchdog timer operation when low speed Ring OSC can be stopped by software is selected by option byte cccccceceesceceeeeeeeeeeeeeeeeeseseeeaeeeeeeeeeeee 155 9 4 3 Watchdog timer operation in STOP mode when low speed Ring OSC can be stopped by software is selected by option byte 157 9 4 4 Watchdog timer operation in HALT mode when low speed Ring OSC can be stopped by software is selected by option byte 159 CHAPTER 10 A D CONVERTER aaa fetes aaraa a Aaea ra A EK A a EM a ar AENEA even stteces 160 10 1 Functions of A D Converter sssssusssensnnunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnna na 160 10 2 Configuration of A D Converterf sssssseseenunnrnunnnnnnnnnnnnnnnnnunnnnnunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn ennnen nna 163 10 3 Registers Used by A D Converter sssuusseenunrenunnnnnnnnnnnnnnnnnnnnnnnunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn ennnen nna 164 10 4 A D Converter Operations ire m e eaaa a aa a a a aaa Ara aaae aa Ea de aannaaien aa 169 10 4 1 Basic operations of A D CONVETTER idap a a a 169 10 4 2 Input voltage and conversion results ccccccceeeceeeceeeeeeeeeeeaeeeeeeeceeeeaaeaeeeeeseseecueaeeeeeenseesnsaees 171 10 4 3 A D
205. efore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of port pins Preliminary User s Manual U17446EJ1VOUD 337 CHAPTER 21 ELECTRICAL SPECIFICATIONS TARGET VALUES X1 Oscillator Characteristics Ta 40 to 85 C Voo 2 0 to 5 5 V Vss 0 V Resonator Recommended Circuit Parameter Conditions Ceramic Oscillation resonator frequency fx Crystal Oscillation resonator frequency fx External X1 input 2 7 V lt Voo lt 5 5 V Note 2 clock frequency fx 2 0 V lt Voo lt 2 7 V X1 input high 2 7 V lt Voo lt 5 5 V low level width txh txt 2 0 V lt Voo lt 2 7 V Notes 1 Use this product in a voltage range of 2 2 to 5 5 V because the detection voltage Vroc of the power on clear POC circuit is 2 1 V 0 1 V 2 Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time Caution When using the X1 oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible e Do not cross the wiring with the other signal lines e Do not route the wiring near a signal line through which a high fluctuating current flows Always m
206. egister 3 PM3 1 2 For how to enable the INTTMOOO if necessary INTTMO010 interrupt see CHAPTER 13 INTERRUPT FUNCTIONS One shot pulse output with software trigger A one shot pulse can be output from the TOO0 pin by setting 16 bit timer mode control register 00 TMCOO capture compare control register 00 CRCO0O and 16 bit timer output control register 00 TOC00 as shown in Figure 6 32 and by setting bit 6 OSPT00 of the TOCO0 register to 1 by software By setting the OSPTOO bit to 1 16 bit timer event counter 00 is cleared and started and its output becomes active at the count value N set in advance to 16 bit timer capture compare register 010 CRO10 After that the output becomes inactive at the count value M set in advance to 16 bit timer capture compare register 000 CROOO N Even after the one shot pulse has been output the TMOO register continues its operation To stop the TM0O0 register the TMC003 and TMC002 bits of the TMCO0 register must be cleared to 00 Note The case where N lt M is described here When N gt M the output becomes active with the CR000 register and inactive with the CR010 register Do notset N to M Cautions 1 Do not set the OSPT00 bit to 1 again while the one shot pulse is being output To output the one shot pulse again wait until the current one shot pulse output is completed 2 When using the one shot pulse output of 16 bit timer event counter 00 with a software trigger do not
207. egister 6 191 Clock selection register 6 190 8 bit timer H compare register 01 135 8 bit timer H compare register 11 135 16 bit timer capture compare register 000 87 16 bit timer capture compare register 010 89 8 bit compare register 80 128 Capture compare control register 00 92 Flash address pointer H 288 Flash address pointer H compare register 288 Flash address pointer L 288 Flash address pointer L compare register 288 Flash programming command register 287 Flash programming mode control register 283 Flash write buffer register 289 Interrupt request flag register 0 225 Interrupt request flag register 1 225 External interrupt mode register 0 227 External interrupt mode register 1 228 Input switch control register 194 Low speed Ring OSC mode register 73 Low voltage detect register 257 Low voltage detection level select register 258 Preliminary User s Manual U17446EJ1VOUD 363 APPENDIX C REGISTER INDEX M MKO MK1 MRAO MRBO MULOH MULOL MULCO O OSTS P PO P2 P3 P4 P12 P13 PCC PFCMD PFS PMO PM2 PM3 PM4 PM12 PMC2 PPCC PRMOO PUO PU2 PU3 PU4 PU12 R RESF RXB6 RXS6 IT TMOO TM80 TMCOO TMC80 TMHMD1 TOCOO 364 Interrupt mask flag register 0 226 Interrupt mask flag register 1 226 Multiplication data register A 217 Multiplicat
208. egisters 116 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 2 CRO010 set value N N CROO0 set value M M M M Figure 6 33 Timing of One Shot Pulse Output Operation with Software Trigger Set TMCO00 to 04H TMOO count starts Count clock l l l l l l l l l l l l l TMOO count OOOOH Joon X N JN aX Jou TR Gv PD OE N N Z E _ _ _ _ _ _ OSPT00 INTTM010 l l auaaaaaaaaaaaaaaasasasasasasasasssusssssssssslslM INTTMO00 n o L _ wei ee iur TOOO pin output l Caution 16 bit timer counter 00 starts operating as soon as a value other than 00 operation stop mode is set to the TMC003 and TMC002 bits Remark N lt M One shot pulse output with external trigger A one shot pulse can be output from the TOO0 pin by setting 16 bit timer mode control register 00 TMCOO capture compare control register 00 CRC0O and 16 bit timer output control register 00 TOC00 as shown in Figure 6 34 and by using the valid edge of the TI000 pin as an external trigger The valid edge of the TI000 pin is specified by bits 4 and 5 ES000 ES010 of prescaler mode register 00 PRMOO The rising falling or both the rising and falling edges can be specified When the valid edge of the T1000 pin is detected the 16 bit timer event counter is cleared and started and the output becomes active at the coun
209. egisters FLAPHC FLAPLC Address FFA6H FFA7H After reset 00H R W FLAPHC FFA7H FLAPLC FFA6H SSS SSS Se FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP c11 c10 c9 ca c7 ce cs c4 c3 c2 c1 co Cautions 1 Be sure to clear bits 4 to 7 of FLAPH and FLAPHC to 0 before executing the self programming command If the value of these bits is 1 when executing the self programming command 2 Set the number of the block subject to a block erase write verify or blank check same value as FLAPH to FLAPHC 3 Clear FLAPLC to 00H when a block erase is performed and FFH when a blank check is performed 288 Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY 7 Flash write buffer register FLW This register is used to store the data to be written to the flash memory This register is set with a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears these registers to OOH Figure 19 18 Format of Flash Write Buffer Register FLW Address FFA8H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 aw Crow rune 8 Protect byte This protect byte is used to specify the area that is to be protected from writing or erasing The specified area is valid only in the self programming mode Because self programming of the protected area is invalid the data written to the protected area is guaranteed Figure 19 19 Format of Protect Byte 1 2 Addres
210. election 0 Operate as compare register 1 Operate as capture register Note If both the rising and falling edges have been selected as the valid edges of the T1000 pin capture is not performed Cautions 1 The timer operation must be stopped before setting CRCOO 2 When the clear amp start mode entered on a match between TMO00 and CRO00 is selected by 16 bit timer mode control register 00 TMC00 CR000 should not be specified as a capture register 3 To ensure the reliability of the capture operation the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 00 PRMOO0 refer to Figure 6 17 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 3 16 bit timer output control register 00 TOC00 This register controls the operation of the 16 bit timer event counter output controller It sets timer output F F set reset output inversion enable disable 16 bit timer event counter 00 timer output enable disable one shot pulse output operation enable disable and output trigger of one shot pulse by software TOC00 is set by a 1 bit or 8 bit memory manipulation instruction Generation of reset signal sets the value of TOCO0 to OOH Figure 6 7 Format of 16 Bit Timer Output Control Register 00 TOC00 Address FF63H After reset OOH R W Symbol 7 lt 6 gt lt 5 gt 4 lt 3 gt lt 2 gt 1 lt 0 gt tocoo o osptoo ospEoo Tocoo4
211. elow Figure 11 25 Permissible Baud Rate Range During Reception Latch timing VY V V V VY Y Data frame length F ere of UART6 Start bit Parity bit J Stop bit FL 1 data frame 11 x FL Minimum permissible Start bit Bit 0 Bit 1 Bit7 Parity bit Y Stop bit data frame length FLmin Maximum permissible Start bit Parity bit Stop bit data frame length FLmax As shown in Figure 11 25 the latch timing of the receive data is determined by the counter set by baud rate generator control register 6 BRGC6 after the start bit has been detected If the last data stop bit meets this latch timing the data can be correctly received Assuming that 11 bit data is received the theoretical values can be calculated as follows FL Brate Brate Baud rate of VART6 k Set value of BRGC6 FL 1 bit data length Margin of latch timing 2 clocks 214 Preliminary User s Manual U17446EJ1VOUD CHAPTER 11 SERIAL INTERFACE UART6 kK 2 _21k 2 Minimum permissible data frame length FLmin 11 x FL x FL ak FL Therefore the maximum receivable baud rate at the transmission destination is as follows 4 _ 22k BRmax FLmin 11 Brate 21k 2 Similarly the maximum permissible data frame length can be calculated as follows 10 X FLmax 11 Ele Sy Fike 21k 2 11 2xk 2xk FL 21k 2 FLmax FLx 11 Therefore the minimum receivable baud rate at the transmission destination is as foll
212. en operation is disabled Supply voltage Voo lt detection voltage Vivi Notes 1 Retained only after a reset by LVI 2 BitO is a read only bit 3 When LVION is set to 1 operation of the comparator in the LVI circuit is started Use software to instigate a wait of at least 0 2 ms from when LVION is set to 1 until the voltage is confirmed at LVIF 4 The value of LVIF is output as the interrupt request signal INTLVI when LVION 1 and LVIMD 0 Cautions 1 To stop LVI follow either of the procedures below e When using 8 bit manipulation instruction Write 00H to LVIM e When using 1 bit memory manipulation instruction Clear LVION to 0 2 Be sure to set bits 2 to 6 to 0 Preliminary User s Manual U17446E 1VOUD 257 CHAPTER 17 LOW VOLTAGE DETECTOR 2 Low voltage detection level select register LVIS This register selects the low voltage detection level This register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH Figure 17 3 Format of Low Voltage Detection Level Select Register LVIS Address FF51H After reset OOHN R W Symbol 7 6 5 3 f LVIS 0 0 0 0 LVIS3 LVIS2 LVIS1 LVISO Detection level Vivio 4 3 V 40 2 V Vivi 4 1 V 40 2 V Vivi2 3 9 V 40 2 V Vivis 3 7 V 40 2 V Vivia 3 5 V 40 2 V Vivis 3 3 V 40 15 V Vivie 3 1 V 40 15 V Vivi7 2 85 V 0 15 V Vivis 2 6 V 40 1 V Vivig 2 35 V 0 1 V
213. er Operation a 16 bit timer mode control register 00 TMC00 4 TMC003 TMC002 TMC001 OVFOO Twco0 CELTE b Capture compare control register 00 CRC00 Clears and starts on match between TMO0 and CROOO 3 CRC002 CRC001 CRC000 a CR000 used as compare register c Prescaler mode register 00 PRM00 ES110 ES100 ES010 ES000 3 2 PRM001 PRMO00 0 1 0 1 Polo 01 0 1 Selects count clock PRMOO0 0 1 0 1 Setting invalid setting 10 is prohibited Setting invalid setting 10 is prohibited Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with the interval timer See the description of the respective control registers for details Preliminary User s Manual U17446EJ 1VOUD 97 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 Figure 6 11 Interval Timer Configuration Diagram 16 bit timer capture compare register 000 CR000 INTTMO00 fxp fxp 2 fxp 28 16 bit timer counter 00 TMOO Selector Noise TIOOO INTPO P30 eliminator Clear circuit Note OVFOO0 is setto 1 only when 16 bit timer capture compare register 000 CR 000 is set to FFFFH fxP Figure 6 12 Timing of Interval Timer Operation toi o Count clock l l l TMO0 count value XW Kooper K X n Kooper A operation enabled INTTMO00 R FL od Interrupt acknowledged Interrupt a
214. er input T1000 T1010 Timer output TO00 output controller Control registers 16 bit timer mode control register 00 TMC00 Capture compare control register 00 CR C00 16 bit timer output control register 00 TOC00 Prescaler mode register 00 PRMOO Port mode register 3 PM3 Port register 3 P 3 Figures 6 1 shows a block diagram of these counters Figure 6 1 Block Diagram of 16 Bit Timer Event Counter 00 Internal bus f Capture compare control 4 register 00 CRC00 INTTM000 16 bit timer capture compare register 000 CR000 T1010 TOOO INTP2 P31 Match fxp fxp 2 fxp 28 Selector Output TO00 T1010 controller INTP2 P31 Output latch P31 TIOOO INTPO P30 16 bit timer capture compare register 010 CR010 INTTM010 4 CRC002 a a PRM000 TMC003 TMC002 TMC001 OVF00 JOSPT00 OSPE00 TOC004LVS00 LVRO0 TOC001 TOE0O 16 bit timer mode 16 bit timer output Prestalet mode control register 00 control register 00 register 00 PRM00 J4 TMC00 TOC00 Internal bus K 86 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 1 2 16 bit timer counter 00 TM00 TMOO0 is a 16 bit read only register that counts count pulses The counter is incremented in synchronization with the rising edge of the count clo
215. erasure cannot be performed for the device In addition even if a write command is executed data different from that which has already been written to the flash memory cannot be written because the erase command is disabled e Block erase Execution of the block erase command for a specific block in the flash memory is prohibited This prohibition setting can be cancelled using the batch erase chip erase command e Write Execution of the write and block erase commands for entire blocks in the flash memory is prohibited This prohibition setting can be cancelled using the batch erase chip erase command The batch erase chip erase block erase and write commands are enabled by the default setting when the flash memory is shipped The above security settings are possible only for on board off board programming Each security setting can be used in combination Table 19 8 shows the relationship between the erase and write commands when the 78KOS KB1 security function is enabled Table 19 8 Relationship Between Commands When Security Function Is Enabled Command Batch Erase Chip Block Erase Write Command Erase Command Command When batch erase chip erase security Disabled Disabled Enabled operation is enabled When block erase security operation is Enabled Enabled enabled When write security operation is enabled Disabled Note Since the erase command is disabled data different from that which has
216. ernal clock input circuit is divided For details of the option byte refer to CHAPTER 18 OPTION BYTE Preliminary User s Manual U17446EJ1VOUD 77 CHAPTER 5 CLOCK GENERATORS 5 5 Operation of CPU Clock Generator A clock fcpu is supplied to the CPU from the system clock fx oscillated by one of the following three types of oscillators e High speed Ring OSC oscillator Internally oscillates a clock of 8 MHz TYP e Crystal ceramic oscillator Oscillates a clock of 1 to 10 MHz e External clock input circuit Supplies a clock of 1 to 10 MHz to X1 pin The system clock oscillator is selected by the option byte For details of the option byte refer to CHAPTER 18 OPTION BYTE 1 High speed Ring OSC oscillator When the high speed Ring OSC oscillator is selected by the option byte the following is possible e Shortening of start time If the high speed Ring OSC oscillator is selected as the oscillator the CPU can be started without having to wait for the oscillation stabilization time of the system clock Therefore the start time can be shortened e Improvement of expandability If the high speed Ring OSC oscillator is selected as the oscillator the X1 and X2 pins can be used as I O port pins For details refer to CHAPTER 4 PORT FUNCTIONS Figures 5 8 and 5 9 show the timing chart and status transition diagram of the default start by the high speed Ring OSC oscillator Remark When the high speed Ring OSC oscillator is used the c
217. ernal verify error Performs abnormal termination processing when an error occurs PFCMD register control FLPMC register control sets value FLPMC register control inverts set value Sets normal mode via FLPMC register control sets value Checks completion of write to specific registers Repeats the same processing when an error occurs Restores interrupt mask flag Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY END abnormal termination processing Perform processing to shift to normal mode in order to return to normal processing StatusError StatusNormal Data to be written DataAdrTop DB XXH DB XXH DB XXH DB XXH DB XXH DataAdrBtm Preliminary User s Manual U17446EJ1VOUD 315 CHAPTER 19 FLASH MEMORY 19 8 11 Examples of operation when interrupt disabled time should be minimized in self programming mode Examples of operation when the interrupt disabled time should be minimized in self programming mode are explained below 1 Erasure to blank check lt 1 gt Specification of block erase command lt 1 gt to lt 5 gt in 19 8 6 lt 2 gt Mode is shifted from normal mode to self programming mode lt 1 gt to lt 5 gt in 19 8 4 lt 3 gt Execution of block erase command Error check lt 6 gt to lt 11 gt in 19 8 6 lt 4 gt Mode is shifted from self programming mode to normal mode lt 1 gt to lt 5 gt in 19 8 5 lt 5 gt Specification of blo
218. es in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of a customer s equipment shall be done under the full responsibility of the customer NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information e While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features e NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC Electronics products developed based on a customer designated quality assurance program for a specific application The recommended applications of an NEC Electronics products depend on its quality grade as indicated below Customers must check the quality grade of each NEC Electronics product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audi
219. es sirara Aaaa dE ectseetcensdbauteeteesbesteeeaie 133 8 1 Functions of 8 Bit Timer H1 00 0 cecceeseeee ee eeee eee eeeeeeeeeneeeeeeenseeeeeenssseeeenseeeeeeeaeeeeeesesseeeseesseenees 133 8 2 Configuration of 8 Bit Timer H1 cee cece eseeeeeeeeee seen seen ee enseeeeeeaseeeeeeeaseeeeeeesseeeesesesenseseeeenens 133 8 3 Registers Controlling 8 Bit Timer H1 cccccccessseeeeeeeeeeeeeseeeeeeeeseneeeeeaeeneeeeesseeeseseseeneeeseenens 136 8 4 Operation of 8 Bit Timer H1 cece ceseeeseeeee ee ee ee eeeeeeeeee seen enaeeaeneeeeseee sens easeeeeeseeesneeeeenenees 139 8 4 1 Operation as interval timer square wave Output ee ce ceeeeececeeeceeeeeeeceeeeeeeceeaeeeeeeeseseeneeeeeeeees 139 8 4 2 Operation as PWM output mode cccccceeeceecee cece ee eeeeeeaeceeeeeseeaaaaeceeeeeseseeeaeeeeeeeseseneeeeeeenees 142 CHAPTER 9 WATCHDOG TIMER tei cccvcccesctsccictes cecteenescecttctee cenetesceeth eden cunchesctenieeeedueesnecteasceeedencneebebe 148 9 1 Functions of Watchdog Timer ccecccesseneesesneeseeeeeeeeeeeeeeeseseseeeeseseeeeesesesneeseseeneeseseseeeseneeeenens 148 9 2 Configuration Of Watchdog Timer ceecccceseereeseseeeeeeeeeeeseeeeeeeseceseeeseseseeeesesesneesesesnenenneenenens 150 9 3 Registers Controlling Watchdog Timer cccccceseeseeseseeeseeeseeeseceeneeseseseeeseeeeneeesesesnenseneenanens 151 9 4 Operation of Watchdog Timer ccccceseeeeseseeeeeeeeeeeeseseeeseseeseeesesesneesesesneeseseen
220. eset signal generation by RESET input or power on clear POC circuit and reading RESF clear RESF to OOH Figure 15 5 Format of Reset Control Flag Register RESF Address FF54H After reset R Symbol RESF WDTRF LVIRF EARS ae SRANA WDTRF Internal reset request by watchdog timer WDT Internal reset request is not generated or RESF is cleared Internal reset request is generated Internal reset request by low voltage detector LVI Internal reset request is not generated or RESF is cleared Internal reset request is generated Note The value after reset varies depending on the reset source Caution Do not read data by a 1 bit memory manipulation instruction The status of RESF when a reset request is generated is shown in Table 15 2 Table 15 2 RESF Status When Reset Request Is Generated Lee oe RESET Input ResetbyPOC ResetbyWDT Reset by LVI Cleared 0 Cleared 0 Preliminary User s Manual U17446EJ1VOUD 251 16 1 CHAPTER 16 POWER ON CLEAR CIRCUIT Functions of Power on Clear Circuit The power on clear circuit POC has the following functions Generates internal reset signal at power on Compares supply voltage Vpop and detection voltage Vroc 2 1 V 0 1 V and generates internal reset signal when Vpop lt Vpoc Compares supply voltage Vpp and detection voltage Vpoc 2 1 V 0 1 V and releases internal reset signal when Vpop Vpoc Cautions 1 If an internal res
221. essing Remark lt 1 gt to lt 8 gt in Figure 19 28 correspond to lt 1 gt to lt 8 gt in 19 8 11 1 previous page Preliminary User s Manual U17446EJ1VOUD 317 CHAPTER 19 FLASH MEMORY An example of a program list when the interrupt disabled time from erasure to blank check should be minimized in self programming mode is shown below START FlashBlockErase Sets erase command MOV FLCMD 03H MOV FLAPH 07H MOV FLAPL 00H MOV FLAPHC 07H MOV FLAPLC 00H CALL ModeOn Execution of erase MOV PFS 00H MOV WDTE 0ACH HALT MOV A PFS CMP A 00H BNZ StatusError 318 Sets flash control command block erase Sets number of block to be erased block 7 is specified here Fixes FLAPL to 00H Sets erase block compare number same value as that of FLAPH Fixes FLAPLC to 00H Shift to self programming mode command Clears flash status register Clears amp restarts WDT Self programming is started Checks erase error Performs abnormal termination proceotsError Preliminary User s Manual U17446EJ1VOUD A 00H CALL BR ModeOff StatusNormal CHAPTER 19 FLASH MEMORY Shift to normal mode END abnormal termination processing Perform processing to shift to normal mode in order to return to normal processing StatusError END normal StatusNormal DI ModeOnLoop MOV MOV MOV MOV MOV MOV CMP
222. essing Software RA78K0S Program that converts program written in mnemonic into object code that can be executed by Assembler package microcontroller In addition automatic functions to generate symbol table and optimize branch instructions are also provided Used in combination with device file DF789234 sold separately lt Caution when used in PC environment gt The assembler package is a DOS based application but may be used under the Windows environment by using PM plus included in the assembler package Part number SxxxxRA78KOS CC78K0S Program that converts program written in C language into object codes that can be executed by C library package microcontroller Used in combination with assembler package RA78KOS and device file DF789234 both sold separately lt Caution when used in PC environment gt The C compiler package is a DOS based application but may be used under the Windows environment by using PM plus included in the assembler package Part number wSxxxxCC78K0S DF789234 File containing the information inherent to the device Device file Used in combination with other tools RA78K0OS CC78KOS ID78KOS NS ID78KOS QB or SM for 78KO0S Part number SxxxxDF 789234 CC78K0S LN Source file of functions constituting object library included in C compiler package C library source file Necessary for changing object library included in C compiler package according to customer s sp
223. et signal is generated in the POC circuit the reset control flag register RESF is cleared to 00H 2 Because the detection voltage Vroc of the POC circuit is in a range of 2 1 V 0 1 V use a voltage in the range of 2 2 to 5 5 V Remark This product incorporates multiple hardware functions that generate an internal reset signal A flag that 252 indicates the reset cause is located in the reset control flag register RESF for when an internal reset signal is generated by the watchdog timer WDT or low voltage detection LVI circuit RESF is not cleared to OOH and the flag is set to 1 when an internal reset signal is generated by WDT or LVI For details of RESF see CHAPTER 15 RESET FUNCTION Preliminary User s Manual U17446EJ1VOUD CHAPTER 16 POWER ON CLEAR CIRCUIT 16 2 Configuration of Power on Clear Circuit The block diagram of the power on clear circuit is shown in Figure 16 1 Figure 16 1 Block Diagram of Power on Clear Circuit Vop Voo S J ees Internal reset signal Reference voltage 3 ILE rce 16 3 Operation of Power on Clear Circuit In the power on clear circuit the supply voltage VoD and detection voltage Vroc 2 1 V 0 1 V are compared and an internal reset signal is generated when Vop lt Vpoc and an internal reset is released when Vpop Vpoc Figure 16 2 Timing of Internal Reset Signal Generation in Power on Clear Circuit Supply voltage VoD POC detection voltage Veoc
224. etect register 2 LVIS Low voltage detection level select register Preliminary User s Manual U17446EJ1VOUD Reset signal Reset signal to LVIM LVIS register 245 CHAPTER 15 RESET FUNCTION Figure 15 2 Timing of Reset by RESET Input lt 1 gt With high speed Ring OSC clock or external clock input High speed Ring OSC clock or external clock input Normal operation Reset period in progress CPU clock ees oscillation stops RESET Operation stops because option byte is referenced Internal reset signal H i J Delay Delay TYP 100ins TYP 100 ns Port pin Hi Z except P130 Port pin fie P130 Note 2 Notes 1 The operation stop time is 277 us MIN 544 us TYP and 1 075 ms MAX 2 When reset is effected P130 outputs a low level If P130 is set to output a high level before reset is effected the output signal of P130 can be dummy output as the reset signal to the CPU lt 2 gt With crystal ceramic oscillation clock Crystal ceramic oscillation clock i Oscillation stabilization Normal operation 1 time 2 fx to 2 reset processing CPU clock Normal operation in progress Reset period oscillation stops RESET Operation stops because option byte is referenced 1 Internal reset signal i Delay Delay TYP 100 ns TYP 100 ns Potpin Ne FUE nop Coe 42 OU th hte a iF except P130 Port pin P130 Note 2 N
225. ets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 3 5 Program Counter Configuration 15 0 2 Program status word PSW The program status word is an 8 bit register consisting of various flags to be set reset by instruction execution PC Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions RESET input sets PSW to 02H Figure 3 6 Program Status Word Configuration 7 0 ew e e oee e e a Interrupt enable flag IE This flag controls interrupt request acknowledge operations of the CPU When IE 0 the interrupt disabled DI status is set All interrupt requests are disabled When IE 1 the interrupt enabled El status is set Interrupt request acknowledgment is controlled with an interrupt mask flag for various interrupt sources This flag is reset to O upon DI instruction execution or interrupt acknowledgment and is set to 1 upon El instruction execution b Zero flag Z When the operation result is zero this flag is set to 1 It is reset to 0 in all other cases c Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set to 1 It is reset to O in all other cases Preliminary User s Manual U17446EJ1VOUD 33 CHAPTER 3 CPU ARCHITECTURE d Carry flag CY This fla
226. etting HALT mode immediately after the conversion starts Figure 10 19 Analog Input Pin Connection If there is a possibility that noise equal to or higher than AVrer or equal to or lower than AVss may enter clamp with a diode with a small Vr value 0 3 V or lower Reference voltage O t AVREF input ANIO to ANI3 C 0 01 to 0 1 uF A Preliminary User s Manual U17446EJ1VOUD 5 6 7 CHAPTER 10 A D CONVERTER ANI0 P20 to ANI3 P23 lt 1 gt The analog input pins ANIO to ANI3 are also used as input port pins P20 to P23 When A D conversion is performed with any of ANIO to ANI3 selected do not access port 2 P20 to P23 while conversion is in progress otherwise the conversion resolution may be degraded lt 2 gt If a digital pulse is applied to the pins adjacent to the pins currently used for A D conversion the expected value of the A D conversion may not be obtained due to coupling noise Therefore do not apply a pulse to the pins adjacent to the pin undergoing A D conversion Input impedance of ANIO to ANI3 pins In this A D converter the internal sampling capacitor is charged and sampling is performed for approx one sixth of the conversion time Since only the leakage current flows other than during sampling and the current for charging the capacitor also flows during sampling the input impedance fluctuates during sampling and in the other state If the shortest conversion time of the reference
227. f PPG Output 16 bit timer capture compare register 000 CR000 fxp fxp 2 fxp 28 Selector 16 bit timer counter 00 Clear TMOO0 circuit TIOOO INTPO P30 amp eliminator 5 Z i 8 TOO00 TI010 fxr 5 INTP2 P31 Q 5 re 16 bit timer capture compare register 010 CR010 Figure 6 31 PPG Output Operation Timing t o Count clock LLALL TMOO count value 3 Xoo00H Yoo01H por A XG UNN N X 0000H 0001HX e Clear 1 t f CR0O00 capture value o CR010 capture value Co l oy Pulse width M 1 E 1 l Laa l 1 cycle N 1 xt Remark 0000H lt M lt N lt FFFFH 114 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 6 4 6 One shot pulse output operation 16 bit timer event counter 00 can output a one shot pulse in synchronization with a software trigger or an external trigger T1000 pin input Setting The lt l gt lt 2 gt basic operation setting procedure is as follows Set the count clock by using the PRMOO register Set the CRCO0 register see Figures 6 32 and 6 34 for the set value Set the TOCOO register see Figures 6 32 and 6 34 for the set value Set any value to the CR000 and CRO1O registers 0000H cannot be set Set the TMC00 register to start the operation see Figures 6 32 and 6 34 for the set value Remarks 1 For the setting of the TO00 pin see 6 3 5 Port mode r
228. f programming error has occurred using bit 1 VCERR and bit 2 WEPRERR of PFS Abnormal lt 10 gt Normal lt 11 gt lt 10 gt Internal verify processing is abnormally terminated lt 11 gt Internal verify processing is normally terminated Note This setting is not required when the watchdog timer is not used 306 Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY Figure 19 25 Example of Internal Verify Operation in Self Programming Mode Internal verify lt 1 gt Set internal verify command FLCMD 01H lt 2 gt Set no of block for internal verify to FLAPH lt 3 gt Set start address to FLAPL lt 4 gt Set the same value as that of FLAPH to FLAPHC lt 5 gt Set end address to FLAPLC lt 6 gt Clear PFS lt 7 gt Clear amp restart WDT counter WDTE ACH Note lt 8 gt Execute HALT instruction Abnormal VCERR and WEPRERR flags Normal lt 11 gt Normal termination lt 10 gt Abnormal termination Note This setting is not required when the watchdog timer is not used Remark lt 1 gt to lt 11 gt in Figure 19 25 correspond to lt 1 gt to lt 11 gt in 19 8 9 previous page Preliminary User s Manual U17446EJ1VOUD 307 CHAPTER 19 FLASH MEMORY An example of a program list that performs an internal verify in self programming mode is shown below START FlashVerify MOV FLCMD 01H Sets flash control command internal veri
229. f the protect byte is read to bits 2 to 6 PRSELFO to PRSELF4 after reset is released 2 Bits 2 to 6 PRSELFO to PRSELF4 are read only Note the following when setting the self programming mode If an interrupt occurs during self programming the interrupt request flag is set 1 and interrupt servicing is performed after the self programming mode is released To avoid this operation disable interrupt servicing by setting MKO and MK1 to FFH and executing the DI instruction during self programming or before a mode is shifted from the normal mode to the self programming mode with a specific sequence No instructions can be executed while a self programming command is being executed Therefore clear and restart the watchdog timer counter in advance so that the watchdog timer does not overflow during self programming Refer to Table 19 11 for the time taken for the execution of self programming If the supply voltage drops or the reset signal is input while the flash memory is being written or erased writing erasing is not guaranteed When the oscillator or the external clock is selected as the main clock a wait time of 16 ws is required from setting FLSPM to 1 to execution of the HALT instruction Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY 2 Flash protect command register PFCMD If the application system stops inadvertently due to malfunction caused by noise or program hang up an operation to write
230. f the valid edge it cannot be used as a timer output TO00 When using P31 as the timer output pin TOOO it cannot be used as the input pin T1010 of the valid edge p 95 Interval timer Changing the CROO0 setting during TMOO operation may cause a malfunction To change the setting refer to 6 5 Cautions Related to 16 Bit Timer Event Counter 00 17 Changing compare register during timer operation p 96 External Event Counter When reading the external event counter count value TMOO should be read p 101 Pulse width measurement To use two capture registers set the TI000 and T1010 pins p 102 Square wave output Changing the CROO0 setting during TMOO operation may cause a malfunction To change the setting refer to 6 5 Cautions Related to 16 Bit Timer Event Counter 00 17 Changing compare register during timer operation p 110 PPG output Changing the CRCOn0 setting during TMOO operation may cause a malfunction To change the setting refer to 6 5 Cautions Related to 16 Bit Timer Event Counter 00 17 Changing compare register during timer operation p 112 O Values in the following range should be set in CR000 and CR010 0000H lt CR010 lt CR000 lt FFFFH p 113 The cycle of the pulse generated through PPG output CR000 setting value 1 has a duty of CR010 setting value 1 CROOO setting value 1 p 113 One
231. fied here MOV FLAPL 00H Fixes FLAPL to 00H MOV FLAPHC 07H Sets erase block compare number same value as that of FLAPH MOV FLAPLC 00H Fixes FLAPLC to 00H MOV PFS 00H Clears flash status register MOV WDTE 0ACH Clears amp restarts WDT HALT Self programming is started MOV A PFS CMP A 00H BNZ StatusError Checks erase error Performs abnormal termination processing when an error occurs FlashBlockBlankCheck MOV FLCMD 04H Sets flash control command block blank check MOV FLAPH 07H Sets number of block for blank check block 7 is specified here MOV FLAPL 00H Fixes FLAPL to 00H 310 Preliminary User s Manual U17446EJ1VOUD MOV MOV MOV MOV HALT MOV CMP BNZ ModeOffLoop MOV MOV MOV MOV MOV MOV CMP BNZ MOV MOV EI BR FLAPHC 07H FLAPLC 0FFH PFS 00H WDTE 0ACH A PFS A 00H StatusError FS 00H FCMD 0A5H LPMC 00H LPMC 0FFH 4J yy yj y LPMC 00H A PFS A 00H ModeOffLoop MKO INT_MKO MK1 INT_MK1 StatusNormal CHAPTER 19 FLASH MEMORY Sets blank check block compare number same value as of FLAPH Fixes FLAPLC to FFH Clears flash status register Clears amp restarts WDT Self programming is started Checks blank check error Performs abnormal termination processing when an error occurs PFCMD register control FLPMC register control sets value FLPMC register contro
232. fy MOV FLAPH 07H Sets verify start address with FLAPH block 7 is specified here MOV FLAPL 00H Sets verify start address with FLAPL Address 00H is Specified here MOV FLAPHC 07H MOV FLAPLC 20H Sets verify end address MOV PFS 00H Clears flash status register MOV WDTE 0ACH Clears amp restarts WDT HALT Self programming is started MOV A PFS MOV CmdStatus A Execution result is stored in variable CmdStatus 0 normal termination other than 0 abnormal termination END 308 Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY 19 8 10 Examples of operation when command execution time should be minimized in self programming mode Examples of operation when the command execution time should be minimized in self programming mode are explained below 1 Erasure to blank check lt 1 gt Mode is shifted from normal mode to self programming mode lt 1 gt to lt 5 gt in 19 8 4 lt 2 gt Execution of block erase Error check lt 1 gt to lt 11 gt in 19 8 6 lt 3 gt Execution of block blank check Error check lt 1 gt to lt 11 gt in 19 8 7 lt 4 gt Mode is shifted from self programming mode to normal mode lt 1 gt to lt 5 gt in 19 8 5 Figure 19 26 Example of Operation When Command Execution Time Should Be Minimized from Erasure to Blank Check Erasure to blank check Figure 19 20 lt 1 gt Shift to self programming lt 1 gt to lt 5 gt mode lt 2 gt Execute bl
233. g OSC is selected by the option byte as the clock source the X1 and X2 pins can be used as I O port pins For details of the option byte refer to CHAPTER 18 OPTION BYTE For details of I O ports refer to CHAPTER 4 PORT FUNCTIONS 5 4 2 Crystal ceramic oscillator The crystal ceramic oscillator oscillates using a crystal or ceramic resonator connected between the X1 and X2 pins If the crystal ceramic oscillator is selected by the option byte as the system clock source the X1 and X2 pins are used as crystal or ceramic resonator connection pins For details of the option byte refer to CHAPTER 18 OPTION BYTE For details of I O ports refer to CHAPTER 4 PORT FUNCTIONS Figure 5 6 shows the external circuit of the crystal ceramic oscillator Figure 5 6 External Circuit of Crystal Ceramic Oscillator Crystal resonator or ceramic resonator Caution When using the crystal ceramic oscillator wire as follows in the area enclosed by the broken lines in Figure 5 6 to avoid an adverse effect from wiring capacitance e Keep the wiring length as short as possible e Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as Vss Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator Preliminary User s
234. g stores overflow and underflow that have occurred upon add subtract instruction execution It stores the shift out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution 3 Stack pointer SP This is a 16 bit register to hold the start address of the memory stack area Only the internal high speed RAM area can be set as the stack area the stack area cannot be set except internal high speed RAM area Figure 3 7 Stack Pointer Configuration 15 0 The SP is decremented before writing saving to the stack memory and is incremented after reading SP restoring from the stack memory Each stack operation saves restores data as shown in Figures 3 8 and 3 9 Caution Since generation of reset signal makes the SP contents undefined be sure to initialize the SP before using the stack memory Figure 3 8 Data to Be Saved to Stack Memory PUSH rp CALL CALLT Interrupt instruction instructions SP SP 3 A SP SP 2 SP SP 2 SP3 PC7 to PCO SP 2 Loweritialt SP 2 PC7 to PCO SP 2 PC15 to PC8 register pairs A SP 1 Upper half SP 1 PC15 to PC8 SP 1 PSW register pairs 4 A SP gt SP gt SP gt Figure 3 9 Data to Be Restored from Stack Memory POP rp RET instruction RETI instruction instruction SP gt Lower half SP PC7 to PCO SP gt PC7 to PCO register pairs SP 44 Upper half
235. ge of the TI000 pin or free running mode is selected when the set value of CROOO is FFFFH and the TMOO value changes from FFFFH to 0000H the OVFOO flag is set to 1 Preliminary User s Manual U17446EJ1VOUD p 91 APPENDIX D LIST OF CAUTIONS Chapter 6 Soft Classification Hard Soft Soft Hard Hard Function 16 bit timer event counter 00 Details of Function TMCOO 16 Bit Timer Mode Control Register 00 Cautions Even if the OVFOO flag is cleared before the next count clock is counted before TMO0 becomes 0001H after the occurrence of a TMOO overflow the OVFO0 flag is re set newly and clear is disabled 4 18 p 91 0 The capture operation is performed at the fall of the count clock An interrupt request input INTTMOn0 however occurs at the rise of the next count clock p 91 0O CRCOO Capture compare control register 00 The timer operation must be stopped before setting CRCOO p 92 When the clear amp start mode entered on a match between TMO0 and CROO0 is selected by 16 bit timer mode control register 00 TMCO00 CROOO should not be specified as a capture register p 92 To ensure the reliability of the capture operation the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 00 PRMOO refer to Figure 6 17 p 92 TOCOO 16 bit timer
236. he watchdog timer does not overflow during self programming Refer to Table 19 11 for the time taken for the execution of self programming RAM is not used while a self programming command is being executed If the supply voltage drops or the reset signal is input while the flash memory is being written or erased writing erasing is not guaranteed The value of the blank data set during block erasure is FFH Preliminary User s Manual U17446EJ1VOUD 381 APPENDIX D LIST OF CAUTIONS Chapter 19 Soft Classification Function Details of Function Self programming function Cautions When the oscillator or the external clock is selected as the main clock a wait time of 16 ws is required starting from the setting of the self programming mode to the execution of the HALT instruction 17 18 The state of the pins in self programming mode is the same as that in HALT mode Since the security function set via on board off board programming is disabled in self programming mode the self programming command can be executed regardless of the security function setting To disable write or erase processing during self programming set the protect byte Be sure to clear bits 4 to 7 of flash address pointer H FLAPH and flash address pointer H compare register FLAPHC to 0 before executing the self programming command If the value of these bits is
237. high speed RAM 256 x 8 bits FF20H i FEIRA OTEA E FEOOH FDFFH Direct addressing Register indirect addressing Based addressing Use prohibted 1000H OFFFH Flash memory 4 096 x 8 bits 0000H i Preliminary User s Manual U17446EJ1VOUD 31 CHAPTER 3 CPU ARCHITECTURE Figure 3 4 Data Memory Addressing uPD78F9234 FFFFH Special function registers SFR 256 x 8 bits SFR addressing FF20H FENER A ARAA ARE A a E E E E E Hac FFOOH FEFFH Short direct addressing Internal high speed RAM 256 x 8 bits FE20H FE1FH FEOOH FDFFH Direct addressing Register indirect addressing Based addressing Use prohibited 2000H 1FFFH Flash memory 8 192 x 8 bits 0000H 1 Preliminary User s Manual U17446EJ1VOUD CHAPTER 3 CPU ARCHITECTURE 3 2 Processor Registers The 78K0S KB1 provides the following on chip processor registers 3 2 1 Control registers The control registers have special functions to control the program sequence statuses and stack memory The control registers include a program counter a program status word and a stack pointer 1 Program counter PC The program counter is a 16 bit register which holds the address information of the next program to be executed In normal operation the PC is automatically incremented according to the number of bytes of the instruction to be fetched When a branch instruction is executed immediate data or register contents are set RESET input s
238. ibited Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with the external event counter See the description of the respective control registers for details 100 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 Figure 6 15 External Event Counter Configuration Diagram Q Internal bus 16 bit timer capture compare register 000 CR000 Match INTTMO00 16 bit timer counter 00 TMO0 OVFOONete fxp Noise eliminator Valid edge of TI000 Note OVFO0 is 1 only when 16 bit timer capture compare register 000 CR000 is set to FFFFH Figure 6 16 External Event Counter Operation Timing with Rising Edge Specified 1 INTTM000 generation timing immediately after operation starts Counting is started after a valid edge is detected twice Count starts T1000 pin input 1 Le Lh PLILI LI LL Lo l TMOO count value 0000H X 0001H X 0002H 0003HX X N 2 X N 1 X N Y0000HY0001H 0002H l CR000 N i INTTMO00 2 INTTM000 generation timing after INTTM000 has been generated twice Tiooo pin input LJ LJ LI LI LI 1 PTY ea Meal Thi Lee l l TMOO count value N 0000H 0001H 0002H 0003H 0004HX X N 1 X N 0000H 0001H 0002H X 0003H X CROOO N i INTTMOOO M 1 Caution When reading the external event counter count value TM00 should be read Preliminary User s Manual U17446E 1VOUD 101 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00
239. ic field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequate When it is dry a humidifier should be used It is recommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels I O settings or contents of registers A device is not initialized until the reset signal is received A reset operation must be executed immediately after power on for devices with reset functions POWER ON OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface as a rule switch on the external power supply
240. ified here Sets address to which data is to be written with FLAPL address 20H is specified here Sets data to be written 10H is specified here Clears flash status register Clears amp restarts WDT Self programming is started Execution result is stored in variable CmdStatus 0 normal termination other than 0 abnormal termination Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY 305 CHAPTER 19 FLASH MEMORY 19 8 9 Example of internal verify operation in self programming mode An example of the internal verify operation in self programming mode is explained below lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt 6 gt lt 7 gt lt 8 gt lt Q gt Set 01H internal verify to the flash program command register FLCMD Set the number of block for which internal verify is performed to flash address pointer H FLAPH Sets the verify start address to flash address pointer L FLAPL Write the same value as that of FLAPH to the flash address pointer H compare register FLAPHC Sets the verify end address to the flash address pointer L compare register FLAPLC Clear the flash status register PFS Write ACH to the watchdog timer enable register WDTE clear and restart the watchdog timer counter Execute the HALT instruction then start self programming Execute an instruction immediately after the HALT instruction if self programming has been executed Check if a sel
241. ing Notes 1 If reset is generated again during this period initialization processing is not started 2 A flowchart is shown on the next page 254 Preliminary User s Manual U17446EJ1VOUD CHAPTER 16 POWER ON CLEAR CIRCUIT Figure 16 3 Example of Software Processing After Release of Reset 2 2 e Checking reset cause Check reset source WDTRF of RESF Yes register 1 Reset processing by watchdog timer LVIRF of RESF Yes register 1 Reset processing by low voltage detector Power on clear external reset generated Preliminary User s Manual U17446EJ1VOUD 255 CHAPTER 17 LOW VOLTAGE DETECTOR 17 1 Functions of Low Voltage Detector The low voltage detector LVI has following functions e Compares supply voltage Vop and detection voltage Vivi and generates an internal interrupt signal or internal reset signal when Vop lt Vivi e Detection levels ten levels of supply voltage can be changed by software e Interrupt or reset function can be selected by software e Operable in STOP mode When the low voltage detector is used to reset bit 0 LVIRF of the reset control flag register RESF is set to 1 if reset occurs For details of RESF refer to CHAPTER 15 RESET FUNCTION 17 2 Configuration of Low Voltage Detector The block diagram of the low voltage detector is shown in Figure 17 1 Figure 17 1 Block Diagram of Low Voltage Detector Voo N ch Internal reset signal
242. ing OSC oscillation 240 kHz TYP Port CMOS I O 13 15 CMOS input 1 1 CMOS output 1 16 bit TMO 8 bit TMH 8 bit TM 8 WDT lch Serial interface LIN Bus supporting UART 1 ch A D converter 10 bits 4 ch 2 7 to 5 5V Multiplier 8 bits x 8 bits Provided Interrupts External Internal RESET pin Provided POC 2 1V 40 1 V LVI Provided selectable by software WDT Provided Operating temperature range Note Use this product in a voltage range of 2 2 to 5 5 V because the detection voltage Vroc of the power on clear POC circuit is 2 1 V 0 1 V 18 40 to 85 C Preliminary User s Manual U17446EJ 1VOUD 1 6 Block Diagram CHAPTER 1 OVERVIEW TO00 T1010 P31 16 bit TIMER EVENT COUNTER 00 T1000 P30 gt 8 bit TIMER 80 K gt TOH1 P42 _ 8 bit TIMER H1 LOW SPEED Ring OSC WATCHDOG TIMER K gt SERIAL INTERFACE UART6 RxD6 P44 TxD6 P43 _ ANIO P20 ANI3 P23 AVREF AVss A D CONVERTER INTPO P30 INTERA INTERRUPT CONTROL MULTIPLIER K gt INTP2 P31 INTP3 P41 78K0S CPU CORE FLASH MEMORY INTERNAL HIGH SPEED RAM Preliminary User s Manual U17446EJ 1VOUD P34 gt re POWER ON CLEAR LOW VOLTAGE OR INDICATOR RESET CONTROL SYSTEM RESET P34 CONTROL
243. ing is not required when the watchdog timer is not used Preliminary User s Manual U17446EJ1VOUD 297 CHAPTER 19 FLASH MEMORY Figure 19 22 Example of Block Erase Operation in Self Programming Mode lt 1 gt Set erase command FLCMD 03H lt 2 gt Set no of block to be erased to FLAPH lt 3 gt Set FLAPL to 00H lt 4 gt Set the same value as that of FLAPH to FLAPHC lt 5 gt Set FLAPLC to 00H lt 6 gt Clear PFS lt 7 gt Clear amp restart WDT counter WDTE ACH Note lt 8 gt Execute HALT instruction lt 9 gt Check execution resul VCERR and WEPRERR flags Abnormal lt 11 gt Normal termination lt 10 gt Abnormal termination Note This setting is not required when the watchdog timer is not used Remark lt 1 gt to lt 11 gt in Figure 19 22 correspond to lt 1 gt to lt 11 gt in 19 8 6 previous page 298 Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY An example of a program list that performs a block erase in self programming mode is shown below START FlashBlockErase MOV FLCMD 03H Sets flash control command block erase MOV FLAPH 07H Sets number of block to be erased block 7 is specified here MOV FLAPL 00H Fixes FLAPL to 00H MOV FLAPHC 07H Sets erase block compare number same value as that of FLAPH MOV FLAPLC 00H Fixes FLAPLC to 00H MOV PFS 00H Clears flash status register MOV WDTE 0ACH Clears amp
244. ing register pair DE Instruction code 0 0 1 0 1 0 1 1 Illustration Memory address specified by register pair DE The contents of addressed memory are transferred 7 46 Preliminary Users Manual U17446EJ1VOUD CHAPTER 3 CPU ARCHITECTURE 3 4 6 Based addressing Function 8 bit immediate data is added to the contents of the base register that is the HL register pair and the sum is used to address the memory Addition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Description example MOV A HL 10H When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 Illustration 10 Memory The contents of the memory addressed are transferred Preliminary User s Manual U17446EJ1VOUD 47 CHAPTER 3 CPU ARCHITECTURE 3 4 7 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatically employed when the PUSH POP subroutine call and return instructions are executed or the register is saved restored upon interrupt request generation Stack addressing can be used to access the internal high speed RAM area only Description example In the case of PUSH DE Instruction code 1 0 1 0 1 0 1 0 Illustration 7 Memory 0 SP FEEOH FEEOH FEDFH D SP
245. interface cable required when using a notebook type PC as the host machine PCMCIA socket supported IE 70000 PC IF C Interface adapter Adapter required when using IBM PC AT and compatibles as the host machine ISA bus supported IE 70000 PCI IF A Interface adapter Adapter required when using a personal computer incorporating the PCI bus is used as the host machine IE 789234 NS EM1 Emulation board Emulation board for emulating the peripheral hardware inherent to the device Used in combination with in circuit emulator A target cable is provided NP 30MC Emulation probe This probe is used to connect the in circuit emulator to the target system and is designed for use with a 30 pin plastic SSOP MC 5A4 type NSPACK30BK YSPACK30BK Conversion connector This conversion connector connects the NP 30MC to a target system board designed to mount a 30 pin plastic SSOP MC 5A4 type e NSPACK30BK Connector for connecting target e YSPACK30BK Connector for connecting emulator QB 80 EP 01T Emulation probe This emulation probe is flexible type and used to connect the in circuit emulator and target system This probe is designed for use with a 30 pin plastic SSOP MC 5A4 type QB 30MC EA 01T This exchange adapter is used to perform pin conversion from the in circuit emulator to target connector QB 30MC YQ 01T This YQ connector is used to connect the target connector and exchange adapter
246. ion Ta 40 to 85 C Voo 2 0 to 5 5 V Vss 0 V Parameter Cycle time minimum instruction execution time Conditions Crystal ceramic oscillation 4 0 V lt Voo lt 5 5 V clock external clock input 3 0 V lt Voo lt 4 0 V 2 7 V lt Voo lt 3 0 V 0 4 2 0 V lt Voo lt 2 7 V 1 High speed Ring OSC 4 0 V lt Voo lt 5 5 V 0 23 clock 2 7 V lt Voo lt 4 0 V 0 47 2 0 V lt Voo lt 2 7 V 0 95 T1000 input high level width low level width 4 0 V lt Voo lt 5 5 V 2 fsam 0 1 Note 2 2 0 V lt Voo lt 4 0 V 2 fsam 0 Note 2 Interrupt input high level width low level width 1 RESET input low level width Notes 1 Use this product in a voltage range of 2 2 to 5 5 V because the detection voltage VPoc of the power on clear POC circuit is 2 1 V 0 1 V 2 Selection of fsam fxp fxP 4 or fxP 256 is possible using bits O and 1 PRMO00 PRMO01 of prescaler mode register 00 PRMOO Note that when selecting the TI000 valid edge as the count clock fsam fxp 342 Preliminary User s Manual UU17446EJ1VOUD CHAPTER 21 ELECTRICAL SPECIFICATIONS TARGET VALUES Tcy vs Voo Crystal C eramic Oscillation Clock External Clock Input Guaranteed ration range Cycle time Toy us Supply voltage Vop V
247. ion and changing MKO and MK to restore the original state Mode shift is completed Caution Be sure to perform the series of operations described above using the user program at an 294 address where data is not erased nor written Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY Figure 19 21 Example of Shifting to Normal Mode Shift to normal mode lt 1 gt Clear PFS PFCMD ASH FLPMC OOH set value Set value is invalid lt 2 gt FLPMC OFFH inverted set value FLPMC OOH set value Set value is valid Abnormal lt 3 gt Check execution resulf lt 4 gt Enable interrupts by executing El instruction and changing When interrupt function is used MKO MK1 lt 5 gt Termination Caution Be sure to perform the series of operations described above using the user program at an address where data is not erased nor written Remark lt 1 gt to lt 5 gt in Figure 19 21 correspond to lt 1 gt to lt 5 gt in 19 8 5 previous page Preliminary User s Manual U17446EJ1VOUD 295 CHAPTER 19 FLASH MEMORY An example of a program list that shifts the mode to normal mode is shown below START ModeOffLoop MOV PFS 00H MOV PFCMD 0A5H PFCMD register control MOV FLPMC 00H FLPMC register control sets value MOV FLPMC 0FFH FLPMC register control inverts set value MOV FLPMC 00H Sets normal mode via FLPMC register control sets value MOV A PFS CM
248. ion data register B 217 16 bit multiplication result storage register H 37 217 16 bit multiplication result storage register L 37 217 Multiplier control register 0 219 Oscillation stabilization time select register 74 236 Port register 0 65 Port register 2 65 Port register 3 65 Port register 4 65 Port register 12 65 Port register 13 65 Processor clock control register 72 Flash protect command register 285 Flash status register 286 Port mode register 0 64 Port mode register 2 64 168 Port mode register 3 64 95 Port mode register 4 64 138 194 Port mode register 12 64 Port mode control register 2 66 168 Preprocessor clock control register 72 Prescaler mode register 00 94 Pull up resistor option register 0 67 Pull up resistor option register 2 67 Pull up resistor option register 3 67 Pull up resistor option register 4 67 Pull up resistor option register 12 67 Reset control flag register 251 Receive buffer register 6 185 Receive shift register 6 185 16 bit timer counter 00 87 8 bit timer counter 80 128 16 bit timer mode control register 00 90 8 bit timer mode control register 80 129 8 bit timer H mode register 1 136 16 bit timer output control register 00 93 Preliminary User s Manual U17446EJ1VOUD APPENDIX C REGISTER INDEX TXB6 Transmit buffer register 6 18
249. ion is resumed 10 18 p 177 O Conversion results just after A D conversion start The first A D conversion value immediately after A D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1 ws after the ADCE bit was set to 1 or if the ADCS bit is set to 1 with the ADCE bit 0 Take measures such as polling the A D conversion end interrupt request INTAD and removing the first conversion result p 178 O A D conversion result register ADCR ADCRH read operation When a write operation is performed to the A D converter mode register ADM and analog input channel specification register ADS the contents of ADCR and ADCRH may become undefined Read the conversion result following conversion completion before writing to ADM and ADS Using a timing other than the above may cause an incorrect conversion result to be read p 178 Chapter 11 Soft Hard Serial interface UART6 UART mode The TxD6 output inversion function inverts only the transmission side and not the reception side To use this function the reception side must be ready for reception of inverted data p 179 If clock supply to serial interface UART6 is not stopped e g in the HALT mode normal operation continues If clock supply to serial interface VART6 is stopped e g in the STOP mode each register stops operating and holds the value immediately before c
250. ion is started Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61 PS60 and CL6 bits Fix the PS61 and PS60 bits to 0 when mounting the device on LIN Make sure that TXE6 0 when rewriting the SL6 bit Reception is always performed with the number of stop bits 1 and therefore is not affected by the set value of the SL6 bit Make sure that RXE6 0 when rewriting the ISRM6 bit Preliminary User s Manual U17446EJ1VOUD 187 CHAPTER 11 SERIAL INTERFACE UART6 2 Asynchronous serial interface reception error status register 6 ASIS6 This register indicates an error status on completion of reception by serial interface UART6 It includes three error flag bits PE6 FE6 OVE6 This register is read only by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH if bit 7 POWERS and bit 5 RXE6 of ASIM6 0 OOH is read when this register is read Figure 11 6 Format of Asynchronous Serial Interface Reception Error Status Register 6 ASIS6 Address FF93H After reset OOH R Symbol 7 6 5 4 3 2 1 0 Status flag indicating parity error If POWERS6 0 and RXE6 0 or if ASIS6 register is read If the parity of transmit data does not match the parity bit on completion of reception E Status flag indicating framing error If POWERS6 0 and RXE6 0 or if ASIS6 register is read If the stop bit is not detected on completion of reception OVE6 Status flag indicati
251. ion time lt 2 gt If the clock source is frit clock supply to the watchdog timer is stopped under the following conditions e f the CPU clock is fx and if fR is stopped by software before execution of the STOP instruction e In HALT STOP mode Remarks 1 fr Low speed Ring OSC clock oscillation frequency 2 fx Oscillation frequency of system clock Preliminary User s Manual U17446EJ1VOUD 149 CHAPTER 9 WATCHDOG TIMER 9 2 Configuration of Watchdog Timer The watchdog timer consists of the following hardware Table 9 3 Configuration of Watchdog Timer Control registers Watchdog timer mode register WDTM Watchdog timer enable register WDTE Figure 9 1 Block Diagram of Watchdog Timer 2 faL to 2 8 faL 2 fri 2 Output Internal reset signal controller Selector fx 24 gt or 2 3 fx to 220 fx Option byte ae ou to set low speed Ring OSC cannot be Watchdog timer enable register WDTE Watchdog timer mode ad stopped or low speed register WDTM Ring OSC can be stopped by software Internal bus 150 Preliminary User s Manual U17446EJ1VOUD CHAPTER 9 WATCHDOG TIMER 9 3 Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers e Watchdog timer mode register WDTM e Watchdog timer enable register WDTE 1 Watchdog timer mode register WDTM This register sets the overflow time and operati
252. ion with fri 480 kHz MAX e Counting starts 2 The following should be set in the watchdog timer mode register WDTM by an 8 bit memory manipulation instructionN s 2 3 e Operation clock Any of the following can be selected using bits 3 and 4 WDCS3 and WDCS4 Low speed Ring OSC clock fr System clock fx Watchdog timer operation stopped e Cycle Set using bits 2 to O WDCS2 to WDCS0 3 After the above procedures are executed writing ACH to WDTE clears the count to 0 enabling recounting Notes 1 As soon as WDTM is written the counter of the watchdog timer is cleared 2 Set bits 7 6 and 5 to 0 1 1 respectively Do not set the other values 3 If the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and x respectively an internal reset signal is not generated even if the following processing is performed e WODTM is written a second time e A 1 bit memory manipulation instruction is executed to WDTE e A value other than ACH is written to WDTE Caution In this mode watchdog timer operation is stopped during HALT STOP instruction execution After HALT STOP mode is released counting is started again using the operation clock of the watchdog timer set before HALT STOP instruction execution by WDTM At this time the counter is not cleared to 0 but holds its value For the watchdog timer operation during STOP mode and HALT mode in each status see 9 4 3 Watchdog timer operation in STOP mode when low speed Ring OSC c
253. ircuits and Connection of Unused Pins Table 2 1 shows I O circuit type of each pin and the connections of unused pins For the configuration of the I O circuit of each type refer to Figure 2 1 Table 2 1 Types of Pin I O Circuits and Connection of Unused Pins Pin Name I O Circuit Type Recommended Connection of Unused Pin POO to P03 Independently connect to Voo or Vss via a resistor Leave open P20 ANI0O to P23 ANI3 Independently connect to AVrer or Vss via a resistor Leave open P30 TIOOO INTPO Independently connect to Voo or Vss via a resistor Leave open P31 T1010 TOOO INTP2 P32 and P33 P34 RESET Connect to Voo via a resistor P40 Input Independently connect to Voo or Vss via a resistor Output Leave open P41 INTP3 P42 TOH1 P43 TxD6 INTP1 P44 RxD6 P45 to P47 P120 P121 X1 Input Independently connect to Vss via a resistor Output Leave open P122 X2 P123 Input Independently connect to Voo or Vss via a resistor Output Leave open P130 Leave open AVREF Directly connect to Vob AVss Connect directly to Vss 26 Preliminary User s Manual U17446EJ1VOUD CHAPTER 2 PIN FUNCTIONS Figure 2 1 Pin I O Circuits Pull up Do E i enable AVREF Ea a e o IN OUT Output n on disable TIT Comparator P ch t l ae N ch Mae AVREF 7h AVss Threshold voltage Schmitt triggered input
254. is N the setting value of the CMP11 register is M and the count clock frequency is font the PWM pulse output cycle and duty are as follows PWM pulse output cycle N 1 fcnt Duty Active width Total width of PWM M 1 N 1 Cautions 1 In PWM output mode three operation clocks signal selected using the CKS12 to CKS10 bits of the TMHMD1 register are required to transfer the CMP11 register value after rewriting the register 2 Be sure to set the CMP11 register when starting the timer count operation TMHE1 1 after the timer count operation was stopped TMHE1 0 be sure to set again even if setting the same value to the CMP11 register Preliminary User s Manual U17446EJ1VOUD 143 CHAPTER 8 8 BIT TIMER H1 2 Timing chart The operation timing in PWM output mode is shown below Caution Make sure that the CMP11 register setting value M and CMPO1 register setting value N are within the following range 00H lt CMP11 M lt CMPO1 N lt FFH Figure 8 9 Operation Timing in PWM Output Mode 1 4 a Basic operation comse U LSU UU ULIUUUULIU sit umer counter H1 oon OTH DOCH i 1 1 1 1 1 CMP01 A5H e l i l l CMP11 01H a a a a a a a Tar s TMHE1 T INTTMH1 n TOHI TOLEV1 0 lt 1 gt 1 lt 2 gt 1 lt 3 gt lt 4 gt TOH ___ nnn TOLEV1 1 lt 1 gt The count operation is enabled by setting the TMHE1 bit to 1 Start 8 bit timer co
255. it I O port with an output latch Each bit of this port can be set to the input or output mode by using port mode register 12 PM12 When the P120 and P123 pins are used as an input port an on chip pull up resistor can be connected by using pull up resistor option register 12 PU12 The P121 and P122 pins are also used as the X1 and X2 pins of the system clock oscillator The functions of the P121 and P122 pins differ therefore depending on the selected system clock oscillator The following three system clock oscillators can be used 1 High speed Ring OSC oscillator The P121 and P122 pins can be used as I O port pins 2 Crystal ceramic oscillator The P121 and P122 pins cannot be used as I O port pins because they are used as the X1 and X2 pins 60 Preliminary User s Manual U17446EJ1VOUD CHAPTER 4 PORT FUNCTIONS 3 External clock input The P121 pin is used as the X1 pin to input an external clock and therefore it cannot be used as an I O port pin The P122 pin can be used as an O port pin The system clock oscillation is selected by the option byte For details refer to CHAPTER 18 OPTION BYTE Generation of reset signal sets port 12 to the input mode Figures 4 12 and 4 13 show the block diagrams of port 12 MA Internal bus T WReu Figure 4 12 Block Diagram of P120 and P123 PU120 PU123 WRpeort PU12 P12 PM12 RD WRxx Selector lt Output latch
256. l inverts set value Sets normal mode via FLPMC register control sets value Checks completion of write to specific registers Repeats the same processing when an error occurs Restores interrupt mask flag END abnormal termination processing Perform processing to shift to normal mode in order to return to normal processing END normal termination processing StatusNormal Preliminary User s Manual U17446EJ1VOUD 311 CHAPTER 19 FLASH MEMORY 2 Write to internal verify lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt 6 gt Mode is shifted from normal mode to self programming mode lt 1 gt to lt 5 gt in 19 8 4 Specification of source data for write Execution of byte write Error check lt 1 gt to lt 10 gt in 19 8 8 lt 3 gt is repeated until all data are written Execution of internal verify Error check lt 1 gt to lt 11 gt in 19 8 9 Mode is shifted from self programming mode to normal mode lt 1 gt to lt 5 gt in 19 8 5 Figure 19 27 Example of Operation When Command Execution Time Should Be Minimized from Write to Internal Verify Write to internal verify Figure 19 20 lt 1 gt Shift to self programming lt 1 gt to lt 5 gt mode lt 2 gt Set source data for write lt 3 gt Execute byte write command Figure 19 24 lt 1 gt to lt 10 gt VCERR and WEPRERR flags lt 4 gt All data written
257. l U17446EJ1VOUD CHAPTER 20 INSTRUCTION SET OVERVIEW This chapter lists the instruction set of the 78KOS KB1 For details of the operation and machine language instruction code of each instruction refer to 78K 0S Series Instructions User s Manual U11047E 20 1 Operation 20 1 1 Operand identifiers and description methods Operands are described in Operand column of each instruction in accordance with the description method of the instruction operand identifier refer to the assembler specifications for details When there are two or more description methods select one of them Uppercase letters and the symbols and are key words and are described as they are Each symbol has the following meaning e Immediate data specification e Absolute address specification e Relative address specification e Indirect address specification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the and symbols For operand register identifiers r and rp either function names X A C etc or absolute names names in parentheses in the table below RO R1 R2 etc can be used for description Table 20 1 Operand Identifiers and Description Methods Identifier Description Method r X RO A R1 C R2 B R3 E R4 D R5 L R6 H R7 rp AX RPO BC RP 1 DE RP2 HL RP3 sfr Special function register symbol saddr FE
258. llation is selected see Figures 15 2 to 15 4 Reset by POC and LVI circuit power supply detection is automatically released when Vop gt Vpoc or Voo gt V v after the reset and program execution starts using the CPU clock after referencing the option byte after the option byte is referenced and the clock oscillation stabilization time elapses if crystal ceramic oscillation is selected see CHAPTER 16 POWER ON CLEAR CIRCUIT and CHAPTER 17 LOW VOLTAGE DETECTOR Cautions 1 For an external reset input a low level for 2 ws or more to the RESET pin 2 During reset signal generation the system clock and low speed Ring OSC clock stop oscillating 3 When the RESET pin is used as an input only port pin P34 the 78KO0S KB1 is reset if a low level is input to the RESET pin after reset is released by the POC circuit and before the option byte is referenced again The reset status is retained until a high level is input to the RESET pin 244 Preliminary User s Manual U17446EJ1VOUD CHAPTER 15 RESET FUNCTION Figure 15 1 Block Diagram of Reset Function C Internal bus Reset signal of watchdog timer Reset control flag register RESF WDTRF LVIRF Set Set Clear Clear RESET D gt Reset signal of power on clear circuit Reset signal of low voltage detector Caution The LVI circuit is not reset by the internal reset signal of the LVI circuit Remarks 1 LVIM Low voltage d
259. lock Normal operation 1 Reset period in progress oscillation stops time 2f to 27 Operation stops because option Watchdog overflow i byte is referencedNote 1 CPU clock Internal reset signal Panpin Ny ee nid te te SSO a ea ae aE ae except P130 Port pin P130 Note 2 Notes 1 The operation stop time is 276 ws MIN 544 us TYP and 1 074 ms MAX 2 When reset is effected P130 outputs a low level If P130 is set to output a high level before reset is effected the output signal of P130 can be dummy output as the reset signal to the CPU Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer Remark fx System clock oscillation frequency Preliminary User s Manual U17446EJ1VOUD 247 CHAPTER 15 RESET FUNCTION Figure 15 4 Reset Timing by RESET Input in STOP Mode lt 1 gt With high speed Ring OSC clock or external clock input STOP instruction is executed High speed Ring OSC clock or external clock input Normal i x 1 Stop status Reset period CPU clock heoa oscillation stops oscillation stops _ Normal operation reset processing CPU clock RESET Operation stops because option byte is referenced 1 Internal reset signal i i f e i Delay Delay TYP 100ins TYP 100 ns Port pin Hi Z except P130 Port pin P130 J Note 2 Notes 1 The operation stop time i
260. lock accuracy is 5 Figure 5 8 Timing Chart of Default Start by High Speed Ring OSC Oscillator RESET H Internal reset System clock CPU clock Option byte is read System clock is selected Operation stops Note Operation stop time is 277 ws MIN 544 ws TYP and 1 075 ms MAX 78 Preliminary User s Manual U17446EJ1VOUD CHAPTER 5 CLOCK GENERATORS a The internal reset signal is generated by the power on clear function on power application the option byte is referenced after reset and the system clock is selected b The option byte is referenced and the system clock is selected Then the high speed Ring OSC clock operates as the system clock Figure 5 9 Status Transition of Default Start by High Speed Ring OSC Power application Voo gt 2 1 V 0 1 V Reset by power on clear Reset signal High speed Ring OSC selected by option byte Start with PCC 02H PPCC 02H Clock division ratio variable during CPU operation Interrupt Interrupt HALT instruction STOP instruction Remark PCC Processor clock control register PPCC Preprocessor clock control register 2 Crystal ceramic oscillator If crystal ceramic oscillation is selected by the option byte a clock frequency of 1 to 10 MHz can be selected and the accuracy of processing is improved because the frequency deviation is small as compared with high speed Ring OSC oscillation 8 MHz TYP
261. lock supply was stopped The TxD6 pin also holds the value immediately before clock supply was stopped and outputs it However the operation is not guaranteed after clock supply is resumed Therefore reset the circuit so that POWER6 0 RXE6 0 and TXE6 0 p 179 If data is continuously transmitted the communication timing from the stop bit to the next start bit is extended two operating clocks of the macro However this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit Do not use the continuous transmission function if the interface is incorporated in LIN p 179 O TXB6 Transmit buffer register 6 Do not write data to TXB6 when bit 1 TXBF6 of asynchronous serial interface transmission status register 6 ASIF6 is 1 p 185 Do not refresh write the same value to TXB6 by software during a communication operation when bit 7 POWERS6 and bit 6 TXE6 of asynchronous serial interface operation mode register 6 ASIM6 are 1 or when bit 7 POWERS6 and bit 5 RXE6 of ASIM6 are 1 Preliminary User s Manual U17446EJ1VOUD p 185 375 APPENDIX D LIST OF CAUTIONS Function Serial Soft Classification interface UART6 Chapter 11 Soft Hard 376 Details of Function Cautions 11 18
262. lue is not guaranteed 15 Capture operation lt l gt lt 4 gt lt 6 gt If the T1000 pin is specified as the valid edge of the count clock a capture operation by the capture register specified as the trigger for the T1000 pin is not possible If both the rising and falling edges are selected as the valid edges of the TI000 pin capture is not performed When the CRCOO1 bit value is 1 the TMOO count value is not captured in the CR000 register when a valid edge of the T1010 pin is detected but the input from the TI010 pin can be used as an external interrupt source because INTTM000 is generated at that timing To ensure the reliability of the capture operation the capture trigger requires a pulse longer than two cycles of the count clock selected by prescaler mode register 00 PRMOO The capture operation is performed at the fall of the count clock A interrupt request input INTTMOn0 however occurs at the rise of the next count clock To use two capture registers set the T1000 and T1010 pins 16 Compare operation The capture operation may not be performed for CR OnO set in compare mode even if a capture trigger is input Remark n 0 1 Preliminary User s Manual U17446E 1VOUD 123 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 17 Changing compare register during timer operation 124 lt l gt With the 16 bit timer capture compare register OnO CROnO used as a compare register when changing CROn0 around the
263. m counter PC to branch This function is carried out when the BR AX instruction is executed Illustration Preliminary User s Manual U17446EJ1VOUD 41 CHAPTER 3 CPU ARCHITECTURE 3 4 Operand Address Addressing The following methods addressing are available to specify the register and memory to undergo manipulation during instruction execution 3 4 1 Direct addressing Function The memory indicated by immediate data in an instruction word is directly addressed Operand format addr16 Label or 16 bit immediate data Description example MOV A OFE80H When setting addr16 to FE80H Instruction code 0 0 1 0 1 0 0 1 OP code 1 0 0 0 0 0 0 0 80H 1 1 1 1 1 1 1 0 FEH Illustration OP code addr16 low addr16 high Memory 42 Preliminary User s Manual U17446EJ1VOUD CHAPTER 3 CPU ARCHITECTURE 3 4 2 Short direct addressing Function The memory to be manipulated in the fixed space is directly addressed with the 8 bit data in an instruction word The fixed space where this addressing is applied is the 256 byte space FE20H to FF1FH An internal high speed RAM is mapped at FE20H to FEFFH and the special function registers SFR are mapped at FFOOH to FF1FH The SFR area where short direct addressing is applied FFOOH to FF1FH is a part of the total SFR area In this area ports which are frequently accessed in a program and a compare register of the timer counter are ma
264. mer oscillator Option byte 1 Cannot be stopped 0 Can be stopped Low speed Ring OSC mode register LSRCM S Internal bus 6 Note Select the high speed Ring OSC oscillator crystal ceramic oscillator or external clock input as the system clock source by using the option byte Preliminary User s Manual U17446EJ1VOUD 71 CHAPTER 5 CLOCK GENERATORS 5 3 Registers Controlling Clock Generators 72 The clock generators are controlled by the following four registers e Processor clock control register PCC e Preprocessor clock control register PPCC e Low speed Ring OSC mode register LSRCM e Oscillation stabilization time select register OSTS 1 Processor clock control register PCC and preprocessor clock control register PPCC These registers are used to specify the division ratio of the system clock PCC and PPCC are set by using a 1 bit or 8 bit memory manipulation instruction Generation of reset signal sets PCC and PPCC to 02H Figure 5 2 Format of Processor Clock Control Register PCC Address FFFBH After reset 02H R W Symbol PCC 7 6 5 4 3 2 1 0 fe se 2 ore ae ae eee aes Caution Bits 7 to 2 and 0 must be set to 0 Figure 5 3 Format of Preprocessor Clock Control Register PPCC Address FFF3H After reset 02H R W Symbol PPCC 7 6 5 4 3 2 1 0 Selection of CPU clock fcru fx fx 2 Note 1 fx 2 fx 22 Note 2 fx 2 Note 1 fx 24 Note 2
265. mmunication is not executed and can enable a reduction in the power consumption For details see 11 4 1 Operation stop mode 2 Asynchronous serial interface UART mode This mode supports the LIN Local Interconnect Network bus The functions of this mode are outlined below For details see 11 4 2 Asynchronous serial interface UART mode and 11 4 3 Dedicated baud rate generator e Two pin configuration TxD6 Transmit data output pin RxD6 Receive data input pin e Data length of communication data can be selected from 7 or 8 bits e Dedicated internal 8 bit baud rate generator allowing any baud rate to be set e Transmission and reception can be performed independently e Twelve operating clock inputs selectable e MSB or LSB first communication selectable e Inverted transmission operation e Synchronous break field transmission from 13 to 20 bits e More than 11 bits can be identified for synchronous break field reception SBF reception flag provided Cautions 1 The TxD6 output inversion function inverts only the transmission side and not the reception side To use this function the reception side must be ready for reception of inverted data 2 If clock supply to serial interface UART6 is not stopped e g in the HALT mode normal operation continues If clock supply to serial interface UART6 is stopped e g in the STOP mode each register stops operating and holds the value immediately before clock supply was stopped The TxD6 pin al
266. mode control register FLPMC 283 Flash protect command register PFCMD 285 360 Preliminary User s Manual U17446EJ1VOUD APPENDIX C REGISTER INDEX Flash status register PFS 286 Flash write buffer register FLW 289 I Input switch control register ISC 194 Interrupt mask flag register 0 MKO 226 Interrupt mask flag register 1 MK1 226 Interrupt request flag register 0 IFO 225 Interrupt request flag register 1 IF1 225 L Low voltage detect register LVIM 257 Low voltage detection level select register LVIS 258 Low speed Ring OSC mode register LSRCM 73 M Multiplication data register A MRAO 217 Multiplication data register B MRBO 217 Multiplier control register 0 MULCO 219 0 Oscillation stabilization time select register OSTS 74 236 P Port mode control register 2 PMC2 66 168 Port mode register 0 PMO 64 Port mode register 2 PM2 64 168 Port mode register 3 PM3 64 95 Port mode register 4 PM4 64 138 194 Port mode register 12 PM12 64 Port register 0 PO 65 Port register 2 P2 65 Port register 3 P3 65 Port register 4 P4 65 Port register 12 P12 65 Port register 13 P13 65 Preprocessor clock control register PPCC 72 Prescaler mode register 00 PRMOO 94 Processor clock control register PCC 72 Pull up resistor option register 0 PUO
267. mory programming mode To rewrite the contents of the flash memory by using the dedicated flash programmer set the 78KOS KB1 in the flash memory programming mode When the 78KOS KB1 is connected to the flash programmer and a communication command is transmitted to the microcontroller the microcontroller is set in the flash memory programming mode Change the mode by using a jumper when writing the flash memory on board 19 7 3 Communication commands The 78K0S KB1 communicates with the dedicated flash programmer by using commands The signals sent from the flash programmer to the 78KOS KB1 are called commands and the commands sent from the 78KO0S KB1 to the dedicated flash programmer are called response commands Figure 19 9 Communication Commands FlashPro4 NEC PG FP4 Flash Prod Command PG FPL2 MODE Tm NEC F Response command mE PG FPL2 o o Power Status 78K0S KB1 Dedicated flash programmer The flash memory control commands of the 78KOS KB1 are listed in the table below All these commands are issued from the programmer and the 78KOS KB1 perform processing corresponding to the respective commands Table 19 6 Flash Memory Control Commands Classification Command Name Function Batch erase chip erase command Erases the contents of the entire memory Block erase command Erases the contents of the memory of the specified block Write
268. mpling time and conversion time do not include the clock p 161 S 9 Converter and conversion frequency error Select the conversion time taking the clock frequency error S time into consideration O ADM A D The above sampling time and conversion time do not include the clock p 166 converter mode frequency error Select the conversion time taking the clock frequency error register into consideration If a bit other than ADCS of ADM is manipulated while A D conversion is p 166 stopped ADCS 0 and then A D conversion is started execute two NOP instructions or an instruction equivalent to two machine cycles and set ADCS to 1 A D conversion must be stopped ADCS 0 before rewriting bits FRO to FR2 p 166 Be sure to clear bits 6 2 and 1 to 0 p 166 ADS Analog Be sure to clear bits 2 to 7 of ADS to 0 p 167 input channel specification register ADCR 10 bit A D When writing to the A D converter mode register ADM and analog input p 167 L conversion result channel specification register ADS the contents of ADCR may become register undefined Read the conversion result following conversion completion before writing to ADM and ADS Using timing other than the above may cause an incorrect conversion result to be read PMC2 Port When PMC20 to PMC23 are set to 1 the P20 ANIO to P23 ANI3 pins cannot p 168 mode control be used as port pins register 2 A D converter Make sure the period of lt 1 gt to lt 4 gt is 1 us or more
269. n into consideration when setting the 196 port mode register and port register Preliminary User s Manual U17446EJ1VOUD CHAPTER 11 SERIAL INTERFACE UART6 The relationship between the register settings and pins is shown below Table 11 2 Relationship Between Register Settings and Pins UART6 Pin Function Operation TxD6 INTP1 P43 RxD6 P44 Stop Reception Transmission Transmission reception Note Can be set as port function Remark x don t care POWERE Bit 7 of asynchronous serial interface operation mode register 6 ASIM6 TXE6 Bit 6 of ASIM6 RXE6 Bit 5 of ASIM6 PM4x Port mode register P4x Port output latch Preliminary User s Manual U17446EJ1VOUD 197 CHAPTER 11 SERIAL INTERFACE UART6 2 Communication operation a Format and waveform example of normal transmit receive data Figures 11 13 and 11 14 show the format and waveform example of the normal transmit receive data Figure 11 13 Format of Normal UART Transmit Receive Data 1 LSB first transmission reception 1 data frame SDBOOROOR ES Character bits 2 MSB first transmission reception 1 data frame BEER Oc ie Character bits One data frame consists of the following bits e Start bit 1 bit e Character bits 7 or 8 bits e Parity bit Even parity odd parity O parity or no parity e Stop bit 1 or 2 bits The character bit length parity and stop
270. n is stabilized The wait time is selected by the option byte For details refer to CHAPTER 18 OPTION BYTE Preliminary User s Manual U17446EJ1VOUD 3 CHAPTER 5 CLOCK GENERATORS Figure 5 11 Status Transition of Default Start by Crystal Ceramic Oscillation Power application Voo gt 2 1 V 0 1 V Reset by power on clear Reset signal Crystal ceramic oscillation selected by option byte Wait for clock oscillation stabilization Start with PCC 02H PPCC 02H Clock division ratio variable during CPU operation Interrupt HALT Interrupt instruction STOP instruction Remark PCC Processor clock control register PPCC Preprocessor clock control register External clock input circuit If external clock input is selected by the option byte the following is possible e High speed operation The accuracy of processing is improved as compared with high speed Ring OSC oscillation 8 MHz TYP because an oscillation frequency of 1 to 10 MHz can be selected and an external clock with a small frequency deviation can be supplied e Improvement of expandability If the external clock input circuit is selected as the oscillator the X2 pin can be used as an I O port pin For details refer to CHAPTER 4 PORT FUNCTIONS Figures 5 12 and 5 13 show the timing chart and status transition diagram of default start by external clock input Preliminary User s Manual U17446EJ1VOUD 81 CHAPTER 5 C
271. n register 4 Preliminary User s Manual U17446EJ1VOUD 57 CHAPTER 4 PORT FUNCTIONS Figure 4 9 Block Diagram of P41 and P44 Voo PU41 PU44 P ch Alternate function 2o pR zZ 5 O 3 3 D o P4 A Output latch P41 INTP3 P41 P44 O paaipxoe WRpem PM4 a PM41 PM44 J PU4 Pull up resistor option register 4 P4 Port register 4 PM4 Port mode register 4 RD Read signal WRxx Write signal Preliminary User s Manual U17446EJ1VOUD MA CHAPTER 4 PORT FUNCTIONS Figure 4 10 Block Diagram of P42 WRpPu Vopn DHF A A Selector 4 J R P42 TOH1 RD no 3B T Bg D 1 g WRpPorT P4 A Output latch P42 WRPm PM4 PM42 Alternate function ENZ PU4 Pull up resistor option register 4 P4 Port register 4 PM4 Port mode register 4 RD Read signal WRxx Write signal Preliminary User s Manual U17446EJ1VOUD 59 CHAPTER 4 PORT FUNCTIONS Figure 4 11 Block Diagram of P43 Voo De Alternate function RD mal lt lt 1 8 o 3 e ba a WRrort P4 2 ay Output latch i P43 1 P43 TxD6 INTP1 WRem PM4 Alternate function aw PU4 Pull up resistor option register 4 P4 Port register 4 PM4 Port mode register 4 RD Read signal WRxx Write signal 4 2 5 Port12 Port 12 is a 4 b
272. nchronously reset the reception circuit Enable reception PS61 PS60 Transmission operation Reception operation Parity bit not output Reception without parity Note Output 0 parity Reception as 0 parity Output odd parity Judge as odd parity Output even parity Judge as even parity Specification of character length of transmit receive data 0 Character length of data 7 bits 1 Character length of data 8 bits Specification of number of stop bits of transmit data 0 Number of stop bits 1 1 Number of stop bits 2 ISRM6 Enabling disabling occurrence of reception completion interrupt in case of error INTSRE6 occurs in case of error at this time INTSR6 does not occur INTSR6 occurs in case of error at this time INTSRE6 does not occur Note If reception as 0 parity is selected the parity is not judged Therefore bit 2 PE6 of asynchronous serial interface reception error status register 6 ASIS6 is not set and the error interrupt does not occur Cautions 1 At startup set POWER6 to 1 and then set TXE6 to 1 To stop the operation clear TXE6 to 0 and then clear POWER6 to 0 At startup set POWER6 to 1 and then set RXE6 to 1 To stop the operation clear RXE6 to 0 and then clear POWER6 to 0 Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RxD6 pin If POWERS is set to 1 and RXEE6 is set to 1 while a low level is input recept
273. nction is used First clear bit 7 ADCS and bit O ADCE of the A D converter mode register ADM to 0 to stop the A D conversion operation and then execute the HALT or STOP instruction STOP mode If the low speed Ring OSC oscillator is operating before the STOP mode is set oscillation of the low speed Ring OSC clock cannot be stopped in the STOP mode refer to Table 14 1 OSTS Oscillation stabilization time select register To set and then release the STOP mode set the oscillation stabilization time as follows Expected oscillation stabilization time of resonator lt Oscillation stabilization time set by OSTS The wait time after the STOP mode is released does not include the time from the release of the STOP mode to the start of clock oscillation a in the figure below regardless of whether STOP mode was released by reset signal generation or interrupt generation The oscillation stabilization time that elapses on power application or after release of reset is selected by the option byte For details refer to CHAPTER 18 OPTION BYTE Settings and operating statuses in HALT mode Because an interrupt request signal is used to clear the standby mode if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset the standby mode is immediately cleared if set Settings and operating statuses in STOP mode
274. nd then starts counting from 0 again If the new value of CROn0 is less than the old value therefore the timer must be reset to be restarted after the value of CROn0 is changed Preliminary User s Manual U17446EJ 1VOUD CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 4 5 6 7 8 9 Capture register data retention The values of 16 bit timer capture compare register OnO CROn0 after 16 bit timer event counter 00 has stopped are not guaranteed Remark n 0 1 Setting of 16 bit timer mode control register 00 TMC00 The timer operation must be stopped before writing to bits other than the OVF flag Setting of capture compare control register 00 CRC00 The timer operation must be stopped before setting CRCOO Setting of 16 bit timer output control register 00 TOC00 lt l gt Timer operation must be stopped before setting other than OSPTOO lt 2 gt If LVS00 and LVROO are read 0 is read lt 3 gt OSPTO0O0 is automatically cleared after data is set so 0 is read lt 4 gt Do notsetOSPTO00 to 1 other than in one shot pulse output mode lt 5 gt A write interval of two cycles or more of the count clock selected by prescaler mode register 00 PRMOO is required to write to OSPTOO successively Setting of prescaler mode register 00 PRM00 Always set data to PRMOO after stopping the timer operation Valid edge setting Set the valid edge of the TI000 pin with bits 4 and 5 ES000 and ESO10 of prescaler mod
275. ng for low voltage detection Check that supply voltage Vop gt detection voltage Vivi in the servicing routine of the LVI interrupt by using bit 0 LVIF of the low voltage detection register LVIM Clear bit 1 LVIIF of interrupt request flag register 0 IFO to 0 and enable interrupts El In a system where the supply voltage fluctuation period is long in the vicinity of the LVI detection voltage wait for the supply voltage fluctuation period check that supply voltage Voo gt detection voltage Vivi using the LVIF flag Clear the LVIIF flag to 0 and then enable interrupts E1 Note For low voltage detection processing the CPU clock speed is switched to slow speed and the A D converter is stopped etc 262 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 17 LOW VOLTAGE DETECTOR Figure 17 6 Example of Software Processing After Release of Reset 1 2 e If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage The reset source power on clear WDT or LVI can be identified by the RESF register Start timer 8 bit timer H1 can operate with the low speed Ring OSC clock set to 50 ms Source fri 480 kHz MAX 2 x compare value 200 53 ms frL low speed Ring OSC clock oscillation frequency Note 1 lt 50 ms has passed TMIFH1 1 TMIFH1 1 Interrupt request is generated C Yes TMIFH1 0 TMIFH1 0 Interrupt request is disabled
276. ng OSC mode register Notes 1 Only P34 is an input only port 2 A 16 bit access is possible only by the short direct addressing 3 Retained only after a reset by LVI 4 Varies depending on the reset cause Preliminary User s Manual U17446EJ1VOUD 37 CHAPTER 3 CPU ARCHITECTURE Table 3 3 Special Function Registers 2 3 Address Special Function Register SFR Name Number of Bits Manipulated After Reset Simultaneously 1 Bit 8 Bits 16 Bits a ais 16 bit timer mode control register 00 TMCOO Prescaler mode register 00 PRMOO Capture compare control register 00 CRCOO 16 bit timer output control register 00 TOCOO 8 bit timer H mode register 1 TMHMD1 A D converter mode register ADM Analog input channel specify register ADS Port mode control register 2 PMC2 Input switching control register ISC a a a a E E e a a E l N 2 Asynchronous serial interface operation mode ASIM6 register 6 Reception buffer register 6 RXB6 Asynchronous serial interface reception error ASIS6 status register 6 Transmission buffer register 6 TXB6 Asynchronous serial interface transmission ASIF6 status register 6 Clock selection register 6 CKSR6 FFH 16H Undefined 00H Undefined 00H Undefined Baud rate generator control register 6 BRGC6 Asynchronous serial interface control register 6 ASICL6 Flash protect c
277. ng of Option Byte OFFFH 1FFFH Flash memory 4096 8192 x 8 bits 0080H Option byte 0000H Preliminary User s Manual U17446EJ 1VOUD 265 266 CHAPTER 18 OPTION BYTE Figure 18 2 Format of Option Byte 1 2 Address 0080H 7 6 5 4 3 2 1 0 DEFOSTS1 DEFOSTSO 1 RMCE OSCSEL1 OSCSELO RINGOSC RINGOSC Low speed Ring OSC clock oscillation 1 Cannot be stopped oscillation does not stop even if 1 is written to the LSRSTOP bit 0 Can be stopped by software oscillation stops when 1 is written to the LSRSTOP bit Cautions 1 If it is selected that low speed Ring OSC clock oscillation cannot be stopped the count clock to the watchdog timer WDT is fixed to low speed Ring OSC 2 If it is selected that low speed Ring OSC can be stopped by software supply of the count clock to WDT is stopped in the HALT STOP mode regardless of the setting of bit 0 LSRSTOP of the low speed Ring OSC mode register LSRCM Similarly clock supply is also stopped when a clock other than the low speed Ring OSC is selected as a count clock to WDT If low speed Ring OSC is selected as the count clock to 8 bit timer H1 however the count clock is supplied in the HALT STOP mode while low speed Ring OSC operates LSRSTOP 0 OSCSEL1 OSCSELO Selection of system clock source Crystal ceramic oscillation clock External clock input High speed Ring OSC clock Caution Because the X1 and X2 pins are also used as the P121 and
278. ng overrun error If POWERS6 0 and RXE6 0 or if ASIS6 register is read If receive data is set to the RXB register and the next reception operation is completed before the data is read Cautions 1 The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of asynchronous serial interface operation mode register 6 ASIM6 2 The first bit of the receive data is checked as the stop bit regardless of the number of stop bits 3 If an overrun error occurs the next receive data is not written to receive buffer register 6 RXB6 but discarded 188 Preliminary User s Manual U17446EJ1VOUD CHAPTER 11 SERIAL INTERFACE UART6 3 Asynchronous serial interface transmission status register 6 ASIF6 This register indicates the status of transmission by serial interface UART6 It includes two status flag bits TXBF6 and TXSF6 Transmission can be continued without disruption even during an interrupt period by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register This register is read only by an 8 bit memory manipulation instruction Reset signal generation clears this register to OOH if bit 7 POWER6 and bit 6 TXE6 of ASIM6 0 Figure 11 7 Format of Asynchronous Serial Interface Transmission Status Register 6 ASIF6 Address FF95H After reset OOH R Symbol 7 6 5 4 3 2 1 0 TXBF6 Transmit buffer data flag If POWERG6 0 or TXE
279. nput to the TI000 pin and the T1010 pin When the edge specified by bits 4 and 5 ES000 and ES010 of prescaler mode register 00 PRMOO is input to the T1000 pin the value of TMOO is taken into 16 bit timer capture compare register 010 CRO10 and an interrupt request signal INTTMO010 is set Also when the edge specified by bits 6 and 7 ES100 and ES110 of PRMOO is input to the T1010 pin the value of TMOO is taken into 16 bit timer capture compare register 000 CR 000 and an interrupt request signal INTTM00O0 is set Specify both the rising and falling edges as the edges of the TI000 and TI010 pins by using bits 4 and 5 ES000 and ES010 and bits 6 and 7 ES100 and ES110 of PRMOO Sampling is performed using the count clock cycle selected by prescaler mode register 00 PRMOO and a capture operation is only performed when a valid level of the T1000 or T1010 pin is detected twice thus eliminating noise with a short pulse width Figure 6 21 Control Register Settings for Measurement of Two Pulse Widths with Free Running Counter a 16 bit timer mode control register 00 TMCO00 4 TMC003 TMC002 TMC001 OVFOO TwCo0 Cee Teleys solo b Capture compare control register 00 CRC00 Free running mode 7 6 5 4 3 CRC002 CRC001 CRC000 CR0O00 used as capture register Captures valid edge of TI010 pin to CROOO CR010 used as capture register c Prescaler mode register 00 PRM00 ES110 ES100 ES010 ES000 3 2 PRM001 PRM000 w
280. nsmit shift register 6 Asynchronous serial interface transmission status register 6 Bit 1 of ASIF6 Bit 0 of ASIF6 Bit 7 of asynchronous serial interface operation mode register ASIM6 Bit 6 of asynchronous serial interface operation mode register ASIM6 Preliminary User s Manual U17446EJ1VOUD 205 206 RxD6 input Start CHAPTER 11 SERIAL INTERFACE UART6 e Normal reception Reception is enabled and the RxD6 pin input is sampled when bit 7 POWER6 of asynchronous serial interface operation mode register 6 ASIM6 is set to 1 and then bit 5 RXE6 of ASIM6 is set to 1 The 8 bit counter of the baud rate generator starts counting when the falling edge of the RxD6 pin input is detected When the set value of baud rate generator control register 6 BRGC6 has been counted the RxD6 pin input is sampled again V in Figure 11 19 If the RxD6 pin is low level at this time it is recognized as a start bit When the start bit is detected reception is started and serial data is sequentially stored in the receive shift register RXS6 at the set baud rate When the stop bit has been received the reception completion interrupt INTSR6 is generated and the data of RXS6 is written to receive buffer register 6 RXB6 If an overrun error OVE6 occurs however the receive data is not written to RXB6 Even if a parity error PE6 occurs while reception is in progress reception continues to the reception position of the stop bit and an
281. o lt 1 gt to lt 6 gt in the description of when starting operation in 17 4 1 When used as reset 260 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 17 LOW VOLTAGE DETECTOR 2 When used as interrupt e When starting operation lt l gt Mask the LVI interrupt LVIMK 1 lt 2 gt Set the detection voltage using bits 3 to 0 LVIS3 to LVISO of the low voltage detection level select register LVIS lt 3 gt Setbit 7 LVION of LVIM to 1 enables LVI operation lt 4 gt Use software to instigate a wait of at least 0 2 ms lt 5 gt Wait until supply voltage Voo gt detection voltage V v at bit 0 LVIF of LVIM is confirmed lt 6 gt Clear the interrupt request flag of LVI LVIIF to 0 lt 7 gt Release the interrupt mask flag of LVI LVIMK lt 8 gt Execute the El instruction when vector interrupts are used Figure 17 5 shows the timing of generating the interrupt signal of the low voltage detector Numbers lt 1 gt to lt 7 gt in this figure correspond to lt 1 gt to lt 7 gt above e When stopping operation Either of the following procedures must be executed e When using 8 bit memory manipulation instruction Write 00H to LVIM e When using 1 bit memory manipulation instruction Clear LVION to 0 Figure 17 5 Timing of Low Voltage Detector Interrupt Signal Generation Supply voltage VoD LVI detection voltage Vivi POC detection voltage Vpoc 2 7V Time LVIMK flag set by softwar
282. o and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC Electronics products is Standard unless otherwise expressly specified in NEC Electronics data sheets or data books etc If customers wish to use NEC Electronics products in applications not intended by NEC Electronics they must contact an NEC Electronics sales representative in advance to determine NEC Electronics willingness to support a given application Note 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries 2 NEC Electronics products means any product developed or manufactured by or for NEC Electronics as defined above MSD 02 11 1 4 Preliminary User s Manual U17446EJ1VOUD Regional Information Some information contained in this document may vary from country to country Before using any NEC Electronics product in your application please contact the NEC Electronics office in your country to obtain a list of
283. o self programming mode is shown below DI ModeOnLoop MOV MOV MOV MOV MOV MOV CMP BNZ MKO 11111111B Masks all interrupts MK1 11111111B PFS 00H PFCMD 0A5H PFCMD register control FLPMC 01H FLPMC register control sets value FLPMC 0FEH FLPMC register control inverts set value FLPMC 01H Sets self programming mode with FLPMC register control sets value A PFS A 00H SModeOnLoop Checks completion of write to specific registers Repeats the same processing when an error occurs Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY 293 CHAPTER 19 FLASH MEMORY 19 8 5 Example of shifting self programming mode to normal mode The operating mode must be returned from self programming mode to normal mode after performing self programming An example of shifting to normal mode is explained below lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt Clear the flash status register PFS Set normal mode using a specific sequence e Write the specific value ASH to PFCMD e Write 00H to FLPMC writing in this step is invalid e Write OFFH inverted value of OOH to FLPMC writing in this step is invalid e Write OOH to FLPMC writing in this step is valid Check the execution result of the specific sequence using bit O0 FRPRERR of PFS Abnormal gt lt 1 gt normal gt lt 4 gt Enable interrupt servicing by executing the El instruct
284. o set again even if setting the same value to the CMP11 register g PWM output In PWM output mode three operation clocks signal selected using the CKS12 p 143 O T to CKS10 bits of the TMHMD1 register are required to transfer the CMP11 register value after rewriting the register 5 Be sure to set the CMP11 register when starting the timer count operation p 143 R TMHE1 1 after the timer count operation was stopped TMHE1 0 be sure to set again even if setting the same value to the CMP11 register Make sure that the CMP11 register setting value M and CMP01 register p 144 setting value N are within the following range OOH lt CMP11 M lt CMP01 N lt FFH Watchdog WDTM Set bits 7 6 and 5 to 0 1 and 1 respectively when low speed Ring OSC p 152 O 2 a timer Watchdog timer cannot be stopped is selected by the option byte other values are ignored Oo 5 mode register After reset is released WDTM can be written only once by an 8 bit memory p 152 manipulation instruction If writing is attempted a second time an internal reset signal is generated WDTM cannot be set by a 1 bit memory manipulation instruction p 152 When using the flash memory self programming by self writing set the p 152 overflow time for the watchdog timer so that enough everflow time is secured Example 1 byte writing 200 ws MIN 1 block deletion 10 ms MIN If a value other than ACH is written to WDTE an internal reset signal is p
285. o transmit data continuously write the first transmit data first byte to the p 189 Asynchronous TXB6 register Be sure to check that the TXBF6 flag is 0 If so write the serial interface next transmit data second byte to the TXB6 register If data is written to the transmission status TXB6 register while the TXBF6 flag is 1 the transmit data cannot be register 6 guaranteed To initialize the transmission unit upon completion of continuous transmission p 189 be sure to check that the TXSF6 flag is O after generation of the transmission completion interrupt and then execute initialization If initialization is executed while the TXSF6 flag is 1 the transmit data cannot be guaranteed CKSR6 Clock Make sure POWER6 0 when rewriting TPS63 to TPS60 p 190 selection register 6 BRGC6 Baud rate Make sure that bit 6 TXE6 and bit 5 RXE6 of the ASIM6 register 0 when p 191 generator control rewriting the MDL67 to MDL60 bits register 6 The baud rate is the output clock of the 8 bit counter divided by 2 p 191 O ASICL6 ASICL6 can be refreshed the same value is written by software during a p 192 Asynchronous communication operation when bit 7 POWER86 and bit 6 TXE6 of ASIM6 serial interface 1 or bit 7 POWER8 and bit 5 RXE6 of ASIM6 1 However if the SBRT6 control register 6 1 and SBTT 1 are set in the refresh operation during the SBF reception SBRF6 1 or SBF transmission between the SBTT6 set
286. ock erase Figure 19 22 lt 1 gt to lt 11 gt lt lt 2 gt Check execution resu Abnormal VCERR and WEPRERR flags Normal lt 3 gt Execute block blank check Figure 19 23 J lt 1 gt to lt 11 gt Abnormal VCERR and WEPRERR flags Normal Figure 19 21 lt 1 gt to lt 5 gt lt 4 gt Shift to normal mode Normal termination Abnormal terminationNote Note Perform processing to shift to normal mode in order to return to normal processing Remark lt 1 gt to lt 4 gt in Figure 19 26 correspond to lt 1 gt to lt 4 gt in 19 8 10 1 above Preliminary User s Manual U17446EJ1VOUD 309 CHAPTER 19 FLASH MEMORY An example of a program list when the command execution time from erasure to black check should be minimized in self programming mode is shown below START MOV MKO 11111111B Masks all interrupts MOV MK1 11111111B DI ModeOnLoop MOV PFS 00H MOV PFCMD 0A5H PFCMD register control MOV FLPMC 01H FLPMC register control sets value MOV FLPMC OFEH FLPMC register control inverts set value MOV FLPMC 01H Sets self programming mode with FLPMC register control sets value MOV A PFS CMP A 00H BNZ ModeOnLoop Checks completion of write to specific registers Repeats the same processing when an error occurs FlashBlockErase MOV FLCMD 03H Sets flash control command block erase MOV FLAPH 07H Sets number of block to be erased block 7 is speci
287. of AVrer or higher and AVss or lower even in the range of absolute maximum ratings is input to an analog input channel the converted value of that channel becomes undefined In addition the converted values of the other channels may also be affected Conflicting operations lt 1 gt Conflict between A D conversion result register ADCR ADCRH write and ADCR ADCRH read by instruction upon the end of conversion ADCR ADCRH read has priority After the read operation the new conversion result is written to ADCR ADCRH lt 2 gt Conflict between ADCR ADCRH write and A D converter mode register ADM write or analog input channel specification register ADS write upon the end of conversion ADM or ADS write has priority ADCR ADCRH write is not performed nor is the conversion end interrupt signal INTAD generated Noise countermeasures To maintain the 10 bit resolution attention must be paid to noise input to the AVrer pin and pins ANIO to ANI3 lt 1 gt Connect a capacitor with a low equivalent resistance and a high frequency response to the power supply lt 2 gt Because the effect increases in proportion to the output impedance of the analog input source it is recommended that a capacitor be connected externally as shown in Figure 10 19 to reduce noise lt 3 gt Do not switch the A D conversion function of the ANIO to ANI3 pins to their alternate functions during conversion lt 4 gt The conversion accuracy can be improved by s
288. of reset signal sets port 0 to the input mode Figure 4 2 shows the block diagram of port 0 Figure 4 2 Block Diagram of P00 to P03 Voo MM WRru PUO D PUOO to PU03 P ch RD 5 a 5 a E hae lt 8 o o D WRpeort Output latch POO to P03 POO to P03 WRem PMO0 to PMO3 PUO Pull up resistor option register 0 PO Port register 0 PMO Port mode register 0 RD Read signal WRxx Write signal 52 Preliminary User s Manual U17446EJ1VOUD CHAPTER 4 PORT FUNCTIONS 4 2 2 Port2 Port 2 is a 4 bit I O port with an output latch Each bit of this port can be set to the input or output mode by using port mode register 2 PM2 When the P20 to P23 pins are used as an input port an on chip pull up resistor can be connected in 1 bit units by using pull up resistor option register 2 PU2 This port is also used as the analog input pins of the internal A D converter Generation of reset signal sets port 2 to the input mode Figure 4 2 shows the block diagram of port 2 Figure 4 3 Block Diagram of P20 to P23 Vpop WReu PU2 fas PU20 to PU23 P ch WRemc PMC2 aa PMC20 to PMC23 RD Po 23 Tal i T 2 E _ D WRPorT P2 oe re 4 O P20 ANI0 to P23 ANI3 A D converter PU2 Pull up resistor option register 2 P2 Port register 2 PM2 Port mode register 2 PMC2 Port mode control registe
289. og timer operation when low speed Ring OSC cannot be stopped is selected by option byte The operation clock of watchdog timer is fixed to low speed Ring OSC After reset is released operation is started at the maximum cycle bits 2 1 and 0 WDCS2 WDCS1 WDCS0O of the watchdog timer mode register WDTM 1 1 1 The watchdog timer operation cannot be stopped The following shows the watchdog timer operation after reset release 1 The status after reset release is as follows e Operation clock Low speed Ring OSC clock e Cycle 2 fre 546 13 ms operation with fri 480 kHz MAX e Counting starts 2 The following should be set in the watchdog timer mode register WDTM by an 8 bit memory manipulation instructions e Cycle Set using bits 2 to 0 WDCS2 to WDCS0 3 After the above procedures are executed writing ACH to WDTE clears the count to 0 enabling recounting Notes 1 The operation clock low speed Ring OSC clock cannot be changed If any value is written to bits 3 and 4 WDCS3 WDCS4 of WDTM it is ignored 2 As soon as WDTM is written the counter of the watchdog timer is cleared Caution In this mode operation of the watchdog timer cannot be stopped even during STOP instruction execution For 8 bit timer H1 TMH1 a division of the low speed Ring OSC clock can be selected as the count source so clear the watchdog timer using the interrupt request of TMH1 before the watchdog timer overflows after STOP instruction
290. ogram memory 8 192 x 8 bits i 5 P Oplionibyte area id CALLT table area 0040H 003FH Program area 0022H 0021H Vector table area 1 y 0000H 0000H Remark The option byte and protect byte are 1 byte each Preliminary User s Manual U17446EJ1VOUD CHAPTER 3 CPU ARCHITECTURE 3 1 1 Internal program memory space The internal program memory space stores programs and table data This space is usually addressed by the program counter PC The 78K0S KB1 provides the following internal ROMs or flash memory containing the following capacities Table 3 1 Internal ROM Capacity Part Number Internal ROM Structure Capacity UPD78F9232 Flash memory 4 096 x 8 bits UPD78F9234 8 192 x 8 bits The following areas are allocated to the internal program memory space 1 Vector table area The 34 byte area of addresses 0000H to 0021H is reserved as a vector table area This area stores program start addresses to be used when branching by RESET input or interrupt request generation Of a 16 bit address the lower 8 bits are stored in an even address and the higher 8 bits are stored in an odd address Table 3 2 Vector Table Vector Table Address Interrupt Request Vector Table Address Interrupt Request Reset input INTAD INTLVI INTP2 INTPO INTP3 INP1 INTTM80 INTTMH1 INTSRE6 INTTMO00 INTSR6 INTTMO010 INTST6 Caution No interrupt sources correspond to the vector table addre
291. ointers H and L Be sure to clear bits 4 to 7 of FLAPH and FLAPHC to 0 before executing the self programming command If the value of these bits is 1 when executing the self programming command FLAPHC and FLAPLC Flash address pointer H compare register and flash address pointer L compare register Be sure to clear bits 4 to 7 of FLAPH and FLAPHC to 0 before executing the self programming command If the value of these bits is 1 when executing the self programming command Set the number of the block subject to a block erase write verify or blank check same value as FLAPH to FLAPHC Clear FLAPLC to 00H when a block erase is performed and FFH when a blank check is performed Preliminary User s Manual U17446EJ1VOUD APPENDIX D LIST OF CAUTIONS Chapter 19 Soft Classification Function Details of Function Shifting to self programming mode Shifting to normal mode Cautions Be sure to perform the series of operations described above using the user program at an address where data is not erased nor written 18 18 Byte write operation If a write results in failure erase the block once and write to it again A N i oO Ear Qa oO lt O Electrical specifica tions Absolute maximum ratings Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That i
292. ommand register PFCMD Flash status register PFS Flash programming mode control register FLPMC Flash programming command register FLCMD Flash address pointer L FLAPL Flash address pointer H FLAPH Flash address pointer H compare register FLAPHC Flash address pointer L compare register FLAPLC Flash write buffer register FLW 8 bit timer mode control register 80 TMC80 Undefined 00H Undefined 8 bit compare register 80 CR80 8 bit timer counter 80 TM80 Multiplication data register A MRAO Multiplication data register B MRBO Multiplier control register 0 MULCO Interrupt request flag register 0 IFO Interrupt request flag register 1 IF1 Interrupt mask flag register 0 MKO Interrupt mask flag register 1 MK1 a lt lt lt a a a a a E E a a a a a a a External interrupt mode register 0 INTMO 38 Preliminary User s Manual U17446EJ1VOUD CHAPTER 3 CPU ARCHITECTURE Table 3 3 Special Function Registers 3 3 Address Special Function Register SFR Name Number of Bits Manipulated After Reset Simultaneously 1 Bit 8 Bits 16 Bits External interrupt mode register 1 00H Preprocessor clock control register 02H Oscillation stabilization time selection register Undefined Processor clock control register 02H Note The oscillation stabilization time that el
293. ommunication is possible when the baud rate error in the slave is 15 or less Figures 11 1 and 11 2 outline the transmission and reception operations of LIN LIN bus TX6 Figure 11 1 LIN Transmission Operation Wakeup Synchronous Synchronous Identifier Data field Data field Checksum signal frame break field field field field 13 bitNe SBF 55H Data Data Data Data 8 bitsNote 1 transmission transmission transmissiontransmissiontransmissiontransmission Note 3 aii INTST6 Notes 1 2 Remark 180 The wakeup signal frame is substituted by 80H transmission in the 8 bit mode The synchronous break field is output by hardware The output width is equal to the bit length set by bits 4 to 2 SBL62 to SBL60 of asynchronous serial interface control register 6 ASICL6 see 11 4 2 2 h SBF transmission INTST6 is output on completion of each transmission It is also output when SBF is transmitted The interval between each field is controlled by software Preliminary User s Manual U17446EJ1VOUD CHAPTER 11 SERIAL INTERFACE UART6 Figure 11 2 LIN Reception Operation Wakeup Synchronous Synchronous Identifier Data field Data field Checksum signal frame break field field field field ie Se I e bus SF ID Data Data Data 13 bitsNote2 reception reception reception reception receptionNete gt G eel ee re RX6 reception Note 3 Reception interrupt INTSR6 Note 4 Edge de
294. on the program is executed after branching to the reset vector address Figure 14 3 HALT Mode Release by Reset Signal Generation 1 When CPU clock is high speed Ring OSC clock or external input clock HALT instruction Reset signal t Operation Reset Operation CPU status mode HALT mode period stops Operation mode System clock Oscillates Oscillation stops Oscillates oscillation Note Operation is stopped 277 ws MIN 544 ws TYP 1 075 ms MAX because the option byte is referenced 2 When CPU clock is crystal ceramic oscillation clock HALT instruction Reset signal i _s E e Operation Reset Operation Oscillation Operation CPU status mode HALT mode period stops stabilization waits mode System clock Oscillates Oscillation stops Oscillates oscillation Oscillation stabilization time 2 fx to 2 7 fx Note Operation is stopped 276 ws MIN 544 ws TYP 1 074 ms MAX because the option byte is referenced Remark fx System clock oscillation frequency Table 14 3 Operation in Response to Interrupt Request in HALT Mode Release Source Operation Maskable interrupt request Next address instruction execution Interrupt servicing execution HALT mode held Reset signal generation Reset processing x don t care 239 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 14 STANDBY FUNCTION 14 2 2 STOP mode 1 STOP mode set
295. on Aug 30 20 04 43 gt Communication interface to device Port UART ch0 Pulse number g Speed 115200Baud Download file Name fod vup e131frec Date sm Chksum ProgAtea 1 Connection to device Port UART chO Pulse Num O Speed 115200 Vad Operation Mode Chip Start Block c End Main window Standard tab in Device setup window Table 19 5 Oscillation Frequency and PG FP4 GUI Software Setting Value Example Oscillation Frequency PG FP4 GUI Software Setting Value Example Communication Frequency 1 MHz lt fx lt 4 MHz 4 MHz lt fx lt 8 MHz 8 MHz lt fx lt 9 MHz 9 MHz lt fx lt 10 MHz Caution The above is a recommendation value A value may change according to the environment to be used Set up after surely performing sufficient evaluation 19 6 2 RESET pin If the reset signal of the dedicated flash programmer is connected to the RESET pin that is connected to the reset signal generator on the board signal collision takes place To prevent this collision isolate the connection with the reset signal generator If the reset signal is input from the user system while the flash memory programming mode is set the flash memory will not be correctly programmed Do not input any signal other than the reset signal of the dedicated flash programmer Preliminary User s Manual U17446EJ1VOUD 275 CHAPTER 19 FLASH MEMORY Figure
296. on as interval timer square wave output When 8 bit timer counter H1 and compare register 01 CMP01 match an interrupt request signal INTTMH1 is generated and 8 bit timer counter H1 is cleared to OOH Compare register 11 CMP11 is not used in interval timer mode Since a match of 8 bit timer counter H1 and the CMP 11 register is not detected even if the CMP11 register is set timer output is not affected By setting bit O TOEN1 of timer H mode register 1 TMHMD71 to 1 a square wave of any frequency duty 50 is output from TOH1 1 Usage Generates the INTTMH1 signal repeatedly at the same interval lt 1 gt Set each register Figure 8 6 Register Setting During Interval Timer Square Wave Output Operation i Setting timer H mode register 1 TMHMD1 TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOENI TMHMD1 Timer output setting Timer output level inversion setting Interval timer mode setting Count clock fent selection Count operation stopped ii CMPO1 register setting e Compare value N lt 2 gt Count operation starts when TMHE1 1 lt 3 gt When the values of 8 bit timer counter H1 and the CMP01 register match the INTTMH1 signal is generated and 8 bit timer counter H1 is cleared to OOH Interval time N 1 fcnt lt 4 gt Subsequently the INTTMH1 signal is generated at the same interval To stop the count operation clear TMHE 1 to 0 Preliminary User
297. on clock of the watchdog timer This register can be set by an 8 bit memory manipulation instruction and can be read many times but can be written only once after reset is released Generation of reset signal sets this register to 67H Figure 9 2 Format of Watchdog Timer Mode Register WDTM Address FF48H After reset 67H R W Symbol 7 6 5 4 3 2 1 0 WDTM wocs4 wocs3 wocs2 wocs1 wDcso WDcs4 wDCS3N 1 Operation clock selection Low speed Ring OSC clock fri System Clock fx Watchdog timer operation stopped wpcs1N Overflow time setting During low speed Ring OSC_ During system clock operation clock operation 2 Vfru 4 27 ms 2 fx 819 2 us 2 fr 8 53 ms 2 fx 1 64 ms 2 fr 17 07 ms 2 fx 3 28 ms 2 fr 34 13 ms 2 fx 6 55 ms 2 fr 68 27 ms 2 fx 13 11 ms 2 ifr 136 53 ms 2 8 fx 26 21 ms 2 Ifa 273 07 ms 2 fx 52 43 ms 2 fr 546 13 ms 27 fx 104 86 ms Notes 1 If low speed Ring OSC cannot be stopped is specified by the option byte this cannot be set The low speed Ring OSC clock will be selected no matter what value is written 2 Reset is released at the maximum cycle WDCS2 1 0 1 1 1 Preliminary User s Manual U17446EJ1VOUD 151 CHAPTER 9 WATCHDOG TIMER Cautions 1 Set bits 7 6 and 5 to 0 1 and 1 respectively when low speed Ring OSC cannot be stopped is selected by the option byte other val
298. ool 11 or on Selects count clock setting 11 is prohibited Specifies both edges for pulse width detection Specifies both edges for pulse width detection Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement See the description of the respective control registers for details Preliminary User s Manual U17446E 1VOUD 105 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 Figure 6 22 Timing of Pulse Width Measurement Operation with Free Running Counter with Both Edges Specified Count clock TMOO count value Xooook 0001 HX X Do Xoo 1 y X pt Yor i K FFFEHXOo00HY X D2 X D2 ioe X X D3 T1000 pin input i i i 1 1 CRO10 capture value xo ye ee EE 1 i INTTMO10 i eu l a S h T1010 pin met i a INTTMO00 cia i i OVF00 i i i i Note 1 i i i i D1 D0 xt 10000H D1 D2 xt D3 D2 l l l l l 1 l 10000H D1 D2 1 xt Note OVFOO must be cleared by software 106 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 3 Pulse width measurement with free running counter and two capture registers When 16 bit timer counter 00 TMOO is operated in free running mode it is possible to measure the pulse width of the signal input to the T1000 pin When the rising o
299. ory manipulation instruction Reset signal generation clears this register to OOH Figure 19 15 Format of Flash Programming Command Register FLCMD Address FFA3H After reset 00H R W Symbol FLCMD2 FLCMD1 FLOMDO Command Name Internal verify This command is used to check if data has been correctly written to the flash memory After data has been written to the memory execute this command by specifying a block number start address and end address If an error occurs bit 1 VCERR or bit 2 WEPRERR of the flash status register PFS is set to 1 Block erase This command is used to erase specified block It is used both in the on board mode and self programming mode 1 0 Block blank check This command is used to check if the specified block has been erased 1 1 Byte write This command is used to write 1 byte data to the specified address in the flash memory Specify the write address and write data then execute this command Other than above Setting prohibited Note If a value other than the above is set and the self programming mode is set the self programming mode is canceled immediately and no execution occurs At this time the flag of the PFS register is not set Preliminary User s Manual U17446EJ1VOUD 287 CHAPTER 19 FLASH MEMORY 5 Flash address pointers H and L FLAPH and FLAPL These registers are used to specify the start address of the flash memory when the memory is erased writ
300. otes 1 The operation stop time is 276 ws MIN 544 us TYP and 1 074 ms MAX 2 When reset is effected P130 outputs a low level If P130 is set to output a high level before reset is effected the output signal of P130 can be dummy output as the reset signal to the CPU Remark fx System clock oscillation frequency 246 Preliminary User s Manual U17446EJ1VOUD CHAPTER 15 RESET FUNCTION Figure 15 3 Timing of Reset by Overflow of Watchdog Timer lt 1 gt With high speed Ring OSC clock or external clock input High speed Ring OSC clock or external clock input Normal operation Resetperiod Normal operation reset processing CPU clock CPU clock in progress oscillation stops p resstp 9 r Operation stops because option Watchdog overnow byte is referenced te 1 Internal reset signal N J Port pin Hi Z Except PISO er eet Oe ES eS eS Port pin P130 Note 2 Notes 1 The operation stop time is 277 us MIN 544 ws TYP and 1 075 ms MAX 2 When reset is effected P130 outputs a low level If P130 is set to output a high level before reset is effected the output signal of P130 can be dummy output as the reset signal to the CPU Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer lt 2 gt With crystal ceramic oscillation clock Crystal ceramic i oscillation clock i Oscilation stabilization Normal operation S reset processing CPU c
301. ounter 00 c TI010 This pin inputs a capture trigger signal to the capture register CROOO of 16 bit timer event counter 00 Preliminary User s Manual U17446EJ1VOUD 23 CHAPTER 2 PIN FUNCTIONS d TOOO This pin outputs a signal from 16 bit timer event counter 00 2 2 4 P40 to P47 Port 4 P40 to P47 constitute a 8 bit I O port port 4 In addition to I O port pins P41 to P44 also have functions to output a timer signal input external interrupt request signals and input output the data of the serial interface These pins can be set to the following operation modes in 1 bit units 1 2 Port mode P40 to P47 function as a 8 bit I O port Each bit of this port can be set to the input or output mode by using port mode register 4 PM4 In addition an on chip pull up resistor can be connected to the port by using pull up resistor option register 4 PU4 Control mode P41 to 44 function to output a signal from an internal timer input external interrupt request signals and input output data of the serial interface a INTP1 and INTP3 These are external interrupt request input pins for which the valid edge rising edge falling edge or both rising and falling edges can be specified b TOH1 This is the output pin of 8 bit timer H1 c TxD6 This pin outputs serial data from the asynchronous serial interface d RxD6 This pin inputs serial data to the asynchronous serial interface 2 2 5 P120 to P123 Port 12
302. ows 20k Brate BRmin FLmax 11y oy The permissible baud rate error between UART6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions as follows Table 11 5 Maximum Minimum Permissible Baud Rate Error Division Ratio k Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error 3 53 4 26 4 56 4 66 4 72 Remarks 1 The permissible error of reception depends on the number of bits in one frame input clock frequency and division ratio k The higher the input clock frequency and the higher the division ratio k the higher the permissible error 2 k Set value of BRGC6 Preliminary User s Manual U17446EJ1VOUD 215 CHAPTER 11 SERIAL INTERFACE UART6 5 Data frame length during continuous transmission When data is continuously transmitted the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value However the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected Figure 11 26 Data Frame Length During Continuous Transmission 1 data frame Start bit of second byte a FE aA TOE O F Fisip PEO FeO Where the 1 bit data length is FL the stop bit length is FLstp and base clock frequency is fxcike the following expression is satisfied FLstp FL 2 fxcike
303. perFlash is a registered trademark of Silicon Storage Technology Inc in several countries including the United States and Japan Caution This product uses SuperFlash technology licensed from Silicon Storage Technology inc e The information contained in this document is being issued in advance of the production cycle for the product The parameters for the product may change before final production or NEC Electronics Corporation at its own discretion may withdraw the product prior to its production e Not all products and or types are available in every country Please check with an NEC Electronics sales representative for availability and additional information e No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document e NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others e Descriptions of circuits software and other related information in this document are provided for illustrative purpos
304. peration Setting 16 bit timer mode control register 00 TMC00 and capture compare control register 00 CRC00 as shown in Figure 6 10 allows operation as an interval timer Setting The basic operation setting procedure is as follows lt l gt Setthe CRCOO register see Figure 6 10 for the set value lt 2 gt Setany value to the CR000 register lt 3 gt Setthe count clock by using the PRMO0 register lt 4 gt Setthe TMCOO register to start the operation see Figure 6 10 for the set value Caution Changing the CR000 setting during TM00 operation may cause a malfunction To change the setting refer to 6 5 Cautions Related to 16 Bit Timer Event Counter 00 17 Changing compare register during timer operation Remark For how to enable the INTTMO000 interrupt see CHAPTER 13 INTERRUPT FUNCTIONS Interrupt requests are generated repeatedly using the count value set in 16 bit timer capture compare register 000 CR000 beforehand as the interval When the count value of 16 bit timer counter 00 TM00 matches the value set to CR000 counting continues with the TM00 value cleared to 0 and the interrupt request signal INTTM000 is generated The count clock of the 16 bit timer event counter can be selected using bits 0 and 1 PRM000 PRMO01 of prescaler mode register 00 PRMOO 96 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 Figure 6 10 Control Register Settings for Interval Tim
305. pped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is cleared to 0 When it is at OOH to 1FH bit 8 is set to 1 See Illustration below Operand format Label or FE20H to FF1FH immediate data Label or FE20H to FF1FH immediate data even address only Description example EQU DATA1 OFE90H DATA1 indicates FE90H in saddr area MOV DATA1 50H When the immediate data to 50H Instruction code 1 1 1 1 0 1 0 1 OP code 1 0 0 1 0 0 0 O 90H saddr offset 0 1 0 1 0 0 0 0 50H immediate data Illustration 7 0 OP code saddr offset m Short direct memory Effective address When 8 bit immediate data is 20H to FF When 8 bit immediate data is OOH to 1F 5a H H Preliminary User s Manual U17446EJ1VOUD 43 CHAPTER 3 CPU ARCHITECTURE 3 4 3 Special function register SFR addressing Function A memory mapped special function register SFR is addressed with the 8 bit immediate data in an instruction word This addressing is applied to the 256 byte space FFOOH to FFFFH However SFRs mapped at FFOOH to FF1FH are accessed with short direct addressing Operand format Special function register name Description example MOV PMO A When selecting PMO for sfr Instruction code 1 1 1 0 0 1 1 1 Illustration OP code sfr offset SFR Effective
306. prohibited 2 ES010 ES000 Bits 5 and 4 of prescaler mode register 00 P RM00 CRC002 Bit 2 of capture compare control register 00 CRC00 Cautions 1 In the free running mode and in the clear amp start mode using the valid edge of the TI000 pin if CR010 is set to 0000H an interrupt request INTTM010 is generated when CR010 changes from 0000H to 0001H following overflow FFFFH 2 If the new value of CR010 is less than the value of 16 bit timer counter 0 TM00 TM00 continues counting overflows and then starts counting from 0 again If the new value of CR010 is less than the old value therefore the timer must be reset to be restarted after the value of CR010 is changed 3 The value of CR010 after 16 bit timer event counter 00 has stopped is not guaranteed 4 The capture operation may not be performed for CR010 set in compare mode even if a capture trigger is input 5 If the register read period and the input of the capture trigger conflict when CR010 is used as a capture register the capture trigger input takes precedence and the read data is undefined Also if the timer count stop and the input of the capture trigger conflict the capture data is undefined 6 Changing the CR010 setting during TM00 operation may cause a malfunction To change the setting refer to 6 5 Cautions Related to 16 Bit Timer Event Counter 00 17 Changing compare register during timer operation Preliminary User s Manual U17446E 1VOUD 89
307. ps operation cleared to 0 when bit 7 POWER6 or bit 6 TXE6 of asynchronous serial interface operation mode register 6 ASIM6 is 0 It starts counting when POWER6 1 and TXE6 1 The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 TXB6 If data are continuously transmitted the counter is cleared to 0 again when one frame of data has been completely transmitted If there is no data to be transmitted next the counter is not cleared to 0 and continues counting until POWER6 or TXE6 is cleared to 0 Reception counter This counter stops operation cleared to 0 when bit 7 POWER86 or bit 5 RXE6 of asynchronous serial interface operation mode register 6 ASIM6 is 0 It starts counting when the start bit has been detected The counter stops operation after one frame has been received until the next start bit is detected Preliminary User s Manual U17446EJ1VOUD CHAPTER 11 SERIAL INTERFACE UART6 Figure 11 24 Configuration of Baud Rate Generator POWER6 fxP fxP 2 fxp 22 fxp 23 fxp 24 fxp 2 fxp 2 Baud rate generator POWER6 TXE6 or RXE6 Selector fxcike fxP 27 i fxP 28 I fxP 29 i fxP 210 Ji I Match detector Baud rate fxP 2 l I I I CKSR6 TPS63 to TPS60 BRGC6 MDL67 to MDL60 le P Remark POWER6 Bit 7 of asynchronous serial interface operation mode register 6 ASIM6 TXE6 Bit 6 of ASIM6 RXE6 Bit 5 of ASIM6 CKSR6 Clock
308. ption Register Address FF30H After reset OOH R W Symbol Address FF32H After reset OOH R W Symbol Address FF33H After reset OOH R W bane Address FF34H After reset OOH R W Symbol PU47 PU46 PU45 PU44 PU43 PU42 PU41 PU40 Address FF3CH After reset 00H R W Symbol Selection of connection of on chip pull up resistor of Pmn m 0 2 3 4 or 12 n 0 to 7 Does not connect on chip pull up resistor Connects on chip pull up resistor Preliminary User s Manual U17446EJ1VOUD 67 CHAPTER 4 PORT FUNCTIONS 4 4 Operation of Port Function The operation of a port differs as follows depending on the setting of the I O mode Caution Although a 1 bit memory manipulation instruction manipulates 1 bit it accesses a port in 8 bit units Therefore the contents of the output latch of a pin in the input mode even if it is not subject to manipulation by the instruction are undefined in a port with a mixture of inputs and outputs 4 4 1 Writing to I O port 1 In output mode A value can be written to the output latch by a transfer instruction In addition the contents of the output latch are output from the pin Once data is written to the output latch it is retained until new data is written to the output latch Reset signal generation clears the data in the output latch 2 In input mode A value can be written to the output latch by a transfer instruction Because the output buffer is off however the pin sta
309. r and connect the flash programmer via the test pad Keep the wiring as short as possible refer to Figure 19 5 and Table 19 4 2 Set the oscillation frequency of the communication clock for writing using the GUI software of the dedicated flash programmer Research the series parallel resonant and antiresonant frequencies of the resonator used and set the oscillation frequency so that it is outside the range of the resonant frequency 10 refer to Figure 19 6 and Table 19 5 Figure 19 5 Example of Mounting Test Pads Test pad Vss X1 X2 eget 4 77T Table 19 4 Clock to Be Used and Mounting of Test Pads Clock to Be Used Mounting of Test Pads High speed Ring OSC clock Not required External clock Crystal ceramic oscillation Before resonator is mounted clock After resonator is mounted Required 274 Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY Figure 19 6 PG FP4 GUI Software Setting Example Click Set oscillation frequency Properties Standard Advanced Device Setting file C Program Files NECT ools32 PG FP4 SET 78F9222 SET Device Name 78F9222 Stalus autoconnected Bootloader Version V1 15 Firmvare Version V1 32 octr off Parallel port in remote control mode Parameter file Name 78F9222 PRM Version 1 003 mi Device Setting file 1 MByte Kenneally ek ie Name 79F9222 SET arameter file AutoCon is on Date M
310. r 2 RD Read signal WRxx Write signal 53 Preliminary User s Manual U17446EJ1VOUD CHAPTER 4 PORT FUNCTIONS 4 2 3 Port3 Pins P30 to P33 constitute a 4 bit I O port with an output latch Each bit of this port can be set to the input or output mode by using port mode register 54 Preliminary User s Manual U17446EJ1VOUD MA WReu CHAPTER 4 PORT FUNCTIONS Figure 4 5 Block Diagram of P31 Voo DHF Internal bus Alternate function RD 5 l lt it amp 1 3 a WRrort P3 A Output latch x P31 lt P31 TI010 TOOO INTP2 WRem PM3 PM31 Alternate function PU3 Pull up resistor option register 3 P3 Port register 3 PM3 Port mode register 3 RD Read signal WRxx Write signal Preliminary User s Manual U17446EJ1VOUD 55 CHAPTER 4 PORT FUNCTIONS Figure 4 6 Block Diagram of P32 and P33 Voo m a MM WRru PU32 PU33 WRPorT Internal bus T 1 P3 Output latch P32 P33 P32 P33 PM3 PM32 PM33 p DB PU3 Pull up resistor option register 3 P3 Port register 3 PM3 Port mode register 3 RD Read signal WRxx Write signal Figure 4 7 Block Diagram of P34 rN RD ai ne 4 P34 RESET Cc Reset O Option byte Ve RD Read signal Caution Because the P34 pin functions alternately as the RESET pin if it is use
311. r FUNCHON e r eda ots edie ee aae e aare ee Nea aa par e nanan ahe Saan da aoaaa daen iadu 217 12 2 Multiplier Comfiguration cceeeccceseeeeeeseeeeeeeseeeseseeneeseseeneeseseseenseseseeeseseseaeseseseeesesesseensnnennaes 217 12 3 Multiplier Control Register ccccessesccssseneeeeseeeseseeeeeeeeeeseeesesesneesesesneeseseeneesesesneesesesneeseenesnaes 219 12 4 Multiplier Operation sez nicecacecescecctsscceccseesensecccetecesanavecteccseesasenzenatecceeeecenazseslscdtetencacausvedcteseqctsinavae 220 CHAPTER 13 INTERRUPT FUNCTIONS cccccssccecesseeeeeeseeeeeeeeeeeeseeeseeeseseseaeseseseaeseseseansesesseeneeeesaes 221 13 1 Interrupt FUNCtION Ty Pe iiccicccncece sec ccvecsceecsnectensrecs cesetececceneeee se edtuedaeravecesedanaueeceesteessannbuateesereets 221 13 2 Interrupt Sources and Configuration ccccceseeececeseeeeeeseeeseeeeeenseeeseenseeeseeeeseseseaeseeeseenseeeseaes 222 13 3 Interrupt Function Control Registers cccsssscccesseceeeseeeeeseseenseeeseeeeseseseeeseseseenseeeseneeeseaes 224 13 4 Interrupt Servicing Operation 0 ccccceeeeeeeeeeeeeeeeeneeeeeeeneeeeaeeeeeseeeseaeeaaneeeeseeeseeeeeeneeeeeeeeeens 229 13 4 1 Maskable interrupt request acknowledgment operatiOn ccccccceeeeceeceeeeeseeeeaeeeeeeeseeeesaees 229 13 4 2 Multiple interrupt servicing cccceececececeeeeece ce eeeeeeeeeeaece cece ceeseaaeceeeeesesaaeaeeeeeeesenseaeeeeeenenaeees 232 13 4 3 Interrupt request PEN
312. r Stop bit is not detected Overrun error Reception of the next data is completed before data is read from receive buffer register 6 RXB6 The error interrupt can be separated into reception completion interrupt INTSR6 and error interrupt INTSRE6 by clearing bit 0 ISRM6 of asynchronous serial interface operation mode register 6 ASIM6 to 0 Figure 11 20 Reception Error Interrupt 1 If ISRM6 is cleared to 0 reception completion interrupt INTSR6 and error interrupt INTSRE6 are separated a No error during reception b Error during reception INTSR6 INTSR6 INTSRE6 INTSRE6 2 If ISRM6 is set to 1 error interrupt is included in INTSR6 a No error during reception b Error during reception INTSR6 INTSR6 INTSRE6 INTSRE6 Preliminary User s Manual U17446EJ1VOUD 207 CHAPTER 11 SERIAL INTERFACE UART6 g Noise filter of receive data The RxD6 signal is sampled with the base clock output by the prescaler block If two sampled values are the same the output of the match detector changes and the data is sampled as input data Because the circuit is configured as shown in Figure 11 21 the internal processing of the reception operation is delayed by two clocks from the external signal status Figure 11 21 Noise Filter Circuit Base clock Internal signal A Match detector RxD6 P44 Internal signal B h SBF transmission When the device is incorporated in LIN
313. r ar e a aaa en da re re a aa a aAA aea aa AEE aae aaa Eara era iaia 15 1 3 Ordering INFOrmation ecen enaa a E E EE E AEN 16 1 4 Pin Configuration Top View ssssssusseennnsnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nennen 17 1 5 78KO0S KX1 Product LineData a aaar ae a a aa aa aaa a E aE aaraa aaa E aaa iaaa 18 T6 Block Diagram ecien aAa E aag ANRA kaya Eata RERA 19 17 Functional QUthine nessieira renaren an aN AA EA AANEEN AREENA SEN EA AAT 20 CHAPTER 2 PIN FUNCT ON a a a ee tie tec aE r Aaaa pa a Aa aa aa AA eaa Aa pran aia ENAK EEAS 21 2k Pin Function LASt ccs cicecec caccecetesccccccessecducecezecescaseccadtsecceetenstincercsuecedesecuceueasecdacusszuneregsuceenaseccattess 21 2 2 Pim FUNES nena a hu dece a site ens naaee dan Decent a a 23 2 2 1 PO0 t0 PO3 POM O noed e eaei ainete A e a i i e iadaan 23 2 2 2 P2010 P239 POr 2 sessris pesn ie sispann ain a idean naai a ia sa eren a aaee eana oi eSa headit 23 2 2 3 EEE OTON mot E ROMS PEETA ETEA A AE A T E 23 2 2 4 P40 to PAT PON Ainnir lieve yg hee a a E aN re ede 24 2 2 5 RAA o H ai PA E AES a E A EEEN T E A AE EEA T TE 24 2 2 6 Eae OIR dedo a ii Ke D REEE E E E E E O TE E ee a 24 227 RESET aniru N E ay eee ea eet 24 2 2 8 KA ae D O E A E E AE EE 25 2 2 9 NA AE E P EAE OM can 2 E A A EA E EE 25 2240 JAVSS rie e EE E wien heeled nei eon eee ee 25 ZA MBD atte ori na E Geen bal N len N 25 PAPA P A E os dover EAE dates epuccunagead accu pond sau
314. r falling edge specified by bits 4 and 5 ES000 and ES010 of prescaler mode register 00 PRMOO is input to the T1000 pin the value of TMOO is taken into 16 bit timer capture compare register 010 CRO10 and an interrupt request signal INTTM010 is set Also when the inverse edge to that of the capture operation is input into CR010 the value of TMOO is taken into 16 bit timer capture compare register 000 CR 000 Sampling is performed using the count clock cycle selected by prescaler mode register 00 PRMOO and a capture operation is only performed when a valid level of the T1000 pin is detected twice thus eliminating noise with a short pulse width Figure 6 23 Control Register Settings for Pulse Width Measurement with Free Running Counter and Two Capture Registers with Rising Edge Specified a 16 bit timer mode control register 00 TMC00 4 TMC003 TMC002 TMC001 OVFOO Twco0 EREL E b Capture compare control register 00 CRC00 Free running mode 7 6 5 4 3 CRC002 CRC001 CRC000 CRO000 used as capture register Captures to CR000 at inverse edge to valid edge of TIOOON CR010 used as capture register c Prescaler mode register 00 PRM00 ES110 ES100 ES010 ES000 3 2 PRM001 PRMO00 pamool an fore a o ooo Selects count clock setting 11 is prohibited Specifies rising edge for pulse width detection Setting invalid setting 10 is prohibited Note If the v
315. rammer dedicated to the microcontrollers incorporating a flash memory Flash memory programmer PG FPL2 Flash programmer dedicated to the microcontrollers incorporating a flash memory Flash memory programmer Provided with the in circuit emulator QB 78KOSKX1MINI FA 30MC 5A4 A Flash memory writing adapter Used in connection with Flash programmer Flash memory writing adapter Designed for use with a 30 pin plastic SSOP MC 5A4 type Remark FL PR4 and FA 30MC 5A4 A are products of Naito Densei Machida Mfg Co Ltd For further information contact Naito Densei Machida Mfg Co Ltd TEL 81 45 475 4191 354 Preliminary User s Manual U17446EJ1VOUD APPENDIX A DEVELOPMENT TOOLS A 5 Debugging Tools Hardware A 5 1 When using in circuit emulator IE 78KOS NS or IE 78KOS NS A IE 78KOS NS In circuit emulator In circuit emulator for debugging hardware and software of application system using 78K 0S Series Supports integrated debugger ID78KOS NS Used in combination with AC adapter emulation probe and interface adapter for connecting the host machine IE 78KOS NS A In circuit emulator This in circuit emulator has a coverage function in addition to the functions of the IE 78K0S NS and enhanced debugging functions such as an enhanced tracer function and timer function IE 70000 MC PS B AC adapter Adapter for supplying power from 100 to 240 VAC outlet IE 70000 CD IF A PC card interface PC card and
316. rd a dedicated program adapter FA series is necessary Download the latest programmer firmware GUI and parameter file from the download site for development tools http Awww necel com micro ods jpn index html Table 19 2 Wiring Between 78K0S KB1 and FlashPro4 FlashPro4 Connection Pin 78KOS KB1 Connection Pin Pin Name 1 0 Pin Function Pin Name Pin No cLK Clock to 78KOS KB1 X1 P121 FLMDON On board mode signal SI RxDN Receive signal X2 P122 SO TxDN Receive signal on board mode signal RESET Reset signal RESET P34 Voo voltage generation voltage monitor Ground Note In the 78KOS KB1 the CLK and FLMDO signals are connected to the X1 pin and the SI RxD and SO TxD signals to the X2 signal therefore these signals need to be directly connected 272 Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY Figure 19 3 Communication with FlashPro4 a FLMDO camo p somo PH O OMANONAWNH 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HHEHHHHHHHEHHHHHE 78K0S KB1 Table 19 3 Wiring Between 78K0S KB1 and PG FPL2 PG FPL2 Connection Pin 78KO0S KB1 Connection Pin Pin Name CLK Pin Function Clock to 78KOS KB1 Pin Name X1 P121 Pin No DGDATA Transmit receive signal on board mode signal X2 P122 RESET Reset signal RESET P34 Voo voltage genera
317. rder to return to normal processing StatusError END normal termination processing StatusNormal MOV MKO 11111111B Masks all interrupts MOV MK1 11111111B 324 Preliminary User s Manual U17446EJ1VOUD DI ModeOnLoop MOV MOV MOV MOV MOV MOV CMP BNZ RET FS 00H FCMD 0A5H LPMC 01H LPMC 0FEH 4J g g y g LPMC 01H A PFS A 00H S ModeOnLoop CHAPTER 19 FLASH MEMORY PFCMD register control FLPMC register control sets value FLPMC register control inverts set value Sets self programming mode via FLPMC register control sets value Checks completion of write to specific registers Repeats the same processing when an error occurs Processing to MOV MOV MOV MOV MOV MOV CMP BNZ MOV MOV EI RET FS 00H FCMD 0A5H LPMC 00H LPMC 0FFH WoW yj uw LPMC 00H A PFS A 00H SModeOff MKO INT_MKO MK1 INT_MK1 PFCMD register control FLPMC register control sets value FLPMC register control inverts set value Sets normal mode via FLPMC register control sets value Checks completion of write to specific registers Repeats the same processing when an error occurs Restores interrupt mask flag DataAdrTop DB DB XXH XXH Preliminary User s Manual U17446EJ1VOUD 325 CHAPTER 19 FLASH MEMORY DB XXH DB XXH DB XXH DataAdrBtm 326 Preliminary User s Manua
318. re 10 1 Timing of A D Converter Sampling and A D Conversion ADCS lt 1 or ADS rewrite _2 MA ADCS Sampling timing INTAD Note Sampling Sampling time time is le Conversion time Conversion time Note 2 or 3 clocks are required from the ADCS rising to sampling start 160 Preliminary User s Manual U17446EJ1VOUD CHAPTER 10 A D CONVERTER Table 10 1 Sampling Time and A D Conversion Time FR2 FR1 FRO Reference Sampling Conversion fxe 8 MHz fxe 10 MHz Note 2 Note 3 Voltage Time Time Sampling Conversion Sampling Conversion Range 1 Time TimeNot3 TimeNote2 TimeNote 0 0 O AVrer gt 4 5 V 12 fxp 36 fxP 1 5 us 4 5 us 1 2 us 3 6 us 0 0 1 AVrer gt 2 85 V 24 fxp 48lfxP 3 0 us 6 0 us Setting prohibited Setting prohibited 2 4 us 4 8 us 0 1 0 AVrer gt 2 7 V 48 fxp 72 fxp Setting prohibited Setting prohibited Setting prohibited Setting prohibited 6 0 ws 9 0 ws 4 8 ws 7 2 us 0 1 1 AVrer 2 2 7 V 88 fxP 112 fxP 11 0 us 14 0 us Setting prohibited Setting prohibited 8 8 us 11 2 us 1 0 O AVrer 24 5 V 24lfxP 72 fxp 3 0 us 9 0 us 2 4 us 7 2 US 1 0 1 AVre 22 85 V 48 fxp 96 fxP 6 0 us 12 0 us 4 8 us 9 6 us 1 1 0 AVrer gt 2 7 V 96 fxP 144 fxp 12 0 us 18 0 us Setting prohibited Setting prohibited 9 6 us 14 4 us 1 1 1 AVrer gt 2 7 V 176 fxe 224 fxp 22 0 us 28 0 us 17 2 us 22 4 us Notes 1 Be
319. register in advance is performed by executing the HALT instruction during self programming mode The HALT state is automatically released when processing is completed To shift to the self programming mode execute a specific sequence for a specific register Refer to 19 8 4 Example of shifting normal mode to self programming for details Remark Data written by self programming can be referenced with the MOV instruction Table 19 10 Self Programming Mode Mode User Program Execution Execution of Write erase for Flash Memory with HALT Instruction Normal mode Enabled Self programming mode Enabled Enabled Note Maskable interrupt servicing is disabled during self programming mode Figure 19 10 shows a block diagram for self programming Figure 19 11 shows the self programming state transition diagram Table 19 11 lists the commands for controlling self programming 280 Preliminary User s Manual U17446EJ1VOUD Figure 19 10 Block Diagram of Self Programming Internal bus if Protect byte M PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELFO Flash programming command register FLCMD Saar Flash programming mode Flash protect command control register FLPMC register PFCMD Flash address pointer H FLAPH Match GNOALPA9PPZLN enuey ssassn Heuwuiasd Increment circuit Flash memory controller Verify HALT release signal Flash memory
320. register value is changed to when the value is transferred to the register If a match signal is generated within three count clocks the changed value cannot be transferred to the register When the values of 8 bit timer counter H1 and the CMP11 register after the change match the TOH1 output becomes inactive 8 bit timer counter H1 is not cleared and the INTTMH1 signal is not generated Clearing the TMHE1 bit to 0 during timer H1 operation makes the INTTMH1 signal and TOH1 output inactive Preliminary User s Manual U17446EJ1VOUD 147 CHAPTER 9 WATCHDOG TIMER 9 1 Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop If a program loop is detected an internal reset signal is generated When a reset occurs due to the watchdog timer bit 4 WDTRF of the reset control flag register RESF is set to 1 For details of RESF see CHAPTER 15 RESET FUNCTION Table 9 1 Loop Detection Time of Watchdog Timer Loop Detection Time During Low Speed Ring OSC Clock Operation During System Clock Operation 2 fr 4 27 ms 2 fx 819 2 us 2 fr 8 53 ms 2 ifx 1 64 ms 2 fr 17 07 ms 2 fx 3 28 ms 2 fr 34 13 ms 2 fx 6 55 ms 2 fr 68 27 ms 2 fx 13 11 ms 2 fr 136 53 ms 2 fx 26 21 ms 2 frk 273 07 ms 2 fx 52 43 ms 2 fr 546 13 ms 2 fx 104 86 ms Remarks 1 fri Low speed Ring OSC clock oscillation frequency 2 fx
321. rement Operations ee eceeeeeeeceeneeeeeeneeeeeenaeeeceeeeeeeseaeeeeeeaeeeeneeeeeesnaeeeeneaas 102 6 4 4 Square wave output Operation eee eeeeeeeeeeeeeeeeeeaeeeceeeeeeeeseeeeeeeaeeeseeeaeeeesneeeeeenaeeeseenaeees 110 6 4 5 PPG Output Operation ee e Bes cbads tee e dee tstte sue sebs five celdnsagta aa E aai EEEE 112 6 4 6 One shot pulse output operation 0 eee cece ee eeeeeeeeeeaeeeseeeaeeeeeaeeeeeeaaeeeseeeaeeesneeeesenaeeeeeeeaeees 115 6 5 Cautions Related to 16 Bit Timer Event Counter 00 0 cceceeeeeceeeeeeeeeeeeeeeeeeeeeeeneeeesnenees 120 10 Preliminary Users Manual U17446EJ1VOUD CHAPTER 7 8 BIT TIMER 80 0 ccccccccsseeeesneeseceeeesneeeeeneeseceaesaesesneeseseeaessaesasneeseseeeseesaseesaneesennenss 126 7 4 Function of 8 Bit Timer 80 cccccceeeeneeeeeeee eee ee seen ee eeseaeeeeeseaeeeeaseceeeeaseeeeeeaseeeeeeeasseneeeasenneeees 126 7 2 Configuration of 8 Bit Timer 80 cceceeeseeeeeeeeeeeeeeeeeeeeeneeeeeeeenseeeeeenaseeeeeasseeeeseeseneeseeesenenes 127 7 3 Register Controlling 8 Bit Timer 80 ccccceeeeeseeeeeeeeeeeeeeeeeeeeeeseseeeeeeaeeeeeeeseseeeseesseenenssseenens 129 T A Operation of 8 Bit Timer BO eiia ieena aeaea cece aare e aaaea e e aaa Er a aa eiaa Aisia ra aandaa 130 7 4 1 Ope ratiorn asintermval timere nannan a a a dl Golde eh ue ee des 130 ka Notes on 3 Bi Timer OO soe noana a E A A A EA AAA 132 CHAPTER 8 8 BIT TIMER Hi vssesiescecceceesensecectciececs catevescetineo
322. riting all INCW MOVW CMPW BNC INCW BR HL AX HL AX DataAdrBtm Flashverify DE FlashWriteLoop i i 7 Clears flash status register Clears amp restarts WDT Self programming is started Checks write error Performs abnormal termination processing when an error occurs Shift to normal mode Restores interrupt mask flag data Address at which data to be written is located 1 Performs internal verify processing if write of all data is completed Address at which data is to be written 1 Preliminary User s Manual U17446EJ1VOUD 323 CHAPTER 19 FLASH MEMORY Setting internal verify command FlashVerify MOVW HL WriteAdr Sets verify address MOV FLCMD 01H Sets flash control command internal verify MOV A H MOV FLAPH A Sets verify start address MOV A L MOV FLAPL A Sets verify start address MOV A D MOV FLAPHC A Sets verify end address MOV A E MOV FLAPLC A Sets verify end address CALL ModeOn Shift to self programming mode Execution of internal verify command MOV PFS 00H Clears flash status register MOV WDTE 0ACH Clears amp restarts WDT HALT Self programming is started MOV A PFS CMP A 00H BNZ StatusError Checks internal verify error Performs abnormal termination processing when an error occurs CALL ModeOff Shift to normal mode BR StatusNormal END abnormal termination processing Perform processing to shift to normal mode in o
323. rks 1 The NP 30MC is a product made by Naito Densei Machida Mfg Co Ltd 2 The YSPACK30BK and NSPACK30BK are products by TOKYO ELETECH CORPORATION Preliminary User s Manual U17446EJ1VOUD 357 APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B 2 Condition for Connecting Target System When Using NP 30MC Emulation board IE 789234 NS EM1 Emulation probe N NP 30MC 13 mm Target system 358 Preliminary User s Manual U17446EJ1VOUD APPENDIX B NOTES ON TARGET SYSTEM DESIGN Figure B 3 Distance Between In Circuit Emulator and Conversion Connector When Using QB 80 EP 01T In circuit emulator IE 78KOS NS or IE 78KOS NS A Target system Emulation board SIMPLE PROBE Board Emulation probe Conversion connector QB 80 EP 01T QB 30MC EA 01T QB 30MC YQ 01T QB 30MC NQ 01T TGCN1 TGCN2 Figure B 4 Condition for Connecting Target System When Using QB 80 EP 01T Emulation board Emulation probe QB 80 EP 01T P a QB 30MC EA 01T Conversion connector QB 30MC YQ 01T QB 30MC NQ 01T Target system Preliminary User s Manual U17446EJ1VOUD 359 APPENDIX C REGISTER INDEX C 1 Register Index Register Name 8 bit A D conversion result register ADCRH 168 8 bit compare register 80 CR80 128 8 bit timer counter 80 TM80 128 8 bit timer H compare register 01 CMP01 135 8 bit timer H compare register 11 CMP11 135 8 bit timer H mode register 1 TMHMD7
324. rom operation start to operation stabilization Therefore when ADCS is set to 1 after 1 ws or more has elapsed from the time ADCE is set to 1 the conversion result at that time has priority over the first conversion result If the ADCS is set to 1 without waiting for 1 ws or longer ignore the data of the first conversion Table 10 3 Settings of ADCS and ADCE Stop status DC power consumption path does not exist Conversion waiting mode only comparator consumes power Conversion mode Comparator i 1 Conversion i i i a i i Conversion _ Conversion i Conversion stopped operation waiting operation Note The time from the rising of the ADCE bit to the rising of the ADCS bit must be 1 ws or longer to stabilize the internal circuit Cautions 1 The above sampling time and conversion time do not include the clock frequency error Select the conversion time taking the clock frequency error into consideration 2 If a bit other than ADCS of ADM is manipulated while A D conversion is stopped ADCS 0 and then A D conversion is started execute two NOP instructions or an instruction equivalent to two machine cycles and set ADCS to 1 3 A D conversion must be stopped ADCS 0 before rewriting bits FRO to FR2 4 Be sure to clear bits 6 2 and 1 to 0 166 Preliminary User s Manual U17446EJ1VOUD 2 3 CHAPTER 10 A D CONVERTER Analog input channel specification register ADS This register
325. rrespond to the vector table address 0014H 222 Preliminary User s Manual U17446EJ1VOUD CHAPTER 13 INTERRUPT FUNCTIONS Figure 13 1 Basic Configuration of Interrupt Function A Internal maskable interrupt 5 Internal bus S T T Vector table address generator Interrupt request gt Standby release signal B External maskable interrupt S Internal bus g S 1 l l l External interrupt mode registers 0 1 INTMO INTM1 Vector table address generator Interrupt request Standby release signal IF Interrupt request flag IE Interrupt enable flag MK Interrupt mask flag Preliminary User s Manual U17446EJ1VOUD 223 CHAPTER 13 INTERRUPT FUNCTIONS 13 3 Interrupt Function Control Registers The interrupt functions are controlled by the following four types of registers e Interrupt request flag registers 0 1 IFO IF1 e Interrupt mask flag registers 0 1 MKO MK1 e External interrupt mode registers 0 1 INTMO INTM1 e Program status word PSW Table 13 2 lists interrupt requests the corresponding interrupt request flags and interrupt mask flags Table 13 2 Interrupt Request Signals and Corresponding Flags Interrupt Request Signal Interrupt Request Flag Interrupt Mask Flag INTLVI LVIIF LVIMK INTPO PIFO PMKO INTP1 PIF 1 PMK1 INTTMH1 TMIFH1 TMMKH1 INTTMO00 TMIFOOO TMMK000 INTTM010 TMIF010 TMMK010 INTAD ADIF ADMK INTP2 PIF
326. s 16 bits Figure 12 3 shows the operation timing of the multiplier where MRAO is set to AAH and MRBO is set to D3H lt 1 gt Counting is started by setting MULSTO lt 2 gt The data generated by the selector is added to the data of MULO at each CPU clock and the counter value is incremented by one lt 3 gt If MULSTO is cleared when the counter value is 111B the operation is stopped At this time MULO holds the data lt 4 gt While MULSTO is low the counter and slave are cleared Figure 12 3 Multiplier Operation Timing Example of AAH x D3H CPU clock FU UU UU UU UU UU UU UU MRAO X AA MRBO X DB y es MULSTO Counter 000B 111B Y 000B poe coun carey ore ocee sree ecr 220 Preliminary User s Manual U17446EJ1VOUD CHAPTER 13 INTERRUPT FUNCTIONS 13 1 Interrupt Function Types All interrupts are controlled as maskable interrupts e Maskable interrupts These interrupts undergo mask control If two or more interrupt requests are simultaneously generated each interrupt has a predetermined priority as shown in Table 13 1 A standby release signal is generated There are nine internal sources and four external sources of maskable interrupts 221 Preliminary User s Manual U17446EJ1VOUD CHAPTER 13 INTERRUPT FUNCTIONS 13 2 Interrupt Sources and Configuration There are a total of 13 interrupt sources and up to four reset sources see Table 13 1 Table 13 1 Interrupt Sources Note 1 Interrupt
327. s 0081H 7 6 5 4 3 2 1 0 e uPD78F9232 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELFO Status Blocks 15 to 0 are protected Blocks 13 to 0 are protected Blocks 14 and 15 can be written or erased Blocks 11 to 0 are protected Blocks 12 to 15 can be written or erased Blocks 9 to 0 are protected Blocks 10 to 15 can be written or erased Blocks 7 to 0 are protected Blocks 8 to 15 can be written or erased Blocks 5 to 0 are protected Blocks 6 to 15 can be written or erased Blocks 3 to 0 are protected Blocks 4 to 15 can be written or erased Blocks 1 and 0 are protected Blocks 2 to 15 can be written or erased 1 All blocks can be written or erased Other than above Setting prohibited Preliminary User s Manual U17446EJ1VOUD 289 CHAPTER 19 FLASH MEMORY Figure 19 19 Format of Protect Byte 2 2 e UPD78F9234 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELFO Blocks 31 to 0 are protected Blocks 29 to 0 are protected Blocks 30 and 31 can be written or erased Blocks 27 to 0 are protected Blocks 28 to 31 can be written or erased Blocks 25 to 0 are protected Blocks 26 and 31 can be written or erased Blocks 23 to 0 are protected Blocks 24 to 31 can be written or erased Blocks 21 to 0 are protected Blocks 22 to 31 can be written or erased Blocks 19 to 0 are protected Blocks 20 to 31 can be written or erased Blocks 1
328. s and generates a voltage to be compared with the analog input signal Voltage comparator The voltage comparator compares the sampled analog input voltage and the output voltage of the D A converter Successive approximation register SAR This register compares the sampled analog voltage and the voltage of the D A converter and converts the result starting from the most significant bit MSB When the voltage value is converted into a digital value down to the least significant bit LSB end of A D conversion the contents of the SAR register are transferred to the A D conversion result register ADCR 10 bit A D conversion result register ADCR The result of A D conversion is loaded from the successive approximation register to this register each time A D conversion is completed and the ADCR register holds the result of A D conversion in its lower 10 bits the higher 6 bits are fixed to 0 8 bit A D conversion result register ADC RH The result of A D conversion is loaded from the successive approximation register to this register each time A D conversion is completed and the ADCRH register holds the result of A D conversion in its higher 8 bits Controller When A D conversion has been completed INTAD is generated Preliminary User s Manual U17446EJ1VOUD 163 CHAPTER 10 A D CONVERTER 9 AVrer pin This pin inputs an analog power reference voltage to the A D converter When the A D converter is not used connect this pin
329. s the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded X1 Oscillator When using the X1 oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows e Always make the ground point of the oscillator capacitor the same potential as Vss Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator Preliminary User s Manual U17446EJ1VOUD
330. s 277 us MIN 544 us TYP and 1 075 ms MAX 2 When reset is effected P130 outputs a low level If P130 is set to output a high level before reset is effected the output signal of P130 can be dummy output as the reset signal to the CPU lt 2 gt With crystal ceramic oscillation clock STOP instruction is executed High speed Ring OSC clock or external clock input i Normal i i me tant _ Stopstatus __ _ Resetperiod _ Oscillation stabilization Normal operation operation lt F ma A mee CPU clock ia ogress T oscillation stops oscillation stops r time kon reset processing CPU clock RESET Operation stops because option byte is referencedNot 1 Internal reset signal i i i Delay Delay TYP 100 ns TYP 100 ns Potpin Ne ne ae ee ee np except P130 Port pin P130 Note 2 Notes 1 The operation stop time is 276 us MIN 544 us TYP and 1 074 ms MAX 2 When reset is effected P130 outputs a low level If P130 is set to output a high level before reset is effected the output signal of P130 can be dummy output as the reset signal to the CPU Remarks 1 For the reset timing of the power on clear circuit and low voltage detector refer to CHAPTER 16 POWER ON CLEAR CIRCUIT and CHAPTER 17 LOW VOLTAGE DETECTOR 2 fx System clock oscillation frequency 248 Preliminary User s Manual U17446EJ1VOUD CHAPTER 15 RESET FUNCTION Table 15 1 Har
331. s Manual U17446EJ1VOUD 139 CHAPTER 8 8 BIT TIMER H1 2 Timing chart The timing of the interval timer square wave output operation is shown below Figure 8 7 Timing of Interval Timer Square Wave Output Operation 1 2 a Basic operation Count clock LI PLI LI LI i Count start i Clear Clear i i CMPO1 N o TMHE1 INTTMH1 e Interval time TOHI lt 1 gt lt 2 gt lt 2 gt lt 3 gt Level inversion Level inversion match interrupt occurrence match interrupt occurrence 8 bit timer counter H1 clear 8 bit timer counter H1 clear lt 1 gt The count operation is enabled by setting the TMHE1 bit to 1 The count clock starts counting no more than 1 clock after the operation is enabled lt 2 gt When the values of 8 bit timer counter H1 and the CMP01 register match the value of 8 bit timer counter H1 is cleared the TOH1 output level is inverted and the INTTMH1 signal is output lt 3 gt The INTTMH1 signal and TOH1 output become inactive by clearing the TMHE1 bit to 0 during timer H1 operation If these are inactive from the first the level is retained Remark N 01H to FEH 140 Preliminary User s Manual U17446EJ1VOUD CHAPTER 8 8 BIT TIMER H1 Figure 8 7 Timing of Interval Timer Square Wave Output Operation 2 2 b Operation when CMPO1 FFH Count clock LJ PLJI LILA LILI 4 Count start Bit timer counter Ht OOH OTH X i Clear Clear i i CMP01 FFH a
332. s Manual U17446EJ1VOUD 167 CHAPTER 10 A D CONVERTER 4 8 bit A D conversion result register ADCRH This register is an 8 bit register that stores the A D conversion result It stores the higher 8 bits of a 10 bit resolution result ADCRH can be read by an 8 bit memory manipulation instruction Reset signal generation makes ADCRH undefined Figure 10 7 Format of 8 Bit A D Conversion Result Register ADCRH Address FF1AH After reset Undefined R Symbol 7 6 5 4 3 2 1 0 5 Port mode control register 2 PMC 2 and port mode register 2 PM2 When using the P20 ANI0 to P23 ANI3 pins for analog input set PMC20 to PMC23 and PM20 to PM23 to 1 At this time the output latches of P20 to P23 may be 0 or 1 PMC2 and PM2 are set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears PMC2 to 00H and sets PM2 to FFH Figure 10 8 Format of Port Mode Control Register 2 PMC 2 Address FF84H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PMC2n Operation mode specification n 0 to 3 0 Port mode 1 A D converter mode Figure 10 9 Format of Port Mode Register 2 PM2 Address FF22H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 Pmn pin I O mode selection n 0 to 3 Output mode output buffer on Input mode output buffer off Caution When PMC20 to PMC23 are set to 1 the P20 ANI0 to P23 ANI3 pins cannot be used as port pins 168 Preliminary User s Manual U17446EJ1VOUD CHAPTER
333. s mode data of 1 byte is transmitted received following a start bit and a full duplex operation can be performed A dedicated UART baud rate generator is incorporated so that communication can be executed at a wide range of baud rates 1 Registers used e Asynchronous serial interface operation mode register 6 ASIM6 e Asynchronous serial interface reception error status register 6 ASIS6 e Asynchronous serial interface transmission status register 6 ASIF6 e Clock selection register 6 CKSR6 e Baud rate generator control register 6 BRGC6 e Asynchronous serial interface control register 6 ASICL6 e Input switch control register ISC e Port mode register 4 PM4 e Port register 4 P4 The basic procedure of setting an operation in the UART mode is as follows lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt 6 gt lt 7 gt Set the CKSR6 register see Figure 11 8 Set the BRGC6 register see Figure 11 9 Set bits 0 to 4 ISRM6 SL6 CL6 PS60 PS61 of the ASIM6 register see Figure 11 5 Set bits 0 and 1 TXDLV6 DIR6 of the ASICL6 register see Figure 11 10 Set bit 7 POWERS of the ASIM6 register to 1 Set bit 6 TXE6 of the ASIM6 register to 1 Transmission is enabled Set bit 5 RXE6 of the ASIM6 register to 1 Reception is enabled Write data to transmit buffer register 6 TXB6 Data transmission is started Caution Take relationship with the other party of communicatio
334. s time the conversion result is undefined Figure 10 12 A D Conversion Operation Rewriting ADM ADCS 1 Rewriting ADS ADCS 0 Conversion is stopped Conversion result is not retained Stopped ADCR ANIn ANIn ANIm ADCRH INTAD Remarks 1 n 0to3 2 m O0to3 A D conversion 172 Preliminary User s Manual U17446EJ1VOUD CHAPTER 10 A D CONVERTER The setting method is described below lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt 6 gt Set bit 0 ADCE of the A D converter mode register ADM to 1 Select the channel and conversion time using bits 1 and 0 ADS1 ADSO of the analog input channel specification register ADS and bits 5 to 3 FR2 to FRO of ADM Execute two NOP instructions or an instruction equivalent to two machine cycles Set bit 7 ADCS of ADM to 1 to start A D conversion An interrupt request signal INTAD is generated Transfer the A D conversion data to the A D conversion result register ADCR ADCRH lt Change the channel gt lt 7 gt lt 8 gt lt 9 gt Change the channel using bits 1 and 0 ADS1 ADSO of ADS An interrupt request signal INTAD is generated Transfer the A D conversion data to the A D conversion result register ADCR ADCRH lt Complete A D conversion gt lt 10 gt Clear ADCS to 0 lt 11 gt Clear ADCE to 0 Cautions 1 Make sure the period of lt 1 gt to lt 4 gt is 1 us or more 2 Itis no problem if
335. seeeseeeesesneeseseseeeseeseseeesesesneesesesneesesesensnenesnans 354 A 5 Debugging Tools Hardware sss sssssnunsennnnnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn 355 A 5 1 When using in circuit emulator IE 78KOS NS or IE 78KOS NS A cece ceeseeeeeeeeeeeenaeeeeeenes 355 A 5 2 When using in circuit emulator QB 78KOSKX1MINI 0 0 ee eeeeeeeeeeeeeeneeeeeeeeeeeceeaeeeeneeeeeeenaeeeeneaas 355 Preliminary User s Manual U17446EJ1VOUD 13 A 6 Debugging Tools Software ccccseccecceseseeeeseeneeeeeeeeeeeeeseeeeeeeseeneeeaseeeeeeaseeeeeeesesneeseeesseensnesenans 356 APPENDIX B NOTES ON TARGET SYSTEM DESIGN cceccsssseeeeeeseeeeeeseeeeeeeseeseeeesesneneneesenens 357 APPENDIX REGISTER INDEX vicccsteicccceectecccstecceeececuceccccecertesecceceessdececsenedeeresscueecsstecetessesncereesseetiess 360 C 1 Register Index Register NAMe cccccccessenneeeeeeneeeeeeeneeeeseeneeeeeeeneeseseceneeenseeneesaseeneeenseeneeenees 360 C2 Register index Symbol acena aea anana NOE ENEA eE ARONA AEI EURAN AA EENAA EAREN EAN 363 APPENDIX D LIST OF CAUTIONS assssneeseennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nanena 366 14 Preliminary User s Manual U17446EJ1VOUD CHAPTER 1 OVERVIEW 1 1 Features O Minimum instruction execution time selectable from high speed 0 2 ws to low speed 3 2 ws with CPU clock of 10 MHz O General purpose registers 8 bits x 8 registers O
336. seeneeeeseaes 253 16 3 Operation of Power on Clear Circuit cccccceceeeseeeceeeeeeeeeeeeeeeeeeseeeseseeeaeeeeeseeeseeeeeseaneeseneens 253 16 4 Cautions for Power on Clear CirCuit cccccceseseeeeseeeeeeeeeeneeeeseeeseeeseeeseeesseaeseeeseenseseseeneeeeseaes 254 CHAPTER 17 LOW VOLTAGE DETECTOR 2 ccccccccesseeceeeseeneeeesneeeeeeseeeseseeseeseeeseeeseseseeeseesseanseeenean 256 17 1 Functions of Low Voltage Detector 0 cccccceeseeeeeeneeeeeeenenseeeeeenseeeeseenseeesaeseeeseanseseseanseessenes 256 17 2 Configuration of Low Voltage Detector ccseeccceseeneeeseeeeeeeseenseseseeeseeeeseeeseeeseanseseseenseeeseaes 256 17 3 Registers Controlling Low Voltage Detector ccecccceesenceseseeeeeeeseeneeeeeseenseeeseenseeeseenseeeseaes 257 17 4 Operation of Low Voltage Detector cccccccseeneeseseeeeeeesneeseeeeneeseseeneeseeeeeneesesesneeseseseensenesnenes 259 17 5 Cautions for Low Voltage Detector cecccccesesencceseereeeeseenseeesnenseeeeseenseeesnaeseseseeseeeseenseeeseaes 262 CHAPTER 18 OPTION BYTE eoi E a shccecssucevces AA seers 265 CHAPTER 19 FLASH MEMORY ccccececcesseeceeeseeeseeeeeeeeeeeeeeeeseseeneeseseseeeseseeneesesesseeeseseseeeseseseuseseenees 268 AQT ae E T 268 19 2 Memory Configurations csccccccccscicecedstecceetsecenseteecveeeccedeecedeoceeeetveceeeedstcvendeveceese eoceceesdctereetcncees 269 12 Preliminary User s Manual U17446EJ1VOUD 13 3 Functional QUEMING iaria nan S a fenwec
337. selection register 6 BRGC6 Baud rate generator control register 6 Preliminary User s Manual U17446EJ1VOUD 211 2 212 CHAPTER 11 SERIAL INTERFACE UART6 Generation of serial clock A serial clock can be generated by using clock selection register 6 CKSR6 and baud rate generator control register 6 BRGC6 Select the clock to be input to the 8 bit counter by using bits 3 to 0 TPS63 to TPS60 of CKSR6 Bits 7 to 0 MDL67 to MDL60 of BRGC6 can be used to select the division value of the 8 bit counter a Baud rate The baud rate can be calculated by the following expression fxcLKe e Baud rate bps 2xk fxcLke Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register k Value set by MDL67 to MDL60 bits of BRGC6 register k 8 9 10 255 b Error of baud rate The baud rate error can be calculated by the following expression Error Actual baud rate baud rate with error e Desired baud rate correct baud rate x 100 Cautions 1 Keep the baud rate error during transmission to within the permissible error range at the reception destination 2 Make sure that the baud rate error during reception satisfies the range shown in 4 Permissible baud rate range during reception Example Frequency of base clock 10 MHz 10 000 000 Hz Set value of MDL67 to MDL60 bits of BRGC6 register 00100001B k 33 Target baud rate 153600 bps Baud rate 10 M 2 x 33 10000000
338. self programming mode lt 1 gt to lt 5 gt in 19 8 4 Execution of byte write command gt Error check lt 5 gt to lt 10 gt in 19 8 8 Mode is shifted from self programming mode to normal mode lt 1 gt to lt 5 gt in 19 8 5 lt 2 gt to lt 5 gt is repeated until all data are written The internal verify command is specified lt 1 gt to lt 5 gt in 19 8 9 Mode is shifted from normal mode to self programming mode lt 1 gt to lt 5 gt in 19 8 4 Execution of internal verify command Error check lt 6 gt to lt 11 gt in 19 8 9 lt 10 gt Mode is shifted from self programming mode to normal mode lt 1 gt to lt 5 gt in 19 8 5 Preliminary User s Manual U17446EJ1VOUD 321 CHAPTER 19 FLASH MEMORY Figure 19 29 Example of Operation When Interrupt Disabled Time Should Be Minimized from Write to Internal Verify Write to internal verify lt 1 gt Set source data for write Figure 19 24 lt 2 gt Specify byte write command lt 1 gt to lt 4 gt Figure 19 20 4 lt 3 gt Shift to self programming lt 1 gt to lt 5 gt mode lt 4 gt Execute byte write command Figure 19 24 lt 5 gt to lt 10 gt lt i gt Check execution resu Abnormal VCERR and WEPRERR flags ae 4 lt 5 gt Shift to normal mode Yes lt 6 gt All data written No Figure 19 25 lt 7 gt Specify internal verify command lt 1 gt to lt 5 gt Figure 19 20 4 lt 8 gt Shif
339. set signal is generated STOP mode is released and a reset operation is performed after the oscillation stabilization time has elapsed Figure 14 6 STOP Mode Release by Reset Signal Generation 1 If CPU clock is high speed Ring OSC clock or external input clock STOP instruction Reset signal ai ae ee Operation Reset Operation CPU status mode STOP mode period stops Operation mode System clock Oscillation _ Oscillation stops Oscillation oscillation Note Operation is stopped 277 ws MIN 544 ws TYP 1 075 ms MAX because the option byte is referenced 2 If CPU clock is crystal ceramic oscillation clock _ STOP instruction Reset signal poe er Operation Reset Operation Oscillation Operation CPU status mode STOP mode period stops stabilization waits mode Oscillation _ Oscillation stops Oscillation System clock oscillation JV Oscillation stabilization time 2 fx to 2 7 fx Note Operation is stopped 276 ws MIN 544 us TYP 1 074 ms MAX because the option byte is referenced Remark fx System clock oscillation frequency Table 14 5 Operation in Response to Interrupt Request in STOP Mode remesa wes Te ean Maskable interrupt request Next address instruction execution 0 1 Interrupt servicing execution Preliminary User s Manual U17446EJ 1VOUD 243 CHAPTER 15 RESET FUNCTION The following four oper
340. setting refer to 6 5 Cautions Related to 16 Bit Timer Event Counter 00 17 Changing compare register during timer operation Preliminary User s Manual U17446EJ 1VOUD CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 3 16 bit timer capture compare register 010 CR010 CRO10 is a 16 bit register which has the functions of both a capture register and a compare register Whether it is used as a capture register or a compare register is set by bit 2 CRC002 of capture compare control register 00 CRCOO CRO10 is set by 16 bit memory manipulation instruction Reset signal generation clears CRO10 to 0000H Figure 6 4 Format of 16 Bit Timer Capture Compare Register 010 CR010 Address FF16H FF17H After reset OOOOH R W Symbol FF17H FF16H e When CR010 is used as a compare register The value set in CRO10 is constantly compared with the 16 bit timer counter 00 TM00 count value and an interrupt request INTTM010 is generated if they match e When CR010 is used as a capture register It is possible to select the valid edge of the TI000 pin as the capture trigger The T1000 valid edge is set by means of prescaler mode register 00 PRMOO refer to Table 6 3 Table 6 3 CR010 Capture Trigger and Valid Edge of T1000 Pin CRC002 1 CRO010 Capture Trigger T1000 Pin Valid Edge Falling edge Falling edge Rising edge Rising edge Both rising and falling edges Both rising and falling edges Remarks 1 Setting ES010 ES000 1 0 is
341. sh programmer and the test pad must be mounted on the target system The test pad is required only when writing data with the crystal ceramic resonator mounted refer to Figure 19 5 for mounting of the test pad Off board programming Data can be written to the flash memory with a dedicated program adapter FA series before the 78KOS KB1 is mounted on the target system Remark The FL PR4 and FAseries are products of Naito Densei Machida Mfg Co Ltd Preliminary User s Manual U17446EJ1VOUD 271 CHAPTER 19 FLASH MEMORY 19 5 Programming Environment The environment required for writing a program to the flash memory is illustrated below Figure 19 2 Environment for Writing Program to Flash Memory FlashPro4 RS 232C NEC i Voo a use Vss RESET DGCLK ote USB DGDATA te Host machine 78K0S KB1 Dedicated flash programmer Note DGCLK and DGDATA are single wire bidirectional communication interfaces They use UART as the communication mode A host machine that controls the dedicated flash programmer is necessary When using the PG FP4 or FL PR4 data can be written with just the dedicated flash programmer after downloading the program from the host machine UART is used for manipulation such as writing and erasing when interfacing between the dedicated flash programmer and the 78KOS KB1 To write the flash memory off boa
342. so holds the value immediately before clock supply was stopped and outputs it However the operation is not guaranteed after clock supply is resumed Therefore reset the circuit so that POWER6 0 RXE6 0 and TXE6 0 3 If data is continuously transmitted the communication timing from the stop bit to the next start bit is extended two operating clocks of the macro However this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit Do not use the continuous transmission function if the interface is incorporated in LIN Preliminary User s Manual U17446EJ1VOUD 179 Remark CHAPTER 11 SERIAL INTERFACE UART6 LIN stands for Local Interconnect Network and is a low speed 1 to 20 kbps serial communication protocol intended to aid the cost reduction of an automotive network LIN communication is single master communication and up to 15 slaves can be connected to one master The LIN slaves are used to control the switches actuators and sensors and these are connected to the LIN master via the LIN network Normally the LIN master is connected to a network such as CAN Controller Area Network In addition the LIN bus uses a single wire method and is connected to the nodes via a transceiver that complies with 1509141 In the LIN protocol the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error Therefore c
343. ss 0 V 1 2 Parameter Conditions Output current high Pins other than 2 0V lt Von lt 5 5V R20 to R23 4 0V lt Vo0 lt 5 5V 2 0 V lt Voo lt 4 0 V P20 to P23 Per pin 2 0 V lt AVrer lt 5 5 V Total 2 0 V lt AVrer lt 5 5 V Output current low Per pin 2 0 V lt Voo lt 5 5 V Total of all pins 4 0 V lt Voo lt 5 5 V 2 0 V lt Voo lt 4 0 V Input voltage high POO to P03 P30 to P34 P40 to P47 P120 P123 P20 to P23 P121 P122 Input voltage low POO to P03 P30 to P34 P40 to P47 P120 P123 0 2Vop P20 to P23 0 3AVREF P121 P122 0 3Vop Output voltage high Total of pins other than 4 0 V lt Voo lt 5 5 V P20 to P23 lon1 5 mA lon1 15 mA lon 100 uA 2 0 V lt Voo lt 4 0 V Voo 0 5 Total of pins P20 to P23 4 0 V lt AVrer lt 5 5 V AVrer 1 0 lon2 10 mA lon2 5 mA 2 0 V lt AVrer lt 4 0 V AVrer 0 5 lon2 5 mA Output voltage low Total of pins 4 0 V lt Voo lt 5 5 V lo 30 mA lo 10 mA 2 0 V lt Voo lt 4 0 V lo 400 WA Input leakage current high Vi VoD Pins other than X1 Input leakage current low Vi 0V Pins other than X1 Output leakage current high Vo Voo Pins other than X2 Output leakage current low Vo 0V Pins other than X2 Note Use this product in a voltage range of 2 2 to 5 5 V because the detection voltage Vroc of the power on
344. ss 0014H 2 3 4 CALLT instruction table area The subroutine entry address of a 1 byte call instruction CALLT can be stored in the 64 byte area of addresses 0040H to 007FH Option byte area The option byte area is the 1 byte area of address 0080H For details refer to CHAPTER 18 OPTION BYTE Protect byte area The protect byte area is the 1 byte area of address 0081H For details refer to CHAPTER 19 FLASH MEMORY 3 1 2 Internal data memory space UPD78F9232 and uwPD78F9234 provide 256 byte internal high speed RAM The internal high speed RAM can also be used as a stack memory 30 Preliminary Users Manual U17446EJ1VOUD CHAPTER 3 CPU ARCHITECTURE 3 1 3 Special function register SFR area Special function registers SFRs of on chip peripheral hardware are allocated to the area of FFOOH to FFFFH see Table 3 3 3 1 4 Data memory addressing The 78K0S KB1 is provided with a wide range of addressing modes to make memory manipulation as efficient as possible The area FEOQOH to FEFFH which contains a data memory and the special function register area SFR can be accessed using a unique addressing mode in accordance with each function Figures 3 3 and 3 4 illustrate the data memory addressing Figure 3 3 Data Memory Addressing uPD78F9232 FFFFH ry Special function registers SFR FR 256 x 8 bits SFR addressing FF20H FERH AATE a T T e N e TA FFOOH FEFFH Short direct addressing Internal
345. sure to set the FR2 FR1 and FRO in accordance with the reference voltage range and satisfy Notes 2 and 3 below Example When AVreF gt 2 7 V e Set FR2 FR1 and FRO 0 1 1 or 1 1 1 e The sampling time is 11 0 ws or more and the A D conversion time is 14 0 ws or more and 100 ws or less 2 Set the sampling time as follows AV AV AV AV REF gt 4 5 V REF gt 4 0 V REF gt 2 7 V 1 0 ws or more 2 4 us or more REF gt 2 85 V 3 0 ws or more 11 0 us or more 3 Setthe A D conversion time as follows AV AV AV AV REF gt 4 5 V REF gt 4 0 V REF gt 2 7 V 3 0 ws or more and less than 100 ws 4 8 us or more and less than 100 ws REF gt 2 85 V 6 0 ws or more and less than 100 ws 14 0 ws or more and less than 100 ws Caution The above sampling time and conversion time do not include the clock frequency error Select the conversion time taking the clock frequency error into consideration Remarks 1 fxr Oscillation frequency of clock to peripheral hardware 2 The conversion time refers to the total of the sampling time and the time from successively comparing Preliminary User s Manual U17446EJ1VOUD with the sampling value until the conversion result is output 161 CHAPTER 10 A D CONVERTER Figure 10 2 shows the block diagram of A D converter Figure 10 2 Block Diagram of A D Converter iat Sample amp hold circuit ANI1 P21 S N Voltage comparator
346. t to self programming lt 1 gt to lt 5 gt mode lt 9 gt Execute internal verify command Figure 19 25 lt 6 gt to lt 10 gt Abnormal VCERR and WEPRERR flags Normal pare 3 lt 10 gt Shift to normal mode Normal termination Abnormal terminationN Note Perform processing to shift to normal mode in order to return to normal processing Remark lt 1 gt to lt 10 gt in Figure 19 29 correspond to lt 1 gt to lt 10 gt in 19 8 11 2 previous page 322 Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY An example of a program list when the interrupt disabled time from write to internal verify should be minimized in self programming mode is shown below Sets write command FlashWrite MOVW MOVW FlashWriteLoop MOV MOV MOV MOV MOV MOV MOV CALL HL DataAdrTop DE WriteAdr 7 FLCMD 05H A D es FLAPH A r m gt z E E gt ModeOn Sets address at which data to be written is located Sets address at which data is to be written Sets flash control command byte write Sets address at which data is to be written Sets address at which data is to be written Sets data to be written Shift to self programming mode Execution of write command MOV MOV HALT MOV CMP BNZ CALL MOV MOV EI PFS 00H WDTE 0ACH A PFS A 00H StatusError ModeOff MKO INT_MKO MK1 INT_MK1 F 7 Judgment of w
347. t value set in advance to 16 bit timer capture compare register 010 CRO10 After that the output becomes inactive at the count value set in advance to 16 bit timer capture compare register 000 CR 000 Note The case where N lt M is described here When N gt M the output becomes active with the CR000 register and inactive with the CR010 register Do notset N to M Caution Do not input the external trigger again while the one shot pulse is being output To output the one shot pulse again wait until the current one shot pulse output is completed Preliminary User s Manual U17446E 1VOUD 117 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 Figure 6 34 Control Register Settings for One Shot Pulse Output with External Trigger with Rising Edge Specified a 16 bit timer mode control register 00 TMC00 4 TMC003 TMC002 TMCO01 OVFOO TMCo0 Perera re eed oe Clears and starts at valid edge of T1000 pin b Capture compare control register 00 CRC00 3 CRC002 CRC001 CRC000 ones ee CRO000 used as compare register CR010 used as compare register c 16 bit timer output control register 00 TOC00 7 OSPT00 OSPE00 TOC004 LVSOO LVROO TOC001 TOE0O Enables TOOO output Inverts output upon match between TMO0 and CROOO Specifies initial value of TOOO output F F setting 11 is prohibited Inverts output upon match between TMOO0 and CR010 Sets one shot pulse output mode
348. ta Multiplication data register A MRAO register B MRBO Counter value 3 3 bit counter CPU clock 1 Start Clear Counter output 16 bit multiplication result storage register 0 Master MULO 16 bit multiplication result storage register 0 Slave 1 MULSTO Multiplier control register 0 MULCO e Internal bus a Reset Preliminary User s Manual U17446EJ1VOUD CHAPTER 12 MULTIPLIER 12 3 Multiplier Control Register The multiplier is controlled by the following register e Multiplier control register O MULCO 1 Multiplier control register 0 MULCO This register indicates the operating status of the multiplier after operation as well as controls the multiplier MULCO can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears this register to OOH Figure 12 2 Format of Multiplier Control Register 0 MULCO Address FFD2H After reset OOH RW Symbol 7 3 2 6 5 4 1 lt 0 gt MULSTO Multiplier operation start control bit Operating status of multiplier 0 Stops operation after resetting counter to 0 Operation stops 1 Enables operation Operation in progress Caution Be sure to clear bits 1 to 7 to 0 Preliminary User s Manual U17446EJ1VOUD 219 CHAPTER 12 MULTIPLIER 12 4 Multiplier Operation The multiplier of the 78KOS KB1 can execute the calculation of 8 bits x 8 bit
349. tage range of 2 2 to 5 5 V because the detection voltage Vroc of the power on clear POC circuit is 2 1 V 0 1V 20 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 2 PIN FUNCTIONS 2 1 Pin Function List 1 Port pins Pin Name Function After Reset Alternate Function Pin POO to P03 Port 0 Input 4 bit I O port Can be set to input or output mode in 1 bit units An on chip pull up resistor can be connected by setting software P20 to P23 Port 2 ANIO to ANI3 4 bit I O port Can be set to input or output mode in 1 bit units An on chip pull up resistor can be connected by setting software Port 3 Can be set to input or output mode in 1 TIOOO INTPO Bip l TI010 TOOO An on chip pull up resistor can be INTP2 connected by setting software Input only Port 4 8 bit I O port INTP3 Can be set to input or output mode in 1 bit units An on chip pull up resistor can be connected by setting software TOH1 TxD6 INTP1 RxD6 Port 12 4 bit I O port Can be set to input or output mode in 1 bit units An on chip pull up resistor can be connected only to P120 and P123 by setting software Port 13 1 bit output only port Note For settings of alternate function refer to CHAPTER 18 OPTION BYTE Caution The P121 X1 and P122 X2 pins are pulled down during reset Preliminary User s Manual U17446EJ1VOUD 21 CHAPTER 2 PIN FUNCTIONS 2 Non port pins Pin Name Function After
350. te taste A A EN O T 25 2 3 Pin I O Circuits and Connection of Unused PINS ceecceseseeeeeeeeeeenseeeeeeeeneeeeeseeeeeeeeneeseenens 26 CHAPTER 3 CPU ARCHITECTURE ooo cicccsccssccccececsascassscuceaseetts lt asaeanbeceasctcectnesavactarcerecstecauscnonesttec aanecaete 28 2A MEMORY SPACO moana ses sie ofteccereshectaetesdaceus vas died E AS 28 3 1 1 Internal program Memory SPACE eee eeeeeeeeeeeeeenneeeeeeeeeeeeeaeeeseeaaeeeeeeeeeeeenaeeeeeeaeeeseeeaeeeesaeeeeaas 30 3 1 2 Internal data memory SPACE i vesscs eevee cceeeeeye esse nieve peia eea eE 30 3 1 3 Special function register SFR Area oo eee inoi i e danei 31 3 1 4 Data memory ACCESSING 0 0 0 eee ee eeeeeeceeeeeeeeeeeeeeeeaaeeeteeeeeeeeaaeeeeeeaaeeeeeeeeeeeeaeeesesaeeeseeeeeeseneeeeneaas 31 3 2 Processor Regist rS sornas nenei cae stev veesite cuesstevecdu sstev cvesnute dees stevenesstte dey stevdveeniterersstee 33 3 2 1 Control iregisterss etfs tscle tei sana eee Geiss conte iad od Sala en onan shear Bis 33 3 2 2 General Purpose reQisters iniia eiia diini ea Sa e aoa daea 35 3 2 3 Special function registers SFRS cc eeeeceeseeeeeeeneeeeeeeaeeeeeneeeeeeaaeeeseeeaeeeseeeeeesaeeeseeaeeeeneeeeeey 36 3 3 Instruction Address Addressing scccccesseeeeeseeeeeeeeeeneeeeseeeseeeeseeeseseseeseeeseaeseseseanseseeseanseeeees 39 3 3 1 Relative AddreSSinG is eisien ieii e aaa a p testi biases 39 3 3 2 Immediate addressing eiaeia aea aa Eaa a a e EE E aa Eaa EE EEEa
351. tection Use Detects the baud rate error measures the T1000 input edge interval in the capture mode by detecting the synchronous field SF length and divides it by the number of bits e Serial interface UART6 182 Preliminary User s Manual U17446EJ1VOUD CHAPTER 11 SERIAL INTERFACE UART6 11 2 Configuration of Serial Interface UART6 Serial interface UART6 consists of the following hardware Table 11 1 Configuration of Serial Interface UART6 Item Configuration Registers Receive buffer register 6 RXB6 Receive shift register 6 RXS6 Transmit buffer register 6 TXB6 Transmit shift register 6 TXS6 Control registers Asynchronous serial interface operation mode register 6 ASIM6 Asynchronous serial interface reception error status register 6 ASIS6 Asynchronous serial interface transmission status register 6 ASIF6 Clock selection register 6 CKSR6 Baud rate generator control register 6 BRGC6 Asynchronous serial interface control register 6 ASICL6 Input switch control register ISC Port mode register 4 PM4 Port register 4 P4 Preliminary User s Manual U17446EJ1VOUD 183 vsL GNOALPA9PPZLN lenuew sJasn Aseuiwul asd Figure 11 4 Block Diagram of Serial Interface UART6 T1000 INTPON RxD6 P44 INTSR6 Reception control INTSRE6 Receive shift register 6 i 1 i fxp RXS6 i fxP 2 f fxp 2 Asyn
352. tection Note 1 INTPO Notes 1 The wakeup signal is detected at the edge of the pin and enables UART6 and sets the SBF reception mode 2 Reception continues until the STOP bit is detected When an SBF with low level data of 11 bits or more has been detected it is assumed that SBF reception has been completed correctly and an interrupt request signal is output If an SBF with low level data of less than 11 bits has been detected it is assumed that an SBF reception error has occurred The interrupt request signal is not output and the SBF reception mode is restored 3 If SBF reception has been completed correctly an interrupt request signal is output This SBF reception completion interrupt enables the capture timer Detection of errors OVE6 PE6 and FE6 is suppressed and error detection processing of UART communication and data transfer of the shift register and RXB6 is not performed The shift register holds the reset value FFH 4 Calculate the baud rate error from the bit length of the synchronous field disable UART6 after SF reception and then re set baud rate generator control register 6 BRGC6 5 Distinguish the checksum field by software Also perform processing by software to initialize UART6 after reception of the checksum field and to set the SBF reception mode again To perform a LIN receive operation use a configuration like the one shown in Figure 11 3 The wakeup signal transmitted from the LIN master is received by detec
353. ten or verified in the self programming mode FLAPH and FLAPL consist of counters and they are incremented until the values match with those of FLAPHC and FLAPLC when the programming command is not executed When the programming command is executed therefore set the value again These registers are set with a 1 bit or 8 bit memory manipulation instruction Reset signal generation makes these registers undefined Figure 19 16 Format of Flash Address Pointer H L FLAPH FLAPL Address FFA4H FFA5H After reset Undefined R W FLAPH FFA5H FLAPL FFA4H eS FLA FLA FLA FLA FLA FLA FLA FLA FLA FLA FLA FLA P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 PO Caution Be sure to clear bits 4 to 7 of FLAPH and FLAPHC to 0 before executing the self programming command If the value of these bits is 1 when executing the self programming command 6 Flash address pointer H compare register and flash address pointer L compare register FLAPHC and FLAPLC These registers are used to specify the address range in which the internal sequencer operates when the flash memory is verified in the self programming mode Set FLAPHC to the same value as that of FLAPH Set the last address of the range in which verification is to be executed to FLAPLC These registers are set with a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears these registers to OOH Figure 19 17 Format of Flash Address Pointer H L Compare R
354. ter FLPMC This register is used to set the operation mode when data is written to the flash memory in the self programming mode and to read the set value of the protect byte Data can be written to FLPMC only in a specific sequence refer to 19 8 3 2 Flash protect command register PFCMD so that the application system does not stop by accident because of malfunctions due to noise or program hang ups This register is set with an 8 bit memory manipulation instruction Reset signal generation makes the contents of this register undefined Preliminary User s Manual U17446EJ1VOUD 283 284 CHAPTER 19 FLASH MEMORY Figure 19 12 Format of Flash Programming Mode Control Register FLPMC Address FFA2H After reset Undefined 1 Riwnhete2 Symbol FLPMC N PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELFO EA FLSPM FLSPM Selection of operation mode during self programming mode Normal mode Flash memory instructions can be fetched from all addresses Notes 1 Cautions 1 Self programming mode Before executing the HALT instruction set the command address offset write data and set FLSPM to 1 After setting these items execute the HALT instruction the flash memory mode is then shifted from the normal mode to the flash memory programming mode PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELFO The set value of the protect byte is read to these bits Bit 0 FLSPM is cleared to 0 when reset is released The set value o
355. tered on match between TM00 and CR000 This means a 1 pulse count operation cannot be performed when this register is used as an external event counter However in the free running mode and in the clear amp start mode using the valid edge of TI000 pin if CR000 is set to 0000H an interrupt request INTTM000 is generated when CR000 changes from 0000H to 0001H following overflow FFFFH If the new value of CR000 is less than the value of 16 bit timer counter 0 TM00 TM00 continues counting overflows and then starts counting from 0 again If the new value of CRO000 is less than the old value therefore the timer must be reset to be restarted after the value of CR000 is changed The value of CR000 after 16 bit timer event counter 00 has stopped is not guaranteed The capture operation may not be performed for CR000 set in compare mode even if a capture trigger is input When P31 is used as the input pin for the valid edge of T1010 it cannot be used as a timer output TO00 Moreover when P31 is used as TOOO it cannot be used as the input pin for the valid edge of T1010 If the register read period and the input of the capture trigger conflict when CROOO is used as a capture register the capture trigger input takes precedence and the read data is undefined Also if the count stop of the timer and the input of the capture trigger conflict the capture trigger is undefined Changing the CR000 setting may cause a malfunction To change the
356. terminated Note This setting is not required when the watchdog timer is not used 300 Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY Figure 19 23 Example of Block Blank Check Operation in Self Programming Mode Block blank check lt 1 gt Set block blank check command FLCMD 04H lt 2 gt Set no of block for blank check to FLAPH lt 3 gt Set FLAPL to 00H lt 4 gt Set the same value as that of FLAPH to FLAPHC lt 5 gt Set FLAPLC to 00H lt 6 gt Clear PFS lt 7 gt Clear amp restart WDT counter WDTE ACH Note lt 8 gt Execute HALT instruction lt 9 gt Check execution resu Abnormal VCERR and WEPRERR flags lt 11 gt Normal termination lt 10 gt Abnormal termination Note This setting is not required when the watchdog timer is not used Remark lt 1 gt to lt 11 gt in Figure 19 23 correspond to lt 1 gt to lt 11 gt in 19 8 7 previous page Preliminary User s Manual U17446EJ1VOUD 301 CHAPTER 19 FLASH MEMORY An example of a program list that performs a block blank check in self programming mode is shown below START FlashBlockBlankCheck MOV FLCMD 04H MOV FLAPH 07H MOV FLAPL 00H MOV FLAPHC 07H MOV FLAPLC 0FFH MOV PFS 00H MOV WDTE 0ACH HALT MOV A PFS MOV CmdStatus A END 302 Sets flash control command block blank check Sets number of block for blank check block 7 is specified here Fixes FL
357. th using 16 bit timer counter 00 TMOO TM00 is incremented each time the valid edge specified by prescaler mode register 00 PRMOO is input When the TMOO count value matches the 16 bit timer capture compare register 000 CR000 value TMOO is cleared to 0 and the interrupt request signal INTTM000 is generated Input a value other than 0000H to CROOO A count operation with a pulse cannot be carried out The rising edge the falling edge or both edges can be selected using bits 4 and 5 ES000 and ES010 of prescaler mode register 00 PRMOO Because an operation is carried out only when the valid edge of the T1000 pin is detected twice after sampling with the internal clock fxe noise with a short pulse width can be removed Preliminary User s Manual U17446E 1VOUD 99 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 Figure 6 14 Control Register Settings in External Event Counter Mode with Rising Edge Specified a 16 bit timer mode control register 00 TMC00 4 TMC003 TMC002 TMC001 OVFOO Tuco LELE 1 orf b Capture compare control register 00 CRC00 Clears and starts on match between TMO0 and CROOO 3 CRC002 CRC001 CRC000 IESE RRR c Prescaler mode register 00 PRMO0 CRO000 used as compare register ES110 ES100 ES010 ES000 3 2 PRM001 PRM000 pawon for o i oo Selects external clock Specifies rising edge for pulse width detection Setting invalid setting 10 is proh
358. that all bits are 1 Preliminary User s Manual U17446EJ1VOUD 39 CHAPTER 3 CPU ARCHITECTURE 3 3 2 Immediate addressing Function Immediate data in the instruction word is transferred to the program counter PC to branch This function is carried out when the CALL addr16 and BR addr16 instructions are executed CALL addr16 and BR addr16 instructions can be used to branch to all the memory spaces Illustration In case of CALL addr16 and BR addr16 instructions 7 0 PC CALL or BR PCH Low Addr PC 2 High Addr 15 8 7 y 0 SS 3 3 3 Table indirect addressing Function The table contents branch destination address of the particular location to be addressed by the immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter PC to branch Table indirect addressing is carried out when the CALLT addr5 instruction is executed This instruction can be used to branch to all the memory spaces according to the address stored in the memory table 40H to 7FH Illustration 7 6 5 1 0 ronstencose D1 ee 1 8 7 6 5 10 5 Effective address 7 Memory Table 0 Low addr Effective address 1 High addr 15 8 7 0 PC 40 Preliminary User s Manual U17446EJ1VOUD CHAPTER 3 CPU ARCHITECTURE 3 3 4 Register addressing Function The register pair AX contents to be specified with an instruction word are transferred to the progra
359. the flash programming mode control register FLPMC may have a serious effect on the system PFCMD is used to protect FLPMC from being written so that the application system does not stop inadvertently Writing FLPMC is enabled only when a write operation is performed in the following specific sequence lt 1 gt Write a specific value to PFCMD A5H lt 2 gt Write the value to be set to FLPMC writing in this step is invalid lt 3 gt Write the inverted value of the value to be set to FLPMC writing in this step is invalid lt 4 gt Write the value to be set to FLPMC writing in this step is valid This rewrites the value of the register so that the register cannot be written illegally Occurrence of an illegal store operation can be checked by bit 0 FPRERR of the flash status register PFS A5H must be written to PFCMD each time the value of FLPMC is changed PFCMD can be set with an 8 bit memory manipulation instruction Reset signal generation makes PFCMD undefined Figure 19 13 Format of Flash Protect Command Register PFCMD Address FFAOQH After reset Undefined Ww Symbol 7 6 5 4 3 2 1 0 PFCMD REG7 REG6 REGS REG4 REG3 REG2 REG1 REGO Caution Disable interrupt servicing by setting MKO and MK to FFH and executing the DI instruction while the specific sequence is under execution Preliminary User s Manual U17446EJ1VOUD 285 CHAPTER 19 FLASH MEMORY 3 Flash status register PFS 286 If data is not written to the
360. the interrupt acknowledgment processing is performed Caution Interrupt requests will be held pending while the interrupt request flag registers 0 1 IFO IF1 or interrupt mask flag registers 0 1 MKO MK1 are being accessed Preliminary User s Manual U17446EJ1VOUD 231 CHAPTER 13 INTERRUPT FUNCTIONS 13 4 2 Multiple interrupt servicing Multiple interrupt servicing in which another interrupt is acknowledged while an interrupt is being serviced can be performed using a priority order system When two or more interrupts are generated at once interrupt servicing is performed according to the priority assigned to each interrupt request in advance see Table 13 1 Figure 13 10 Example of Multiple Interrupts Example 1 Multiple interrupts are acknowledged Main processing INTxx servicing INTyy servicing INTxx gt INTyy RETI RETI During interrupt INTxx servicing interrupt request INTyy is acknowledged and multiple interrupts are generated The El instruction is issued before each interrupt request acknowledgment and the interrupt request acknowledgment enable state is set Example 2 Multiple interrupts are not generated because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE 0 INTyy gt INTyy is held pending RETI INTxx gt IE 0 RETI Because interrupts are not enabled in interrupt INTxx servicing the El instruction is not issued interrupt request
361. the interrupt request flag of INTTM 000 TMIF 000 0 Enable the INTTM000 interrupt TMMK000 0 generated Remark n 0 1 If CRO10 is changed during timer counting without performing processing lt 1 gt above the value in CR010 may be rewritten twice or more causing an inversion of the output level of the TO00 pin at each rewrite Preliminary User s Manual U17446EJ 1VOUD CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 18 Edge detection lt l gt In the following cases note with caution that the valid edge of the TlOn0 pin is detected a Immediately after a system reset if a high level is input to the T10n0 pin the operation of the 16 bit timer counter 00 TMO0 is enabled gt If the rising edge or both rising and falling edges are specified as the valid edge of the TIOnO pin a rising edge is detected immediately after the TM00 operation is enabled If the TMOO operation is stopped while the TIOnO pin is high level TMOO operation is then enabled after a low level is input to the T10n0 pin If the falling edge or both rising and falling edges are specified as the valid edge of the T10n0 pin a falling edge is detected immediately after the TM00 operation is enabled c When the TMOO operation is stopped while the TIOnO pin is low level TMOO operation is then enabled after a high level is input to the TIOnO pin If the rising edge or both rising and falling edges are specified as the valid edge of the T10n0 pin a rising
362. thod Functional Outline Operation Mode On board programming Flash memory can be rewritten after the device is mounted on the Flash memory target system by using a dedicated flash programmer programming mode Off board programming Flash memory can be rewritten before the device is mounted on the target system by using a dedicated flash programmer and a dedicated program adapter board FA series Self programming Flash memory can be rewritten by executing a user program that has Self programming mode been written to the flash memory in advance by means of on board off board programming Remarks 1 The FA series is a product of Naito Densei Machida Mfg Co Ltd 2 Refer to the following sections for details on the flash memory writing control function e 19 7 On Board and Off Board Flash Memory Programming e 19 8 Flash Memory Programming by Self Writing 270 Preliminary User s Manual U17446EJ1VOUD CHAPTER 19 FLASH MEMORY 19 4 Writing with Flash Programmer The following two types of dedicated flash programmers can be used for writing data to the internal flash memory of the 78KOS KB1 e FlashPro4 PG FP4 FL PR4 e PG FPL2 Data can be written to the flash memory on board or off board by using a dedicated flash programmer 1 2 On board programming The contents of the flash memory can be rewritten after the 78KOS KB1 has been mounted on the target system The connectors that connect the dedicated fla
363. til bit 7 ADCS of the A D converter mode register ADM is reset 0 by software If a write operation is performed to ADM or the analog input channel specification register ADS during an A D conversion operation the conversion operation is initialized and if the ADCS bit is set 1 conversion starts again from the beginning Reset input makes the A D conversion result register ADCR ADCRH undefined 170 Preliminary User s Manual U17446EJ1VOUD CHAPTER 10 A D CONVERTER 10 4 2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins ANIO to ANI3 and the theoretical A D conversion result stored in the 10 bit A D conversion result register ADCR is shown by the following expression VAIN SAR INT AVREF x 1024 0 5 or ADCR 0 5 x E lt Va lt ADCR 0 5 x AREF 1024 1024 where INT Function which returns integer part of value in parentheses VAIN Analog input voltage AVrer AVreF pin voltage ADCR 10 bit A D conversion result register ADCR value SAR Successive approximation register Figure 10 11 shows the relationship between the analog input voltage and the A D conversion result Figure 10 11 Relationship Between Analog Input Voltage and A D Conversion Result SAR ADCR 1023 _ _ 03FFH 1022 E E e a 03FEH 1021
364. ting 1 and the INTST6 occurrence it triggers the SBF reception and SBF transmission again so do not set In the case of an SBF reception error return the mode to the SBF reception p 193 mode again and hold 1 the status of the SBRF6 flag Preliminary User s Manual U17446EJ1VOUD APPENDIX D LIST OF CAUTIONS Chapter 11 Soft Classification Function Serial interface UART6 Details of Function ASICL6 Asynchronous serial interface control register 6 Cautions Before setting the SBRT6 bit to 1 make sure that bit 7 POWERS and bit 5 RXE6 of ASIM6 1 Moreover after setting the SBRT6 bit to 1 do not clear the SBRT6 bit to 0 before the SBF reception ends an interrupt request signal is generated 12 18 The read value of the SBRT6 bit is always 0 SBRT6 is automatically cleared to 0 after SBF reception has been correctly completed Before setting the SBTT6 bit to 1 make sure that bit 7 POWER6 and bit 6 TXE6 of ASIM6 1 Moreover after setting the SBTT6 bit to 1 do not clear the SBTT6 bit to 0 before the SBF transmission ends an interrupt request signal is generated The read value of the SBTT6 bit is always 0 SBTT6 is automatically cleared to 0 at the end of SBF transmission Before rewriting the DIR6 and TXDLV6 bits clear the TXE6 and RXE6 bits to 0 Bits 7 6 and 5 POWER6 TXE6 and RXE6 of ASIM6 Clear POWER to 0 after cl
365. ting and operating statuses The STOP mode is set by executing the STOP instruction Caution Because an interrupt request signal is used to clear the standby mode if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset the standby mode is immediately cleared if set Thus in the STOP mode the normal operation mode is restored after the STOP instruction is executed and then the operation is stopped for 34 us TYP after an additional wait time for stabilizing the oscillation set by the oscillation stabilization time select register OSTS has elapsed when crystal ceramic oscillation is used The operating statuses in the STOP mode are shown below Table 14 4 Operating Statuses in STOP Mode Setting of HALT Mode Low S peed Ring OSC Can Be Stopped Low S peed Ring OSC Cannot Be Stopped When Low Speed Ring OSC Oscillation Continues When Low Speed Ring OSC Oscillation Stops System clock Oscillation stops CPU Operation stops Port latch Holds status before STOP mode is set 16 bit timer event counter 00 Operation stops 8 bit timer 80 Operation stops 8 bit timer Sets count clock to fxr to fxp 2 Operation stops H1 Sets count clock to fri 2 Operable Operable Operation stops Watchdog Clock to peripheral hardware timer selected as operating clock Setting prohibited Operation stops Low
366. ting the edge of the external interrupt INTPO The length of the synchronous field transmitted from the LIN master can be measured using the external event capture operation of 16 bit timer event counter 00 and the baud rate error can be calculated The input signal of the reception port input RxD6 can be input to the external interrupt INTPO and 16 bit timer event counter 00 by port input switch control ISCO ISC1 without connecting RxD6 and INTPO TIO00 externally Preliminary User s Manual U17446EJ1VOUD 181 CHAPTER 11 SERIAL INTERFACE UART6 Figure 11 3 Port Configuration for LIN Reception Operation Selector P44 RxD6 gt RXD6 input Port mode PM44 Output latch P44 Selector Selector P30 INTPO TI000 INTPO input Port mode PM30 Port input selection control ISCO Output latch P30 lt ISCO gt 0 Selects INTPO P30 1 Selects RxD6 P44 Selector T1000 input Port input selection control ISC1 lt ISC1 gt 0 Selects T1000 P30 1 Selects RxD6 P44 Remark ISCO ISC1 Bits 0 and 1 of the input switch control register ISC see Figure 11 11 The peripheral functions used in the LIN communication operation are shown below lt Peripheral functions used gt e External interrupt INTPO wakeup signal detection Use Detects the wakeup signal edges and detects start of communication e 16 bit timer event counter 00 T1000 baud rate error de
367. tion Ground Figure 19 4 Communication with PG FPL2 PG FPL2 signal name peona Lp aan GND EHEAAARAE 78K0S KB1 Preliminary User s Manual U17446EJ1VOUD 273 CHAPTER 19 FLASH MEMORY 19 6 Pin Connection on Board To write the flash memory on board connectors that connect the dedicated flash programmer must be provided on the target system First provide a function that selects the normal operation mode or flash memory programming mode on the board When the flash memory programming mode is set all the pins not used for programming the flash memory are in the same status as immediately after reset Therefore if the external device does not recognize the state immediately after reset the pins must be processed as described below The state of the pins in the self programming mode is the same as that in the HALT mode 19 6 1 X1 and X2 pins The X1 and X2 pins are used as the serial interface of flash memory programming Therefore if the X1 and X2 pins are connected to an external device a signal conflict occurs To prevent the conflict of signals isolate the connection with the external device Perform the following processing 1 and 2 when on board writing is performed with the resonator mounted when it is difficult to isolate the resonator while a crystal or ceramic resonator is selected as the system clock 1 Mount the minimum possible test pads between the device and the resonato
368. tion of 8 bit timer counter 80 clear TCE80 bit 7 of 8 bit timer mode control register 80 TMC80 to 0 lt 2 gt Set the count clock of 8 bit timer 80 refer to Tables 7 3 and 7 4 lt 3 gt Set the count value to CR80 lt 4 gt Enable the operation of TM80 set TCE80 to 1 When the count value of 8 bit timer counter 80 TM80 matches the set value of CR80 the value of TM80 is cleared to 00H and counting is continued At the same time an interrupt request signal INTTM80 is generated Tables 7 3 and 7 4 show the interval time and Figure 7 5 shows the timing of the interval timer operation Cautions 1 When changing the value of CR80 be sure to stop the timer operation If the value of CR80 is changed with the timer operation enabled a match interrupt request signal may be generated immediately 2 If the count clock of TMC80 is set and the operation of TM80 is enabled at the same time by using an 8 bit memory manipulation instruction the error of one cycle after the timer is started may be 1 clock or more Therefore be sure to follow the above sequence when using TM80 as an interval timer Table 7 3 Interval Time of 8 Bit Timer 80 fxe 8 0 MHz TCL801 TCL800 Minimum Interval Time Maximum Interval Time Resolution 2 fxp 8 us 2 fxe 2 05 ms 2 fxe 8 us 2 ifxe 32 us 2 fxe 8 19 ms 2 fxp 32 us 2 ifxe 128 us 2 fxe 32 7 ms 2 fxe 128 us 2 fxe 8 19 ms 2 4 fxp 2 01 s 2 fxp 8 19 ms
369. to Voo The signal input to ANIO to ANI3 is converted into a digital signal based on the voltage applied across AVrer and AVss 10 AVss pin This is the ground potential pin of the A D converter Always use this pin at the same potential as that of the Vss pin even when the A D converter is not used 11 A D converter mode register ADM This register is used to set the conversion time of the analog input signal to be converted and to start or stop the conversion operation 12 Analog input channel specification register ADS This register is used to specify the port that inputs the analog voltage to be converted into a digital signal 13 Port mode control register 2 PMC 2 This register is used when the P20 ANI0 to P23 ANI3 pins are used as the analog input pins of the A D converter 10 3 Registers Used by A D Converter The A D converter uses the following six registers e A D converter mode register ADM e Analog input channel specification register ADS e 10 bit A D conversion result register ADCR e 8 bit A D conversion result register ADCRH e Port mode control register 2 PMC2 e Port mode register 2 PM2 1 A D converter mode register ADM This register sets the conversion time for analog input to be A D converted and starts stops conversion ADM can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears this register to OOH 164 Preliminary User s Manual U17446EJ1VOUD
370. to clear bits 2 to 7 to 0 2 Before setting INTM1 set PMK3 to 1 to disable interrupts To enable interrupts clear PIF3 to 0 then clear PMK3 to 0 5 Program status word PSW The program status word is used to hold the instruction execution result and the current status of the interrupt requests The IE flag used to enable and disable maskable interrupts is mapped to PSW PSW can be read and write accessed in 8 bit units as well as using bit manipulation instructions and dedicated instructions El and DI When a vectored interrupt is acknowledged the PSW is automatically saved to a stack and the IE flag is reset to 0 Generation of reset signal sets PSW to 02H Figure 13 6 Program Status Word PSW Configuration Symbol 7 6 5 4 3 2 1 0 After reset 02H Used in the execution of ordinary instructions Whether to enable disable interrupt acknowledgment 0 Disabled 1 Enabled 228 Preliminary User s Manual U17446EJ1VOUD CHAPTER 13 INTERRUPT FUNCTIONS 13 4 Interrupt Servicing Operation 13 4 1 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0 A vectored interrupt request is acknowledged in the interrupt enabled status when the IE flag is set to 1 The time required to start the interrupt servicing after a maskable interrupt request has been generated
371. to digital values a 1 2LSB error naturally occurs In an A D converter an analog input voltage in a range of 1 2LSB is converted to the same digital code so a quantization error cannot be avoided Note that the quantization error is not included in the overall error zero scale error full scale error integral linearity error and differential linearity error in the characteristics table Figure 10 13 Overall Error Figure 10 14 Quantization Error 174 Preliminary User s Manual U17446EJ1VOUD CHAPTER 10 A D CONVERTER 5 Full scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value Full scale 3 2LSB when the digital output changes from 1 110 to 1 111 6 Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero scale error and full scale error are 0 7 Differential linearity error While the ideal width of code output is 1LSB this indicates the difference between the actual measurement value and the ideal value Figure 10 15 Zero Scale Error Figure 10 16 Full Scale Error 111 ge i aes Full scale error S Ideal line ge 09 5 Q o 111 SOW
372. to peripheral hardware The clock to the peripheral hardware is supplied by dividing the system clock fx The division ratio is selected by the pre processor clock control register PPCC Three types of frequencies are selectable fx fx 2 and f2 Table 5 3 lists the clocks supplied to the peripheral hardware Table 5 3 Clocks to Peripheral Hardware Selection of clock to peripheral hardware fxr fx fx 2 fx 2 Setting prohibited Low speed Ring OSC clock The low speed Ring OSC oscillator of the clock oscillator for interval time generation is always started after release of reset and oscillates at 240 kHz TYP It can be specified by the option byte whether the low speed Ring OSC oscillator can or cannot be stopped by software If it is specified that the low speed Ring OSC oscillator can be stopped by software oscillation can be started or stopped by using the low speed Ring OSC mode register LSRCM If it is specified that it cannot be stopped by software the clock source of WDT is fixed to the low speed Ring OSC clock frL The low speed Ring OSC oscillator is independent of the CPU clock If it is used as the source clock of WDT therefore a hang up can be detected even if the CPU clock is stopped If the low speed Ring OSC oscillator is used as a count clock source of 8 bit timer H1 8 bit timer H1 can operate even in the standby status Table 5 4 shows the operation status of the low
373. tor For details refer to CHAPTER 9 WATCHDOG TIMER LSRCM can be set by using a 1 bit or 8 bit memory manipulation instruction Generation of reset signal sets LSRCM to OOH Figure 5 4 Format of Low Speed Ring OSC Mode Register LSRCM Address FF58H After reset 00H R W Symbol 7 6 5 4 3 2 1 lt 0 gt LSRSTOP Oscillation stop of low speed Ring OSC Low speed Ring OSC oscillates Low speed Ring OSC stops Preliminary User s Manual U17446EJ1VOUD 73 CHAPTER 5 CLOCK GENERATORS 3 Oscillation stabilization time select register OSTS This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the STOP mode is released The wait time set by OSTS is valid only when the crystal ceramic oscillation clock is selected as the system clock and after the STOP mode is released If the high speed Ring OSC oscillator or external clock input is selected as the system clock source no wait time elapses The system clock oscillator and the oscillation stabilization time that elapses after power application or release of reset are selected by the option byte For details refer to CHAPTER 18 OPTION BYTE OSTS is set by using an 8 bit memory manipulation instruction Figure 5 5 Format of Oscillation Stabilization Time Select Register OSTS Address FFF4H After reset Undefined R W Symbol 7 6 5 4 3 2 1 0 Selection of oscillation stabilization time 2 fx 102 4 us 2 fx 409 6
374. tus remains unchanged Once data is written to the output latch it is retained until new data is written to the output latch Reset signal generation clears the data in the output latch 4 4 2 Reading from I O port 1 In output mode The contents of the output latch can be read by a transfer instruction The contents of the output latch remain unchanged 2 In input mode The pin status can be read by a transfer instruction The contents of the output latch remain unchanged 4 4 3 Operations on I O port 1 In output mode An operation is performed on the contents of the output latch and the result is written to the output latch The contents of the output latch are output from the pin Once data is written to the output latch it is retained until new data is written to the output latch Reset signal generation clears the data in the output latch 2 In input mode The pin level is read and an operation is performed on its contents The operation result is written to the output latch However the pin status remains unchanged because the output buffer is off Reset signal generation clears the data in the output latch 68 Preliminary User s Manual U17446EJ1VOUD CHAPTER 5 CLOCK GENERATORS 5 1 Functions of Clock Generators The clock generators include a circuit that generates a clock system clock to be supplied to the CPU and peripheral hardware and a circuit that generates a clock interval time generation clock to be supplied to
375. uction Generation of reset signal sets this register to 01H Address FF90H After reset 01H R W Symbol lt 7 gt lt 6 gt lt 5 gt 4 3 2 1 0 ASIM6 POWER6 TXE6 RXE6 PS61 PS60 ISRM6 POWER6 Enabling disabling operation of internal operation clock Disable operation of the internal operation clock fix the clock to low level and asynchronously reset the internal circuit TXE6 Enabling disabling transmission oo Disable transmission operation synchronously reset the transmission circuit RXE6 Enabling disabling reception oo Disable reception synchronously reset the reception circuit Notes 1 The output of the TxD6 pin goes high and the input from the RxD6 pin is fixed to high level when POWER6 0 during a transmission 2 Asynchronous serial interface reception error status register 6 ASIS6 asynchronous serial interface transmission status register 6 ASIF6 bit 7 SBRF6 and bit 6 SBRT6 of asynchronous serial interface control register 6 ASICL6 and receive buffer register 6 RXB6 are reset Caution Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to set the operation stop mode To start the operation set POWER6 to 1 and then set TXE6 and RXE6 to 1 Remark To use the RxD6 P44 and TxD6 INTP1 P43 pins as general purpose port pins see CHAPTER 4 PORT FUNCTIONS Preliminary User s Manual U17446EJ1VOUD 195 CHAPTER 11 SERIAL INTERFACE UART6 11 4 2 Asynchronous serial interface UART mode In thi
376. ues are ignored 2 After reset is released WDTM can be written only once by an 8 bit memory manipulation instruction If writing is attempted a second time an internal reset signal is generated 3 WDTM cannot be set by a 1 bit memory manipulation instruction 4 When using the flash memory self programming by self writing set the overflow time for the watchdog timer so that enough everflow time is secured Example 1 byte writing 200 ws MIN 1 block deletion 10 ms MIN Remarks 1 fR Low speed Ring OSC clock oscillation frequency 2 fx System clock oscillation frequency 3 x Don t care 4 Figures in parentheses apply to operation at fr 480 kHz MAX fx 10 MHz 2 Watchdog timer enable register WDTE Writing ACH to WDTE clears the watchdog timer counter and starts counting again This register can be set by an 8 bit memory manipulation instruction Generation of reset signal sets this register to 9AH Figure 9 3 Format of Watchdog Timer Enable Register WDTE Address FF49H After reset 9AH R W Symbol 7 6 5 4 3 2 1 0 Cautions 1 If a value other than ACH is written to WDTE an internal reset signal is generated 2 If a 1 bit memory manipulation instruction is executed for WDTE an internal reset signal is generated 3 The value read from WDTE is 9AH this differs from the written value ACH 152 Preliminary User s Manual U17446EJ1VOUD CHAPTER 9 WATCHDOG TIMER 9 4 Operation of Watchdog Timer 9 4 1 Watchd
377. unter 80 Wa oO e fxe 210 5 TMB0 fxp 216 TCE80 TCL801 TCL800 8 bit timer mode control register 80 TMC80 Internal bus ab Remark fxr Oscillation frequency of clock to peripheral hardware Preliminary User s Manual U17446EJ1VOUD 127 CHAPTER 7 8 BIT TIMER 80 1 2 128 8 bit compare register 80 CR80 This 8 bit register always compares its set value with the count value of 8 bit timer counter 80 TM80 It generates an interrupt request signal INTTM80 if the two values match CR80 is set by using an 8 bit memory manipulation instruction A value of OOH to FFH can be set to this register Reset signal generation makes the contents of this register undefined Figure 7 2 Format of 8 Bit Compare Register 80 CR80 Address FFCDH After reset Undefined WwW Symbol 7 6 5 4 3 2 1 0 Caution When changing the value of CR80 be sure to stop the timer operation If the value of CR80 is changed with the timer operation enabled a match interrupt request signal may be generated immediately 8 bit timer counter 80 TM80 This 8 bit register counts the count pulses The value of TM80 can be read by using an 8 bit memory manipulation instruction Reset signal generation clears TM80 to OOH Figure 7 3 Format of 8 Bit Timer Counter 80 TM80 Address FFCEH After reset 00H R Symbol 7 6 5 4 3 2 1 0 Preliminary User s Manual U17446EJ1VOUD CHAPTER 7 8 BIT TIMER
378. unter H1 by masking one count clock to count up At this time TOH1 output remains inactive when TOLEV1 0 lt 2 gt When the values of 8 bit timer counter H1 and the CMP01 register match the TOH1 output level is inverted the value of 8 bit timer counter H1 is cleared and the INTTMH1 signal is output lt 3 gt When the values of 8 bit timer counter H1 and the CMP11 register match the level of the TOH1 output is returned At this time the 8 bit timer counter value is not cleared and the INTTMH1 signal is not output lt 4 gt Clearing the TMHE1 bit to O during timer H1 operation makes the INTTMH1 signal and TOH1 output inactive 144 Preliminary User s Manual U17446EJ1VOUD CHAPTER 8 8 BIT TIMER H1 Figure 8 9 Operation Timing in PWM Output Mode 2 4 00H JUUUULIQUUULIUUL 8 bit timer counter H1 00H Kor FFH CMP11 b Operation when CMPO1 2200 FEH FFHAOOH OTH c Operation when CMPO1 pe y Ne LI TT ag A TEN eg a el iji I che i iM Count clock onor A s 7 YT ou T 5 5 L oO I Ss Fro z gt O gt S O O zZ uu fo m Q Ee o B a foe 0 TOLEV1 145 Preliminary User s Manual U17446EJ1VOUD CHAPTER 8 8 BIT TIMER H1 Figure 8 9 Operation Timing in PWM Output Mode 3 4 00H 01H CMP11 d Operation when CMPO1 Count clock CMP01 CMP11 TMHE1 INTTMH1 0 TOLEV1 Preliminary User s Manual U17446EJ1
379. ure compare registers 000 and 010 CR000 and CRO10 to 0000H 13 Operation of OVFOO flag lt l gt The OVF00 flag is also set to 1 in the following case Either of the clear amp start mode entered on a match between TMO00 and CR 000 clear amp start at the valid edge of the T1000 pin or free running mode is selected CR0O00 is setto FFFFH When TM0O0 is counted up from FFFFH to 0000H Figure 6 37 Operation Timing of OVF00 Flag Count clock l CR000 FFFFH i TM0O FFFEH X FFFFH X 0000H X 0001H X i OVF00 INTTMO00 lt 2 gt Even if the OVF0O0 flag is cleared before the next count clock is counted before TM00 becomes 0001H after the occurrence of a TM0O0 overflow the OVF00 flag is re set newly and clear is disabled 122 Preliminary User s Manual U17446EJ 1VOUD CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 14 Conflicting operations If the register read period and the input of the capture trigger conflict when CRO00 CRO1O0 is used as a capture register the capture trigger input takes precedence and the read data is undefined Also if the count stop of the timer and the input of the capture trigger conflict the captured data is undefined Figure 6 38 Capture Register Data Retention Timing Count clock tuoo countvaue X_N Nat Kwe2X K m Xma Xm Edge input INTTMO10 Capture read signal CR010 capture value i po p Capture Capture but read va
380. us 2 fx 3 27 ms 2 fx 13 1 ms Cautions 1 To set and then release the STOP mode set the oscillation stabilization time as follows Expected oscillation stabilization time of resonator lt Oscillation stabilization time set by OSTS 2 The wait time after the STOP mode is released does not include the time from the release of the STOP mode to the start of clock oscillation a in the figure below regardless of whether STOP mode was released by reset signal generation or interrupt generation STOP mode is released as Caution 3 The oscillation stabilization time that elapses on power application or after release of reset is selected by the option byte For details refer to CHAPTER 18 OPTION BYTE Voltage waveform of X1 pin Remarks 1 fx 10 MHz 2 Determine the oscillation stabilization time of the resonator by checking the characteristics of the resonator to be used 74 Preliminary User s Manual U17446EJ1VOUD CHAPTER 5 CLOCK GENERATORS 5 4 System Clock Oscillators The following three types of system clock oscillators are available e High speed Ring OSC oscillator Internally oscillates a clock of 8 MHz TYP e Crystal ceramic oscillator Oscillates a clock of 1 to 10 MHz e External clock input circuit Supplies a clock of 1 to 10 MHz to the X1 pin 5 4 1 High speed Ring OSC oscillator The 78KO0S KB1 includes a high speed Ring OSC oscillator 8 MHz TYP If the high speed Rin
381. value of the blank data set during block erasure is FFH When the oscillator or the external clock is selected as the main clock a wait time of 16 ws is required starting from the setting of the self programming mode to the execution of the HALT instruction The state of the pins in self programming mode is the same as that in HALT mode Since the security function set via on board off board programming is disabled in self programming mode the self programming command can be executed regardless of the security function setting To disable write or erase processing during self programming set the protect byte Be sure to clear bits 4 to 7 of flash address pointer H FLAPH and flash address pointer H compare register FLAPHC to 0 before executing the self programming command If the value of these bits is 1 when executing the self programming command 19 8 3 Registers used for self programming function The following registers are used for the self programming function Flash programming mode control register FLPMC Flash protect command register PFCMD Flash status register PFS Flash programming command register FLCMD Flash address pointers H and L FLAPH and FLAPL Flash address pointer H compare register and flash address pointer L compare register FLAPHC and FLAPLC Flash write buffer register FLW The 78K0S KB1 has an area called a protect byte at address 0081H of the flash memory 1 Flash programming mode control regis
382. ventecervedienedestee cestveneesesveiuteeresives 75 5 4 1 High speed Ring OSC oscillator oo eee ceeeeeeeeeeeeeeeneeeeeeaeeeeeeeaeeeeeeeeeeenaeeeseeaeeesnneeeeeeenaeeeeneas 75 5 4 2 Crystal ceramic OSCillator ivcst 2c csezy esete a a a apa Vues cdeeaendy sag era E Taa NES 75 5 4 3 External clock input circuit 2 s2 120 tecceececeeecge eaii ie ieia aeda dakini diadusi iiine 77 5 4 4 PreSCaller EAEN E EE E EE E E be EEE E E E ves det ae 77 5 5 Operation of CPU Clock Generator ssssssssusnssssnnnnnnunnnnnnnnnnunnnnnnnnnnnunnnnnnnnnnnnnnnnnnnnnn nnmnnn enmana 78 5 6 Operation of Clock Generator Supplying Clock to Peripheral Hardware 00008 83 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 00 cccccceeeeee cece ee eeeeeeeeee sees eesensseaeeeeeeeeeeseeeensneeees 85 6 1 Functions of 16 Bit Timer Event Counter 00 cccceeceeeeeeeeeeeeeeeeeeeeeeseeeeeseeeseeeeeseeaeeeeeeeens 85 6 2 Configuration of 16 Bit Timer Event Counter 00 cssscccesssseeceeeseeeeeeeseeeeeeeseenseeeeseeneeeeseaes 86 6 3 Registers to Control 16 Bit Timer Event Counter 00 ccessscesesseeeeeeeeeeeeeeseeeeseseseeneeeeseees 90 6 4 Operation of 16 Bit Timer Event Counter 00 cccccceceeeeeseeeeee cece eeeeeeseeeeeeeeeseeeeeseaneeeeeeens 96 6 4 1 Interval timer Operation s00 cecil eee eee deen eee te E AEEA aie ieee 96 6 4 2 External event counter Operation iiio tiniee eieiei a a a ains 99 6 4 3 Pulse width measu
383. voltage is used to perform sufficient sampling it is recommended to make the output impedance of the analog input source 1 kQ or lower or attach a capacitor of around 0 01 uF to 0 1 uF to the ANIO to ANI3 pins see Figure 10 19 Interrupt request flag ADIF The interrupt request flag ADIF is not cleared even if the analog input channel specification register ADS is changed Therefore if an analog input pin is changed during A D conversion the A D conversion result and ADIF for the pre change analog input may be set just before the ADS rewrite Caution is therefore required since at this time when ADIF is read immediately after the ADS rewrite ADIF is set despite the fact A D conversion for the post change analog input has not ended When A D conversion is stopped and then resumed clear ADIF before the A D conversion operation is resumed Figure 10 20 Timing of A D Conversion End Interrupt Request Generation ADS rewrite ADS rewrite ADIF is set but ANIm conversion start of ANIn conversion start of ANIm conversion has not ended A D conversion ADCR ADCRH Remarks 1 n 0to3 2 m 0to3 Preliminary User s Manual U17446EJ1VOUD 177 CHAPTER 10 A D CONVERTER 8 Conversion results just after A D conversion start The first A D conversion value immediately after A D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1 ws after the ADCE bit was set to 1 or if the ADCS bit is set
384. w e Bit 9 1 3 4 AVREF e Bit 9 0 1 4 AVRer The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows e Analog input voltage Voltage tap Bit 8 1 e Analog input voltage lt Voltage tap Bit 8 0 Comparison is continued in this way up to bit 0 of SAR Upon completion of the comparison of 10 bits an effective digital result value remains in SAR and the result value is transferred to the A D conversion result register ADCR ADCRH and then latched At the same time the A D conversion end interrupt request INTAD can also be generated Repeat steps lt 5 gt to lt 11 gt until ADCS is cleared to 0 To stop the A D converter clear ADCS to 0 To restart A D conversion from the status of ADCE 1 start from lt 3 gt To restart A D conversion from the status of ADCE 0 however start from lt 2 gt Remark The following two types of A D conversion result registers can be used lt 1 gt ADCR 16 bits Stores a 10 bit A D conversion value lt 2 gt ADCRH 8 bits Stores an 8 bit A D conversion value Preliminary User s Manual U17446EJ1VOUD 169 CHAPTER 10 A D CONVERTER Figure 10 10 Basic Operation of A D Converter I Conversion time Sampling time A D converter A Sampling A D conversion operation Conversion result SAR Undefined ADCR Conversion ADCRH result INTAD A D conversion operations are performed continuously un
385. when it is used as a capture trigger In the former case the count clock is fxr and in the latter case the count clock is selected by prescaler mode register 00 PRMO0 The capture operation is not performed until the valid edge is sampled and the valid level is detected twice thus eliminating noise with a short pulse width 5 When using P31 as the input pin T1010 of the valid edge it cannot be used as a timer output TO00 When using P31 as the timer output pin TO00 it cannot be used as the input pin T1010 of the valid edge Remark n 0 1 5 Port mode register 3 PM3 This register sets port 3 input output in 1 bit units When using the P31 TO00 TIO10 INTP 2 pin for timer output set PM31 and the output latch of P31 to 0 When using the P30 TIOOO INTPO and P31 TO00 TIO10 INTP2 pins as a timer input set PM30 and PM31 to 1 At this time the output latches of P30 and P31 can be either 0 or 1 PM3 is set by a 1 bit or 8 bit memory manipulation instruction Generation of reset signal sets the value of PM3 to FFH Figure 6 9 Format of Port Mode Register 3 PM3 Address FF23H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM3 1 1 pws PM32 PM31 PM30 P3n pin I O mode selection n 0 to 3 Output mode output buffer on Input mode output buffer off Preliminary User s Manual U17446EJ 1VOUD 95 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 6 4 Operation of 16 Bit Timer Event Counter 00 6 4 1 Interval timer o
386. y occur immediately after the processing in lt 3 gt If supply voltage VDD detection voltage VLv1 when LVIM is set to 1 an internal reset signal is not generated Cautions for low voltage detector In a system where the supply voltage Vpop fluctuates for a certain period in the vicinity of the LVI detection voltage VLv the operation is as follows depending on how the low voltage detector is used lt 1 gt When used as reset The system may be repeatedly reset and released from the reset status In this case the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action 1 below lt 2 gt When used as interrupt Interrupt requests may be frequently generated Take action 2 below Chapter 18 Low speed Ring OSC clock If it is selected that low speed Ring OSC clock oscillation cannot be stopped the count clock to the watchdog timer WDT is fixed to low speed Ring OSC oscillation If it is selected that low speed Ring OSC can be stopped by software supply of the count clock to WDT is stopped in the HALT STOP mode regardless of the setting of bit O LSRSTOP of the low speed Ring OSC mode register LSRCM Similarly clock supply is also stopped when a clock other than the low speed Ring OSC is selected as a count clock to WDT If low speed Ring OSC is selected as the count clock to 8 bit timer H1 however th

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