Implementing the TERIDIAN 73S8024RN in NDS Applications
Contents
1. SEMICONDUCTOR CORP 73S8024RN A Maxim Integrated Products Brand Low Cost Smart Card Interface IC Application Note Note AN_8024RN_001 April 2007 Implementing the Teridian 73S8024RN in NDS Applications 1 Introduction This application note highlights particular design considerations required to implement Conditional Access smart card interfaces in compliance with the NDS specification LC T056I when using the TERIDIAN 73S8024RN integrated circuit This note details in particular the design constraints related to the PCB layout and external components choice and placement and the typical tests that should be performed prior to submitting an application to NDS certification testing Reference document is the IRD Interface Specifications for Use with NDS Smart Cards NDS document referenced LC T056 Rev I 2 Demo Board The data and chart measurements presented herein have been measured on a TERIDIAN 73S8024RN Demonstration Board modified to meet NDS LC T0O56I requirements Refer to the 73S8024RN Demo Board User s Manual for general information about this board Note that the electrical schematic of this board is by default designed to meet compliance with EMV4 0 specification As a result there are some minor differences between both electrical schematics The TERIDIAN 73S8024RN configuration does not install components L1 C6 and C7 Other component differences are described in this note and the NDS compliant electrical s2. C2 Duty 50 0 External Clock 1 16 Y 21 Apr 2004 10 08 38 Ch3 2 00 VQ 20MHz crystal source at 5V 73S8024RN Low Cost Smart Card Interface IC Application Note AN_8024RN_001 20MHz external clock source at 5V Page 7 2007 TERIDIAN Semiconductor Corporation Rev 1 2 SS 73S8024RN A Maxim Integrated Products Brand Low Cost Smart Card Interface IC Application Note AN_8024RN_001 3 5 Crystal Load Capacitors In order to insure the proper operation of the crystal oscillator circuit the crystal load capacitors must be chosen appropriately The crystal load capacitance C as specified by the crystal manufacturer must equal the series load capacitance Cp plus the stray board capacitance Cs CL Cs Cp Where Cp 1 1 C1 1 C2 C1 and C2 are the load capacitors If a balanced crystal load capacitors are used recommended then C1 C2 and Cp C1 2 If CL 20 pF from the crystal mfr spec and the stray capacitance is assumed to be 5 0 pF then C1 2 C Cs 2 20pF 5pF 30pF Note If the loading is any higher then the oscillator circuit may not generate the output clock properly As a result it is not recommended to use this oscillator circuit to drive any other circuitry 3 6 VCC Output The 73S8024RN Demo Board is configured with 2 output capacitors on the Vcc output C9 and C11 A typical NDS implementation only requires 1 capacitor C9 is not necessary and the value o
3. Products Brand Low Cost Smart Card Interface IC Application Note AN_8024RN_001 Figure 3 6 External resistor divider for setting Vpptn In order to set the new threshold voltage the equivalent resistance must be determined This resistance value will be designated K which is defined as R3 R1 R3 and is calculated as K 2 789 Vu 0 6125 where Vu is the desired new threshold voltage To determine the values of R1 and R3 use the following formulas R1 24000 K R3 R1 K 1 K Taking the example above where a Vpp fault threshold voltage of 2 7V is desired solving for K gives gt K 2 789 2 7 0 6125 0 42046 Solving for R1 gives gt R1 24000 0 42046 57080 Solving for R3 gives gt R3 57080 0 42046 1 0 42046 41412 Using standard 1 resistor values gives R1 57 6KQ and R3 42 4KQ These values give an equivalent resistance of K 0 4228 a 0 6 error If the 2 3V default threshold is acceptable this pin must be left unconnected 2007 TERIDIAN Semiconductor Corporation Rev 1 2
4. the 100us requirement Tek AS t 1 Acqs VCC w 0 47uF 500V hi20 0us Chi Z 2V 18 Sep 2003 1 00 V2 08 11 07 08 17 19 Figure 3 4 Deactivation time 0 47uF VCC Figure 3 5 Deactivation time 1 47uF VCC 3 Power Supply Threshold Detection The 73S8024RN contains 3 different voltage supervisors They monitor the voltages on Vpc Vcc and Vpp Any voltage drop on any of these 3 signals is immediately detected and it initiates an automated card deactivation sequence that protects the card Vpc and Vcc threshold voltages also called fault voltages are internally set The voltage threshold of the Vpp voltage supervisor is internally set by default to 2 3V nominal However it may be desirable in some applications to modify this threshold value For instance when using a host controller that has a voltage operating range of 2 7V to 3 6V the 73S8024RN will be by default still expecting the host to be able to exchange information with him whereas the host is actually powered down In such a case the Vpp fault threshold voltage should be set to 2 7V to automatically deactivate the smart card at the same time that the host is down The pin VDDF_ADJ is used to connect an external resistor divider between VDD and GND to modify VDD Fault Figure 3 12 shows the connection of the external resistors V pp R1 73S8024R VDDF_ADJ R3 2007 TERIDIAN Semiconductor Corporation Rev 1 2 SS 73S8024RN A Maxim Integrated
5. up identically for all configurations Typical NDS Conditional Access applications require card clock frequencies of 4 5MHz 6 75MHz and 13 5MHz to be supported The same hardware configuration is required for both Class A and Class B 5V and 3V smart card operation The NDS specification also requires the card clock duty cycle to be in the range 45 to 55 3 4 3 73S8024RN Operational Configuration The typical NDS card clock frequencies of 4 5 6 75 and 13 5MHz are derived from the maximum frequency of 13 5MHz divided by 1 2 and 3 13 5 6 75 and 4 5 The 73S8024R supports a divide by 1 2 4 and 8 internal clock divider but not divide by 3 As a result a crystal that is used with the oscillator circuit will not be able to generate all three frequencies If all three frequencies are required then an external clock source must be provided to generate them If the clock divider rates of 1 2 4 and 8 are acceptable for a particular application then a crystal may be used Generation of the smart card clock signal CLK at the above mentioned three NDS frequencies can be done in one of two ways as long as the frequency of the signal applied on XTALIN is stable and doesn t exceed 27MHz The first way uses the NDS clock frequencies of 4 5 6 75 and 13 5 input directly to the 8024RN using the divide by one divider The second way is to use of an external clock source that provides frequencies of 9 13 5 and 2 MHz When the divide by 2 clock divider is con
6. 73S8024RN for NDS Applications Page 2 2007 TERIDIAN Semiconductor Corporation Rev 1 2 NRA CORP 7398024RN A Maxim Integrated Products Brand Low Cost Smart Card Interface IC Application Note AN_8024RN_001 POB Foot pri nt Item Quantity Reference Part see attached zip Digikey part number Part number Manufactuer 2 1 pon moa 6o 41s221 ND c1eo8x5Rosiosk Tok 8 2 jcace tr 603 445 1317 1 ND_ C1608X7R1C104Kk TDK 4 1 5 Smart Card Connector ITT_CCM02 2504 __ccm02 2504 ND__ __ccm02 2504 T _ITTCannon 7358024RN 2850P 7358024RN TERIDIAN Table 3 1 BOM for NDS compliant configuration 2007 TERIDIAN Semiconductor Corporation Rev 1 2 SS 73S8024RN A Maxim Integrated Products Brand Low Cost Smart Card Interface IC Application Note AN_8024RN_001 3 2 Power Supply 3 2 1 Analog Power Supply Vpc The 73S8024RN incorporates a Low Drop Out voltage regulator to generate the card power supply Voc The VPC pin is the power supply input of this regulator and the correct Vpc voltage must be asserted on this pin in order to ensure proper generation of Vcc to the card Depending on the card voltage required the Vpc power supply input can eventually be different as follows Power supply Vpc to support both 3V and 5V smart cards Vpc must be 5V nominal and the following condition must be respected 4 85V lt Vpc lt 5 5V Decoupling and PCB Layout The 73S8024R Demo Board and the
7. chematic is described in the Figure 3 1 Note that the 73S8024RN Demo Board is available Contact your TERIDIAN Semiconductor representative for further information concerning its availability 3 Design Guide 3 1 Typical Electrical Schematic and Bill of Materials The electrical schematic recommended for a typical NDS LC T056I compliant smart card interface implementation is given in Figure 3 1 and its corresponding Bill of Materials is in Table 3 1 The jumpers represent the different configuration options for use with the 738S8024RN and components references correspond to the Demo Board references 2007 TERIDIAN Semiconductor Corporation Rev 1 2 AN 8024R NDS Conformance SCLK SIO SC 4 Values are set for i VDD fault SC 8 threshold of 2 7V OFFB INTB See section 3 7 If 2 3V threshold is acceptable i don t install RI 5V See section 3 2 1 C1 10uF PGND a R3 S i 4 i VDD GND C2 0 1uF R1 O C1 and C2 must be placed within z 57 6k 5mm of the Ul pins and connected VDD by thick track wider than 0 5mm 3 3V R3 42 2k CLKDIV1 SADO AUX2UC CLKDIV2 SAD1 Ou y 5V3VB SAD2 vee CLKSTOP CLKLVL pn CMDVCCB 0 1uF RSTIN System Interface NZ VoD H a a S Note R4 should be R4 added for increased noise immunity 20k C11 1 0uF K g NZ SW1 and SW2 are Normally Closed J5 Smart Card Connector Figure 3 1 Typical Schematic using the
8. f C11 must be 1uF 50 lf fitting the 1uF capacitor into an existing application is problematic both C9 and C11 can be populated with 0 47uF 50 capacitors This capacitor should be placed as close to the card connector This Vcc output configuration meets the NDS specifications for both voltage and current consisting of constant and dynamic loads The ripple is shown to be less than 35 mV for DC loads and less than 60 mV for dynamic loads typical Figures 3 2 and 3 3 show Vcc ripple for 5V and 3V interfaces respectively Tek inai z 76 Acqs giiez 70 Acqs amp 4 A 648mV gt s s A 648mvV 4 648 V 2 648 V C3 Pk Pk C3 Pk Pk 2mv 32mv C3 Mean C3 Mean 4 8952V 2 9380 V C3 Max C3 Max 4 912 V 2 952 V C3 Min C3 Min 4 880 V 2 920 V M2 18 Sep 2003 2 18 Sep 2003 200MVQ Ch4 10 0mva oae 200mVQ Ch4 10 0MVQ ea Figure 3 2 C11 5V w 65mA dc load current Figure 3 3 C11 3V w 65mA dc load current 2007 TERIDIAN Semiconductor Corporation Rev 1 2 SS 73S8024RN A Maxim Integrated Products Brand Low Cost Smart Card Interface IC Application Note AN_8024RN_001 According to NDS LC T056l specification deactivation time for Vcc must be less than 100us Figures 3 4 and 3 5 show actual measurements carried out on the 73S8024RN Demo Board using capacitor values of 0 47uF and 1 47uF for Vcc output decoupling C11 The deactivation time is less than 80us It demonstrates that C11 1uF 50 allows the 73S8024RN to meet
9. figured the NDS operational frequencies of 4 5 6 75 and 13 5MHz are output to the smart card For applications that require higher smart card clock frequencies the maximum external input clock crystal speed is 27MHz Between 20 and 2 7MHz the divide by 1 clock divider is not recommended In order to get smart card frequencies up to 20MHz use the divide by 1 divider for either the crystal oscillator or external clock input The following scope capture diagrams show the smart card CLK for each configuration running at 2OMHz 2007 TERIDIAN Semiconductor Corporation Rev 1 2 sy USEE SEMICONDUCTOR CORP A Maxim Integrated Products Brand Tek 2 00GS 5 l 306 Acqs 1 T E nnn T 1 C3 Freq 1 20 0008MHz C3 Duty 50 0 M12 5ns Cha 1 15V 21 Apr 2004 soomv 10 13 03 Tek Bij 2 00GS s l 40 Acqs 1 Laren T C3 Freq 1 20 0000MHz CLK 3 Duty 50 0 C2 Duty 50 0 1 External Clock WE 1 00 YQ 10 10 46 20MHz crystal clock source at 3V 73S8024RN Low Cost Smart Card Interface IC Application Note AN_8024RN_001 20MHz external clock source at 3V Page 6 2007 TERIDIAN Semiconductor Corporation Rev 1 2 sy USEE SEMICONDUCTOR CORP A Maxim Integrated Products Brand Tek HJA 2 00GS s L Acqs EE SEE Guid F 3 Freq 1 20 0016MHz C3 Duty 50 0 i M12 5ns RT J 1 16V 21 Apr 2004 SE 1 00 Y 10 17 13 Tek 2 00GS 5 238 Acqs 1 Lar T 1 C3 Freq 1 20 0004MHz CLK C3 Duty 50 1
10. recommended Electrical Schematic has 2 decoupling capacitors on Vpc The larger capacitor is 10 uF and the small capacitor is 0 1uF respectively C1 and C2 The smaller capacitor should be placed very close to the 73S8024RN Vpc should be routed on a plane for best results If no plane is possible the larger capacitor should be as close as possible to the 73S8024RN 3 2 2 Digital Power Supply The 73S8024RN has a separate power supply input Vpp that powers the internal digital circuitry Vpp is also the reference voltage to interface with the host microcontroller Operating Vpp voltage for implementing the 73S8024RN in NDS applications is 2 7V lt Vpp lt 5 5V 3 3 Operating Temperature The operating temperature range for implementing the 73S8024RN in NDS applications is between 40 C and 85 C 2007 TERIDIAN Semiconductor Corporation Rev 1 2 SS 73S8024RN A Maxim Integrated Products Brand Low Cost Smart Card Interface IC Application Note AN_8024RN_001 3 4 Generation of the Smart Card Clock CLK Signal 3 4 1 General The 73S8024RN provides an oscillator that can generate a clock signal from an external crystal connected to the pins XTALIN and XTALOUT Alternatively it can also accept an external clock signal presented on the XTALIN pin When the external clock signal is used XTALOUT must be left unconnected 3 4 2 NDS Adherence In order to use the 73S8024RN and meet full NDS compliance typical hardware must be set
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