5 Key Steps To Design A Compact, High‐Efficiency PFC Stage
Contents
1. FF line eg 37 FF 5 2 Vine ms BOH The PFC stage operates in critical conduction mode no frequency reduction when Vpp exceeds 2 5 V that is as long as the instantaneous line current is higher than 25 2 Viine rms BOH 112 R L If as specified we want to start to reduce the frequency when the line current goes below 450 mA resistor RFF must be eq 38 hine tn R a 25 2 g Vine rms BOH Z FF 112 450 10 L eq 39 _ 252 77 5 112 450 103 200 10 It may be more convenient to express this threshold as a percentage of the maximal line current which is given by gz na Z 2674 He max Vin rms LL 272 kQ I eq 40 With a 270 kQ resistor the circuit starts to reduce the frequency when the line current is about 17 of its maximum value The minimum 20 kHz operation will be obtained when the FFcontrol pin voltage is about 0 75 V nominal At that point the current is 17 x 0 75 2 5 or 5 of its maximum value Below this level the circuit enters skip mode Remark A filtering capacitor Cpp is recommended between pin3 and ground to protect the pin from possible surrounding noise In a typical application it must be small however not to distort the voltage sensed by pin 2 Practically the time constant it forms together with the sensing resistors must remain lower than the line period divided by 150 Tine 1 150 150 fine that is less than 150 us in 50 Hz line2. gt Np en CL pos 2 8 Detection ZCD Va a 5 mA _ OCP Current R 25 2 Vine rms BOH Controlled FF 112 L linelin Frequency 1 Fold back Ce or FF 150 fine Ree leg is the bias current that is targeted within the resistor divider Values in the range of 50 uA to 100 uA generally give a good trade off between losses and noise immunity Cpg is the filtering capacitor that can be placed between the FB pin and ground to increase the noise immunity of this pin Ry is the resistance of the X2 capacitors discharge resistors Rx and Rx according to Figure 5 Viine rms boH line rms level above which the circuit starts operating VpoxH is an internal 1 V reference Viine rms LL is the line rms voltage lowest level in normal condition e g 90 V Vout nom IS the output nominal level e g 390 V Pin avg max IS the maximum input power of your application Placed between Rcs and the CS ZCD pin resistor Rocp must be greater than 3 9 kQ but not too high for noise immunity Generally resistors in the range of 5 kQ give good results liine th is the line current level below which the NCP1611 starts to reduce the frequency http onsemi com 11 AND9062 D Detailed Schematic for our 160 W Universal Mains Application U1 GBU606 Rth1 B57153S150M C4 220 nF Type X2 R2 1000 kQ R1 1000 kQ C1 D3 1nF lt IPA50R250 Type Y2 1N4148
3. with the feedback resistors must remain at a very high frequency compared to the line one Practically lt 1 150 Ror R p2 fine generally give good results Cp A type 2 compensation network Consisting of two capacitors and of one resistor this circuitry sets the crossover frequency and the loop characteristic In steady state the feedback being in the range of the 2 5 V regulation reference voltage the feedback bottom resistor R 2 of Figure 1 or R11 of Figure 7 sets the bias current in the feedback resistors as follows _ Veer _ 25 eq 16 R p2 R p2 leg Trade off between losses and noise immunity dictates the choice of this resistor Resistors up to 56 KQ Ifg 50 uA generally give good results Higher values can be considered if allowed by the board PCB layout Please note anyway that a 250 nA sink current 500 nA max on the 40 C to 125 C temperature range is built in to ground the feedback pin and disable the driver if the pin is accidently open If Ippg is set below 50 uA the regulation level may be significantly impacted by the 250 nA sink current When the bottom resistor is selected select the upper resistor as follows Vout nom eq 17 In our application we select a 27 kQ for Ry IFg 92 uA As for R two 1 800 kQ resistors are placed in series with a 560 kQ one These normalized values precisely give Rw1 4 16 MQ leading to a nominal 388 V regulation level which is
4. 1 SUMMARY OF THE MAIN EQUATIONS steps components tomme O om fine Line frequency It is often specified in a range of 47 63 Hz for 50 Hz 60 Hz applications Viine rms LL Lowest Level of the line voltage e g 90 V Viine rms HL Highest Level for the line voltage e g 264 V in many countries Viine rms boH Brown Output Line Upper Threshold The circuit prevents operation until the line rms voltage exceeds this level Vout nom Nominal Output Voltage 8Vout pk pk Peak to Peak output voltage low frequency ripple Step1 Key Specifications tHoLD uP Hold up Time that is the amount of time the output will remain valid during line drop out Vout min Minimum output voltage allowing for operation of the downstream converter Pout max Maximum output power consumed by the PFC load that is 160 W in our application Pin avg max Maximum power absorbed from the mains in normal operation Generally obtained at full load low line it depends on the efficiency that as a rule of a thumb can be set to 95 2 2 Pout m n V V is the forward voltage of any diode of the bridge It is out generally in the range of 1 V or n less Input Diodes Bridge Losses GJENG JE V line rms line rms 2 Vine rms LL T In our application Su Tees SEE on max lt 2 Pin s r La 2 ax 2V2 LL pr pk Mi 7 20 u 476 uH D 1d we 170 Inductor Pin ba lias line rms LL I
5. 2 z Vinerms on Vout nom This resistor must be greater than 3 9 kQ but not too high for noise immunity necessity Generally resistors in the range of 5 kQ give good results gt Zero Current Circuitry The CS ZCD pin is also designed to receive a signal from an auxiliary winding for Zero Current Detection As illustrated in Figure 1 this voltage is applied thought a diode to prevent this signal from distorting the current sense information during the on time and through a resistor Rzcp This resistor must be high enough so that no more than 5 mA is injected to the CS ZCD pin The auxiliary winding being maximum near the line zero crossing and equal to n 222 Van where respectively nayx and np are the auxiliary and primary turns ratio of the magnetic component this constraint leads to Naux Np Vien gi Ver pos Rzcp gt eq 33 V CL pos 5mA Ta OCP Where Vor pos is the 9 V minimum level of the CS ZCD pin positive clamp The voltage applied to the CS ZCD pin is eq 34 R n V OCP aux V V 3 ZCD out nom lin Rzop Roce P This voltage is compared to the NCP1611 750 mV internal threshold for demagnetization detection For a proper detection a scale down factor Rocp Naux Rzop Roce P in the range of 20 generally gives good results One way is to select Rocp Rzcp Maux Np in the range of 0 1 and re arranging Equation 33 compute n n Va
6. Collateral AND9064 D PDE 2 Joel Turchi Compensation of a PFC stage driven by the NCP1654 Application note AND8321 D http www onsemi com pub link Collateral AND8321 D PDE 3 Joel Turchi Compensating a PFC stage Tutorial TND382 D available at http www onsemi com pub link Collateral TND382 D PDE 4 EVBUM2149 D NCP1611 Evaluation Board User s Manual http www onsemi com pub link Collateral EVBUM2049 D PDF 5 NCP1611 design worksheet http www onsemi com pub Collateral NCP1611 20DWS XLS 6 NCP1611 evaluation board documents http www onsemi com PowerSolutions supportDoc do type boards amp rpn NCP 1611 7 NCP1611 data sheet http www onsemi com pub link Collateral NCP1611 D PDE ON Semiconductor and D are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation specia
7. conditions In our case the resistive impedance on pin3 is Rrr Hence 1 Ree Cre lt 150 fe eq 41 C lt 1 J 411 pF 150 Pre fing 150 270k 60 Layout and Noise Immunity Considerations The NCP1611 is not particularly sensitive to noise However usual layout rules for power supply apply Among them let us remind the following ones The loop area of the power train must be minimized Star configuration for the power ground that provides the current return path Star configuration for the circuit ground The circuit ground and the power ground should be connected by one single path This path should preferably connect the circuit ground to the power ground at a place that is very near the grounded terminal of the current sense resistor Rsense A 100 or 220 nF ceramic capacitor should be placed between the circuit Vcc and GND pins with minimized connection length The components resistors or capacitors that program the circuit operation must be placed as close as possible to the pin they drive As aforementioned it is furthermore recommended to place a filtering capacitor on the 3 relatively high impedance pins of the circuit feedback Input voltage sensing Vsense and FFcontrol to protect the pin from possible surrounding noise It must be small however not to distort the voltage sensed by these pins See the corresponding sections for more details http onsemi com 9 AND9062 D Table
8. is targeted in applications where the connection including GND or of a short of the boost circuit is fed by an auxiliary power source Its start up or bypass diode Application note AND9062 details the level is lower than 11 25 V to allow the circuit to be behavior of a NCP1611 driven PFC stage under safety powering from a 12 V rail Both versions feature a tests 1 large Vcc operating range 9 5 V to 35 V Like in FCCrM controllers internal circuitry allows near unity power factor even when the switching frequency is reduced 2 The voltage of the Brown out detection block input pin Vsense is also used to detect the line range and reduce the loop gain in high line conditions 2 step feed forward Semiconductor Components Industries LLC 2013 1 Publication Order Number January 2013 Rev 1 AND9062 D AND9062 D PFC STAGE DIMENSIONING Filter Figure 1 Generic Schematic Step 1 Define the Key Specifications fline Line frequency 50 Hz 60 Hz applications are targeted Practically they are often specified in a range of 47 63 Hz and for calculations such as hold up time one has to factor in the lowest value specified Viine rms LL Lowest level of the line voltage This is the minimum rms input voltage for which the PFC stage must operate Such a level is usually 10 12 below the minimum typical voltage which could be 100 V in many countries We will take Vline rms LL 90 V Viine rms HL Highest leve
9. may be too long for most applications even when considering Rpo1 and Rpo2 resistors that slightly lower the actual X2 capacitors discharge impedance In this case appropriately reduce Ry and Rx Low stand by losses and noise immunity are the considerations when dimensioning Rpo1 and Rpg The first criterion leads to high impedance resistors to limit the bias current drawn from the line since it can significantly impact the light load losses On the other hand very large values can cause noise issues In practice Rpo2 120 KQ generally gives good results Rx Rx2 and Rpo2 being selected Rpo1 can be derived from Equation 25 based on the desired Viine rms boH level as follows Root Rooo 4 Vine ms por 1 Rx 2 Va Vagn In our application if Viine rms boH is 81 V Rx1 Rx2 Rx 1 MQ and Rpo2 120 KQ we obtain 120k 81 1000k 2 1 0V 2 In practice 3 x 1 800 kQ resistors in series with a 560 kQ one are used for a global 5 960 kQ Rbo1 value which leads to Viine rms boH STRI V and Viine rms boL 69 8 V Remark A filtering capacitor Cpo is recommended between pin2 and ground to protect the pin from possible surrounding noise It must be small however not to distort the voltage sensed by pin 2 Practically the time constant it eq 27 Roi 120 k 6253 kQ eq 28 http onsemi com 7 AND9062 D forms together with the sensing resistors must remain lower than the line period divided by 15
10. 0 Tine 1 150 150 fine that is less than 150 us in 50 Hz line conditions If not the voltage applied to pin 2 may not be proportional to the input voltage but a filtered phase shift portion of it so this should be taken into account when dimensioning the brown out circuitry and the frequency fold back behavior In our case the resistive impedance on pin2 can be approximated to Rpo2 Hence i 1 Rpo2 Cro lt 100 fine gt 1 1 4 nF 1 Coo lt 700 Ro fin 100 120k 60 Step 5 Current Sense Network The current sense circuitry consists of A current sensing resistor Rcs A resistor Rpp that adjusts the frequency fold back characteristic gt Computing Rcs The circuit detects an over current situation if the voltage across the current sense resistor exceeds 0 5 V Hence cs q r eq 29 L pk max Combining this equation with Equation 3 leads to Vinerms LL 4 2 r P inavg max cs eq 30 In our practical case 2 __ 00949 2 170 In order to have a bit of margin a 80 mQ resistor is selected Rcs losses can be computed using the equation giving the MOSFET conduction losses where Rcs replace Rps on Pr Ymax Rog cs 2 Pinavg max i 1 V ine ms LL Hence our 80 mQ current sense resistor will dissipate about 275 mW at full load low line RsENSE must be applied to the CS ZCD pin through a resistor Rocp of Figure 1 R cs eq 31 eq 32 8
11. 2 2 Q e R4 Ge R6 cM 1nF BE 10 kQ Type Y2 R3 C6a 80 mQ 3W gt 68 uF 450 V 68 uF 450 V L1 c3 07 DZ2 D4 680 nF N 22 uF 50 V 33 V Fi Type X2 Fi 1N4148 T e S ej 6 el EP ae L N Earth Socket for External 90 265 Vrms VCC Power Source Figure 6 Application Schematic Power Section R22 560 kQ R8 560 kQ R23 1 800 kQ R9 R11 1 800 kQ R24 27 KQ 1 800 kQ R10 D6 C13 1 800 kQ 1N4148 10 nF R25 1 800 kQ R26 D5 R7 1N4148 0Q DRV Isense R14 R13 120 kQ 270k2 0Q Figure 7 Application Schematic Control Section http onsemi com 12 AND9062 D Conclusions This paper summarizes the key steps when dimensioning a NCP1611 driven PFC stage The proposed approach being systematic it can be easily applied to other applications In addition an Excel Spreadsheet is available that further eases your design by computing the main components of your and information on the performance of this board in the NCP1611 Evaluation Board Manual 4 Implementation details BOM GERBER files can be found on our web site 6 More details on the circuit operation can be found in its data sheet 7 application according to the described method 5 The process has been illustrated by the example of the 160 W wide mains evaluation board You can find details References 1 Joel Turchi Safety tests on a NCP1611 driven PFC stage Application note AND9064 D http www onsemi com pub link
12. AND9062 D 5 Key Steps To Design A Compact High Efficiency PFC Stage Using the NCP1611 ON Semiconductor http onsemi com APPLICATION NOTE This paper describes the key steps to rapidly design a Discontinuous Conduction Mode PFC stage driven by the NCP1611 The process is illustrated in a practical 160 W universal mains application Maximum Output Power 160 W Rms Line Voltage Range from 90 V to 265 V Regulation Output Voltage 390 V Frequency Fold back when the Line Current is less than 450 mA Introduction Fast Line Load Transient Compensation Dynamic Housed in a SO 8 package the NCP1611 is designed to Response Enhancer and Soft OVP Due to the slow optimize the efficiency of your PFC stage throughout the loop response of traditional PFC stages abrupt changes load range Incorporating protection features for rugged in the load or in the input voltage may cause significant operation it is ideal in systems where cost effectiveness over or under shoots This circuit drastically limits reliability low stand by power and high efficiency are key these possible deviations from the regulation point regurements Safety Protections NCP1611 features make the PFC Current Controlled Frequency Fold back CCFF stage extremely robust Among them we can mention The circuit operates in Critical conduction Mode the Brown Out Detection block Note 2 that stops CrM when the instantaneous line current is medium or high
13. ON LITERATURE FULFILLMENT Literature Distribution Center for ON Semiconductor P O Box 5163 Denver Colorado 80217 USA Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Email orderlit onsemi com N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com USA Canada Europe Middle East and Africa Technical Support Phone 421 33 790 2910 Japan Customer Focus Center Phone 81 3 5817 1050 Order Literature http www onsemi com orderlit For additional information please contact your local Sales Representative AND9062 D
14. When this current is lower than a preset level the frequency linearly decays to about 20 kHz CCFF maximizes the efficiency at both nominal and light loads Note 1 In particular stand by losses are minimized operation when the ac line is too low and the 2 level Current Sensing that forces a low duty ratio operation mode in the event that the current exceeds 150 of the current limit which may be caused by the inductor saturation or by a short of the bypass or boost diode Eased Manufacturing and Safety Testing Elements of the PFC stage can be accidently shorted badly soldered or damaged as a result of manufacturing or handling incidents excessive operating stress or other troubles In particular adjacent pins of controllers can be shorted a pin grounded or badly connected It is Skip Mode To further optimize the efficiency the circuit skips cycles near the line zero crossing where the power transfer is particularly inefficient If superior power factor is needed this feature can be inhibited by forcing a minimum 0 75 V voltage Low Start up Current and large Vcc range The often required that such open short situations do not extra low start up consumption of the B version cause fire smoke nor loud noise The NCP1611 NCP1611B allows the use of high impedance integrates enhanced functions that help address resistors for charging the Vcc capacitor The A version requirement for instance in case of an improper pin NCP1611A
15. acceptable http onsemi com 4 AND9062 D Compensating the Loop The loop gain of a PFC boost converter is proportional to the square of the line magnitude if no feed forward is applied Hence this gain almost varies of an order of magnitude in universal mains conditions The Vsgnse pin voltage is representative of the line voltage value The 1 7 Vin rms BOH e g 133 V Vin rms BOH e g 78 V 2 2 Vin rms BOH NCP1611 uses this information to perform a discrete feed forward function in high line that is detected when the pin voltage happens to exceed 2 2 V the PWM gain is divided by 3 compared to a low line state which is set if VsENSE is less than 1 7 V for 25 ms see Figure 3 and Figure 5 Viine rms 3 Vin rms BOH e g 172 V e g 234 V Figure 3 2 step Feed forward Limits the Loop Gain Variation with Respect to Line Using the method described in 1 and 2 we can easily derive two small signal transfer functions of our PFC stage one for high line one for low line Low line transfer function g eq 18 Vout Vinnes Road 1 Veontro 840000 L Voutnom 7 4 g Pio Cour High line transfer function i eq 19 Vout Vinnes Road 1 Veontro 1920000 L Vounom 4 4 g Pat Couk Rept Where Cyyik is the bulk capacitor Rjyad is the load equivalent resistance Lis the PFC coil inductance Vout nom IS the regulation level of the PFC output PFC stages must be
16. ad min is the load equivalent resistor at full load Vout nom _ 8902 160 The crossover frequency is selected as low as possible but higher or equal to the PFC boost stage pole at full load 1 2 4 Hz i z R Coun load min R load min T 950 P out max The phase margin is generally set between 45 and 70 degrees In our application if we target a 15 Hz crossover frequency and a 60 degree phase margin 71 3 in radians we have 2 90 950 aes 640000 200 10 6 390 eq 22 i T_T 154 tan 3 z C2 772 742 950 136 10 780 103 200 nF let s choose 220 nF c 154 Bit 2x 15 780 103 1 9 uF let s choose 2 2 uF R 950 136 10 _ 29 kQ 2 22 10 Step 4 Input Voltage Sensing The NCP1611 monitors the line voltage In general resistors are placed between the two line wires to discharge the X2 capacitors safety requirements These resistors Rx and Rx of Figure 1 and Figure 5 scale down the input voltage that can then be easily sensed by the controller Assuming these resistors exhibit the same Ry resistance the voltage applied to pin 2 is eq 23 R Roo Roo R V bo bo1 bo X y 4 pm Roor Roos Rx Reor Rood Rx ine This expression simplifies as follows R V ping ee 5 Vine eq 24 Ry ZRpot 2Rbo2 The brown out comparator detects a brown out situation if the Vsgnse pin voltage remains lower than VboL 0 9 V for mor
17. e than 50 ms In this case the circuit gradually discharges the control signal until the skip staticOVP level is reached and hence the circuit stops operating Operation resumes as soon as the Vsgynse pin voltage exceeds Vbor 1 0 V If Viine rms boH is the minimal rms voltage of the line to enter operation and Viine ms boL the maximum voltage leading to a Brown Out fault we have Ry 2Rpot 2Roo2 v2 Rooe Viine rms boH VoH eq 25 Ry 2Rpot 2Rbo2 2 Rboz Vine rms bol Vor eq 26 Where Vbou is the 1 0 V upper brown out internal threshold Vbor is the 0 9 V lower brown out internal threshold hitp onsemi com 6 AND9062 D Nas EMI PFC AC Line O i Filter Boost Converter Rx2 Rx1 BONOK ET 50 ms i Rbo1 Fog Time Vsence Pin Fe a C 1 0 V If BONOK High 0 9 V If BONOK Low Rbo2 D LLine Fag ms ag Blanking Time F C 2 2 V If LLine High 1 7 V If LLine Low Current FFcontrol Pin Information Generation 2 lramp je DRV J Figure 5 Brown Out and Line Range Detection Block Rx and Rx are implemented for safety considerations In general they must be selected so that the series combination of Rx1 Rx2 2Rx form with the X2 EMI capacitors a time constant less than 1 s In our case the two 1 MQ resistors Rx1 Rx2 Rx I MQ are implemented that together with the selected X2 capacitors leads to a 1 8 s discharge time constant which
18. eam converter with a sufficient input voltage Pout Output power This is the power consumed by the PFC load Pout max Maximum output power This is the maximum output power level that is 160 W in our application Pin avg max Maximum input power This is the maximum power that can be absorbed from the mains in normal operation This level is obtained at full load low line Assuming an efficiency of 95 in these conditions we will use _ 160 _ 95 170 W Iline max Maximum line current obtained at full load low line P in avg max Prp g Line Current Threshold below which the circuit reduces the frequency CCFF expressed as a percentage Of Tjine max If this parameter is higher than 100 the PFC stage will permanently operates with a reduced frequency Conversely if Prp x is close to zero the PFC stage will function in CrM no frequency fold back in almost the whole power range This parameter is normally selected in the range of 10 to 20 Step 2 Power Components Selection In heavy load conditions the NCP1611 operates in Critical conduction Mode CrM Hence the inductor the http onsemi com 2 AND9062 D bulk capacitor and the power silicon devices are dimensioned as usually done with any other CrM PFC This section does not detail this process but simply highlights key points 1 Inductor Selection The on time of the circuit is internally limited The power the PFC stage can deliver depends
19. l consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATI
20. l for the line voltage This is the maximum input rms voltage It is usually 10 above the maximum typical voltage 240 V in many countries We select Vline rms HL 264 V Viine rms boH Brown out line upper threshold The circuit prevents operation until the line rms voltage exceeds Viine rms boH The NCP1611 offers a 10 hysteresis Hence if no specific action is taken it will detect a brown out situation and stop operation when the rms line voltage goes below V ine rms boL that equates 90 x Vline rms boH In our application we target Viinerms bo 90 X Vinerms it 81 V Viine rms bor 90 x Viine rms boH 7 3 V Vout nom Nominal output voltage This is the regulation level for the PFC output voltage also designated bulk voltage Voutnom must be higher than V2 x Viine rms HL 390 V is our target value 8Vout pk pk Peak to peak output voltage ripple This parameter is often specified as a percentage of the output voltage It must be selected equal or lower than 8 to avoid triggering the Dynamic Response Enhancer DRE in normal operation tyoLp up Hold up time This parameter specifies the amount of time the output will remain valid during line drop out One line cycle is typically specified This requirement requires knowing the minimum voltage on the PFC stage output necessary for the proper operation in your application Vout min We have assumed Vout min 350 V is high enough to provide the downstr
21. ne frequency minimum value 47 Hz this leads to 160 11 Coum gog pr 47 3902 PUF ea 10 Hold up time specification 2 P t Coi gt out max foe DP eq 12 Vout nom Vout min Hence a 10 ms hold up time imposes 2160 10m Crue gt 7 108 uF eq 13 mk 38902 3502 Rms capacitor current The rms current depends on the load characteristic Assuming a resistive load we can derive the following approximate expression of its magnitude Note 3 eq 14 loms max 2 32 2 Pin avg max Fass ae Vine rms LL Vout nom Voutnom In our application we have 2 IR 2 322 170 189 z 97 90 390 390 eq 15 Gms IR v1 318 0 168 1 1A 3 It remains wise to verify the bulk capacitor heating on the bench Step 3 Feedback Arrangement As shown by Figure 1 the feed back arrangement consists of A resistor divider that scales down the bulk voltage to provide pin8 with the feedback signal The upper resistor of the divider generally consists of three or four resistors for safety considerations see Rg Ro and R10 of Figure 7 If not any accidental shortage of this element would apply the output high voltage to the controller and destroy it A filtering capacitor that is often placed between pin8 and ground to prevent switching noise from distorting the feedback signal A 1 nF capacitor is often implemented Generally speaking the pole it forms
22. nn z 2 j Vei Goa P 5 mA Prop Roce gt In our application this leads to Rocp Rzcp gt 4 2 KQ We selected Roce Rzcp 4 7 KQ This selection also meets the Rocp gt 3 9 kQ requirement see precedent paragraph The NCP1611 integrates a leading edge blanking on the CS ZCD pin that prevents the need for a filtering capacitor It is still possible to add one but it must be very small not to distort the ZCD signal Otherwise the circuit may not turn on at the very valley or worse inappropriately skip valleys In other words check that the ZCD signal is correct and not too filtered In our application this capacitor should not exceed 22 pF gt Computing Rer Rpr adjusts the current level below which the frequency starts to be reduced The FFcontrol pin sources a current that is proportional to http onsemi com 8 AND9062 D V control V control min V control min lsp 140 109 Vono V control max Since Vpin2 1V when Vine v2 x Viine rms BOH we can write eq 35 1V Ving Vine pin2 fr line 2 Vine ms Bor Further noting that V control _ V controlmin tor Veoniral max V control min ton max where ton max IS the 25 us internal maximum on time and that fine Vine ton line oO Equation 35 changes into 56 L 1 line FF 7 eq 36 5 2 Vine rms BOH The FFcontrol pin voltage is then 56 Reg Le ly
23. o avoid excessive MOSFET losses Assuming that Rps on doubles at high temperature the maximum conduction losses are about 1 7 W The total conduction losses can then be as high as about 5 1 W Switching losses cannot be easily computed We will not attempt to predict them Instead as a rule of the thumb we will assume a loss budget equal to that of the MOSFET conduction ones Experimental tests will check that they are not under estimated One can anyway note that the MOSFET turn off can be accelerated using the schematic of Figure 2 where the Q1 NPN transistor TO92 amplifies the MOSFET turn off gate current This enhancer is not implemented in our board http onsemi com 3 AND9062 D DRV D2 R2 1N4148 R1 M1 R10 10 kQ Q1 9 Figure 2 Q1 Speeds Up the MOSFET Turn Off The boost diode is the source of the following conduction losses lout x Vf where Iout is the load current and V the diode forward voltage The maximum output current being nearly 0 4 A the diode conduction losses are in the range of 0 4 W assuming Vr 1 V Ppiope 0 4 W 3 Output Bulk Capacitor There generally are three main criteria constraints when defining the bulk capacitor Peak to peak low frequency ripple P C puik OD Vout nom out max OV out pk pk eq 10 where 27 x fiine is the line angular frequency This ripple must keep lower than 4 of the output voltage 8 peak to peak Taking into account the li
24. ok pk max 53A l _ 5 3 _ _ Lpk max ims max 52 2 28 6 I Lrms max Pon max 3 Rosin MOSFET A Conduction P Losses _ outmax n Viine rms LL Rpscon is the drain source 8 2 Ved ae In of the an V Step2 Power Components out nom Paimas These 3 equations quantify the C bulk lt constraints resulting from the 8V out pk pk lt Voutnom low frequency ripple 2 p t 8Vout pk pk that must be kept C out max HOLD UP below 8 the hold up time bulk y 2_V 2 requirement and the rms current Bulk putnom outmin to be sustained Capacitor Constraints Ic rms max Fi a 2 Pin avg max V P out max Vout nom Vine rms LL out nom http onsemi com 10 AND9062 D Table 1 SUMMARY OF THE MAIN EQUATIONS continued steps componens Fom somme Resistor Divider Cy S 150 Rep Ripa fine _ Viine rms LL R 640000 L Voutnom Go ng n load min Step3 Feedback Arrangement C wae i Compensation 2 1 fe Rjoad min Cbulk C2 Viine rms boH Input Voltage 1 Sensing v2 VboH Resistors 1 lt i 150 Rio fiine D N c D C gt i line rms LL 4 yn Pin avg max Current Sense Resistor 2 Pin avg max 8 2 i Viine rms LL 1 3x V Viine rms LL vo 5 hr AUS veg v o a Zero Current R
25. on the inductor since L will determine the current rise for a given on time More specifically the following equation gives the power capability of the PFC stage V 2 line rms gt Tormak eq 1 2L The smaller the inductor the higher the PFC stage power capability Hence L must be low enough so that the full power can be provided at the lowest line level V 2 line rms LL Ton max eg 2 2 Pin avg max Like in traditional CrM applications the following equations give the other parameters of importance P in avg HL Maximum peak current NE P in avg max VL pk max 2v2 eg 3 Vine ma LL Maximum rms current l pr max IL rms max HATE eg 4 v6 In our application the inductor must then meet the following requirements 902 lt 20 u 476 uH 2 170 K Li pk max 2 2 ie 53A eq 5 53 22A TL rms max 16 Ton max 20 us is the minimum value for Ton max the typical value being 25 us Ton max 20 us is hence used in Equation 5 since this is the worst case when calculating L It is in addition recommended to select an inductor value that is at least 25 less than that returned by Equation 5 for a healthy margin A 200 uH 6 Apk inductor ref 750370081 from WURTH ELEKTRONIK is selected It consists of a 10 1 auxiliary winding for zero current detection One can note that the switching frequency in CrM operation depends on the inductor val
26. slow More practically high PF ratios require the low regulation bandwidth to be in the range of 20 Hz or lower Hence sharp variations of the load result in excessive over and under shoots These deviations are effectively contained by the NCP1611 dynamic response enhancer together with its accurate over voltage protection Still however a type 2 compensation is recommended as shown in the following figure ICONTROL To PWM Comparator Figure 4 Regulation Trans conductance Error Amplifier Feed back and Compensation Network http onsemi com 5 AND9062 D The output to control transfer function brought by the type 2 compensator is Veontrol _ 1 sR C eq 20 Vout SR C on 1 sR cS 1 2 Where Ro Vout nom i Vier Gea Gea being the 200 uS error amplifier trans conductance gain Vout nom the bulk nominal voltage and Vrep the OTA 2 5 V voltage reference Applying the compensation method described in 2 and 3 we obtain the following dimensioning equations Vinesmslu Pjoad min Go 21 640000 L Vautnom q 21 Go tan 3 bm C ae 2 2 72 fo Pioad min C puik i Ro Go C 2 x fe i Ro Ce Pioadmn Cour 2 C Where Vin rms LL is the rms voltage of the line when at its lowest level 90 V in our case Go is static gain at the lowest level of the line Viine rms LL dm is phase margin in radians e feis the targeted crossover frequency Rio
27. ue Vine t Vout Vinel few ET eq 6 in avg For instance at low line full load top of the sinusoid the switching frequency is _ 2 90 2 390 V2 90 4 170 390 200 10 8 fsw 80 kHz eq 7 2 Power Silicon Devices Generally the diode bridge and the power MOSFET are placed on the same heat sink As a rule of the thumb one can estimate that the heat sink will have to dissipate around 4 of the output power in wide mains applications 95 being generally the targeted minimum efficiency 2 of the output power in single mains applications In our wide mains application about 6 4 W are then to be dissipated We selected a low profile heat sink from COLUMBIA STAVER reference TP207ST 120 12 5 NA SP 03 whose thermal resistance has been measured to be in the range of 6 C W Among the sources of losses that contribute to this heating one can list The diodes bridge conduction losses that can be estimated by the following equation PI Fa 18 V P T J O eq 8 Pordge 2 Vi V Fv PE line rms line rms where Vy is the forward voltage of the bridge diodes The MOSFET conduction losses are given by Pon max eq 9 P 8v2 e 2 4 out max 2 R iL ME t ran i In our application we have Iz Vout nom PBRDGE 3 4 W assuming that Vx is 1 V Pon max 3 4 x RDs on In our application a low Rps on MOSFET 0 25 Q 25 C is selected t
Download Pdf Manuals
Related Search