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PX1 User Manual - Blue Chip Technology

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1. J1 2 P3 P4 P5 6 57 H2 J3 TERM m P8 P9 P10 BUZZER J4 09 P js PROCESSOR Esse BEA alsv pam 6 2 VID DIS Joe 9 CCS FLASHBE 8959525959959595 gt 2 9 ul J8 5 6 00 3 3 Ica 213 A 34599 BLUE CHIP TECHNOLOGY Ltd 5555555555555 59 10 PXI Issue 1 0 2 522 VRT lono STD E IC10 E T 0 J12 RE P15 5 2 12 mus J13 P18 F SIM 12 54 TOPSIDE IC39 IC44 UNDERSIDE Drg No A3 96 0111 D Issue 2 Sht 01 of 01 127 172 Blue Chip Technology Ltd
2. 15 S3 GRAPHICS SUBSYSTHEM 5 ete 15 RESOLUTIONS 8 22020 22 16 BIOS EE 16 SETUP UTILITY o x tin i ri i v EGRE 17 PCISUPPORT eS 17 PLUG AND PLAY 17 AUTO CONFIGURATION CAPABILITIES esee 17 ADVANCED POWER MANAGEMENT seen 18 SLEEP MODE SUPPORT esee opem 18 Blue Chip Technology Ltd 01271019 doc SECURITY FEATURES 19 CONNECTORS Ce o er eer 19 BACK PANEL CONNECTORS ice eee dene 19 ON BOARD 5 00 00000000000000 000000002 20 BUS CONNECTORS n iie e eer PUDE 22 JUMPERS eie EE re 22 CPU FREQUENCY SELECTION J1 amp J11 ee 22 ON BOARD VIDEO JO6 24 CMOS BATTERY SOURCE CLEAR CMOS 713 24 ISA BUS GLOCK 112 ie de t ere eer tated devs velaten tes 24 MMX SETTINGS 24 TABLE OF JUMPERS 25 STATUS LEDS reed up 26 USER INSTALLABLE 27 SYSTEM MEMORY iiie teet 27 REAL TIME CLOCK BATTERY REPLACEMENT 28 CPUUPGRADE PUE p dettes 28 GRAPHICS MEMORY 28 SOFTWARE DESCRIPTION eerie eese eene ente etna 28 BIOS SETUP
3. m Micro if prae Mouse if present Primary E IDE Secondary E IDE RESERVED y o0 0 0 Cascade channel CONNECTORS BACK PANEL CONNECTORS The back panel houses four connectors for the video RS232 communications port PS 2 mouse and PS 2 keyboard 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL APPENDICES PAGE 61 VIDEO CONNECTOR P12 15 WAY CONDENSED D TYPE PINNO SIGNAL PINNO SIGNAL 5 OVolts Ground 6 JjoOVols Ground 7 OVots Groun 8 JjoOVols Ground 9 NoUsd 140 Volts Ground 15 PS 2 MOUSE PORT P13 6 WAY MINI DIN PINNO SIGNAL PINNO SIGNAL 5 Mouse Clock 6 jNotUsed RS232 SERIAL PORT 1 P15 9 WAY D TYPE PINNO SIGNAL PINNO SIGNAL 5 6 Jj DataSetReay 7 ReajyToSed 8 j ClarToSend 9 Ringing indicator OP o S PS 2 KEYBOARD PORT P18 6 WAY MINI DIN PINNO SIGNAL PINNO SIGNAL Keyboard Data Not Used 5 Volts fused Keyboard Clock 6 Not Used INTERNAL I O HEADERS The board has a number of internal peripheral connectors Blue Chip Technology Ltd 01271019 doc 01271019 doc PAGE 62 APPENDICES PX1 USER MANUAL PRIMARY IDE CONNECTOR P1 40 WAY HEADER PINNO SIGNAL PINNO SIGNAL Data bit 7 HD Data bit 8 HD Data bit 6 HD 6 Databit9 HD Data bit 5 HD
4. 60 INTERNAL HEADERS 2 61 FLOPPY DISK DRIVE CONNECTOR P2 34 WAY 62 POWER CONNECTOR 4 WAY 5 4 DISK DRIVE CONNECTOR 63 ECP EPP PARALLEL PORT 26 WAY 64 BATTERY CONNECTOR P17 4 WAY 67 BUS CONNECTORS 4 eie dee ne RD ge ge itus 67 ERROR MESSAGES Hate teer Pte res hey 72 AMIBIOS ERROR BEEP 73 AMIBIOS ERROR CODES ON THE POST DISPLAY 74 AMIBIOS ERROR 55 79 NMI MESSAGES oiei ef ce de pt eer tette ig 81 PCI CONFIGURATION ERROR MESSAGES 81 BOARD LAN OU Va te teet ee eden 83 Blue Chip Technology Ltd 01271019 doc COMPANY PROFILE COMPANY PROFILE Blue Chip Technology is the leading specialist PC product manufacturer in UK Europe Blue Chip Technology provides innovation with quality design and manufacturing from a single source Based in the North West our purpose built complex contains one of the most advanced research and development facility engineering workshop and production lines Specialising in the provision of industrial computing and electronic solutions for a wide range of UK and European organisations Blue Chip Technology has one of the UK s largest portfolios of industrial PCs peripherals and data
5. A38 40 A 42 A43 4 A46 47 48 A49 KEY Blue Chip Technology Ltd No Connect Vcc Vcc PCIINT2 PCIINT4 REQ4 REQ2 Al Al AD27 Al 3 CBE3 Al AD21 Al 3 AD17 IRDY DEVSEL GND PLOCK PERR 3 3V SERR CBE1 AD14 GND AD12 AD10 GND 5 9 c Q Q wloz lF 995 z k iz z lt lt x o lt lt o PAGE 71 01271019 doc 72 PX1 UsER MANUAL KEY B60 NOTE The PCI connector details shown here are for the PX1 processor card The PCI connectors of a backplane differ slightly some pins having a position dependent signal 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL ERROR MESSAGES PAGE 73 ERROR MESSAGES AMIBIOS ERROR BEEP CODES The BIOS performs a Power On Self Test POST after a reset or reboot If errors occur during the POST the microprocessor indicates the status of the test by writing codes to the I O port at address 80 Hex If the BIOS cannot find and configure the display controller then the errors are communicated through a series of audible beeps by the speaker drive circuit Fatal errors which prevent the system from continuing the boot process will produce beep codes Other errors are displayed textually For these see AMIBIOS Error Messages in the following subsection BEEPS ERROR MESSAGE DESCRIPTION Video failure
6. 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL SOFTWARE DESCRIPTION The optimal and fail safe settings are OPTIMAL IRQ3 ISA EISA IRQ 4 ISA EISA IRQ 5 PnP IRQ 7 ISA EISA IRQ 9 IRQ 10 PnP IRQ 11 IRQ 14 15 RESERVED MEMORY SIZE FAILSAFE ISA EISA ISA EISA PnP ISA EISA PnP PnP PnP PnP PnP PAGE 45 This option specifies the size of the memory area reserved for legacy ISA adapter cards The settings are Disabled 16K 32K or 64K The Optimal and Fail Safe default settings are Disabled RESERVED MEMORY ADDRESS This option specifies the beginning address in hex of the reserved memory area The specified ROM memory area is reserved for use by legacy ISA adapter cards The settings are C0000 C4000 C8000 CC000 D0000 D4000 D8000 DC000 The Optimal and Fail Safe default settings are C8000 PERIPHERAL SETUP Peripheral Setup options are displayed by choosing the Peripheral Setup icon from the WINBIOS Setup main menu Peripheral Setup options are described in this section ONBOARD PCI IDE This option specifies the onboard IDE controller channels that will be used The settings are Primary Secondary Both or Disabled The Optimal and Fail Safe default settings are Both Blue Chip Technology Ltd 01271019 doc 46 SOFTWARE DESCRIPTION PX1 UsER MANUAL ONBOARD FDC This option enables the floppy drive controller on the PC board The set
7. 1 Single Board Blue Technology User Manual 1 User Manual Document Part N 0127 1019 Document Reference PX1X 401271019 doc Document Issue Level 1 3 Manual covers PCBs with the following Issue N 1 x is any digit rights reserved No part of this publication may be reproduced stored in any retrieval system or transmitted in any form or by any means electronic mechanical photocopied recorded or otherwise without the prior permission in writing from the publisher For permission in the UK contact Blue Chip Technology Information offered in this manual is believed to be correct at the time of printing Blue Chip Technology accepts no responsibility for any inaccuracies The information contained herein is subject to change without notice There are no express or implied licences granted herein to any intellectual property rights of Blue Chip Technology Ltd All trademarks and registered names acknowledged Blue Chip Technology Ltd Chowley Oak Tattenhall Chester Cheshire CH3 9EX Telephone 01829 772000 Facsimile 01829 772001 Amendment History ee eme d Level Date 02 10 96 First Approved Issue 20 03 97 Updated for Issue 1 0 PCB previously Rev C amp C 1 tpe iue ipei ee 20 10 97 Additions to manual see 97 100 CONTENTS iyu uon uvO 1 MANUAL OBJECTIVES 1 LIMITATIONS OF LIABILITY eitr 2
8. AH 00h DL Watchdog period 00h disabled Olh FFh 255mins DH Extended functions Bit 0 route time out to reset Set to 1 the system will reset when the watchdog times out Set to 0 the watchdog will need to be polled to detect a timeout Return values Returns with the carry flag clear AH 01H EXTENDED WATCHDOG RESET Blue Chip Technology Ltd 01271019 doc 54 SOFTWARE DESCRIPTION PX1 USER MANUAL Issuing this command will reset the watchdog within the SMC932 Ultra IO controller to start timing down again Input Parameters AH 01h Return values None AH 02H EXTENDED WATCHDOG STATUS This will return the status of the SMC932 Ultra IO watchdog for systems that are polling the status Input parameters AH 02h Return values AL Watchdog status 00h Watchdog OK FFh Watchdog time out Carry flag mirrors the status of the SMC932 time out bit AH 03H RESERVED This function is reserved for future use AH 04H RESERVED This function is reserved for future use AH 05H WATCHDOG ENABLE This function enables the simple 500ms watchdog Input parameters 05h Return values Returns with the carry flag clear AH 06H WATCHDOG TICK 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL SOFTWARE DESCRIPTION PAGE 55 This function resets the count on the 500ms watchdog Input parameters 5068 Return values Returns with the carry flag clear AH
9. 30 2 Open Link Link Open 133 6 2 Open Link Open Link 150 6 30 25 tink Lin Link Open 166 66 33 25 link Link Open Link Blue Chip Technology Ltd 01271019 doc 24 HARDWARE DESCRIPTION PX1 UsER MANUAL ON BOARD VIDEO J6 The is equipped with a link J6 to allow the user to disable the on board video when external video adapters are being used If a PCI video adapter is fitted into a system the on board video will be automatically disabled without having to fit a jumper on J6 J6 must be fitted when using ISA based adapter boards in a 1 based system CMOS BATTERY SOURCE CLEAR CMOS J13 This jumper is used to clear the CMOS RAM in the event that the contents become corrupt It selects the source of backup power to the CMOS RAM and also allows the CMOS to be cleared down to the default settings Fitting the link to the CLR position with the power off allows on board capacitors to discharge and will reset the CMOS memory The jumper should then be returned to the NORM position to restore normal operation ISA BUS CLOCK J12 This jumper changes the clock frequency of the ISA bus The effect of this jumper on the ISA clock depends upon the setting of the CPU clock speed jumpers With the jumper linked the clock frequency is divided by 8 With the jumper open the clock frequency is divided by 6 resulting in a higher ISA
10. 8 Data bit 10 HD Data bit 4 HD Data bit 11 HD Data bit 3 HD Data bit 12 HD 13 Data bit 2 HD Data bit 13 HD 15 Data bit 1 HD Data bit 14 HD 17 Data bit 0 HD Data bit 15 HD 19 Ground Not used 21 Drive Request Ground 23 Write HD Ground 25 IO Read HD Ground 7 Drive Read Not Used 29 Drive Acknowledge Ground 31 IRQ14 Not Used 33 Address 1 HD 1 Kohm to Ground 35 Address 0 HD Address 2 HD FLOPPY DISK DRIVE CONNECTOR P2 34 WAY HEADER PINN SIGNAL SIGNAL 5 6 Notused 7 Grouwa 8 index Grua 10 Blue Chip Technology Ltd PX1 UsER MANUAL APPENDICES PAGE 63 RS485 SERIAL PORT 2 10 WAY HEADER PIN NO SIGNAL PIN NO SIGNAL Rx FDX Term 10 K to 5V Rx FDX eim eer T HDX See I RX Tx HDX 9 10 K to Gnd RS232 SERIAL PORT 2 P4 10 WAY HEADER Pinne Pinne 5 TrasmitData 6 ClearToSend 7 DataTermReady 8 Ringiglndicatr 9 Gowd 0 Notused POWER CONNECTOR P5 4 WAY 514 DISK DRIVE CONNECTOR SIGNAL 12 Volts DC Not required for PX1 operation Only required for PC 104 cards that need 12 Ground Ground 5 Volts DC Pin 4 is at top left corner of board Blue Chip Technology Ltd 01271019 doc 64 APPENDICES PX1 USER MANUAL ECP EPP PARALLEL PORT 26 WAY HE
11. advanced Power Management features The settings are Enabled Disabled or Inst On The default settings are Disabled INSTANT ON SUPPORT If this option is set in Power Management APM it allows the computer to go to full power on mode when leaving a power conserving state AMIBIOS uses the RTC Alarm function to wake the computer at a pre specified time The settings are 1 to 14 minutes or Disabled The default settings are Disabled Blue Chip Technology Ltd 01271019 doc 40 SOFTWARE DESCRIPTION PX1 UsER MANUAL GREEN PC MONITOR POWER STATE This option specifies the power management state that the Green PC compliant video monitor enters after the specified period of display inactivity has expired The settings are Off Standby or Suspend The default settings are Standby VIDEO POWER DOWN MODE This option specifies the power management state that the video subsystem enters after the specified period of display inactivity has expired The settings are Disabled Standby or Suspend The default settings are Disabled HARD DISK POWER DOWN MODE This option specifies the power management state that the hard disk drive enters after the specified period of display inactivity has expired The settings are Disabled Standby or Suspend The default settings are Disabled HARD DISK TIMEOUT MIN This option specifies the length of a period of hard disk inactivity When this period expires the hard disk drive enters
12. breite telis 29 OVERVIEW OF THE SETUP MENU SCREENS e 29 MAINSCREEN itio ete none iem 29 OVERVIEW OF THE SETUP KEYS nennen nre 32 STANDARD SELOP ss 32 ADVANCED CMOS SETUP e ied 34 ADVANCED CHIPSET SETUP 5 e ADDE 38 POWER MANAGEMENT SETUP 39 PNP SETUP unius uU IM 42 PERIPHERAL SETUP eed EN EE prever 45 DISKONCHIP 2000 SUPPORT 49 IEPREBEACBP 2 p ee 49 2 OPERATING THE DISKONCHIP nenne 50 2 1 INSTALLING THE DISKONCHIP 2000 50 2 2 CONFIGURING THE DISKONCHIP 2000 AS THE BOOT DEVICE 50 2 3 CONFIGURING THE DISKONCHIP 2000 AS THE FIRST DRIVE 51 BIOS EXTENSIONS SOFTWARE INTERFACE eee 52 ENABLING BIOS 8 52 ACCESSING INT 50H 8 202002 0 52 INT 50H FUNCTION 2 53 01271019 doc Blue Chip Technology Ltd CONTENTS Punnn M M 55 ADDRESS MAPS 56 MEMORY MAP eet 56 as e ope p nb PR PIPER 56 PCI CONFIGURATION SPACE 58 INTERRUPTS amp DMA CHANNELS esee 59 SS heilen 60 BACK PANEL CONNECTORS
13. Hte Rete tei Dette 1 PRECAUTIONS re rb ret e Hr Ferrer 2 ELECTRO STATIC DISCHARGES 2 ON BOARD ice terti tient sale 2 RELATED PUBLICATIONS renei trn b hU tee Le te teet Geb te eda 3 3 USER GUIDE 5 OVEBRVIEW cniin o dei tole RH 5 BOARD LEVEL 2 6 CRU i deci ee aep ete eee 6 PROCESSOR UPGRADE ni enecens etre tt tvi ele o aa edel renes 7 SECOND LEVEE CACHE n eae breites 7 SYSTEM MEMORY eie ter Pe e Ie 7 BUS EXPANSION SLOTS b dee eerie ie eere ied 8 ELECTROMAGNETIC sse 8 SPECIEIGATION 4 31 t ete Read 10 HARDWARE DESCRIPTION e eeeeeeeeee sette ne t innen sse tn ases sets se tnnae 10 PERIPHERAL COMPONENT INTERCONNECT PCT PCISET 11 62437FX TRITON SYSTEM CONTROLLER 5 esee 12 62438FX TRITON DATA PATH TDP 12 62371FB PCI ISA IDE ACCELERATOR 12 IDE SUPPORT 12 SMC 37C932 SUPER I O CONTROLLER eere 14 FLOPPY eee eei etie tee o eere 14 KEYBOARD INTERFACE 14 REAL CLOCK CMOS RAM AND
14. Under these circumstances it may be beneficial to add a ferrite clamp on the keyboard lead as close as possible to the connector A suitable type is the Chomerics type H8FE 1004 AS Ensure that the screens of any external cables are bonded to a good RF earth at the remote end of the cable Failure to observe these recommendations may invalidate EMC compliance Warning This is a Class A product In a domestic environment this product may cause radio interference in which case the user may be required to take adequate measures Blue Chip Technology Ltd 01271019 doc 10 USER GUIDE PX1 UsER MANUAL SPECIFICATION 1 Power 45V 596 Required for processor operation Requirement 12 5 Only required with security monitor micro controller option 433 V 5 Not required for board operation 5V 59 TheISA 104 amp PCI voltage 12V 5 rails are linked on board Typical System Consumption 35 Watts Pentium 100 16 MB RAM 256 KB L2 cache 3 2 FDD 540 MB HDD Temperature Non Operating 40 to 70 C Operating 0 C to 55 C min airflow of 200 Shock Non Operating Half sine 2ms m drop Vibration Non Operating 5 Hz 500 Hz 3 1 RMS random Operating 10 Hz 500 Hz 1 0 g RMS random EMC Emissions EN55022 A Immunity EN50082 2 Blue Chip ICON Industrial PC Chassis MTBF Calculated 72 000 Hrs Dimensions Board only 338 x 122 mm Power Consumption figures given are for a typical
15. acquisition cards This extensive range of products coupled with our experience and expertise enables Blue Chip Technology to offer an industrial processing solution for any application The PX1 Single Board PC is the latest addition to our portfolio providing a cost effective product development and volume production tool for OEMs A unique customisation and specialised system integration service is also available delivering innovative solutions to customers problems The company s success and reputation in this area has led to a number of large design and manufacturing projects for companies such as BNFL Aston Martin JaguarSport and British Gas British Standards Institute approval BS EN 9001 means that all of Blue Chip Technology s design and manufacturing procedures are strictly controlled ensuring the highest levels of quality reliability and performance Blue Chip Technology are also committed to the single European market and continue to invest in the latest technology and skills to provide high performance computer and electronic solutions for a world wide customer base 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL INTRODUCTION PAGE 1 INTRODUCTION MANUAL OBJECTIVES This manual describes in detail the Blue Chip Technology PX1 Single Board processor card We have tried to include as much information as possible but we have not duplicated information that is provided in the standard IBM Technical References
16. monitor for power conservation purposes When this option is set to Monitor and there is no display activity for the length of time specified in the value in the Full On to Standby Timeout Min option the computer enters a power saving state The settings are Monitor or Ignore The default settings are Ignore IRQ 3 4 5 7 9 10 11 12 13 14 15 These options enable event monitoring When the computer is in a power saving mode activity on the named interrupt request line is monitored by AMIBIOS When any activity occurs the computer enters Full On mode Each of these options can be set to Monitor or Ignore The settings are OPTIMAL IRQ3 Monitor Ignore IRQ 4 Monitor Ignore 5 Ignore Ignore IRQ 7 Monitor Ignore IRQ 9 Ignore Ignore IRQ 10 Ignore Ignore IRQ 11 Ignore Ignore IRQ12 Monitor Ignore IRQ 13 Ignore Ignore IRQ 14 Monitor Ignore IRQ 15 Monitor Ignore Blue Chip Technology Ltd 01271019 doc 42 SOFTWARE DESCRIPTION PX1 USER MANUAL PCI PNP SETUP PLUG AND PLAY AWARE OS Set this option to Yes if the operating system installed in the computer is Plug and Play aware AMIBIOS only detects and enables PnP ISA adapter cards that are required for system boot The Windows 95 operating system detects and enables all other PnP aware adapter cards Windows 95 is PnP aware Set this option to No if the operating system such as DOS OS 2 Windows 3 x does not use PnP You must set this option
17. unless it proved to be necessary to aid in the understanding of the Single Board The manual is sectioned into logical parts and includes a User Guide which will help the non technical get the unit up and running A Troubleshooting Guide is also included to help when things go wrong We strongly recommend that you study this manual carefully before attempting to interface with 1 or change the standard configurations Whilst all the necessary information is available in this manual we would recommend that unless you are confident you contact your supplier for guidance Please be aware that it is possible to create configurations within the CMOS RAM that make booting impossible If this should happen clear the CMOS settings see the description of the Jumper Settings for details If you have any suggestions or find any errors concerning this manual and want to inform us of these please contact our Customer Support department with the relevant details LIMITATIONS OF LIABILITY In no event shall Blue Chip Technology be held liable for any loss expenses or damages of any kind whatsoever whether direct indirect incidental or consequential arising from the design or use of this product or the support materials supplied with this product If this product proves to be defective Blue Chip Technology is only obliged to replace or refund the purchase price at Blue Chip Technology s discretion according to their Terms and Con
18. 4 devices The system BIOS supports Logical Block Addressing LBA and Extended Cylinder Head Sector ECHS translation modes as well as AT API e g CD ROM devices on both IDE interfaces Detection of IDE device transfer rate and translation mode capability is automatically determined by the system BIOS In the Windows M 95 environment a driver can allow the IDE interface to operate as a PCI bus master capable of supporting PIO Mode 4 devices with transfer rates up to 16MB sec while minimising the system demands upon the processor Normally programmed I O operations require a substantial amount of CPU bandwidth In true multi tasking operating systems like Windows 95 the CPU bandwidth freed up by using bus mastering IDE can be used to complete other tasks while disk transfers are occurring 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL HARDWARE DESCRIPTION PAGE 13 Microsoft will provide this driver for Windows M 95 other software vendors may make drivers available for other operating systems Detailed information on the PClIset is available in the Intel 82430 PCISet data sheet Blue Chip Technology Ltd 01271019 doc 14 HARDWARE DESCRIPTION PX1 UsER MANUAL SMC 37C932 SuPER CONTROLLER Control for the integrated serial ports parallel port floppy drive RTC and keyboard controller is incorporated into a single component the SMC 37C932 This component provides Two NS16C550 compatible UARTs with send
19. Chip Technology Ltd 01271019 doc 6 USER GUIDE PX1 USER MANUAL BOARD LEVEL FEATURES e Socket 7 Pentium Processor socket supporting 75 166 MHz operation On board 3 3 V CPU voltage regulator Intel Triton 82430 PCISet chipset 82437 System Controller TSC 82438FX Data Path TDP 82371FB PCI ISA IDE Accelerator PIIX 256KB or 512 KB PipeLine Burst Level 2 cache 256 Asynchronous Level 2 cache using plug in COAST connector e Four SIMM sockets providing up to 128 MByte of EDO or FPM DRAM S3 Trio PCI graphics controller with 1 MByte standard video memory Plug in option for 2MByte Video feature connector PICMG compliant PCI ISA amp PC 104 expansion busses e SMC 37C932 I O controller providing Dual PCI IDE interfaces Dual floppy interface Dual 16C550 RS 232 422 485 serial interfaces EPP ECP bi directional parallel interface Real time clock with on board battery PS 2 mouse and keyboard connectors On board Solid State Disk Flash and Security microcontroller providing power monitoring and reset control On board status LEDs Drive for up to 14 ISA 3 PCI expansion slots and 3 PC 104 cards CPU The single board PC is designed to operate with Pentium Processors running at 3 3 3 45 or 3 6 Volts An on board voltage regulator circuit provides the required voltage for the processor from the 5 volt output of a standard PC power supply On board jumpers enable the use of VRT specified
20. cannot be modified BOOT SECTOR VIRUS DETECTION If set to Enabled this will flag a warning when the boot sector of a hard disk drive is changed The options are Enabled and Disabled The default is Disabled ADVANCED CMOS SETUP QUICK BOOT Set this option to Enabled to instruct the BIOS to boot quickly If set to Enabled the BIOS does not test memory above 1 MB and the BIOS does not wait up to 40 seconds for a READY signal from the hard drive If the READY signal is not received immediately from the IDE drive it is not configured as if it was absent The default is Disabled BOOTUP SEQUENCE This option specifies the sequence of the boot drives floppy drive A hard drive C or a CD ROM drive The settings are C A CD ROM A C CD ROM CD ROM C A The default is A C CD ROM 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL SOFTWARE DESCRIPTION PAGE 35 BOOT CPU SPEED Allows the system s boot speed to be set The options are Low and High The optimal setting is High the fail safe is Low If High is selected boot up occurs at full speed If Low 1 selected the board operates at a slower speed approximately equivalent to 25 MHz PC AT Default is low BOOT UP NUM LOCK Allows you to set the start up state of Num Lock on your keyboard The options are and The default is On FLOPPY DRIVE SEEK Set this option to specify fl
21. control to be transfered to segment 0 Control is in segment 0 To check lt gt lt gt key and verify main BIOS checksum either zCTRL2 HOME is pressed or main BIOS checksum is bad go to check point EO else goto check point D7 D7 Main BIOS runtime code is to be decompressed and control to be passed to main BIOS in shadow RAM 01271019 doc Blue Chip Technology Ltd PX1 USER MANUAL ERROR MESSAGES PAGE 75 BOOT BLOCK RECOVERY CODE CHECKPOINTS CODE DESCRIPTION HEX EO On Board Floppy Controller if any is initialised To start base 512K memory test To initialise interrupt vector table To initialise and interrupt controllers To enable floppy and timer IRQ enable internal cache Initialize floppy drive Start looking for a diskette in drive A and read 1st sector of the diskette by AMIBOOT ROM file Flash program successful BIOS is going to restart RUNTIME CODE 15 UNCOMPRESSED IN F000 SHADOW RAM CODE DESCRIPTION HEX 06 POSTcodetobeuncompressed 08 CMOS checksum calculation to be Any initialisation before keyboard BATtobedonenex 12 To init CMOS if Init CMOS in every boot is set or END key is pressed Going to disable DMA and Interrupt controllers 13 Video display is disabled and port B is initialised Chipset init about to begin 14 Blue Chip Technology Ltd 01271019 doc 76 ERROR MES
22. correctly or PnP aware adapter cards installed in your computer will not be configured properly The settings are No or Yes The Optimal and Fail Safe default settings are No PCI BURST MODE Set this option to Enabled to enable PCI burst mode The settings are Disabled or Enabled The Optimal default setting is Enabled The Fail Safe default setting is Disabled PCI CONCURRENCY Set this option to Enable to allow PCI peer to peer cache concurrency Options are Enabled or Disabled The default is Enabled PCI LATENCY TIMER IN PCI CLOCKS This option sets latency of all PCI devices on the PCI bus The settings are in units equal to PCI clocks The settings are 32 64 96 128 160 192 224 or 248 The Optimal and Fail Safe default settings are 64 ALLOCATE IRQ TO PCI VGA Use this option to specify whether the PCI device initialisation code within the BIOS should allocate an IRQ to the PCI VGA controller Setting this option to YES reduces the available IRQ lines to the rest of the system by 1 The options are Yes or No The optimal and fail safe defaults are No 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL SOFTWARE DESCRIPTION PAGE 43 PCI VGA PALETTE SNOOP This option must be set to Enabled if any ISA adapter card installed in the computer requires VGA palette snooping The settings are Disabled or Enabled The Optimal and Fail Safe default settings are Disabled PCI IDE BUS MASTER Set this option to Enabled to
23. default for this is Auto PRIMARY IDE SLAVE This reports if a primary slave IDE hard disk is connected to the system It is configured exactly as described under Primary IDE Master above The default is Not Installed SECONDARY IDE MASTER This reports if a secondary master IDE hard disk is connected to the system It is configured exactly as described under Primary IDE Master above The default is Not Installed SECONDARY IDE SLAVE This reports if a secondary slave IDE hard disk is connected to the system It is configured exactly as described under Primary IDE Master above The default is Not Installed NUMBER OF CYLINDERS If Hard Disk Type is set to User Definable you must type the correct number of cylinders for your hard disk If Hard Disk Type is set to Auto Configured this reports the number of cylinders for your hard disk and cannot be modified Blue Chip Technology Ltd 01271019 doc 34 SOFTWARE DESCRIPTION PX1 UsER MANUAL NUMBER OF HEADS If Hard Disk Type is set to User Definable you must type the correct number of heads for your hard disk If Hard Disk Type is set to Auto Configured this reports the number of heads for your hard disk and cannot be modified NUMBER OF SECTORS If Hard Disk Type is set to User Definable you must type the correct number of sectors for your hard disk If Hard Disk Type is set to Auto Configured this reports the number of sectors for your hard disk and
24. has started and before boot begins A prompt may be enabled that informs users to press the DEL key to access Setup PCI SUPPORT The AMI BIOS supports Version 2 0 of the PCI BIOS specification Support is also provided for Version 1 0 of the PCI bridge specification PCI to PCMCIA bridging can also be supported using third party expansion cards ISA PLUG AND PLAY The AMI BIOS incorporates ISA Plug and Play capabilities as defined by the Plug and Play Release 1 0A specification Plug and Play BIOS Version 1 0A ESCD Version 1 02 This allows auto configuration of Plug and Play ISA cards and resource management for non Plug and Play or legacy ISA cards when used in conjunction with Plug and Play aware operating systems such as Windows 95 AUTO CONFIGURATION CAPABILITIES The auto configuration utility operates in conjunction with the system Setup utility to allow the insertion and removal of PCI and ISA Plug and Play cards to the system without user intervention Plug amp Play When the system is turned on after adding a PCI or ISA Plug and Play card the BIOS automatically configures interrupts DMA channels I O space and memory space The user does not have to configure jumpers or worry about potential resource conflicts Because PCI and ISA Plug and Play cards use the same interrupt resources as ISA cards the user can specify the interrupts used by ISA add in cards in the Setup utility Blue Chip Technology Ltd 0127
25. receive 16 byte FIFO Multi mode bi directional parallel port Standard mode IBM and Centronics compatible Enhanced Parallel Port EPP with BIOS Driver support High Speed mode Extended Capabilities Port ECP compatible e Industry standard floppy controller with 16 byte data FIFO 2 88 MB floppy support e Integrated Real Time Clock Integrated 8042 compatible keyboard controller The 37C932 is normally configured by the BIOS automatically however configuration of these interfaces is possible via the CMOS Setup program that can be invoked during boot up The serial ports can be enabled as COMI 2 or disabled The parallel port can be configured as normal extended EPP ECP or disabled The floppy interface is configurable Header connectors located near the top of the board allow cabling to use these interfaces FLOPPY CONTROLLER The 37C932 is software compatible with the DP8473 and 82077 floppy disk controllers The floppy interface can be configured for 360 KB or 1 2 MB 5 media or for 720 KB 1 44 or 2 88 MB 3 media in the BIOS setup By default the Floppy A interface is configured for 1 44 MB and Floppy B is disabled KEYBOARD INTERFACE PS 2 keyboard mouse connectors are located on the back panel side of the single board PC The 5V lines to these connectors are protected by a fuse Care must be taken to turn off the system power before installing or removing a keyboard or mouse otherwise the fuse may r
26. settings required for the memory size or type which is automatically detected by the system BIOS BUS EXPANSION SLOTS The is designed for use in a passive backplane providing expansion slots for add in cards There may be up to 14 ISA bus expansion connectors and three PCI expansion connectors One slot is shared by both types of connector this is reserved for the PX1 processor card All PCI expansion slots accept PCI bus master cards and fully support the PCI specification version 2 0 In addition the board incorporates a set of PC 104 connectors to allow up to three PC 104 expansion units to be fitted on board without occupying a bus slot in the backplane PCI 3 3 VOLT CAPABILITIES Support for 3 3 Volts to the PCI connectors requires a power supply with a 3 3V DC output The PICMG power connector definition has 3 pins reserved for 3 3V The on board voltage regulator only provides 3 3V or 3 45 or 3 6V to the CPU Triton chipset and cache No other on board resources require 3 3V ELECTROMAGNETIC COMPATIBILITY This product meets the requirements of the European EMC Directive 89 336 EEC and is eligible to bear the CE mark It has been assessed operating in a Blue Chip Technology ICON industrial PC However because the board can be installed in a variety of computers certain conditions have to be applied to ensure that the compatibility is maintained Subject to those conditions it meets the requirements for
27. specify that the IDE controller on the PCI local bus has bus mastering capability The settings are Disabled or Enabled The Optimal and Fail Safe default settings are Disabled OFFBOARD PCI IDE CARD This option specifies if an offboard PCI IDE controller adapter card is used in the computer You must also specify the PCI expansion slot on the motherboard where the offboard PCI IDE controller card is installed If an offboard PCI IDE controller is used the on board IDE controller on the motherboard is automatically disabled The settings are Disabled Auto Slotl Slot2 Slot3 or Slot 4 If Auto is selected AMIBIOS automatically determines the correct setting for this option The Optimal and Fail Safe default settings are Auto In the AMIBIOS for the Intel Triton chipset this option forces IRQ 14 and 15 to a PCI slot on the PCI local bus This is necessary to support non compliant PCI IDE adapter cards OFFBOARD PCI IDE PRIMARY IRQ This option specifies the PCI interrupt used by the primary IDE channel on the offboard PCI IDE controller The settings are Disabled INTA INTB INTC INTD or Hardwired The Optimal and Fail Safe default settings are Disabled OFFBOARD PCI IDE SECONDARY IRQ This option specifies the PCI interrupt used by the secondary IDE channel on the offboard PCI IDE controller The settings are Disabled INTA INTB INTC INTD or Hardwired The Optimal and Fail Safe default settings are Disabled Blue Chip Tech
28. specifying the system peripheral options such as serial and parallel port modes AUTO DETECT HARD DISK Automatically determines the parameters of any IDE devices connected and sets up the parameters for USER DEFINED drives CHANGE USER PASSWORD Allows the password for the user level options to be set or changed This option cannot be changed unless a supervisor password has been set CHANGE SUPERVISOR PASSWORD Allows the password for the supervisor level options to be changed 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL SOFTWARE DESCRIPTION PAGE 31 AUTO CONFIGURATION WITH OPTIMAL SETTINGS Resets the CMOS setup options to a high performance configuration The optimal default settings are best case values and should optimise the system performance If CMOS RAM is corrupted the optimal settings are loaded automatically AUTO CONFIGURATION WITH FAIL SAFE SETTINGS Resets the CMOS setup options to a lower performance but guaranteed working configuration The fail safe settings provide far from optimal system performance but are the most stable settings Use these settings as an diagnostics aid if the system is performing erratically SAVE SETTINGS AND EXIT When selected this allows you to save the change to CMOS and exit the Setup program You can also press the F10 key anywhere in the Setup program to do this EXIT WITHOUT SAVING When selected this allows you to exit the Setup program without sav
29. the POST IDE LED Two pins of header P9 pins 13 amp 14 may be connected to an LED to provide a light when an IDE hard drive connected to the on board IDE controller is active SLEEP RESUME SWITCH Two pins of header P9 pins 11 amp 12 may be connected to a momentary action normally open SPST switch The switch may be used to toggle the PC in and out of SMM modes i e Sleep Resume Blue Chip Technology Ltd 01271019 doc 22 HARDWARE DESCRIPTION PX1 UsER MANUAL BUS CONNECTORS The board incorporates the standard PC AT 16 bit ISA bus and PCI bus connectors to passive backplanes Additionally the board has one set of 04 sockets for on board expansion See the appendices for the pin out details Note that the PCI connector details the signals at the 1 processor connector These are different for each PCI slot on a backplane JUMPERS Jumpers are used on the board to select various options Some of the jumpers are factory set to suit particular semiconductor options These must not be disturbed or damage to the board may ensue Refer to the board layout drawing at the end of the manual for the positions of the various jumpers CPU FREQUENCY SELECTION J1 amp J11 The external CPU bus operates at frequencies of 50 60 and 66 MHz but is scaled up internally giving a range of CPU frequencies of 75 to 166 MHz There are four links in two locations involved in CPU frequency selection J1 and J11
30. 07H GET HARDWARE IO BASE ADDRESS This function returns the value of the locatable hardware IO base address Input parameters 07h Return values AX Hardware IO Base address AH 08H GET BIOS EXTENSION VERSION This function returns the BIOS extension version number Input parameters AH 08h Return values AH Major version number AL Minor revision number Blue Chip Technology Ltd 01271019 doc 56 PX1 UsER MANUAL APPENDICES ADDRESS MAPS MEMORY MAP RANGE RANGE DESCRIPTION DECIMAL HEX not available for UMB open to ISA and PCI bus BIOS moveable by QEMM 386MAX VO MAP The following table lists the I O addresses used by single board PC devices Some of these devices e g graphics may not be present in all configurations Some devices serial ports parallel ports etc may be configured for various addresses or disabled These I O locations are listed in the Variable Resources column 01271019 doc Blue Chip Technology Ltd PX1 USER MANUAL APPENDICES PAGE 57 HEX B yes RESOURCES 0000 000F PIIX DMA 1 0020 0021 PIIX Interrupt Controller 1 002E 002F Ultra configuration registers 0040 0043 PIIX Timer 1 0060 Keyboard Controller Data Byte 0061 PIIX NMI speaker control 0064 Kbd Controller CMD STAT Byte 0070 bit 7 i PIIX Enable NMI 0070 bits 6 0 i 87C307PIIX RTC Address 0071 87C307PIIX RTC Data 0080 008F PIIX DMA Page Register 00A0 00A1 PI
31. 1019 doc 18 HARDWARE DESCRIPTION PX1 UsER MANUAL If using Windows M 95 the auto configuration utility only initialises the devices required to boot up Windows 95 initialises all the other devices since it is a Plug and Play aware operating system ADVANCED POWER MANAGEMENT The PX1 AMI BIOS supports power management through System Management Mode SMM interrupts to the CPU and Advanced Power Management APM Version 1 1 In general power management capabilities will allow the system to be put into a power managed Stand by mode either by entering a user configurable hot key sequence on the keyboard or by the expiration of a hardware timer which detects system inactivity for a user configurable time When in the Stand by mode the single board PC reduces power consumption by using the power saving capabilities of the Pentium processor and also running down hard drives and turning off DPMS compliant monitors Add in cards supplied with APM aware drivers can also be put into a power managed state for further energy savings The ability to respond to external interrupts is fully maintained while in Stand by mode allowing the system to service requests such as in coming Fax s or network messages while unattended albeit slowly until the system wakes up SLEEP MODE SUPPORT When Advanced Power Management APM is activated in the System BIOS and the Operating System s APM driver is loaded Sleep mode Stand By can be ente
32. 1271019 doc 66 PX1 UsER MANUAL SECURITY MONITOR MICROCONTROLLER P10 10 WAY HEADER Reserved for future use Ext Temp Sensor Signal Ext Temp Sensor Ground Fault LED Ext Temp Sensor 5 V Serial Security Key l p 6 Ground 7 8 Ground 9 No Connect 10 Grud VESA VIDEO FEATURE CONNECTOR P11 26 PIN HEADER PINNO SIGNAL PINNO SIGNAL Ground 6 2 5 Enable Video 8 DaaPs 13 Rea 1 Data P6 Data P7 Pixel Clock 25 Bue Blue Ground COAST CACHE CONNECTOR P16 This is an industry standard connector for Cache On A Stick The COAST connector is a 160 pin socket which is designed to prevent reversed fitting of the cache module Please note that each cache module is designed specifically for each chipset i e there are cache modules specific to the 430FX Triton chipset The available options for the PX1 cache are 256kbyte asynchronous 256 or 512KByte of synchronous Pipeline burst or none 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL APPENDICES PAGE 67 BATTERY CONNECTOR P17 4 WAY HEADER Signa O 43 6 Volts DC Not used ke BUS CONNECTORS ISA BUS XT CONNECTIONS Large gold fingers on main component side B Large gold fingers on reverse side PINNO SIGNAL PINNO SIGNAL 65 B IiQ9 6 DRE X A9 fsbo B
33. A connection to a monitor was not detected short Refresh Failure The memory refresh circuitry on the single board PC is faulty Parity is not supported on this product will not occur Failure Memory failure in the first 64 KB of memory or Operational Timer 1 on the single board PC is not functioning The CPU on the single board PC generated an error m The keyboard controller 8042 may be bad The Failure BIOS cannot switch to protected mode Interrupt Error UN oll System video adapter is either missing or its memory Read Write Error is faulty This is not a fatal error EUN ou Error encoded in BIOS 10 CMOS Shutdown The shutdown register for CMOS RAM failed Register Rd Wrt Error External Cache Bad Blue Chip Technology Ltd 01271019 doc 74 ERROR MESSAGES PX1 UsER MANUAL AMIBIOS ERROR CODES ON THE POST DISPLAY As the BIOS performs the POST after a reset or reboot the microprocessor indicates the status of the test by writing codes to the I O port at address 80 Hex The unit provides an on board decode of this information displaying the code on on board LEDs It can also drive an optional POST display without modification The following codes indicate the progress of the microprocessor during the power on test UNCOMPRESSED INIT CODE CHECKPOINTS HEX RU EUM starting going to 4GB flat mode To start Memory sizing E000 ROM enabled Init code is copied to segment 0 and
34. ADER PINN SIGNAL SIGNAL 4 Error Initialise Select input Ground 11 Ground 13 Ground 15 Ground 17 Ground 19 20 Ground 2 3 22382 71 15 17 A 2 Ground 2 Ground Select Output Not Used IN SYSTEM EPLD PROGRAM P7 6 WAY HEADER Reserved for manufacturing use only No user connection PIN NO SIGNAL PIN NO SIGNAL JTAG Test Clock JTAG Test Data Out JTAG Test Mode Select 5 Volt JTAG Test Data In 6 Ground 01271019 doc Blue Chip Technology Ltd Blue Chip Technology Ltd PX1 UsER MANUAL APPENDICES PAGE 65 SECONDARY IDE CONNECTOR P8 40 WAY HEADER PINNO SIGNAL PINNO SIGNAL Data bit 7 HD Data bit 8 HD Data bit 6 HD 6 Data bit 9 HD Data bit 5 HD Data bit 10 HD Data bit 4 HD Data bit 11 HD Data bit 3 HD Data bit 12 HD 13 Data bit 2 HD Data bit 13 HD 15 Data bit 1 HD Data bit 14 HD 17 Data bit 0 HD Data bit 15 HD 19 Ground 21 Drive Request 23 IO Write HD 25 IO Read HD 27 Drive Read 29 Drive Acknowledge 31 IRQ15 33 Address 1 HD 13 15 2 23 25 29 33 UTILITY CONNECTOR P9 20 WAY HEADER SIGNAL 5 HighSpeedLED ve 6 HighSpeedLED ve 7 Keyocksve 8 Keylock ve Ground 9 PowerlED ve 10 PowerLED ve Ground 0
35. I O register located at OCFCh The PCI Configuration Address register is only accessible by a DWORD access the PCI Configuration Data register is accessible by DWORD WORD or BYTE accesses ACCESS CONFIGURATION SPACE USING MECHANISM 1 1 Using a DWORD write command output the required I O configuration address to I O port CF8H 2 Using a DWORD read or write command read or write data from the I O port CFCH NOTE Any address output to CF8H is always on a 4 byte DWORD boundary You can read or write any BYTE WORD or DWORD in the four byte range by using the correct offset as follows DWORD CFCh WORD CFCh or CFEh BYTE CFDh CFEh or CFFh CONFIGURATION ADDRESS REGISTER BIT DEFINITION FUNCTION SETTING FUNCTION NUMBER REGISTER NUMBER 1 CONFIG SPACE ENABLE FLAG Bit 31 Always to indicate access 15 to configuration space RESERVED Bits 30 24 Always 00h 01271019 doc Blue Chip Technology Ltd PX1 USER MANUAL APPENDICES PAGE 59 BUS NUMBER Bits 23 16 Always 00h unless a bridge card is installed in a PCI slot DEVICE NUMBER Bits 15 11 Used to indicate a specific PCI device The Triton TSC has a predefined device number of 00000h The PIIX and four PCI slots also have specific device numbers that device number is determined by which PCI Address Data line is connected to the device s ID SEL pin Table E 1 details the specific mapping information FUNCTION NUMBER Bit
36. IX Interrupt Controller 2 0082 0083 Control Status Interrupt Controller 2 00 0 00DE PIIX DMA 2 00 0 Reset Numeric Error 0100 0107 Reserved for Board Confign 0170 0177 Secondary IDE Channel 01F0 01F7 Primary IDE Channel 0200 0207 Gameport Joystick 0278 027B Parallel Port 2 02 8 02 Serial Port 4 02 8 0O2FF Serial Port 2 0376 Sec IDE Chan Cmd Port 0377 Sec IDE Chan Stat Port 0378 037F Parallel Port 1 0380 03 53 Trio64V Parallel 3 03 0 03DF S3 Trioc4V 8 Serial 3 03 5 Floppy Channel 1 03 6 IDE Chan Cmnd OSF7 Write Floppy Chan 1 Cmd 03F7 bit 7 i Floppy Disk Chg Chan 1 03F7 bits 6 0 i Pri IDE Chan Status Port OSF8 Serial Port 1 LPT 400h ECP regs LPT base 400h 0400 0401 Edge Level INTR Control Reg OCF8 PCI Config Address Reg OCF9 Turbo amp Reset control Reg OCFC OCFF PCI Config Data Reg FFAO FFA7 tary Bus MasterIDE regs FFA8 FFAF 2ary Bus Master IDE regs FFOO FFO7 IDE Bus Master Reg only accessible by DWORD accesses Blue Chip Technology Ltd 01271019 doc 58 PX1 UsER MANUAL PCI CONFIGURATION SPACE MAP The Triton chipset uses Configuration Mechanism 1 to access the PCI configuration space The PCI Configuration Address register is a 32 bit I O register located at OCF8h the PCI Configuration Data register is a 32 bit
37. Link J11 selects the host CPU operating frequency of 50 60 and 66 MHz Link selects the clock scaling multiplying factor Link J1 is latched by the CPU on reset and used to configure the CPU phase locked loop oscillator This allows higher speed processors to be clocked down e g running a P133 as a P100 but over clocking processors is not recommended as it will degrade the reliability of the device over time Note also that there are internal differences between each of the CPU types i e there are register differences between a P100 and a P133 it is not simply silicon grading as was the case for 486 type CPUs INTERNAL CPU CLOCK SPEED J1 These jumpers sets the internal CPU clock speed to either 1 2 2 or 3 times that of the external CPU clock speed These jumpers should be configured depending on the speed of the processor 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL HARDWARE DESCRIPTION PAGE 23 CPU CLOCK PAIR PAIR MULTIPLIER A B EXTERNAL CPU CLOCK SPEED J11 This jumper block sets the CPU s external operating frequency to memory at 50 60 or 66 MHz The default setting depends on the specific memory and type of Pentium processor installed It is used in conjunction with EXTERNAL PAIR PAIR BUS FREQ A B SUMMARY OF LINK SETTINGS HOST CLK J1 J1 J11 J11 SCALING A B A B FACTOR 90 6 30 15 Open Open Link Open 100 66 15 Open Open Open Link 120 60
38. M in the form of a COAST Cache On A STick Module The memory sub system is designed to support up to 128 MB of EDO DRAM for improved performance or standard Fast Page DRAM in standard 72 pin SIMM sockets Type 7 Pentium OverDrive socket provides upgrades for future OverDrive processors PXI single board PC utilises Intel s Triton 82430 to provide increased integration and performance over other single board PC designs The Triton PCIset contains an integrated PCI Bus Mastering IDE controller with two high performance IDE interfaces allowing up to four IDE devices such as hard drives CD ROM readers etc The SMC 37C932 Super I O controller integrates the standard PC I O functions floppy interface two FIFO serial ports one EPP ECP capable parallel port a Real Time Clock keyboard and mouse PS 2 controller The also provides for driving up to three external PCI local bus slots These provide a high bandwidth data path for data movement intensive functions such as video or networking Up to fourteen ISA slots may be driven to complete the I O capability In addition to superior hardware capabilities a full set of software drivers and utilities are available to allow advanced operating systems such as Windows 95 to take full advantage of the hardware capabilities Features such as bus mastering IDE Windows 95 ready Plug and Play Advanced Power Management are available for the PX1 Blue
39. Main menu screen In each screen there are options for modifying the system configuration Select a sub menu screen by pressing the up T or down arrow keys followed by Enter Within the menu use the up T or down lt gt keys to select an item then use lt PgUp gt or lt PgDn gt to modify it For certain items pressing Enter will bring up a subscreen After you have selected an item use the lt PgUp gt or lt PgDn gt keys to modify the setting MAIN SCREEN Shows the following menu Standard Setup Advanced CMOS Setup Advanced Chipset Setup Power Management Setup PCI PnP Setup Peripheral Setup Auto Detect Hard Disk Change User Password Change Supervisor Password Auto Configuration with Optimal Settings Auto Configuration with Fail Safe Settings Save Settings and Exit Exit without Saving Blue Chip Technology Ltd 01271019 doc 30 SOFTWARE DESCRIPTION PX1 UsER MANUAL Their operation is as follows STANDARD SETUP For setting up and modifying basic items such as floppy disk drives hard drives and system time amp date ADVANCED CMOS SETUP For modifying the more advanced features of the PC e g system bootup options ADVANCED CHIPSET SETUP For modifying hardware level options POWER MANAGEMENT SETUP For specifying the Green PC features such as IDE and VGA timeouts PCI PNP SETUP For specifying Plug and Play options e g IRQ assignments PERIPHERAL SETUP For
40. O HA Volts 4 SA7 TOR A2 569 2 IRQS Blue Chip Technology Ltd 01271019 doc 68 PX1 UsER MANUAL ISA BUS AT CONNECTIONS C Large gold fingers on main component side Large gold fingers on reverse side PINNO SIGNAL PINNO SIGNAL ce La pe 5 ce Larz co MEMR po 0 01271019 doc Blue Chip Technology Ltd PX1 USER MANUAL APPENDICES PAGE 69 PC104 PC XT CONNECTOR P20 64 WAY SOCKET SIDEA SIGNAL SIDEB SIGNAL 12 Volts Blue Chip Technology Ltd 01271019 doc 70 APPENDICES PX1 USER MANUAL PC104 PC AT CONNECTOR P19 40 WAY SOCKET SIDEC SIGNAL SIDED SIGNAL 6 6 2 8 _ 0 RQ 9 arz 9 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL APPENDICES PCI CONNECTORS PIN SIGNALNAME PIN SIGNALNAME A4 A 6 A7 PCIINT1 B7 gt o oo A16 A17 A18 A19 A20 21 2 2 25 26 28 29 1 A32 A34 A35 A37 A38 A40 A41 42 A43 A44 A46 A47 A48 A49 M 7 8 9 2 13 AIS Ate A17 A18 9 A20 A21 A22 A23 A25 A26 A28 A29 AS A32 A34 A35
41. SAGES PX1 UsER MANUAL CODE DESCRIPTION HEX BIOS code segment writeable memory R W test retrace checking Video display checking over Display mode to be set next Display mode set Going to display the power on message the total system memory size for writing patterns to test memory base 640k memory below 1M memory of memory above 1M memory 4B Amount of memory above 1M found and verified Check for soft reset and going to clear memory below 1M for soft reset If power on go to check point 4Eh Memory below 1M cleared SOFT RESET Going to clear memory above 1M 4D Memory above 1M cleared SOFT RESET Going to save the memory size Goto check 52h memory size 4F Memory size display started This will be updated during memory test Going for sequential and random memory test Memory test started NOT SOFT RESET About to display the first 64k 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL ERROR MESSAGES PAGE 77 CODE DESCRIPTION Memory testing initialisation below 1M complete Going to adjust displayed memor Size for relocation shadow 1M to follow information Memory size information is saved CPU registers are saved Going to enter in real mode 54 Shutdown successful CPU in real mode Going to disable gate A20 line and disable parity NMI 4 d line parity NMI disable successful Going to adjust memory ding relocation shadow size adjusted for relocation sha
42. Y The PX1 single board PC provides four 72 pin SIMM sites for memory expansion The sockets support 1M x 32 4 MB 2M x 32 8 MB 4M x 32 16 MB and 8M x 32 32 MB single sided or double sided SIMM modules Minimum memory size is 8 MB and maximum memory size using four 8M x 32 SIMM modules is 128 MB Memory timing requires 70 ns fast page devices or for optimum performance 601 EDO DRAM If the memory bus speed is 60 MHz or slower 75MHz 90MHz 120MHz 150MHz or 180MHz Pentium Processor speed 70ns EDO DRAM may be used If the memory bus speed is 66 MHz 60 ns DRAM should be used Additionally 36 bit SIMM modules may be used but parity generation and checking are not supported EDO DRAM is designed to improve DRAM read performance The four sockets identified as SIMM 1 2 3 amp 4 on the PCB layout diagram at the end of the manual are arranged as Bank A and Bank B Blue Chip Technology Ltd 01271019 doc 8 USER GUIDE PX1 UsER MANUAL Each bank consists of two sockets providing a 64 bit wide data path Both SIMMs in a bank must be of the same memory size and type although the memory type and size may be different between Banks A and B It is even possible to have 70 ns Fast Page DRAM one bank and 60 ns EDO DRAM in the other in which case each bank is independently optimised for maximum performance At least one Bank must be populated Bank A only Bank B only or both banks may be populated There are no jumper
43. an industrial environment Class A product 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL USER GUIDE PAGE 9 The board must be installed in a computer system chassis which provides screening suitable for the industrial environment Any recommendations made by the computer system manufacturer supplier must be complied with regarding earthing and the installation of boards The board must be installed with the backplate securely screwed to the chassis of the computer to ensure good metal to metal i e earth contact Most EMC problems are caused by the external cabling to boards It is imperative that any external cabling to the board is totally screened and that the screen of the cable connects to the metal end bracket of the board and hence to earth It is recommended that round screened cables with a braided wire screen are used in preference to those with a foil screen and drain wire Use metal connector shells which connect around the full circumference of the screen they are far superior to those which earth the screen by a simple pig tail The keyboard will play an important part in the compatibility of the processor card since it is a port into the board Similarly it will affect the compatibility of the complete system fully compatible keyboard must be used otherwise the complete system could be degraded The keyboard itself may radiate or behave as if keys are pressed when subject to interference
44. ard and mouse operation will be locked until the User Password is entered See the Security Menu section of the appendix for more details If the password is forgotten it can be cleared by turning off the system and clearing the CMOS RAM CONNECTORS Three sets of connectors are incorporated on the PX1 PC board These provide connectivity to standard external peripherals monitor keyboard etc in chassis peripherals disk drives etc and bus devices A complete table of the available connectors and their pin outs is given in the appendices The PC board layout at the end of the manual shows their positions BACK PANEL CONNECTORS The back panel provides external access to the VGA PS 2 mouse keyboard and the first serial communications port interfaces All the connectors follow the industry standard The diagram shows the general location of the connectors Blue Chip Technology Ltd 01271019 doc 20 HARDWARE DESCRIPTION PX1 USER MANUAL 9 12 00000 Oo PS 2 Mouse P13 RS232 Serial 1 P15 0000 o 9 o 5 2 Keyboard P18 ON BOARD CONNECTORS There are connectors on board for Floppy Disk Drive IDE and VESA feature connector There are also sockets for graphics memory upgrade if graphics is present SIMMs and external battery Connectors are provided for the following peripheral
45. atch CMOS Memory Size Mismatch CMOS Time and Date Not Set Diskette Boot Failure Display Switch Not Proper DMA Error 1 Error 2 Controller Failure HDD Controller Failure INTR 1 Error INTR 2 Error Invalid Boot Diskette Keyboard Is Locked Unlock It Keyboard Error KB Interface Error Off Board Parity Error On Board Parity Error Parity Error 01271019 doc Cache memory is defective Replace it Most AT systems include two timers There is an error in timer 2 CMOS RAM is powered by a battery The battery power is low Replace the battery After CMOS RAM values are saved a checksum value is generated for error checking The previous value is different from the current value Run AMIBIOS Setup The values stored in CMOS RAM are either corrupt or non existent Run Setup The video type in CMOS RAM does not match the type detected by the BIOS Run AMIBIOS Setup The amount of memory on the single board PC is different than the amount in CMOS RAM Run AMIBIOS Setup Run Standard CMOS Setup to set the date and time in CMOS RAM he boot disk in floppy drive A is corrupt It cannot be used to boot the system Use another boot disk and follow the screen instructions The display jumper is not implemented on this product this error will not Error in the second channel The BIOS cannot communicate with the floppy disk drive controller Check all appr
46. bus frequency The default setting for this jumper is Linked In general this jumper should only be removed if higher ISA performance is required and the ISA expansion cards can handle the faster bus clock A clock frequency of greater than 8 33 MHz violates the ISA specification although many ISA cards are designed to support higher clock frequencies ISA BUS SPEED BUS FREQUENCY JUMPER LINKED JUMPER OPEN 8 6 50 MHz 6 25 MHz 8 33 MHz 60 MHz 7 5 MHz 10 MHz 66 MHz 8 33 MHz 11 MHz MMX SETTINGS J10 If an MMX CPU is used the links 710 x 3 must be set to Classic pentiums must use the standard setting 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL HARDWARE DESCRIPTION PAGE 25 TABLE OF JUMPERS JUMPER AREA OF INFLUENCE ACTION LINK Selects the internal CPU clock A External CPU speed x1 5 L 2 L L x2 5 L Speed COM 2 5485 Termination None Unterminated Link Terminated by 100R u1 Use in conjunction with J11 EDO Extended Data Out Memor 5V 5 Volt Default On board video select None Link BIOS Memory Type CPU Core Voltage Select 3 6 CPU I O Voltage Select VRT 3 links STD Select External Bus Frequency Use in conjunction with J1 Selects ISA Bus Speed Bus speed depends on Bus 77 Frequency CMOS Battery Support None Link J1 J2 J3 J4 J5 J6 Selects BIOS ROM Type J9 J10 J11 J12 J13 None CLR On board Speaker None Disabled Li
47. configuration This information is preliminary and is provided only as a guide to calculating approximate total system power usage when additional resources are added 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL HARDWARE DESCRIPTION PAGE 11 HARDWARE DESCRIPTION PERIPHERAL COMPONENT INTERCONNECT PCISET The Intel Triton 82430FX PCIset consists of the 82437FX Triton System Controller TSC two 82438FX Triton Data Path TDP devices and one 82371FB PCI ISA IDE Accelerator PIIX bridge chip The Triton PCIset provides the following functions CPU interface control Integrated L2 write back cache controller Pipelined Burst SRAM 256KB or 512KB Direct Mapped Integrated DRAM controller 64 bit path to Memory Support for EDO and Fast Page DRAM 8 MB to 128 MB main memory Fully synchronous PCI bus interface 25 30 33 MHz PCI to DRAM gt 100 MBytes sec PCI to DRAM posting of 12 Dwords 5 Dword buffers for CPU to PCI write posting 4 Dword buffers for PCI to Memory bus master cycles Support for up to 5 PCI masters Interface between the PCI bus and ISA bus Integrated fast IDE interface Support for up to 4 devices Mode 4 transfers up to 16MB sec Integrated 8 x 32 bit buffer for PCI IDE burst transfers Enhanced Fast DMA controller Interrupt controller and steering Counters Timers SMI interrupt logic and timer with Fast On Off mode Note N
48. dicates the system reset status The LED is illuminated when in held in reset MONITOR MICROCONTROLLER STATUS Yellow LED D2 indicates the status of the monitor microcontroller if fitted The LED is illuminated when a fault condition has occurred WATCHDOG TIMER STATUS Yellow LED D1 indicates the watchdog time out status The LED is illuminated when a timeout has occurred 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL HARDWARE DESCRIPTION PAGE 27 USER INSTALLABLE UPGRADES SYSTEM MEMORY The table shows the possible memory combinations The PX1 will support both Fast Page DRAM or EDO DRAM SIMMs but they cannot be mixed within the same memory bank If Fast Page DRAM and EDO DRAM SIMMs are installed in separate banks each bank will be optimised for maximum performance Parity generation and detection are NOT supported but parity SIMMs x36 may be used SIMM requirements are 70ns Fast Page Mode or 6015 EDO DRAM 70 ns EDO may be used with a 60 MHz or slower external CPU clock with tin lead connectors SIMM TYPE AMOUNT SIMM TYPE AMOUNT MEMORY Note SIMMs may be parity x 36 or non parity x 32 Blue Chip Technology Ltd 01271019 doc 28 HARDWARE DESCRIPTION PX1 UsER MANUAL EDO DRAM Extended Data Out or Hyper Page DRAM is designed to improve the DRAM read performance EDO DRAM holds the memory data valid until the next CAS falling edge unlike standard fast page mode DRAM which tri state
49. ditions of Sale Blue Chip Technology Ltd 01271019 doc 2 INTRODUCTION PX1 USER MANUAL PRECAUTIONS It is imperative that precautions are taken to avoid electro static discharges or any maltreatment of the on board battery ELECTRO STATIC DISCHARGES The devices on this card can be totally destroyed by static electricity Ensure that you take necessary static precautions ideally wear an approved wrist strap or touch a suitable ground to discharge any static build up This should be repeated if the handling is for any length of time When carrying the board around please place it into the non conductive bag in which it came This will prevent any static electricity build up ON BOARD BATTERY This board is fitted with a Lithium battery Great care should be taken with this type of battery Under NO circumstances should the outputs be shorted be exposed to temperatures in excess of 100 C be burnt e be immersed in water e be unsoldered e be recharged be disassembled If the battery 1 mistreated in any way there is a very real possibility of fire explosion and harm 01271019 doc Blue Chip Technology Ltd PX1 USER MANUAL INTRODUCTION PAGE 3 RELATED PUBLICATIONS The following publications will provide useful information related to the Standard Personal Computer and can be used in conjunction with this manual e IBM Personal Computer AT Technical Reference 1502494 IBM 1984 e IBM Perso
50. dow C400 16K Shadow C800 16K Shadow 00 16K Shadow D000 16K Shadow D400 16K Shadow D800 16K Shadow 00 16K Shadow These options control the location of the contents of the 16KB blocks of ROM beginning at the specified memory location If no adapter ROM is using the named ROM area this area is made available to the local bus Blue Chip Technology Ltd 01271019 doc 38 SOFTWARE DESCRIPTION PX1 UsER MANUAL The settings are The contents of 0000 C3FFFh are written to the same address in system memory RAM for faster execution Cache The contents of the named ROM area are written to the same address in system memory RAM for faster execution if an adapter ROM will be using the named ROM area Also the contents of the RAM area can be read from and written to cache memory Disabled The video ROM is not copied to RAM The contents of the video ROM cannot be read from or written to cache memory The default setting is Cache for C000 and C400 disabled for the remainder In the AMIBIOS for the Intel Triton chipset the E000h page is used as ROM during POST but shadowing is disabled and the ROM CS signal is disabled to make the E000h page available on the local bus ADVANCED CHIPSET SETUP MEMORY HOLE Use this option to specify an area in memory that cannot be addressed on the ISA bus The settings are Disabled 512 640K or 15 16MB The default setting 1s Disabled INSTALLED MEMORY Use t
51. dow Going to clear Hit lt DEL gt message Hit DEL message cleared WAIT message displayed About to start DMA and interrupt controller test page register test passed To do 1 base register test DMA 1 base register test passed do DMA 2 base register test DMA 2 base register test passed To program DMA unit 1 and 2 DMA unit 1 and 2 programming over To Initialize 8259 interrupt controller Extended NMI sources enabling is in progress Keyboard test started clearing output buffer checking for stuck key to issue keyboard reset command Keyboard reset error stuck key found To issue keyboard controller interface test command Keyboard controller interface test over To write command byte and init circular buffer Command byte written Global data init done To check for lock key Lock key checking over To check for memory size mismatch with CMOS Memory size check done To display soft error and check for password or bypass setup Password checked About to do programming before setup Programming before setup complete To uncompress SETUP code and execute CMOS setup Returned from CMOS setup program and screen is cleared About to do programming after setup Programming after setup complete Going to display power on screen message First screen message displayed WAIT message displayed PS 2 Mouse check and extended BIOS data area allocation to be done Setup options programm
52. drawn from the PICMG supply to extend the life of the battery S3 GRAPHICS SUBSYSTEM The PXI single board PC is provided with an S3 Trio64V SVGA graphics controller with 1 MB of graphics memory upgradeable to 2 MB The graphics DRAM can be upgraded to 2 MB by installing two 256kB x 16 SOJ memory devices in the provided sockets The Trio64V has a 64 bit graphics engine that provides acceleration for scaling the video display without compromising picture quality or frame rate The on chip RAMDAC clock synthesiser is capable of output pixel data rates of 135 MHz providing non interlaced screen resolutions of up to 1280 x 1024 x 256 colours at 75 Hz with 2MB of DRAM Blue Chip Technology Ltd 01271019 doc 16 HARDWARE DESCRIPTION PX1 UsER MANUAL Hardware acceleration for graphics functions such as BitBLTs with ROPs 2 point line draws trapezoidal and polygon fills clipping and cursor support provide high performance operation under Windows and other GUI environments In addition a fast linear addressing scheme reduces the software overhead by mapping the display memory into the CPU s upper memory address space and allowing direct CPU access to the display memory The PXI single board PC supports the 26 pin VESA feature connector for synchronising graphics output with an external NTSC or PAL signal and a shared frame buffer interface to maximise multi media performance PXI also supports other VESA standards such as the VESA DPMS pr
53. functions 01271019 doc Second serial comms port RS232 and RS485 Parallel port Floppy disk drives Primary and secondary IDE devices Blue Chip Technology Ltd PX1 UsER MANUAL HARDWARE DESCRIPTION PAGE 21 In addition connectors provide for e An external battery for battery backed SRAM installations Power supply connection for stand alone no backplane applications e Front panel components switches LED speaker etc This utility connector is described in more detail below e On board programming of the EPLD This is for manufacture only and is not a user connection UTILITY CONNECTOR The PX1 PC board provides connectors to support functions which would normally be located within the enclosure and also duplicate connections for some of the external interfaces System Speaker System Reset Switch Keyboard Power LED Hard Drive Activity LED an External Battery and a Sleep Resume switch SPEAKER An on board Piezo speaker is included It may be disabled by removing a link on jumper J3 An off board speaker may be connected to the header P9 pins 1 amp 2 and driven independently of the on board buzzer The speaker provides error beep code information during the Power On Self Test if the system cannot use the video interface RESET Two pins of header P9 pins 3 amp 4 may be connected to a momentary normally open SPST switch When the switch is closed the system will perform a hard reset and run
54. he DiskOnChip operate as a standard disk drive The DiskOnChip 2000 can contain the operating system in it to allow systems to boot without a hard disk The DiskOnChip 2000 can also be configured as the boot device in systems with a hard disk see below Configuring the DiskOnChip 2000 as the first drive The DiskOnChip is a self contained device The installation of the DiskOnChip does not require any software installation The design of the DiskOnChip allows for full upward and downward compatibility While available today in capacities of 2 to 72MBytes future DiskOnChip devices with higher densities will be fully compatible with standard DiskOnChip sockets The basic design of the DiskOnChip actually supports an unlimited capacity Blue Chip Technology Ltd 01271019 doc 50 SOFTWARE DESCRIPTION PX1 UsER MANUAL 2 OPERATING THE DISKONCHIP 2 1 INSTALLING THE DISKONCHIP 2000 When installing or removing the DiskOnChip be sure to first touch a grounded surface to discharge any static electricity from your body Use the following procedure to install the DiskOnChip Align pin 1 on the DiskOnChip with pin 1 of Flash socket Push the DiskOnChip into the socket carefully until it is fully seated Check to make sure the DiskOnChip is installed securely and there are no bent pins Caution The DiskOnChip may be permanently damaged if installed incorrectly To install the DiskOnChip as drive C on a system without a hard dis
55. hieve transfer rates of approximately 2 5Mbs ECP provides symmetric bi directional communications 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL SOFTWARE DESCRIPTION PAGE 47 PARALLEL PORT IRQ Selects which IRQ is assigned to the parallel port Available options are Auto 5 or 7 The default is Auto PARALLEL PORT DMA This option 15 only available if the setting for the Parallel Port Mode option is ECP The settings are Auto None DMA CH 0 DMA CH 1 DMA CH 2 or CH 3 channel The default setting is Disabled HARDWARE IO PORT BASE ADDRESS This specifies the base address of the configuration and control registers The permissible options are 100 hex 300 hex 400 hex 500 hex 600 hex 700 hex 800 hex 900 hex A00 hex BOO hex C00 hex DOO hex E00 hex and FOO hex Note the absence of 200 hex in the list The default is 100 hex SERIAL PORT 2 MODE Specifies whether the second serial port will be used as RS232 or RS485 Options are RS232 and RS485 The optimal and fail safe defaults are RS232 RS485 DUPLEX MODE Specifies whether the second serial port will be used as full or half duplex when running in RS485 mode This option is only available when the options Serial Port 2 Mode is set to RS485 The options are FULL or HALF The Optimal and Fail Safe defaults are FULL FEATURE CONNECTOR Specifies whether the S3 feature connector is enabled or disabled The options are E
56. his option to specify the total amount of memory installed in the system when using the memory hole This option should ONLY be used with OS 2 The options are Disabled 32MB and 64MB The optimal and fail safe defaults are Disabled DRAM SPEED Specify the RAS access speed of the SIMMs installed in the motherboard as system memory The settings are 60nS or 70nS The default is 70nS 01271019 doc Blue Chip Technology Ltd PX1 USER MANUAL SOFTWARE DESCRIPTION PAGE 39 Caution If you have installed SIMMs with different speeds in the motherboard select the speed of the slowest SIMM You must always use SIMMs that have the same speed within each memory bank IRQ12 M MOUSE FUNCTION Set this option to Enabled to specify that IRQ12 will be used for the mouse The settings are Disabled or Enabled The Optimal and Fail Safe default settings are Enabled 8 BIT RECOVERY TIME SYSCLK This option specifies the length of the delay in units of SYSCLKs inserted between consecutive 8 bit I O operations The settings are 1 2 3 4 5 6 7 or 8 the Optimal and Fail Safe default settings are 8 16 BIT RECOVERY TIME SYSCLK This option specifies the length of the delay in SYSCLKs inserted between consecutive 16 bit I O operations The settings are 1 2 3 4 5 6 7 or 8 The Optimal and Fail Safe default settings are 4 POWER MANAGEMENT SETUP POWER MANAGEMENT APM Set this option to Enabled to enable the power management and APM
57. ing any changes This means that any changes made while in the Setup program will be discarded and NOT SAVED Pressing the Esc key in any of the four main screens will do this Blue Chip Technology Ltd 01271019 doc 32 SOFTWARE DESCRIPTION PX1 UsER MANUAL OVERVIEW OF THE SETUP KEYS SETUP KEY DESCRIPTION F1 Pressing the F1 key brings up a help screen for the currently selected item Esc Pressing the Esc key takes you back to the previous screen Pressing it in the Main Advanced Security or Exit screen allows you to Exit Discarding Changes see later in this chapter lt PgUp gt Pressing either key moves the selection of the current item up or down lt PgDn gt the available options Pressing the up key changes the selection to the previous item or option Pressing the down key changes the selection the to the next item or option lt gt lt gt gt Pressing the left lt lt gt or right lt gt keys in the Main Advanced Security or Exit menu screens changes the menu screen Pressing either key in a subscreen does nothing Pressing the lt F5 gt key allows you to Load Setup Defaults see later in this chapter Pressing the lt F6 gt key allows you to Discard Changes see later in this chapter Pressing the lt F10 gt key allows you to Exit Saving Changes see later in this chapter STANDARD SETUP This section describes the Setup options found on the standard set
58. ing after CMOS setup about to start Going for hard disk controller reset Hard disk controller reset done Floppy setup to be done next Floppy setup complete Hard disk setup to be done next Init of different BUSes optional ROMs from C800 to start Going to do any init before C800 optional ROM control Any init before C800 optional ROM control is over Optional ROM check and control will be done next a 6 e EN 0 901 95 Blue Chip Technology Ltd 01271019 doc 78 ERROR MESSAGES PX1 USER MANUAL HEX a eee processing after optional ROM returns control and enable external cache Any initialisation required after optional ROM test over Going to setup timer data area and printer base address base address i Coprocessor test 9C Required initialisation before Coprocessor is over Going to Initialize the Coprocessor next Coprocessor initialised Going to do any initialisation after Coprocessor test Initialisation after Coprocessor test is complete Going to check extd keyboard keyboard ID and num lock Keyboard ID command to be 9 Going to display any soft errors Keyboard typematic rate set To program memory wait states Going to enable parity NMI 7 NMI and parity enabled Going to do any initialisation required before giving control to optional ROM at E000 Initialisation before E000 ROM control over E000 ROM
59. k set the CMOS setup of drive C to not installed indicating that no physical magnetic disk is installed and reboot the computer The DiskOnChip 2000 will install as drive C The DiskOnChip needs to be formatted with the System files in order for it to be a bootable drive See Configuring the DiskOnChip as the BOOT device below To install the DiskOnChip as drive D on a system with a hard disk just reboot the system and the DiskOnChip will install as drive D To install the DiskOnChip as Drive C on a system with a hard disk see below Configuring the DiskOnChip as the first drive 2 2 CONFIGURING THE DISKONCHIP 2000 AS THE BOOT DEVICE In order to configure the DiskOnChip as the boot device the operating system files need to be copied into it Copying the operating system files into DiskOnChip Should be done like in any other hard disk The following is an example of a typical initialization process Set the DiskOnChip as a regular drive in your system not a boot drive Install a bootable floppy diskette in drive A and boot the system 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL SOFTWARE DESCRIPTION PAGE 51 At the DOS prompt type SYS C to transfer the DOS system files to the DiskOnChip assuming the DiskOnChip is installed as drive C Copy any files needed into the DiskOnChip Remove the floppy diskette and reboot the system The system will boot from the DiskOnChip and will allow you to run a
60. nabled The Optimal and Fail Safe default settings are Enabled HIT DEL MESSAGE DISPLAY Set this option to Disabled to prevent Hit DEL if you want to run Setup from appearing on the first AMIBIOS screen when the computer boots The settings are Disabled or Enabled The Optimal and Fail Safe default settings are Enabled INTERNAL CACHE This option specifies the caching algorithm used for L1 internal cache memory The settings are SETTING DESCRIPTION Disabled Neither L1 internal cache memory on the CPU or L2 secondary cache memory is disabled WriteBack Use the write back caching algorithm default WriteThru Use the write through caching algorithm 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL SOFTWARE DESCRIPTION PAGE 37 EXTERNAL CACHE This option specifies the caching algorithm used for L2 secondary external cache memory The settings are SETTING DESCRIPTION Disabled L2 cache is disabled WriteBack L2 cache is write back Deafult WriteThru L2 cache is write through SYSTEM BIOS SHADOW CACHEABLE When this option is set to Enabled the contents of the F0000h system memory segment can be read from or written to L2 secondary cache memory The contents of the F0000h memory segment are always copied from the BIOS ROM to system RAM for faster execution The settings are Enabled or Disabled The Optimal default setting is Enabled The Fail Safe default is Disabled Default is Enabled C000 16K Sha
61. nabled and Disabled The Optimal and Fail Safe defaults are Disabled If set to enabled and a device is not connected to the feature connector the display will blank when the feature connector is initialised When the feature connector is enabled the S3 VGA Controller will only use IMB of video memory limiting the resolutions available Blue Chip Technology Ltd 01271019 doc 48 SOFTWARE DESCRIPTION PX1 UsER MANUAL BIOS EXTENSIONS Specifies whether the PX1 BIOS extensions are available the section BIOS Extensions Software Interface for details of the functions available The options are Enabled and Disabled The optimal and fail safe defaults are Disabled 01271019 doc Blue Chip Technology Ltd PX1 USER MANUAL SOFTWARE DESCRIPTION PAGE 49 DISKONCHIP 2000 SUPPORT The PX 1 supports the use of M Systems DiskOnChip 2000 Flash Module the notes below detail the use of the device please consult the user manual if any more detail is required 1 PREFACE This note describes how to integrate DiskOnChip 2000 with PC compatible systems The DiskOnChip 2000 is a single chip FlashDisk designed to plug into a standard 32 pin EEPROM socket The DiskOnChip 2000 should be mapped into an 8KByte window in the BIOS expansion address space of the PC which is usually located between address 9CO000H to OEFFFFH The DiskOnChip 2000 contains a built in copy of the M Systems industry standard TrueFFS software which makes t
62. nal System 2 and Personal Computer BIOS Interface Technical Reference 15F0306 IBM 1987 e The Programmers PC Sourcebook Microsoft e The Winn L Rosch Hardware Bible Brady PC104 Consortium Technical Specification TRADEMARKS IBM PC AT and PS 2 are trademarks of International Business Machines Corporation IBM AMI Hi Flex BIOS is a trademark of American Megatrends Inc Intel is a registered trademark of the Intel Corporation All 80x86 and Pentium processors are registered trademarks of Intel Corporation MSDOS and WINDOWS are registered trademarks of the Microsoft Corporation PC 104 is a registered trademark of the PC 104 Consortium Blue Chip Technology Ltd 01271019 doc 4 INTRODUCTION PX1 UsER MANUAL 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL USER GUIDE PAGE 5 USER GUIDE OVERVIEW The Blue Chip Technology 1 single board PC sets new standards for integration of the latest advances in processor memory and I O technologies The 1 complies with the new PICMG form factor providing ISA PCI and PC 104 bus interfaces on a single PC AT plug in card The PICMG single board PC is an ideal platform for the increasing requirements of today s and tomorrow s embedded applications The flexible PICMG design will accept Pentium processors operating at 75 90 100 120 133 150 166 and 200 MHz The user may install 256 KB of asynchronous Cache or 256 KB or 512 KB of Pipeline Burst Cache RA
63. nd access any files that have been copied into the DiskOnChip 2 3 CONFIGURING THE DISKONCHIP 2000 AS THE FIRST DRIVE The DiskOnChip can be configured to be installed as the last drive default or as the first drive in the system When configured as the last drive the DiskOnChip is installed as disk D if there is another hard drive installed and as drive C if no other hard disk is installed When configured as the first drive the DiskOnChip is always installed as drive C The DiskOnChip is shipped from the factory configured to install as the last drive To configure the DiskOnChip to be installed as the first drive proceed as follows Boot the system and make sure the DiskOnChip is installed correctly as drive D At the DOS prompt type DUPDATE D FIRST S DOC2000 EXB After re booting the system the DiskOnChip will appear as drive C Blue Chip Technology Ltd 01271019 doc 52 SOFTWARE DESCRIPTION PX1 UsER MANUAL BIOS EXTENSIONS SOFTWARE INTERFACE The BIOS extensions provide the programmer with access to some of the additional functionality provided through the hardware on the PX 1 board This is achieved through the use of a software interrupt int 50h and a description of the functions available is described below ENABLING BIOS EXTENSIONS Boot the PX 1 card and enter the BIOS set up by pressing the DEL key Select Peripheral Set up Set the BIOS Extensions to enabled Save the settings and exit set up
64. nk Enabled None Link NORM Enabled Disabled EPROM Default Flash PROM Factory setting only 5 V Flash or EPROM Default 12 V Flash Reserved Not Allowed 2V9 CPU core 3V3 CPU core 3V45 CPU core 3V6 CPU core VRT CPU J10 Standard CPU External Bus Frequency 50 MHz 60 MHz 66 MHz Reserved Bus speed 6 Bus speed 8 Not Allowed Clear CMOS RAM Use on board batter In the table L indicates the presence of a link the absence Blue Chip Technology Ltd 01271019 doc 26 HARDWARE DESCRIPTION PX1 UsER MANUAL STATUS LEDS Along the top edge of the PCB on the reverse side is a row of LEDs These are arranged in groups to indicate the status of various board functions P O S T DISPLAY Red LEDs D10 to D17 inclusive display the Power On Self Test POST data byte Diode D17 represent the LSB and D10 the MSB The LED is illuminated when the POST data bit is 1 See the Appendix for details of the error codes POWER SUPPLY INDICATORS Green LEDs D5 D9 inclusive show the presence of the power supplies Each LED is illuminated when the appropriate voltage is present D9 Host CPU IO and chipset supply 3 3 Volts D8 5 Volt supply D7 12 Volt supply D6 12 Volt supply D5 5 Volt supply IDE ACTIVITY DISPLAY Yellow LED D4 indicates primary and secondary IDE activity Hard disk or CD ROM and is illuminated when active SYSTEM RESET STATUS Red LED D3 in
65. nology Ltd 01271019 doc 44 SOFTWARE DESCRIPTION PX1 UsER MANUAL DMA CHANNELS 0 1 3 5 6 7 These options specify the bus to which the DMA channel is allocated These options determine if AMIBIOS should remove a DMA channel from the available pool passed to BIOS configurable devices The available pool is determined by reading the ESCD more DMA channels must be removed from the pool the end user can use these PCI PnP Setup options to remove the channel by assigning the option to the ISA EISA setting Onboard I O is configurable by AMIBIOS The DMA channels used by onboard I O are configured as PCI PnP The default settings are OPTIMAL FAILSAFE Channel 0 PnP PnP Channel 1 PnP PnP Channel ISA EISA ISA EISA Channel 5 PnP PnP Channel 6 PnP PnP Channel 7 PnP PnP IRQ 3 4 5 7 9 10 11 14 15 These options specify the bus that the named interrupt request lines IRQs are used on These options allow you to specify IRQs for use by legacy ISA adapter cards These options determine if AMIBIOS should remove an IRQ from the pool of available IRQs passed to BIOS configurable devices The available IRQ pool is determined by reading the ESCD If more IRQs must be removed from the pool the end user can use these PCI PnP Setup options to remove the IRQ by assigning the option to the ISA EISA setting Onboard I O is configurable by AMIBIOS The IRQs used by onboard I O are configured as PCI PnP
66. oppy drive A will perform a seek operation on system boot are Enabled and Disabled The default setting is enabled MOUSE SUPPORT When this option is enabled the BIOS will support a PS 2 style mouse The options are Enabled and Disabled The default setting is enabled SYSTEM KEYBOARD This option specifies that a keyboard is attached to the computer The settings are Present or Absent The Optimal and Fail Safe default settings are Present PRIMARY DISPLAY This option specifies the type of display monitor and adapter in the computer The settings are Mono CGA40 CGA80 EGA VGA or Absent The Optimal and Fail Safe default settings are VGA EGA PASSWORD CHECK This option enables password checking every time the computer is powered on or every time Setup is executed If Always is chosen a user password prompt appears every time the computer is turned on If Setup is chosen the password prompt appears if Setup is executed Blue Chip Technology Ltd 01271019 doc 36 SOFTWARE DESCRIPTION PX1 UsER MANUAL OS 2 COMPATIBLE MODE Set this option to Enabled to permit AMIBIOS to run with IBM OS 2 The settings are Enabled or Disabled The default settings are Disabled WAIT FOR F1 IF ERROR AMIBIOS POST error messages are followed by Press F1 to continue If this option is set to Disabled AMIBIOS does not wait for you to press the key after an error message The settings are Disabled or E
67. opriate connections after the system is powered down The BIOS cannot communicate with the hard disk drive controller Check all appropriate connections after the system is powered down nterrupt channel 1 failed POST i another boot disk continue There is a timing problem with the keyboard Set the Keyboard option in Standard CMOS Setup to Not Installed to skip the keyboard POST routines Parity error in memory installed in an expansion slot The format is OFF BOARD PARITY ERROR ADDR HEX XXXX Where is the hex address where the error occurred Parity is not supported on this product this error will not occur Parity error in system memory at an unknown address Blue Chip Technology Ltd PX1 UsER MANUAL ERROR MESSAGES PAGE 81 ISA NMI MESSAGES 1 MESSAGE EXPLANATION Memory Parity Error at Memory failed XXXXX If the memory location can be determined it is displayed as XXXXX If not the message is Memory Parity Error Card Parity Error at An expansion card failed XXXXX If the address can be determined it is displayed as XXXXX If not the message is O Card Parity Error DMA Bus Time out A device has driven the bus signal for more than 7 8 microseconds PCI CONFIGURATION ERROR MESSAGES The following PCI messages are displayed as a group with bus device and function information lt Checksum Error Cleared gt V String Sy
68. ot all chipset functions are utilised in the design of the PXI in particular only three off board PCI expansion slots are available Blue Chip Technology Ltd 01271019 doc 12 HARDWARE DESCRIPTION PX1 UsER MANUAL 82437FX TRITON SYSTEM CONTROLLER TSC The 82437FX provides all control signals necessary to drive a second level cache and the DRAM array including multiplexed address signals It also controls system access to memory and generates snoop controls to maintain cache coherency 82438FX TRITON DATA PATH TDP There are two 82438FX components which provide data bus buffering and dual port buffering to the memory array Controlled by the 82437FX the 82438FX devices add one load each to the PCI bus and perform all the necessary byte and word swapping required Memory and I O write buffers are included in these devices 82371FB PCI ISA IDE ACCELERATOR PIIX The 82371FB provides the interface between the PCI and ISA buses and integrates a dual channel fast IDE interface capable of supporting up to 4 devices The 82371FB integrates seven 32 bit DMA channels five 16 bit timer counters two 8 channel interrupt controllers PCI to AT interrupt mapping circuitry NMI logic ISA refresh address generation and PCI ISA bus arbitration circuitry together all on one device IDE SUPPORT The 1 single board PC provides two independent high performance bus mastering PCI IDE interfaces capable of supporting PIO Mode 3 and Mode
69. otocol to put a DPMS compliant monitor into power saving modes and the VESA Display Data Channel DDC2B which permits transfer of monitor identification and resolution support data for ease of use RESOLUTIONS SUPPORTED RESOLUTION 1MB 2MB REFRESH RATE HZ DRAM DRAM 640x480x4 X X 640x480x8 X X 60727585 640 480 16 X X 607275 640x480x24 60 72 75 56 60 72 75 85 60 72 75 800x600x24 60 72 75 43 Interlaced 60 70 75 85 1024x768x16 43 Interlaced 60 70 75 45 Interlaced 60 72 75 1280x1024x8 45 Interlaced 60 72 75 Bios The single board PC uses an AMI System BIOS and an 53 Video BIOS both of which are stored in EPROM In addition to the System and Video BIOSes the EPROM also contains the Setup utility Power On Self Tests POST and the PCI auto configuration utility This single board PC supports system BIOS shadowing allowing the BIOS to execute from 64 bit on board write protected DRAM 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL HARDWARE DESCRIPTION PAGE 17 The BIOS displays a sign on message during POST identifying the type of BIOS and a revision code SETUP UTILITY The ROM based Setup utility allows the configuration to be modified without opening the system for most basic changes The Setup utility is accessible only during the Power On Self Test POST by pressing the DEL key after the POST memory test
70. processors Pentium processors which run internally at 75 90 100 120 133 150 166 180 and 200 MHz are supported 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL USER GUIDE PAGE 7 The Pentium processor maintains full backward compatibility with the 8086 80286 1386 and Intel486 processors It supports both read and write burst mode bus cycles and includes separate 8 KB on chip code and 8 KB data caches which employ a write back policy Also integrated into the Pentium processor is an advanced numeric co processor which significantly increases the speed of floating point operations whilst maintaining backward compatibility with 1486DX math co processor and complying to ANSI IEEE standard 754 1985 PROCESSOR UPGRADE The PX1 single board PC has a 321 pin Zero Insertion Force ZIF processor socket socket 7 that provides users with an OverDrive processor upgrade path OverDrive processors being developed for use with socket 7 will provide performance beyond that delivered by the originally installed Pentium Processor SECOND LEVEL CACHE The Pentium processor s internal cache can be complemented by a second level cache using the COAST connector Pipeline Burst SRAM provides performance similar to expensive Synchronous Burst SRAMs for only a slight cost premium over the slower performing Asynchronous SRAMs With the Triton chipset the performance level of Pipeline Burst and Synchronous SRAMS is identical SYSTEM MEMOR
71. red in one of three ways Sleep Resume may be activated by using either a momentary action sleep switch in the UTILS header a keyboard hot key sequence or by a time out of the system inactivity timer Both the keyboard hot key and the inactivity timer are programmable in the BIOS setup timer is set to 10 minutes by default To re activate the system or Resume the user simply uses the keyboard or mouse or presses the sleep switch Note that mouse activity will only wake up the system if a mouse driver is loaded While the system is in Stand By or Sleep mode it is fully capable of responding to and servicing external interrupts even though the monitor will only turn on user interrupt occurs as mentioned above 01271019 doc Blue Chip Technology Ltd PX1 USER MANUAL HARDWARE DESCRIPTION PAGE 19 SECURITY FEATURES SUPERVISOR PASSWORD If enabled the supervisor password protects all sensitive Setup options from being changed by a user unless the password is entered see appendix If the password is forgotten it may be cleared by turning off the system and clearing the CMOS RAM USER PASSWORD The User Password feature provides access to all setup options that do not require the supervisor password The User Password feature also provides security during the boot process The User Password can be enabled using the Setup utility At boot up the system will complete the operating system boot up process but keybo
72. s 10 8 Used to indicate a specific function in multifunction PCI devices The PIIX is the only multi function device on 1 located on the single board PC Use 00h for the basic PIIX device and Olh for the PCI IDE BUS MASTER FUNCTION For a multi function PCI add in card refer to the card s documentation to determine the allowable function numbers REGISTER NUMBER Bits 7 2 Defines one of 64 DWORD locations for a specific PCI device Note that Bits 1 and 0 must always be Oh for DWORD access The table below lists the PCI bus and device numbers used by the single board PC It also lists the data range that must be written to the I O Configuration Address register to access the device DEVICE BUS DEVICE ID CONFIG ADDRESS FUNCTION SEL REGISTER 00 00 0 8000 0000 8000 00 PIIX 00 07 0 AD18 8000 3800 8000 38FC PIIX IDE BUS MASTER 00 07 1 AD18 8000 3900 8000 39FC INTERRUPTS amp DMA CHANNELS The following tables list the Interrupt and DMA Channel configuration options for on board devices The serial ports parallel ports and IDE controller can be configured using SETUP or any other Plug and Play resource manager such as the Windows 95 Device Manager The Graphics interrupt is assigned by the auto configure utility during boot up Blue Chip Technology Ltd 01271019 doc 60 PX1 UsER MANUAL iN c INTERRUPTS 0 Interval Timer from slave PIC 6 Floppy Controller
73. s the memory data when negates to precharge for the next cycle With EDO the CAS precharge overlaps the data valid time allowing CAS to negate earlier while still satisfying the memory data valid window time REAL TIME CLOCK BATTERY REPLACEMENT The on board battery may be replaced using a Crompton Eternacell type 048 9 lithium battery or equivalent This battery has 1000 mAh rating CPU UPGRADE A 7 Zero Insertion Force ZIF socket provides users with a performance upgrade path to the Pentium Overdrive Processors GRAPHICS MEMORY UPGRADE The single board PC has 1 MB of Fast Page DRAM installed for graphics Two SOJ type sockets ICA amp IC5 on the underside of the board provide for upgrade of the graphics DRAM Two 256K x 16 60 ns DRAMs may be installed to provide a total of 2 MB of graphics DRAM Note these must be installed in pairs The DRAM must be of the Dual CAS type and not the Dual Write type Suitable types are Toshiba TC514260BJ 60 NEC yPD424260LE 60 Hitachi HM514260CJ 6 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL SOFTWARE DESCRIPTION PAGE 29 SOFTWARE DESCRIPTION BIOS SETUP This section details the BIOS CMOS Setup Utility The parameters described below are based on BIOS version 1 10 other BIOS versions may differ from the description below as new features are added OVERVIEW OF THE SETUP MENU SCREENS The Setup program initially displays the
74. stem Board Device Resource Conflict String Primary Output Device Not Found V String Primary Input Device Not Found V String Primary Boot Device Not Found V String lt NVRAM Cleared By Jumper V String lt Data Invalid Cleared V String Static Device Resource Conflict V String The following messages chain together to give a message such as PCI I O Port Conflict Bus 00 Device OD Function 01 If and when more than 15 PCI conflict errors are detected the log full message is displayed lt PCI I O Port V String lt PCI Memory Conflict gt V String lt PCI IRQ Conflict gt V String lt Bus gt V String lt Device gt V String lt Function gt V String PCI Error Log is Full gt V String Floppy Disk Controller Resource Conflict gt Text Blue Chip Technology Ltd 01271019 doc 82 ERROR MESSAGES PX1 UsER MANUAL Primary IDE Controller Resource Conflict gt Text Secondary IDE Controller Resource Conflict gt Text lt Parallel Port Resource Conflict gt V Text Serial Port 1 Resource Conflict gt V Text Serial Port 2 Resource Conflict gt V Text 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL PAGE 83 BOARD LAYOUT
75. the power conserving mode specified in the Hard Disk Power Down Mode option described above The settings are Disabled 1 Min minutes and all one minute intervals up to and including 15 Min The default settings are Disabled STANDBY TIMEOUT This option specifies the length of the period of system inactivity when the computer is in Full On mode before the computer is placed in Standby mode In Standby mode some power use is curtailed The settings are Disabled 1 Min 2 Min and all one minute intervals up to and including 15 Min The default settings are Disabled SUSPEND TIMEOUT This option specifies the length of the period of system inactivity when the computer is already in Standby mode before the computer is placed in Suspend mode In Suspend mode nearly all power use is curtailed The settings are Disabled 1 Min 2 Min and all one minute intervals up to and including 15 Min The default settings are Disabled 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL SOFTWARE DESCRIPTION PAGE 41 SLOW CLOCK RATIO This option specifies the speed at which the system clock runs in power saving modes The settings are expressed as a ratio between the normal clock speed and the power down clock speed The settings are 1 1 1 2 half as fast as normal 1 4 the normal clock speed 1 8 1 16 1 32 1 64 or 1 128 The default setting is 1 8 DISPLAY ACTIVITY This option specifies if AMIBIOS is to monitor activity on the display
76. tings are Auto Enabled or Disabled The default setting is Auto ONBOARD SERIAL This option enables serial port 1 on the board and specifies the based I O port address for serial port 1 The settings are Auto 3F8h 3E8h 2F8h 2E8h or Disabled The default setting is Auto ONBOARD SERIAL PORT2 This option enables serial port 2 on the board and specifies the base I O port address for serial port 2 The settings are Auto 3F8h 3E8h 2F8h 2E8h or Disabled The default setting 15 Auto ONBOARD PARALLEL PORT This option enables the parallel port on the board and specifies the parallel port based I O port address The settings are Auto 378h 278h 3BCh or Disabled The default setting is Auto PARALLEL PORT MODE This option specifies the parallel port mode ECP and EPP are both bi directional data transfer schemes that adhere to the IEEE P1284 specifications The settings are SETTING DESCRIPTION The normal parallel port mode is used This is the default setting Use this setting to support bi directional transfers on the parallel port EPP The parallel port can be used with devices that adhere to the Enhanced Parallel Port EPP specification EPP uses the existing parallel port signals to provide asymmetric bi directional data transfer driven by the host device The parallel port can be used with devices that adhere to the Extended Capabilities Port ECP specification ECP uses the DMA protocol to ac
77. to get control next A8 A9 Returned from E000 ROM control Going to do any initialisation required after E000 optional ROM control A E i Goi A2 A3 Soft error display complete Going to set keyboard typematic rate 4 5 Initialisation after E000 optional ROM control is over Going to display the System configuration AB To uncompress DMI data and execute DMI POST init B1 System configuration is displayed Going to copy any code to specific area Copying of code to specific area done Going to give control to INT 19 boot loader 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL ERROR MESSAGES PAGE 79 AMIBIOS ERROR MESSAGES Textual error messages are displayed in the following format ERROR Message Line 1 ERROR Message Line 2 For most displayed error messages there is only one message If a second message appears it is RUN SETUP If this message occurs press to run Setup Utility The table of messages is shown on the next page Blue Chip Technology Ltd 01271019 doc 80 ERROR MESSAGES PX1 UsER MANUAL ERROR EXPLANATION MESSAGE 8042 Gate A20 Gate A20 on the keyboard controller 8042 is not working Replace the 8042 Error Address Line Short Error in the address decoding circuitry on the single board PC Cache Memory Bad Do Not Enable Cache CH 2 Timer Error CMOS Battery State CMOS Checksum Failure CMOS System Options Not Set CMOS Display Type Mism
78. to let the system reboot ACCESSING INT 50H FUNCTIONS Most high level languages allow access to software interrupts through a particular function call The user loads a particular function code into the AH register followed by a specific set of parameters in the other registers before executing the interrupt For example in Quick Basic Read E2 Data via interrupt 50 call Sinclude QB BI DIM INARY 7 OUTARY 7 CONST AX 0 1 CX 2 DX 3 BP 4 SI 5 DI 6 FL 7 INARY S AX amp H0400 Read 2 data INARY S amp H31 address amp H31 CALL INT860LD amp H50 INARY OUTARY Call the APEX service PRINT E2 ADDRESS amp H31 CONTAINS OUTARYS DX 01271019 doc Blue Chip Technology Ltd PX1 USER MANUAL SOFTWARE DESCRIPTION PAGE 53 and similarly in C include lt stdio h gt include lt dos h gt define APEX 0x50 void main void union REGS regs regs x ax 0x0400 read e2 regs x bx 0x31 address 0x31 11686 APEX amp regs amp regs printf e2 Address 0x31 contains x n regs x dx INT 50H FUNCTION DEFINITIONS This covers version 1 3 of the BIOS extensions Other versions may have additional functions available AH 00H EXTENDED WATCHDOG ENABLE The SMC932 Ultra IO controller provided a programmable watchdog that can be used to monitor the system health and reset the system should the application stop working and not refresh the watchdog Input parameters
79. up screen SYSTEM DATE When selected this allows you to set the current date by specifying a date month and year SYSTEM TIME When selected this allows you to set the current time by entering values for hours minutes and seconds FLOPPY A TYPE When selected this allows you to cycle through the available options to specify the physical size and capacity of the diskette drive The options are Disabled 360 KB 5 25 inch 1 2 MB 5 25 inch 720 KB 3 5 inch 1 44 1 25 MB 3 5 inch 2 88 MB 3 5 inch The default is 1 44 MB 3 5 inch 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL SOFTWARE DESCRIPTION PAGE 33 FLOPPY B TYPE When selected this allows you to cycle through the available options to specify the physical size and capacity of the diskette drive The options are Disabled 360 KB 5 25 inch 1 2 MB 5 25 inch 720 KB 3 5 inch 1 44 1 25 MB 3 5 inch 2 88 MB 3 5 inch The default is Disabled PRIMARY IDE MASTER This reports if a primary master IDE hard disk is connected to the system and allows for the configuration of drive parameters When selected this allows the manual configuration of the hard drive or have the system auto configure it The options are Auto Configured User Definable and Disabled There are also options for IDE CD ROM and 46 predefined hard drive types If you select User Definable then the Number of Cylinders Number of Heads and Number of Sectors can each be modified The
80. upture and result in a return to base repair 01271019 doc Blue Chip Technology Ltd PX1 UsER MANUAL HARDWARE DESCRIPTION PAGE 15 The integrated 8042 microcontroller contains the AMI Megakey keyboard mouse controller code which besides providing traditional keyboard and mouse control functions supports Power On Reset POR password protection The POR password can be defined by the user in the Setup program The keyboard controller also provides the facility for a lt CTRL gt lt ALT gt lt DEL gt hot key sequence to perform a system software reset It performs this by jumping to the beginning of the BIOS code and running the POST operation REAL TIME CLOCK CMOS RAM AND BATTERY The integrated Real Time Clock RTC is DS1287 and MC146818 compatible and provides a time of day clock 100 year calendar with alarm features The RTC can be set via the BIOS SETUP program The RTC also supports 242 bytes of battery backed CMOS RAM in two banks which is reserved for BIOS use The CMOS RAM can be set to specific values or cleared to the system default values using the BIOS SETUP program Also the CMOS RAM values can be cleared to the system defaults by using a configuration jumper on the single board PC The appendix lists the jumper configurations An on board Lithium battery provides power to the RTC and CMOS memory The battery has an estimated lifetime of three years if the board remains unpowered When the system is powered up power is

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