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1. rem BC Wessage Background Program Block 1553B LUT 5 Area E Message Number Reserved 2 2 DDB Address I Address in LUT 2 SMB DATA BUFFERS BASE REGISTER A Time Tag HI Time Tag LO BRP Data IRP N DI N Options mask Queues Address 4 Insertion Program Data buffer Address HI Data buffer Address LO RTSTAD 1553 LUT RT Simulation Table DATA BUFFERS i Time Tag HI Error Injection i c 1553B LUT 1 Word Time Tag LO E Address DDB Address 4 DDB Data Db Options mask Low High Priority Priority Data buffer Address HI Interrupt Interrupt Data buffer Address LO RTI RTI gt RT30 Message Message RT30 Interrupt Status Report Figure 3 1 Organisation Diagram 18 UM 10986 Rev B 3 4 1 Base Register Names and Locations The names and locations of the Base Registers are contained in table 3 1 UM 10986 Rev B Table 3 1 Base Register Names and Locations BASE Control Register Write Clock HI Word Read 02H Clock LO Word Read only 04H Command Register CR 06H Status Register SR 08H Backgroun
2. un 31 4 2 MESSAGE DESCRIPTOR BLOCK MDB io 32 4 2 1 Message Number OOF i 32 4 2 2 1553B Event Mask 02H ni dte te eRace liane elica 32 4 2 3 Message Word 04H Gi tte ie pee Uo r et p Artois rali 33 4 2 4 1553B Message Error Phase Definition 06H iii 34 4 2 5 1553B Message Error Description Word 08 34 4 2 6 Address in Look Up Table AH eerie reina iaia tiara 35 4 2 7 Command Word 1 uil 35 4 2 8 Command Word 2 0EH rie 35 4 2 9 Retry Subroutine Absolute Address 14H 35 4 2 10 Inter message Gap Time 18H ii 36 42411 Status Word 1 telis iicet alia 36 4 2 12 Status Word 36 43 DATA BUFFERS SIMULATION AND MONITORING iii 37 4 3 1 IV Ug am 4 3 2 Descriptor BLOCK i idR e ree eoe eR ee 4 3 2 1 NUS PH 4320 Data Status Report ied eterne orte ORIS O e Epit 4 3 2 3 Toggle Frequency and Buffer Address HI 08H 4324 Link Pointer to New DDB OCT rtr rti trt I aa 4 3 2 5 Address of Modify Word Value to Write 0EH 10H ennt 40 43 2 6 Extended Sub AddresS oO
3. PIN DESCRIPTION 1 1553 PRIMARY VE 2 1553 SECONDARY VE 3 TRIGGER OUT COLLECTOR 4 TRIGGER IN CATHODE 5 GROUND 6 1553 PRIMARY VE 7 1553 SECONDARY VE 8 TRIGGER OUT EMITTER 9 TRIGGER IN ANODE Figure 1 2 IIB 1553 PCI 2C Front Panel Connectors UM 10986 Rev 12 115 LINKER BLOCKS There are 6 user configurable linker blocks all of which are 3 pin types located as shown in the diagram below d Bear Ses Esa IEEE E EE CTIITII III LITI IT ILTI LI IEEE PEE EE E E IG GG n mma mai 71 3 uui 43 20000 WO n rn rn rn d n 3 namamana C 1 222220 L mssumssmssumasui gt n gt gt gt gt 19009009 999 299 Figure 1 3 IIB 1553 PCI 2C Linker Block locations 1 15 1 Linker Block Functions and Settings L1 is provided for the selection of Big Endian Motorola format or Little Endian Intel format and is supplied with factory default position as Big Endian Motorola format with header mounted towards the PCI front panel as indicated above L6 is provided for the selection of which 1553 module is accessed first Channel 1 or Channel 2 and is supplied with factory default position for Channel 1 to be the first module t
4. DDB ADDRESS OPTION MASK 02H Header Address 04H Data Word Count 06H Data Status Report 08H Toggle Frequency and Buffer Address HI 0AH Buffer Address LO 0CH Link Pointer to Address of another DDB 0EH Address of Modify Word 10H Value to Write 12H Message Interrupt Code 14H Set of Message Number 16H Message Indicator in the Set of Messages 18H Reserved 1AH Reserved 1CH Reserved 1EH Reserved UM 10986 Rev B 38 4 3 2 1 Option Mask 00H BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 09 BIT 08 BIT 07 BIT 06 BIT 05 BIT 04 to 00 1 Interrupt on Correct Message 1 Interrupt on Error Message 1 HI LO Priority Queue 0 LO 1 HI 1 Interrupt on Set of Messages 1 Message Interrupt If Message Correct 1 Link only on Correct Message 1 Link to New Enabled 1 Modify Word Enabled 0 0 0 Header Word Count 4 3 2 2 Data Status Report 06H BIT 15 to 14 BIT 13 to 00 NOTE 00 Good Message 01 Message Running 10 Error Message Signed Wordcount Error 0 No Wordcount Error The wordcount error is calculated as follows TX Wordcount Command Wordcount DDB Count Header Count RX Wordcount Wordcount Received DDB Count Header Count 4 3 2 3 Toggle Frequency and Buffer Address HI 08H The word 24 in Base Registers defines if the data buffer toggle feature is enabled and also the toggle offset MSB
5. Sy 1 Sync Type Error Sh 1 Short Word Error TA 1 Terminal Address Error Lg 1 Long Word Error NR 1 No Response Error Mn Manchester Error WC 1 Wordcount Error Py 1 Parity Error UM 10986 Rev B 58 Trigger Data 2 Trigger Data 2 Bit Mask Register Base Address 3CH This register will define the bits to be ignored in the trigger bit pattern for trigger data 2 Any bit set in this register will be masked from the trigger test condition Trigger Data 2 Bit Pattern Register Base Address 3EH This register will define the bit pattern required for trigger data 2 Trigger Data 2 Bus ID Word Type Mask Base Address 40H This register will define the Bus ID and Word Type bits to be ignored in the Bus ID Word Type Register DIS D14 D13 D12 D11 DIO D09 D07 DOS D04 D03 D02 D01 DOO 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Both W bits 1 Ignore Word Type in trigger condition Both B bits 2 1 Ignore Bus ID in trigger condition Trigger Data 2 Bus ID Word Type Register Base Address 42H This register will define the Bus ID and Word Type for the trigger condition D15 D14 D13 D12 D11 DIO DOS D04 DO2 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 WMsb WLsb BMsb BLsb 0 0 Trigger on Command 0 0
6. 41 4 3 3 Data Buffers 41 424 MODE COMMANDS eee 42 4 5 INTERRUPT REQUESTS ile 43 4 5 1 Interrupt Coding eiit eerie yl ile rale HEU Dee dcn 43 4 5 2 Set Message Interrupts Rm 43 4 5 3 Message Status Report Queue ziii RIT GERNE a EE EEE 44 UMI 10986 Rev B 3 5 MULTIPLE REMOTE TERMINAL MODE OF OPERATION srsrrrerrerrereerin ze sere nece senten neo nionene 45 5 1 INTRODUCTION eR EU Nara aiar aaa 45 5 2 LOOK UPSTABLES siii AIR re RISE E O EAEE E E EREET aO E e EEEE LI bebe o dede bes 46 5 3 MODE COMMANDS SPECIFICATIONS 46 5 4 DATA WORDS STORAGE ecese i khe kae vins sooo eb ER ERE YD cbe 46 5 5 1553B ERROR INJECTION DEFINITION nennen nee 46 5 5 1 Global RT Error Description Word RT Simulation Table iii 47 5 5 2 Message Error Injection Word Look up Table iii 48 2 0 INTERRUPTS CODING lata e sk Sa pite eb Oden esae 49 5 6 1 Low and High Priority Interrupts two word code iii 49 5 6 2 Message Interrupts or set of messages eene eem eem eene 49 5 6 3 Status Report Queue two words per report ii 49 SPECIFIC FUNCTIONS AI M 49 5 7 1 Data Message RECEDHON mM italici E rR daS
7. Descriptor Block A data descriptor block is associated with each data message this 16 word set defines the data buffering and associated queue control information Interrupt selection is defined in the option mask word interrupt on correct or erroneous message or after a set of different messages priority of interrupt three different available one interrupt only per message The data word count contains the data word count expected by the user The Western Avionics IIB 1553 PCI 2C processor compares this word count with real data word count transmitted on the bus and writes the difference if any in the data status report word This last word also contains the status flag of the transmission message received correct or with error message running The most significant byte of data buffer address can be used to enable toggled buffer control toggle on beginning of each minor frame or on multiple cycles of this minor frame This allows user software synchronised on the frame cycle to always access the correct buffer The set of message interrupt features provides the possibility to send an interrupt after the last message of the set of messages It is to be used when the frame sequence is not purely repetitive Up to 128 different sets of messages from 2 to 16 messages each can be defined Refer to table 4 Error injection on 1553B data words is defined in the message descriptor blocks Table 4 2 Data Descriptor Block
8. INTERRUPT Figure 1 1 IIB 1553 PCI 2C Functional Block Diagram 15 PROTOCOL MANAGEMENT UNIT A micro controller based structure running at 40Mhz handles the management of the 1553B protocol for each of the operating modes BC MRT BM The micro controller works each of the 1553B command status and data words functions of its operating mode and the configuration tables in RAM The micro controller management unit allows flexibility and expandability for the bus control tasks and user interface 16 1553 INTERFACE The 1553B interface is a dual redundant interface which includes a standard dual redundant transceiver and a Manchester encoder decoder with full error detection and error injection capabilities which include Manchester bit error Synch bit error Parity error Word length error Wrong bus error Both bus error Response time error UM 10986 Rev B 9 1 7 FEATURES The features of the Western Avionics IIB 1553 PCI 2C are listed as follows Universal PCI card Memory mapped real time PCI interface 2MByte of RAM per 1553 channel Multiple interrupt queues for various events 1553B data protocol managed by a micro controller providing complete flexibility and extension capability Error Injection and detection External Triggers Internal Self tests 18 SYSTEM CHARACTERISTICS AND SPECIFICATIONS The characteristics and specifications of the Western Avionics IIB 1553 PCI 2C are listed as
9. DIS 014 DI2 DIO 007 DOS D04 DOI 0 0 0 0 Trigger Post Trigger Full Stack Half Stack 0 0 0 0 0 0 0 0 H T Ifset a physical INTA interrupt will be generated when the trigger condition is met If set a physical INTA interrupt will be generated when all the post trigger data is captured F If set a physical INTA interrupt will be generated when the stack is full H If set a physical INTA interrupt will be generated when the stack is half full UM 10986 Rev B 53 6 2 5 Load Clock HI LO Registers 38H1 3AH If a LOAD CLOCK command is executed these two registers define a 32 bit value to be loaded into the counter If a SYNCHRONIZE CLOCK command is executed the two registers define a 32 bit signed number to be added to the current clock value 6 2 6 Current Address Register CAR 42H This register contains the PAGE address of the current message being stored 6 2 7 Trigger Occurrence Register TOR 44H This register contains the PAGE address of the message that met the pre programmed trigger condition 6 2 8 Trigger Set up Pointer TSP 46H This register contains the absolute address of the trigger set up data NOTE This value is only 16 bits trigger set up data must reside in the first 64Kbytes of the board 6 2 8 1 Trigger Set up Data TSP Address 00 Post Trigger Count Register PTCR This register will contain the numbe
10. CODE COMMAND 0000H Illegal 0001H GO TO BCT MODE 0002H GO TO MRT MODE 0003H GO TO MON MODE 0004H Reserved 0005H Reserved 0006H Reserved 0007H Reserved 0008H Reserved 0009H Reserved 000AH Reserved 000BH Reserved 000CH LOAD CLOCK 000DH SELFTEST 000EH RUN MONITOR 000FH STOP MONITOR 0010H SYNCHRONISE CLOCK After the command is loaded bit CO in the Command register can be cleared When the CR clears the board is ready for a new command UM 10986 Rev B 52 6 2 3 Status Register SR This register contains a code reflecting the status of the board as shown in table 6 3 Table 6 3 Status Registers CODE COMMAND 0001H Reserved 0002H Reserved 0003H MONITOR IDLE 0004H Reserved 0005H Reserved 0006H Reserved 0007H MONITOR RUNNING 0008H Reserved The Status Register will contain the following information after completion of selftest D15 D14 D13 D12 D11 DIO DOS 007 006 DOS 004 D03 D02 DOO 1 0 0 LS 0 0 LC_ MS 4 2 MI 1 0 0 0 LS 1 1553B Interface Test Failed FR 1 Frame Counter Test Failed LC 1 Local Clock Test Failed 5 1 Memory Test 5 Failed M4 1 Memory Test 4 Failed M3 1 Memory Test 3 Failed M2 1 Memory Test 2 Failed MI 21 Memory Test I Failed If no selftest errors are detected the Status Register will be 8008H 6 2 4 IRQ Selection Register 34H
11. D07 006 DOS D04 D02 1 0 0 LS 0 0 LC MS M4 M3 M2 MI 1 0 0 0 18 1 1553B Interface Test Failed LC 1 Local Clock Test Failed MS 1 Memory Test 5 Failed M4 1 Memory Test 4 Failed M3 1 Memory Test 3 Failed M2 1 Memory Test 2 Failed MI 1 Memory Test 1 Failed Several bits can be set simultaneously If no self test errors are detected the code in the status register will be 8008H UM 10986 Rev 22 3 4 2 5 Background Running Pointer 08H In the BC mode the Background Running Pointer BRP directs the firmware to the location of a background program which can be used to organise the message sequencing Before sending a BC start the user must initialise the BRP BRP is updated by the on board processor after executing a BC STOP command Table 3 4 is a list of the possible instructions with descriptions and examples Table 3 4 Instruction Set Background Program DELAY 0000 XXXXH XXXX Delay LSB of 10 5 NOPI 000 NOP2 0002 PC PC 2 NOP3 0003 PC PC 3 BSR 0004H XXXXH XXXX 16 bit signed branch to subroutine BRA 0006H XXXXH XXXX 16 bit signed branch JMP 0007 XXXXH XXXX 16 bit absolute address for jump RTS 0008H Return from subroutine RTI 0009H Return from insertion routine ENI 000 Enable program insertion DSI 000 Disable program insertion LOOP
12. WESTERN AVIONICS MIL STD 1553B PCI Two Channel INTELLIGENT INTERFACE BOARD P N 1010986601 Rev User Manual UM 10986 Rev B Western Avionics Ltd 13 14 Shannon Free Zone Co Clare Ireland 11 June 2002 1 Table of Contents GENERAL TION siisessscscsszsessenssdduccoosssscesesdencssncsevessesteessancssoessoscsestess eussasss encssneesoscesssaccsoseasseasceseese 6 1 1 INTRODUCTION ice ceci te HER AR A Ara 6 1 2 MANUAL DESCRIPTION repe ou eoru ep rege ee ini 6 1 3 CAPABILITIES E cha pete cad ates 7 1 3 1 General 7 1 3 2 Bus Controller BC Features With MRT Simulation and Data 7 1 3 3 Multiple Remote Terminal Features iii 8 1 3 4 Chronological Bus Monitor CM Features 8 1 4 THE 1553 1 2 ARCHITECTURE ariani aio a iii 9 1 5 PROTOCOL MANAGEMENT UNIT Ei ee e HERE E EES RE CA E ERSTE 9 1 6 sx BAUINTEREAGE H 9 1 7 oec Idi IEEE tu M 10 1 8 SYSTEM CHARACTERISTICS AND SPECIFICATIONS enne enne 10 1 9 LIST OF FURNISHED 5 iei tette ce Pet det bei aee io ent e e 11 1 10 LIST OF RELATED PUBLICATIONS 1 0 4 1 666 0000000000000000000000000000000
13. 0 0 Illegal 0 1 Secondary 1 0 1 1 Both Buses NR 1 Indicates that an RT failed to respond to a command No Response Only set for last word 1 Indicates that the RT status word did not match the address of the command word Terminal Address Error Sy 1 Indicates that the 1553B word did not have the correct SYNC type 6 4 4 Next Address Pointer This word will define the page address of the next message This value will be set to FFFFH for the last message after the post trigger count has expired and capturing has stopped 6 4 5 RT Response Time 1 2 These two locations will define the RT response times if any of the Status words in the message The second Response time is only applicable for 1553B RT RT transfers 6 4 6 Flow Diagram TRIGGER SETUP Base 46H Trigger STACK Set up Register PTCR SCCR SPR FPR etc UM 10986 Rev B 66 7 SOFTWARE TOOLS AND SUPPORT 7 1 INTRODUCTION Western Avionics provides a complete suite of library functions in C source code together with a Windows Graphical User Interface GUI as standard for all PCI based products The Windows GUI utilises the C driver library functions to provide commonality of approach in programming Up grades are made freely available on our web site 7 1 1 Loading Software Software is provided as a self loading file titled setup WA EXE Running this disk will load the Windows GUI P N 1L01675H01 in a single fold
14. 0 0 0 0 0 0 0 0 D 1 Error condition disabled Trigger Data 3 Error Word Register Base Address 52H This register will define the Errors required in the trigger condition If more than one error is set the trigger condition will be a logical OR of the errors D15 D14 D13 D12 D11 DIO 0081007 DOS 004 DO2 DOO 0 0 0 Py Sh 0 0 WC 0 0 NR TA Sy O Sy 1 Sync Type Error Sh 1 Short Word Error TA 1 Terminal Address Error Lg 1 Long Word Error NR 1 No Response Error Mn 1 Manchester Error WC 1 Wordcount Error Py Parity Error UM 10986 Rev B 60 Trigger Data 4 Trigger Data 4 Bit Mask Register Base Address 54H This register will define the bits to be ignored in the trigger bit pattern for trigger data 4 Any bit set in this register will be masked from the trigger test condition Trigger Data 4 Bit Pattern Register Base Address 56H This register will define the bit pattern required for trigger data 4 Trigger Data 4 Bus ID Word Type Mask Base Address 58H This register will define the Bus ID and Word Type bits to be ignored in the Bus ID Word Type Register D15 D14 D13 D12 D11 DIO 0081007 DOS 004 D03 D02 0011 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Both W bits 1 Ignore Word Type in trigger condition Both B bits 1 Ignore Bus ID in trigger condition Trigger Data 4
15. 14 BIT 13 BIT 12 BIT 11 Bit 09 BIT 10 BITS 08 to 00 UM 10986 Rev B Wrong Both Buses Error NO RESPONSE Error RT ADDRESS Error TX Error Mn LG SH Py WC Late Response SYNC Type Error 0 Ist Status 1 2nd Status RX Status Bits 44 5 MULTIPLE REMOTE TERMINAL MODE OF OPERATION 51 INTRODUCTION In Multiple Remote Terminal mode the Western Avionics IIB 1553 PCI 2C board can simulate up to 31 RTs After initialisation by the host the board is ready to listen to the bus activity and to respond to command words for the simulated RTs The description of the mode of operation uses tables similar to those defining the bus controller mode providing the same associated features multiple data buffering signalisation etc Refer to figure 5 1 the Multiple Remote Terminal Organisation Diagram The specifics of the MRT mode of operation mainly concern the following The logical path to point into the look up tables The errors injection capabilities BASE REGISTER RT Simulation DATA Table BUFFERS RTO RTI RTO 1553B LUT Time Tae HI IRP DDB Time Tag LO Illegalization Word e Options mask Data RX DDB Address UU p Queues Address Data buffer Address HI RT30 TX Data buffer Address LO RTSTAD RT31 Broadcast DATA BUFFERS RTO 1553B Mode T DDB 1015 mas Code L
16. 1553B RT RT BROADCAST 1 0 1 1 1553B BC RT BROADCAST 1 1 0 0 Reserved BROADCAST 1 1 0 1 RECEIVE CLOCK BROADCAST 1 1 1 0 Reserved BROADCAST 1 1 1 1 Reserved BROADCAST 1 Extended Subaddress l Retry on EVENT 1 Interrupt on EVENT enabled 1 Interrupt on EVENT HI priority queue 0 LO priority 0 0 0 0 1 33 4 2 4 1553 Message Error Phase Definition 06H The following word defines the location of errors that can be injected into the 1553B message 05 014 D13 D12 DIO D06 DOS 1004 002 DOI 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X XXX 000 gt Error Injection Disabled XXX 001 gt Inject Error in 1st BC TX Initial BC message XXX 011 gt Inject Error in 1st RT SIM Ist RT response XXX 100 gt Inject Error on 2nd RT SIM 2nd RT RT response 4 2 5 1553 Message Error Description Word 08H The following word defines the errors that can be injected into the 1553B message 05 04 D12 DII DIO 009 DOS D07 106 005 004 003 002 T T T X X X X X X X X X X X X X 000 gt Modulation Error XXXXXXXXXXXXX WWWWWWYYYYYYY WWWWWW Word Number For Modulation Error Y Y Y Y Y Y 0 000 00 Parity error 55 54 53 52 SI 50 Synchro Pattern Error 0 B4 B3 B2 BI BO Manchester Bit Error 1 L4 L3 L2 LI LO Word Length Error TTT 001 gt Wrong Bus Error XXXXXXXXXXXXX 0000000000000 TTT 0
17. Bus Word Type Register Base Address 5AH This register will define the Bus ID and Word Type for the trigger condition D15 D14 D13 D12 D11 DIO 0081007 DOS 004 D02 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Wmsb WLsb BMsb BLsb 0 0 Trigger on Command 0 0 Illegal 0 1 Trigger on Status 0 1 Trigger on Primary 1 0 Trigger on Data 1 0 Trigger on Secondary 1 1 Trigger on RT RT Transfer 1 1 Trigger on Both Buses Trigger Data 4 Error Word Mask Register Base Address 5CH This register will define if the Error Word Register is to be included in the trigger condition 015 D14 D13 D12 D11 DIO 009 DOS 004 0031002 D01 DOO 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 D 1 Error condition disabled Trigger Data 4 Error Word Register Base Address 5EH This register will define the Errors required in the trigger condition If more than one error is set the trigger condition will be a logical OR of the errors DIS D14 D13 D12 D11 DIO D09 008 007 DOS D04 0031002 DOO 0 0 Lg sh o lo 0 0 NR ITA sy 0 Sy 1 Sync Type Error Sh 1 Short Word Error TA 1 Terminal Address Error Lg 1 Long Word Error NR 1 No Response Error Mn 1 Manchester
18. Error WC zl Wordcount Error Py 1 Parity Error Trigger Start Register Base Address 60H This register defines the first trigger to be used in the trigger sequence This will be in the range 1 to 5 UM 10986 Rev B 61 Examples The first trigger used in the sequence is defined by the contents of the Trigger Start Register For these examples assume that the Trigger Start Register points to Trigger 1 value 1 Key TTR Trigger Type Register Trigger Data Pointer TPP Trigger Pass Pointer TFP Trigger Fail Pointer TSR Trigger Stop Register Example 1 Find the word defined by Trigger Data 1 then save the number of messages defined by the PTC register TTRI TDPI TPPI TSR Example 2 000IH 0001H 0005H 0001H 0006H Find the message with word defined by the Trigger Data 2 followed by the Nth word within the message defined by the Trigger Data 4 Then save the number of messages defined by the PTC register TTRI TDPI TPPI UM 10986 Rev B 000IH 0002H 0002H 0001H 0002H 0004H 0005H 000IH 0006H 62 Example 3 Find the message with word defined by Trigger Data 4 followed by the Nth word within the message defined by Trigger Data 1 by Trigger Data 3 i e Trigger on a specific 32 bit word TTRI 0001H TDPI 0004H TPP 0002H 0001 TTR2 0002H TDP2 000 TPP2 0003H TFP2 000 TTR3 0001H TDP3 0003
19. Interrupt Coding 1 LO andHI priority interrupts two words Messages without error 0800H DDB Address Messages with error 0C00H DDB Address BC Event without RETRY 1000H Status Queue Address BC Event with RETRY 4000H Status Queue Address Send Interrupt SITL SITH 2000 SITL SITH Vector 2 Message Interrupts one word Message Interrupt Code from DDB Only if Message is Good 4 5 2 Set Message Interrupts When in a DDB bit 12 of the option mask word is set e The 10th word gives a set of message numbers to The 12th word gives a message indicator For each set the on board processor manages a set word register It makes an OR with message indicator in the set word register Then if set word register is equal to FFFFH on board processor sends message interrupt code defined in the 9th word of the DDB and resets set word register It is possible to define sets from 2 to 16 messages The user initialises at 0 set of messages table The 256 word set of messages table is pointed to by the set of Messages Start Address 26H in Base registers UM 10986 Rev B 4 5 3 Message Status Report Queue At the end of a message if an event is detected and matches with the 1553B Event Masks of the MDB a Message Status Report is pushed in to the Message Status Report queue 2 words per report Message Number MSB 0 EVENTS with EVENTS BIT 15 BIT
20. MANUAL DESCRIPTION The following paragraphs provide a general description of the manual layout and content Section 1 General Information contains a brief description of the manual and a general description of the Western Avionics IIB 1553 PCI 2C This section also contains the architecture protocol management MIL STD 1553B interface information instrument specifications information concerning accessories furnished items and also safety precautions Section 2 Installation and Preparation for Use contains instructions on installation preparation for use self test and reset of the Western Avionics IIB 1553 PCI 2C card Section 3 Operation contains a functional description of the Western Avionics IIB 1553 PCI 2C and operating procedures necessary to run the card Section 4 Bus Controller Mode of Operation contains information on the mode of operation for the Bus Controller function of the Western Avionics IIB 1553 PCI 2C card Section 5 Multiple Remote Terminal Mode of Operation contains information on the mode of operation for the Multiple Remote Terminal function of the Western Avionics IIB 1553 PCI 2C card Section 6 Chronological Bus Monitor Mode of Operation contains information on the mode of operation for the Chronological Bus Monitor function of the Western Avionics 1553 2C card Section 7 Software tools and support by web access for up grades contains information on the various soft
21. TPP3 0005H TFP3 000 TTR4 0006H Example 4 Find the message with word defined by Trigger Data 4 followed by the Nth word within the message defined by Trigger Data 1 Then selectively capture all messages with word defined by Trigger Data 3 followed by word within the message defined by Trigger Data 2 TTRI 0001H TDPI 0004H TPP 0002H 0001H YTTR2 0002H TDP2 0001H TPP2 0003H TFP2 000 ITR3 0004H TDP3 0003 TPP3 0004H TFP3 0003H TTR4 0005H TDR4 0002H TPP4 0005H 0003H L TSR 0006H UM 10986 Rev B 63 Example 5 Find the message with word defined by Trigger Data followed by the Nth word within that message which does not meet the conditions of Trigger Data 2 TTRI 0001H 000 000 0002H PTTR2 0002H TDP2 0002H TPP2 000 o 0004H TSR 0006H UM 10986 Rev B 64 64 STACK DATA FORMAT When the Bus Monitor is commanded to start all messages will be stored before the trigger condition is met Therefore all pre trigger data is captured The first captured message will start at the address defined by the Start Page Register All following messages will start on an even PAGE boundary The STACK data will wraparound after the Finish Page Register value has been exceeded The format of the messages are shown in table 6 4 Table 6 4 Stack Data Format WORD No NAME 1 Previou
22. follows Size Standard PCI card 175 by 107 mm Power 5Vdc 1 2 Amps Maximum 12Vdc 320 mAmps Maximum Temperature Operating 0 C to 50 C e Non operating 20 C to 70 C MTBF e 82 315 Hrs Ground Benign 25 C Front Panel Connectors UM 10986 Rev B Channel 1 9 Pin sub miniature D type M2408 23 31 e J2 Channel 2 9 Pin sub miniature D type M2408 23 31 10 19 LIST OF FURNISHED ITEMS The following is a list of furnished items 1 Bus Analyser Simulator Model IIB 1553 PCI 2C 2 Users Manual UM 10986 This document 1 10 LIST 0F RELATED PUBLICATIONS The following is a list of related publications 1 MIL STD 1553 2 PCI LOCAL BUS specification 1 11 STORAGE DATA As the PC card contains electrostatic sensitive devices ESD s special storage and handling is required Do not store near electrostatic electromagnetic magnetic or radiation fields 112 TOOLS AND TEST EQUIPMENT No special tools or test equipment is required to test the Western Avionics IIB 1553 PCI 2C 113 SAFETY PRECAUTIONS WARNING UM 10986 Rev B 11 1 14 FRONT PANEL LAYOUT AND CONNECTOR PIN OUT DETAILS Channel 1 Connector J1 PIN DESCRIPTION 1 1553 PRIMARY VE 2 1553 SECONDARY VE 3 TRIGGER OUT COLLECTOR 4 TRIGGER IN CATHODE 5 GROUND 6 1553 PRIMARY VE 7 1553 SECONDARY 8 TRIGGER OUT EMITTER 9 TRIGGER IN ANODE Channel 2 Connector J2
23. register is clear When the command register is clear the user can insert the next command to be executed After the command is loaded bit CO in the control register can be cleared When the command register clears the board is ready for a new command Refer to table 3 2 Table 3 2 Command Register CR CODE COMMAND 0000H Illegal 0001H GO TO BC MODE 0002H GO TO MRT MODE 0003H GO TO MON MODE 0004H BC COLD Start 0005H BC WARM Start 0006H BC STOP 0007H MRT COLD Start 0008H MRT WARM Start 0009H MRT STOP 000AH PAUSE 000BH UNPAUSE 000CH LOAD CLOCK 000DH SELFTEST 000EH RUN MONITOR 000FH STOP MONITOR 0010H Synchronise CLOCK UM 10986 Rev B 21 3 4 2 4 Status Register SR 06H The status register will contain a word reflecting the status of the board as shown in table 3 3 Table 3 3 Status Register CODE STATUS 0001H BC IDLE 0002H MRT IDLE 0003H MON IDLE 0004H BC RUNNING 0005H BC INSERTION RUNNING 8004H BC PAUSED Background 8005H BC PAUSED Insertion 9004H EXECUTING SOFTWARE PAUSE SWPSE A004H EXECUTING HARDWARE PAUSE HWPSE 0006H MRT RUNNING 8006H MRT PAUSED 0007H MON RUNNING 0008H MON RUNNING XXX8H EXECUTING SELFTEST FINISHED SELFTEST The status register will contain the following information after completion of self test D15 D14 D12 D11 DIO DOS
24. the Window Trigger will branch to the trigger defined in the Pass Register If the value of the Window Word Count Register is non zero the Window Trigger will use this value to specify the word number within the message for the Trigger test to be carried out If this value is zero all words within the message will be tested The Window Trigger would normally be preceded by a Single Trigger The Single Trigger would define the specific 1553B command word then pass to the Window Trigger to define a specific bit pattern of a particular word within this message If the Window Trigger Fail Register points back to the Single Trigger requirements then the monitor will start again with the next 1553B message Reserved Selective 1 Trigger Mode The Selective 1 Trigger searches for a particular word as with the Single Trigger type However if the last word of a message is encountered before this trigger condition is met the message is not saved on the stack If this trigger condition is met it will branch to the trigger defined by the Pass Register Selective 2 Trigger Mode This trigger type is the same as the Window Trigger with the following exceptions a If the specific word within the message is not found the message will not be stored on the stack and the next trigger is defined by the contents of the Fail Pointer Register b When the trigger condition is found the message is stored on the stack If the number of selective messages defined b
25. time tag words e A particular way allowing the user to store header words of the data message in a different buffer from the following data words The header option and the number of header words are defined in the option mask Header Address Header Message K Data Message K Header Message 2 Data Message 2 Header Message 1 Header Word Data Message 1 Time Tag High Time Tag Low Data Data Data Buffer Address Data Data UM 10986 Rev 41 DB ADDRESS 1553B BUFFER 00H Time Tag HI 02H Time Tag LO 04H Data 06H Data 08H Data 0AH Data 0CH with or without Header Word Table 4 3 Data Buffers 44 MODE COMMANDS In Bus Controller mode the Western Avionics IIB 1553 PCI 2C board can transmit all mode command messages For each mode command message data descriptor blocks pointed through the look up table allow the definition of interrupt requests or associated data word address storage If such a command is directed to an on board simulated RT the corresponding actions are made on the RT simulation table e Transmit RT status word last command word bit word Inhibit or override inhibit Examples a Synchronise with Data Word The data is obtained from the data buffer pointed by the DDB b Transmit Last Command A DDB is analysed th
26. 000 XXXXH Load loop counter with value XXXX DBNE 000DH XXXXH LOOP LOOP I If lt gt O branch signed offset XXXX INITF 000 XXXXH Initialise frame duration to XXXX LSB 1005 SWPSE 000FH Wait for new on board start of frame HALT 0010H End of BC program SITL _ OOH Set low priority Push XXXX on LO queue SITH 0012H XXXXH Set high priority IRQ Push XXXX on HI queue HWPSE 0013H wait for external Trig LO HI for new frame SMB 0014H XXXXH Send message XXXXH absolute address of TRGOUT 0015 XXXXH Trig out to the XXXXH level e Instructions 1 2 3 e NOPx the user can replace two or three instruction words BSR BRA DNBE offset is defined in bytes count always even offset BSR 15 levels of subroutines available TRGOUT xxxx e Instructions to put TRIGOUT at 0 if xxxx 0000H or 1 if xxxx 0001H On power on the output is on 0 level per default e LOOP xxxx e Load loop counter with value XXXX Only one level of loop UM 10986 Rev B 28 INITF xxxx Minor frame duration minor cycle time e 10 us for the LSB the value for 20ms is 7DOH e It must be initialised at the beginning of the background program This instruction resets the minor frame counter register SWPSE Software Pause e To be put at end of each minor cycle instruction list with the minor frame duration utility to have automat
27. 0000000000000 nennen 11 1 11 STORAGE DATA itte beet ey tin Ebr Ea da eoe tis Ree eve 11 1 12 TOOLS AND TEST EQUIPMENT 1e nies cinere rapere e epe erroe eere ae tee REY OH ye ceeds 11 113 SAFETY PRECAUTIONS uerit AIA MERE RENE INE 11 1 14 FRONT PANEL LAYOUT AND CONNECTOR PIN OUT DETAILS esee 12 1 15 LINKER SUJESO CEREREM 13 1 15 1 Linker Block Functions and Settings eese esee eene eene tenent nennt enne nennen 13 INSTALLATION AND PREPARATION FOR 5 1 eee etes seo sos etna setas eee ee seen aseo 14 2 1 GENERAD alal an 14 2 2 INSTALLATION OF THE IIB 1553 PCI 2C iii 14 2 3 TURN ON e RARI ine tse RA A inno 14 24 RESER Lal 14 2 5 SPECIFICFEATURES m 15 2 5 1 Control Register Features 15 2 5 2 Bg dT M doesn 15 2 5 3 lao rai E 15 2 5 4 Trigger Out Features us ici eet Tee cost QUERN re NOSE TERNI ii 15 2 6 Io WU dI OI anna eni 16 2 6 1 DL 16 2 6 2 Electrical Characteristics nnne 16 2 6 3 Capabilities RITE 16 2 7 1535338 INTERFACE c e aa 1
28. 1 global toggle enabled 0 no toggle offset 15 bits MSB OFFSET 15 14 0 The 5th word in a DDB enables the toggle feature for the corresponding data buffer and the toggle frequency BIT 15 BIT 14 to 11 BIT 10 to 08 BIT 07 to 00 UM 10986 Rev B 1 Enable toggle local 0 Frequency indicator gt 000 FHz 001 F 2Hz 011 F 4Hz 111 F 8Hz Buffer Address 39 When global toggle is enabled for a data buffer if the toggle feature is selected bit 15 1 the address of the toggle buffer is Buffer Address High Toggle Buffer Offset 15 bits Buffer Address Low DDB Buffer Bank A bit15 1 Buffer Address Offset Buffer Bank B The toggle is synchronised on the minor frame counter register which is incremented on each minor cycle restart The on board processor stores the data buffer in bank A or B depending on the number of the running minor cycle and the frequency indicator of the message Minor Cycle O 1 2 3 4 5 6 7 8 9 frequency F F Hz A B F 2 Hz A A B B A F 4 Hz A A F 8 Hz A A 4 3 2 4 Link Pointer to New DDB 0CH If the message is good or bit 10 of the option mask is clear and bit 9 of the option mask is set the value in
29. 10 gt Both Bus Error XXXXXXXXXXXXX 0000000000000 TTT 011 gt Word Count Error XXXXXXXXXXXXX 000000PCCCCCC P Word Count Error Polarity 0 Word Count Error VE 1 Word Count Error VE CCCCCC Word Count Error Value Allows 64 Words TTT 100 gt Response Time Error XXXXXXXXXXXXX 00000000RRRRR RRRR Unique Response Time for simulated RT in uS 101 gt Illegal Command Not applicable for BC Mode XXXXXXXXXXXXX 0000000000000 110 gt Extended Subaddress Not applicable for BC Mode XXXXXXXXXXXXX 0000000000000 TTT 111 gt Resync System Clock Not applicable for BC Mode XXXXXXXXXXXXX 0000000000000 UM 10986 Rev B 24 1 Word Number For the first word of the message command or status WWWWWW 000000 2 Synchro Pattern Error Defines a specific synchro bit each Si defines the level for 500ns duration at least 1 bit of S5 SO must be set 55 54 53 52 51 50 right synchro bit example false synchro bit example 55 50 011001 3 Manchester Bit Error 4 0 defines the bit position in word for the error 4 Word Length Error 0 defines the number of bits in the word NOTE This count has an offset of 1 such that a value of 01111 will result on a valid word with a data bit count of 16 Wrong bus error i RT response on the wrong bus e Both busses error RT response on both busses e Response time error RRRRR replaces the gl
30. 4 Type Register Base Address 26H This register will define the trigger type allocated to trigger 4 This value will be the range 1 to 6 Trigger 4 Data Pointer Base Address 28H This register will define the trigger data allocated to trigger 4 This value will be the range 1 to 4 Trigger 4 Pass Pointer Base Address 2AH This register will define the new trigger to be activated if this trigger condition passes This value will be the range 1 to 5 Trigger 4 Fail Pointer Base Address 2CH This register will define the new trigger to be activated if this trigger condition fails This value will be the range 1 to 5 Trigger Stop Register Base Address 2EH This register will always be programmed to the value 6 This register is the STOP trigger sequence register UM 10986 Rev B 57 Trigger Data 1 Trigger Data 1 Bit Mask Register Base Address 30H This register will define the bits to be ignored in the trigger bit pattern for trigger data 1 Any bit set in this register will be masked from the trigger test condition Trigger Data 1 Bit Pattern Register Base Address 32H This register will define the bit pattern required for trigger data 1 Trigger Data 1 Bus ID Word Type Mask Base Address 34H This register will define the Bus ID and W
31. 49 5 7 2 Reception of Mode Commands Data Words nen nennen 49 5 7 3 Mode Command Synchronise with Data Word 50 5 7 4 Frequency TOggle m 50 6 CHRONOLOGICAL BUS MONITOR MODE OF OPERATION e eeeeee ense en enne serene 51 6 1 INTRODUCTION e 51 6 2 BASE REGISTERS lillo ia e RR e nemus alia 51 6 2 1 Control Register Write tae ati a ple 52 6 2 2 Command Register CR E 52 6 2 3 REPISION SIR ei TITLE ERRORI RENO ONORI I 53 6 2 4 IRO Selection Register iei Puce tes see pte edet ener 53 6 2 5 Load Clock HI LO Registers 38H1 3AH ii 54 6 2 6 Current Address Register CAR 42H 54 6 2 7 Trigger Occurrence Register TOR 44H iii 54 6 2 8 Trigger Set up Pointer TSP 46 eee ieri 54 6 2 8 1 Mn peer Set Up Data gasses sacs ested huss nu ueterem a cetur Ust ens dotes 54 6 3 DETAILED TRIGGER DESCRIPTION 55 64 STACK DATA FORMAT ici treten t tei bete koe Me Pone Pee RE deese te dg 65 6 4 1 Previous Address Pointer ie 65 6 4 2 Time Stamp HYL O p 6
32. 5 6 4 3 pyo 65 6 4 4 Next Address Pointen riscia 66 6 4 5 RI Response Time 1 2 accetto e tite dug tes tpe aiar 66 6 4 6 Flow 66 7 SOFTWARE TOOLS AND 8 2 401 17 04 61 61 80 00 000 1 61106100010001010000 0 0 0 0004 041 toss nio nen eee zione seeeneceeionenne 67 7 1 INTRODUCTION e atin Mech aie aon en ies 67 ZI Loading SOftW re E ree te oce suede CE EL IR 67 7 1 2 SOftW Te SARAI 67 7 1 3 5 SEU mtus 67 7 1 4 Comments and SupgestiOns uui ie tte tete oett at turae ie ei 67 UM 10986 Rev B 4 Figure 1 1 Figure 1 2 Figure 1 3 Figure 3 2 Figure 4 1 Figure 4 2 Figure 5 1 Table 3 1 Table 3 2 Table 3 3 Table 4 1 Table 4 2 Table 4 3 Table 6 1 Table 6 2 Table 6 3 Table 6 4 List of Figures IIB 1553 PCI 2C Functional Block 9 IIB 1553 PCI 2C Front Panel Connectors eene enne trennen trennen 12 IIB 1553 PCI 2C Linker Block locations eene 13 Remote Terminal Simulation 29 Bus Controller Organisation Diagram iii 31 Data B
33. 5 Reserved 46H 3 4 2 26 PRI SEC 1553B RT TX Inhibit HI LO 48H 4EH HI RT 30 n m RT17 RT16 LO RT15 RT14 RTI RTO 0 enable the transmitter 1 disable the transmitter A bit set defines the specific RT transmitter as inhibited Initialisation by the user before cold start Disable enable by corresponding mode command messages The user can modify the inhibit bits in real time The receive function of the simulated RT is never disabled UM 10986 Rev B 28 3 5 REMOTE TERMINAL SIMULATION TABLE For each RT 16 words are used to define and store information concerning RTs RTSTAD must be a multiple of 20H RT31 Broadcast Refer to table 3 2 The pointer to this table Set all others to 0 Broadcast 1553B Look up Table Reserved Broadcast 1553B Mode Commands Look up Table RTSTAD 3 00H Simulation Type word 02H RT Status Word 04H 1553B Last Command Word 06H 1553B Look up Table Address MRT Only 08H Reserved 0AH 1553B Mode Commands Look up table Address MRT Only 0CH Vector Word 0EH 1553B BIT Word RTO 10H Reserved 12H Reserved 14H Reserved 16H Global RT Error Descriptor Word MRT Only 18H Not Used 1AH Not Used 1CH Not Used 1EH Not Used 20H RT1 p 3C0H RT30 1 3E0H Only 3 words used Address Figure 3 2 Remote Terminal Simulati
34. 6 2 7 1 Introduction iaia 16 2 7 2 Electrical Characteristics ii 16 OPERA TION T 17 3 1 INTRODUCTION Aaa 17 3 2 SORA NCO cT 17 3 3 ORGANISATION DIAGRAM opea Rupee e E eee ae Ee EET 17 3 4 BASE REGISTERS i rec i eerte t cott eset i p eee dde etd c pe e eee ipee vical c dee 17 3 4 1 Base Register Names and Locations i 19 3 4 2 Register Descriptions e t eet tetra to eee RR eee Ee Leere ted EL EE s dE ee oe 20 3 4 2 1 Control Register Write eae e RR E a 20 3 4 2 2 Clock Word Read OOH Clock LO Word Read 02H enne 20 3 4 2 3 Command Register CR 04H e te RANA e pa epe exea en eMe ey eene 21 3 4 2 4 Status Register NIE SUE OR M 22 3 4 2 5 Background Running Pointer BRP 08H 23 3 4 2 6 Insertion Running Pointer OAH ii 25 3 4 2 7 Reserved OCH 25 3 4 2 8 LPIQAP 0EH Low priority interrupt queue start address 25 3 4 2 9 I ccs MO 25 UM 10986 Rev B 2 3 4 2 10 HPIQAP 12H High priority interrupt queue start address ie 25 3 4 2 11 Reserved MH sitiorem a i eie be WO dE 25 3 4 2 12 MIQAP 16H Mess
35. Event Mask 04H Message Type Word 06H 1553B Message Error Phase Definition 08H 1553B Message Error Description Word 0AH Address in Look up Table 0CH Command Word 1 0EH Command Word 2 10H Reserved 12H Reserved 14H Retry Subroutine Absolute Address 16H Reserved 18H Inter message Gap Time 1AH Reserved 1CH Status Word 1 received 1EH Status Word 2 for RT RT received 4 2 1 Message Number 00H The number of the message is used in Message Status Report to identify messages 4 2 2 1553B Event Mask 02H A logical AND is carried out with the 1553B event mask and the detected bus events If the result is lt gt 0 a message status report will occur and a retry if selected BIT 15 i Wrong Both bus error BIT 14 No response error BIT 13 i RT address error BIT 12 Transmission error BIT 11 f Wrong sync error Bit 10 to 00 Status bits of RX status word not including address bits UM 10986 Rew 32 4 2 3 Message Type Word 04H BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 to 8 BIT 07 BIT 06 BIT 05 BIT 04 BIT 03 BIT 02 BIT 01 BIT 00 UM 10986 Rev B 1 1553B TX on PRI bus 1 1553B TX on SEC bus 0 0 11 10 09 08 0 0 0 0 1553B MODE WITHOUT DATA 0 0 0 1 1553B MODE WITH DATA 0 0 1 0 1553B RT RT 0 0 1 1 1553 0 1 0 0 Reserved 0 1 0 1 Reserved 0 1 1 0 Reserved 0 1 1 1 Reserved 0 0 0 0 1553B MODE WITHOUT DATA BROADCAST 1 0 0 1 1553B MODE WITH DATA BROADCAST 1 0 1 0
36. IIB 1553 PCI 2C board does not store more data words than the number defined by Data Word Count if no header option or Data Word Count Header Word Count 1 if header option Data Word Count is defined in the DDB extra word for 1553B messages will be the last received word of a message in excess of the DDB data word count 55 1553B ERROR INJECTION DEFINITION Error injection on status word and 1553B data words transmitted can be defined message by message using the message error descriptor word in the look up table or globally for all messages transmitted by an RT using global RT error injection word in each RT simulation table UM 10986 Rev B 46 5 5 1 Global RT Error Description Word RT Simulation Table The following word defines the errors that can be injected into the message 05 014 012 DII DIO 009 D07 D06 DOS 004 D02 T T T X X X X X X X X X X X 000 gt Modulation Error XXXXXXXXXXXXX WWWWWWYYYYYYY WWWWWW Word Number For Modulation Error Y Y Y Y Y Y Y E ERROR TYPE 0 0000 00 Parity error 0 S5 S4 S3 S2 SI SO Synchro Pattern Error 1 0 B4 B3 B2 BI BO Manchester Bit Error 1 1 14 L3 I2 LI LO Word Length Error 001 gt Wrong Bus Error XXXXXXXXXXXXX 0000000000000 TTT 010 gt Both Bus Error XXXXXXXXXXXXX 0000000000000 TTT 011 gt Word Count Error 000000PCCCCCC Word Count Error Polarity 2 Word Count Erro
37. Illegal 0 1 Trigger on Status 0 1 Trigger on Primary 1 0 Trigger on Data 1 0 Trigger on Secondary 1 1 Trigger on RT RT Transfer 1 1 Trigger on Both Buses Trigger Data 2 Error Word Mask Register Base Address 44H This register will define if the Error Word Register is to be included in the trigger condition DIS D14 D13 D12 D11 DIO D09 008 007 DOS D04 D02 D01 DOO 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 D 1 Error condition disabled Trigger Data 2 Error Word Register Base Address 46H This register will define the Errors required in the trigger condition If more than one error is set the trigger condition will be a logical OR of the errors D15 D14 D13 D12 D11 DIO 0081007 DOS D04 D02 DOO 0 0 0 Sh O 0 WC 0 0 NR TA 5 0 Sy 1 Sync Type Error Sh 1 Short Word Error TA 1 Terminal Address Error Lg i Long Word Error NR 1 No Response Error Mn 1 Manchester Error WC 1 Wordcount Error Py E Parity Error UM 10986 Rev B 59 Trigger Data 3 Trigger Data 3 Bit Mask Register Base Address 48H This register will define the bits to be ignored in the trigger bit pattern for trigger data 3 Any bit set in this register will be masked from the trigger test condition Trigger Data 3 Bit Pattern R
38. Set mains power on host computer to ON The Western Avionics IIB 1553 PCI 2C will perform system self test on each channel for the BC MRT and CM lasting approximately four seconds 2 4 RESET The Western Avionics IIB 1553 PCI 2C hardware and firmware are reset as follows Reset e Signal RES from the PCI bus Power up and power down Bit location in control register accessible by the PCI interface UM 10986 Rev B 14 2 5 SPECIFIC FEATURES 2 5 1 Control Register Features This is a 16 bit write only register accessible from the PCI bus This register is mapped into the memory field The features are as follows Hardware reset Three prioritised interrupts to the local on board processor for indication and control Acknowledge PCI Interrupt 2 5 2 Counter Features This 32 bit counter is a free running counter with a 0 515 or LSB and can be read from a memory mapped location via the PCI bus interface The counter should be read in a single 32 bit access The counter can be updated and used by the on board processor as follows Used Data buffers time tagging Frame cycles control Bus Monitoring Updated User request 1553B command 2 5 3 Trigger In Features Trigger In enters the board logic through a 9 way socket connector and then an opto coupler Inputs to this feature can be used for hardware starts of the major and or minor frames or external trigger for the bus monitor 2 5 4 Trigger Feature
39. T s Different RT response time can be defined in the error description words LSB lus For some modes this global RT response time register is not programmable fixed at 4us e 1553B Mode without data If the value is less than 4 on board processor selects 415 3 4 2 22 RT No Response Time Out Register RT Response Time The programmable response time out defines maximum response time allowed by the board to an RT before detecting NO RESPONSE LSB lus UM 10986 Rev B 26 3 4 2 23 IRQ Selection Register 34H DIS 014 DI2 DIO 007 DOS D04 DOI 0 0 0 0 Cycling Message HI Queue LO Queue 0 0 0 0 M 0 0 H 0 0 L C If set a physical INTA interrupt will be generated when a Broadcast Synchronise With Data mode code occurs M If set a physical INTA interrupt will be generated when a push to the Message Queue occurs If set a physical INTA interrupt will be generated when a push to the High Priority Queue occurs L Tf set a physical INTA interrupt will be generated when a push to the Low Priority Queue occurs 3 4 2 24 T
40. UT p Time Tag HI Time Tag LO Tlegalization Word Data buffer Address Data DDB Address Low High Priority Priority TX Interrupt Interrupt Message Message Interrupt Status Report Figure 5 1 Multiple Remote Terminal Organisation Diagram UM 10986 Rev B 45 52 LOOK UP TABLES For each RT the Western Avionics IIB 1553 PCI 2C board manages three different look up tables the address of these tables are obtained from the RT simulation tables These tables are as follows 1553B Look up Table giving a descriptor for each 1553B sub address 1553B Mode Command Look up Table giving a descriptor for each 1553B mode code NOTE The T R bit of the Command word or Action word is used as an offset to point to the RX or TX block of the look up tables Each descriptor includes Message Error Description or Illegalization word e Data Descriptor Block Address or Extended sub address look up table address as for BC mode 53 MODE COMMANDS SPECIFICATIONS illegal mode codes defined in the 1553B standard are automatically illegalized The error descriptor word allows illegalization of complementary mode codes Associated data words which are not obtained from the RT Simulation Tables can be obtained from or stored in memory using Data Descriptor Blocks For each mode code DDB can be used to define IRQ s 54 DATA WORDS STORAGE To avoid data buffers overwriting in memory when receiving a data message the
41. XXXXXXXXXX 0000000000000 110 gt Extended Subaddress XXXXXXXXXXXXX 0000000000000 111 gt Resync System Clock XXXXXXXXXXXXX 0000000000000 NOTE For NO ERROR set 000 and WWWWWW 111111 UM 10986 Rev B 48 5 6 INTERRUPTS CODING 5 6 1 Low and High Priority Interrupts two word code On data messages without error 0800H DDB address On data messages with error 0C00H address On mode commands without error 0900H DDB address On mode commands with error 0D00H DDB address 5 6 2 Message Interrupts or set of messages interrupt One word code equals message interrupt code in data descriptor block The code is pushed in queue only if the message is correct Sets of Messages Same feature as for BC mode 5 63 Status Report Queue two words per report Code pushed into queue only if error on message and Interrupt on erroneous message not set in the Ist Word Pointer to the double word in look up table look up table address index 2nd Word Events BIT 15 Wrong Both Buses Error IT14 No Response Error IT13 RT Address Error IT12 TX Error Mn Lg Sh Py WC Late Response BIT 11 SYNC Type Error BIT 10 to 0 Not Used 5 7 SPECIFIC FUNCTIONS 5 7 1 Data Message Reception Each data message not transmitted by the Western Avionics IIB 1553 PCI 2C board may be stored The path to access the data buffer is given by the RT look up table for messages BC lt
42. age interrupt queue start address e 25 3 4 2 13 Reserved SH ani ri o RR epe er Div ERREUR E ERO ens 3 4 2 14 SRQAP Status report queue start address i 3 4 2 15 Reserved 1CH sssuaziia O 3 4 2 16 RTSTAD RT simulation table start address 3 4 2 17 Reserved 20 paia lanciando 3 4 2 18 Reserved 22H pir HE E E dE eed 3 4 2 19 Toggle Buffer Address Offset 24H ener eiim etre ee EE Ed ee eee EP eoa ERE 3 4 2 20 Set of Messages Start Address 26H 3 4 2 21 Global RT Response Time Register 28H 3 4 2 22 RT No Response Time Out Register ie 3 4 2 23 IRQ Selection Register em Pe Bo ie 3 4 2 24 Test and Set Register and SRQADP 3CH 3 4 2 25 Reserved 46 tenido 3 4 2 26 PRI SEC 1553B RT TX Inhibit HI LO 48H 4 3 5 REMOTE TERMINAL SIMULATION TABLE i 3 5 1 Simulation Type Word i eret re ERI PEE aiar 2 9 2 Armor EL n 3 9 9 1353B East Command Word eee itinerari PER ENDE 3 5 4 1353B Bit upon 4 BUS CONTROLLER OF OPERATION scscsssssssssssssccssesesscsssssesscsssscessessessesssssessesssssesssssnesees 31 4 1 INTRODUCTION Bor
43. be activated if this trigger condition fails This value will be the range 1 to 5 Trigger 2 Trigger 2 Type Register Base Address 16H This register will define the trigger type allocated to trigger 2 This value will be the range 1 to 6 Trigger 2 Data Pointer Base Address 1 8H This register will define the trigger data allocated to trigger 2 This value will be the range 1 to 4 Trigger 2 Pass Pointer Base Address This register will define the new trigger to be activated if this trigger condition passes This value will be the range 1 to 5 Trigger 2 Fail Pointer Base Address This register will define the new trigger to be activated if this trigger condition fails This value will be the range 1 to 5 UM 10986 Rev B 56 Trigger 3 Trigger 3 Type Register Base Address This register will define the trigger type allocated to trigger 3 This value will be the range 1 to 6 Trigger 3 Data Pointer Base Address 20H This register will define the trigger data allocated to trigger 3 This value will be the range 1 to 4 Trigger 3 Pass Pointer Base Address 22H This register will define the new trigger to be activated if this trigger condition passes This value will be the range 1 to 5 Trigger 3 Fail Pointer Base Address 24H This register will define the new trigger to be activated if this trigger condition fails This value will be the range 1 to 5 Trigger 4 Trigger
44. beginning of each minor cycle and toggles bank A or B are managed when this message occurs Minor Cycle O 1 2 3 4 5 6 7 8 9 frequency F F Hz A B B B B F 2 Hz A A B B A F 4 Hz A A A F 8 Hz A A A A UM 10986 Rev 50 6 CHRONOLOGICAL BUS MONITOR MODE OF OPERATION 61 INTRODUCTION When acting in BC or MRT mode a comprehensive window monitor facility is provided However the Western Avionics IIB 1553 PCI 2C can also act as a chronological monitor for bus event detection and message recording In this mode the Western Avionics IIB 1553 PCI 2C can be set to trigger on specific events and sequentially record precise time stamped messages a stack size and position of this stack can be defined by the user NOTE When the Western Avionics IIB 1553 PCI 2C is in this mode the BC MRT facility is not available address pointers for the Bus Monitor are 16 bit words defining a PAGE address Each page is 32 bytes Example If a message pointer contains the value 2301H this indicates an absolute address of 2301H x 20H BASE 46020H 6 2 BASE REGISTERS Table 6 1 Base Registers BASE REGISTER 00H Control Register Write Clock HI Word Read 02H Cloc
45. d Running Pointer BRP Address of Program 0AH Insertion Running Pointer IRP Address of Program 0CH Reserved 0EH Low Priority Interrupt Queue Start Address Pointer 10H Reserved 12H High Priority Interrupt Queue Start Address Pointer 14H Reserved 16H Message Interrupt Queue Start Address Pointer 18H Reserved Status Report Queue Start Address Pointer 1CH Reserved EH RT Simulation Table Address Register RTSTAD 20H Amplitude Register 22H Coupling Register 24H Toggle Buffer Address Offset MSB 1 Global Enable 26H SET OF MESSAGES Start Address 28H Global RT Response Time Register us 2AH RT No Response Timeout Register us 2CH Reserved 2EH Reserved 30H Reserved 32H Reserved 34H IRQ Selection Register 36H Minor Frame Counter Register 38H Load Clock HI Register 3AH Load Clock LO Register 3CH Test and Set register TASR 3EH Service Request Queue Address Pointer SRQADSP 40H Cycling Interrupt Update Register 42H Monitor Current Address Register CAR 44H Monitor Trigger Occurrence Register TOR 46H Monitor Trigger Set up Pointer TSP 48H PRI Bus 1553B RT TX inhibit bits 4AH PRI Bus 1553B RT TX inhibit bits LO 4CH SEC Bus 1553B RT TX inhibit bits 1 4EH SEC Bus 1553B RT TX inhibit bits LO 50H Reserved 52H Reserved 54H Reserved 56H Reserved 19 3 4 2 Base Register Descriptions The Base Register functions are defined in the following paragraphs 3 4 2 1 Control Regist
46. e data word transmitted is stored in the data buffer If the RT is simulated the last command word from the RT simulation table Is transmitted c Transmit Bit Word Similar to transmit last command d Transmit Vector Word Similar the transmit last command and then if the RT is simulated the service request bit in the RT status word is reset and the vector word is reset or updated with the next vector word in FIFO s if any UM 10986 Rev B 42 45 INTERRUPT REQUESTS Three types of interrupt requests IRQ can be generated by the Western Avionics IIB 1553 PCI 2C board IRQ L and IRQ H low priority and high priority are synchronisation interrupts defined as follows By instructions in the BC instruction list In message descriptor block to report on bus events detection In data descriptor block to signal transmission of a message RQ M is a data message interrupt and occurs only when the transmission of a data buffer is correct and the requesting bit is set in the data descriptor block It can also be programmed to occur with the last message of a set of 2 to 16 messages set of messages option When setting an IRQ the Western Avionics IIB 1553 PCI 2C board pushes a vector code into queues each code defines the event origin of the IRQ Each queue must start at an address multiple of 200H The user must manage the reading pointer and erase with a 0000H value the codes after reading 4 5 1
47. egister This register will define the bit pattern required for trigger data 3 Trigger Data 3 Bus ID Word Type Mask Base Address 4AH Base Address 4CH This register will define the Bus ID and Word Type bits to be ignored in the Bus ID Word Type Register D15 D14 D13 D12 D11 DIO 0081007 DOS D04 D02 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Both W bits 1 Ignore Word Type in trigger condition Both B bits ze Ignore Bus ID in trigger condition Trigger Data 3 Bus ID Word Type Register Base Address 4EH This register will define the Bus ID and Word Type for the trigger condition D15 D14 D13 D12 D11 DIO 0081007 DOS 004 D02 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 WMsb WLsb BMsb BLsb 0 0 Trigger on Command 0 0 Illegal 0 1 Trigger on Status 0 1 Trigger on Primary 1 0 Trigger on Date 1 0 Trigger on Secondary 1 1 Trigger on RT RT Transfer 1 1 Trigger on Both Buses Trigger Data 3 Error Word Mask Register Base Address 50H This register will define if the Error Word Register is to be included in the trigger condition D15 D14 D13 D12 D11 DIO 0081007 DOS 004 D02 DOO 0 0 D 0 0 0 0 0
48. er Write 00H D15 014 D12 DIO 006 DOS 1004 002 DOI 0 0 0 0 0 0 0 HR 0 IRQ 0 0 0 1 CO CO Clear gt Command Request Cl Clear gt Insertion Request HR Clear gt Hardware RESET If IEN is set and IRQ is set then interrupt line will be cleared If is set and IRQ is clear then the interrupt line will be asserted for test purposes only If IEN is clear the value of IRQ is unaffected Note This register must be accessed to clear the interrupt during an interrupt service routine Examples 1 0102H generates a command request 2 0163H clears the interrupt line 3 4 3 2 Clock HI Word Read 00H Clock LO Word Read 02H Local Clock Reading CK HI LO Read as a 32 bit word Update Local Clock by the User Write the new value in the registers LOAD Clock HI LO Registers Write the LOAD CK code 000CH in the command register Write CO 0 in control register After executing command on board processor sets CO to 1 See Command Register below Synchronise Clock If the above procedure is carried out using the synchronise clock command 0010H the contents of LOAD Clock HI will be added to the current clock value as a 32 bit signal offset UM 10986 Rev B 20 3 4 2 3 Command Register CR 04H Prior to clearing the command request bit CO in the control register the user must first test that the command
49. er and the C Driver Library P N 1L01616H01 to it s own folder Please follow on screen instructions when loading this software 7 1 2 Up grading Software It is advisable to check our web site at http www western av com to down load any up grades that may be made available for your unit and to see any new releases of support software 7 4 3 On line support If you have any problems with any software provided please contact by e mail at support western av com for prompt attention 7 1 4 Comments and suggestions If you find any errors or areas that are confusing in this manual we would like to hear from you Comments and suggestions can be made on line to support western av com please just reference this User Manual UM 10986 Rev A with your text You may also forward comments and suggestions by fax to 353 61 471675 UM 10986 Rev B 67
50. est and Set Register and SRQADP 3CH These two words are used to automatically manage FIFO s of vector words for each simulated RT For simulated RTs the Service Request bit in the status word can be set and reset by the user The vector word can be initialised by the user After a Transmit Vector Word mode command message the on board processor automatically resets the service request bit and the vector word On the other hand a service request queue is defined to automatically queue words representing successive requests for the simulated RTs This service request queue is 3 words long starting at the initial address in the service request queue address pointer SRQADP For a request two words are set in the queue as follows 1 RT number 000000000RRRRRIX RT address X Priority BIT 1 1 25 Vector word Two different priorities are available X O High priority X Low priority Reading this FIFO the on board processor manages each RT two 32 word vector words FIFO s one per priority These vector words are then used by the RT simulation If an RT FIFO is not empty the on board processor reads it then writes the value in RT vector words RT Simulation Table and sets the service request bit in the status word If a Transmit Vector Word mode command message occurs the on board processor reads the RT FIFO s e Ifempty the on board processor resets the service request bit and the vector word Otherwise on b
51. gt Except for RT gt RT messages even if the RTs are simulated or not the path to point to the data buffer is always given by the transmitting RT look up table but the receiving RT look up table must point to a false DDB Received status words from RTs not simulated on board are stored in the associated disabled RT SIM table If an external RT fails to respond a value of FFFFH will be stored in the SIM table 5 7 3 Reception of Mode Commands Data Words For each mode command with data word message if the data word is not transmitted by the board it must be stored RT simulated or not The path for storing the data word is given by the RT mode command look up table UM 10986 Rev B 49 5 7 3 Mode Command Synchronise with Data Word When receiving a broadcast mode command Synchronise with Data word the on board processor e Stores the data word value in the Cycling Interrupt Update Register in base registers and set the cycling IRQ Accesses to a DDB to store the data word in a buffer and time tag the data buffer e Uses the value of the data word which is for example the minor cycle number 0 to 7 to manage frequency toggling of the data buffers 5 7 4 Frequency Toggle The frequency toggle option works in the same manner as the BC mode except that the minor cycle number is given by the data word associated to the mode command synchronise with data word This mode command is due to circulate on the bus at the
52. ic minor frame restart Examples INITF xxxx HWSPE waiting an external trig SWPSE JSR Minor Cycle 1 SWPE SWPSE BRA xxxx with Minor cycle X SMB xxxx SMB xxxx RTS LOOP 8 JSR Minor cycle SWPSE DBNE xxxx SITH BRA xxxx e Insertion Commands be executed during SWPSE state HALT e On completion of this instruction the board will return to the BC idle state To re start the board Cold Warm Start command register SITH SITL e The on board processor puts the value code xxxx in the cycling FIFO s gt Priority gt Low Priority HWPSE Hardware Pause Restart by external Trig In external CK e the registers are not initialised e Used to synchronise messages of minor frames on external Trig In Example See SWPSE above UM 10986 Rev B 24 3 4 2 6 Insertion Running Pointer The Insertion Running Pointer IRP has the same set of instructions as Instruction Set Background Program To initiate an insertion the user must first load with the address of the insertion program Then bit Cl can be cleared in the control register The background program be interrupted by an insertion command The insertion program cannot be interrupted by any other insertion command In this case the second insertion request will be delayed until the end of the first one Insertion
53. k LO Word Read LSB of clock 0 5 uS 04H Command Register CR 06H Status Register SR 08H Reserved to Reserved 2AH Reserved 2CH Reserved 2EH Reserved 30H Reserved 32H Reserved 34H IRQ Selection Register 36H Reserved 38H Load Clock HI Register 3AH Load Clock LO Register 3CH Reserved 3EH Reserved 40H Reserved 42H Current Address Register CAR 44H Trigger Occurrence Register TOR 46H Trigger Set up Pointer TSP UM 10986 Rev B 51 6 2 1 Control Register Write 00H 05 14 D13 D12 DIO 006 DOS 104 002 DOI 0 0 0 0 0 0 0 HR 0 IRQ 0 0 0 1 CO CO Clear gt Command Request Cl Clear gt Insertion Request HR Clear gt Hardware RESET If IEN is set and IRQ is set then interrupt line will be cleared If is set and IRQ is clear then the interrupt line will be asserted for test purposes only If is clear the value of IRQ is unaffected Note This register must be accessed to clear the interrupt during an interrupt service routine Examples 1 0102H generates a command request 2 0163H clears the interrupt line 6 2 2 Command Register CR Prior to clearing the Command Request bit CO in the Control Register the user must first test that the CR is clear When the CR is clear the user can insert the next command to be executed Refer to table 6 2 Table 6 2 Command Registers
54. n simultaneously be simulated non simulated data buffers can be monitored internal minor frame duration counter allows autonomous control of cycling Insertion instruction lists define sequences of same way as in the Multi Remote mode frames Acrylic messages can be inserted on the host request messages to be inserted Refer to figure 4 1 the Bus Controller Organisation Diagram Message Descriptor Block BASE REGISTER M ssa NI bi r Background Program X ieee BRP Area RF Ml Address in LUT gt ToLUT aaa 4 gt SMB Insertion Progr 5 gram DATA BUFFERS Queues Address Time Tag HI RT Simulation High Priority Interrupt RTSTAD ha A Table RTO RTI n DDE Time Tag LO 4 Options mask RT30 Data buffer Address HI 1553B LUT Data buffer Address LO Reserved MRT Low Priority Interrupt DDB Address Address from MDB Message Message Interrupt Status Report tei BC MRT MRT Figure 4 1 Bus Controller Organisation Diagram 2312 UM 10986 Rew 42 MESSAGE DESCRIPTOR BLOCK MDB Each bus message is defined by a message descriptor block as shown in table 4 1 Table 4 1 Message Descriptor Block MBD ADDRESS MESSAGE NUMBER 02H 1553B
55. nes Data buffers to be issued by the BC or the simulated RTs are transmitted by the Western Avionics IIB 1553 PCI 2C board all others can be monitored A multiple data buffering structure is implemented These paths use a look up table and data descriptor block Refer to figure 4 2 Data Buffers Simulation and Monitoring LOOK UP TABLE Reserved MRT Data descriptor Block Address Reserved MRT Data descriptor Block Address Figure 4 2 Data Buffers Simulation and Monitoring UM 10986 Rev B 1553B TYPE DATA DESCRIPTOR BLOCK Option mask Header Address Data Word Count Data Status Report Toggle Freq Buffer Addr High Buffer Address Low Link Pointer to another Reserved Reserved Message Interrupt Code Set of Message Number Reserved Reserved Reserved Reserved 537 1553B DATA BUFFERS Time Tag High Time Tag Low Data Data Data Data Data 4 3 1 Look Up Table The sixth word of a message descriptor block points to a double word in the look up table that contains the address of a 1553B data descriptor block An identical architecture is defined in MRT mode but using 1553B subaddresses to point into the look up table Look up Table Address Error Injection Word MRT only 02H i DDB Address Extended Subaddress look up table address 4 3 2
56. o be accessed with header mounted towards the PCI front panel as indicated above L2 and L3 are provided for connection of the Secondary buses of the two channels to one another as may be required and are supplied without this feature enabled with header mounted away from the PCI front panel as indicated Please note that the 1553 differential lines are routed to L2 negative and L3 positive so both headers should be located identically for this feature to operate correctly L4 and L5 are provided for connection of the Primary buses of the two channels to one another as may be required and are supplied without this feature enabled with header mounted away from the PCI front panel as indicated Please note that the 1553 differential lines are routed to L4 negative and L5 positive so both headers should be located identically for this feature to operate correctly UM 10986 Rev B 13 2 INSTALLATION AND PREPARATION FOR USE 2 1 GENERAL On delivery inspect the unit for possible damage 1f it is damaged notify the shipping company and contact your distributor or the Western Avionics for details of return procedure When unpacking remove all protective covering and store covering and packing container as unit may need to be reshipped at a later date 22 INSTALLATION OF THE IIB 1553 PCI 2C Prior to installing the Western Avionics IIB 1553 PCI 2C ensure that all power has been removed from the host computer 23 TURNON
57. oard processor reads the FIFO s and writes this next value in the RT vector word High priority vector words are processed before low priority vector words The following 4Kbyte block after the service request queue is reserved for the individual RT requesting FIFO s managed by the on board processor gt T SERVICE REQUEST QUEUE 003EH nie 0040H ire gt Pr UM 10986 Rev B Dfe To enter a request in the User Requesting Queue the user must manage the current writing pointer SRQADP in Base Registers and control the words pointed at are clear if these words are non zero the queue is full Reaching the end of the queue the user must restart at the beginning of the queue If several user CPUs can enter requests at the same time it is necessary to share control of SRQADP using for example the TASR flag with a test and set instruction To enter a request a CPU must carry out the following procedure Test and set the TASR word MSB bit and a e If free the SRQADP is read to define the entry address in the queue If the entry location defined by the SRQADP are clear the two words may be entered in the queue If these words are non zero the queue is full Increments the SRQADP if the end is reached reinitialise it to the beginning Resets the TASR If not free waits until free 3 4 2 2
58. obal RT response time LSB uS e Illegal command Reserved for MRT only 4 2 6 Address in Look Up Table 0AH This will contain the address in the look up table for the DDB pointer See figure 4 1 4 2 7 Command Word 1 0CH First Command Word 4 2 8 Command Word 2 0EH Second Command Word RT RT 1553B 4 2 9 Retry Subroutine Absolute Address 14H On completion of a message if an Event defined by the Mask has occurred and the Retry Event is enabled the Subroutine defined by this absolute address will be called NOTES 1 The retry subroutine must be terminated by the RTS instruction to return execution back to the main background or insertion program 2 This feature can be used for immediate insertion of Acyclic messages or retry of the same message on the alternate bus UM 10986 Rev B 35 4 2 10 Inter message Gap Time 18H e Gap between the end of this message and the 1553B line and the beginning of the next one next MDB LSB 01 05 4 2 11 Status Word 1 ICH First RX Status Word in the message If the BC detects no response error this value will be updated with FFFFH 4 2 12 Status Word 2 Second RX Status Word in the message RT RT If the BC detects a no response error from the second RT this value will be updated with FFFFH UM 10986 Rev B 36 43 DATA BUFFERS SIMULATION AND MONITORING The Western Avionics IIB 1553 PCI 2C board processes all the data buffers running on the 1553B li
59. on Table 3 5 1 Simulation Type Word Bits 14 to 0 are for MRT only UM 10986 Rev BIT 15 BIT 14 BIT 13 BIT 12 BIT 7 BIT 6 BIT 0 other bits Bits 7 and 6 RT simulated 1 Reserved 1 Inhibit transmitter 1553B on primary bus 1 Inhibit transmitter 1553B on secondary bus Errors enabled on primary bus status word and data Errors enabled on secondary bus Status word and data 1 Enable global error injection 0 Enable global RT errors defined in the RT simulation table as message per message errors defined in the look up tables 29 3 5 2 Status Word Broadcast and message error bits are dynamically updated Service request bit automatically set by the request files and cleared by the TX vector word mode code command Busy bit can be set by user to disable data transmission 3 5 3 1553B Last Command Word Automatically updated including broadcast so the TX last command mode code is correctly simulated 3 5 4 1553B Bit Word For user purposes UM 10986 Rev B 30 4 BUS CONTROLLER MODE OF OPERATION In the Bus Controller mode the Western Avionics IIB 1553 PCI 2C board runs a list of instruction pointed to by the Each bus message is defined by a Message Descriptor Block 41 INTRODUCTION Background Running Pointer defining the bus frame MDD and the associated data is accessed through a Look Up Table LUT and Data Descriptor Blocks DDB the Remote Terminals ca
60. ord Type bits to be ignored in the Bus ID Word Type Register D15 D14 D13 D12 D11 DIO 0081007 DOS 004 D02 0011 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Both W bits 1 Ignore Word Type in trigger condition Both B bits 1 Ignore Bus ID in trigger condition Trigger Data 1 Bus ID Word Type Register Base Address 36H This register will define the Bus ID and Word Type for the trigger condition D15 D14 D13 D12 D11 DIO 0081007 DOS 004 D02 0011 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 WMsb WLsb BMsb BLsb 0 0 Trigger on Command 0 0 Illegal 0 1 Trigger on Status 0 1 Trigger on Primary 1 0 Trigger on Data 1 0 Trigger on Secondary 1 1 Trigger on RT RT Transfer 1 1 Trigger on Both Buses Trigger Data 1 Error Word Mask Register Base Address 38H This register will define if the Error Word Register is to be included in the trigger condition D15 D14 D13 D12 D11 DIO 0081007 DOS 004 DO2 DOO 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 D 1 Error condition disabled Trigger Data 1 Error Word Register Base Address 3AH This register will define the Errors required in the trigger condition If more than one error is set the trigger condition will be a logical OR of the errors D15 D14 D13 D12 D11 DIO 0081007 DOS 004 D02 DOO 0 0 0 Py Sh 0 0 WC 0 0 NR TA 5 0
61. program starting just before a minor cycle start will delay this one is updated by on board processor after executing stop command 3 4 3 7 Reserved 0CH 3 4 25 LPIQAP 0EH Low priority interrupt queue start address 3 4 2 9 Reserved 10H 3 4 2 10 HPIQAP 12H High priority interrupt queue start address 3 4 2 11 Reserved 14H 3 4 2 12 MIQAP 16H Message interrupt queue start address 3 4 2 13 Reserved 18H 3 4 2 14 SRQAP Status report queue start address 3 4 2 15 Reserved ICH 3 4 2 16 RTSTAD RT simulation table start address Contains the address of the RT Simulation Tables which defines the RT status when they are simulated 3 4 2 17 Reserved 20H 3 4 2 18 Reserved 22H UM 10986 Rev B 25 3 4 2 19 Toggle Buffer Address Offset 24H MSB 1 globaltoggleenable 0 toggle offset 15 bits MSB offset 15 14 0 For a data buffer if toggle feature is selected bit 15 1 address of toggle buffer is Buffer Address High Toggle Buffer Offset Buffer Address Low 15 bits For further details refer to paragraph 4 3 3 3 3 4 2 20 Set of Messages Start Address 26H This is the pointer of a 256 word table reserved to on board processor to compute registers Set of Messages For further details refer to paragraph 4 5 2 3 4 2 21 Global RT Response Time Register 28H This is response time for all the simulated R
62. r VE 3 Word Count Error VE CCCCCC Word Count Error Value Allows 64 Words TTT 100 gt Response Time Error XXXXXXXXXXXXX 00000000RRRRR RRRR Unique Response Time for simulated RT in uS See NOTE 4 in paragraph 5 5 2 NOTE Global error injection is enabled disabled by the LSB bit of the simulation type word UM 10986 Rev B 47 001 5 5 2 Message Error Injection Word Look up Table The following word defines the errors that can be injected into the message 05 014 D12 DII DIO 009 D07 D06 005 004 003 002 DOI T T T X X X X X X X X X 0 X X X 000 gt Modulation Error XXXXXXXXXXXXX WWWWWWYYYYYYY WWWWWW Word Number For Modulation Error O status word 1 19 data word Y Y Y Y Y Y Y ERROR TYPE 0 0000 00 Parity error 0 S5 S4 S3 S2 SI SO Synchro Pattern Error 1 0 B4 B3 B2 BI BO Manchester Bit Error 1 1 L4 L3 I2 LI LO Word Length Error TTT 001 gt Wrong Bus Error XXXXXXXXXXXXX 0000000000000 010 gt Both Bus Error XXXXXXXXXXXXX 0000000000000 TTT 011 gt Word Count Error XXXXXXXXXXXXX 000000PCCCCCC P Word Count Error Polarity 0 Word Count Error VE 1 Word Count Error VE CCCCCC Word Count Error Value Allows 64 Words TTT 100 gt Response Time Error XXXXXXXXXXXXX 00000000RRRRR RRRR Unique Response Time for simulated RT in uS See NOTE 4 in paragraph 5 5 2 101 gt Illegal Command XXX
63. r of messages to be stored after the trigger condition is met This value will be in the range 0000H to 8000H 0000H Stop immediately after trigger message 8000H Capture Forever 02H Selective Capture Count Register SCCR This register will contain the number of messages to be stored when the monitor is in the Selective Capture Mode This value will be in the range 0000H 8000H 20000H 1 message 8000H Selective Capture Forever 04H Start Page Register SPR This register will contain the desired PAGE address for the start of the monitor stack area 06H Finish Page Register FPR This register will contain the desired PAGE address for the end of the monitor stack area This value must be greater than the Start Page Register value 08H Window Word Count Register This register will contain the word number in the specified message on which the window trigger test is to be carried out If this value is zero the test will be carried out on any word within the specified message 0AH Reserved UM 10986 Rev B 54 0CH Hardware Trigger Register 015 D14 D13 D12 D11 DIO 009 008 DOS D04 0031002 D01 DOO 0 0 0 0 0 0 0 0 0 0 T N The Monitor will wait for LO HI transition on the TRIG IN input before storing messages and searching for the software trigger condition N 1 The Monitor will wait for a HI LO transi
64. rminal Features Simulation Up to 31 1553B RT simulations Mode and Broadcast commands handling Comprehensive Error Injection Data Words Transfers Data buffer simulation for simulated RTs Sub address based data buffer access offering same powerful data buffering as in bus controller mode non transmitted data messages monitored 13 4 Chronological Bus Monitor CM Features Capture of all bus activity in chronological stack with time tagging of each message Comprehensive multi trigger facilities allowing selective capture and interrupts to be performed on complex data sequence Cyclical stack up to 2Mbyte with interrupt on completion of capture 1553B errors detected UM 10986 Rev B 8 14 1553 2 ARCHITECTURE The Western Avionics IIB 1553 PCI 2C board is a memory mapped PCI MIL STD 1553B interface with high performance architecture and complex features Placed in a 3 3V or 5V PCI slot universal the IIB 1553 PCI 2C card provides enhanced test and simulation functions for all modes of operation of a MIL STD 1553B bus The host equipment using the on board RAM defines all configuration and data structures INTERRUPT 4 UNIVERSAL PCI INTERFACE Protocol Channel 2 Management 1553B Unit INTERFACE 1553B Lines in out Protocol Channel 1 Management 1553B 1553B Lines in out Unit INTERFACE
65. s Trigger Out is in fact a bit in a register accessible by the on board processor to indicate to the external world that an event has been detected This event can be as follows Beginning of major and or minor frames Beginning of a message Bus Monitor trigger detected Trigger Out exits the board through an opto coupler and a nine way socket connector on the front panel UM 10986 Rev B 15 26 PCI INTERFACE 2 6 1 Introduction The PCI interface on the Western Avionics IIB 1553 PCI 2C board conforms to PCI LOCAL BUS specification Rev 2 2 2 6 2 Electrical Characteristics 5 and 12V All driving and loading rules are respected 2 6 3 Capabilities The Western Avionics IIB 1553 PCI 2C board is used as a 2Mbyte field R W Static RAM 2Mbyte Read only 32 bit counter one 32 bit access Write only 16 bit register one 16 bit access 27 1553 INTERFACE 27 1 Introduction 1553B interface matches the MIL STD 1553B Standard 2 7 2 Electrical Characteristics The 1553B interface provides one dual redundant bus for each channel Primary bus e Secondary bus The 1553B interface can be programmed to be e Transformer coupled Direct coupled UM 10986 Rev B 16 3 OPERATION 3 1 INTRODUCTION The Western Avionics IIB 1553 PCI 2C Intelligent Interface Board provides two independent 1553 channels each of which provides Bus Controller BC Multi Remote Terminal MRT func
66. s Address Pointer 2 Time Stamp HI 3 Time Stamp LO 4 Data 5 Errors N 4 Data N 3 Errors N 2 RT Response Time LSB 0 5 uS N 1 RT Response Time 2 LSB 0 5 uS N Next Address Pointer 6 4 1 Previous Address Pointer The first word of each message will define the page address of the previous message The first message stored will set this pointer to 0000H 6 4 Time Stamp HI LO These two locations are a 32 bit word defining the value of the 32 bit 0 5 5 clock when the message started 6 4 5 Data These words describe the previous DATA word TYPE BUS ID and associated errors as follows D15 D14 D13 D12 D11 DIO 0081007 DOS D04 D02 DOO ED 0 0 Mn Lg Sh TI TO WC BO NR TA 0 ED 1 Indicates last 1553B word in message Py 1 1553B data word had Parity error Mn 1553B data word had a Manchester error Lg 1 1553B data word had too many bits Long Sh 1553B data word had too few bits Short UM 10986 Rev B 65 T1 TO describe the 1553B word type as follows 0 WORD 0 0 Command Word 0 1 Status Word 1 0 Data Word 1 1 RT RT Command Word 1 Indicates 1553B message had a word count error Only set for last word Bl BO Describe the bus the 1553B word was captured on as follows B1 BUS ID
67. this location will replace the original DDB address in the look up table This feature defines a different DDB for the next occurrence of the same message 4 3 2 5 Address of Modify Word Value to Write 0EH 10H After the message is complete and bit 8 of the option mask is set the Value to Write is written in the address defined by the contents of OEH Action is limited to the first 64Kbytes of the memory UM 10986 Rev B 40 4 3 2 6 Extended Sub Address To enable the extended sub address feature see the MDB type word When enabled the value of the DDB address in the look up table is in fact a pointer for a further look up table called the extended look up table The on board processor uses the 1553B byte of the first data word received multiplied by four to calculate an offset in the extended look up table to find the true DDB address word Therefore the DDB and data buffer used is defined by the value of the first 1553B RX data word offset gt Reserved MRT 02H DDB address 4 3 3 Data Buffers Data buffers are pointed to by the buffer address word contained in the data descriptor blocks The address of the toggled buffer is calculated by adding the global toggle offset to the data buffer address value in the DDB The first two words of a data buffer are updated with the value of the local clock at the beginning of the message 1553B data buffers can be stored as follows e The standard way data words behind the
68. tion on the TRIG IN input before storing messages and searching for the software trigger condition T 1 The Monitor will generate a gt 1 5yS pulse on the TRIG OUT when the software trigger condition has been detected C 1 Monitor will generate a gt 1 5uS pulse on the TRIG OUT when the post trigger message count has been reached 6 3 DETAILED TRIGGER DESCRIPTION The Bus Monitor has four triggers that can be set up to trigger on a wide variety of complex conditions Each trigger can be allocated one of four different data and error conditions If a trigger passes this condition it then moves on to trigger defined by the Pass register If a trigger fails this condition it then moves on to the trigger defined by the Fail Register Value 1 Value 2 Value 3 Value 4 Value 5 Each trigger is allocated a trigger type value from one to six and these are as follows Single Trigger Mode The Single Trigger Mode will search for the trigger data defined by the Trigger Data Pointer Register If this condition is TRUE for the incoming 1553B word the Single Trigger will branch to the trigger defined in the Pass Register If it fails it will branch to the trigger defined by the Fail Trigger Register Window Trigger The Window Trigger Mode will search for the trigger data defined by the Trigger Data Pointer Register within the first 1553B message it encounters If this condition is TRUE for a word within the incoming message
69. tions which may be run either independently or simultaneously An independent Chronological Bus Monitor is also provided In order to run any of these functions information must be loaded into specific fixed register locations Base Registers Some of these registers contain pointers to other areas of memory registers The selection of these pointers is left up to the discretion of the user Therefore memory blocks can be positioned in the on board memory to suit user requirements This set up means that fixed position registers are minimal 3 2 CONVENTIONS 1 BASE PCI Base Address of this board 2 The memory range BASE 10000H to End of Memory is reserved for the 1553B data blocks other data must reside in the first 64Kbytes After a Power On On board processor doing its power on initialisation Then executing Self Test Then waiting for a user command DSI default insertion program is disabled 3 3 ORGANISATION DIAGRAM The organisation diagram figure 3 1 shows how the functional areas of the Western Avionics IIB 1553 PCI 2C board can be controlled 34 BASE REGISTERS The only fixed position registers are the Base Registers Base Registers are the starting points for a description of operation of any of the three modes of operation BC and They are located starting at the board Base Address UM 10986 Rev B 17
70. uffers Simulation and Monitoring essere ener 37 Multiple Remote Terminal Organisation Diagram nemen 45 List of Tables Base Register Names and 19 Command Register CR E 21 Status Register era E ila A E IEEE HIER 22 Message Descriptor Block aset be rerit HC TANI 32 Data Descriptor BIOCK qu EE 38 Data Bufters i TE EE ET EEEE E EEEE E A REE 42 Base Registers och e bei etes Ihe 51 Command uri 52 Niue curl m 53 Stack Data Format ET P 65 UM 10986 Rev B xS 1 GENERAL INFORMATION 1 1 INTRODUCTION The Western Avionics IIB 1553 PCI 2C Intelligent Interface Board is a standard PCI card designed to meet the requirements of MIL STD 1553B and STANAG 3838 The Western Avionics IIB 1553 PCI 2C provides two independent 1553 channels both dual redundant to give a powerful and intelligent interface between a PCI based host equipment and the 1553B data bus Each channels Bus Controller and Multi Remote Terminal functions can operate both independently or simultaneously An additional independent Chronological Bus Monitor function is provided Western Avionics IIB 1553 PCI 2C provides complete and comprehensive test and simulation functions for all applications in MIL STD 1553B systems 12
71. ware support packages that are available for this unit together with information of obtaining up grades by web access UM 10986 Rev B 6 13 CAPABILITIES The Western Avionics IIB 1553 PCI 2C provides the following capabilities and functions for each independent channel 1 3 1 General Memory mapped real time universal PCI interface 2MByte of RAM INTA interrupt 1553B data protocol managed by a micro controller providing flexibility and extensibility Comprehensive Error Injection External Triggers Internal Self tests Standard single PCI card format 13 2 Bus Controller BC Features With MRT Simulation and Data Monitoring Bus Control Autonomous frame control using comprehensive set of instructions and message descriptor blocks Acyclic message insertion Error injection Frame frequency selection Inter message gap selection Response time out selection Bus events detection mask storage and reporting bus errors status word bits Simultaneous MRT Simulation up to 31 Data Words Transfers UM 10986 Rev B Data buffer simulation for BC and the simulated RT s Sub address based data buffer access with data descriptor blocks defining each bus message Multi buffering linked buffers or frequency toggled buffers Interrupt queues Data status report Data buffer time tagging 32 bits time tag Simultaneous monitoring of all data buffers 1 3 3 Multiple Remote Te
72. y the Selective Capture Count Register have not been stored the next trigger is defined by the contents of the Fail Pointer Register UM 10986 Rev B 55 When the programmed number of messages have been stored the next trigger is defined by the Pass register Therefore the two selective capture triggers allow the storage of a specific message or messages Value 6 Post Trigger Count Mode This mode is used as a terminator to the trigger sequence This mode simply stores the number of messages defined by the Post Trigger Count Register on the stack and then stops activity If the PTC is set to H8000 storage will continue until the board is commanded to halt NOTES This trigger mode always in the Trigger Stop Register and never in other register This is trigger 5 and must always pointed at as last part of trigger sequence Trigger 1 Trigger 1 type Register Base Address 0EH This register will define the trigger type allocated to trigger 1 This value will be in the range 1 to 6 Trigger 1 Data Pointer Base Address 10H This register will define the trigger data allocated to trigger 1 This value will be the range to 4 Trigger 1 Pass Pointer Base Address 12H This register will define the new trigger to be activated if this trigger condition passes This value will be the range to 5 Trigger 1 Fail Pointer Base Address 14H This register will define the new trigger to

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