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MPC875/MPC870 Hardware Specifications

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1. All Num Characteristic Frequencies Unit Min Max 170 Slave cycle time 2 171 1Slave enable lead time 15 ns 172 Slave enable lag time 15 ns 173 Slave clock SPICLK high or low time 1 teyc 174 Slave sequential transfer delay does not require deselect 1 teyc 175 Slave data setup time inputs 20 ns 176 Slave data hold time inputs 20 ns 177 1Slave access time 50 ns SPISEL Input SPICLK 1 0 Input SPICLK Cl 1 Input SS lt 177 181 lt gt SPIMISO Output SPIMOSI Input Figure 61 SPI Slave CP 0 Timing Diagram MPC875 MPC870 Hardware Specifications Rev 3 0 64 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics SPISEL Input SPICLK 1 0 Input SPICLK Cl 1 Input SPIMISO Output SPIMOSI Input Figure 62 SPI Slave CP 1 Timing Diagram 13 111 C AC Electrical Specifications Table 28 provides the PC SCL lt 100 KHz timings Table 28 I C Timing SCL 100 KHz All Num Characteristic Frequencies Unit Min Max 200 5 clock frequency slave 0 100 1 KHz 200 SCL clock frequency master 1 5 100 KHz 202 1 Bus free time between transmissions 4 7 HS 203 Low period of SCL 4 7
2. Name Pin Number Type P G6 nput 3 3 V only P A1 F5 nput 3 3 V only P A2 D3 nput 3 3 V only 101516 A IP_A3 E4 Input 3 3 V only IP_A4 D2 Input 3 3 V only IP_A5 E3 nput 3 3 V only 4 nput 3 3 V only P A7 C2 Input 3 3 V only ALE_B C8 Bidirectional DSCK Three state 3 3 V only IP_B 0 1 B8 D9 Bidirectional 3 3 V only IWP 0 1 VFLS 0 1 OPO B6 Bidirectional 3 3 V only OP1 C6 Output OP2 B5 Bidirectional 3 3 V only MODCK1 STS OP3 B2 Bidirectional 3 3 V only 2 0500 BADDR 28 29 E8 C5 Output BADDR30 D8 Output REG AS C7 Input 3 3 V only PA15 P14 Bidirectional USBRXD PA14 U16 Bidirectional USBOE Optional open drain PA11 R9 Bidirectional RXD4 Optional open drain MII1 TXDO 5 V tolerant RMII1 TXDO PA10 R12 Bidirectional MII1 TXERR Optional open drain TIN4 5 V tolerant CLK7 MPC875 MPC870 Hardware Specifications Rev 3 0 75 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information Table 36 Pin Assignments JEDEC Standard continued Name Pin Number Type PA7 R11 Bidirectional CLK1 BRGO1 TIN1 PA6 P11 Bidirectional CLK2 TOUT1 PA4 P7 Bidirectional CTS4 MII1 TXD1 RMII TXD1 PA3 R5 Bidirectional MIl1 RXER 5 V tolerant RMII1 RXER BRGOS3 PA2 N6 Bidirectional
3. o o lt lt 0 J o 241 o X o o x o U gt w 2 m ay o u gt N O O O O O O N 8 8 m gt m x lt vo o n lt ra lt ini o 00 o AO mi 00 D C Ul 00 D l 4 o N S gt hod O O O O O O O O O 4 o Q x o zi o gt O ORI 2 O O O O Q Q O O O O N S X ny amp lt imi lt lt gt ie 8 gt 3 gt 4 gt x o z o ORD e D18 D19 D20 D21 gt N gt R gt R o O O O O O O O O m a 2 x lt ini o z lt S m m N N x x o 19 OO O MS O O 2020 9991 10 S Q g S ROSE 2 YY 19 99 ORIN S oo 000 4557776677 ee oe 1 8 Or O30 O Or 56 Oh 10 0 0 O40 4 755055 2 m N S m mi Ol 2 o 9 vu 0 S D a 4 D o 4 z s Figure 68 Pinout of the PBGA Package JEDEC Standard Table 36 contains a list of the MPC875 870 input and output signals and shows multiplexing and pin assignments Table 36 Pin Assignments JEDEC Standard Nam
4. 5 V tolerant RMII1 CRS DV TXD4 PA1 T4 Bidirectional MIl1 RXDO 5 V tolerant RMII1 RXDO BRGO4 PAO P6 Bidirectional MIl1 RXD1 5 V tolerant RMII1 RXD1 TOUT4 PB31 T5 Bidirectional SPISEL Optional open drain MIl1 TXCLK 5 V tolerant RMII1 REFCLK PB30 T17 Bidirectional SPICLK Optional open drain 5 V tolerant PB29 R17 Bidirectional SPIMOSI Optional open drain 5 V tolerant PB28 R14 Bidirectional SPIMISO Optional open drain BRGO4 5 V tolerant PB27 N13 Bidirectional I2CSDA Optional open drain BRGO1 PB26 N12 Bidirectional I2CSCL Optional open drain BRGO2 MPC875 MPC870 Hardware Specifications Rev 3 0 76 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Table 36 Pin Assignments JEDEC Standard continued Name Pin Number Type PB25 U13 Bidirectional SMTXD1 Optional open drain 5 V tolerant PB24 T12 Bidirectional SMRXD1 Optional open drain 5 V tolerant PB23 U12 Bidirectional SDACK1 Optional open drain SMSYN1 PB19 T11 Bidirectional MIl1 RXD3 Optional open drain RTS4 PC15 R15 Bidirectional DREQO 5 V tolerant L1ST1 PC13 U9 Bidirectional MIl1 TXD3 5 V tolerant SDACK1 PC12 T15 Bidirectional MIl1 TXD2 5 V tolerant TOUT1 11 12 Bidirectional USBRXP PC10 U11 Bidirectional USBRXN TGATE1 PC7 T10 Bidirectional CT
5. m Figure 27 PCMCIA Access Cycles Timing External Bus Write Figure 28 provides the PCMCIA WAIT signals detection timing CLKOUT Figure 28 PCMCIA WAIT Signals Detection Timing MPC875 MPC870 Hardware Specifications Rev 3 0 39 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 13 shows the PCMCIA port timing for the MPC875 870 Table 13 PCMCIA Port Timing 33 MHz 40 MHz 66 MHz 80 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max P57 CLKOUT to OPx valid 19 00 19 00 119 001 19 00 ns MAX 0 00 x B1 19 00 P58 HRESET negated to OPx 25 70 121 701 114 401 112 401 ns drive MIN 0 75 x B1 3 00 P59 IP_Xx valid to CLKOUT rising edge 5 00 500 5 00 15001 ns MIN 0 00 x B1 5 00 P60 CLKOUT rising edge to IP_Xx invalid 1 00 1 00 11001 1100 ns MIN 0 00 x B1 1 00 1 OP2 and OP3 only Figure 29 provides the PCMCIA output port timing for the MPC875 870 CLKOUT Output Signals HRESET 5 OP2 OP3 Figure 29 PCMCIA Output Port Timing Figure 30 provides the PCMCIA input port timing for the MPC875 870 CLKOUT Input Signals Figure 30 PCMCIA Input Port Timing MPC875 MPC870 Hardware Specifications Rev 3 0 40 PRELIMINARY SUBJECT TO CHANGE WITHOU
6. 63 TIN TGATE high time clk 64 TIN TGATE cycle time clk 65 CLKO low to TOUT valid w Pp 25 ns CLKO TIN TGATE Input s TOUT Output Figure 46 CPM General Purpose Timers Timing Diagram 64 13 5 Serial Interface AC Electrical Specifications Table 21 provides the serial interface SI timings as shown in Figure 47 to Figure 51 Table 21 SI Timing All Frequencies Num Characteristic Unit Min Max 70 L1RCLKB L1TCLKB frequency DSC 0 2 SYNCCLK MHz 2 5 71 L1RCLKB L1TCLKB width low DSC 0 2 P 10 ns 71a L1RCLKB L1TCLKB width high DSC 0 8 P 10 ns 72 LITXDB L1ST1 and L1ST2 L1RQ L1CLKO rise fall time 15 00 ns 73 LIRSYNCB L1TSYNCB valid to L1CLKB edge SYNC setup time 20 00 ns MPC875 MPC870 Hardware Specifications Rev 3 0 50 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics Table 21 SI Timing continued All Frequencies Num Characteristic Unit Min Max 74 L1CLKB edge to L1RSYNCB L1TSYNCE invalid SYNC hold time 35 00 ns 75 L1RSYNCB L1TSYNCB rise fall time 15 00 ns 76 L1RXDB valid to L1CLKB edge L1RXDB setup time 17 00 ns 77 1L1CLKB edge to L1RXDB invalid L1RXDB hold time 13 00 ns 78 L1CLKB edge to
7. MPC875 MPC870 Hardware Specifications Rev 3 0 52 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics L1RCLKB FE 1 CE 1 Input L1RCLKB FE 0 CE 0 Input L1RSYNCB Input L1RXDB Input L1ST 2 1 Output L1CLKOB Output Figure 48 SI Receive Timing with Double Speed Clocking DSC 1 MPC875 MPC870 Hardware Specifications Rev 3 0 53 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics L1TCLKB FE 0 CE 0 Input L1TCLKB FE 1 CE 1 Input LITSYNCB Input LTTXDB Output L1ST 2 1 Output y 2 Figure 49 SI Transmit Timing Diagram DSC 0 MPC875 MPC870 Hardware Specifications Rev 3 0 54 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics L1RCLKB FE 0 GEO 7 72 gt 83a sz 0 L1RCLKB Input L1RSYNCB Input L1TXDB Output L1ST 2 1 Output L1CLKOB Output Figure 50 SI Transmit Timing with Double Speed Clocking DSC 1 MPC875 MPC870 Hardware Specifications Rev 3 0 55 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics LL gt 8 a Ndu 8011 n
8. Bus Signal Timing Figure 19 provides the timing for the asynchronous asserted UPVVATT signal controlled by the UPM CLKOUT UPWAIT BS_A 0 3 T T T 67 GPL 10 5 GPL 10 5 X X X Figure 19 Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing Figure 20 provides the timing for the asynchronous negated UPVVATT signal controlled by the UPM CLKOUT UPWAIT 10 5 GPL 10 5 oo Figure 20 Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing MPC875 MPC870 Hardware Specifications Rev 3 0 34 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 21 provides the timing for the synchronous external master access controlled by the GPCM Al0 311 TSIZ f R VV BURST CSx Figure 21 Synchronous External Master Access Timing GPCM Handled ACS 00 Figure 22 provides the timing for the asynchronous external master memory access controlled by the GPCM CLKOUT ee eee eee 5 5 O AS Al0 31 TSIZI0 11 R W CSx Figure 22 Asynchronous External Master Memory Access Timing GPCM Controlled ACS 00 Figure 23 provides the timing for the asynchronous external master control signals negation AS CSx WE 0 3 OE GPLx BS 0 3 Figure 23 Asynchronous External Master Control Signals Negation Timing MPC875 MPC870 Hardware Specification
9. Figure 42 SDACK Timing Diagram Peripheral Write Externally Generated TA CLKO Output TS Output RAV Output TA 8 Output SDACK Figure 43 SDACK Timing Diagram Peripheral Write Internally Generated TA MPC875 MPC870 Hardware Specifications Rev 3 0 48 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics CLKO eu J N Vf V NL TS Output TA Output SDACK Figure 44 SDACK Timing Diagram Peripheral Read Internally Generated TA 13 3 Baud Rate Generator AC Electrical Specifications Table 19 provides the baud rate generator timings as shown in Figure 45 Table 19 Baud Rate Generator Timing All Num Characteristic Frequencies Unit Min Max 50 BRGO rise and fall time 10 ns 51 BRGO duty cycle 40 60 52 BRGO cycle 40 ns BRGOX Figure 45 Baud Rate Generator Timing Diagram MPC875 MPC870 Hardware Specifications Rev 3 0 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 49 Freescale Semiconductor CPM Electrical Characteristics 13 4 Timer AC Electrical Specifications Table 20 provides the general purpose timer timings as shown in Figure 46 Table 20 Timer Timing Num Characteristic All Frequencies Min Max Unit 61 TIN TGATE rise and fall time 10 ns 62 TIN TGATE low time 1 clk
10. P54 PCWE IOWR negated to D 0 31 5 60 4 30 1 80 1125 ns invalid MIN 0 25 x B1 2 00 WAITA and WAITB valid to 8 00 8 00 8 00 8 00 ns P55 CLKOUT rising edge MIN 0 00 x B1 8 00 CLKOUT rising edge to WAITA and 2 00 2 00 2 00 2 00 ns P56 WAITB invalid MIN 0 00 x B1 2 00 1 PSST 1 Otherwise add PSST times cycle time PSHT 0 Otherwise add PSHT times cycle time These synchronous timings define when the WAITA signals are detected in order to freeze or relieve the PCMCIA current cycle The WAITA assertion will be effective only if it is detected 2 cycles before the PSL timer expiration See Chapter 16 PCMCIA Interface in the MPC885 PowerQUICC Family User s Manual MPC875 MPC870 Hardware Specifications Rev 3 0 37 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 26 provides the PCMCIA access cycle timing for the external bus read CLKOUT a e n ce H Figure 26 PCMCIA Access Cycles Timing External Bus Read MPC875 MPC870 Hardware Specifications Rev 3 0 38 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 27 provides the PCMCIA access cycle timing for the external bus write CLKOUT QO 2 Q A a 7 o a 5
11. ski s s 15 Bus Signal Timing 15 IEEE 1149 1 Electrical Specifications 44 CPM Electrical Characteristics 46 USB Electrical Characteristics 67 FEC Electrical Characteristics 67 Mechanical Data and Ordering Information 71 Document Revision History 82 ey PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 2 freescale semiconductor Features Table 1 shows the functionality supported by the members of the MPC875 MPC870 Table 1 MPC875 870 Devices Cache Ethernet Securit Part scc smc usB En I Cache D Cache 1 10BaseTl 10 100 g MPC875 8 Kbyte 8 Kbyte 1 2 1 1 1 Yes MPC870 8 Kbyte 8 Kbyte 2 1 1 No 2 Features The MPC875 870 is comprised of three modules that each use the 32 bit internal bus a MPC8xx core a system integration unit SIU and a communications processor module CPM The following list summarizes the key MPC875 870 features e Embedded MPC8xx core up to 133 MHz e Maximum frequency operation of the external bus is 80 MHz in 1 1 mode The 133 MHz core frequency supports 2 1 mode only The 66 80 MHz core frequencies support both the 1 1 and 2 1 modes Single issue 32 bit core compatible with the PowerPC architecture definition with thirty two 32 bit general purpose registers GPRs The core performs branch p
12. 0 00 x B1 6 00 B19 CLKOUT rising edge to D 0 31 valid hold 1 00 1 00 12 01 12 01 ns time MIN 0 00 x B1 1 00 B20 1 D 0 31 valid to CLKOUT falling edge 4001 14001 1400 14001 ns setup time MIN 0 00 x B1 4 00 B21 CLKOUT falling edge to D 0 31 valid 2 00 12001 1200 12001 ns hold time 5 MIN 0 00 x B1 2 00 B22 CLKOUT rising edge to CS asserted 7 60 13 80 6 30 12 50 3 80 10 00 3 13 9 43 ns GPCM ACS 00 MAX 0 25 x B1 6 3 B22a CLKOUT falling edge to CS asserted 8 00 800 800 8 00 ns GPCM ACS 10 TRLX 0 MAX 0 00 x B1 8 00 B22b CLKOUT falling edge to CS asserted 7 60 13 80 6 30 12 50 3 80 10 00 3 13 9 43 ns GPCM ACS 11 TRLX 0 EBDF 0 MAX 0 25 x B1 6 3 B22c CLKOUT falling edge to CS asserted 10 90 18 00 10 90 16 00 5 20 12 30 4 69 10 93 ns GPCM ACS 11 TRLX 0 EBDF 1 MAX 0 375 x B1 6 6 B23 CLKOUT rising edge to CS negated 2 00 8 00 2 00 8 00 2 00 8 00 2 00 8 00 ns GPCM read access GPCM write access ACS 00 TRLX 0 amp CSNT MAX 0 00 x B1 8 00 B24 A 0 31 and BADDR 28 30 to CS 5 60 14301 1 80 113 ns asserted GPCM ACS 10 TRLX 0 MIN 0 25 x B1 2 00 24 A 0 31 and BADDR 28 30 to CS 13 201 110 501 5 60 14251 ns asserted GPCM ACS 11
13. 15 00 2 50 15 00 2 5 15 00 ns the memory controller or PCMCIA interface MIN 0 00 x B1 2 5 B14 1 CLKOUT to TEA assertion 2 50 9 00 2 50 9 00 2 50 9 00 2 50 9 00 ns MAX 0 00 x B1 9 00 B15 CLKOUT to TEA High Z 2 50 15 00 1 2 50 1 15 00 2 50 15 00 2 50 15 00 ns MIN 0 00 x B1 2 50 B16 TA BI valid to CLKOUT setup time 6 00 6 00 600 6 ns MIN 0 00 x B1 6 00 B16a KR RETRY CR valid to CLKOUT 4 50 450 450 450 ns setup time MIN 0 00 x B1 4 5 B16b BB BG BR valid to CLKOUT setup time 4 00 4 00 4 00 400 ns 2 4MIN 0 00 x B1 0 00 17 CLKOUT to TA TEA BI BB BG BR valid 1 00 1 00 200 200 ns hold time MIN 0 00 x B1 1 00 3 B17a CLKOUT to KR RETRY CR valid hold 2 00 200 200 200 ns time MIN 0 00 x B1 2 00 MPC875 MPC870 Hardware Specifications Rev 3 0 17 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 10 Bus Operation Timings continued 33 MHz 40 MHz 66 MHz 80 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B18 D 0 31 valid to CLKOUT rising edge 6 00 16 01 6 00 16 01 ns setup time MIN
14. MAX 0 25 x B1 6 80 B28c CLKOUT falling edge to 10 90 18 00 10 90 18 00 5 20 12 30 4 69 11 29 ns WE 0 3 BS_B 0 3 negated GPCM write access TRLX 0 CSNT 1 write access TRLX 0 CSNT 1 EBDF 1 MAX 0 375 x B1 6 6 B28d CLKOUT falling edge to CS negated 18 00 18 00 112301 11 30 ns GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 1 MAX 0 375 x B1 6 6 B29 WE 0 3 BS_B 0 3 negated to D 0 31 5 60 14301 1180 113 ns High Z GPCM write access CSNT 0 EBDF 0 MIN 0 25 x B1 2 00 B29a WE 0 3 BS_B 0 3 negated to D 0 31 13 20 10 50 15 60 4 25 ns High Z GPCM write access TRLX 0 CSNT 1 EBDF 0 MIN 0 50 x B1 2 00 B29b CS negated to D 0 31 High Z GPCM write 5 60 4301 11801 113 ns access ACS 00 TRLX 0 amp CSNT 0 MIN 0 25 X B1 2 00 B29c CS negated to D 0 31 High Z GPCM write 13 20 10 50 5 60 1425 ns access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 0 MIN 0 50 x B1 2 00 B29d WE 0 3 BS_B 0 3 negated to D 0 31 43 50 135 501 20 70 116 751 ns High Z GPCM write access TRLX 1 CSNT 1 EBDF 0 MIN 1 50 x B1 2 00 B29e CS negated to D 0 31 High Z GPCM write 43 501 135 501 20 70 16 75 ns access TRLX 1 CSNT 1 ACS 10
15. MBMR MBMR GPLB4DIS 0 Machine B mode register PAPAR PAPAR 5 9 0 Port A pin assignment register PAPARI12 131 PADIR PADIR 5 9 0 Port A data direction register PADIR 12 13 PBPAR PBPAR 14 181 0 Port B pin assignment register PBPAR 20 22 PBDIR PBDIR 14 8 0 Port B data direction register PBDIR 20 22 PCPAR PCPAR 4 5 0 Port C pin assignment register PCPAR 8 9 PCPAR 14 MPC875 MPC870 Hardware Specifications Rev 3 0 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Layout Practices Table 7 Mandatory Reset Configuration of MPC875 870 continued Value Register Configuration Field binary PCDIR PCDIR 4 51 0 Port C data direction register PCDIRI8 91 PCDIR 14 PDPAR PDPAR 3 7 0 Port D pin assignment register PDPAR 9 5 PDDIR PDDIRI3 71 0 Port D data direction register PDDIR 9 15 10 Layout Practices Each Vpp pin on the MPC875 870 should be provided with a low impedance path to the board s supply Each GND pin should likewise be provided with a low impedance path to ground The power supply pins drive distinct groups of logic on chip The Vpp power supply should be bypassed to ground using at least four 0 1 uF bypass capacitors located as close as possible to the four sides of the package Each board designed should be characterized and additional appropriate decoupling capacitors should be used if required The capacitor leads and associa
16. Processor lt Bus Interface Bus Interface gt Core 8 Kbyte Unit Unit Data Cache Load Store Data MMU Bus 32 Entry DTLB System Functions PCMCIA ATA Interface Slave Master IF Fast Ethernet Controller 4 Interrupt Timers Controllers 8 K byte Parallel I O Dual Port RAM 10 100 BaseT 4 Baud Rate Media Access 32 Bit RISC Controller V Control Generators and Program 7 lt Parallel Interface Port ROM Timers MIIL RMII USB SMC1 SPI c Serial Interface Figure 2 MPC870 Block Diagram 3 Maximum Tolerated Ratings This section provides the maximum tolerated voltage and temperature ranges for the MPC875 870 Table 2 displays the maximum tolerated ratings and Table 3 displays the operating temperatures MPC875 MPC870 Hardware Specifications Rev 3 0 Freescale Semiconductor PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 7 Maximum Tolerated Ratings Table 2 Maximum Tolerated Ratings Rating Symbol Value Unit Supply voltage 1 core 0 3 to 3 4 V voltage VppH I O 0 3 to 4 V voltage VDDSYN 0 3 to 3 4 V Difference lt 100 mV between VDDL and VDDSYN Input voltage Vin GND 0 3to V Storage temperature range Teig 55 to 150 C T The power supply of the device must start its ramp from 0 0 V Functional o
17. RxD3 Input RENA CD3 Input Figure 56 Ethernet Receive Timing Diagram MPC875 MPC870 Hardware Specifications Rev 3 0 60 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics TCLK3 TxD3 Output TENA RTS3 Input RENA CD3 Input NOTE 2 NOTES 1 Transmit clock invert TCI bit in GSMR is set 2 If RENA is negated before TENA or RENA is not asserted at all during transmit then the CSL bit is set in the buffer descriptor at the end of the frame transmission Figure 57 Ethernet Transmit Timing Diagram 13 8 SMC Transparent AC Electrical Specifications Table 25 provides the SMC transparent timings as shown in Figure 58 Table 25 SMC Transparent Timing All Num Characteristic Frequencies Unit Min Max 150 SMCLK clock period 1 100 ns 151 SMCLK width low 50 ns 151A SMCLK width high 50 ns 152 SMCLK rise fall time 15 ns 153 1SMTXD active delay from SMCLK falling edge 10 50 ns 154 SMRXD SMSYNC setup time 20 ns 155 1 RXD1 SMSYNC hold time 5 ns 1 SyneCLK must be at least twice as fast as SMCLK MPC875 MPC870 Hardware Specifications Rev 3 0 61 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics SMCLK SMTXD Output SMSYNC SMRXD Input NOTE 1 This delay is
18. Configuration data to HRESET 1 504 501 1425 001 1277301 1237501 ns R73 rising edge setup time MIN 15 00 x B1 50 00 Configuration data to RSTCONF 350 00 350 00 1350 001 350 00 ns R74 1 rising edge setup time MIN 0 00 x B1 350 00 Configuration data hold time after 0 00 0 00 0 00 0 00 ns R75 RSTCONF negation MIN 0 00 x B1 0 00 Configuration data hold time after 0 00 0 00 0 00 0 00 ns R76 HRESET negation MIN 0 00 x B1 0 00 HRESET and RSTCONF 25 00 25 00 25 00 25 00 ns R77 1 asserted to data out drive MAX 0 00 x B1 25 00 RSTCONF negated to data out 25 00 25 00 25 00 25 00 ns R78 high impedance MAX 0 00 x B1 25 00 CLKOUT of last rising edge 25 00 25 00 25 00 25 00 1 ns before chip three states R79 HRESET to data out high impedance MAX 0 00 x B1 25 00 Rgo DSDI DSCK setup 90 90 75 00 4550 3750 ns MIN 3 00 x B1 Rai DSDI DSCK hold time 0 00 ooo 0200 600 Ins MIN 0 00 x B1 0 00 SRESET negated to CLKOUT 242 40 1200 001 1121201 1100 001 ns R82 rising edge for DSD and DSCK sample MIN 8 00 x B1 MPC875 MPC870 Hardware Specifications Rev 3 0 42 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE F
19. nput 3 3 V only IRQ1 P5 nput 3 3 V only IRQ7 N5 Input 3 3 V only 510 5 14 11 14 15 13 16 Output CS6 F12 Output CE1 B CS7 D15 Output MPC875 MPC870 Hardware Specifications Rev 3 0 73 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering information Table 36 Pin Assignments JEDEC Standard continued Name Pin Number Type WEO E15 Output BS BO IORD WE1 D17 Output BS B1 IOWR WE2 D16 Output BS B2 PCOE VVE3 G13 Output BS B3 PCVVE BS Af0 3 F14 E16 E17 F15 Output GPL A0 C17 Output GPL_BO OE F13 Output GPL_A1 GPL_B1 GPL_A 2 3 E14 C16 Output GPL_B 2 3 CS 2 3 UPWAITA D11 Bidirectional 3 3 V only GPL_A4 UPWAITB E12 Bidirectional GPL_B4 GPL_A5 D12 Output PORESET D5 Input 3 3 V only RSTCONF C3 Input 3 3 V only HRESET E7 Open drain SRESET C4 Open drain XTAL D6 Analog output EXTAL D7 Analog input 3 3 V only CLKOUT G4 Output EXTCLK B4 Input 3 3 V only TEXP B3 Output ALE_A B7 Output CE1A C15 Output CE A D14 Output VVA T A D4 nput 3 3 V only MPC875 MPC870 Hardware Specifications Rev 3 0 74 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering information Table 36 Pin Assignments JEDEC Standard continued
20. or ACS 11 EBDF 0 MIN 1 50 x B1 2 00 MPC875 MPC870 Hardware Specifications Rev 3 0 19 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 10 Bus Operation Timings continued Num Characteristic 33 MHz 40 MHz 66 MHz 80 MHz Min 1 Max Min Max Min Max Min 1 Max Unit B29f WE 0 3 BS_B 0 3 negated to D 0 31 High Z GPCM write access TRLX 0 CSNT 1 1 MIN 0 375 x B1 6 30 5 00 3 00 0 00 0 00 ns B29g CS negated to D 0 31 High Z GPCM vrrite access TRLX 0 CSNT 1 ACS 10or ACS 11 EBDF 1 MIN 0 375 x B1 6 30 5 00 3 00 0 00 0 00 ns B29h 0 3 5 10 3 negated to D 0 31 High Z GPCM write access TRLX 1 CSNT 1 EBDF 1 MIN 0 375 x B1 3 30 38 40 31 10 17 50 13 85 ns B29i CS negated to D 0 31 0 3 High Z GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 1 MIN 0 375 x B1 3 30 38 40 31 10 17 50 13 85 ns B30 CS WE 0 3 BS_B 0 3 negated to A 0 31 BADDR 28 30 invalid GPCM write access MIN 0 25 x B1 2 00 5 60 4 30 1 80 1 13 nS B30a WE 0 3 BS_B 0 3 negated to A 0 31 BADDR 28 30 invalid GPCM write access TRLX 0 CSNT 1 CS
21. us 204 High period of SCL 4 0 HS 205 Start condition setup time 4 7 HS 206 1 Start condition hold time 4 0 us 207 Data hold time 0 HS 208 Data setup time 250 ns 209 1 SDL SCL rise time 1 HS MPC875 MPC870 Hardware Specifications Rev 3 0 65 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics Table 28 12 Timing SCL lt 100 KHz continued All Num Characteristic Frequencies Unit Min Max 210 SDL SCL fall time 300 ns 211 Stop condition setup time 4 7 HS 1 SCL frequency is given by SCL BRGCLK_frequency BRG register 3 x pre scalar x 2 The ratio SyncClk BRGCLK pre_scalar must be greater than or equal to 4 1 Table 29 provides the PC SCL gt 100 KHz timings Table 29 12 Timing SCL gt 100 KHz All Frequencies Num Characteristic Expression Unit Min Max 200 SCL clock frequency slave fSCL 0 BRGCLK 48 Hz 200 SCL clock frequency master 1 fSCL BRGCLK 16512 BRGCLK 48 Hz 202 1 Bus free time between transmissions 1 2 2 x 1501 5 203 1 Low period of SCL 1 2 2 x fSCL 5 204 High period of SCL 1 2 2 x 1501 5 205 1 Start condition setup time 1 2 2 x fSCL 5 206 Start condition hold time 1 2 2 x fSCL 5 207 1Data hold time 0 5 208 Data setup time 1 40 x fSCL 5 209 SD
22. 3 can be added to meet these requirements The MUR420 Schottky diodes control the maximum potential difference between the external bus and core power supplies on power up and the 1N5820 diodes regulate the maximum potential difference on power down MPC875 MPC870 Hardware Specifications Rev 3 0 Freescale Semiconductor PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 13 Mandatory Reset Configurations MUR420 VDDL gt 1N5820 Figure 3 Example Voltage Sequencing Circuit 9 Mandatory Reset Configurations The MPC875 870 requires a mandatory configuration during reset If hardware reset configuration word HRCW is enabled the HRCW DBGC value needs to be set to binary X1 in the HRCW and the SIUMCR DBGC should be programmed with the same value in the boot code after reset This can be done by asserting the RSTCONF during HRESET assertion If HRCW is disabled the SIUMCR DBGC should be programmed with binary X1 in the boot code after reset by negating the RSTCONF during the HRESET assertion The MBMR GPLB4DIS PAPAR PADIR PBPAR PBDIR PCPAR and PCDIR need to be configured with the mandatory values in Table 7 in the boot code after the reset is negated Table 7 Mandatory Reset Configuration of MPC875 870 Register Configuration Field ce HRCW HRCW DBGC X1 Hardvvare reset configuration vvord SIUMCR SIUMCR DBGC X1 SIU module configuration register
23. Hardware Specifications Rev 3 0 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 69 Freescale Semiconductor FEC Electrical Characteristics 15 4 MII Serial Management Channel Timing MDIO Mil MDC Table 34 provides information on the MII serial management channel signal timing The FEC functions correctly with a maximum MDC frequency in excess of 2 5 MHz The exact upper bound is under investigation Table 34 MII Serial Channel Timing 22 falling edge to MII_MDIO output invalid minimum propagation delay Mit falling edge to MII_MDIO output valid max prop delay Bet a ae ie NO es sivyoc ns e MII_MDIO input to MDC rising edge hold za e 4 Figure 67 shows the MII serial management channel timing diagram M14 15 MII_MDC output 10 MD O output M11 MII_MDIO input bq 5 M12 M13 Figure 67 MII Serial Management Channel Timing Diagram MPC875 MPC870 Hardware Specifications Rev 3 0 70 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering information 16 Mechanical Data and Ordering Information Table 35 identifies the packages and operating frequencies available for the MPC875 870 Table 35 Available MPC875 870 Packages Frequencies Package Type Temperature Tj Frequency MHz Order Number Plastic ball grid array 0 C to 95 C 66 KMPC875ZT
24. L1ST1 and L1ST2 valid 10 00 45 00 ns 78A LT1SYNCB valid to L1ST1 and L1ST2 valid 10 00 45 00 ns 79 L1CLKB edge to L1ST1 and L1ST2 invalid 10 00 45 00 ns 80 L1CLKB edge to L1TXDB valid 10 00 55 00 ns 80A L1TSYNCB valid to L1TXDB valid 10 00 55 00 ns 81 L1CLKB edge to L1TXDB high impedance 0 00 42 00 ns 82 L1RCLKB L1TCLKB frequency DSC 1 m 16 00 or MHz SYNCCLK 2 83 L1RCLKB L1TCLKB width low DSC 1 P 10 ns 83a LTRCLKB L1TCLKB width high DSC 1 5 P 10 ns 84 L1CLKB edge to L1CLKOB valid DSC 1 m 30 00 ns 85 L1RQB valid before falling edge of L TSYNCB 1 00 LITCLK 86 L1GRB setup time 42 00 ns 87 L1GRB hold time 42 00 ns 88 L1CLKB edge to L1SYNCB valid FSD 00 CNT 0000 BYT m 0 00 ns DSC 0 The ratio SyncCLK L1RCLKB must be greater than 2 5 1 These specs are valid for IDL mode only 3 Where P 1 CLKOUT Thus for a 25 MHz CLKOT rate P 40 ns 4 These strobes and TxD on the first bit of the frame become valid after the L1CLKB edge or L1SYNCB whichever comes later MPC875 MPC870 Hardware Specifications Rev 3 0 51 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics L1RCLKB FE 0 CE 0 Input L1RCLKB FE 1 CE 1 Input L1RSYNCB Input L1RXDB Input L1ST 2 1 Output Figure 47 SI Receive Timing Diagram with Normal Clocking DSC 0
25. NOTICE Freescale Semiconductor Bus Signal Timing Table 12 shows the PCMCIA timing for the MPC875 870 Table 12 PCMCIA Timing 33 MHz 40 MHz 66 MHz 80 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max A 0 31 REG valid to PCMCIA 20 70 16 70 9 40 7 40 ns P44 strobe asserted MIN 0 75 x B1 2 00 A 0 31 REG valid to ALE 28 30 23 00 13 20 10 50 ns P45 negation 1 MIN 1 00 x B1 2 00 CLKOUT to REG valid 7 60 15 60 6 30 14 30 3 80 11 80 1 3 13 11 13 ns P46 MAX 0 25 x B1 8 00 paz CLKOUT to REG invalid 860 780 480 4425 ns MIN 0 25 x B1 1 00 pag CLKOUT to CET CE2 asserted 7 60 15 60 6 30 14 30 3 80 11 80 313 1113 ns MAX 0 25 x B1 8 00 pag CLKOUT to CET CE2 negated 7 60 15 60 6 30 14 30 3 80 11 80 3 13 1113 ns MAX 0 25 x B1 8 00 CLKOUT to PCOE IORD PCWE 11 00 111001 111001 11 00 1 ns P50 1 IOVVR assert time MAX 0 00 x B1 11 00 CLKOUT to PCOE IORD PCWE 2 00 11 00 2 00 11 00 2 00 11 00 2 00 11 00 1 ns P51 11OVVR negate time MAX 0 00 x B1 11 00 CLKOUT to ALE assert time MAX 7 60 13 80 6 30 12 50 3 80 10 00 3 13 9 40 ns 22 0 25 x B1 6 30 P53 CLKOUT to ALE negate time MAX 15 60 114301 11 80 11 13 ns 0 25 x B1 8 00
26. SMTXD1 Optional open drain MIl2 TXD3 MPC875 MPC870 Hardware Specifications Rev 3 0 78 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information Table 36 Pin Assignments JEDEC Standard continued Name Pin Number Type PE17 T8 Bidirectional TIN3 Optional open drain CLK5 BRGO3 SMSYN1 MIl2 TXD2 PE16 U6 Bidirectional L1RCLKB Optional open drain CLK6 MIl2 TXCLK RMII2 REFCLK PE15 T7 Bidirectional TGATE1 MIl2 TXD1 RMII2 TXD1 PE14 P8 Bidirectional MIl2 TXDO RMII2 TXDO TMS T14 nput 5 V tolerant TDI T13 Input DSDI 5 V tolerant TCK R13 Input DSCK 5 V tolerant TRST U14 Input 5 V tolerant TDO P13 Output DSDO 5 V tolerant MIl1_CRS U10 Input MIl_MDIO M13 Bidirectional 5 V tolerant 1 TX EN U5 Output 11 5 V tolerant MII1 COL R10 nput Vsssyn E5 PLL analog GND Vsssynt F6 PLL analog GND VDDSYN E6 PLL analog Vpp GND H8 H9 H10 H11 J8 J9 J10 J11 K8 K9 K10 K11 L8 L9 L10 Power L11 U15 VDDL F7 F8 F9 F10 F11 H6 H13 J6 J13 K6 K13 L6 L13 N7 N8 Power N9 N10 N11 MPC875 MPC870 Hardware Specifications Rev 3 0 79 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information Table 36 Pin Assignments JEDEC Standard continued Name
27. bit stuffing Supports both 12 and 1 5 Mbps data rates automatic generation of preamble token and data rate configuration Note that low speed operation requires an external hub Flexible data buffers with multiple buffers per frame Supports local loopback mode for diagnostics 12 Mbps only Serial peripheral interface SPD Supports master and slave modes Supports multiple master operation on the same bus e Inter integrated circuit port Supports master and slave modes Supports a multiple master environment e The MPC875 has a time slot assigner TSA that supports one TDM bus TDMb Allows SCC and SMC to run in multiplexed and or non multiplexed operation Supports T1 CEPT PCM highway ISDN basic rate ISDN primary rate user defined 1 or 8 bit resolution Allows independent transmit and receive routing frame synchronization and clocking Allows dynamic changes Can be internally connected to two serial channels one SCC and one SMC e PCMCIA interface Master socket interface release 2 1 compliant Supports one independent PCMCIA socket on the MPC875 MPC870 8 memory or I O windows supported e Debug interface Eight comparators four operate on instruction address two operate on data address and two operate on data Supports conditions z lt gt Each watchpoint can generate a break point internally e Normal high and normal low power modes to con
28. fall time ns 103 1TXD3 active delay from falling edge 0 00 30 00 ns 104 1RTS3 active inactive delay from TCLK3 falling edge 0 00 30 00 ns 105 CTS3 setup time to TCLK3 rising edge 40 00 ns 106 1 RXDS3 setup time to RCLKS rising edge 40 00 ns 107 hold time from RCLKS rising edge 0 00 ns 108 setup time to RCLK3 rising edge 40 00 ns 1 The ratios SyncCLK RCLK3 and SyneCLK TCLK3 must be greater or equal to 3 1 2 Also applies to CD and CTS hold time when they are used as external sync signals MPC875 MPC870 Hardware Specifications Rev 3 0 57 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics Figure 52 through Figure 54 shovv the NMSI timings RCLK3 RxD3 Input CD3 Input CD3 SYNC Input Figure 52 SCC NMSI Receive Timing Diagram TCLK3 TxD3 Output RTS3 Output CTS3 Input CTS3 SYNC Input Figure 53 SCC NMSI Transmit Timing Diagram MPC875 MPC870 Hardware Specifications Rev 3 0 58 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics TCLK3 TxD3 Output 108 lt gt E Bi CTS3 Echo Input Figure 54 HDLC Bus Timing Diagram 13 7 Ethernet Electrical Specifications Table 24 provides the Ethernet
29. negated to A 0 31 invalid GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 0 MIN 0 50 x B1 2 00 13 20 10 50 5 60 4251 ns B30b WE 0 3 BS_B 0 3 negated to A 0 31 Invalid GPCM BADDR 28 30 invalid GPCM write access TRLX 1 CSNT 1 CS negated to A 0 31 invalid GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 0 MIN 1 50 x B1 2 00 43 50 35 50 20 70 16 75 ns B30c 0 3 5 10 3 negated to A 0 31 BADDR 28 30 invalid GPCM write access TRLX 0 CSNT 1 CS negated to A 0 31 invalid GPCM write access TRLX 0 CSNT 1 ACS 10 ACS 11 EBDF 1 MIN 0 375 x B1 3 00 8 40 6 40 2 70 1 70 ns B30d WE 0 3 BS_B 0 3 negated to A 0 31 BADDR 28 30 invalid GPCM write access TRLX 1 CSNT 1 CS negated to A 0 31 invalid GPCM write access TRLX 1 CSNT 1 ACS 10 or 11 EBDF 1 38 67 31 38 17 83 14 19 ns MPC875 MPC870 Hardware Specifications Rev 3 0 20 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 10 Bus Operation Timings continued Num Characteristic 33 MHz 40 MHz 66 MHz 80 MHz Min Max Min Max Min Max Min Max Unit B31 CLKOUT falling edge to CS valid as requested by control b
30. 2 220 8 Power Supply and Power Sequencing This section provides design considerations for the MPC875 870 power supply The MPC875 870 has a core voltage Vppu and PLL voltage Vppsyn which both operate at a lower voltage than the I O voltage VppH The I O section of the MPC875 870 is supplied with 3 3 V across Vppu and Vss GND The signals PA 0 3 PA 8 11 PB15 PB 24 25 PB 28 31 PC 4 7 PC 12 13 PC15 PD 3 15 TDI TDO TCK TRST TMS MII_TXEN and MII_MDIO are 5 V tolerant No input can be more than 2 5 V greater than Vppu In addition 5 V tolerant pins cannot exceed 5 5 V and remaining input pins cannot exceed 3 465 V This restriction applies to power up down and normal operation One consequence of multiple power supplies is that when power is initially applied the voltage rails ramp up at different rates The rates depend on the nature of the power supply the type of load on each power supply and the manner in which different voltages are derived The following restrictions apply VDDL must not exceed Vppu during power up and power down e Vppr must not exceed 1 9 V and Vppu must not exceed 3 465 V These cautions are necessary for the long term reliability of the part If they are violated the electrostatic discharge ESD protection diodes are forward biased and excessive current can flow through these diodes If the system power supply design does not control the voltage sequencing the circuit shown in Figure
31. 4 16 7 256X o SIDE VIEW 1Z 0 56 A B c BOTTOM VIEW ZO 15S IA NOTES 1 ALL DIMENSIONS ARE IN MILLIMETERS 2 INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14 5M 1994 3 MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A 4 DATUM A THE SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS Note Solder sphere composition is 95 5 Sn 45 Ag 0 5 Cu for MPC875 870VRXXX Solder sphere composition is 62 Sn 36 Pb 2 Ag for MPC875 870ZTXXX Figure 69 Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package MPC875 MPC870 Hardware Specifications Rev 3 0 Freescale Semiconductor PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 81 Document Revision History 17 Document Revision History Table 37 lists significant changes betvveen revisions of this hardvvare specification Table 37 Document Revision History Revision Number Date Changes 0 2 2003 nitial release 0 1 3 2003 Took out the time slot assigner and changed the SCC for SCC3 to SCC4 0 2 5 2003 Changed the package drawing removed all references to Data Parity Changed the SPI Master Timing Specs 162 and 164 Added the RMII and USB timing Added the 80 MHz timing 0 3 5 2003 Made sure the pin types were correct Changed the Features list to agree with the MPC885 0 4 5 2003 Corrected the signals that had overlines on them Made corrections on two pins tha
32. 66 KMPC870ZT66 ZT suffix Leaded VR suffix Lead Free are available as needed MPC875ZT66 MPC870ZT66 80 KMPC875ZT80 KMPC870ZT80 8752 80 8702 80 133 8752 133 8702 133 8752 133 8702 133 Plastic ball grid array 40 C to 100 C 66 KMPC875CZT66 KMPC870CZT66 CZT suffix Leaded CVR suffix Lead Free are available as needed MPC875CZT66 MPC870CZT66 133 875 2 133 870 2 133 875 7 133 870 2 133 16 1 Pin Assignments Figure 68 shovvs the VEDEC pinout of the PBGA package as vievved from the top surface For additional information see the MPC885 PowerQUICC Family User 5 Manual NOTE The pin numbering starts with B2 in order to conform to the JEDEC standard for 23 mm body size using a 16 x 16 array MPC875 MPC870 Hardware Specifications Rev 3 0 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor 71 Mechanical Data and Ordering information NOTE This is the top vievv of the device o x m o o D ALEA IPBO BURST o a n 9 O m s g zi Q o 2 fa g m m J R F ol R Hi gt GPLAB3 GPLAO O O O O O O O m gt x m gt N gt D m o m A x 3 gt imi al o o m D gt o N m O O O o O O O 2 m gt a m gt
33. Freescale Semiconductor MPC875 MPC870 MPC875EC Rev 3 0 07 2004 Hardware Specifications This hardware specification contains detailed information on power considerations DC AC electrical characteristics and AC timing specifications for the MPC875 MPC870 The CPU on the MPC875 MPC870 is a 32 bit PowerPC core that incorporates memory management units MMUs and instruction and data caches and that implements the PowerPC instruction set This hardware specification covers the following topics 1 Overview The 875 870 is a versatile single chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems The MPC875 MPC870 provides enhanced ATM functionality over that of other ATM enabled members of the MPC860 family Freescale Semiconductor Inc 2004 All rights reserved SO 06 Ov Oi a Contents OVETV eVV z aa AR a 39035 ah magn Sb 1 Featiitee n s aa ang dra winareararaiae 2 Maximum Tolerated Ratings 7 Thermal Characteristics 9 Povver Dissipation 9 Characteristics R s l m 10 Thermal Calculation and Measurement 11 Power Supply and Power Sequencing 13 Mandatory Reset Configurations 14 Layout Practices
34. L SCL rise time 1 10 x fSCL 5 210 SDL SCL fall time 1 33 x fSCL 5 211 Stop condition setup time 1 2 2 2 x fSCL 5 1 SCL frequency is given by SCL frequeney BRG register 3 x pre scalar x 2 The ratio SyncClk Brg_Clk pre_scalar must be greater than or equal to 4 1 MPC875 MPC870 Hardware Specifications Rev 3 0 66 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor USB Electrical Characteristics Figure 63 shovvs the PC bus timing Figure 63 12 Bus Timing Diagram 14 USB Electrical Characteristics This section provides the AC timings for the USB interface 14 1 USB Interface AC Timing Specifications The USB Port uses the transmit clock on SCC1 Table 30 lists the USB interface timings Table 30 USB Interface AC Timing Specifications All Frequencies Name Characteristic Unit Min Max US1 USBCLK frequency of operation MHz Low speed 6 MHz Full speed 48 US4 USBCLK duty cycle measured at 1 5 V 45 55 1 USBCLK accuracy should be 500 ppm or better USBCLK may be stopped to conserve power 15 FEC Electrical Characteristics This section provides the AC electrical specifications for the fast Ethernet controller FEC Note that the timing specifications for the MII signals are independent of system clock frequency part speed designation Also MII signals use TTL signal level
35. N nput high voltage all inputs except EXTAL and EXTCLK 2 Vin 2 0 3 465 Input low voltage 3 Vib GND 0 8 EXTAL EXTCLK input high voltage 0 7 X VDDH VDDH Input leakage current Vin 5 5 V except TMS TRST DSCK and lin 100 HA DSDI pins for 5 V tolerant pins 1 Input leakage current Vin Vppu except TMS TRST DSCK and lin 10 HA 0501 Input leakage current Vin 0 V except TMS TRST and 0501 lin 10 HA pins Input capacitance 4 Cin 20 pF Output high voltage IOH 2 0 mA VppH 3 0 V VoH 2 4 V except XTAL and open drain pins Output low voltage VoL 0 5 V IOL 2 0 mA CLKOUT IOL 3 2 mA5 IOL 5 3 mA IOL 7 0 mA TXD1 PA14 TXD2 PA12 IOL 8 9 mA TS TA TEA BI BB HRESET SRESET 1 The difference between VppL and Vppsyn Cannot be more than 100 mV 2 The signals PA 0 15 PB 14 31 PC 4 15 PD 3 15 PE 14 31 TDI TDO TCK TRST TMS MIl1_TXEN MII_MDIO are 5 V tolerant The minimum voltage is still 2 0 V 3 ViL max for the I C interface is 0 8 V rather than the 1 5 V as specified in the I C standard MPC875 MPC870 Hardware Specifications Rev 3 0 10 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Thermal Calculation and Measurement Gi Input capacitance is periodically sampled 5 A 0 31 TSIZO REG TSIZ1 D 0 31 IRQ 2 4 IRQ6 RD VVR BURST IP_B 0 1 PA 0 4 PA 6 7 PA 10 11 PA15 PB19 PB 23 31 PC 6 7
36. PC 10 13 PC15 PD8 PE 14 31 MII1_CRS MII_MDIO MII1_TXEN MII1_COL 6 BDIP GPL_B 5 BR BG FRZ IRQ6 CS 0 7 WE 0 3 BS_A 0 3 GPL A0 GPL BO OE GPL_A1 GPL_B1 GPL_A 2 3 GPL_B 2 3 CS 2 3 UPWAITA GPL_A4 UPWAITB GPL_B4 GPL_A5 ALE A CE1_A CE2 A OP 0 3 BADDR 28 30 7 Thermal Calculation and Measurement For the following discussions Pp Vppu X Ippu Pro where Py is the power dissipation of the I O drivers NOTE The Vppsyy power dissipation is negligible 7 1 Estimation with Junction to Ambient Thermal Resistance An estimation of the chip junction temperature Ty in C can be obtained from the following equation Ty TA Roya X Pp where TA ambient temperature C Roya package junction to ambient thermal resistance C W Pp power dissipation in package The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance However the answer is only an estimate test cases have demonstrated that errors of a factor of two in the quantity T T are possible 7 2 Estimation with Junction to Case Thermal Resistance Historically thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance Rosa Reyc Roca where Resa junction to ambient thermal resistance C W Royc junction to case thermal resistance C W Re
37. PM for data beats where DLT3 1 in the UPM RAM words This is only the case where data is latched on the falling edge of CLKOUT CLKOUT 2007 4 7 7 D 0 31 Figure 10 Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 1 Figure 11 through Figure 14 provide the timing for the external bus read controlled by various GPCM factors CSx WE 0 3 D 0 31 Figure 11 External Bus Read Timing GPCM Controlled ACS 00 MPC875 MPC870 Hardware Specifications Rev 3 0 27 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing 010 311 Figure 12 External Bus Read Timing GPCM Controlled TRLX 0 5 10 gt a 82 X CSx D 0 31 Figure 13 External Bus Read Timing GPCM Controlled TRLX 0 ACS 11 MPC875 MPC870 Hardware Specifications Rev 3 0 28 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing CLKOUT CSx OE Bra gt 6220220 r 18 a gt gt 19 D 0 31 Figure 14 External Bus Read Timing GPCM Controlled TRLX 1 ACS 10 ACS 11 MPC875 MPC870 Hardware Specifications Rev 3 0 29 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 15 thr
38. Pin Number Type VbpH G7 G8 G9 G10 G11 G12 H7 H12 J7 J12 K7 K12 L7 L12 M7 Power M8 M9 M10 M11 M12 N C B17 T16 U2 U17 No connect MPC875 MPC870 Hardware Specifications Rev 3 0 80 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering Information 16 2 Mechanical Dimensions of the PBGA Package Figure 69 shovvs the mechanical dimensions of the PBGA package 25 SEATING 1 INDEX 19 3 C k 256x za10 2 A I 0 251 10 351 TH 4 R 19 7 H 19 3 125 D D mn Lo 7 D 4X CN 0 2 1 D TOP VIEW H 19 05 D 15X 1 27 H D TAn D D r 2 x eee ee o 94 Pe o oe I ie 2000 000099004 S u 4 82 L PEEP CCP Oooo ee oe 0 5 n 19 05 0 62 1555666063 039 d n 1 22 0 50 G 666646 6616565646665656 0 635 112 7 F 6666564 He 2 54 6160050506 22 D SESS OSS HO SSS OSD B BOC 00090000000 2345676 9N0 12 1
39. S4 5 V tolerant LITSYNCB USBTXP PC6 P10 Bidirectional CD4 5 V tolerant L1RSYNCB USBTXN PD8 T3 Bidirectional RXD4 5 V tolerant MII MDC 1 9 Bidirectional CLK8 Optional open drain LITCLKB MIl1 RXCLK PE30 R8 Bidirectional L1RXDB Optional open drain MIl1 RXD2 MPC875 MPC870 Hardware Specifications Rev 3 0 Mechanical Data and Ordering Information Freescale Semiconductor PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 77 Mechanical Data and Ordering information Table 36 Pin Assignments JEDEC Standard continued Name Pin Number Type PE29 U7 Bidirectional 2 5 Optional open drain PE28 R7 Bidirectional TOUT3 Optional open drain MII2 COL PE27 T6 Bidirectional L1RQB Optional open drain MII2 RXERR RMII2 RXERR PE26 T2 Bidirectional L1CLKOB Optional open drain MII2 RXDV RMII2 CRS_DV PE25 R4 Bidirectional RXD4 Optional open drain MII2 RXD3 L1ST2 PE24 U8 Bidirectional SMRXD1 Optional open drain BRGO1 MII2 RXD2 PE23 U4 Bidirectional TXD4 Optional open drain MII2 RXCLK L1ST1 PE22 P4 Bidirectional TOUT2 Optional open drain MII2 RXD1 RMII2 RXD1 SDACK1 PE21 T9 Bidirectional TOUT1 Optional open drain MII2 RXDO RMII2 RXDO PE20 U3 Bidirectional 2 Optional open drain PE19 R6 Bidirectional L1ITXDB Optional open drain MII2 TXEN RMII2 TXEN PE18 M5 Bidirectional
40. T NOTICE Freescale Semiconductor Bus Signal Timing Table 14 shows the debug port timing for the MPC875 870 Table 14 Debug Port Timing All Frequencies Num Characteristic Unit Min Max D61 DSCK cycle time 3 x TCLOCKOUT D62 DSCK clock pulse width 1 25 x TCLOCKOUT m D63 DSCK rise and fall times 0 00 3 00 ns D64 1 DSD input data setup time 8 00 ns D65 DSDI data hold time 5 00 ns D66 DSCK low to DSDO data valid 0 00 15 00 ns D67 DSCK low to DSDO invalid 0 00 2 00 ns Figure 31 provides the input timing for the debug port clock DSCK Figure 31 Debug Port Clock Input Timing Figure 32 provides the timing for the debug port DSCK DSDI DSDO Figure 32 Debug Port Timings MPC875 MPC870 Hardware Specifications Rev 3 0 41 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 15 shows the reset timing for the MPC875 870 Table 15 Reset Timing 33 MHz 40 MHz 66 MHz 80 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max CLKOUT to HRESET high 20 00 20 00 20 00 20 00 ns R69 impedance MAX 0 00 x B1 20 00 CLKOUT to SRESET high 20 00 m 20 00 20 00 20 00 1 ns R70 impedance MAX 0 00 x B1 20 00 RSTCONF pulse width 515 20 1425 001 257 60 1212 50 ns R71 MIN 17 00 x B1 R72 ri
41. T valid MIN 0 00 x B1 1 00 1 001 1 00 1 00 1 00 ns B39 AS valid to CLKOUT rising edge MIN 0 00 x B1 7 00 7 00 7 00 7 00 7 00 ns B40 A 0 31 TSIZ 0 1 RD VVR BURST valid to CLKOUT rising edge MIN 0 00 x B1 7 00 7 00 7 00 7 00 7 00 nS B41 TS valid to CLKOUT rising edge setup time MIN 0 00 x B1 7 00 7 00 7 00 7 00 7 00 ns MPC875 MPC870 Hardware Specifications Rev 3 0 22 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 10 Bus Operation Timings continued 33 MHz 40 MHz 66 MHz 80 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B42 CLKOUT rising edge to TS valid hold 2 00 12001 1200 12001 ns time MIN 0 00 x B1 2 00 B43 AS negation to memory controller signals TBD TBD TBD ns negation MAX TBD 1 For part speeds above 50 MHz use 9 80 ns for B11a 2 The timing required for BR input is relevant when the MPC875 870 is selected to work with the internal bus arbiter The timing for BG input is relevant when the MPC875 870 is selected to work with the external bus arbiter 3 For part speeds above 50 MHz use 2 ns for B17 4 The D 0 31 input timings B18 and B19
42. TRLX 0 MIN 0 50 x B1 2 00 B25 CLKOUT rising edge to OE 9 00 9 00 9 00 9 00 ns WE 0 3 BS_B 0 3 asserted MAX 0 00 x B1 9 00 B26 CLKOUT rising edge to OE negated 2 00 9 00 2 00 9 00 2 00 9 00 2 00 9 00 ns MAX 0 00 x B1 9 00 B27 A 0 31 and BADDR 28 30 to CS 35 90 1293301 16 90 113601 ns asserted GPCM ACS 10 TRLX 1 MIN 1 25 x B1 2 00 B27a A 0 31 and BADDR 28 30 to CS 43 501 135 501 120 701 16 75 ns asserted GPCM ACS 11 TRLX 1 MIN 1 50 x B1 2 00 MPC875 MPC870 Hardware Specifications Rev 3 0 18 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 10 Bus Operation Timings continued 33 MHz 40 MHz 66 MHz 80 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B28 1 CLKOUT rising edge to 9 00 9 00 19001 19001 ns WE 0 3 BS_B 0 3 negated GPCM write access CSNT MAX 0 00 x B1 9 00 B28a CLKOUT falling edge to 7 60 14 30 6 30 13 00 3 80 10 50 3 13 9 93 ns WE 0 3 BS_B 0 3 negated GPCM write access TRLX CSNT 1 EBDF 0 MAX 0 25 x B1 6 80 B28b CLKOUT falling edge to cs negated 114301 13 00 110 501 19 33 ns GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 0
43. XTCLK and CLKOUT have a continuously varying phase skew Bib CLKOUT frequency jitter peak to peak 1 1 1 1 ns Bic Frequency jitter on EXTCLK 10501 050 10501 0 50 96 Bid CLKOUT phase jitter peak to peak 4 4 4 4 ns for OSCLK x 15 MHz CLKOUT phase jitter peak to peak 5 5 5 5 ns for OSCLK lt 15 MHz B2 1CLKOUT pulse width low 12 1 18 2 10 0 15 0 6 1 9 1 5 0 7 5 ns MIN 0 4 x B1 MAX 0 6 x B1 B3 CLKOUT pulse width high 12 1 18 2 10 0 15 0 6 1 9 1 5 0 7 5 ns MIN 0 4 x B1 MAX 0 6 x B1 B4 CLKOUT rise time 4 00 1400 4 00 14001 ns B5 CLKOUT fall time 4 00 1400 4 00 14001 ns B7 CLKOUT to A 0 31 BADDR 28 30 7 60 630 3 80 313 ns RD WR BURST D 0 31 output hold MIN 0 25 x B1 B7a CLKOUT to TSIZ 0 1 REG RSV BDIP 7 60 6 30 13801 313 ns PTR output hold MIN 0 25 x B1 B7b CLKOUT to BR BG FRZ VFLS 0 1 7 60 630 13801 313 ns VF 0 2 IWP 0 2 LWP 0 1 STS output hold MIN 0 25 x B1 MPC875 MPC870 Hardware Specifications Rev 3 0 16 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 10 Bus Operation Timings continued 33 MHz 40 MHz 66 MHz 80 MHz Num Characteristi
44. able 4 shows the thermal characteristics for the MPC875 870 Table 4 MPC875 870 Thermal Resistance Data Rating Environment Symbol Value Unit Junction to ambient 1 Natural convection Single layer board 1s Roua 43 C W Four layer board 2s2p Royma 29 Airflow 200 ft min Single layer board 1s Regma 36 Four layer board 2s2p Roya 26 Junction to board 4 Ross 20 Junction to case 5 Resco 10 Junction to package top 9 Natural convection Wor 2 Airflow 200 ft min Wot 2 1 Junction temperature is a function of on chip power dissipation package thermal resistance mounting site board temperature ambient temperature airflow power dissipation of other components on the board and board thermal resistance 2 Per SEMI G38 87 and JEDEC JESD51 2 with the single layer board horizontal 3 Per JEDEC JESD51 6 with the board horizontal 4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51 8 Board temperature is measured on the top surface of the board near the package 5 Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method MIL SPEC 883 Method 1012 1 with the cold plate temperature used for the case temperature For exposed pad packages where the pad would be expected to be soldered junction to case thermal resistance is a simulated value from the junction to the exposed pad without contact
45. c Unit Min Max Min Max Min Max Min Max B8 CLKOUT to A 0 31 BADDR 28 30 1380 11250 110 001 9 43 ns RD WR BURST D 0 31 valid MAX 0 25 x B1 6 3 1 CLKOUT to TSIZ 0 1 REG RSV BDIP 1380 11250 110 001 9 43 ns PTR valid MAX 0 25 x B1 6 3 B8b CLKOUT to BR BG VFLS 0 1 VF 0 2 113 801 112 501 10 00 9 43 ns IWP 0 2 FRZ LWP 0 1 STS valid 2 MAX 0 25 x B1 6 3 B9 CLKOUT to A 0 31 BADDR 28 30 7 60 13 80 6 30 12 50 3 80 1 10 00 3 13 9 43 ns RD WR BURST D 0 31 TSIZ 0 1 REG RSV PTR High Z MAX 0 25 x B1 6 3 B11 CLKOUT to TS BB assertion 7 60 13 60 6 30 12 30 3 80 9 80 3 13 9 13 ns MAX 0 25 x B1 6 0 11 CLKOUT to TA B assertion when driven 2 50 9 30 2 50 9 30 2 50 9 80 2 5 93 ns by the memory controller or PCMCIA interface MAX 0 00 x B1 9 30 B12 CLKOUT to TS BB negation 7 60 12 30 6 30 11 00 3 80 8 50 3 13 7 92 ns MAX 0 25 x B1 4 8 B12a CLKOUT to TA B negation when driven 2 50 9 00 2 50 9 00 2 50 9 00 2 5 9 00 ns by the memory controller or PCMCIA interface MAX 0 00 x B1 9 00 B13 CLKOUT to TS BB High Z 7 60 21 60 6 30 20 30 3 80 14 00 3 13 12 93 ns MIN 0 25 x B1 B13a CLKOUT to TA BI High Z when driven by 2 50 1 15 00 2 50
46. ca case to ambient thermal resistance C W Rgjc is device related and cannot be influenced by the user The user adjusts the thermal environment to affect the case to ambient thermal resistance Ro a For instance the user can change the airflow around the device add a heat sink change the mounting arrangement on the printed circuit board or change the thermal dissipation on the printed circuit board surrounding the device This thermal model is most useful for ceramic packages with heat sinks where some 90 of the heat flows through the case and the heat sink to the ambient environment For most packages a better model is required MPC875 MPC870 Hardware Specifications Rev 3 0 Freescale Semiconductor PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 11 Thermal Calculation and Measurement 7 3 Estimation with Junction to Board Thermal Resistance A simple package thermal model that has demonstrated reasonable accuracy about 20 is a two resistor model consisting of a junction to board and a junction to case thermal resistance The junction to case thermal resistance covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the top of the package The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board It has been observed that the thermal performance of most plastic packages and especially PBGA packages is str
47. dino gould indjno 1 21917 Ndu gaxy I indjno fndur gONASHIT indul ay194 41 Figure 51 IDL Timing MPC875 MPC870 Hardware Specifications Rev 3 0 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor 56 CPM Electrical Characteristics 13 6 SCC in NMSI Mode Electrical Specifications Table 22 provides the NMSI external clock timing Table 22 NMSI External Clock Timing All Frequencies Num Characteristic Unit Min Max 100 RCLK3 and TCLK width high 1 1 SYNCCLK ns 101 RCLK3 and TCLK3 width low 1 SYNCCLK 5 ns 102 RCLK3 and TCLKS rise fall time 15 00 ns 103 1TXD3 active delay from TCLK3 falling edge 0 00 50 00 ns 104 RTS3 active inactive delay from TCLK3 falling edge 0 00 50 00 ns 105 CTS3 setup time to TCLK3 rising edge 5 00 ns 106 1 RXDS3 setup time to RCLK3 rising edge 5 00 ns 107 RXD3 hold time from RCLK3 rising edge 2 5 00 ns 108 CD3 setup time to RCLK3 rising edge 5 00 ns 1 The ratios SyncCLK RCLK3 and SyneCLK TCLK3 must be greater than or equal to 2 25 1 2 Also applies to CD and CTS hold time when they are used as external sync signals Table 23 provides the NMSI internal clock timing Table 23 NMSI Internal Clock Timing All Frequencies Num Characteristic Unit Min Max 100 RCLK3 and TCLK3 frequency 0 00 SYNCCLK 3 MHz 102 RCLK3 and TCLKS rise
48. e Pin Number Type A 0 31 R16 N14 M14 P15 P17 P16 N15 N16 M15 N17 L14 M16 Bidirectional L15 M17 K14 L16 L17 K17 G17 K15 J16 J15 G16 J14 H17 Three state 3 3 V only H16 G15 K16 H14 J17 H15 F17 TSIZO F16 Bidirectional REG Three state 3 3 V only MPC875 MPC870 Hardware Specifications Rev 3 0 72 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Mechanical Data and Ordering information Table 36 Pin Assignments JEDEC Standard continued Name Pin Number Type TSIZ1 G14 Bidirectional Three state 3 3 V only RD WR D13 Bidirectional Three state 3 3 V only BURST B9 Bidirectional Three state 3 3 V only BDIP C13 Output GPL B5 TS C11 Bidirectional Active pull up 3 3 V only TA C12 Bidirectional Active pull up 3 3 V only TEA B12 Open drain BI B13 Bidirectional Active pull up 3 3 V only IRQ2 9 Bidirectional RSV Three state 3 3 V only IRQ4 E9 Bidirectional KR Three state 3 3 V only RETRY SPKROUT D 0 31 L5 N3 L3 L2 R2 K2 H3 G2 R3 M3 N2 M2 M4 N4 K5 K3 K4 Bidirectional P3 J2 J3 J4 05 H2 P2 H4 H5 G5 L4 G3 F2 F3 E2 Three state 3 3 V only CR E10 Input IRQ3 FRZ B10 Bidirectional IRQ6 Three state 3 3 V only BR B11 Bidirectional 3 3 V only BG D10 Bidirectional 3 3 V only BB C10 Bidirectional Active pull up 3 3 V only IRQO M6
49. equal to an integer number of character length clocks Figure 58 SMC Transparent Timing Diagram 13 9 SPI Master AC Electrical Specifications Table 26 provides the SPI master timings as shown in Figure 59 and Figure 60 Table 26 SPI Master Timing All Num Characteristic Frequencies Unit Min Max 160 MASTER cycle time 4 1024 teyc 161 1 MASTER clock SCK high or low time 2 512 toye 162 MASTER data setup time inputs 15 ns 163 Master data hold time inputs 0 ns 164 1Master data valid after SCK edge 10 ns 165 Master data hold time outputs 0 ns 166 1 Rise time output 15 ns 167 Fall time output 15 ns MPC875 MPC870 Hardware Specifications Rev 3 0 62 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics SPICLK 1 0 Output SPICLK Cl 1 Output SPIMISO Input SPIMOSI Output SPICLK 1 0 Output SPICLK Cl 1 Output SPIMISO Input SPIMOSI Output Figure 60 SPI Master CP 1 Timing Diagram MPC875 MPC870 Hardware Specifications Rev 3 0 63 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics 13 10SPI Slave AC Electrical Specifications Table 27 provides the SPI slave timings as shown in Figure 61 and Figure 62 Table 27 SPI Slave Timing
50. h impedance 20 00 ns J90 TRST assert time 100 00 ns 491 TRST setup time to TCK low 40 00 ns J92 falling edge to output valid 50 00 ns J93 falling edge to output valid out of high impedance 50 00 ns J94 TCK falling edge to output high impedance 50 00 ns J95 1 Boundary scan input valid to TCK rising edge 50 00 ns J96 TCK rising edge to boundary scan input invalid 50 00 ns MPC875 MPC870 Hardware Specifications Rev 3 0 44 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor IEEE 1149 1 Electrical Specifications TCK TCK TMS TDI TDO Figure 37 JTAG Test Access Port Timing Diagram TCK 90 J90 TRST Figure 38 JTAG TRST Timing Diagram MPC875 MPC870 Hardware Specifications Rev 3 0 45 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics TCK Output Signals Output Signals Jan joe 95 J96 Output Signals Figure 39 Boundary Scan JTAG Timing Diagram 13 CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module CPM of the MPC875 870 13 1 Port C Interrupt AC Electrical Specifications Table 17 provides the timings for port C interrupts Table 17 Port C Interrupt Timing 33 34 MHz Num Characteri
51. it CST4 in the corresponding vvord in the UPM MAX 0 00 x B1 6 00 1 50 6 00 1 50 6 00 1 50 6 00 1 50 6 00 ns B31a CLKOUT falling edge to CS valid as requested by control bit CST1 in the corresponding vvord in the UPM MAX 0 25 x B1 6 80 7 60 14 30 6 30 13 00 3 80 10 50 3 13 10 00 ns B31b CLKOUT rising edge to CS valid as requested by control bit CST2 in the corresponding word in the UPM MAX 0 00 x B1 8 00 1 50 8 00 1 50 8 00 1 50 8 00 1 50 8 00 ns B31c CLKOUT rising edge to CS valid as requested by control bit CST3 in the corresponding word in the UPM MAX 0 25 x B1 6 30 7 60 13 80 6 30 12 50 3 80 10 00 3 13 9 40 ns B31d CLKOUT falling edge to CS valid as requested by control bit CST1 in the corresponding word in the UPM EBDF 1 MAX 0 375 x B1 6 6 13 30 18 00 11 30 16 00 7 60 12 30 4 69 11 30 ns B32 CLKOUT falling edge to BS valid as requested by control bit BST4 in the corresponding word in the UPM MAX 0 00 x B1 6 00 1 50 6 00 1 50 6 00 1 50 6 00 1 50 6 00 ns B32a CLKOUT falling edge to BS valid as requested by control bit BST1 in the corresponding word in the UPM EBDF 0 MAX 0 25 x B1 6 80 7 60 14 30 6 30 13 00 3 80 10 50 3 13 10 00 ns B32b CLKOUT rising edge t
52. k Timing MPC875 MPC870 Hardware Specifications Rev 3 0 24 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 6 provides the timing for the synchronous output signals CLKOUT 2 2 A 0 Output v Signals A Output G Signals Output v Signals Figure 6 Synchronous Output Signals Timing Figure 7 provides the timing for the synchronous active pull up and open drain output signals CLKOUT B13 0 TEA Figure 7 Synchronous Active Pull Up Resistor and Open Drain Outputs Signals Timing MPC875 MPC870 Hardware Specifications Rev 3 0 25 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 8 provides the timing for the synchronous input signals aur ff XX fisa TEA KR RETRY CR sum WO Figure 8 Synchronous Input Signals Timing Figure 9 provides normal case timing for input data It also applies to normal read accesses under the control of the user programmable machine UPM in the memory controller oor ff ua 0007 mee XX XX Figure 9 Input Data Timing in Normal Case MPC875 MPC870 Hardware Specifications Rev 3 0 26 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 10 provides the timing for the input data controlled by the U
53. lid as requested by control bit CST4 in the corresponding word in the UPM MIN 0 25 x B1 2 00 5 60 4 30 1 80 ns B34a A 0 31 BADDR 28 30 and D 0 31 to CS valid as requested by control bit CST1 in the corresponding word in the UPM MIN 0 50 x B1 2 00 13 20 10 50 5 60 4 25 5 B34b A 0 31 BADDR 28 30 and D 0 31 to CS valid as requested by CST2 in the corresponding word in UPM MIN 0 75 x B1 2 00 20 701 16 70 9 40 6 80 ns B35 A 0 31 BADDR 28 30 to CS valid as requested by control bit BST4 in the corresponding vvord in the UPM MIN 0 25 x B1 2 00 5 60 4 30 1 80 1 13 ns B35a A 0 31 BADDR 28 30 and D 0 31 to BS valid as requested by BST1 in the corresponding word in the UPM MIN 0 50 x B1 2 00 13 20 10 50 5 60 4 25 ns B35b A 0 31 BADDR 28 30 and D 0 31 to BS valid as requested by control bit BST2 in the corresponding word in the UPM MIN 0 75 x B1 2 00 20 70 16 70 9 40 7 40 ns B36 A 0 31 BADDR 28 30 and D 0 31 to GPL valid as requested by control bit GxT4 in the corresponding word in the UPM MIN 0 25 x B1 2 00 5 60 4 30 1 80 ns B37 UPWAIT valid to CLKOUT falling edge 8 MIN 0 00 x B1 6 00 6 00 6 00 6 00 6 00 ns B38 CLKOUT falling edge to UPWAI
54. n the processor clock frequency must exceed the MIT CLK frequency 1 Table 32 provides information on the MII transmit signal timing Table 32 MII Transmit Signal Timing MIl_TX_CLK to TXD 3 01 MIL_TX_EN invalid SS a TX CLK to MII_TXD 3 0 M L TX EN valid oe 7 un Tun yx cuxane san sm ss TCO n Yes TK MPC875 MPC870 Hardware Specifications Rev 3 0 68 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor FEC Electrical Characteristics Table 32 MII Transmit Signal Timing continued l li M20 R RMII TXD 1 01 TX EN to RMII REFCLK setup 4 ns MII Se M21 R RMII TXD 1 01 RMII TX EN data hold from RMII_REFCLK rising Mil edge Figure 65 shows the MII transmit signal timing diagram M7 MII_TX_CLK input M5 M8 MII_TXD 3 0 outputs MII_TX_EN MII_TX_ER M6 Figure 65 MII Transmit Signal Timing Diagram 15 3 MII Async Inputs Signal Timing MII CRS MII_COL Table 33 provides information on the MII async inputs signal timing Table 33 MII Async Inputs Signal Timing Num Characteristic Min Max Unit M9 MII_CRS MII_COL minimum pulse width 1 5 MII_TX_CLK period Figure 66 shows the MII asynchronous inputs signal timing diagram MII_CRS MII_COL M9 Figure 66 MII Async Inputs Timing Diagram MPC875 MPC870
55. o BS valid as requested by control bit BST2 in the corresponding word in the UPM MAX 0 00 x B1 8 00 1 50 8 00 1 50 8 00 1 50 8 00 1 50 8 00 ns B32c CLKOUT rising edge to BS valid as requested by control bit BST3 in the corresponding vvord in the UPM MAX 0 25 x B1 6 80 7 60 14 30 6 30 13 00 3 80 10 50 3 13 10 00 ns B32d CLKOUT falling edge to BS valid as requested by control bit BST1 in the corresponding word in the UPM EBDF 1 MAX 0 375 x B1 6 60 13 30 18 00 11 30 16 00 7 60 12 30 4 49 11 30 ns B33 CLKOUT falling edge to GPL valid as requested by control bit GxT4 in the corresponding word in the UPM MAX 0 00 x B1 6 00 1 50 6 00 1 50 6 00 1 50 6 00 1 50 6 00 ns MPC875 MPC870 Hardware Specifications Rev 3 0 21 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 10 Bus Operation Timings continued Num Characteristic 33 MHz 40 MHz 66 MHz 80 MHz Min 1 Max Min Max Min Max Min Max Unit B33a CLKOUT rising edge to GPL valid as requested by control bit GxT3 in the corresponding word in the UPM MAX 0 25 x B1 6 80 7 60 14 30 6 30 13 00 3 80 10 50 3 13 10 00 ns B34 A 0 31 BADDR 28 30 and D 0 31 to CS va
56. on the SCC supporting full 10 Mbps operation HDLC SDLC HDLC bus implements an HDLC based local area network LAN Asynchronous HDLC to support point to point protocol PPP AppleTalk Universal asynchronous receiver transmitter UART Synchronous UART Serial infrared IrDA Binary synchronous communication BISYNC Totally transparent bit streams Totally transparent frame based with optional cyclic redundancy check CRC e SMC serial management channel UART low speed operation Transparent e Universal serial bus USB Supports operation as a USB function endpoint a USB host controller or both for testing purposes loopback diagnostics USB 2 0 full ovv speed compatible The USB function mode has the follovving features Four independent endpoints support control bulk interrupt and isochronous data transfers MPC875 MPC870 Hardware Specifications Rev 3 0 4 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Features CRC16 generation and checking CRC5 checking NRZI encoding decoding with bit stuffing 12 or 1 5 Mbps data rate Flexible data buffers with multiple buffers per frame Automatic retransmission upon transmit error The USB host controller has the following features Supports control bulk interrupt and isochronous data transfers 16 generation and checking NRZI encoding decoding with
57. ongly dependent on the board temperature If the board temperature is known an estimate of the junction temperature in the environment can be made using the following equation Ty Ta Rey x Pp vvhere Roy junction to board thermal resistance C W Ta board temperature C Pp power dissipation in package If the board temperature is known and the heat loss from the package case to the air can be ignored acceptable predictions of junction temperature can be made For this method to work the board and board mounting must be similar to the test board used to determine the junction to board thermal resistance namely a 2s2p board with a power and a ground plane and vias attaching the thermal balls to the ground plane 7 4 Estimation Using Simulation When the board temperature is not known a thermal simulation of the application is needed The simple two resistor model can be used with the thermal simulation of the application 2 or a more accurate and complex model of the package can be used in the thermal simulation 7 5 Experimental Determination To determine the junction temperature of the device in the application after prototypes are available the thermal characterization parameter VY yy can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation Ty Tr x Pp vvhere thermal characterization parame
58. ory Variable block sizes 32 Kbyte 256 Mbyte Selectable write protection On chip bus arbitration logic HGeneral purpose timers Four 16 bit timers or tvvo 32 bit timers Gate mode can enable disable counting Interrupt can be masked on reference match and event capture e Two fast Ethernet controllers FEC Two 10 100 Mbps Ethernet IEEE 802 3 CDMAV CS that interface through MII and or RMII interfaces e System integration unit SIU Bus monitor Software watchdog Periodic interrupt timer PIT Clock synthesizer Decrementer and time base Reset controller IEEE 1149 1 test access port JTAG e Security engine is optimized to handle all the algorithms associated with IPsec SSL TLS SRTP 802 11i and iSCSI processing Available on the MPC875 the security engine contains a crypto channel a controller and a set of crypto hardware accelerators CHAs The CHAs are Data encryption standard execution unit DEU DES 3DES Two key K1 K2 K1 or three key K1 K2 K3 ECB and CBC modes for both DES and 3DES Advanced encryption standard unit AESU Implements the Rinjdael symmetric key cipher ECB CBC and counter modes 128 192 and 256 bit key lengths Message digest execution unit MDEU SHA with 160 or 256 bit message digest MD5 with 128 bit message digest HMAC with either algorithm Master slave logic with DMA 32 bit addres
59. ough Figure 17 provide the timing for the external bus vvrite controlled by various GPCM factors CLKOUT 2 Ne 7 E D 0 31 Figure 15 External Bus Write Timing GPCM Controlled TRLX 0 CSNT 0 MPC875 MPC870 Hardware Specifications Rev 3 0 30 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing CLKOUT a s v 010 31 Figure 16 External Bus VVrite Timing GPCM Controlled TRLX 0 CSNT 1 MPC875 MPC870 Hardware Specifications Rev 3 0 31 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing CLKOUT Al0 31 D 0 31 Figure 17 External Bus Write Timing GPCM Controlled TRLX 1 CSNT 1 MPC875 MPC870 Hardware Specifications Rev 3 0 32 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 18 provides the timing for the external bus controlled by the UPM CLKOUT CSx 2 a ee D B32 Bam a 0 oe MA B36 g l g S GPL 10 5 Figure 18 External Bus Timing UPM Controlled Signals MPC875 MPC870 Hardware Specifications Rev 3 0 33 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor
60. perating conditions are provided with the DC electrical specifications in Table 6 Absolute maximum ratings are stress ratings only functional operation at the maxima is not guaranteed Stress beyond those listed may affect device reliability or cause permanent damage to the device Caution All inputs that tolerate 5 V cannot be more than 2 5 V greater than VDDH This restriction applies to power up and normal operation that is if the MPC875 870 is unpowered a voltage greater than 2 5 V must not be applied to its inputs Table 3 Operating Temperatures Rating Symbol Value Unit Temperature 1 standard Ta min 0 C Tifmax 95 C Temperature extended Ta min 40 C Tifmax 100 C T Minimum temperatures are guaranteed as ambient temperature TA Maximum temperatures are guaranteed as junction temperature Ti This device contains circuitry protecting against damage due to high static voltage or electrical fields however it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level for example either GND or Vppy MPC875 MPC870 Hardware Specifications Rev 3 0 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Thermal Characteristics 4 Thermal Characteristics T
61. rediction with conditional prefetch and without conditional execution 8 Kbyte data cache and 8 Kbyte instruction cache see Table 1 Instruction cache is two way set associative with 256 sets in 2 blocks Data cache is two way set associative with 256 sets Cache coherency for both instruction and data caches is maintained on 128 bit 4 word cache blocks Caches are physically addressed implement a least recently used LRU replacement algorithm and are lockable on a cache block basis MMwUs with 32 entry TLB fully associative instruction and data TLBs MMwUs support multiple page sizes of 4 16 and 512 Kbytes and 8 Mbytes 16 virtual address spaces and 16 protection groups Advanced on chip emulation debug mode e Up to 32 bit data bus dynamic bus sizing for 8 16 and 32 bits 32 address lines e Memory controller eight banks Contains complete dynamic RAM DRAM controller Each bank can be a chip select or RAS to support a DRAM bank Up to 30 wait states programmable per memory bank Glueless interface to DRAM SIMMS SRAM EPROMs Flash EPROMs and other memory devices DRAM controller programmable to support most size and speed memory interfaces Four CAS lines four WE lines and one OE line MPC875 MPC870 Hardware Specifications Rev 3 0 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Features Boot chip select available at reset options for 8 16 or 32 bit mem
62. reescale Semiconductor Bus Signal Timing Figure 33 shovvs the reset timing for the data bus configuration HRESET R7 D RSTCONF R73 5 Figure 33 Reset Timing Configuration from Data Bus Figure 34 provides the reset timing for the data bus vveak drive during configuration m 75 7 ae HRESET RSTCONF er F D 0 31 OUT VVeak pe Figure 34 Reset Timing Data Bus Weak Drive During Configuration MPC875 MPC870 Hardware Specifications Rev 3 0 43 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor IEEE 1149 1 Electrical Specifications Figure 35 provides the reset timing for the debug port configuration SRESET Rao R80 gt XJ DSCK DSDI Figure 35 Reset Timing Debug Port Configuration 12 IEEE 1149 1 Electrical Specifications Table 16 provides the JTAG timings for the MPC875 870 shown in Figure 36 to Figure 39 Table 16 JTAG Timing All Num Characteristic Frequenci s Unit Min Max J82 TCK cycle time 100 00 ns J83 TCK clock pulse width measured at 1 5 V 40 00 ns J84 rise and fall times 0 00 10 00 ns J85 TMS TDI data setup time 5 00 ns J86 TMS TDI data hold time 25 00 ns J87 low to TDO data valid 27 00 ns J88 low to TDO data invalid 0 00 ns J89 TCK low to TDO hig
63. refer to the rising edge of the CLKOUT in which the TA input signal is asserted 5 For part speeds above 50 MHz use 2 ns for B19 6 The D 0 31 input timings B20 and B21 refer to the falling edge of the CLKOUT This timing is valid only for read accesses controlled by chip selects under control of the user programmable machine UPM in the memory controller for data beats where DLT3 1 in the RAM words This is only the case where data is latched on the falling edge of CLKOUT 7 The timing B30 refers to CS when ACS 00 and to WE 0 3 when CSNT 0 8 The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally The timings specified in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 19 9 The AS signal is considered asynchronous to the CLKOUT The timing B39 is specified in order to allow the behavior specified in Figure 22 MPC875 MPC870 Hardware Specifications Rev 3 0 23 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Figure 4 provides the control timing diagram CLKOUT Outputs Outputs nputs nputs A Maximum output delay specification B Minimum output hold time c Minimum input setup time specification Minimum input hold time specification Figure 4 Control Timing Figure 5 provides the timing for the external clock CLKOUT Figure 5 External Cloc
64. requencies in 1 1 bus mode and Table 9 shows the frequency ranges for standard part frequencies in 2 1 bus mode Table 8 Frequency Ranges for Standard Part Frequencies 1 1 Bus Mode Part Frequency 66 MHz 80 MHz Min Max Min Max Core frequency 40 66 67 40 80 Bus frequency 40 66 67 40 80 MPC875 MPC870 Hardware Specifications Rev 3 0 15 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 9 Frequency Ranges for Standard Part Frequencies 2 1 Bus Mode Part Frequency 66 MHz 80 MHz 133 MHz Min Max Min Max Min Max Core frequency 40 66 67 40 80 40 133 Bus frequency 20 33 33 20 40 20 66 Table 10 provides the bus operation timing for the MPC875 870 at 33 40 66 and 80 MHz The timing for the MPC875 870 bus shown assumes a 50 pF load for maximum delays and a 0 pF load for minimum delays CLKOUT assumes a 100 pF load maximum delay Table 10 Bus Operation Timings 33 MHz 40 MHz 66 MHz 80 MHz Num Characteristic Unit Min Max Min Max Min Max Min Max B1 Bus period CLKOUT see Table 8 ns Bia 1 EXTCLK to CLKOUT phase skew If 2 2 2 2 ns CLKOUT is an integer multiple of EXTCLK then the rising edge of EXTCLK is aligned with the rising edge of CLKOUT For a non integer multiple of EXTCLK this synchronization is lost and the rising edges of E
65. resistance 6 Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51 2 5 Power Dissipation Table 5 provides information on power dissipation The modes are 1 1 where CPU and bus speeds are equal and 2 1 where CPU frequency is twice bus speed Table 5 Power Dissipation Pp Die Revision eae Frequency Typical 1 Maximum Unit 66 MHz 310 390 mW 4 S 80 MHz 350 430 mW 2 1 133 MHz 430 495 mW 1 Typical power dissipation is measured at VppsvN 1 8 V and Vppy is at 3 3 V MPC875 MPC870 Hardware Specifications Rev 3 0 Freescale Semiconductor PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 9 DC Characteristics 2 Maximum power dissipation at Vppsyy 1 9 V and Vppu is at 3 5 V NOTE The values in Table 5 represent Vppy based power dissipation and do not include VO power dissipation over Vppu I O power dissipation varies widely by application due to buffer current depending on external circuitry The Vppsyy power dissipation is negligible 6 DC Characteristics Table 6 provides the DC electrical characteristics for the MPC875 870 Table 6 DC Electrical Specifications Characteristic Symbol Min Max Unit Operating voltage I O 3 135 3 465 V VppL Core 1 7 1 9 V Vppsyn 1 7 1 9 V Difference 100 mv between VDDL and VDDSY
66. rized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Learn More For more information about Freescale Semiconductor products please visit www freescale com Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc The described product contains a PowerPC processor core The PowerPC name is a trademark of IBM Corp and used under license All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2004 ae z freescale semiconductor
67. s Rev 3 0 35 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Bus Signal Timing Table 11 provides the interrupt timing for the MPC875 870 Table 11 Interrupt Timing All Frequencies Num Characteristic 1 Unit Min Max 139 IRQx valid to CLKOUT rising edge setup time 6 00 ns 140 11RQx hold time after CLKOUT 2 00 ns 141 11RQx pulse width low 3 00 ns 142 11RQx pulse width high 3 00 ns 143 11RQx edge to edge time 4xTcLocKOUT T The 139 and 140 timings describe the testing conditions under which the RQ lines are tested when being defined as level sensitive The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT The 141 142 and 143 timings are specified to allow correct functioning of the IRQ lines detection circuitry and have no direct relation with the total system interrupt latency that the MPC875 870 is able to support Figure 24 provides the interrupt detection timing for the external level sensitive lines CLKOUT Figure 24 Interrupt Detection Timing for External Level Sensitive Lines Figure 25 provides the interrupt detection timing for the external edge sensitive lines CLKOUT Fo a g ee 12 a 143 gt Vey Figure 25 Interrupt Detection Timing for External Edge Sensitive Lines MPC875 MPC870 Hardware Specifications Rev 3 0 36 PRELIMINARY SUBJECT TO CHANGE WITHOUT
68. s 32 bit data Operation at 8xx bus frequency Crypto channel supporting multi command descriptors Integrated controller managing crypto execution units Buffer size of 256 bytes for each execution unit with flow control for large data sizes e Interrupts Six external interrupt request IRQ lines MPC875 MPC870 Hardware Specifications Rev 3 0 Freescale Semiconductor PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 3 Features 12 port pins vvith interrupt capability 223 internal interrupt sources Programmable priority betvveen SCCs Programmable highest priority request e Communications processor module CPM RISC controller Communication specific commands for example GRACEFUL STOP TRANSMIT ENTER HUNT MODE and RESTART TRANSMIT Supports continuous mode transmission and reception on all serial channels 8 Kbytes of dual port RAM Several serial DMA SDMA channels to support the CPM Three parallel I O registers with open drain capability e On chip 16 X 16 multiply accumulate controller MAC One operation per clock two clock latency one clock blockage MAC operates concurrently with other instructions FIR loop Four clocks per four multiplies e Four baud rate generators Independent can be connected to any SCC or SMC Allows changes during operation Autobaud support option SCC serial communication controller Ethernet IEEE 802 3 optional
69. s compatible with devices operating at either 5 0 V or 3 3 V 15 1 MII and Reduced MII Receive Signal Timing The receiver functions correctly up to a MIT_RX_CLK maximum frequency of 25 MHz 1 The reduced MII RM receiver functions correctly up toa RMIT_REFCLK maximum frequency of 50 MHz 1 There is no minimum frequency requirement In addition the processor clock frequency must exceed the MIT RX CLK frequency 1 MPC875 MPC870 Hardware Specifications Rev 3 0 67 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor FEC Electrical Characteristics Table 31 provides information on the MII receive signal timing Table 31 MII Receive Signal Timing Num Characteristic Min M MII_RXD 3 0 MIl_RX_DV MII_RX_ER to MII_RX_CLK setup M2 mi RX_CLK to MII_RXD 3 0 MII RX DV MII_RX_ER hold 4 2 MII_RX_CLK pulse width high MII_RX_CLK period M1 M2 M3 M1_R 2R RMII_RXD 1 0 RMII_CRS_DV RMII_RX_ERR to RMII_REFCLK ns MII setup M M RMIL REFCLK to RMII_RXD 1 0 CRS DV RMIl_RX_ERR MII hold Figure 64 shows MII receive signal timing M3 RX CLK input M4 MIl_RXDJ 3 0 inputs RX DV MIL RX ER y M1 Figure 64 Receive Signal Timing Diagram 15 2 MII and Reduced Mil Transmit Signal Timing The transmitter functions correctly up to a TX CLK maximum frequency of 25 MHz 1 There is no minimum frequency requirement In additio
70. serve power 1 8 V core and 3 3 V I O operation with 5 V TTL compatibility MPC875 870 comes in a 256 pin ball grid array PBGA package MPC875 MPC870 Hardware Specifications Rev 3 0 Freescale Semiconductor PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 5 Features The MPC875 block diagram is shown in Figure 1 System Interface Unit SIU Embedded MPC8xx Processor Core Fast Ethernet Controller 10 100 BaseT Media Access Control MILI R MII Instruction 8 K byte Bus Instruction Cache 32 Entry ITLB Bus Internal External Bus Interface Bus Interface 8 Kbyte Unit Unit Data Cache System Functions Data MMU 32 Entry DTLB PCMCIA ATA Interface Slave M aster IF Instruction MMU Unified Memory Controller nie Security Engine Controller AESU MDEU 4 Interrupt 8 K byte Parallel 1 0 Controllers Dual Port RAM 4 Baud Rate 32 Bit RISC Controller Virtual IDMA and Program Parallel Interface Port ROM Serial DMAs USB SCC4 SMC1 SPI 12 Time Slot Assigner tt Serial Interface Figure 1 MPC875 Block Diagram MPC875 MPC870 Hardware Specifications Rev 3 0 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Maximum Tolerated Ratings The MPC870 block diagram is shown in Figure 2 nstruction 8 Kbyte Bus Instruction Cache Instruction MMU Unified Memory Controller H gt System Interface Unit SIU ye 32 ITLB gys Internal External
71. sign or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unautho
72. stic Unit Min Max 35 Port C interrupt pulse width low edge triggered mode 55 ns 36 Port C interrupt minimum time betvveen active edges 55 ns Figure 40 shovvs the port C interrupt detection timing 36 gt Port C Input Figure 40 Port C Interrupt Detection Timing MPC875 MPC870 Hardware Specifications Rev 3 0 46 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics 13 2 IDMA Controller AC Electrical Specifications Table 18 provides the IDMA controller timings as shown in Figure 41 to Figure 44 Table 18 IDMA Controller Timing All Num Characteristic Frequencies Unit Min Max 40 DREQ setup time to clock high 7 ns 41 DREQ hold time from clock high 1 TBD ns 42 SDACK assertion delay from clock high 12 ns 43 SDACK negation delay from clock low 12 ns 44 SDACK negation delay from TA low 20 ns 45 8 negation delay from clock high 15 ns 46 TA assertion to falling edge of the clock setup time applies to external TA 7 ns 1 Applies to high to lovv mode EDM 1 CLKO Output 0 DREQ Input Figure 41 IDMA External Requests Timing Diagram MPC875 MPC870 Hardware Specifications Rev 3 0 47 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics CLKO Output TS Output R W Output TA Input SDACK
73. t were typos 0 5 5 2003 Changed the pin descriptions for PD8 and PD9 0 6 5 2003 Changed a few typos Put back the 12C Put in the new reset configuration corrected the USB timing 0 7 6 2003 Changed the pin descriptions per the June 22 spec removed Utopia from the pin descriptions changed PADIR PBDIR PCDIR and PDDIR to be 0 in the Mandatory Reset Config 0 8 8 2003 Added the reference to USB 2 0 to the Features list and removed 1 1 from USB on the block diagrams 0 9 8 2003 Changed the USB description to full low speed compatible 1 0 9 2003 Added the DSP information in the Features list Put a new sentence under Mechanical Dimensions Fixed table formatting Nontechnical edits Released to the external web 1 1 10 2003 Added TDMb to the MPC875 Features list the MPC875 Block Diagram added 13 5 Serial Interface AC Electrical Specifications and removed TDMa from the pin descriptions MPC875 MPC870 Hardware Specifications Rev 3 0 82 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Document Revision History Table 37 Document Revision History continued Revision N mber Date Changes 2 0 12 2003 Changed DBGC in the Mandatory Reset Configuration to X1 Changed the maximum operating frequency to 133 MHZ Put the timing in the 80 MHz column Put in the orderable part numbers Rounded the timings to hundredths in the 80 MHz column Put the pin numbers in footnotes by the maximum c
74. ted printed circuit traces connecting to chip Vpp and GND should be kept to less than half an inch per capacitor lead At a minimum a four layer board employing two inner layers as Vpp and GND planes should be used All output pins on the MPC875 870 have fast rise and fall times Printed circuit PC trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times This recommendation particularly applies to the address and data buses Maximum PC trace lengths of six inches are recommended Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the Vpp and GND circuits Pull up all unused inputs or signals that will be inputs during reset Special care should be taken to minimize the noise levels on the PLL supply pins For more information please refer to Section 14 4 3 Clock Synthesizer Power Vppsyn Vsssyn gt Vsssyn1 of the 885 PowerQUICC Family User s Manual 11 Bus Signal Timing The maximum bus speed supported by the MPC875 870 is 80 MHz Higher speed parts must be operated in half speed bus mode for example an MPC875 870 used at 133 MHz must be configured for a 66 MHz bus Table 8 shows the frequency ranges for standard part f
75. ter Ty thermocouple temperature on top of package Pp power dissipation in package The thermal characterization parameter is measured per the JESD51 2 specification published by JEDEC using a 40 gauge type T thermocouple epoxied to the top center of the package case The thermocouple should be positioned so that the thermocouple junction rests on the package A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction The thermocouple wire is placed flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire MPC875 MPC870 Hardware Specifications Rev 3 0 12 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor Power Supply and Power Sequencing 7 6 References Semiconductor Equipment and Materials International 415 964 5111 805 East Middlefield Rd Mountain View CA 94043 MIL SPEC and EIA JESD JEDEC specifications 800 854 7179 or Available from Global Engineering Documents 303 397 7956 JEDEC Specifications http www jedec org 1 C E Triplett and B Joiner An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module Proceedings of SemiTherm San Diego 1998 pp 47 54 2 B Joiner and V Adams Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling Proceedings of SemiTherm San Diego 1999 pp 21
76. timings as shown in Figure 55 to Figure 57 Table 24 Ethernet Timing All Num Characteristic Frequencies Unit Min Max 120 CLSN width high 40 ns 121 RCLK3 rise fall time 15 ns 122 1 RCLKS3 width low 40 m ns 123 RCLK3 clock period 80 120 ns 124 1 RXDS8 setup time 20 ns 125 1 RXD3 hold time 5 ns 126 RENA active delay from RCLK3 rising edge of the last data bit 10 ns 127 RENA width low 100 ns 128 TCLK3 rise fall time m 15 ns 129 TCLK3 width low 40 ns 130 TCLK3 clock period 99 101 ns 131 1 TXD3 active delay from TCLK3 rising edge 50 ns 132 TXD3 inactive delay from TCLK rising edge 6 5 50 ns MPC875 MPC870 Hardware Specifications Rev 3 0 59 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Freescale Semiconductor CPM Electrical Characteristics Table 24 Ethernet Timing continued All Num Characteristic Frequencies Unit Min Max 133 TENA active delay from TCLK3 rising edge 10 50 ns 134 TENA inactive delay from TCLK3 rising edge 10 50 ns 138 CLKO1 low to SDACK asserted 20 ns 139 CLKO1 low to SDACK negated 20 ns 1 The ratios SyncCLK RCLK3 and SyneCLK TCLK3 must be greater than or equal to 2 1 2 SDACK is asserted whenever the SDMA writes the incoming frame DA into memory CLSN CTS1 Input gt Figure 55 Ethernet Collision Timing Diagram RCLK3
77. urrents in Table 6 Changed 22 and 41 in the Timing Put TBD in the Thermal table 3 0 1 07 2004 Added sentence to Spec B1A about EXTCLK and CLKOUT being in Alignment for 7 19 2004 Integer Values Added a footnote to Spec 41 specifying that EDM 1 Added the thermal numbers to Table 4 Added RMII1 EN under M1II_EN in Table 36 Pin Assignments Added a tablefootnote to Table 6 DC Electrical Specifications about meeting the VIL Max of the 12 Standard e Put the new part numbers in the Ordering Information Section MPC875 MPC870 Hardware Specifications Rev 3 0 Freescale Semiconductor PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE 83 How to Reach Us USA Europe Locations Not Listed Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 480 768 2130 800 521 6274 dapan Freescale Semiconductor Japan Ltd Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 8573 Japan 81 3 3440 3569 Asia Pacific Freescale Semiconductor Hong Kong Ltd 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 852 26668334 Home Page www freescale com MPC875EC Rev 3 0 07 2004 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to de

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