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Physical Layer Design for a Spread Spectrum Wireless LAN

1. Figure 2 3 e To 14 c t 0 gt t A 1 d t Tb 0 gt t A 1 T t d t c t 0 gt t 1 T t O c t d t as c t Gc t 0 0 gt t Figure 2 2 Direct Sequence Spread Spectrum Spreading and Despreading The narrow pulses with duration 7 are referred to as chips The bandwidth expansion factor or processing gain is determined by N Ty Te where Tp is the information symbol duration The autocorrelation function of c t is given by R t R t ur 2 2 00 S w the power spectral density PSD of c t is the Fourier transform of R t CHAPTER 2 SPREAD SPECTRUM AND WIRELESS LANS Baseband Ba ol Data Information modulo 2 T D modulation amp DownConverter modulo 2 Output d t Data d t adder UpConverter amp Demodulatior adder la PN Code Local PN Code Generator Generator Figure 2 3 A Typical Direct Sequence Spread Spectrum Transmitter and Receiver R t FS 2 3 To spread the spectrum equally a relatively constant power spectral density for c t is desired Ideally the autocorrelation function R t which is the reverse Fourier transform of the power spectral density S w is an impulse function t see Figure 2 4 Practically R t has a peak value when t 0 and is relatively small when t Z 0 The larger the peak value the more signal to noise ratio SNR margi
2. EE Z80182 RAM ld gt T an Tx Buffer STEL m E 2000 o HOST E Rx Buffer D o CPU Program a ar Storage o RF Control ER i CAR 780182 Communication Peripherals Figure 6 1 Overall Software Environment The comprehensive description of each peripheral interface is presented in the next section In Section 6 3 we will briefly discuss the flow chart of Zilog s emulation program 79 CHAPTER 6 SOFTWARE DEVELOPMENT Recommended future software development is suggested in Section 6 4 6 2 Peripheral Interfaces The interface between the 280182 PC and Z2000 is depicted in Figure 6 2 The Zilog 780182 is an intelligent peripheral controller It provides three 8 bit parallel input output I O Ports Ports A B and C and two ESCC channels Channels A and B rial Signal leed RxDA Serial Transfer 2 o yy Cu ESCC Channel B TXDA TxIN ia Z80182 T m EG ESCC Channel Serial N 8 bits A Port C Transfer S Y Port A Parallel Signals Control amp Parallel Host Control Serial Data Bus Transfer Port B 8 bits y e PC ISA Bus RF Control Figure 6 2 Peripheral Interfaces Configured to Plug in PC ISA Bus PORT A When the Z2000 Evaluation Board is plugged into the ISA bus of a PC the software residing in the 280182 will detect the ISA bus connection and configure this port to be the host data bus for parallel data transfer between the PC and the Z80182 PORT
3. ap gr 3d S1 ld Wap BL ZHWN 89 BAT SAA EP de 17 9bb ga NV 3d WEP ge J3H uy G2 ONY pe Zh ch Figure 5 13 Tx Exciter Output Spectrum 77 Chapter 6 Software Development 6 1 Physical Layer Control Program Description Figure 6 1 is an illustration of the overall system model on which the control software is based The 280182 718 94 supports 128 kbytes of RAM and 64 kbytes of read only memory ROM The RAM space is divided into three portions the transmitter buffer TxBuffer the receiver buffer RxBuffer and the control program space The locations and the sizes of these two buffers are defined by the control program and the buffer spaces are reserved during system initialization The ROM stores the Zilog provided Z80182 firmware which performs board level initialization after power up or reset and then invokes the Z80182 Debug Monitor and a Hayes compatible AT command Set Processor The data flow is shown in Figure 6 1 The MAC layer first sends its data frames to the assigned serial Com port connected to the personal computer PC bus The Z80182 retrieves the data and then passes them to the 7280182 controller The control program then takes the data and stores them in the transmitter buffer TxBuffer At the same time the Z80182 s Enhanced Serial Communications Controller ESCC is activated to fetch data from the transmitter buffer and then converts them into a serial bit
4. vr vr rn kran rn ra 51 Theoretical BER Performance of Non coherent DPSK 53 Quantization Effect o o sa sakke a ka Se ge A 55 BER Performance with Symbol Tracking Threshold 5 57 BER Performance with Symbol Tracking Ej N 4 dB 58 BER Performance with Symbol Tracking E N 6dB 59 RF Module Architecture 2222s 62 vii LIST OF FIGURES 5 2 Functional Blocks of the Transmitter Module 64 5 3 Detailed Circuit for Tx Exciter o 0 000 000 0000 65 5 4 Detailed Circuit for Tx Exciter e e 66 5 5 Overall System Hardware Interface rv rn rer ra eee 68 5 6 Colpitts Crystal Oscillator rar rv rn rer ra kran 69 5 7 The AC Equivalent Colpitts Oscillator rv arva 69 5 8 Another Equivalent Circuit 2 22 70 5 9 MAV 11 Amplifier 22r 72 5 10 Baseband Spread Signal TxI Spectrum kran 74 5 11 Baseband Spread Signal Spectrum After Low pass Filter 75 5 12 Colpitts Crystal Oscillator Output Spectrum 76 5 13 Tx Exciter Output Spectrum len 77 6 1 Overall Software Environment 0 0000 eee eee 79 6 2 Peripheral Interfaces Configured to Plug in PC ISA Bus 80 6 3 Flow Chart for the Emulation Program 2 4 84 A 1 Magnitude Response of the Moving Average System N 11 90 ix LIST OF TABLES 4 1 The 16 Combi
5. Proceedings National Telecommunications Conferences 1978 pp 35 6 1 35 6 4 Dra 94 Draft Standard IEEE 802 11 YEEE 1994 Feh 95 Kamilo Feher Wireless Digital Communications Modulation amp Spread Spectrum Applications Prentice Hall Inc 1995 Got 71 Irving M Gottlieb Understanding Oscillators Howard W Sams amp Co Inc Indianapolis Indiana 1971 Hig 94 High Performance Microprocessor Development Tools IAR Systems Software Inc San Francisco California September 1994 Hay 94 Wes Hayward Introduction to Radio Frequency Design The American Radio Relay League Inc 1994 Hol 77 Jack K Holmes and Chang C Chen Acquisition Time Performance of PN Spread Spectrum Systems IEEE Transactions on Communications Vol Com 25 No 8 Au gust 1977 pp 778 784 88 References Hop 77 Phillip M Hopkins A Unified Analysis of Pseudo noise Synchronization by Envelope Correlation IEEE Transactions on Communications Vol Com 25 No 8 August 1977 pp 7 10 118 Jib 91 Waseem W S Jibrail and Abdul razak J Houmadi Acquisition of Direct Se quence Spread Spectrum Signals Using Sliding Correlators International Journal of Electronics Vol 71 No 5 1991 pp 733 743 Mat 92 MATLAB User s Guide for Unix Station The MathWorks Inc Natick Mas sachusetts August 1992 Rao 88 B V Rao and A A Deshpande Why the Barker Sequence bit length does not exceed thirteen Journal of
6. 00 98r Am seu 390027 49002 gt 001 8l 001 L zy E LARA C I Ory HNL nx dr 3t al aif e 00 00 00 Seo a O 4922 00 y bby e eva g 3 E d 490044 ESY o 9897 am 3 HNL Y cv ceu L Zo yen 4N 0 2 po oey IT EY ZHNOLI dg Iul Heg ES 081 2 09Sd To sol 00 00 aly gj 9H 40022 40007 T F LW Te 0 00 00 P 81 ou Ly gj S der 49002 614 98 HALY it for Tx Exciter Detailed Circu Figure 5 3 65 CHAPTER 5 RF HARDWARE DESIGN PN 80184 Nm id NL T Jdg9 HANG Z ndino eouenboJ i Jd007 44002 0 6 nano 2 6843 yg HO OPONI ocu y 20 90U9 9 98 ZHN fyl Me io HA Anjo e 5 SGH so HNL ego mus gad evo LAN ZED do dd0gi y zi 5 T 164 m BLISNE 18 e Hoes 869 vau Me ATT NU vi 1ndino eubis moo lt anio peje npo N wgp O m l dino jndui gt HAN YEO ZH 0 ME v cGy LEO N 00 00 6ry Sra lt 8l Lv NI Figure 5 4 Detailed Circuit for Tx Exciter 66 CHAPTER 5 RF HARDWARE DESIGN diode multiplier and filters to generate a 745 MHz local oscillator This signal is mixed with the 170 MHz modulated signal to generate the sum product for 915 MHz output Another possible solution for the up converter is to employ the
7. H31N32 i WAP TH 62 2H B HM ZHA BE Mg SIH ap gr 901 vdd 8p r ly wap PH 438 dy 9661 e ONY PS 8P dt Figure 5 10 Baseband Spread Signal TxI Spectrum 74 CHAPTER 5 RF HARDWARE DESIGN 385 FEE gM5 ZHA E MBA ZHA BE BL N dS nua snotAadd 330 NO ANAW Ld ST4UOJ 1104 Hd 440 NO 177 lt 17d voi 9d S1 ld Wap E8 8 2H f YAW 7HA BE ME SIH ZH H3lNdJ Haoa dd 28 ES YM wap gd gr VGA 338 an gr 90 3v 3d ap ge L S651 WAP gr 434 d De ONY FT Ge st Figure 5 11 Baseband Spread Signal Spectrum After Low pass Filter 75 CHAPTER 5 RF HARDWARE DESIGN NOOZ AV3d NYdS 18v NYdS OHuZ N dS TINA NCOZ NYdS asu pdoe JMS HN MBA ZHW gre NYdS ZHW E MO SJH 7HN O41 H31IN32 YH0J JH 38 dS VM ZHW OPE NYdS 8p r 507 v3d ap ge iY Wap gp 434 d 966 L ddS EB b Tc Figure 5 12 Colpitts Crystal Oscillator Output Spectrum 76 CHAPTER 5 RF HARDWARE DESIGN nua SNOT AI dg 440 NO DN3W 173 Brun 440d Vid 440 NO iP ver Jasu E dMS ZHW L NYdS ZH BL MOA ZHA MT ME Saye ZHA Ag Gir UIJLNSO
8. 4 4 Simulation of the Z2000 The purpose of this simulation is to verify our understanding of the operation of the 22000 and to predict the performance of the system Although the Z2000 is a digital processing device and a computer simulation seems to be easy not every function and its realization in this chip has been well documented and a software simulation is a convenient way to check our perception 49 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP 4 4 1 Simulation Techniques A simulation model based on MATLAB Mat 92 is described as shown in Figure 4 21 MATLAB was chosen due to its rich collection of functions Channel Noise Generator Random pl Transmitter Q Receiver Performance Data Gen Analysis Figure 4 21 Simulation Model of the 72000 Transmitter and the receiver are each partitioned into several functional blocks according to the operation of the Z2000 The signals are represented in complex envelope format and are sequentially processed from input to output The signal quantization process is performed before and after each stage of simulation with the quantization bit number set according to the specification of the 22000 4 4 2 The Simulation Model This simulation model is based on a baseband signal simulation We do not include the BPSK QPSK modulation and demodulation processes as the bandpass waveform can be sufficiently represented by
9. See Section 4 3 2 for how to choose the NCO frequency The NCO frequency is programmed in a 32 bit Frequency Control Register and is clocked by the receiver s clock signal RXIFCLK To avoid destructive aliasing the NCO frequency may not be programmed above 5096 of RXIFCLK Negative frequencies can be realized by the two s complement operation The formula for calculating this register value is given in Z20 94 4 3 Receiver The sampled and digitized received IF signal is first down converted to baseband and then PN despread with a PN matched filter symbol tracking processor incorporates a thresh old detector to detect a correlation peak once per symbol and a flywheel circuit to track the symbol The block diagram of the receiver is shown in Figure 4 8 Sampling Down Lowpass PN Matched Symbol Differential Process gt Converter Filter Filter Tracking Demodulation Figure 4 8 The 22000 Receiver 4 3 1 Sampling Process The analog IF signal is first converted to a digital IF signal by on board analog to digital converter ADC clocked at RXIFCLK The frequency of RXIFCLK is provided by an on board crystal oscillator with a maximum value of 45 056 MHz We use this maximum value in our application The sampling process introduces a spectrum image the fundamental and harmonics of the sampling frequency RXIFCLK result in images of the input signal spectr
10. PC gt ER DAC l gt UpConverter 4 re Host lt ADC le Down Converter um vo Y Y U Data Interface Baseband IF RF Figure 4 1 The Overall Transceiver System the 72000 chip and data buffering and packetizing for communications between the host and the Z2000 transceiver Figure 4 1 We will focus on the Z2000 chip in this chapter The 31 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP overall system hardware and software issues will be addressed in Chapter 5 and Chapter 6 respectively The transmitter in the 22000 chip incorporates a PN spreader and a DPSK modulator while the receiver integrates a digital down converter a PN matched filter despreader and a DPSK demodulator The block diagram is shown in Figure 4 2 The functionality of each block is programmable by the 280182 controller through the Z2000 control registers We will discuss each functional block of the 72000 in the following sections data Q splitter IF stream Differential XOR gt BPSK QPSK output Encoder I Baseband PN code Signal J Control Interface Generator Control command Frequency Frequency Numerically Discriminator Control Control Oscillator NU Out 1 Q Combiner E m Thres PN Matched Down digitized Differential lag Detector a Filte
11. for i 1 N pncod out chip rate i 1 1 chip rate i denco out i chip end clear denco out 7 1 o oo ooo Jo JoJo do do do da da a a a a a ado od oo do do do a a a a oo do JoJo do do do do o aa o lh BPSK Modulator with Sampling Process BPSPL The signal is generated in complex format 7 1 o o oo oo ooo JoJo do do da a a a a a a ad do od Jo do do do a a a ao oo JoJo do do o o o a l lh N fix length pncod out SampleNoPerChip bpspl out exp j pncod out fix O N 1 SampleNoPerChip 1 lt 0 pi clear pncod out 7 a a a a a a o o Do Do o o o o o o o a a a a a a a a a eee do oo do Do Jo le olo lolo olo o lo lo lo lo lo o a a a a a a a a 95 APPENDIX B SIMULATION APPROACH 4 Channel Noise Adder AGC CNAAA The noise is also in complex format with its variance calculated from Eb No hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh N length bpspl out cnaaa out bpspl out randn 1 N j randn 1 N sqrt Noi var hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh Matched Filter MAFLT hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh match_in cnaaa_out BitNo_Matchin 3 Quanlevel Matchin 2 BitNo Matchin match in round match in Quanlevel Matchin Quanlevel Matchin BitNo Matchout 10 Quanlevel Matchout 2 BitNo Matchout tap fliplr chip 4 reverse the chip N length match in fep out zeros 1 N preallocate the memory space front en
12. 4 11 show the BPSK and QPSK spectrum after the direct IF sampling To clearly show the I and Q channels spectrum in the same graph we use the different spectral heights to represent the I and Q channel s spectrum They must be the same height in the reality if the I and Q channels of a QPSK signal are balanced The phase is shown 38 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP Q o o BPSK QPSK Modulated Signal In gt LPF I Y Y Y out A D LPF Qu o 5 Set to Zero or Disabled A D Figure 4 10 The Operation of Direct IF Sampling by jm gt 0 freq Sampling Sampling Frequenc Frequenc q y in in q y Figure 4 11 Direct IF Sampling of a QPSK Signal As we observe from Figure 4 9 it does not matter for a BPSK signal which way the spectrum is moved by the complex NCO However if the signal is QPSK modulated an incorrect sign of the NCO will move a spectral inverted Q signal to the zero frequency This will cause a 180 phase inversion to the Q signal In this case the sign of the NCO frequency is determined by high side or low side conversion High side conversion means that an IF signal is down converted by a local oscillator whose frequency is higher than the signal center frequency As we see in Figure 4 12 a negative NCO frequency should 39 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP be applied
13. Ang is the angle of the signal and U is an unwrapped phase function modulo 360 operation This explanation will help us to understand the differential decoder process Actually the decoded output L Q can be found from its constellation whose angle value is calculated by Angldecoded out k U Ang in k Anglin k 1 4 5 4 2 2 PN Spreader As we said earlier the Z2000 uses symbol synchronous PN modulation in data transmission and reception This means that every data symbol I and Q symbols in QPSK mode coming out of the differential encoder is XOR ed with one complete PN code sequence Data from differential 1 0 1 m om encoder PN code generator 11100010010 11100010010 11100010010 ae 11100010010 00011101101 11100010010 Figure 4 6 The Operation of PN Modulation 35 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP Thus we see that the data rate is increased by the length of PN code and the spectrum is spread after PN modulation by the same number The Z2000 allows two independent PN codes to be employed one for preamble and another for information data Moreover the lengths of these two PN codes may be different However the length of both have an upper bound of 64 chips due to hardware limits and a lower limit of 10 chips because of the FCC Part 15 requirement of 10 dB minimum processing gain Preamble Data Data oon Pream
14. B This port is configured as a programmable I O for the RF interface In our application the program sends initialization data for the two frequency synthesizers in the transmitter and the receiver and an additional RF power control signal is sent through this port PORT C This port is multiplexed with ESCC channel A to provide serial data transfer 80 CHAPTER 6 SOFTWARE DEVELOPMENT control The transmit data are sent serially through the TxDA pin of Z80182 to TxIN pin of the 22000 and the data are received serially through the RxDA pin of the 280182 from RxOut pin of the Z2000 see Figure 6 2 ESCC channel A s signals control the transceiving of these data stream through this parallel port ESCC Channel A Multiplexed with Port C as described in the PORT C description ESCC Channel B control the ISA bus data parallel transfer in the ISA bus mode Oth erwise it controls the serial data transfer to and from the PC host through RS232 RS422 6 2 1 Z80182 and PC Interface The Z80182 communication peripheral is able to support an ISA bus or an RS232 RS422 interface performing the data exchange between the a PC host and the 280182 The software senses the two different hardware connections and the interface is configured accordingly In the ISA bus case Port A is connected to the ISA Data bus and is assigned as a parallel data port while the ISA control signal is connected to the Z80182 In the RS232 RS422 case the PC asynchronous COM port
15. In Chapter 4 we CHAPTER 1 INTRODUCTION investigate the operation of the 22000 Evaluation Board Mathematical representations of each functional block in the Z2000 spread spectrum burst processor are also provided A simulation of the 22000 was conducted and the results are shown In Chapter 5 we present the radio transmitter design Chapter 6 briefly describes the software interface between the MAC layer and the physical layer the control software for the spread spectrum processing and the radio transceiver Chapter 2 Spread Spectrum and Wireless LANs 2 1 Introduction Spread spectrum communication technology has been used extensively in a wide variety of military applications since the 1940 s because of its inherent military advantages im munity to intentional jamming interference the capability of hiding a spread signal from eavesdroppers security and high resolution ranging Sim 85 In the last decade the wire less communication market experienced significant growth especially in cellular telephony personal communications systems PCS and wireless local area networks WLANs In creasingly researchers have been interested in the issue of spread spectrum because of its potential technical advantages including higher spectrum utilization and resistance to mul tipath Currently spread spectrum techniques have been used in satellite communications position location systems and telemetry systems These techniques are also
16. MHz A dual frequency synthesizer is implemented in the receiver to generate two local oscillator frequencies one at 985 MHz and another at 90MHz The 20 MHz IF output is fed into the automatic gain control AGC circuit to generate the gain control signals for the four amplifiers which are located before and after the two mixers This AGC is adjusted such that the receiver outputs an IF level of 0 8 V p This output can be fed directly into the 22000 Evaluation Board in phase channel input for direct IF sampling For QPSK 62 CHAPTER 5 RF HARDWARE DESIGN modulation the 20 MHz modulated signal can be 90 split into two separate channels in phase and quadrature phase and then fed into two ADCs to perform the quadrature sampling The receiver output is a 20 MHz BPSK QPSK modulated spread signal with a band width of 4 MHz The receiver bandwidth puts an upper limit for the system PN chip rate which is 2 MHz chip sec Accordingly the maximum data rate is limited to 181 8 Kbits sec for an 11 bit PN code and 31 7 Kbits sec for a 63 bit PN code For QPSK modulation these data rates are doubled A 14 4 MHz Colpitts crystal oscillator with an output level adjustable in the range of 50 to 500 mv provides the reference frequency for both frequency synthesizers For each frequency synthesizer there is a serial programming bus connected to the 72000 port This bus is used to program the frequency synthesizer s registers which control the output fre
17. Motorola MC145190 145191 Fre quency Synthesizer Evaluation Kit The output frequency of this kit is controlled through three control lines Two of these are multiplexed with the frequency synthesizer in the receiver and the synthesizer is selected by its own enable signal The up converter mixer and filters work the same as the crystal up converter we described before The benefit of using the Frequency Synthesizer Evaluation Kit is that the frequency is adjustable so the RF spectrum can be moved in the ISM 902 928 MHz band All control signals are programmed by the Z2000 Evaluation Board The exciter routes the control signals and the power supplies from the Z2000 Evaluation Board to the Grayson receiver and the up converter in the transmitter 5 4 Circuit Designs 5 4 1 Colpitts Oscillator Design We use two oscillators in the RF module one operates with a 7th overtone 170 MHz crystal and another with a fundamental 14 4 MHz crystal The one operating at 170 MHz is shown in Figure 5 6 The AT cut crystal may be operated on odd mechanical overtones In this design we use a 7th overtone 170 MHz crystal operating in serial resonance At its serial resonance point the crystal has minimum impedance and can be replaced by a small value resistor It provides a path for the oscillator feedback loop Hay 94 However the reactance of the crystal s parallel holder capacitance is small enough compared to the resistor that it will shunt significant curren
18. OF THE ZILOG Z2000 CHIP We find in the graph Appendix A that the alias is attenuated more than 20 dB Theoretically we want to choose an IF frequency as high as possible compared to the sampling rate so that the undesired alias will appear far away from the zero frequency This allows the low pass filter to as much as possible eliminate the alias in the primary Nyquist region We also desire the sampling rate to be as high as possible compared to the incoming signal bandwidth in order to maximize the decimation ratio M and to increase filter attenuation Practically the sampling rate is limited by the highest operating frequency of the Z2000 Evaluation Board The signal bandwidth should be traded off with the IF center frequency to provide the minimum spectrum aliasing after the integrate and dump filter The signal aliasing distortion can not be eliminated or decreased by increasing signal power as the distortion is proportional to the signal strength and it can only be reduced by careful early system planning considering the system performance and capacity The output magnitude of the accumulation process depends on the number of samples accumulated in the sum operation which is determined by the decimation ratio M We show this in the following example In this project the analog input to the ADC is 0 8 Vpp with 1V DC bias voltage added by the 22000 Evaluation Board The reference voltage of the ADC is 2V unipolar positive operation with r
19. at receiver input is 1 N of that 13 CHAPTER 2 SPREAD SPECTRUM AND WIRELESS LANS of the system without the spreading The SNR at received baseband output remains the same regardless of whether or not the spreading despreading process is introduced Thus from the SNR point of view spread spectrum offers no better performance if the transmitted power is kept the same This phenomenon will be explained more clearly in terms of E No in the next chapter Resistance to narrow band interference is achieved by the processing gain This kind of interference may come from intentional jamming or from already existing narrow band systems At the receiver the desired spectrum is despread back to the information band width while the narrow band interference is spread to modulation bandwidth The PSD of the interference is reduced by the processing gain The following low pass filter has a cut off frequency which matches the information bandwidth thus only a fraction 1 N of interference power will reach the low pass filter output The larger the processing gain the more the resistance to interference 14 Chapter 3 Direct Sequence Spread Spectrum System Design 3 1 Variable Data Rate Transmission Technique In the overall spread spectrum system the baseband data d t is multiplied twice by the spreading despreading PN sequence c t Since c t 1 there is no effect on the re ceived despread output signal Thermal noise modeled as an add
20. baseband waveform samples If later on we need to study the quantization effect or other issues of the modulation and demodulation processes we can add these blocks to our simulation models Since the code is written in block format the integration will not take great effort as long as the input and output interfacing is matched The block diagram is shown in Figure 4 22 It is almost the same as the Z2000 internal block diagram except that the modulation and demodulation blocks are removed The more detailed descriptions of the simulation environment the realization of these blocks and also the commented code written in MATLAB are included in Appendix B 50 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP Random Data InputData Differential PN Code Generator Processor Encoder Spreading Y Performance Channel Analysis Noise Adder Y Differential Ly Symbol E Power PN Matched Decoder Tracking Detector Filter Figure 4 22 Simulation Block Diagram In the current stage of simulation we have not included a model for the frequency tracking loop Thus we assume that there is no phase offset between the transmitted and received baseband signal 4 4 3 Calculation of E N and Noise Variance The energy per bit j is calculated as the product of average signal power P and bit duration Ty As the channel signal is assumed to be a p
21. defined as 74 Let Pf denote the probability of false alarm the error made by the threshold detector due to noise We assume that the following verification mode will detect the false alarm with probability of 1 and that the penalty time of false alarm is kr4 where k is an integer The elapsed time between test cells is now 74 if no false alarm happens with probability of 1 Pr and k 1 4 when false alarm happens with probability of Pr Thus the average time spent per test is To Ta 1 Pi k 1 rtaPs kPt Da 3 13 Secondly we consider the missed detection probability Let q denote the total number of search cells and P4 the probability of detecting correct phase position If a missed detection happens another q tests should follow before the next possible correct detect If we assume the time uncertainty region is uniformly distributed from 0 to q 1 with the mean value of ER ene T i then the average acquisition time Taq becomes Es 1 gt Tag y To dTo 1 Pa Pa 2qTo 1 Pa Pa 3qT o 1 Pa Pa Iq A oo iT qT Pa Y k 1 P3 k 1 23 CHAPTER 3 DIRECT SEQUENCE SPREAD SPECTRUM SYSTEM DESIGN q 1 gt 1 Pi AN T 9 2 ot dio Pa 2 P T qlo 14 Toe gt 2 3 14 If q is a large integer then 2 Pas acq dop 2 2 Pa 2P4 NI q kPf 1 Ta 3 15 Basically the difference in acquisition time between a sliding correlator and
22. fading is obtained from the pseudo random property of spread ing code The receiver for a spread spectrum signal is designed to despread the received spread signal with the desired PN code sequence From propagation theory we know that the receiver will receive time shifted signals via several paths The sum of these time shifted signals is the input to the correlation operation with the locally generated PN code As discussed before the autocorrelation function of the PN code is impulsive Therefore the correlation with the time shifted multipath components will be approximately zero as long as the time delays of multipath components are greater than one chip duration At the out put of the despreader we see only the correlation of transmitted data sequence with itself and the correlation with additive white Gaussian noise AWGN Practically the autocor relation is not identically zero and there will still be some multipath interference but it is 12 CHAPTER 2 SPREAD SPECTRUM AND WIRELESS LANS greatly attenuated When the bandwidth of transmitted signal is increased the chip dura tion becomes correspondingly smaller and more multipaths can be resolved Anti multipath capability is a significant advantage when we realize that the propagation in wireless LAN environment is strongly affected by the construction materials and the building type espe cially when the transmitter and receiver operate in an obstructed channel Rap 95 Let us
23. is connected to ESCC Chan nel B and data is transfered in serial format through the connection The Channel B is configured to handle the interfacing and the data transfer It works as a serial to parallel parallel to serial converter and controller with data transfer rates up to 115 2 Kbps for RS232 and 4 Mbps for RS422 In our application we use the ISA bus to communicate with the PC Although the Zilog provided emulation program has the capability of using RS232 RS422 our control program only focuses on the ISA bus case because it supports a higher data rate The ISA bus and the Z80182 provides a communication path to and from the PC Based on this the Z80182 AT command set processor and debug monitor can accept and interpret user commands from the PC Control can be handed off between the AT command set processor and the debug monitor by special commands specified in the Z2000 user manual 220 94 A more detailed description of each command is also in the manual Here we will only discuss how to load the control program to RAM space 8l CHAPTER 6 SOFTWARE DEVELOPMENT Loading the control program requires that the Zilog terminal emulator program tz exe be running on the PC host Using the load command L tz will download the specified file into RAM The file must be in Intel Hex format Z20 94 After the code is loaded into RAM space it can be executed using the go command with starting address This starting address is determ
24. look at the model of the spread spectrum receiver in Figure 2 7 and study the signal to noise ratio SNR performance of the system NS Baseband information BandPass DownConverter Despreading LowPass dat A Filter 8 Demodulator B Filter C ata Figure 2 7 The Model of Spread Spectrum Receiver Assume that the noise at the antenna input is thermal noise only The definition of SNR is the received power divided by the white noise power which is contained in a bandwidth equal to the signal bandwidth Cou 90 The processing gain is defined as the ratio to the SNR out of the low pass filter divided by the SNR into the despreading process SNR at C Ng _ SNR at B No Ne 2B N Ne 2NB 2 N 2 4 processing gain where Np is the noise power at B and No is the noise power at C As the signal bandwidth at A is the same as that at B 2N B the processing gain can also be the SNR at C divided by SNR at A We know from Section 2 2 1 that the spreading process reduces the power spectral density PSD of transmitted signal by N at the price of occupying N times more bandwidth If the PSD is sufficiently low it is possible for the spread spectrum signal to be transmitted along with other narrow band systems without greatly interfering with them However as the bandwidth of the bandpass filter of Figure 2 7 is N times wider than the non spread signal and when the signal power remains the same the SNR
25. o a ado do AAA DOS This program first generates the spread spectrum signal The noise is added to each baseband sample The quantization operation is performed before and after each functional block The flywheel strategy is applied in the symbol tracking block 7 o do ooo ooo lee da a da a a JJ od lodo JoJo do do do do doa a ad ooo o JoJo do Jo a a la dedehedololololololele SII do ooo oo e do do do da da a a a a JJ od lodo JoJo do do do do doa lbh ooo JoJo JoJo Jo a a la la la a la ooo fofo lodo clear clear the memory space Iter No 2 Repeat the simulation data No 10000 The data number for each simulation for EBNO ITER 1 1 EbNo dB 8 Eb No in dB EbNo 10 EbNo dB 10 Eb No barker 11 11100010010 PN code 93 APPENDIX B SIMULATION APPROACH SampleNoPerChip 2 Two samples per chip chip barker 11 2 1 PN code in polar format chip rate length chip 4 PN code length Noi var SampleNoPerChip 2 chip rate EbNo Calculate the channel noise variance Throughput zeros 1 Iter No storing the number of the correct received data for Iter 1 Iter No begin the simulation MISI Jd dd Jd df ooo a a a a a a a a oa do oo do do oo fo da a a a a ao o Jo do ooo fo fa o a alo o ad ORIGINAL DATA GENERATOR 7 1 o ooo ooo JoJo Jo do do da a a a a a a ado od oo do do do a a a a do do JoJo do do do do o aa o lh rand seed sum 100 clock set the seed of
26. stream The ESCC interface then manages the transmission of this bit stream to the 22000 spread spectrum 78 CHAPTER 6 SOFTWARE DEVELOPMENT processor and to the RF section for on air transmission Note that it is the MAC layer s responsibility to detect the communication channel s activity When the MAC layer sends data to the physical layer there is no delay in physical transmission The buffer is designed to eliminate the data rate difference between receiving and transmitting In the receiver direction the received RF signal is first down converted despread and the data are then sent back to 280182 The bit stream is retrieved by the ESCC channel converted from a serial to a parallel bit stream and stored in the receiver buffer RxBuffer Z80182 handles the parallel transfer of the data to the ISA bus for the PC host The data transfer between PC host and Z2000 is fully managed by the Z80182 s communication peripherals The control program is written to configure all the necessary communication interfaces by setting the control registers and coordinating the internal micro controller system to make it work for a high speed wireless communication system There is additional control for the RF section to perform the RF module configuration Serial Bit Stream IF Signal i and Control Z 2000 Evaluation Board
27. synchronization has been achieved The integration period here is a key parameter for which each system design must trade off based on its peculiar performance requirements A short integration period integration results in a low probability of detecting the in phase signal Py and a high probability of false alarm detections Py A long integration period on the other hand improves the reliability of a correct decision but the time taken to dismiss each out of phase conditions is longer and consequently the mean acquisition time is longer 3 2 3 PN Matched Filter A matched filter is a linear filter which maximizes the output signal to noise ratio given 19 CHAPTER 3 DIRECT SEQUENCE SPREAD SPECTRUM SYSTEM DESIGN local PN code c t received Integrate and mi signal p t gt Dump Filter k r t c t dt Figure 3 3 A Sliding Correlator matched filter J y t x t h t x t h x T t z Figure 3 4 A Matched Filter an input signal waveform Cou 90 When the input noise is white Gaussian the impulse response of the matched filter becomes h t x T t 3 6 where x t is the input signal with interval from 0 to T The output of the matched filter is given by t t y 200 eh f s ht Ddr emer t nd 37 0 0 It can be shown that y t is the autocorrelation function of zx t y t reaches its peak value when it is sampled at time t T y T EU
28. the Institution of Electronics and Telecommunication Engineers v 34 n 6 Nov Dec 1988 pp 461 462 Rap 84 Stephen S Rappaport and Donald M Grieco Spread Spectrum Signal Acquisi tion Methods and Technology IEEE Communications Magazine Vol 22 No 6 1984 Rap 95 Theodore S Rappaport Wireless Communications Principles and Practice IEEE Press and Prentice Hall 1995 Rar 83 Benjamin Rarzen Design of Crystal and Other Harmonic Oscillators John Wiley amp Sons Inc 1983 Pol 84 A Polydoros and C L Weber A Unified approach to serial search spread spectrum code acquisition Part 1 General Theory IEEE Transactions on Commu nications Vol Com 32 No 5 May 1984 Sim 85 M K Simon et al Spread Spectrum Communication Computer Science Press 1985 The 94 The Spread Spectrum Handbook Third Edition Standford Telecommunications Inc September 1994 Yan 95 Desmond Yan and Paul Ho Code Acquisition in a CDMA System based on Barker Sequence and Differential Detection IEEE International Symposium on Per sonal Indoor and Mobile Radio Communication PIMRC v 1 1995 pp 233 236 218 94 Z180 Family Microprocessors and Peripherals Data Book Zilog Inc Cambell California 1994 220 94 Z2000 Spread Spectrum Development Kit User s Manual Zilog Inc Cambell California 1994 89 Appendix A Moving Average System Ebene b
29. was designed to study the quantization effect of this digital pro cessing chip The quantization is realized in simulation by truncating or rounding the value to its closest quantization level The number of the quantization levels is determined by the bit number of each signal in the Z2000 The biggest quantization effect is thought to be from quantizing the PN matched filter input signal which is rounded to 3 bits in the chip The same number of data bits and iterations were carried out as in the first series of simulations Figure 4 24 shows this simulation result Interestingly the resulting BER performance is also close to the theoretical one T his means that the quantization effect can be ignored based on the current simulation model One explanation is that white Gaussian noise even at E N equal to 9 dB is much greater than the quantization noise so that the quantization noise can be neglected A third simulation was done to study the performance of the symbol tracking scheme suggested by Zilog T he simulation is carried out without quantization and the flywheel tracking strategy is applied in the symbol tracking block The number of data bits and iterations are the same as before As we know the flywheel strategy is based on the knowledge of a previous correct detection While the Zilog data sheet does not have a description of how the acquisition is performed we assume an ideal situation where the first detection always happens at the corr
30. 1 Sampling Procesos sats HET SRG a hea ee b gt 37 43 20 Down Converter its Gert E ude A ug tu Gas 38 4 3 3 Low Pass Filter oem Se Ros m RR RE RR ende 41 4 3 4 PN Matched Filter 4 2 24 ba ooo Ro y 45 4 8 5 Differential Decoder llle 47 4 4 Simulation of the 22000 tesi pi 2A 49 4 4 1 Simulation Techniques 2e 50 4 4 2 The Simulation Model ear rv rv rv rn rn kran 50 4 4 3 Calculation of E N and Noise Variance 51 4 4 4 Simulation Results and Analysis rns 52 4 4 5 Future Work lees 56 5 RF Hardware Design 61 5 1 RF Module Description 002020 eee ee ee 61 5 2 Power Consideration in the Transmitter Modules srt mad tr a codem Uus hys 63 5 83 Hardware Interface assis pon e a ux rae LESS YR on uds dg 64 CONTENTS 54 Circuit Designs s Aa N tia a usb de 67 5 4 1 Colpitts Oscillator Design o e 67 5 4 2 Amplifier Design 22r 71 5 5 Experimental Results e 72 6 Software Development 78 6 1 Physical Layer Control Program Description 78 6 2 Peripheral Interfaces 222r 80 6 2 1 Z80182 and PC Interface o e rn rn nrk 81 6 2 3 280182 and Z2000 Interface L rar rv rn rn ea 82 6 2 3 RF Control Interface 82 6 3 The Emulation Program s Flow Chart len 83 6 4 Fiture Work corte car ek a AR bcne demo es ea a 83 7 Conclusions 86 A Moving Av
31. 2 2 Principles of Spread Spectrum rv rv kr rn ee 2 2 1 Spread Spectrum and the PN Code o 2 2 2 Two Widely Used Spread Spectrum Systems 2 2 3 Synchronization Requirement in the Spread Spectrum System 2 3 Wireless LAN using Direct Sequence Spread Spectrum 2 3 1 Wireless LAN Systems vr rv vr kr a 2 3 2 The Benefits of Using Direct Sequence Spread PECUARIA heady rs 3 Direct Sequence Spread Spectrum System Design 3 1 Variable Data Rate Transmission Technique 3 2 PN Despread Techniques 22e 3 2 1 Symbol Acquisition and its Impact on System Performance s sk vag eX edt euni fam RE Ee 3 2 2 Sliding Correlator ema saa eR GAS EG AE lede EE 3 23 PN Matched Filter 222r 3 2 4 Mean Acquisition Time Analysis lll QOQ gt A O Q 10 10 12 CONTENTS 3 8 Spreading Code Design 22e 25 3 3 1 The Despreading Process and Partial Correlation 25 3 3 2 M Sequences and Barker Codes 2 arv vr rv rv vr 26 3 3 3 Correlation Function Comparison 2 aa vr e kr nrk 27 4 Operation of the Zilog Z2000 Chip 31 AL OVeEVIEW vag sd xr 31 42 Transmitters 3 Logs ioc eG Ens SSG om Mb op NITE an E S ket 32 4 2 1 Differential Encoder rv rv rv a 33 4 22 PN Spreader uode a a a A Sonet Ne a 35 123 BPSK QPSK Modulator cau T dox uso pe 36 4 3 e Receiver puss dd Ma ee oe LS Peces rego aa s ets 37 4 3
32. Bm output at 170 MHz 11dB Colpitts 2 dBm 92 dBm 9dBm Power gt cosine 5 dBm Oscilator gt Am ado gt Splitter sine 5dBm Figure 5 2 Functional Blocks of the Transmitter Module the carrier power is above 9 dBm and is fed into PSCQ 2 180 for 90 power splitting This PSCQ 2 180 introduces 4 dB insertion loss The two outputs a 5 dBm cosine and sine signal drive the balanced modulator SBL 1 which has a 3 5 dB conversion loss when the LO input power level is 5dBm and the frequency is 170 MHz The RF port of SBL 1 outputs a 8 dBm signal After a 3 dB resistive attenuator the I and Q channel signals are combined in the PSC 2 1 combiner The combiner output is approximately 11 dBm as the combiner s insertion loss is below 0 5 dB Another SBL 1 device serves as a current controlled attenuator Through this variable attenuator and the following two amplifiers the signal power level is adjusted and amplified to 0 dBm at 170 MHz 5 3 Hardware Interface The hardware interface is shown in Figure 5 5 The Transmit Exciter outputs BPSK QPSK signal at 170 MHz as described in the last section At the current stage of this project an crystal controlled up converter is used to translate the 170 MHz spectrum to 915 MHz This crystal up converter employs a crystal oscillator operating at 93 125 MHz and a x8 64 RF HARDWARE DESIGN CHAPTER 5 sjejeureig 9L E SUN p MTS r 01
33. Clock signal The timing requirements for these three input signals and the method of calculating the control register words are detailed in the data sheet of each frequency synthesizer program written in C and compiled by the IAR compiler Hig 94 to perform the above frequency control operations is attached in the 82 CHAPTER 6 SOFTWARE DEVELOPMENT Appendix If another RF section is required this program should be modified to output other control signals using other pins of Port B Also this program should eventually be integrated into the initialization portion of the overall physical layer control program 6 3 The Emulation Program s Flow Chart The flow chart for the emulation program is shown in Figure 6 3 In the Intro function the emulation program first checks the status of the ESCC Control Read registers and assigns the communication control to and from the PC host The Reset function disables the Z2000 s transmitter and receiver It then clears copies of the 22000 registers in RAM space and finally sets all of the ESCC channel Write Registers to zero The ESCC initialization function Init configures its 15 Write Registers to the Syn chronous Data Link Control SDLC protocol and then enables the ESCC Also it sets the Z2000 s registers for normal BPSK operation The transmitter and receiver s buffer space is then allocated in the RAM space The transmitter buffer s content is set according to the user s selectio
34. DIX B SIMULATION APPROACH symtk out zeros 1 N preallocate the memory space flywheel zeros 1 N preallocate the memory space flywheel 1 22 first one is correctly detected Ha_win 1 specify the window size fori 2 N flywheel i flywheel i 1 2 chip rate A powde_10 flywheel i Ha_win flywheel i Ha_win max A max A B find A max A if max A THRESHOLD flywheel i flywheel i B 1 2 end end symtk out maflt 8 flywheel clear powde 10 maflt 8 TJ JJ IIIS fo o a a a a a a a a a a ao o o oo do Vo AAA Differential Demodu DDEMO ASSI IS Idee lll JoJo do do do do da a a a a a ado do oo do do do do do do aa ooo lodo N length symtk out test zeros 1 N 1 preallocate the memory space Calculate the dot product for decision circuit test symtk out 1 N 1 conj symtk out 2 N data out test lt 0 differential decoder s decision 4 calculate the throughput for this simulation Throughput Iter sum data in 1 data No data out 1 data No 98 APPENDIX B SIMULATION APPROACH 4 calculate the BER of this simulation ber EBNO ITER Iter 1 Throughput Iter data No end end of one simulation BER EBNO_ITER 1 sum Throughput data No Iter No end end of the total iterations of simulations 99 Appendix C Modifications to the IAR Compiler e In the iar iccz80 getchar c file 1 add an include file for bo
35. IGN should be tuned to the frequency just below the overtone Rar 83 The 14 4 MHz crystal oscillator operates similarly except that a fundamental crystal is used Figure 5 4 Let us consider the Colpitts LC oscillator We assume that the crystal is short circuited 12V e e o E aa 2N5179 7 01 UF 0 Ol NANA Y E L 10p a nM s _ OtuF 2 l5pf pan Y D O1uF T 23 6k L15p 170MHz 510 e e e 4 turns 3 16 Diameter Figure 5 6 Colpitts Crystal Oscillator The Colpitts LC oscillator can be equivalent to an emitter follower and a capacitive divider coupling network Got 71 Figure 5 7 o WNW 1 R d Re C i Figure 5 7 The AC Equivalent Colpitts Oscillator The oscillator load impedance is approximately Re The another equivalent circuit with 69 CHAPTER 5 RF HARDWARE DESIGN an ideal transformer is shown in Figure 5 8 el Ic n Re NAN A NC COME NCON H Figure 5 8 Another Equivalent Circuit Here the transistor is replaced by amplifier A and the turns ratio of the ideal transformer is given by C1 0 5 1 n 55 51 C is the serial capacitance of C1 and Ca C1 Ca 5 2 Ci 0 2 L and C together contribute to the parallel resonance of this network thus L is given by 1 f mo 5 3 I ET 5 4 Gers p Usually in this crystal controlled oscillator we design the LC net
36. M I A 3 8 The impulse response of this filter is said to match the signal x t A transversal digital matched filter is usually used for PN despreading in a spread spec trum system The structure of this transversal digital matched filter is shown in Figure 3 5 20 CHAPTER 3 DIRECT SEQUENCE SPREAD SPECTRUM SYSTEM DESIGN Delay T ay Figure 3 5 A Transversal Matched Filter The set of transversal matched filter coefficients a ay az az an are found in Cou 90 to be acd s 3 9 where s is the known signal vector s s1 s2 53 sw and R is the known autocorrelation matrix for the input noise T11 T12 Dee TAN T21 T22 is TIN R TN1 TN2 TNN If we assume that the input noise is white Gaussian noise then We DU 3 10 Tmn j 00 m n where og is the noise power Thus 21 CHAPTER 3 DIRECT SEQUENCE SPREAD SPECTRUM SYSTEM DESIGN R o diag N 3 11 and i a R s 03 diag N s 09 diag N s og s 3 12 Therefore if the transversal matched filter s coefficient vector is proportional to the incoming signal vector the instantaneous output signal to noise ratio is maximized In practice og affects only the gain of the transversal filter and a is simply set to be s The PN matched filter based on this derivation of transversal matched filter is depicted in Figu
37. On another hand the low side conversion should use an NCO with positive frequency If the opposite sign is chosen the Z2000 provides a second chance to recover the inverted Q channel signal in the Output Control Processor As we know in a QPSK signal the I channel leads the Q channel by 90 The inverted Q channel spectrum introduces an inversion to the Q channel and this can be corrected by reversing the output sequence to Q first followed by I This sequence reversing operation can be accomplished by a setting on the Output Processor Control Register Q jn A 0 freq Q jm in ix x Q 1 Qj QA V LAN VIA f freq Q Q Sampling i p Frequency jy eue jm jm Dr NCO 0 freq A negativ NCO move the spectrum to the left Aix jn NG T i 0 req Sampling i Frequency Q Ideal Q peque Lowpass JT Filter JT Figure 4 12 High Conversion With Direct IF Sampling In quadrature sampling mode two ADCs are used simultaneously Figure 4 13 shows the operation of the quadrature sampling method Equation 4 6 shows the mathematical formula for this down conversion operation 40 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP gt o gt lout m gt A D QPSK 69 Modulated 90 Phase 4 Signal Splitter gt AD gt Qu sin Figure 4 13 The Operation of Quadrature Sampling Lin Qi
38. Physical Layer Design for a Spread Spectrum Wireless LAN by Guoliang Li Thesis submitted to the faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING APPROVED Dennis G Sweeney Chairman Scott F Midkiff Brian D Woerner September 12 1996 Blacksburg Virginia Keywords Wireless LAN Spread Spectrum Radio transceiver PN code Physical Layer Design for a Spread Spectrum Wireless LAN by Guoliang Li Committee Chairman Dennis G Sweeney Bradley Department of Electrical Engineering ABSTRACT A wireless local area network LAN system is proposed to provide mobility for exist ing data communication services This thesis presents a physical layer design for a direct sequence spread spectrum ISM band radio LAN system This radio system employs spread spectrum communication technology and a differential binary phase shift keying quadrature phase shift keying BPSK QPSK non coherent receiver to overcome the adverse indoor wireless environment Moreover a variable data rate transmission technique is used to dy namically configure the spread spectrum system according to channel performance This physical layer incorporates the Zilog 22000 Evaluation Board performing direct sequence spread spectrum processing a Grayson 900 MHz radio receiver and a transmitter module which was designed and built at Virginia
39. Tech The transmitted spectrum occupies a 4 MHz bandwidth in the 900 MHz ISM band and this system supports a data rate of up to 363 Kbits sec The spread spectrum system design along with detailed descriptions of hardware and control software development are presented ACKNOWLEDGEMENTS I would like to express my deep appreciation to my advisor Professor Dennis G Sweeney for his introducing me to spread spectrum communications and hardware design Without his guidance suggestions and encouragement I could not have completed this work I am also very grateful for his patience in correcting and commenting on my thesis My sincere thanks also go to my committee members Professor Scott F Midkiff and Professor Brian D Woerner for their ideas suggestions on my work and their comments on this thesis I want to thank Barry Mullins for his terminal program support and also Todd Fleming for their advice on the software development It is also a pleasure to acknowledge Gunadi Gunawan who sponsored me for further study in United States and has always encouraged me during these past two years I would also like to thank MingZhi Yao for her spiritual support from the beginning of this research work Finally I wish to thank my parents and my brothers for their understanding encour agement and love during my life iii TABLE OF CONTENTS 1 Introduction 2 Spread Spectrum and Wireless LANs 25E Introduehons A mme Lese maso e aros Eo ee ed
40. a PN matched filter is the dwell time 74 In the PN matched filter 7 is half chip duration while in the sliding correlator 7 is a multiple of the chip duration 10 to 100 ensuring that the decision is based on enough received information The minimum integration period depends solely on the length of the PN sequence used Dav 78 shows that the minimum value must be n for maximum length code with code length 2 1 For non maximum length code operation with a short code length the integration period is typically chosen to be the whole code length As we see the PN matched filter has a short acquisition time compared to the sliding correlator The presence of data modulation frequency offsets and Doppler effect place a lower limit on the integration period and the sliding correlator is better in the low signal to noise ratio situation as a longer correlation period can be used In this project we chose the Zilog Z2000 chip Adv 94 see Chapter 4 for direct sequence spread spectrum processing transversal PN matched filter is incorporated in this chip to perform the preamble and data despreading As its mean acquisition time is much smaller than that of the sliding correlator the PN matched filter satisfies the fast acquisition requirement of our wireless LAN application 24 CHAPTER 3 DIRECT SEQUENCE SPREAD SPECTRUM SYSTEM DESIGN 3 3 Spreading Code Design 3 3 1 The Despreading Process and Partial Correlation In wireless LAN
41. a step size of 1 dB White Gaussian noise is added to the each baseband sample with a noise variance calculated by Equation 4 20 T he 11 bit Barker code is applied to each simulation In the first simulation the quantization processes were removed before and after each simulation block and the symbol tracking process suggested by Zilog was disabled The symbol output is the power detector output value when the local PN code and received PN code is aligned In other words detections happen at the symbol boundaries For each simulation 5000 data bits for E N below or equal 7 dB and 10000 data bits for E No above 7 dB to improve the simulation accuracy when the BER is considerably small are generated by the random data generator This whole process iterates 10 times for each 52 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP 4 E 0 2 4 6 8 Eb No dB Figure 4 23 Theoretical BER Performance of Non coherent DPSK 53 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP Ey N value and the BER is averaged over these 10 iterations Figure 4 24 shows this result Careful observation shows that the BER performance is close to the theoretical one Moreover if we reverse the channel signal s polarity the BER performance remains the same because the DPSK demodulation operation is not affected by any constant phase shift to the received signal All these results imply that the simulation model is created correctly A second simulation
42. ampling Figure 4 15 Integrate and Dump Filter The low pass function in this filter is implemented by a moving average system Fig ure 4 15 which can be characterized by the impulse response h n as follows M M y n 5 z n k z n x 5 n k z n h n 4 7 k 1 k 1 where M h n M n k 4 8 k 1 H e Flh m h n ef di M l ede d edu M y e juk a ET k 1 42 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP Ww w eie il A quM LIE e 3 el e 2 AM _ jj SM bd i sin oo 2 A plot of the magnitude response of the moving average system with M 11 is shown in Figure 4 16 as an example As we see H e is periodic with a normalized period of 27 as the sampling process in the discrete time system introduces the spectrum aliasing A logl H el L t I gt 27 27 11 Figure 4 16 The Magnitude Response of the Moving Average System In our application the receiver outputs a BPSK QPSK modulated signal centered at 20 MHz with a bandwidth of 4 MHz As the PN matched filter requires two samples per chip the decimation ratio is given by sample rate 45 056 M Hz M 11 4 10 2x single side bandwidth 2x2MHz The undesired spectrum is 20MHz away from the zero frequency and its frequency normalized by sampling rate RXIFCLK of 45 056MHz is 20M Hz A 0 44 4 11 45 056M Hz 43 CHAPTER 4 OPERATION
43. ange from 0 to 2V and the ADC uses two s complement representation Thus the maximum digital output of the ADC is ogy x 128 LRL 51 LRL where LRL stands for lowest resolvable signal level after the quantization Now the digitized signal is multiplied by 128 LRL NCO signal summed over 11 samples and then divided by 256 the 8 least significant bits are discarded The peak magnitude of the output from the integrate and dump filter is given by 51 LRL x 128 x 11 256 280 LRL 4 12 The PN matched filter allows only a 3 bit offset two s complement word with an effective range of 43 5 LRL from 3 5 LRL to 3 5 LRL The output must be scaled for the PN matched filter In the Z2000 this is referred to as a viewport and it is effectively a gain 44 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP controller The viewport should be set to 07 then the PN matched filter input is given by 280 or 5 22LRL lt 3 5 LRL 4 13 4 3 4 PN Matched Filter The PN matched filter is designed to operate with two signal samples per chip to allow the system to sample the incoming signal asynchronously with respect to the PN spread rate This requires that the integrate and dump filter output rate must be twice the PN chip rate Also to avoid spectrum aliasing the output rate of the integrate and dump filter must be less than or equal to one half the frequency of RXIFCLK The number of samples summed by the integrate a
44. annel deterioration 2 When the channel is clear we use a short PN code and increase the data transmission rate to increase the throughput By dynamically changing the transmission rate according to the channel performance we have the following benefits 1 A disconnected link is less likely to occur and data transmission remains continuous but perhaps at a lower rate 2 The channel transmission capacity is fully used in both the bad channel and good channel cases The theory that longer PN codes have a better BER performance for a given chip rate leads to the second application in our system We may use a long PN code for the preamble and a short one for the information data Thus by this assignment we improve the burst acquisition reliability and consequently increase the packet throughput or overall data throughput of the system 17 CHAPTER 3 DIRECT SEQUENCE SPREAD SPECTRUM SYSTEM DESIGN The variable data rate transmission technique is useful in the wireless environment as the physical channel is always impacted by the movement of transceivers from one location to another by a changing physical environment or by interference from outside signals From the above discussion we obtain the formula for calculating the channel data rate as follows channel data rate PN chip rate PN code length BPSK 3 4 channel data rate 2 x PN chip rate PN code length QPSK 3 5 3 2 PN Despread Techniques 3 2 1 Symbo
45. applications data transmission is bursty and the receiver is not synchro nized to the other transmitters when they are not transmitting This means that the local PN code generator has no information about when the signal comes Therefore code acqui sition is needed at the receiver each time a burst arrives otherwise the PN code despreader will not have the timing information to correctly despread the signal At least one preamble symbol is required precede the information symbols After the receiver detects this pream ble symbol acquisition it generates the exact timing signal based on the PN chip rate for the PN despreader to extract the information symbols Let us study the general model of the despreading operation as shown in Figure 3 7 Spread Q gt E Decision making Signal 0 Circuit Local PN code Generator Figure 3 7 A General Model of Despreading Process As mentioned before the receiver has to detect the preamble symbol but before the whole preamble PN code has been received and shifted chip by chip into the PN despreader there is only a partial overlap between the received and the local PN code This is called the partial correlation which results in a noisy input for the decision circuit of the acquisition process Yan 95 Thus we want this partial correlation of preamble PN code to be as small as possible compared to its the autocorrelation peak Moreover this partial correlation is p
46. area From August 1995 to January 1996 he worked as a co op design engineer in the Personal Com munications System PCS Department at Bell Northern Research now Nortel Research in Richardson Texas From February 1996 to August 1996 he was a research assistant in the Center for Wireless Telecommunications at Virginia Tech His Master research focused on the physical layer design for a spread spectrum wireless LAN 104
47. ble PN code Data PN Code Data PN Code Figure 4 7 The Alignment of PN Code with Preamble and Information Data It is suggested that a longer PN code be used for the preamble This takes advantage of the higher processing gain and it will improve burst acquisition performance The lengths and their coefficients of both PN codes are programmed by Z80182 control registers 4 2 3 BPSK QPSK Modulator The BPSK QPSK modulator implemented in the Z2000 is a fully digital modulator The spread signal is translated to a digitized immediate frequency IF modulated signal by multiplying it with a digitized discrete and quantized sine and or cosine waveform from the numerically controlled oscillator NCO This output signal is then fed into an external digital to analog converter DAC and the analog output can be up converted to RF for transmission in the radio channel The NCO output is also used in the Z2000 receiver to translate the received IF to baseband If the receiver s IF is chosen to be different than the transmitter s IF then an external BPSK QPSK modulator for the transmitter is required It uses the PN spread signal I and or Q channel from the PN spreader directly and an analog carrier signal as its two inputs This is shown in detail in Chapter 5 With an 36 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP external modulator the NCO frequency can be chosen by only considering the operation of the receiver
48. ch the wireless LANs operate is usually ad verse the transmitted signal is distorted by multipath fading collapsed with thermal noise or interfered by other signals This distorted signal may cause the receiver to make incorrect decisions declaring an acquisition while missing the correct position or just missing the detection In both cases the packet will be declared lost by the receiver after a time out period and the transmitter has to retransmit the packet while other users have to wait Such packet loss will not only decrease the overall system throughput but will also increase the mean transmission time of packet and hence a longer delay can be expected Thus mean acquisition time detection probability and false alarm probability are im portant criteria for analyzing the performances of PN matched filters and sliding correlators 3 2 2 Sliding Correlator Figure 3 3 shows a sliding correlator The operation of this correlator is as follows The signal after the multiplication operation is simply integrated over a fixed period of time the integration period At the end of this time period a threshold detector is used to decide whether the correlator output signal corresponds to an in phase condition or out of phase condition and hence whether or not initial synchronization can be declared If the threshold is not exceeded the locally generated PN code is delayed by half of a chip period and this process repeats until an initial
49. cordingly There are only a few sets of parameters and thus it is much easier for the control program to manage The emulation program only deals with transceiving data from and to the buffer Our next step should be to program the Z80182 to receive send the data from to the PC ISA bus This portion is critical because of the high data rate and the complexity of interface control Finally the RF section control program should be integrated into the initialization portion of the overall control program 85 Chapter 7 Conclusions A physical layer design for an ISM band direct sequence spread spectrum wireless LAN is presented This physical layer directly interfaces with the MAC layer and uses the 902 928 MHz ISM band for the RF transmission The Zilog Z2000 Evaluation Board is implemented for the spread spectrum processing The RF module consists of the Grayson receiver module and our transmitter Chapter 2 introduces the concepts of the spread spectrum technology and wireless LAN systems The operations of two widely used spread spectrum systems direct sequence and frequency hopping systems and the acquisition issue are briefly addressed Several wireless LAN systems and the transmission technologies that wireless LAN employs are discussed Finally the interface between the physical layer and the MAC layer are defined In Chapter 3 we first present the variable data rate transmission technique and then we investigate how the despreadin
50. d processor average the matched filter input fep out 1 match in 1 fep out 2 N match in 2 N match in 1 N 1 2 match zeros 1 N preallocate the memory space for i 1 N k fix 1 2 1 if k gt chip_rate k chip_rate decide if this is only partial overlay 96 APPENDIX B SIMULATION APPROACH end match i sum tap 1 k fep out i 2 i 2 k 2 end Quantized the matched filter output to 10 bits match out fix match Quanlevel Matchout Quanlevel Matchout clear match match in fep out cnaaa out dncov out bpspl out 71 1 o ooo JoJo Jo JoJo do do do da da a a a a ao Jd od JoJo do do do do do o aa oo oo lodo Power Detector POWDE IA RARA AA AAA df fo oo a a a a a a a a a a a o ooo do Vo fa a a a AS BitNo Viewport 8 Quanlevel VP 2 BitNo Viewport BitNo Magnitude 10 Quanlevel Magnitude 2 BitNo Magnitude VP_CTRL 0 Quantized to 8 bit with a view port control maflt 8 fix match out 2 VP CTRL Quanlevel VP Quanlevel VP powde real match out the real value is used in BPSK case powde 10 fix powde Quanlevel Magnitude Quanlevel Magnitude clear match out 7 a a a a da a lle Do Do o o o o o o o a a a a a a a a a ello bo oo do lolo le olo lolo olo lodo o alo Symbol Tracking SYMTK hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh THRESHOLD 5 define the threshold N round length powde 10 2 chip rate 2 97 APPEN
51. difference is indicated by the angle of c k For BPSK modulation the only two possible phase differences are 0 and 180 So the sign of the real part of c k has the information for the phase difference As r k is a real signal the conjugate operation can be omitted Relc k Acos p k p k 1 1 o k k 1 0 1 d k k 1 1809 sign Re c k 4 17 For QPSK modulation there are four possible phase differences 0 90 180 and 270 We still can decode the data from the phase of c k In practice the Z2000 introduces a 45 or 45 phase shift before the complex conjugation as shown in Figure 4 19 r k SS Delay Conjugate Tb multiplication 1 j RNA j Figure 4 19 The Conjugate Multiplication for DQPSK 48 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP The c k is thus expressed as c h VIA eil 605 1 48 4 18 The signal constellation of c k is rotated clockwise or counterclockwise depending on whether 4 45 or 45 is introduced Figure 4 20 Now the original data can be easily decoded by the signs of the real and imaginary components of c t dot or cross products respectively used in the Z2000 data sheet Im Im 01 j IQ 4 01 IQ e e 00 11 Re Re e e 10 e e 11 10 00 45 Phase Shift 45 Phase Shift Figure 4 20 The Conjugate Multiplication for DQPSK with Phase Shift
52. e 4 1 The Overall Transceiver System ooo vil O d oco o N C LIST OF FIGURES 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 4 10 4 11 4 12 4 13 4 14 4 15 4 16 4 17 4 18 4 19 4 20 4 21 4 22 4 23 4 24 4 25 4 26 4 27 5 1 The Structure of the 22000 2 2 000200 02004 32 The 22000 Transmitter 2 2 2 0 0 eA 33 The Differential Encoder 2 len 33 The Signal Constellation of QPSK 0 35 The Operation of PN Modulation 22s 35 The Alignment of PN Code with Preamble and Information Data 36 The 42000 Receiver ss a a e wok ger sek gane RR ER EH e 37 Spectrum Aliasing after Direct IF Sampling of a BPSK Signal 38 The Operation of Direct IF Sampling o 39 Direct IF Sampling of a QPSK Signal 39 High Conversion With Direct IF Sampling 40 The Operation of Quadrature Sampling 41 Quadrature Sampling aaa 42 Integrate and Dump Filter nen 42 The Magnitude Response of the Moving Average System 43 The Operation of PN Matched Filter aa vr ra kn nrk 45 The Operation of Conjugate Multiplication 47 The Conjugate Multiplication for DQPSK 48 The Conjugate Multiplication for DQPSK with Phase Shift 49 Simulation Model of the 22000 o e e e 50 Simulation Block Diagram
53. e the optimization level vi selects the processor type is 64180 b makes the object code a library module Note that the Z80182 processor is compatible with the 64180 instead of Z80 processor e Add these two modules to the run time library module c164180 by the following commands xlib def cpu z80 rep mod putchar c164180 rep mod getchar c164180 exit Now the library module c164180 will have the modified putchar and getchar modules e To test the modified modules before installing them in the library place the following lines into the rf xcl file 102 APPENDIX C MODIFICATIONS TO THE IAR COMPILER A putchar A getchar c164180 e Also we need to modify the rf xcl file to allocate the memory segments Z CODE CODE RCODE CDATAO ZVECT CONST CSTR CCSTR 4680 Z CODE INTVEC 2000 Z DATA DATAO IDATAO UDATAO ECSTR WCSTR TEMP CSTACK 1000 1FFF e Finally the last two lines of the generated rf hex file should be deleted to provide file compatiblity 103 VITA Guoliang Li was born in China on July 12 1971 He received his Bachelor of Science of Electrical Engineering BSEE from Xiamen University China in June 1992 After that he worked in Xiamen TV Station China as a system engineer In 1994 he came to the Bradley Department of Electrical Engineering at Virginia Polytechnic Institute and State Univer sity Virginia Tech for his M S E E with concentration in the communication
54. eated Repeated s A Data Input Stream Data Symbol Data Symbol Data Symbol one Figure 3 1 Symbol Synchronization Assuming that the PN code length is L chips E can be given by the energy of each PN chip E times L E L Ee 3 2 hence the BER or P is also given by Ec L 1 BER P 5e No 3 3 If we decrease the input data rate lengthen the symbol period without changing the PN chip rate limited by RF receiver automatic gain control bandwidth as shown in Figure 3 2 the bandwidth of the spread signal is unchanged as the PN chip rate remains the same In addition the energy of each PN chip Ee is unchanged Consequently L is increased and 16 CHAPTER 3 DIRECT SEQUENCE SPREAD SPECTRUM SYSTEM DESIGN thus the processing gain and the energy per bit Ej are increased It can be seen from Equation 3 3 that as LE N increases the BER will decrease L chips L gt L PN code generator PN code Repeated AR Data Input Stream Data Symbol Data Symbol TNR Figure 3 2 Decreasing the Data Rate Therefore we find that by increasing the length of the PN code for a given chip rate we have better BER performance at the cost of a lower data rate From this mechanism we come to our variable data rate transmission technique 1 When the wireless channel is degraded and BER is high we increase the PN code length and slow down the data transmission rate to compensate for ch
55. ect time By doing this we study the flywheel strategy s impact only on data reception This simulation shows that the BER performance is greatly affected by the symbol tracking process Figure 4 25 shows that the flywheel tracking process will degrade the system BER performance by at least 3 dB when Ej N is large The threshold settings will greatly also affect the BER performance Figures 4 26 and 54 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP zation uantizat l LI l l l l l l l H l l l l l l LI l l l l l l l H l l Q ith BER Performance with E BERPerf E j E g E I a 10 Figure 4 24 Quantization Effect 55 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP 4 27 show how the BER performance is affected If the white noise is small enough the BER decreases when the threshold increases This means that when a higher threshold is set the detections will be less likely to exceed this threshold Thus the flywheel strategy is more likely to use the previous correct detection timing information instead of the largest noisy signal s timing to track the symbol We should remember that we assumed that the first detection is always at the right time If this condition is not satisfied we should expect increased deterioration in the BER performance Another situation we need to conside
56. emerging in personal communications systems and wireless information network applications In 1985 the Federal Communications Commission FCC released three unregulated ISM bands to encourage the development of spread spectrum technology The frequencies of CHAPTER 2 SPREAD SPECTRUM AND WIRELESS LANS these unlicensed spectrum are 902 to 928 MHz 2400 to 2483 5 MHz and 5725 to 5850 MHz Part 15 247 of FCC rules governing these frequencies bands requires that the transmitters use spread spectrum modulation with a transmitted power less than 1 W and the processing gain of the spread spectrum system be larger than 10 we will discuss the processing gain in the following sections The drawback of this unlicensed operation is that one must be able to operate with interference from other users in the same bands A direct sequence spread spectrum wireless LAN WLAN system is proposed in this paper This system is designed to be compatible with IEEE 802 11 which is a standard being developed using direct sequence and frequency hopping techniques in the 2 4 GHz ISM band and baseband infrared IR technique Dra 94 The main difference in this work from IEEE 802 11 is that we use the 902 928 ISM band for radio frequency RF transmission It is intended to provide signal coverage up to 500 800 feet One of the benefits of using spread spectrum is that the transmission capability of the wireless channel can be maximized by using a variable data rate trans
57. er Code Correlation Function 28 CHAPTER 3 DIRECT SEQUENCE SPREAD SPECTRUM SYSTEM DESIGN 80 T T T 40 1 Partial Correlation i 20 40 60 80 100 120 140 80 T T T 60 1r 40 1 Period Autocorrelation j 20 40 60 80 100 120 140 Time Figure 3 10 63 Bit Code Correlation Function 29 CHAPTER 3 DIRECT SEQUENCE SPREAD SPECTRUM SYSTEM DESIGN 80 T T T 40 Partial Correlation j 20 40 60 80 100 120 140 Time 80 T T T 60 n E 40 1 Period Autocorrelation 20 40 60 80 100 120 140 Time Figure 3 11 64 Bit Code Correlation Function 30 Chapter 4 Operation of the Zilog Z2000 Chip 4 1 Overview The Z2000 The 94 is a 100 pin spread spectrum digital processor manufactured by Zilog It combines a direct sequence spread spectrum transmitter and a receiver together in single chip On the Zilog Z2000 Evaluation Board the Z2000 works with Zilog s Z80182 intelligent peripheral controller With microcode residing in its random access memory RAM space the controller carries out the system configuration parameters setting for Control Interface Z2000 Evaluation Board Radio Transceiver I
58. er the acquisition is declared If this is the case then an automatic 56 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP Simulated Z2000 Performance 4 Figure 4 25 BER Performance with Symbol Tracking Threshold 5 2 4 Eb No dB 57 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP 0 45 ES umm us l l 0215 a NE PS SS SS E CE TEA E 0 05 25 15 Threshold 10 4 dB Figure 4 26 BER Performance with Symbol Tracking Ep No 58 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP 25 15 Eb No uda 6 dB Figure 4 27 BER Performance with Symbol Tracking Ey N5 59 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP frequency control AFC loop should be added to perform frequency tracking to maintain synchronization 3 Missed detection counter This counter records the number of times that a threshold is not exceeded at the expected time per burst The threshold for this counter can be set in the control registers If this threshold is exceeded during a burst it means that a PN code misalignment occurs or the AFC is tracking the incorrect frequency In this case the receiver should be reset to acquisition mode 4 Automatic frequency control The AFC loop should synthesize the NCO output to the received carrier when the initial frequency uncertainty is within the pull in range o
59. erage System 90 B Simulation Approach 91 B 1 Simulation in the MATLAB Environment 91 B 2 PN Matched Filter Gasa re Mag og Lu e ken no bohcgeshe b gt 92 B 3 Symbol Tracking Processor 2A 92 B 4 Commented Simulation Code 0 00000 ee eee 93 C Modifications to the IAR Compiler 100 vi LIST OF FIGURES 2 1 2 2 2 3 2 4 2 5 2 6 2 7 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 Power Spectral Density PSD of Spread Spectrum Direct Sequence Spread Spectrum Spreading and Despreading A Typical Direct Sequence Spread Spectrum Transmitter and Receiver The Ideal PSD and Autocorrelation Function of c t Frequency Hopping in the Time and Frequency Domains A Typical Frequency Hopping Spread Spectrum Transmitter and Receiver The Model of Spread Spectrum Receiver 2 ar vr rv vraker Symbol Synchronization 2 rar ee Decreasing the Data Rate rv rv rn nrk kran A Sliding Correlator acoc ecs 2 22 A Matched Filtet e 4 uxor ER OUS RO o IE a EY Ro US eS A Transversal Matched Filter 0 2 0 2 0200 00000 eee A PN Matched Filterz used ORE dex eeu A General Model of Despreading Process llle M Sequence PN Code Generator pee ee ee 11 Bit Barker Code Correlation Function 3 10 63 Bit Code Correlation Function 0 00000 eee ee 3 11 64 Bit Code Correlation Function ee
60. f the AFC loop Only a small phase shift relative to the phase difference carrying information 180 for BPSK and 90 for QPSK is allowed if the AFC is tracking the correct frequency 60 Chapter 5 RF Hardware Design 5 1 RF Module Description The RF module is a half duplex radio transceiver designed to interface with the Zilog Z2000 Evaluation Board The RF frequency is 915 MHz which is in the middle of the 902 928 MHZ ISM band An additional stage of up conversion can be implemented to move the 915 MHz spectrum to a higher frequency such as the 2 4 GHz and 5 7 GHz ISM bands A corresponding down converter can be employed in the receiver The RF module including a transmitter and a receiver is shown in Figure 5 1 The transmitter is of conventional design The transmitter input is the baseband spread signals TXI and TXQ from the Zilog 22000 Evaluation Board These digital signals are first low pass filtered to reduce the modulation side lobes and then BPSK QPSK modulated onto a 170 MHz carrier generated by the Colpitts crystal oscillator Rar 83 After a current controlled variable attenuator and an amplifier the modulated signal is fed into a 170MHz helical bandpass filter for the further elimination of side lobes Another amplifier stage increases the power level of this band limited signal to 0 dBm This signal is then mixed with a 745 MHz carrier from a frequency synthesizer The sum product of 915 MHz passes through a bandpass
61. fect by pseudo randomly hopping the RF carrier frequency in the available RF band Here the processing gain of the FHSS system is given by the ratio of the spread signal bandwidth to the information bandwidth CHAPTER 2 SPREAD SPECTRUM AND WIRELESS LANS 2 2 3 Synchronization Requirement in the Spread Spectrum System In a spread spectrum system the generated PN code at the receiver side must be aligned or synchronized to the received PN sequence otherwise the PN code misalignment will prevent effective despreading Synchronization is usually accomplished by two processes an acquisition of the initial PN code alignment followed by a tracking process to eliminate a possible new phase shift introduced to the received signal during the signal reception process The synchronization is important in a spread spectrum system Without synchroniza tion the spread spectrum will appear as noise at the receiver will is unable to perform despreading Hence synchronization performance will greatly affect the overall system data reception capability We will focus on this topic in Chapter 3 2 3 Wireless LAN using Direct Sequence Spread Spectrum 2 3 1 Wireless LAN Systems Wireless network products are targeted primarily for LAN coverage and data rates above 1 Mb s They provide mobility to wired counterparts through the wireless channel Generally wireless networks come in two forms The simple one is base station LAN system It is a LAN w
62. filter centered at 915 MHz to an RF amplifier and then onto antenna 61 CHAPTER 5 RF HARDWARE DESIGN TRANSMITTER TXI gt LowPass Variable BandPass BandPass TXQ gt Filter gt QPSK Attenuator Filter gt Filter d digital 915 MHz to Sprea igita Antenna signal from STEL 2000 170 MHz Crystal 745 MHz Freq Oscillator Synthesizer 14 4 MHz Crystal Reference Control Bus from PC Oscillator Dual Frequency 985 MHz Synthesizer 90 MHz 915 MHz BandPass BandPass 70 MHz SAW 20 MHz From Filter Fiter bo ATR Fiter Antenna 70 MHz r Automatic Gain Control AGC 20 MHz IF output to BandPass STEL2000 7 ra Filter mer 0 8 Vpp RECEIVER Figure 5 1 RF Module Architecture for transmission The frequency synthesizer can be controlled to generate a signal at other frequencies to up convert the 170 MHz spectrum to any frequency in the ISM band as long as the bandpass filters and the RF amplifiers have the appropriate bandwidth Note that the signal bandwidth should not exceed the ISM band boundaries The Grayson receiver was manufactured by Grayson Electronics in Lynchburg VA It was designed for a similar applications and it is being used for our wireless LAN project It uses two stages of down conversion from 915 MHz to 70 MHz and then to 20
63. g methods and the PN code affect the acquisition and the BER performance of the system The PN matched filter despreading method is compared to the sliding correlator in the terms of average acquisition time performance and is found to be suitable for wireless LAN applications An 11 bit Barker code and a 63 bit M sequence code are suggested In Chapter 4 we talk about the operation of the Zilog 22000 spread spectrum processor 86 CHAPTER 7 CONCLUSIONS The operational theory and the hardware realization of each functional block of the Z2000 are described A baseband simulation of this chip is conducted to verify our understanding and to predict the system BER performance Chapter 5 presents the RF hardware design issues In this project a transmitter exciter has been designed and built to perform BPSK QPSK modulation and move the baseband spread spectrum to IF frequency at 170 MHz Colpitts crystal oscillators for 170 MHz and 14 4 MHz are designed to provide the carrier frequency for the modulation and the reference frequency for the frequency synthesizers Chapter 6 describes the control software development The operation of the Z2000 is controlled by the Zilog 80182 intelligent peripherals controller The control interfaces between the PC 80182 controller and 22000 chip and an additional RF module control interface are defined in this chapter Zilog s emulation source code is modified to solve the incompatibility issues of a different comp
64. iler system IAR compiler The work needed to implement a full physical layer control program is briefly described In this thesis we studied the operation of the 22000 Evaluation Board and translated its data sheet description into a mathematical representation A simulation of 22000 based on the mathematical representation was built to study the quantization effect and the Zilog s flywheel symbol tracking strategy s effect on the overall BER performance The results show that the quantization effect can be neglected and the flywheel strategy degrades the BER performance when there is no phase difference between the transmitter and receiver A transmitter exciter has been designed and built The IAR C compiler system was configured to work for the Z80182 processor and the physical layer hardware control software was modified from the Zilog s emulation program to provide reliable data frame transceiving 87 References Ber 92 D Bertsekas and R Gallager Data Networks Second Edition Prentice Hall Inc 1992 Buc 92 R M Buchrer and B D Woerner Teaching Spread Spectrum for Commercial wireless Communications Cou 90 L W Couch Digital and Analog Communication System Macmillan Publishing Company 1990 Adv 94 Z2000 Spread Spectrum Transceiver Advance Information Specification Zilog Inc Cambell California 1994 Dav 78 S Davidovici and D L Schilling Minimum Acquisition Time of a PN Sequence
65. in lobe Figure 5 11 shows the baseband signal s spectrum after the low pass filter eliminates the undesired side lobes The low pass filter is a three element Butterworth filter with a cutoff frequency at 2 MHz The first side lobe is attenuated about 7 dB compared to Figure 5 10 In Figure 5 12 we show the spectrum of the output from the Colpitts crystal oscillator This signal is amplified after MAV 11 amplifier and low pass filtered by a three element Butterworth filter This filter is designed to cutoff at near 170 MHz The graph shows that the 170 MHz frequency output is fairly clean and the second harmonic is more than 25 dB below the desired 170 MHz The last graph Figure 5 13 presents the BPSK modulated signal right after the two stages of MAV 11 amplification The output signal level is adjustable through the current controlled attenuator If a helical bandpass filter with center frequency at 170 MHz and a cutoff bandwidth of 4 MHz is available later it should be operated between two stages of amplification as shown in Figure 5 3 and we will expect the side lobes be attenuated to a greater degree From these four graphics we can say that this Tx Exciter works as we designed to perform the BPSK modulation at 170 MHz 73 CHAPTER 5 RF HARDWARE DESIGN Jas NUAN SNOT Aad 440 NO NIH 17d Bryuag Hid 11d 330 NO 1P7 lt 1d Fol 9d 51d ZHA GH BT NYdS EE E dMS zH E MBA LA d ZHA GE MB 58 ZH
66. ine aps 85F 1 1 40 0 6 0 4 0 2 Normalized Frequency 11 Figure A 1 Magnitude Response of the Moving Average System N 90 Appendix B Simulation Approach B 1 Simulation in the MATLAB Environment This spread spectrum simulation involves a significant computation and it is time consuming and memory consuming It is strongly recommended to make every effort to avoid unnec essarily complicated algorithms and to follow advice from MATLAB manual Mat 92 1 Vectorize the simulation algorithm to eliminate for and while loops The reason is that MATLAB s built in vector and matrix operations are 10 times faster than its compiler interpreter operations 2 Preallocate any vectors in which output results are stored By doing so we eliminate memory allocation each time any number of vector elements are needed and increase the efficiency of memory by using contiguous memory space It is also important to use the clear function in MATLAB to remove variables no longer in use from the work space Otherwise the computer system may not have enough swap space for new variables The simulation models for some functional blocks are straight forward and the source code for these models is easy to understand if the reader is familiar with the operation of the functional blocks and with MATLAB In the following we include the code description 91 APPENDIX B SIMULATION APPROACH fo
67. ined when the Hex file is linked and is specified in the link command file We will discuss this further in Appendix C 6 2 2 480182 and Z2000 Interface In this application the least significant 6 bits of Port C PC5 PCO are configured to be an output input on a bit by bit basis and are multiplexed with the control pins from the ESCC channel A Serial data is communicated through ESCC Channel A TxDA and RxDA pins to TxIN and RxOut pins on the Z2000 respectively Thus the control signals are generated by ESCC channel A and sent out through Port C to the 22000 All of the 22000 control registers are written through this path Note that these registers are not readable so the control program must keep a copy of them in the memory if it needs values later 6 2 3 RF Control Interface The Z2000 provides a parallel Port B for the RF section control including frequency syn thesizer initialization power control and half duplex switch control In this application there are two frequency synthesizers designed to work for the up converter and the down converter The control signals should be present on the three input lines for each synthesizer immediately after power up or system reset These three lines are PLL Enable Serial Data and Serial Clock The synthesizer needs to first be enabled by a falling edge on PLL Enable then the synthesizer control register words should appear serially on the Serial Data line and are clocked in by the Serial
68. ith wireless transceivers and a central base station which controls the communication access of all the mobile stations A multi access reservation mechanism can be used to send a short access reservation packet to reserve longer non contending slots for actual data packets This scenario is similar to the communication between a satellite and earth stations Another form is a stand alone wireless system a LAN architecture with in tegrated wireless transceivers which support communication directly with each station The wireless media is shared without a central base station or access point In this case access is controlled through a Carrier Sense Multiple Access Collision Avoidance CSMA CA pro tocol In CSMA CA the nodes monitor the channel transmission activity and transmit in 10 CHAPTER 2 SPREAD SPECTRUM AND WIRELESS LANS sequence node first listens to the channel to detect a quiescent period and then continues to wait for a small amount of time If there is no transmission occurs during this period of time the station starts transmission The amount of waiting time depends on where the node is in the network sequence As each node has a different waiting period the priority of transmission is different The node with a longer waiting period is allowed to transmit only after the transmissions of nodes with shorter waiting periods thus no collision will oc cur Ber 92 Some additional access protocol to maintain bandwidth or channe
69. itive white Gaussian noise AWGN is introduced in the receiver by the low noise amplifier LNA and the down converter This noise bandwidth is as wide as that of the spread spectrum signal During the despreading process the noise is multiplied by the despreading PN sequence c t Mul tiplication reverses the polarity of the noise waveform but has no impact on the power spectral density or the probability density function of AWGN We come to the conclusion that the spreading despreading operation does not affect the signal energy and does not affect the spectral and probability density function of the noise For this reason the overall bit error rate BER or the probability of error P in an AWGN channel is the same as the BER performance of the modulated and demodulated system without spread spec trum In our case if we assume that non coherent differential phase shift keying DPSK 15 CHAPTER 3 DIRECT SEQUENCE SPREAD SPECTRUM SYSTEM DESIGN modulation is used then the BER performance of this spread spectrum system is found to be approximated by Pro 95 E 1 BER P ze No 3 1 where Ey is the average energy of a received bit and No is the noise power density In this wireless LAN application we use a symbol synchronous PN modulation tech nique The PN code repeats itself once per symbol and is aligned with the symbol transi tions as shown in Figure 3 1 Lchips PN code generator PN code Rep
70. l Acquisition and its Impact on System Performance In a spread spectrum system synchronization is a common requirement and is usually com bined with the PN despreading process acquiring initial alignment of the transmitted and local codes within a time frequency uncertain region acquisition and secondly reducing and maintaining the alignment error as much as possible tracking Typically the acquisi tion process is realized by continuously monitoring some function of despread output signal If this function of the output signal level exceeds some specified threshold then an initial acquisition is declared followed by a transition to fine alignment tracking process There are two basic approaches to the direct sequence spread spectrum despreading function the PN matched filter and the sliding correlator With the bursty data transmission in LAN applications a fast acquisition with high detection probability PN despreading process is desirable to minimize the physical level processing time This improves the system performance in terms of overall system through put The transmitter should have a preamble that is long enough for the receiver to perform acquisition Thus the longer the average acquisition time the longer the preamble required and the greater the physical layer overhead This results in reduced overall throughput 18 CHAPTER 3 DIRECT SEQUENCE SPREAD SPECTRUM SYSTEM DESIGN Secondly since the radio environment in whi
71. l allocation might be included to improve the overall system performance in a wireless environment These two wireless network systems can be integrated with a wired network if the co ordination problem is solved This is because the transmission rates might be quite different In this thesis we consider a stand alone wireless LAN based on the proposed IEEE 802 11 standard Three different technologies are currently in use to provide wireless connections for WLAN systems infrared IR systems licensed cellular systems operating at 18 19 GHz and unlicensed spread spectrum systems operating in the ISM bands IR LANs are of two distinct types line of sight LOS direct beam infrared DBIR or diffused infrared DFIR As their signals do not penetrate walls they are easy to install where signal confinement within a walled room is desired The disadvantages of IR WLANs are that they suffer interference from the sun and other light sources Propagation range is limited relative to radio WLANs and they are sensitive to shadowing DFIR LANs do not require a direct LOS path between the transmitter and the receiver and therefore they are less susceptible to signal blockage and shadowing However due to the scattered signal power and the resulting multipath fading DFIR can provide only moderate data rate and coverage DBIR LANs use a focused beam to improve receiver signal to noise ratios and reduce multipath propagation This allows for higher data
72. mission technique This technique reduces the data rate when the wireless channel is degraded to ensure reliable data reception and increases the data rate when the channel is clear to fully use the channel capacity By dynamically changing the data rate according to the channel performance this technique helps to maintain the link during the adverse conditions It reduces the necessity of link re initialization by reducing dropout and it also maximizes the overall system throughput This technique will be described further in Chapter 3 2 2 Principles of Spread Spectrum 2 2 1 Spread Spectrum and the PN Code Generally a spread spectrum signal is generated by modulating a signal so that the resultant transmitted signal has a bandwidth much larger than the original signal bandwidth This is shown in Figure 2 1 Two requirements need to be met in a spread spectrum system First the modulated CHAPTER 2 SPREAD SPECTRUM AND WIRELESS LANS signal occupies a much wider spectrum than the original message signal Second the modu lated signal appears to be random and uncorrelated to the original data although generated from the original data Buc 92 A key parameter of the spread spectrum system is the bandwidth expansion factor or the processing gain As we see in Figure 2 1 the transmit ted power is spread over a bandwidth N times wider than the information symbol rate Thus without changing the signal power the power spectral density PSD
73. n coswt jsinwt Lincoswt Qinsinwt j Li sinwt Qincoswt lout Em IQout 4 6 where w is the angle frequency of the NCO output This sampling method is equivalent to when the input signal is complex and is thus only defined in the positive frequency domain The two ADCs converting the real I and Q channel signals can be thought of an ADC converting a complex I jQ signal Thus this sampling does not introduce an undesired alias in the primary Nyquist region This is shown in Figure 4 14 A negative NCO frequency will correctly down convert the spectrum to baseband 4 3 3 Low Pass Filter A digital low pass filter is required with the direct IF sampling to remove the other undesired spectrum in the primary Nyquist region While in quadrature sampling as we see in Figure 4 14 this filter is unnecessary In the digital domain an integrate and dump filter is usually used to perform this low pass filtering process In our application this integrate and dump filter not only low pass filters the undesired spectrum in the primary Nyquist 41 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP 0 freq l LA p Sampling Frequency Sampling Frequency freq Figure 4 14 Quadrature Sampling region but also decreases the sampling rate This reduces the computational complexity of the following operations Due to this it is usually called a decimator filter Moving Average i Down i x n System hin y n S
74. n After that the re ceiver buffer is reset to zero and is ready to store incoming data This is done in the Init TxRxBuffer function After this system initialization the emulation program is ready for a user s operating command It supports reading writing and comparing buffers starting data transfer from the transmitter buffer and storing data in the receiver buffer It can also access the 722000 registers reading is through copies of the registers in RAM as stated previously The operation of the 22000 is configured as needed by modifying these register words 6 4 Future Work This emulation program provides an interface for user access to all of the Z2000 s registers This is unnecessary for our control program We only need to change some operating 83 CHAPTER 6 SOFTWARE DEVELOPMENT Program Start Select MIMIC Or ESCC B Reset STEL 2000 Reset its register copy Reset ESCC channel Initialize ESCC to SDLC Enable ESCC Configure STEL 2000 Allocate Buffer Space Set TxBuffer Content Reset RxBuffer to Zero y Print out the Control Menu Waiting for User Response User Command done Processing Figure 6 3 Flow Chart for the Emulation Program 84 CHAPTER 6 SOFTWARE DEVELOPMENT parameters according to the MAC layer s configuration frames such as the PN code or data rate Other key parameters will be modified ac
75. n the receiver allows and the more reliable the acquisition and reception of the data PSD a t gt freq gt t 0 q 0 The ideal power spectral density of c t The ideal autocorrelation function of c t Figure 2 4 The Ideal PSD and Autocorrelation Function of c t Frequency Hopping Spread Spectrum Frequency hopping spread spectrum FHSS is similar to DSSS in the sense of spreading the signal energy over a wider bandwidth than the information bandwidth The difference is that the available channel bandwidth is divided into a large number of continuous fre quency slots and a PN generator drives a digital frequency synthesizer to hop among the CHAPTER 2 SPREAD SPECTRUM AND WIRELESS LANS center frequencies of these available frequency slots The hopping pattern of the frequency synthesizer is determined by the output of the PN generator Figure 2 5 Frequency Slot A Time Slot Figure 2 5 Frequency Hopping in the Time and Frequency Domains Baseband Data Bi ot modulation amp Q BandPass Dembdul tion Lowpass Output d t Data d t seno i Filter Filter PN Code et Digital Frequency Digital Frequency Local PN Code Generator Synthesizer Synthesizer Generator Figure 2 6 A Typical Frequency Hopping Spread Spectrum Transmitter and Receiver Thus a FHSS system produces a spreading ef
76. nations for QPSK Differential Encoder 4 2 PN Matched Filter Viewport Setting Chapter 1 Introduction Today communication has increasing influence on our daily life Wireless data communi cation services allow people to access the data network without a physical connection IEEE 802 11 is being proposed to provide wireless connection for local area network LAN using spread spectrum techniques in the Industrial Scientific Medical ISM bands and baseband infrared techniques In this project we want to design and build a real wireless LAN system operating at 902 928 MHz of the ISM bands The physical layer of this network has been designed to perform direct sequence spread spectrum processing and RF transceiving variable data transmission strategy is employed in this system so that we are able to configure the physical layer dynamically based on the medium access control MAC layer s control frame In this thesis the physical layer subsystem was designed and hardware and software supports were built based on the above requirements We employ the Zilog 22000 Evaluation Board to perform spread spectrum processing and a Grayson 900 MHz receiver for radio signal receiving The radio transmitter was designed and built in the Center for Wireless Telecommunications Virginia Tech In the next chapter we want to introduce spread spectrum operation and the concept of wireless LAN Chapter 3 describes the spread spectrum system design
77. nd dump filter is the number of RXIFCLK samples over half a PN chip duration A front end processor operating at the front of the matched filter averages the data stream from the integrate and dump filter over each chip period by adding each incoming sample to the previous one The PN matched filter calculates the cross correlation between the incoming signal and the locally stored PN code coefficients twice per chip The FEP and PN matched filter is shown in Figure 4 17 PR RR rn a TapO Tap1 Tap63 EE 2T T 2T gt 27 i Co C1 Figure 4 17 The Operation of PN Matched Filter 45 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP The matched filter output is 63 output y Data n 2T c n 2T 4 14 n 0 Note that 1 T is the baseband sampling rate which is twice the chip rate In other words T is half the chip duration For the proper operation of the PN matched filter a delay time of 2T one chip duration is required for each of the 64 delay lines The cross correlation value is compared against a programmable threshold each symbol period When the threshold is exceeded symbol detection is declared and a symbol clock pulse is generated To increase the probability of detection and reduce the false alarm rate a flywheel circuit is inserted in the symbol tracking processor This flywheel circuit is designed t
78. o compare the cross correlation value one symbol period after the last correctly detected one within a window of T Therefore in one symbol duration only three of the PN matched filter outputs are compared against the threshold One is the sample exactly one symbol period after the last correct detect plus or minus one sample If none of these three samples exceeds the threshold a symbol detect signal will be inserted exactly one symbol period after the last valid detect The operation of this circuit assumes a constant symbol rate and uses the knowledge of the symbol rate to predict the time of next symbol with a precision of 1 sample half the chip duration The PN matched filter is designed to operate at twice the chip rate such that it provides a time accuracy within 0 5 chip duration during the tracking operation In the 72000 the PN matched filter is able to switch between the acquisition mode and the data despreading mode In other words after acquisition is declared by using the preamble PN code coefficients to despread the first symbol of the burst preamble the filter is configured to automatically switch to another set of PN code coefficients for data code spreading The output of the PN matched filter is 10 bits and another viewport control is implemented to prevent the input signal into the differential demodulation stage from exceeding 128LRL 8 bits For PN code lengths of 11 and 63 Table 4 2 shows how to set this view
79. of the signal would be N times lower than it would be in non spread transmission and the signal is less likely to be detected Obviously this property makes spread spectrum attractive for military applications in which the signal must be hidden from eavesdroppers PSD Original Signal Spectrum 77 Spread Signal Spectrum gt Frequency Figure 2 1 Power Spectral Density PSD of Spread Spectrum The processing gain N is defined by N transmitted signal bandwidth 2 1 rocessing gain N E IES information bandwidth which specifies to what extent the original signal is spread Practically N is an integer with a typical value of 10 logigN 10 to 30 dB The pattern used in the spread spectrum system to spread the information spectrum CHAPTER 2 SPREAD SPECTRUM AND WIRELESS LANS is called the spreading pattern or spreading code This spreading code is generated in a deterministic way but should appear to be random or noise like Hence it is usually called the pseudo random or pseudo noise PN code In order for the spread spectrum receiver to reliably despread the signal a common requirement of the PN code is good autocorrelation performance There may be additional requirements in some applications For example in a Code Division Multiple Access CDMA system a small cross correlation value with multiple PN codes is desired and in our wireless LAN system a good partial correlation i
80. olar waveform with an amplitude of 1 volt the average signal power is thus 1 watt Hence the energy per bit is expressed as 1 Ep P To Re 4 19 where Ry is the bit rate The noise power in the channel is the product of the two side noise figure N 2 and the bandwidth of chip sequence we only consider the positive frequency domain N N Pnoise E i BWehip zx gt D N Ro 4 20 where N is the processing gain From Equation 4 19 and 4 20 we find the relationship between noise power Pnoise and Ep N as follows 51 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP No NR 1 NR 1 N 1 meer cV v AEE R 2 B N a Actually the noise power equals the noise variance as the mean value of the white noise is zero 4 4 4 Simulation Results and Analysis Simulations were carried out to study the bit error rate BER performance of the Z72000 The quantization effect and the symbol tracking performance are obtained from the simu lation results As we know this spread spectrum system employs the Differential Phase Shift Keying DPSK technique The BER performance of this spread spectrum system is the same as that of DPSK without spread spectrum This conclusion comes from Section 3 1 Thus in our non coherent DPSK spread spectrum simulation the theoretical BER performance is given by 1 BER P em 4 22 A plot of Equation 4 22 is shown in Figure 4 23 The simulations were conducted with Ey N from 4 dB to 9 dB with
81. port register 46 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP Table 4 2 PN Matched Filter Viewport Setting PN code length level at output of view port register view port input level into M PN matched filter setting ratio Diff Demo LRL LRL 11 38 5 00 1 38 5 63 220 5 01 2 110 25 4 3 5 Differential Decoder The data is encoded as the phase difference of two consecutive symbols in differential mod ulation so the objective of the differential decoder is to detect this phase difference Any possible constant phase shift added to the whole symbol stream has no effect on the correct decoding An easy way to compute the phase difference is conjugate multiplication Let r k r k 1 denote the received baseband signal at time interval k and a previous time interval k 1 respectively To show the operation clearly we represent these two signals in amplitude angle form as follows r k A k AB r k 1 A k 1 IR 4 15 where A 9 are the amplitude and angle components respectively r k gt Delay Conjugate r k 1 Tb multiplication Figure 4 18 The Operation of Conjugate Multiplication 47 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP Then by conjugate multiplication c k r k r k 1 A k e A k 1 e 490 A e l k k 1 4 16 where A A k A k 1 is a constant Thus the phase
82. quency The Z2000 port is programmed to send the control data streams in the format specified by each type of frequency synthesizer Once the registers are set the frequency synthesizer will have continuous output 5 2 Power Consideration in the Transmitter Module The block diagram of the transmitter module is shown in Figure 5 2 The detailed circuit for this module is also shown in Figures 5 3 and 5 4 The two 7486 XOR gates in each channel perform unipolar to polar conversion with an output level at 5 5 dBm A resistor divider designed for impedance matching introduces 6 dB attenuation After a three element Butterworth low pass filter and a three resistor resistive attenuation network the signal is attenuated approximately 10 dB and arrives at the balanced modulator SBL 1 IF port at about 4 5 dBm A 170 MHz frequency is generated by the 2N5179 Colpitts crystal oscillator Its output is 2 dBm After a MAV 11 amplifier and a low pass filter to eliminate the undesired harmonic frequencies 63 CHAPTER 5 RF HARDWARE DESIGN 5 dBm cosine 5 5 dBm 5 dBm 1 5dBm 45dBm 8dBm 11dBm Unipolar gt gt gt LPF gt gt Di to Polar 6dB 3dB 3dB 11 dBm gt 3dB Am TxQ Unipolar gt LPF gt gt to Polar 6 dB 3dB 3dB 11 dBm sine 11dB 11 dB 5 dBm ang Helical Siter zu 0 d
83. r Converter IF input To Demod Host Figure 4 2 The Structure of the 72000 4 2 Transmitter The transmitter incorporates a differential encoder a PN spreader and a BPSK modulator with a carrier frequency derived from a numerically controlled oscillator The block diagram is shown in Figure 4 3 32 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP Digital M LC NE Differential E reed NG A Stream Encoder oder odulation Output Numerically Controlled Oscillator Figure 4 3 The 22000 Transmitter 4 2 1 Differential Encoder In the differential encoder the polarity of the data is presented in the phase change between consecutive bits The differential decoder can correctly recover the original data as long as the phase difference between successive symbols is maintained after the transmission The absolute phase of each symbol is not required for correct decoding Hence the differential modulation allows a phase ambiguity that may be introduced by some carrier recovery circuits For BPSK operation the differential encoder compares the input bit in k with the previous output bit out k 1 by a logical exclusive OR operation out k in k amp out k 1 in k out k 1 in k out k 1 4 1 where amp represent the exclusive OR operation or modulo 2 addition This is illustrated in Figure 4 4 An arbitrary reference binary digit is as
84. r is that we assume the ideal frequency and phase tracking in this simulation However this is not true for the real situation The flywheel strategy is designed for the real receiver when there are phase and frequency offsets between transmitter and receiver In this case we expect the flywheel strategy will help to correct symbol tracking 4 4 5 Future Work As stated previously the simulation was done to verify our understanding of Z2000 s oper ation and it only considers for a limited system configuration Some additional functions should be added to provide a more sophisticated performance analysis 1 QPSK modulation The data stream is divided into an I and Q channels at the Input Processor and converged back to one stream at the Output Processor This will affect the differential encoder and decoder This function and the realization of DQPSK has already been discussed in Section 4 2 and 4 3 2 Preamble acquisition In the current simulation model we assume there is no phase difference between the carrier of transmitter and the local NCO frequency In other words it is a coherent system If this assumption is not valid then one preamble symbol is required to precede the information symbol for the PN matched filter to perform acquisition As the PN code for this preamble could be different from the PN code used for information symbols the PN matched filter is required to automatically switch to another set of PN code immediately aft
85. r some functional blocks which might not be easy for the beginner B 2 PN Matched Filter SET FILTER INPUT DOWN CONVERTER OUTPUT SET THE PN MATCH FILTER TAP COEFFICIENTS FRONT END PROCESSOR CALCULATES THE AVERAGE OF TWO CONSECUTIVE SAMPLES LOOP FOR EVERY SAMPLE IF THE INCOMING CHIP LENGTH PN CHIP LENGTH CORRELATION LENGTH INCOMING CHIP LENGTH OTHERWISE CORRELATION LENGTH PN CHIP LENGTH ENDIF CALCULATE THE CORRELATION VALUE ENDLOOP SET FILTER OUTPUT QUANTIZATION OF CORRELATION VALUE B 3 Symbol Tracking Processor SET SYMBOL TRACKING PROCESSOR STP INPUT POWER DETECTOR OUTPUT SET THRESHOLD THE FIRST DETECTION HAPPENS AT THE CORRECT LOCATION LOCATE THIS FIRST SYMBOL DETECTION AS FLYWHEEL VALUE LOOP FOR EVERY SYMBOL DURATION FETCH THE NEXT 3 STP INPUTS CENTERED AT THE LAST FLYWHEEL VALUE FIND THE MAXIMUM POWER IN THESE 3 STP INPUTS IF THIS MAXIMUM POWER gt THRESHOLD THIS IS A SYMBOL DETECTION THIS MAXIMUM OUTPUT IS REGARDED AS A STP OUTPUT 92 APPENDIX B SIMULATION APPROACH LOCATE THIS SYMBOL DETECTION AS A UPDATED FLYWHEEL VALUE OTHERWISE THIS MAXIMUM OUTPUT IS STILL BE REGARDED AS A STP OUTPUT SET CURRENT FLYWHEEL VALUE THE LAST FLYWHEEL S VALUE ENDIF ENDLOOP B 4 Commented Simulation Code 7 1 oo ooo oo JoJo JoJo do do do da da da da a a JJ Jd lodo JoJo Jo do do do doa la ad lodo o JoJo JoJo Jo a la da dedehedololololololele TJ dad do od do dd df do do oa a a a a a a o o a ao o Jo o Vo a a aa o oo
86. rate and longer range but they are best suited only for fixed terminals because of the need for alignment Signal propagation in the 18 19 GHz microwave frequency band is significantly con 11 CHAPTER 2 SPREAD SPECTRUM AND WIRELESS LANS strained by dense construction materials such as concrete and steel Signal transmission can be satisfactory throughout an open office area but sufficiently confined by the floors and walls to permit frequency reuse by other systems The disadvantage is that the radio transmitter and receiver at microwave bands are rather specialized and expensive As the signal in the ISM bands can penetrate buildings this system provides a larger coverage than IR and microwave LANs The inherent advantages of spread spectrum allow several spread spectrum LAN systems to operate in the same area Also the unlicensed op eration and the variable data rate transmission technique make it attractive The drawback is that the spread spectrum LAN must overcome current and future possible interference from other users of the same bands The inherent advantages of direct sequence spread spec trum will be presented in the next section The variable data rate transmission technique will be discussed in the next chapter 2 3 2 The Benefits of Using Direct Sequence Spread Spectrum Resistance to multipath fading and interference are the two inherent reasons for the use of spread spectrum in wireless LAN Resistance to multipath
87. re 3 6 received Shifted Register signal amp 4 1 2 3 EE z 54 Q aa D 1 2 3 JE Local PN Code Figure 3 6 A PN Matched Filter 3 2 4 Mean Acquisition Time Analysis Generally there are two analytical methods to derive the mean acquisition time a discrete time Markov chain model and a time domain combinational technique The former models the acquisition process as a Markov statistical process with a state transition diagram The transition probabilities of each state transition are calculated Using appropriate Markov 22 CHAPTER 3 DIRECT SEQUENCE SPREAD SPECTRUM SYSTEM DESIGN chain properties and signal flow graph connection reduction techniques the moment gen erating function of the acquisition process can be derived and the first and second order statistics of acquisition time can be determined from this moment generating function The Markov chain model which is a systematic method requires a background in statistical processes but it can be modified to model some complicated search strategies A detailed discussion of this method is presented in Pol 84 The time domain combinational technique provides more insight and understanding of the acquisition process Jib 91 Assume a single dwell serial search acquisition system Single dwell means that one fixed integration period is applied to generate decision statistics for every threshold comparison The dwell time or integration period is
88. roportional to the magnitude of the signal and it can not be eliminated by increasing the signal power We should be careful to choose a PN code with a good autocorrelation 25 CHAPTER 3 DIRECT SEQUENCE SPREAD SPECTRUM SYSTEM DESIGN function and also whose partial correlation is considerably below its autocorrelation peak By doing this we provide a large threshold margin for the acquisition and symbol decision circuit and will have small false alarm and missed detect probabilities Several kinds of PN codes such as Walsh codes M sequence codes Gold codes and Barker codes have been proposed for different applications of spread spectrum In the next section we describe the M sequence and the Barker codes These two codes have good periodic autocorrelation properties and their partial correlation is well below the autocorrelation peak In Section 3 3 3 three codes proposed by Zilog and Utilicom are compared in terms of their correlation performance m stages shift register 1 2 3 aa m Figure 3 8 M Sequence PN Code Generator 3 3 2 M Sequences and Barker Codes M sequences also called maximum length shift register codes are usually generated by the mean of an m stage digital shifted register with feedback as shown in Figure 3 8 The output sequence is periodic with length n 2 1 The most important property of this maximum length PN code is that its periodic autocorrelation function i
89. s also needed We will address the issue of the PN code in more detail in the following sections Spread spectrum systems are classified by the ways that the original data is modu lated by the PN code The most commonly employed spread spectrum techniques are the following Direct Sequence Spread Spectrum DSSS Frequency Hopping Spread Spectrum FHSS Hybrid Direct Sequence and Frequency Hopping Spread Spectrum Time Hopping Spread Spectrum Chirp Spread Spectrum In wireless local area network applications direct sequence and frequency hopping meth ods are used extensively and are discussed in this chapter 2 2 2 Two Widely Used Spread Spectrum Systems Direct Sequence Spread Spectrum Direct sequence spread spectrum DSSS involves modulo 2 addition of the information signal to a sequence of higher frequency This process is shown in Figure 2 2 where d t is the information signal and c t is the PN chip sequence signal with a higher frequency T t is the direct sequence spread spectrum signal by adding modulo 2 c t and d t The last graph of Figure 2 2 shows that the spread spectrum signal is despread back to CHAPTER 2 SPREAD SPECTRUM AND WIRELESS LANS the information signal d t by adding modulo 2 T t with a replica of PN chip sequence signal c t A typical direct sequence spread spectrum transmitter and receiver is shown in
90. s impulse like n when the time shift is zero and 1 for all other shifts This implies that the power spectrum is nearly white and hence the sequence resembles white noise which is the desired property for the spread spectrum system However the partial correlation function of an m sequence code is not as good as that of a Barker code 26 CHAPTER 3 DIRECT SEQUENCE SPREAD SPECTRUM SYSTEM DESIGN Barker codes are characterized by a partial correlation function that is negative or zero at all time shifts except at the zero time shift For this reason Barker codes are ideal for preamble acquisition Besides theirs periodic autocorrelation function is also impulse like just the same as for M sequence codes Therefore Barker codes are also ideal for information data detection Unfortunately Barker codes only exist for code lengths of L 2 3 4 5 7 11 13 Rao 88 and thus offer limited processing gain the maximum is only 10 log 13 11 1 dB 3 3 3 Correlation Function Comparison In this project we use the Zilog Z2000 Evaluation Board The 94 to perform spread spec trum processing Zilog provides an emulation program to demonstrate the operation of this board In this program an 11 bit Barker code one 64 bit code and another 63 bit code are suggested We have determined the partial correlation functions and periodic autocorrelation functions for each code as shown in Figures 3 9 3 10 and 3 11 A comparison of these figure
91. s shows that the Barker code has ideal partial correlation and periodic autocorrelation functions From the periodic autocorrelation function we find that the 63 bit code is actually a M sequence code Although its periodic autocorrelation is impulse like as desired its partial correlation will introduce noise into the acquisition circuit Thus we conclude that the Barker code is optimum for preamble and data spreading but is processing gain limited and that the M sequence code is optimum only for data spreading Considering that data may be transmitted in a noisy environment and that we want to use a longer PN code with larger processing gain in such circumstance to improve the acquisition probability the M sequence code is considered to be a sub optimum solution for the preamble spreading code The other 64 bit code is shown to have poor correlation properties and will greatly degrade system performance In our variable data rate transmission technique we will use the same PN spreading code for preamble and data The 11 bit Barker code is chosen for the high data rate and this 63 bit M sequence code for the low data rate 27 CHAPTER 3 DIRECT SEQUENCE SPREAD SPECTRUM SYSTEM DESIGN Partial Correlation o T T L 0 5 10 15 20 25 Time 15 T T T T c 2 10r a L j o 8 2 5r 7 2 lt Ko 2 ok js 4 5 0 5 10 15 20 25 Time Figure 3 9 11 Bit Bark
92. sumed for the initial bit of the output sequence QD gt E Delay T Figure 4 4 The Differential Encoder 33 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP For QPSK operation the differential encoder is more complicated There are four possi ble states in each of the inputs and outputs of the differential encoder The 16 combinations are shown in Table 4 1 Table 4 1 The 16 Combinations for QPSK Differential Encoder New input Previously Encoded Out I Q k 1 In I Q g O 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1 1 0 1 0 0 0 0 1 1 1 By a logical truth table transformation the encoded output can be expressed in terms of the input states and previous states as follows Out I k AC D BCD ACD BCD Out Q k BC D ACD BCD ACD 4 2 if In Lk B In Q k Out I k 1 D Out I k 1 4 3 For ease of understanding we can consider the signal constellation of QPSK signal I Q Note that here the constellation is Gray encoded so that the most likely errors caused by noise will result in a single bit error in the k bit symbol It is easy to find that Anglout k U1Ang in k Ang out k 1 4 4 34 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP Im 01 0 l Q9 200 A e R angl l Q 90 1 Q 01 180 LQ 11 270 1Q 10 10 Figure 4 5 The Signal Constellation of QPSK where
93. supply typical biasing circuit is shown in Figure 5 9 The RF choke increases the AC load of the biasing branch so it does not affect the amplifier s load The biasing resistor R is calculated as follows V 5 5 PS mU 5 8 T1 CHAPTER 5 RF HARDWARE DESIGN RF choke VY Y o V R 01uF IN AV 11 z po OUT O1uF Figure 5 9 MAV 11 Amplifier To reduce the power dissipated by the biasing resistor R we use a 8V supply instead of 12V then R is calculated to be 42 2 The power consumption is P 60 mA x 42 Q 0 15W 150mW 5 9 A conventional resistor with 1 4 W power specification satisfies this power requirement 5 5 Experimental Results In this section we show the outputs from an HP 8590 Spectrum Analyzer These results are obtained when Utilicom s 63 bit M sequence code is used as the PN spread code and the signal is BPSK modulated An on board 16 MHz crystal oscillator provides the receiver IF clock signal RXIFCLK The register at address 41y defining the number of TXIFCLK cycles per chip is set to 7 Thus from the 22000 User s Manual the PN chip rate is given by 16 MHz 2MH 5 10 741 t The first graph Figure 5 10 depicts the spectrum of the Tx Exciter input TxI which 72 CHAPTER 5 RF HARDWARE DESIGN is the digitized spread output signal from the Z2000 s PN spreader It is a polar baseband signal spectrum with the first side lobe 13 dB lower than the ma
94. t around the crystal path To avoid this an inductor chosen to be resonant with the crystal parallel capacitance at the designed overtone frequency is used across the crystal To prevent the crystal from operating at other overtones the LC network in this oscillator should have a relatively high Q providing enough selectivity to select only the desired overtone Another consideration is that the Colpitts LC oscillator 67 CHAPTER 5 RF HARDWARE DESIGN An Up Converter is Used 16 pins 16 pins BNC SMA Power 12 5 P 170MHz SMA pi v Ground 915MHz RF ha S PLL1 Enable Tx Exciter Up Converter d PLL2 Enable Power V PLL DATA 15 pins Ground 2 PLL_CLK Ground S Tx DATA I PLL1 Enable Tx_DATA Q PLL_CLK E PLL DATA 14 4 MHz Ref e Power 12v e N i 15 pi 20MHz IF pins SMB Grayson Receiver GIU SR An MC145190 145191 Frequency Synthesizer Evaluation Kit is Used 16 pins 16 pins 9 pins 9 pins 5 PDs Power 12 45 PILS Lnuble BNC P Ground PLL CLK 915MHz RF S PLL1 Enable MC 1451 a PLID Ee Tx Exciter PLL DATA 5190 conaoe Ground MC 145191 5 PLL CLK z PLL DATA BNC BNC E Tx DATAM 15 pins 170MHz S 2 9 Power 12v W Ground Q PLL1_Enable S PLL CLK N PLL_DATA 14 4 MHz Ref ad 15 pins 915MHz RF MHz IF BNC SMB Grayson Receiver SMB i Figure 5 5 Overall System Hardware Interface 68 CHAPTER 5 RF HARDWARE DES
95. th Z80 and 64180 intrinsic functions include lt intrz80 h gt 2 add the following two definitions Hdefine MIMIC DATA OxFO addr of mimic RBR fifo define MIMIC CONT OxF5 addr of mimic LSR Reg 3 modify the low level get function by changing the input output addresses char low level get void Read one char from I 0 Hardware dep 1 while input MIMIC CONT amp 0x20 100 APPENDIX C MODIFICATIONS TO THE IAR COMPILER return input MIMIC DATA Ox7f return In EOF indicate failure 4 save it back to the same name e In the iar iccz80 putchar c file 1 add a include file for both Z80 and 64180 intrinsic functions include lt intrz80 h gt 2 add the following two definitions define MIMIC DATA OxFO addr of mimic RBR fifo define MIMIC CONT OxF5 addr of mimic LSR Reg 3 modify the __low_level_put function by changing the input output addresses void low level put char c while input MIMIC CONT amp 0x01 while buffer not ready 5 output MIMIC DATA c 101 APPENDIX C MODIFICATIONS TO THE IAR COMPILER 4 save it back to the same name e Copy these two modified files into the iar lib directory e Compile these two files to create r01 object modules using the following commands iccz80 putchar ml z9 v1 b iccz80 getchar ml z9 v1 b ml specifies that the large memory model is used and z9 defin
96. the uniform generator to different value each time data in rand 1 data No 2 gt 5 rand is a uniform random number generator 1 and O are generated with the same probability 0 5 7h a a a a a a a o Do Do o o o o o o o a a a a a a a a a eee do oo do do o lo olo dole olo o lo o o lo lo o a a a a a a a a Input Processors INPSR 7 a a a a a a a o Do Do o lolo o o o a a a a a a a a a a a o Do do lolo do lolo le lolo dole olo o lo o dodo lo o a a a a a a a a inpsr out data in The Input Processor is disabled in BPSK 7 1 o ooo ooo JoJo do do do da da a a a a a ao od od oo do do do do a a a Jo o o JoJo do do o o a eel lh Differential Encoder DENCO 7 1 oo oo JoJo do JoJo do do da da a a a a a ao od od oo do do do a a a a JoJo JoJo do do o do o aa o lh N length inpsr out denco zeros 1 N preallocate the memory space 94 APPENDIX B SIMULATION APPROACH denco 1 xor inpsr out 1 1 The first is xor with 1 fori 2 N denco i xor inpsr_out i denco i 1 xor operation end denco out 1 denco The 1 is also transmitted denco out 2 denco out 1 change to polar format clear denco inpsr out MISI ISI dd ooo a a a a a a a a oa da ado do ooo fo da a a a a a o Jo do do oo o fo fa o o la oo ad h PN Spread Coder PNCOD 7 1 o do oo JoJo JoJo do do do da da a a a a a ad od od oo do do do o a a a JoJo JoJo do do do do o aa oo N length denco out pncod out zeros 1 N chip rate
97. um centered at the multiples of the sampling frequency Figure 4 9 In other words copies of the analog signal spectrum are shifted by integer multiples of the sampling fre 37 CHAPTER 4 OPERATION OF THE ZILOG Z2000 CHIP quency and then superimposed to produce a periodic signal spectrum By this mechanism a band limited signal with a frequency higher than the sampling rate can still be sampled without distortion as long as the bandwidth of the input signal satisfies the Nyquist sam pling theorem BW IRX IFCLK and the frequency is supported by the external ADCs Note that the BW here is referred to the single side bandwidth of the baseband signal Sampling Frequency Sampling Frequency gt Figure 4 9 Spectrum Aliasing after Direct IF Sampling of a BPSK Signal 4 3 2 Down Converter The numerically controlled oscillator generates a complex sine and cosine signal It moves the center frequency of signal spectrum replica which is the closest to zero frequency to zero frequency This can be done in two ways a positive NCO frequency moves the left spectrum replica A in Figure 4 9 to zero frequency and a negative NCO frequency moves the right one B in Figure 4 9 to zero frequency Here we need to talk about two sampling methods that Z2000 provides direct IF sampling and quadrature sampling In direct IF sampling mode only one ADC is used with the other one disabled or held to zero see Figure 4 10 Figure 4 9 and
98. work with Q about 10 the reason will be discussed later This leads to ie LG 5 5 TfL 10 70 CHAPTER 5 RF HARDWARE DESIGN From Equations 5 2 5 4 and 5 5 we obtain 1 Re 2nfCo 5 58 In our design we use C1 10 pF C2 15 pF The L is calculated to be 0 14 uH and Re should be at least 312 Q Although the transistor is an emitter follower and offers no voltage amplification and no phase shift the transformer in the equivalent circuit provides the in phase voltage am plifying The total phase shift of the loop is zero and the loop gain is given by Caron loop gain G a 5 7 where G is the voltage gain of the common collector transistor amplifier A G is related to the current amplification parameter 3 and the emitter resistor Re Its value is less than unity The loop gain is mainly determined by the ratio of C1 to C5 Adjusting one of the capacitors will enable the loop gain exceed unity and will excite the oscillator In practice this tuning method is replaced by fixing these two capacitors and using a variable capacitor across the inductor Figure 5 3 5 4 2 Amplifier Design We choose the MAV 11 monolithic amplifier for this design It has a wide bandwidth from DC to 1 GHz with output power up to 17 dBm The bias configuration is simple and its operation is rather stable For normal operation the MAV 11 amplifier requires a DC bias 5 5V at pin 3 and draws about 60 mA current from the power

Physical Layer Design for a Spread Spectrum Wireless LAN

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