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AU6802N1 USERS MANUAL

1. Z 2 o0ocr uoOioucowu o OQooooaoadoadadgaagagpao 39 21 DGND 40 c 26 DGND CSB 1 CLKIN RDB 1 XTAL INHB RD 4 VDD PRTY 1 SCK ERRHLD C DATA ERRSTB C SCSB FSEL1 1 OUTMD FSEL2 C XSEL2 VDD 1 XSEL TESTI 1 ACMD TEST2 4 MDSEL AGND 52 114 AGND 1 13 72 a 8 20 MNLO00392W00 2 2 Pin Description Symbol Description Remarks R1E External exciting signal input R1 Ref 4 2 3 R2E External exciting signal input R2 VCC Analog power pin Connect to 5V Ref 4 5 SINMNT Resolver signal SIN monitor output Input gain should be adjusted to be approximately 2 3 Vp p for this pin Ref 4 2 2 S4 Resolver signal S4 input pin S2 Resolver signal S2 input pin AGND Analog ground pin Connect to OV Ref 4 5 s1 Resolver signal S1 input pin s3 Resolver signal S3 input pin Ref 4 2 2 Resolver signal COS monitor output Input gain should be COSMNT H A adjusted to be approximately 2 3 Vp p for this pin VCC Analog power pin Connect to 5V Ref 4 5 Exciting signal output pin Output signal should be 2Vp p RSO 1096 which center voltage is COM pin level This signal will be used for input of exciting voltage booster amplifier COM output pin Output is 0 5 X VCC 5 voltage It must be 470pF decou
2. Time Rush in acceleration mode Refer specification P35 for detail about switching conditions entering to releasing from acceleration mode 66 MNLO00392W00 10 2 2 Switching the internal control during acceleration mode In this product switching the internal control during acceleration mode is done by proportional gain switching of compensator E Compensator configuration Compensator From synchronous detection 1 3 Integrator 1 PI control element K lt 1 gt Su While K proportional gain T integration time constant s laplace operator Difference between normal mode and acceleration mode Mode name Explanation Normal mode Normal operation mode except the acceleration mode below High tracking rate mode by enlarging the proportional gain K by Acceleration mode 32times of that in normal mode 10 2 3 Considerations in the use of acceleration mode 1 Change behavior when switching mode It is considered that the acceleration mode does not occur frequently in usual operation except in special cases But if it occurs actually by large angular acceleration is applied to the rotational axis it may seem that some abnormal operation has occurred momentarily at observing the output waveform cause the control loop gain suddenly change to 32 times 2 Miss operation by noise and error Note that even in the case that large angular a
3. A range of monitor signal Input R Gain Monitor signal Moreover a range of monitor signal max amplitude will be varied by the deviation of resolver transformation ratio and the deviation of input impedance In case of exceeding the max range 0 5 3 5Vp p of monitor signal amplitude it cause to detect abnormal sensor signal Example of monitor waveform At 0 EET CH2 1V 4 H T T 20us div 2 m 3 V p n p COSMNT GND n NEM SY gt MAE AAA pes COM 1 2VCC SINMNT GND av 1 2 360Y Filter Offset Record Length Trigger Smoothing ON CH1 0 004 Main 10K Mode AUTO BW 20MHz CH2 0 004 Zoom 10K Type EDGE CHI 4 CH3 0 00 Delay 0 1ns CH4 0 00 Hold OFF D 2us gt 19 MNLO00392W00 XIf potential difference between SINMNT and CONMNT generate by the deviation of R it cause a error source Please select appropriate resistor grade according to your system tolerance Example In case of there is a A COSMNT against a SINMNT 1 Error E A SIN20 rad Voltage difference 1 case A 0 01 then Error max 0 29 0 01 2 rad 2 DC bias resistor to detect breaking Ray Re When the signal line come down monitor output level must be below the fault detecting level 0 15Vcc 0 75V Without this bias resistor fault detection depends on its angle In fault case If normal side monitor signal go under the fault d
4. If it exceed 10 please make phase adjustment at external exciting signal input circuit Mi How to convert an angle from phase shift Monitor out signal DC coupling example Monitor out signal AC coupling example Stopped q Stopped CHISIYO CH2 IV CHSE5SV CH4 5V T us div CHIEIV CH2E1V CH3ESV CHdE5V l us div DC 103 DC 101 DG 101 at Aus div RC 101 RC 10 1 DG w1 DC 101 1Qus div SINMNT d deeds t roi NOME biebesseios NORMIMIMBZS GND Lol COSMNT xD GND pudo c aT 2 90us 12AT 344 B28kHZ d c T S R2E GND Da LL R1E GND gt Eoceno Ar errr rr ere rs E waa raa ara E n AAA Converted angle deg 360 deg X time shift us exciting F period us Above example exciting F 10KHz gt exciting F period 100 y 1 10KHz Time shift 2 9 Us Converted angle 10 4deg 360X2 9 100 99 MNLO00392W00 6 2 Check Point for Digital Output 6 2 1 Check Point of Output Angle Please check that the each digital output show your required format which you set and angle output data is changing with resolver rotation If angle output is not change while resolver rotation or output format is different with your setting please check a polarity of each digital input terminal Also if output angle data does not match with actual angle or output data is not stable refer section 6 1 and please check if there is no problem for resolver related connec
5. a FR Waveform max value Center of swing Amplitude level 2 lt VCC Waveform min value Center of swing Amplitude level 2 gt OV COM current OM lt 2mA R R 451 Assuming R2 10Vp p And also assuming R 4 7K i 20K 20K Center value of swing 2 5V X 2 24V 20K 20K 4 7K Assuming 3Vp p for R2E amplitude level 4 1K 3 Vp p 10 Vp p x R 10 9K911K Ra 4 7K Waveform max value 2 24V 3V 2 3 74V lt VCC OK Waveform min value 2 24V 3V 2 0 74V gt 0V OK COM current 2 5V 5V 1 11K 4 7K 0 48mA lt 2mA OK ub e MNLO00392W00 3 Considering the phase shift When any phase difference exists between the exciting component of Resolver signals S1 S3 S2 S4 and the external input signal for exciting Resolver R1E R2E the loop gain of R D conversion loop is equivalently decreased which may affect the performance of R D conversion That means that it spent long time to settle down the angle output or not be able to settle down the angle data In case of phase shift existing a phase adjustment circuit should be inserted into the RIE R2E line so that the phase difference is 10 degree or less As confirmation the phase shift may be adjusted between the exciting component of Resolver signal monitor terminals COSMNT amp SINMNT and the external input signal for exciting Resolver R1E R2E E How to convert an angle from phase shift Delay of
6. a probability that all of errors will be worst value considering process capability etc Also it might need excessive precision characteristic to satisfy system then system cost might lead to increase Then static error of resolver system estimates normally with root mean square RMS method sr Je e E np e id While s Static error of resolver system Ep Error of resolver Es error of resolver misalignment pp Static error of this IC itself E Resolver signal input circuit Resistance accuracy MEstimation of angular velocity proportional error Angular velocity proportional error of resolver system is caused by response delay of this IC and signal delay which depend on the filter circuit constructed in resolver input circuit This error is getting bigger with higher angular velocity and it is obtained by converting the angular displacement from total delay time at applied angular velocity Then it is estimated as the sum of individual errors due to the delay factor piy RDDLY iu FLTDLY uet While py Angular velocity proportional error of resolver system gpp y Angle error of this IC response delay re rp y Angle error of the filter time constant at resolver signal input circuit 69 MNLO00392W00 10 4 FAQ E Questions on the performance characteristic of R D conversion Q How much time it takes to convert R D Assumed as delay time from input of reso
7. 0 45 2 25V Internal control deviation V Test duration i i XIn case of VCC 5V There is an abnormal R D conversion situation control m deviation exceed the threshold i and if such situation is over 50 of test duration it is detected as fault Internal control deviation V Test duration 7 4 Error reset ERRHLD output is generated when an error occurred and it can be cleared by setting ERRSTB Low MError reset operation waveform ERRSTB ERRHLD Error condition Error cancellation Dot Error continues X Refer 9 8 for detail timing X Please use ERRHLD output after it is surely cleared by ERRSTB signal If the error is not released even after error reset please eliminate the true error factor according to the section 8 1 do MNLO00392W00 8 If you think troubleshooting In this chapter there are corresponding examples for the case of error detected by the function of fault detection and for the case of strange angle output data Please check these examples for your troubleshooting and operation check 8 1 In case of error detection When an error is detected ERR or ERRHLD output are H level refer to the following troubleshooting flow Firstly please perform to estimate reason of fault detection and error factor should be identified and eliminated according to the procedure of chapter 8 1 1 or later Regarding the operation of fault detection function please refer chapter 7 MW T
8. Equivalent to 3 33 4 s HM 12 Bits resolution setting Items Symbol Min Typ Max Unit Remarks and conditions Resolution 12 Bit A number of divisions per electrical angle Absolut f the electrical Conversion accuracy 4 4 LSB o F das IE AN input in a stationary state ACMD H Settling time 1 25 ms Input step of 180 electrical angle Settling range 8LSB max ACMD L Settling time 2 ms Input step of 180 electrical angle Settling range 8LSB max ME Capable of following angular velocity Maximum electrical angle ee deg Output response delay in a constant R bilit 0 4 0 4 A 10000min angle velocity Equivalent to 6 67 4 s 58 MNL000392W00 9 4 Failure detection characteristic Items Symbol Min Typ Max Unit Remarks and conditions Abnormal sensor signal breaking down of exciting source lines VCC VDD 5 0V Detection threshold 0 523 0 55 0 577 Compared to the monitor output High side xVCC xVCC xVCC voltage Min Max are reference VCC VDD 5 0V Detection threshold 0 428 0 45 0 472 Compared to the monitor output Low side xVCC xVCC xVCC voltage Min Max are reference Detection time 0 2 ms Time required detecting fault Abnormal sensor signal breaking of Resolver signal lines VCC VDD 5 0V i 0 143 0 15 Compared to the monitor output Detection threshold xVCC xVCC lar Min Max are reference Detection time 0 1 ms Time r
9. Normal signal is also XExample of VCC 5V under 0 5Vp p Resolver electrical angle 0 42 In case of short between S1 S3 or S2 S4 when normal signal amplitude go under the threshold value error can detect in such angle range MNLO00392W00 7 2 Abnormal sensor signal breaking of Resolver signal lines 7 2 1 Concept Detection In the resolver signal input circuit applying the external DC bias circuit will make monitor output level shifted from COM voltage of reference potential to GND side in DC Concept detection is to detect that voltage shift In view DC Normal resolver signal input circuit In view DC Breaking resolver signal input circuit AU6802N1 AU6802N1 COSMNT COSMNT SINMNT SINMNT 3 S4 S1 S2 Resolver DC R DC bias Rg or Rag In this case During breaking line VEXT GND entered to Resolver terminal S1 and S3 S2 and S4 are same DC differential amplifier circuit input Then monitor output potential Then monitor output that is differential amplifier shift to GND side against COM potential as reference output is COM potential as DC reference one 7 2 2 Circuit Configuration COMP x2 SINMNT E Detection result COSMNT 0 15 x VCC 7 2 3 Detection Principle The principle is comparison between monitor output and threshold voltage If voltage magnitude of SINMNT or COSMNT exceed down the threshold value 0 15 X VCC it is detected as fault situation
10. Output buffer pa ae du Geter Note Rising up falling down time of output means the time required to pass through the voltage between 0 3V and 2 7V 61 MNLO00392W00 9 8 Timing diagram E Timing of power ON Vrsth Rising up 100 V us max 5V Power supply for IC Resolver signal input Rotational velocity at start 20 000min max Vex turned on Initial tracking R D output Valid output Normal operation TA EM gt Acceleration mode ACMD H ACMD L i control 20ms max 100ms max Abnormality Invalid Valid detection function Error output 160ms max 3X This shows the boot sequence recommended 5V Power supply for ICs VCC VDD and the power supply for exciting amplifier of Resolver V xr should be turned on at the same time Or 5V should be turned on later Otherwise please refer the specification p18 22 E Timing of power OFF Vrstl 5V 5V Power supply for ICs lt Indefinite Internal reset R D output Output valid Normal operation 10 uw s max 52 MNLO00392W00 E Timing of bus control 0 min 40ns max 0 min CSB RDB DO D11 PRTY Data valid Output j 35ns max E Timing of INHB RD signal 100ns max 100ns max INHB RD DO D11 K Datalocked X Data locked E Timing of OUTMD signal 40ns max 40ns max OUTMD E Timing of PRTY signal 20ns max 20ns ma
11. Refer section 1 3 or 9 1 as R D conversion system and this method is one of the negative feedback control of closed loop configuration In such a system normally control deviation should be 0 This concept detection is that the excessive control deviation means out of control and this situation is detected as abnormal 7 3 2 Circuit Configuration COMP x2 Avoid sudden angular Error deviation acceleration Control 0 45 x ve 7 3 3 Detection Principle This detection principle is to compare the internal control deviation 1 and the threshold value If there are situation that the absolute value of internal control deviation is less than low threshold or bigger than high threshold 2 and if this situation is over 50 of test duration 3 then it is detected as fault X1 A internal control deviation signal can not be verified by this product s terminals X2 In case of VCC 5V anomaly detection condition is excess threshold less than 2 25 Vbo bigger than 2 15 Vbo of internal control voltage X3 ACMD H condition is 5ms ACMD L condition is 120ms 45 MNLO00392W00 7 3 4 Relationship of threshold and Typical abnormal detection pattern 1 Normal Internal control deviation amp Almost 0 J Veco X 0 55 2 75V In the state that have been successfully R D converted COM 2 5V control deviation is almost 0 i i X Then it is not detected as fault i i Veco X
12. XExample of VCC 5V case detection condition is under 0 75V of monitor output voltage 43 MNLO00392W00 7 2 4 Relationship of threshold and Typical abnormal detection pattern 1 Normal gt 5 COSMNT envelope kE cos 0 3 2 3Vp p E SINMNT envelope kE sin z ps In normal monitor signal case o both SINMNT and COSMNT exceed a threshold value then COM 2 5V it does not detect abnormal sensor signal Vec X0 15 0 75V Example of VCC 5V Resolver electrical angle 2 Detection pattern 3 Breaking between S1 S3 or S2 S4 XThis figure is the case breaking between S2 S4 XBy mounting DC bias resistance Monitor out V In case of breaking signal line monitor output will be less than threshold DC level and it is detected as fault Resolver electrical angle 3 Detection pattern Excessive monitor output XThis figure is excessive SINMNT signal case Monitor out V In case of SINMNT or COSMNT is excessive and cross the threshold it is detected as fault Resolver electrical angle 44 MNLO00392W00 4 Detection pattern Noise superimposed This figure is the case that SINMNT have noise superimposed Monitor out V Due to a noise monitor output cross the threshold down Then it is detected as fault Resolver electrical angle 7 3 Abnormal R D conversion Excessive control deviation 7 3 1 Concept Detection This product adopted digital tracking method
13. as even parity The number of 1 data between 1 12 and PRTY must be even 12bit mode example SCSB para KO XL AO AL AO A1 AO AL AO XE ALL I The number of 1 must D11 D0 the number of 1 is 7 be even Then PRTY 1 OWhile SCSB L fix output data repeat every SCK 16 clocks Then 14 16 data fix as 0 More than 16 sck case f SCSB sx LLU UU UU UU UU Un f Li cara AE tkezkospeskoskosko TAS BOE INO THE A A0 KO KOKE IRANE i LI SCK 16CLK Repeat every 16CLK gt 4 Serial output mode A B pulse mode The absolute angle detection is possible with serial out mode and A B pulse mode Power up starting time first absolute data read with serial output mode Since then absolute data can count UP DOWN with A B pulse data So you can reduce the number of CPU interface as 6 line serial 3lines A B Z 3lines Combination usage of serial mode and parallel mode can be used for fail detection of digital output data 32 MNLO00392W00 4 4 Clock Input 20MHz 4 4 1 Crystal Resonator Ceramic Resonator Below describes equivalent circuit of resonator section CLKIN is inverted signal of XTAL and these 2 pins connect to comparator input While there is cross point between XTAL voltage and CLKIN voltage internal CLK will be stable In this case it is possible to use another devise which does not list in recommended parts documented in specification P30 Figure25 Each cas
14. difference Resolver signal SIN connection might be reversed Please check Resolver S2 and S4 connection They might be reversed deviation of 90 Resolver signal SIN and COS line might be missed Please check Resolver S2 S4 and S1 S3 connection They might be reversed 54 deviation of 180 Resolver exciting signal might be reversed Please check Resolver R1 and R2 connection They might be reversed Direction difference and deviation 180 Resolver signal COS connection might be reversed Please check Resolver S1 and S3 connection They might be reversed MNLO00392W00 8 2 4 In case of rapid change in the output angle data and disturbance In case of rapid change in the output angle data or a sudden disturbance while rotation please follow below troubleshooting flow and identify the factors and then improve your system Troubleshooting flow of rapid change in the output angle data and disturbance Rapid angle change and sudden disturbance while rotation Please check whether error occurs or not during constant angular velocity rotation Error occurs Error does not occur Please check whether SINMNT or COSMNT waveform has some noise waveform distortion or not There are noise Looks normal waveform distortion If trouble occurs with ACMD H please check whether trouble also occur with ACMD L No problem with ACMD L Disturbance data by Might enter Migh
15. excite resolver directly 1 Example circuit for single power source Cf AU6802N1 Rf Vexr Q1 470pF Ci Ri vo Y COM 13 E Y 10k Q 10k Q 10kQ Cf Emitter resistance DC cut capacitor Bias circuit Current sensing resistor In case of V_ variation is expected by battery power possible minimum voltage must be considered as reference voltage aS MNLO00392W00 2 Example circuit for dual power source AU6802N1 M Method for setting constants Refer below for setting constants lt Description of symbol HVexr Vg External power supply For exciting voltage booster amplifier circuit Iker Exciting current of Resolver Riexr Resistor for setting exciting current of Resolver Veer Exciting voltage of Resolver Zro Input impedance of Resolver Specified value Vaso RSO pin AU6802N1 output voltage 2Vp p typ Step Calculate the exciting current by setting the exciting voltage based on the voltage of external power supply Vrer Ire X Zro Step Calculate the circuit constants based on the exciting current Irer 2 Vago XRf 7 RiexrXRi For single power source IREF VrsoXRf RiexrXRi For dual power source lt Setting condition gt Rus Geer 10 Q RfFZ50kQ CIXRiz5x10 s CfxRf amp 5x107 s The power supply for an operational amplifier should be the same as that for the transistor buffer 19 MNL000392W00 X Calculation method des
16. lt Jamagal TAMAGAWA SEIKI CO LTD Smartcoder AU6802N1 USERS MANUAL MNLO00392W00 Table of Contents Sarety Mattarss coser cut O E i UE mA Gia lane dare W ces diel g peeeste cieataos e EN ON 12 Product OVER e E tete P Be us 5 1 2 Prod ct Features occ vem eoe XE RE Ree etos ea o e Sess Ax dete tu eT 5 1 3 Block Diagram 5o se REESE CAES etes RATES Cei de OO RU arae s CA de lcs d 6 1 4 Spec Overview oi es eR EAR Ree a a es RE re ORA NU WU ER Y RE RR 6 1 5 Related documents 2 zo sil blew iae uot beams cir id rede T 2 Pin List Name and Functions ccccseseeceseccecsecceceseecesesenceseseneesenees 8 2 1 Pini Assignment AA veo bios e t vases tr ptu e pL n 8 2 2 Pin Description ista ER Rae vA ER SEA RON a E as OES 9 Gs oetupn3EloW Cree ete O erty io ce ae tay Aare oe cr Pane iP y 4 Peripheral CircurE Desipno Reed ISI zri12 4 1 Example of Peripheral Circuit o o ro 12 4 2 Resolver Interface soe essa at Me eee eal eee oe 18 4 2 1 Excitation Amplifier Circuit o ooo 13 4 2 2 Resolver Signal Input Circuit o ooo oo o 18 4 2 3 External Input Circuit for exciting the Resolver 2 4 3 Digital Interface gon torea ESTE GO URGERE RARE OR HEX GANE DW 2T MESS AA 2T 4 3 2 Output Interface os oe ee e eoe RE EI EA ANUS 30 4 4 Clock Input 20MHz Rs 33 4 4 1 C
17. monitor output Progress of monitor output Excitation signal cycle T 4s Excitation signal cycle T us R1E R2 waveform ime shift 8 u Time shift us Monitor output SINMNT or COSMNT Phase shift angle corresponding value F360 23 MNL000392W00 How to adjust progressing phase AU6802N1 Adjust with Capacitor Ci There might happen to exceed OV VCC range of R2E terminal voltage and it cause some failure Then the terminal voltage for R2E should not exceed 0V VCC by means of adding the external resistor R Rj to divide the voltage Mi The amount of progressing phase indication 1 AX xf xC x R R The amount of progressing phase Q scan degree Example When R2 10Vp p would like to set 10 for progressing phase excitation frequency 10KHz X R Rip concept is same as chapter 4 2 3 2 Assuming R 11K R 4 7K 10 arctan AP ee 27 x 10000 x C x LIK 4 7K _ 1 27m x 10000 x 11K 4 7K x tan10 0 00575u gt 0 0056 y Please adjust it with actual circuit exe MNLO00392W00 QHow to adjust delaying phase 1 Basic circuit to adjust delaying phase Use single power source for exciting amplifier AU6802N1 R1 R2 Insert capacitor Ci between R1E and R2E M The amount of delaying phase indication The amount of delaying phase Q arctan 27 x f x C x2x R Q0K 4 20K degree Rgi 20K 3 20K means parallel
18. t o b Fare l Data can read with p 35 controlling CSB RDB D 34 INHB DS 32 Data Bus D4 31 Ll D3 30 Refer to SPEC pl7 D2 29 Figure 13 Di 28 Kn Do 27 e PRTY 44 AA LLL LL e CSB Chip Select CS RDB 42 Read RD Please refer section 9 8 for 1 INHB RD 43 VINE NE 11 PRTY CSB RDB INHB signal timings OUTMD 19 M H Parallel mode 30 MNL000392W00 2 Pulse interface mode Pulse output mode is set by OUTMD L AU6802N1 SS Output data Dil 39 H gt A D10 38 B D9 37 Z D8 36 m U V Ww Settings are below D7 35 MEN osB L D5 32 U1 RDB L pa 31 gt y INHB H D 30 gt w1 D2 29 ERR D1 28 gt _ ERRHLD po 27 NC VDD CSB 41 RDB 42 INHB RD 43 OUTMD 19 4 L Pulse mode 3 Serial output mode OSerial output data is controlled by SCSB SCK 12Bit mode SCSB A sx LIUUUUUUUUUUUUT DATA Ae tA ez es es clero ao de Ue A y MSB LSB PRTY LI i Data read time 10Bit mode X Please refer section 9 8 for each signal timings MNLO00392W00 OPRTY is defined
19. 90 or 180 54 8 2 4 In case of rapid change in the output angle data and disturbance 4555 8 3 If the situation does not improve 0 0 cc eee een eens 56 SoElactorical charactertstioss nao eee eae 007 9 1 Absolute maximum rating o oooooorr ra 35 9 2 Power related characteristic 2 22 57 9 3 R D conversion characteristic lisse 58 9 4 Failure detection characteristic llle e 59 9 5 Analog signal characteristic 0 0 cece eee hs 60 9 6 DC characteristic of digital signal 0 0 cee eee eas 61 9 7 AC characteristics of digital signal o ooo ee eens 61 9 8 Timing MAZO A a E 62 VOTADA A Ent A MEM C RAUM o 65 10 1 R D conversion principle 0 0 0 I rs 65 10 2 Acceleration mode eee ehh hah 66 10 2 1 Effect of acceleration mode 0 ccc eee 66 10 2 2 Switching the internal control during acceleration mode 6T 10 2 3 Considerations in the use of acceleration mode o ooooooo 67 10 3 About the error of resolver system 0 0 cc cece ee s 68 10 31 Error sources c ore UE A E NUR Pa RU PIDE a 68 10 32 Error estimates senec v NER e ER REO Et a EUR 69 10 4 EAQ st we ein go EEG aa bos Sao EE Ao ME Wes 70 10 5 Terms and Definitions 20 0 0c lah 81 HIE AREVISIONUMISTORV AT AIT UP LUN I D NR TRUE AEN oa EL
20. A LL BiA ememr o X o Ko sit Meco Neira Undefined EU MNLO00392W00 E Questions about the digital input configuration Regarding UVW pole number selection bits XSEL1 XSEL2 Are these bits used for the absolute angle output mode of parallel out Do not use for the absolute angle output mode A Even if setting change between X1 X2 X3 X4 each absolute angle output shows one rotation data which means electrical angle 0 360 A specification said that RSO output frequency selection pin setting FSEL1 L FSEL2 L means VEL_MODE 10KHz What kind of setting is this In VEL_MODE DO D11 output switch to the register value of internal operation This setting is for internal method only We recommend not to use it by customer Q Would like to use accuracy 10bit mode Is there no problem to startup with MDSEL H It is no problem while 5V Power supply for IC VCC VDD and the power supply for exciting amplifier of Resolver Vg are turned on at the same time Or 5V is turned on later Another sequence which 5V power turn on before the power supply for exciting amplifier on is not recommended to start up with 10bit mode If you would like to use 10bit mode with this sequence firstly start with 12bit mode setting and after completing initial follow up you can change to 10bit mode by MDSEL setting For detail please refer p18 22 of specification Q Are there any notes in case of fixed off ACM
21. D L at acceleration mode Some instantaneous tracking delay or overshooting can not be avoided at the input of excessive angular acceleration by a sudden change of angular velocity or an external turbulence to the mechanical shaft of resolver i e shock etc In the power up sequence when exciting amplifier power is faster or same time for AU6802N1 power up initial follow up time will be extended from 20ms max which is ACMD H case to 100ms max Also if exciting amplifier power is later than Au6802N1 power up initial follow up time might need long time or inability to follow forever For detail of acceleration mode please refer section 10 2 Sih MNLO00392W00 Are there any notes in case of fixed on ACMD H at acceleration mode If acceleration mode occurs it may seem that some abnormal operation has occurred momentarily at observing the output waveform because the loop gain of control system changes significantly Judgment of entering to acceleration mode depends on comparison between the deviation of control residual polarity and threshold value Then even if non actual operation which does not occur rotational acceleration at mechanical axis resolver the acceleration mode may occur because following situations are acceleration condition from the perspective of R D like excessive magnetic distortion of waveform or an electrical error in the Resolver signal or some noise etc For detail of acc
22. EME 83 3 MNL000392W00 Safety Matters MNotes Smartcoder AU6802N1 is an integrated circuit i e electronic device with a high grade quality level suitable for use in automobiles trains etc and is designed for units involving direct control and safety of transportation equipment But the calculated failure rate is not zero Also there are some possibility to do unplanned work cause of noise static electricity wiring error etc Therefore the customer is to assume this responsibility considering the possibility of failure and to design multiple back up solutions within the equipment or system to avoid a serious system failure These application samples which listed in this manual are reference examples If you use these examples please make sure that you understand your system equipments and those functions and safety The information contained in this manual might be changed as necessary For the latest content please contact your local sales representative M Product Warranty 1 Warranty Period The warranty period for Smartcoder AU6802N1 is one year after shipping Failed products within this warranty period will be replaced with new one 2 Coverage Even if within the warranty period we will not take responsibility for the products which show quality degradation caused by deviant usage against this document or specification like below In case of usage of unguaranteed condition environment handling non
23. RSO output frequency selection pin RSO freq 20kHz 10kHz Ref 4 3 1 FSEL1 H L FSEL2 H H Other combination Digital power pin Connect to 5V Ref 4 5 These pins do not affect the operation directly Connect to the digital power VDD Analog ground pin Connect to OV Ref 4 5 Note Class means as follow DY I Digital input D O Digital output D O BUS Digital output 3 state output Ep MNLO00392W00 3 Setup Flow 4 Peripheral Circuit Design Page 12 Peripheral circuit 4 1 Example of Peripheral Circuit design Production 4 2 Resolver Interface 4 3 Digital Interface 4 4 Clock Input 20MHz 4 5 Power Source 4 6 Countermeasures for Noise 5 Connection Page 36 5 1 Example of Resolver Connection Connection 5 2 Example of Power Connection Check Point of Opec ion 6 Check Point of Operation Page 38 6 1 Check Point for Resolver interface 6 2 Check Point for Digital Output 7 Function of Fault Detection Page 41 7 1 Abnormal sensor signal Practical use breaking down of exciting source lines 7 2 Abnormal sensor signal breaking of Resolver signal lines 7 3 Abnormal R D conversion Excessive control deviation 7 4 Error reset 8 If you think that failure Page 47 8 1 In case of error detection 8 2 In case of wrong angle data 8 3 When the situation has not
24. Recommended power supply voltage Power supply voltage VCC VDD must be used at the same VDD 4 75 5 0 5 25 V potential Reset release voltage Vrsth 3 9 44 V Power On Reset release voltage Reset voltage Vrstl 3 7 4 2 V Power On reset voltage Reset voltage hysteresis Vrhys 0 2 V Vrsth Vrstl Supply current loc 30 45 mA Current consumption without load p MNLO00392W00 9 3 R D conversion characteristic HM 10 Bits resolution setting y 60 000 min angular velocity Maximum 64 000 rad s angular acceleration range electrical angle Capable of following angular acceleration range Items Symbol Min Typ Max Unit Remarks and conditions Resolution 10 Bit A number of divisions per electrical angle Absolute error of the electrical angle Conversion accuracy 2 2 LSB g input in a stationary state ACMD H Settling time 1 1 ms Input step of 180 electrical angle Settling range 8LSB max ACMD L Settling time 2 15 ms Input step of 180 electrical angle Settling range 8LSB max Maxi Capable of following angular velocity aximum E 240 000 min range angular velocity electrical angle Capable of following angular Maximum 256 000 rad s acceleration range angular acceleration electrical angle deg Output response delay in a constant Responsibilit 02 02 f J E 10000min angle velocity
25. S Digital output 3 state output Ei e MNLO00392W00 Class Description Remarks OUTMD H OUTMD L 12 12Bit LSB PRTY nada D O BUS 11 ERRHLD Ref 4 3 2 1 D O BUS 10 10Bit LSB ERR Ref 4 3 2 2 D O BUS 9 W1 Ref 4 3 2 4 D O BUS 8 Vi D O BUS 7 U1 D O BUS Digital ground pin Connect to OV Ref 4 5 OUTMD H OUTMD L VB w Ref 4 3 1 D O BUS 5 Ref 4 3 2 1 D O BUS 4 Ref 4 3 2 2 D O BUS 03 Ref 4 3 2 4 D O BUS 2 D O BUS 1 MSB D O BUS gt Digital ground pin Connect to 0V Ref 4 5 Chip selection pin CSB and Read pin RDB DO D11 and PRTY output state can be controlled D0 D11 PRTY out Valid High impedance CSB L RDB L Inhibit pin D0 D11 signal data state Through Hold can switch Other combination Ref 4 3 2 1 Ref 4 3 2 2 INHB RD z DO D11 signals Through Hold INHB RD H L This is even parity signal of the parallel output data 1 D O BUS 12 12Bit mode Or 1 4 10 10Bit mode in case of the number of H level data is even this pin output as L ERRHLD Error state hold pin Once this devise detect fault condition this pin output will be changed to H and keep it Error reset pin This signal reset the ERRHLD output state ERRSTB ERRHLD signal HOLD Clear HOLD state ERRSTB H L
26. ad of adjusting terminal S1 S4 please adjust SINMNT COSMNT voltage level which is 2 3Vp p with COM potential center Q Please tell us voltage specification of RIE R2E differential input signals Input signal voltage range of each terminals must be 0 VCC Regarding the differential signals R1E R2E it is operational while there is potential A B n i difference But it is recommended to apply over 4Vp p because applying higher voltage will be getting better comparator sensitivity Q There has been recommended to add 470pF capacitor between RSO and COM What happens if it does not exist A A purpose of this capacitor is stability of the conversion Without this capacitor R D output data will sometimes vibrate Q As a noise countermeasure would like to add normal mode capacitor Cy How much capacitor value do you recommend Cy insertion is required as counter action for some negative effect of electrical noise injection Actual cap value can not specify due to it depend on the noise level A Too large cap value might cause larger attenuation and phase change of resolver signals So Cy value variability might cause an imbalance between SIN and COS and it becomes error factor Be careful about it When adjusting the phase by input circuit of resolver exciting signals are there any impacts on the response characteristic A response specification is a converted value of dela
27. age saturation and abnormal waveform They are getting to be the error factor of R D conversion 79 MNL000392W00 H Questions about the application Q Is it possible to use with phase modulation type BRT resolver A No This product only support amplitude modulation type BRX resolver Q Is it possible to use multiple AU6802N1 which connect same one resolver It is basically usable if same exciting signal input to each IC s R1E R2E terminals However in case of error at external exciting amplifier and RSO output abnormality of A exciting signal source IC all R D system becomes unavailable Note that it must be required to put capacitor between RSO and COM regardless RSO output use or not Q How much cable length between resolver and AU6802N1 can we extend It can not to say simple because it depend on the type of cable and wiring but basically there are not much problem about cable length itself which is a few meters except for noise superimposed etc Example for extremely long cable length is about 150m extended application exist and proven Anyway it may require for phase adjustment or signal level adjustment etc because long cable might cause phase shift or amplitude change due to cable capacity 80 MNLO00392W00 10 5 Terms and Definitions Te
28. appens when the leakage flux of the motor passes through the resolver lts effect will be bigger turbulence of digital output which will generate error Tek 5 00MS s 2 Acqs Stopped CHIE Wy Ch3 Zoom 1 0X Vert 0 5X Horz SINMNT MUITO 1 L00V 4 1 00 M20 0ps Width CN T i i E 5 00V Filter Offset Record Length Trigger 11 Smoothing 4 cH oov Main WK Mode SGL S BW 20fiz CH2 0 00V Zoum 2K Type EDGE CHI Y CH3 0 00V Delay 9 0ns CH4 0 09v Hold Off MINIMUM Basic waveform 10KHz deformed MWaveforms of electrical noise Electrical noise happens when the spike noise caused by PWM drive of the motor affects signal lines Turbulence of digital output will not be so big but it will generate error depend on the size of noise Basic waveform 10KHz was not changed much But spike noise was overlapped 35 MNLO00392W00 5 Connection 5 1 Example of Resolver Connection E Connection example Used RSO as excitation source Vexr AU6802N1 Excitation amplifier circuit External exciting signal input circuit Sensor Sensor cable Circuit board 36 MNLO00392W00 MW Connection example Used external oscillator as excitation source Vexr AU6802N1 j ms A A m E Resolve S2 S2 Si 001 W 53 S3 R1 HR RSO i Excitation amp i amplifier COM TER circuit i i I I I I I l f External excit
29. cceleration does not apply acceleration mode may occur due to excessive magnetic electrical distortion of waveform electrical error noise in the resolver signals If unexpected acceleration mode occurs by error or noise and your system have problem due to discontinuity of angular output data please correspond by ACMD terminal setting And refer specification for ACMD setting sequence Op MNLO00392W00 10 3 About the error of resolver system Resolver system with this product causes an error against actual angular position by resolver accuracy this Smartcoder accuracy peripheral configuration error etc In this chapter explain the error sources of resolver system and general estimation method of total error 10 3 1 Error sources There are error sources of resolver system like the following sources accuracy R isali Static error by mounting accuracy when user esolver misalignment install the resolver Static error of the resolver itself generated by manufacturing variation etc E R id R Static error of the resolver itself generated by rror sources esolver side esolver error manufacturing variation etc R D side R D static error 12Bit mode EALSB E Angle 0 85 SOURCES accuracy 1OBit mode 2LSB E Angle 07 IC response delay generates an error according to the angular velocity R D response Delay at constant angular S c min velocity T UTERE 000 min Static error by ampl
30. connection resistor value of Ray and 20K 20K Example When Ry Ra 47K would like to set 10 for delaying phase excitation frequency 10KHz Ra 20K 20K 21 6KQ 10 arctan 27 x 10000 x C x 2x 21 6K _ tan10 27 x 10000 x 2 x 21 6K 65p gt 68p Please adjust it with actual circuit e MNLO00392W00 2 Basic circuit to adjust delaying phase using dual power source for exciting amplifier AU6802N1 Insert a capacitor C M The amount of delaying phase indication The amount of delaying phase Y arctan 27 x x Cj x R R degree R R 2 means parallel connection resistor value of R and Rip Example When R2 10Vp p would like to set 10 for delaying phase excitation frequency 10KHz AR R concept is same as chapter 4 2 3 2 Assuming R 11K R 4 7K Then R R 3 3K Q 10 arctan 27r x 10000x C x 3 3K tan10 27 x 10000 x 3 3K i2 850p gt 910p Please adjust it with actual circuit cM MNLO00392W00 4 3 Digital Interface 4 3 1 System Setting AU6802N1 ll Setting for resolution Resolution 10 bits 12 bits MDSEL H x d Setting for digital output resolution Parallel Pulse Serial 10 bits 1024 split Number of pulse 256C T 12 bits 4096 split Number of pulse 1024C T H Setting of internal control mode Acceleration mode ON OFF ACMD H I Set the i
31. cribing in specification is based on DC circuit concept Resolver is a AC circuit and that input impedance R REsISTANCE jX CONDUCTOR cause voltage phase shift and current phase shift Also there are some impacts at parallel connection of Rf and Cf Then it might not get exact exciting voltage value as calculated In such a case please adjust each constant by yourself Voltage can be adjusted by R value And it is effective to make pre validation using circuit simulation like SPICE Example Vext Battery 12V 8V 16V fluctuation Excitation frequency 10KHz Resolver Spec Input impedance 769 R part 18 Q L part 1 18mH Let s excite this resolver with current type amplifier described in P14 Vext define as 8V use minimum fluctuation Saturation voltage of OP AMP assume as x0 8 supply gt 8VX0 8 6 4V Regarding R1 GND and R2 GND Set amplitude center as 4V 8VX 1 2 Set amplitude as 4Vp p Then target amplitude is set as R1 R2 8Vp p R2 GND R1 GND Voltage Max under 6 4V 4V center 8V X 1 2 According to the formula of P15 Resolver excitation current Iker 0 11Ap p 8Vp p 76 Q Rexr 4 7Q lt Resolver input impedance 7602 10 Rf 100K Then Vaso X RE R xr xRix1 2 Iker Ri Vaso x Rf 2Vp px100K lt R mxr X Ire X 1 2 4 7x0 11x1 2 Example of circuit simulation 774K lt gt Resolver input impedance 18 Q 1 18mH Please adjust at actual c
32. e you select resonator included in recommended one we recommend you to ask resonator company about optimal constant oscillation of your actual print board Cause there might change their oscillation condition due to wiring pattern difference AU6802N1 equivalent circuit of resonator section an e LC K 7 Internal CLK e 4 4 2 External Clock In the case of external clock clock must connect to CLKIN 25 Pin and XTAL should be open NC CLKIN pin is TTL level input X 20MHz clock might be noise source It is effective for EMC countermeasure to make signal pattern wider and shorter also guard by GND line 33 MNLO00392W00 4 5Power Source AU6802N1 DC 5V OV Power source is single supply t9V 5 Analog power line and Digital power line can connect to same power line If you set separate power line for analog VCC and digital VDD there must be no potential difference between VCC and VDD or AGND and DGND Also power switching power on or power off should be done simultaneously Above figure is example of power connection No need to collect analog power line or digital power line Regarding 0 1uF capacitors it should be located close to AU6802N1 device as much as possible 34 MNLO00392W00 4 6 Countermeasures for Noise Below waveforms are measured actually Countermeasure for noise must be done in accordance with the specification P34 contents MWaveforms of magnetic noise Magnetic noise h
33. each application it needs to set appropriate monitor signal level with gain adjustment of resolver input signal to fit R D conversion effectively Also it need to have external DC bias resistor activating the function which detect any breaking of Resolver signal lines S1 S4 mounted in AU6802N1 devise In this chapter show you example of resolver signal input circuit MExample of resolver signal input circuit AU6802N1 Resolver signal level Mexr Monitor Output 1 COSMNT NN SINMNT 3 S4 i 1 70kQ j 70kQ S1 S2 ZF i 1 000pF x 2 P Common mode Gain setting resistor capacitor Normal mode DC bias resistor to capacitor detect breaking Specification of Differential Amplifier Input Resistance Resistance ratio Gain 18 MNLO00392W00 1 Gain setting resistor R R R value is defined to put in MAX range 2 3Vp p of monitor output 70K Monitor amplitude Vp p Resolver signal amplitude Vp p X while R R R R 20K Example Resolver spec Exciting voltage AC7Vrms transformer ratio 0 286 Use it as exciting voltage 10Vp p monitor output max amplitude assumed 2 5Vp p Resolver output max 2 86Vp p 10Vp p X 0 286 then 2 5 Vp p 2 86Vp p Vp plX D gt 60K R 20K In this case due to the resistor value variability of AU6802N1 differential amplifier monitor output max amplitude can be the range described in below table
34. eleration mode please refer section 10 2 MS MNLO00392W00 M Questions about the function of fault detection Q Does the fault detection result affect the behavior of R D conversion Does not affect The fault detection function is independent to R D conversion so fault A detection result does not give a constraint on the output of R D conversion It will continue to operate R D conversion as abnormal condition When the error reset at ERRSTB How long time do we need to set reset situation ERRSTB L A Minimum 40ns Same as maximum time to be extended ERRHLD signal Q Does the error reset function by ERRSTB affect the behavior of R D conversion Does not affect ERRSTB is a function to reset ERRHLD output only DC bias resistance was connected in reverse polarity Nevertheless error detection looks work at signal disconnection situation Why is the error detected Depending on the angle there might be detected as error of abnormal sensor signal Because they are connected in reverse polarity in disconnection case monitor output A voltage expect shift to VCC side Then correct R D conversion can not operate and it is considered that abnormality have been detected by error detection function of abnormal R D conversion When monitor output exceeds 3 5Vp p it is detected as fault And are there any other negative effect It is considered about volt
35. eliminated according to the below troubleshooting flow Troubleshooting flow for Abnormal R D conversion detection Abnormal R D conversion Excessive control deviation detected Please check phase shift between differential signal R1E R2E and monitor signal SINMNT or COSMNT Refer 6 1 3 y Phase shift greater Phase shift less than 10 Please check whether error detect only startup or not Only startup time Error detect after startup also y Please check whether output digital data settle down or not Break of control loop i by phase shift during synchronous detection or degradation of the dynamics Might be excessive Might be inappropriate sequence of power up Resolver signal angular acceleration Reconsider power up timing or follow the Avoid a rapid change in appropriate power up sequence angular velocity or set Refer specification p18 22 acceleration mode Adjust phase shift value at Resolver signal input circuit Refer 4 2 3 50 MNLO00392W00 8 2 In case of wrong angle data Despite the rotating Resolver angle output data is not changed or output shows the different format data or output data is not fit to actual angle In such case please follow below troubleshooting flow and identify the behavior of the output data Then please improve this error condition by the procedure described in chapter 8 2 1 and later ll Troubleshooting flow of wrong digital an
36. equired detecting fault Abnormal R D conversion Excessive control deviation VCC VDD 5 0V Detection threshold 0 523 0 55 0 577 V Compare to the absolute value of internal High side xVCC xVOC xVCC control deviation Min Max are reference VCC VDD 5 0V Detection threshold 0 428 0 45 0 472 V Compare to the absolute value of internal Low side xVCC xVCC xVCC control deviation Min Max are reference Acceleration mode ON It is judged as an internal error when the 5 probability of excessive control residuals 50 in the average value for the period Required time period for judgment 3 o Acceleration mode OFF It is judged as an internal error when the 120 ms probability of excessive control residuals 50 in the average value for the period X In case of the continuous time of failure is shorter than above detection time there is possibility not to detect failure 99 MNLO00392W00 9 5 Analog signal characteristic Items Symbol Min Typ Max Unit Remarks and conditions Signal source output for exciting Resolver RSO VCC VDD 5 0V COM 2 5V Balanced potential to COM Frequency selection setting FSEL1 L FSEL2 H Fo External CLK IN Frequency Frequency selection setting FSEL1 H FSEL2 H Foue External CLK IN Frequency Output voltage Output frequency 1 Output frequency 2 Load impedance Common output COM Output vo
37. esolver multiplication factor and the setting number of poles for UVW is below Resolver XM UVW poles 4X x1 2X x2 1X x4 Each combination output 4 pulse of UVW every 90 degree while one revolution of Resolver 29 MNL000392W00 4 3 2 Output Interface 1 Parallel Output mode Parallel output is set by OUTMD H MParallel I O interface mode Stand alone Interfaced by dedicated I O AU6802N1 ST Output data om 39 KS 01 bio 38 92 D9 37 gt gt __ 63 ps 36 c 4 CSB L or 35 5 RDB L pe 34 Er Paralel Output Data can read with D5 32 gt 97 y pa 31 gt 68 controlling INHB D3 30 9 D2 29 9 10 bi 28 11 po 27 12 Refer to SPEC p17 PRTY 44 9 Parity Output Figure 1 4 CSB 41 RDB 42 s 4 p INHB RD 43 S Inhibit Input L fixed data OUTMD 19 je H Parallel mode Please refer section 9 8 for Pp1 11 PRTY INHB signal timings HM Parallel BUS interface mode Bus output interfaced by BUS line DU 5eseieesereees D12 lt __AU6802N1 D11 39 Re D10 38 D9 37 kcc
38. etecting level fault can detect as breaking of exciting source line Estimated value of Ray Rg is shown below with some Vyg 4 voltage 3 Normal mode capacitor Cy While basic circuit doesn t have Cy it can improve electrical noise But gain resistor Ri and Cy work as filter it causes one of factor of phase shift Time constant 2 X Ri R 4 20K X Cy R4 R 4 20K means parallel connection of R and R 4 20K This capacitor has an impedance 1 w C4 and it affect signal level also Deviation of capacitor is much worse than the deviation of resistor please select the small deviation parts or small capacitance parts to avoid impact of signal level 4 Common mode capacitor Cc Standard usage is putting 1000p capacitance between S1 S4 signals and GND 20 MNLO00392W00 4 2 3 External Input Circuit for exciting the Resolver AU6802N1 R D conversion include synchronous detection function which use a phase signal with the external input RIE R2E of resolver excitation signal Then R1E R2E terminals need to have same phase input signal with the carrier of resolver signal In this chapter there shows example external input circuit of resolver excitation signal 1 Basic circuit sample using single power source for exciting amplifier AU6802N1 R1 R2 External resistor Ref VEXT RRi Rae 5V system O kQ 12V system 47 kQ 24V system 120 kQ In case o
39. f direct input for RIE R2E exciting signal level might exceed VCC and it cause some failure So please note that the terminal voltage for RIE R2E should not exceed VCC Power supply voltage by means of adding the external resistor Rp Rp to divide the voltage Rei Rr2 47KQ example Stopped q CHIs5Y CH2 s5Y CH3sS5y CHa 5Y 20us div DC 103 DC 101 DE 10 1 DC 10 1 20us div T A A HORMBDMS ZS R1 GND a i 7Vp p n x e 6V center R2 GND E EN e e R1E GND NEM 7Vp p X 20K 20K 20K 20K 47K bo e R T4 MT gt is as 2 76Vcenter R2E GND ur uu e SN dus m NET 6V x 20K 20K 20K 20K 47K MAX side 4 37V 2 76V 3 22Vp p 2 lt VCC MIN side 1 15V 2 76V 3 22Vp p 2 gt GND ee MNLO00392W00 2 Basic circuit sample using dual power source for exciting amplifier AU6802N1 0 1 uw F Riz In this dual power source case an exciting signal is OV center So it needs to make R1E R2E terminal input level as shifting DC level There might happen to exceed OV VCC range of R2E terminal voltage and it cause some failure Then the terminal voltage for R2E should not exceed OV VCC by means of adding the external resistor R R to divide the voltage DC cut Capacitor Ci gt 0 1 y R around 3 3 4 7K around 10 of 20K2 20KQ 20K 20K 20K 20K R Center value of swing V COM V Xx Ri Amplitude level Vp p R2 Vp p x
40. gle data Wrong digital angle output Please check the behavior of the output data during one Resolver rotation Rapid changes in disturbance data A B pulse sudden Indefinite free run can Rotation direction Fixed output data f dp not get one rotation difference deviation of data 90 deviation of 180 To 8 2 1 To 8 2 2 To 8 2 3 To 8 2 4 disturbance Eu MNLO00392W00 8 2 1 In case of angle data output is stopped In case of angle output data is completely stopped please follow below troubleshooting flow and identify the factors and then improve your system ll Troubleshooting flow of fixed output Angle output data is completely stopped Please check whether external clock input is surely connected to CLKIN terminal or not What type of output is down Parallel output down Serial output down Please check INHB signal polarity L level H level No clock input IC Setting is fixed data Might be inappropriate Might be inappropriate operation stopped by setting of CSB or RDB setting of SCSB or the resonator circuit SCK unmatching lt lt lt a lt a i i SCSB or SCK should Enter the appropriate Please check data CSB or RDB terminal changing with INHB should not be H level be entered appropriately clock or adjust the resonator circuit H level S02 MNLO00392W00 8 2 2 In case of indefinite free run can not get one rotation data In case of angle outp
41. improved MNLO00392W00 4 Peripheral Circuit Design AU6802N1 require some peripheral circuit to get digital angle data In this chapter we explain the design method and important point for required peripheral circuit design 4 1 Example of Peripheral Circuit Resolver BRX Digital Smartcoder angle data BEEP AU6802N1 Exciting voltage i booster Amp E DE per odi Clock A ae External power DC 5vV single power supply source 12s MNL000392W00 4 2 Resolver Interface X Examples mentioned in this articles shows only the concept of basic functions Please note that each application might have their each individual requirement Therefore the circuit configuration and the decision of constants for practical resistors and the function of protection for input output circuits etc should be designed for each application 4 2 1 Excitation Amplifier Circuit Resolver BRX type is the sensor which generates the amplitude signal responding to the rotational angle of output winding by applying excitation signal to excitation windings Then exciting amplifier circuit to excite resolver need to get resolver output signals There are 2 type of excitation amplifier circuit current control type and voltage control type Show merit demerit of each method in below Please determine appropriate method for your system considering them Excitation Amp Merit Demerit Current control Preve
42. ing signal input circuit i I I I I I i I I I I 1 jj Sensor Sensor cable Circuit board Resolver output signals S1 S2 S3 S4 are connected to each corresponding AU6802N1 terminals S1 S2 S3 S4 through the resolver signal input circuit Resolver input signals R1 R2 are connected to each corresponding AU6802N1 terminals RTE R2E through the external exciting signal input circuit Regardless of whether RSO output use or not there must be capacitor connection between RSO and COM 5 2 Example of Power Connection Refer the section 4 5 37 MNL000392W00 6 Check Point of Operation 6 1 Check Point for Resolver Interface 6 1 1 Check Point of Excitation Signal Check your resolver excitation signals R1 R2 whether the resolver is excited with your designed amplitude or not If signals are small or saturated situation please review your excitation amplifier circuit again If there are no signals please check the connection to resolver and power supply status 6 1 2 Check Point of Monitor Signal Amplitude 1 Check point of amplitude change Observing the waveform of resolver exciting signals and monitor output SINMNT COSMNT please check if the monitor output have a same frequency carrier of excitation signals After then rotate the resolver please check that monitor signal amplitude is changing with corresponding resolver angle If there is no signal or no amplitude change by rotation
43. ing of Resolver signal lines 43 L2 le Concept Detection a AC WES a ios 43 7 2 2 Circuit Configuration eee ehh hs gt 43 7 2 3 Detection Principles ete eA He eR Bada eoe es 43 7 2 4 Relationship of threshold and Typical abnormal detection pattern 44 7 3 Abnormal R D conversion Excessive control deviation 45 13 1 Concept Detection x DIS ei UE BS ee Ce be E S E UE S 45 7 3 2 Circuit Configuration hh hes 45 R33 Detection Principle 3 uere dC eS xe tt e ce Ae S otk 4b5 7 3 4 Relationship of threshold and Typical abnormal detection pattern 46 T A Error reset uis Aan hom beh beh Gh ow ae tetera kook A eta ot NG aas Balada ane 46 8 If you think troubleshooting ecce 47 8 1 In case of error detection naa E a ee eee hs 4T 8 1 1 Suspicion of Abnormal sensor signal breaking down of exciting source lines 48 8 1 2 Suspicion of Abnormal sensor signal breaking of Resolver signal lines 49 8 1 3 Suspicion of Abnormal R D conversion Excessive control deviation 50 8 2 In case of wrong angle data o o e e 8 2 1 In case of angle data output is stopped 0 0 ccc eee eee 152 8 2 2 In case of indefinite free run can not get one rotation data 53 8 2 3 In case of rotation direction difference deviation of
44. ircuit Cf 100p Emitter resistance 4 7 Q Bias resistance 1KQ Then around Ri 460K2 8Vp p between R1 R2 qe MNLO00392W00 Single power source Vexy 12V Waveform sample Stopped El 2 X CHIS5Y CH2E5V 3 M th 20us div DC 101 DC 11 1 2 20us div i i i NORM 50MS s R2 GND R1 GND 7Vp p 14Vp p Stopped CHI 5V CH2 5 DC 10 1 20us div 20us div NORM 50MS s YOKOGAWA 4 107 d 10MS s 100H5 div R1 R2 1 00 U diu DC Full CH4 10 1 2 00 U diu DC Full Edge CH4 Normal 9 70 U 17 6V center 1 2 V 7 OV center The wrong constant selection cause wider amplitude and waveform distortion will be occurred by OP AMP or Tr saturation voltage etc Need to avoid distortion Rail to Rail OP AMP type can set more wider active output voltage without distortion generation It might happen to have R1 GND R2 GND oscillation due to OP AMP characteristic If this kind of wave is observed DC cut Capacitor Ci might cause unstability of DC current then insertion of resistor between Ci output and GND will be effective to stabilize it Additional resistor around 100K Q MNLO00392W00 4 2 2 Resolver Signal Input Circuit R D conversion of AU6802N1 will be done with monitor output SINMNT COSMNT While voltage level of resolver signal is different with
45. itor Please check the signal level connection status Refer 4 2 2 Refer 5 1 Please check connection of exciting line exciting amplifier circuit status supply voltage UU 48 MNLO00892W00 8 1 2 Suspicion of Abnormal sensor signal breaking of Resolver signal lines In case of suspicion the breaking of resolver signal lines true error factor should be identified and eliminated according to the below troubleshooting flow HM Troubleshooting flow of detecting break of Resolver signal lines Abnormal sensor signal breaking of Resolver lines detected Please check whether SINMNT and COSMNT amplitude center is VCC 2 or shifting to GND Shift to GND Not shifted Please check whether MAX signal amplitude of SINMNT or COSMNT is within 3 5Vp p or not Exceed 3 5Vp p Not exceed 3 5Vp p Breaking of Resolver line Might be inappropriate signal Might be detected fault by Refer pattern level noise superimposed Refer pattern Refer pattern 5 Please check connection Please adjust monitor signal Avoid noise superimpose itself Or add special sequence in between S1 S3 or S2 S4 Refer 4 2 2 upper system to disable fault detection by noise which show periodic status of signal line continuity level 49 MNL000392W00 8 1 3 Suspicion of Abnormal R D conversion Excessive control deviation In case of suspicion the abnormal R D conversion true error factor should be identified and
46. itude imbalance between SIN Resolver signal input input and COS input circuit Resistance accuracy Filter delay time constant generate an error Resolver signal input according to the angular velocity circuit Filter time constant 7 J j Extemal magnetic field affect the flux of the Environmental External magnetic field j resolver and it cause error factor 68 MNL000392W00 10 3 2 Error estimates Total error of the resolver system using this IC is a combination of potential errors which include static error that typically come from resolver itself or this IC itself and proportional error of angular velocity that come from delay of this IC or peripheral circuit depending on the angular velocity Erm FEsr Epy t While 77 Total Error of resolver system sr Static error of resolver system py Angular velocity proportional error X Each error might have different unit and there are concepts which are Number of multiple Mechanical angle Electrical angle Refer section 10 5 for each term When estimating the error please be careful to fitting the unit M Estimation of static error Considering the estimation method of resolver system static errors which include resolver accuracy and error of this IC itself and the variation of the peripheral circuit or configuration the easiest way is taking the sum of the maximum error caused by factors But it is difficult to assume
47. listed in this manual or specification In case of Remodeling Repair which is not done by Tamagawa seiki In case of misusing this product In case of unforeseen matters which can not expect at technology level of shipping age A MNL000392W00 1 Introduction 1 1 Product Overview Smartcoder AU6802N1 is an R D Resolver to Digital conversion IC used with a brushless Resolver such as Singlsyn Smartsyn etc It converts the electrical information analog signal corresponding to a mechanical rotational angle of the Resolver to the corresponding digital data and transmits it It was developed as simple usage low cost and having high quality enough to be used on vehicles while maintaining high reliability that the Resolver Synchro system has had conventionally It provides you wide range applications for angle detection 1 2 Product Features M Wide operating temperature range for automotive quality 40 C 125 C M Real time output High tracking rate 240 000min 10Bit resolution M Single power supply of DC 5V lil Small size light weight 10 X 10mm Pin interval 0 65mm 52pin TQFP Mass 0 3g M Built in test to detect following faults abnormal sensor signal abnormal R D conversion W Selectable output mode Pulse Parallel Bus Serial output W Selectable resolution mode 10Bit 12Bit W Selectable setting a number of poles for UVW X 1 2 3 4 HM Selectable clock input 20MHz External CLK input Crystal resonato
48. ltage Resistance variation 1 Input frequency Input voltage range 0 B 5 V COM 2 5V Resolver signal input S1 S4 Input resistance ar no Input resistance ratio ase 100 f ror fo Resistance variation 1 Input gain o amas sof Internal feedback R Internal input R I 1 Input voltage 1 Vp p Differential input Resolver signal monitor output SINMNT COSMNT 10 kQ Load impedance Allowable load impedance of SINMNT COSMNT 60 MNLO00392W00 9 6 DC characteristic of digital signal Items Symbol Min Typ Max Unit Remarks and conditions Recommended input H voltage for High level input voltage Vu 20 VDD MD P aj all digital input terminals Recommended input L voltage for Low level input voltage Vi V are i s all digital input terminals Pull t f digital input A estamos kQ ull up resistor value of digital inp terminal ES High level output voltage Io OmA Low level output voltage VoL 0 4 V Ig 8mA 9 7 AC characteristics of digital signal Items Symbol Min Typ Max Unit Remarks and conditions External CLK input frequency Fork Serial CLK input frequency PRR meesme w o D FE Input falling down time o 10 mo Output rising up time r 12 m ns C 15pF Output falling down time ow 12 22 ns C 15pF e EEES Propagation delay time 1
49. lver signal to output of its angle data Then it will be as follows M Resolution 12Bit mode 6 66 Us max M Resolution 10Bit mode 3 33 Us max Response spec is converted value from above time to the angular displacement of constant speed of rotation Q What is the frequency period of the output data update rate A It is 5MHz 200ns while CLK input is 20MHz Q Please tell us a frequency response of negative feedback loop which realize R D conversion Bandwidth of control system is approximately as follows and the response performance against a rapid angle change that is above following frequency is 40dB dec characteristic A M Resolution 12Bit mode 800Hz M Resolution 10Bit mode 1 200Hz Q What happen to the output data in case of resolver signal input is above maximum angular velocity R D is unable to work tracking with angular velocity which is over specification so it is A unable to follow the rotation of the resolver Then A B Z and angle output O becomes irrelevant data Bog MNLO00392W00 What is settling time The time to respond when resolver signal input change as step like 180 This is one of the indicators which shows control system performance of R D converter In normal operation there is no chance to work this step 180 response for the actual resolver signals Angle Settling time 180 AS z 0 gt Time In the
50. nternal control mode H Setting of number of poles for UVW Number of poles x1 x2 x3 x4 XSEL1 H gt H up XSEL1 XSEL2 H H SEF 4L XSEL2 Set the cycle number of output pattern for UVW Refer next page for detail Pulse number of A B Z output is not changed by this setting H Setting of output mode MODE Pulse output Parallel absolute output OUTMD ai Na H Set the type of parallel output DO D11 Pulse mode A B Z U V W U1 V1 W1 ERR ERRHLD Parallel mode Absolute output Pure binary H Setting of RSO output exciting frequency RSO freq 20KHz 10KHz FSEL1 H eL FSEL2 H H Set the frequency of resolver excitation Before setting please check the target resolver specification Ale MNLO00392W00 H Setting number of poles of UVW X This specific setting X1 X2 X3 X4 means cycle number of waveform output pattern which range is 0 360 degree of electrical angle It does not have any relation with resolver multiplication factor of angle X1 X2 X3 X4 X1 pole case X2 pole case _ 0 90 180 270 360 Electrical angle degree Electrical 360 Electrical 360 Electrical 360 Electrical 360 AS 0 90 180 270 360 Resolver angle degree Example of 4X resolver 28 c MNL000392W00 Example In case of 8 poles 4 pole pair motor the relationship of r
51. ntion of secondary Circuit is getting complex and type failure damage of output TR it might not operate as etc by short circuit between calculations exciting lines Exciting voltage might vary Less temperature change of due to resolver input resolver signal due to impedance variability constant current Voltage control Circuit is simple and it will possibility to have secondary type operate as calculations failure due to overcurrent by short circuit between Exciting voltage can be exciting lines constant There might have temperature change of resolver signal Separate power supply V is required for the excitation amplifier circuit in addition to the AU6802N1 5V power supply Higher resolver exciting voltage caused higher resolver output voltage and it can expect to improve the S N ratio or noise immunity That mean it need appropriate DC power supply For example exciting voltage 7Vrms 20V 7V X4 2X2 require 24V for single power source or 15V for dual power sources Resolver operation will be possible at the lower exciting voltage compared to the value described in the specification So please decide exciting voltage value considering noise immunity and power equipment which can be prepared 13 7 MNL000392W00 In this chapter we will show you the example of excitation amplifier circuit current control type using RSO output X RSO output does not have enough driving power to
52. operation of the rotating resolver output angle data against actual resolver angle is shifted with the direction of rotation Are there any considerable factor Typical factors are following 1 Displacement of the device which put on the resolver There might become angular displacement depending on direction caused by mechanical misalignment of device like backlash of gear etc The problem of this factor is only depending on the rotation direction and it is not depend on revolution speed of resolver 2 Time constant of filter circuit If resolver signal input to AU6802N1 through filters there might show angular displacement depending on rotation direction while high speed resolver operation caused by time constant delay value of filter circuit The problem of this factor normally tends to be large in proportion to the number of revolution 3 Response of AU6802N1 Delay time of response Delay time from resolver signal input to corresponding angular data output might cause of the deviation angle which depend on the direction at high speed resolver operation The problem of this factor normally tends to be large in proportion to the number of revolution Fil MNLO00392W00 H Questions about the resolver interface Q Please tell the voltage specification of S1 S4 input signals Input signal voltage range of each terminals must be 0 VCC For the signal level adjustment of operational setting inste
53. ow can I do A AU6802N1 have only 12bit mode or 10bit mode When 12bit mode ignore the lower 4 bits And when 10bit mode ignore the lower 2 bits then data will be looks like 8bit Q Using encoder equivalent pulse mode A B pulse duty looks unstable while resolver rotate with same speed What is possible cause Encoder equivalent pulse output of this IC is theoretically poorer performance than A optical encoder pulse output Due to the affect of resolver potential error and R D potential error and also R D conversion principle itself it is possible to be disordered pulse duty even if in normal operation condition Q For the digital output serial interface output and parallel interface output are prepared Both interfaces should be used A Either one interface is enough and there are no problem for operation of this IC According to the system environment please use appropriate interface J4 MNL000392W00 In serial output case after SCSB falling edge is the data which is before first SCK falling edge unnecessary No need After SCSB falling edge output data which shows until SCK falling edge is undefined value Please ignore it SCSB DATA Bit 1 a Undefined To read the serial output data with above system which is better trigger SCK rising edge or SCK falling edge Please use SCK rising edge Serial output data change with SCK falling edge timing Then if you read the data
54. please check the connection between resolver and AU6802N1 MWaveform example of exciting signal and monitor signal with some fixed angle Electrical angle Excitation signal SINMNT COSMNT Electrical angle Excitation signal SINMNT COSMNT 38 MNLO00392W00 2 Check point of amplitude level Rotating the resolver with observing a monitor signal please check the monitor signal SINMNT and COSMNT maximum amplitude its recommended range is 2 3Vp p If signal amplitude is not appropriate range please adjust your circuit constants of exciting amplifier and resolver signal input circuit Excitation signal 4 2 3Vp p SINMNT 2 3Vp p COSMNT 6 1 3 Check point of phase shift Rotating the resolver with observing a monitor signal and differential signal R1E R2E of external exciting signal input please check that phase difference between differential signal R1E R2E and monitor signal SINMNT or COSMNT should be within 10 The measurement will be done at common phase position between R1E R2E signal and monitor
55. pling capacitor between COM pin and RSO pin Analog ground pin Connect to OV Ref 4 5 Ref 4 2 1 Resolution selection pin Resolution 10 Bit Ref 4 3 1 MDSEL H Internal control mode selection pin Ref 4 3 1 Acc Mode ON Ref 10 2 ACMD H Number of poles UVW selection pin These pins control to U1 V1 W1signals No of pole x1 X2 X3 Ref 4 3 1 XSEL1 H L XSEL2 H H L Ref 4 3 1 Ref 4 3 2 1 Ref 4 3 2 2 Ref 4 3 2 4 Parallel output DO D11 mode selection pin Output mode Absolute mode Pulse mode OUTMD H L Chip selection pin for serial output It controls DATA pin mode and serial out data will be latched at SCSB falling edge DATA pin mode Valid High impedance SCSB L H Ref 4 3 2 3 Ref 4 3 2 4 Serial data output pin The data which is absolute angle data D O BUS f at falling edge of SCSB is transmitted with SCK Serial clock input pin It is used the serial output function Frequency is 2MHz max Digital power pin Connect to 5V Ref 4 5 Oscillator connection pin Ref 4 4 External clock input pin Frequency of the device to be connected is 20MHz Digital ground pin Connect to OV Ref 4 5 Ref 4 4 Note Class means as follow AZI Analog input D I Digital input AJO Analog output D O BU
56. r Ceramic resonator g MNL000392W00 1 3 Block Diagram zl SER DATA SERIAL VF sck j OUTPUT sing cosg t t PHACON 1261s a M PARALLEL OUTPUT x come COUNTER p 10 12 Bits Jl mao __ PULSE OUTPUT GENLOG ABALU V W U VW 2 sotto Se 1 cos f als EXCITE SIGNAL INPUT RIE RESOLUTION SET 10 12 Bits T RE 0X1 2 3 4 EXCITE SOURCE SELF DIAGNO OUTPUT OUTPUT CLK 20MHz HORSO VO CONTROL SIGNAL SYSTEM CONTROL SIGNAL U V W NUMBER OF POLE SET 1 4 Spec Overview Binary code parallel 107 12bit bus compatible positive logic Conversion accuracy Static 2 LSB 4 LSB Settling time ACMD H 1 ms Typ 2 5 ms Typ For step input of 180 in electric angle ACMD L 15 ms Typ 60 ms Typ Regrets WAGE Malis cage e 0 2 Max 10 000 min 04 Max 10 000 min in electric angle Dii EA E Encoder emulation output A B 256 C T 1 024 C T abnormal sensor signal EX breaking down of exciting sourse lines Fault detection function Breaking of Resolver signal lines abnormal R D conversion DC 5V 5 45mA Max 30mA Typ em MNLO00392W00 1 5 Related documents 1 80110141114E Smartcoder AU6802N1 specification we Mees MNLO00392W00 2 Pin List Name and Functions 2 1 Pin Assignment
57. rm Number of multiple N Definition Show 1 2 the number of poles pole pair Display is added with X Term Mechanical angle 0 m Definition Rotational angle of resolver rotor Machine axis Term Electrical angle O e A Machine 1 cycle 360 N number of multiple define as electrical 1 cycle 360 Definition Oe NOm Term Exciting signal Definition Signal to be applied to the excitation winding of the resolver Term Resolver input impedance Zro Definition Resolver exciting side impedance Term Resolver signal X Signal outputted from the output winding of resolver when we applied the Definition en excitation signal Term Resolver transformation ratio Definition Ratio of the excitation voltage and resolver signal maximum voltage 81 MNLO00392W00 Term BRX 1Phases 2Phases Amplitude modulation type brushless resolver ll Configuration of resolver am 0 91 Excitation M Output equation Excitation Eri r2 Esin t Output Es s3 KE cos 0 sin o t Es2 s4 kE sin 0 sino ft Definition H Exciting signal and resolver signal waveform META ULA MNLO00392W00 11 Revision history Revised date Revision Revision content reason 2013 05 10 z 83 MNL000392W00
58. roubleshooting flow of error Error detected Please check whether both SINMNT and COSMNT amplitude are less than 0 5Vp p or not Less than 0 5Vp p Greater than 0 5Vp p Please check whether SINMNT or COSMNT signal cross 0 75 V5 line or not Sometimes less 0 75V 5 Always above 0 75 Vp Abnormal sensor signal Abnormal sensor signal Abnormal R D conversion breaking down of exciting breaking of Resolver signal Excessive control deviation source lines lines To 8 1 1 To 8 1 2 To 8 1 3 47 MNLO00392W00 8 1 1 Suspicion of Abnormal sensor signal breaking down of exciting source lines In case of suspicion the breaking down of exciting source lines true error factor should be identified and eliminated according to the below troubleshooting flow MW Troubleshooting flow of detecting break down of exciting source lines Abnormal sensor signal breaking down of exciting source lines detected Please check about excitation signal R1 R2 Refer 6 1 1 Not output Output normally Please check about SINMNT and COSMNT amplitude change Refer 6 1 2 1 Changing No change in amplitude No amplitude in one signal Signal level might be Might be resolver inappropriate wiring connection Refer pattern error Might be signal line short Refer pattern Breaking down of exciting source lines Please check that each signal line does not have shorted to VDD GND Signal Please adjust mon
59. rystal Resonator Ceramic Resonator o ooo o o 44 2 External Clock cureranno a Y Se a Oa io 33 4 5 Power Source ees A hs ee RE A NE s 32 4 6 Countermeasures for Noise eee rre 3 ES Gonneclol eee s due eg re E T ee ae Gb 5 1 Example of Resolver Connection ee eee e 36 5 2 Example of Power Connecti0N ee eee eee eens 31 O Ohe POMADA es ies 38 6 1 Check Point for Resolver Interface o ooo e 38 6 1 1 Check Point of Excitation Signal 0 0 0 00 0 cece eens 38 6 1 2 Check Point of Monitor Signal Amplitude 0 0 0 cece eee eee 38 6 1 3 Check point of phase shift o oooooo ooo oo 39 6 2 Check Point for Digital Output o o 40 6 2 1 Check Point of Output Angle o ooo ooo o 40 6 2 2 Check point of abnormality Detection 0 cee eee 40 Z Punetuon ofla Detectioly eee c cun ore ence ee teeta 41 7 1 Abnormal sensor signal breaking down of exciting source lines 41 7 1 1 Concept Detection 4 ssec ere err e 41 71 2 Circuit Configurations 5 5 2 ber is EBEN een E Mae ada io 41 ri x MNLO00392W00 T3 Detection Principle 3 085 b een a Ba ae eek aS abbate e ss 41 7 1 4 Relationship of threshold and Typical abnormal detection pattern 42 7 2 Abnormal sensor signal break
60. t be instantaneous magnetic noise acceleration mode by power failure Resolver error etc Nothing change or problem occur with ACMD L Abnormal sensor signal or abnormal R D conversion M Refer 8 1 Identify the factors If it is no problem Please check supply And improve system please operate with voltage variation with appropriate ACMD L mode Under 4 5V case need countermeasure countermeasure 55 MNL000392W00 8 3 If the situation does not improve If the situation does not improve even if section 8 1 or 8 2 steps perform and if there is another phenomenon which does not mention in this manual please contact us with waveforms when an error occur appropriate abnormal signal SINMNT COSMNT and also inform us about detail troubled circuit information 56 MNLO00392W00 9 Electrical characteristics 9 1 Absolute maximum rating Items Symbol Absolute maximum rating Unit Power supply voltage iris iur id VDD 0 3 7 0 V Analog input voltage Via 0 3 7 0 V Digital input voltage Vi 0 3 VDD 0 3 V Digital output current Io 10 10 mA Operating temperature Tose 40 125 c Storage temperature Ttg 65 150 C Allowable loss Pp 245 mW X If you use the IC beyond the absolute maximum rating it may cause permanent damage to the IC 9 2 Power related characteristic Items Symbol Min Typ Max Unit Remarks and conditions VCC 4 75 5 0 5 25 V
61. tions 6 2 2 Check point of abnormality Detection ERR output and ERRHLD output should be both L level for normal condition while ERRSTB input is H level If this device detects some error condition ERR output or ERRHLD output will be H level Then you may refer section 8 1 and please isolate the true cause of the error and remove it 40 MNLO00392W00 7 Function of Fault Detection AU6802N1 has built in test function of fault detection which detects abnormal sensor signal and abnormal R D conversion These error conditions output at the ERR or ERRHLD terminal The 3 kind of contents of detection are shown below Abnormal sensor signal breaking down of exciting source line R1 amp R2 Abnormal sensor signal breaking of resolver signal line S1 S2 S3 amp S4 Abnormal R D conversion Excessive residuals of control signal In this chapter describe each detection method typical fault detection pattern and error reset operation This built in test function is independent from R D conversion function and does not restrict the R D conversion output by its result i e any detection of abnormal state 7 1 Abnormal sensor signal breaking down of exciting source lines 7 1 1 Concept Detection This concept is to detect smaller monitor output amplitude level then it defines as abnormal sensor signal Breaking down of exciting source line can not excite resolver As a result resolver outp
62. ultiplied by feedback sin This is encoded by comparator Analog to Digital conversion and sinjWt component is removed by synchronous detection Through a compensator which stabilize negative feedback loop and improve its characteristic In general compensator is PI control which configure with type I direct servo loop digital angular output can be generated as counter value 65 MNLO00392W00 10 2 Acceleration mode An acceleration mode is the function to improve the dynamic performance more than primary characteristic and to be possible making more correct sensing according to switching of internal control mode against unexpected high angular acceleration In this product it is possible to set ON OFF by ACMD terminal 10 2 1 Effect of acceleration mode After rapid change of resolver angle high angle acceleration happen output angle will converge at a resolver angle In case of acceleration mode is ON output will soon be able to follow the resolver angle compare the case of mode OFF Cause of switching the internal control mode rate of change angle is getting faster than mode OFF condition After following the angle of target output control mode return to normal from acceleration mode Effect of acceleration mode in a step response Out angle ACMD OFF o a amp g Time E Resolver angle Out angle ACMD ON Out angle ACMD OFF ob S lt x T apa A ie ed cr a DENN RU
63. ut data is indefinite free run might not get one rotation data please follow below troubleshooting flow and identify the factors and then improve your system MW Troubleshooting flow of indefinite free run can not get one rotation data indefinite free run can not get one rotation data Please check whether error occurs or not Error occurs occurs Error doesnot occur S OE does not occur Whatis behavior of the data 00 is behavior of the data y y y Data is undefined Data is free run Can not get one rotation data Parallel output Keep rotation y Control loop might be Abnormal sensor signal Output might be or abnormal R D disabled conversion Refer 8 1 Please check signal Refer 8 1 3 Please check the polarity of CSB RDB polarity of OUTMD Output format might be different failing and SCSB 53 MNLO00392W00 8 2 3 In case of rotation direction difference deviation of 90 or 180 In case of angular output data shows different rotation direction or there might be angular displacement of 90 or 180 please follow below troubleshooting flow and identify the factors and then improve your system E Troubleshooting flow of rotation direction difference deviation of 90 or 180 Rotation direction difference deviation of 90 or180 Please check the situation Rotation direction difference deviation of 90 deviation of 180 Rotation direction
64. ut signal will disappear and abnormal sensor signal can be detect 7 1 2 Circuit Configuration COMP x4 055 x VGC SINMNT Peak detection Error 0 45 x VCC 7 1 3 Detection Principle The principle is comparison between monitor output and threshold voltage Detect situation that the voltage magnitude of SINMNT and COSMNT are above low side threshold and below high side threshold It mean both monitor amplitude is under 0 1 X VCC Vp p and define this situation as abnormal Example of VCC 5V case detection condition is under 0 5Vp p of both monitor amplitude A MNLO00392W00 7 1 4 Relationship of threshold and typical abnormal detection pattern 1 Normal COSMNT envelope kE cos 0 2 3Vp p SINMNT envelope kE sin0 K Vee X0 55 2 75V Monitor out V COM 2 5V Vec X 0 45 2 25V Example of VCC 5V Resolver electrical angle In normal monitor signal case either SINMNT or COSMNT exceed a threshold value then it does not detect abnormal sensor signal 2 Detection pattern Monitor amplitude is under threshold Monitor out V Under0 5Vp p oe irem dem d me a drm rh mm SER S em Em Example of VCC 5V Resolver electrical angle Breaking down of exciting circuit or smaller monitor output will detect as abnormal signal in full angular range 3 Detection pattern Shorted between S1 S3 or S2 S4 Monitor out V V XExample Shorted between S1 S3 case
65. with SCK falling edge there might read false data depending on read timing SCK DATA DATA switch timing Plan to use serial output function But data need only 8bit due to above system configuration How should I handle about serial output data Please exit serial output sequence SCSB L gt H after 8 serial data output Even in the middle to end data is refreshed and next output mode start with MSB data Example pnm le Data refresh Data refresh timing i timing m O e UE UUA DATA Jesi uil lon Undefined Undefined Rs MNLO00392W00 Plan to use serial output function But data need 16bit width due to upper system configuration How should I handle about serial output data While keeping SCSB L and keeping SCK input beyond PRTY bit please stop serial output sequence after 16 serial data output If you continue adding SCK after PRTY bit while keeping SCSB L additional bit until 16t SCK takes O data and repeat the same data for each 16 SCK clock Example of accuracy 12Bit mode One ATE IU i Data capture Data capture i timing i timing SCSB SCK DATA Undefined Example of accuracy 10Bit mode E s Data capture Data capture i i timing timing j SCSB Hu tv qp M A Star sees seen ee peg DAS UE FO FOIS US EU ER FT Undefined Undefined Data capture timing SCSB VA z E Or en aso Aaa BAT
66. x DO Dii Datal Data3 PRTY Parity3 Parity1 63 MNLO00392W00 BE Serial output operation waveform 250ns min 250ns min 300ns min SCSB SCK DATA 50ns max i bOns max 50ns max gt 300ns min E Timing of error reset 40ns max 0 100ns ERRSTB ERRHLD Error status Error reset 64 MNLO00392W00 10 Appendix 10 1 R D conversion principle This product adopted digital tracking method as R D conversion system and this method is one of the negative feedback control of closed loop configuration then it convert from Resolver analog signal to digital signal A control deviation is shown in below equation and it must be normally 0 with the negative feedback control system Control deviation K sin 0 Q sinwt Here assuming e O means 0 then Resolver analog angular signal can be converted to digital angular data E Configuration of digital tracking method R D converter _ R D converter tracking method 21221 _ l Resolver l BRX l l Control deviation l i l n Exciting signal Control deviation K sin 0 sinwt X cos K cos sinwWtXsinQ K sin 0O sinwt e 0 Explanation of concept An amplitude modulated resolver signals enter to R D converter To calculate control deviation sin modulated signal is multiplied by feedback cos and cos modulated signal is m
67. ying time at electrical angle output Then not affected Ea MNLO00392W00 Specification said that phase difference between external exciting input R1E R2E and resolver monitor signals COSMNT SINMNT should be within 10 If phase difference is over 10 what kind of actual impact can we face When phase difference is over 10 it takes time to settle angular output at startup or in worst case it can not settle forever Also when there is a steep angle change of resolver IC might not be able to respond or takes long time to catch up AU6802N1 are performing synchronous detection with reference the signal phase of external exciting input R1E R2E Then such phase difference cause phase shift of synchronous detection Equivalently negative feedback control loop gain that realize R D conversion is getting decrease and dynamic transfer characteristic have some impact so such symptoms appears J3 MNL000392W00 H Questions about the output interface In the situation of digital output terminals might be shorted each other short to VDD or Q GND what kind of issues will be appear when the power is active When the voltage is different between the shorted pin One side H and other side A L excessive current flow from H to L heating up and finally IC might be damaged Q Would like to get 8bit parallel output data H

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