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Hardware Manual - Phytec Messtechnik GmbH

1. 128kB to 8MB 0 to 8MB Sync Burst FLASH SRAM EPROM 32 Bit 0 Wait 32 Bit FRAM or Clock EEPROM or Calendar AM Alarm i UART QSPI A UART QSPI B RS232 Transceiver I CANA RS232 Transceiver CAN Transceiver CAN B r9 9 CAN Transceiver 26kB SRAM VDDH VDDL MIOS Counter PWM lO TPUA TPUB ADC A ADC Figure 1 Block Diagram phyCORE MPC555 mI D C n n e t r Data Bus Address Bus Control Signals IRQRTC ARQ O 4 RXD1 TXD1 RXD1 TXD1 QSPI RXD2 TXD2 RXD2 TXD2 QSPI A CANH CANRX CANTX B CANL B CANH CANRX B CANTX WakeUp 3 3V 5V VBat JTAG BDM MDA O 9 0 7 15 A TPU 0 15 B TPU 0 15 A T2CLK B_T2CLK AD 0 15 B_AD 0 15 ETRIG 1 2 PHYTEC Me technik GmbH 2005 L 523e_5 Introduction 1 2 View of the phyCORE MPC555 9 CB36 Co B22 CB40 a Hl o Seis S 5 o o 2 U5 U7 U3 U14 05 5 C16 d R24 al a 3 C1C2C10 5050 DES 0 m ES gt z 2 3 al J18 E a T ane
2. Parameter Requirements Characteristics Dimensions 72 mm x 57 mm Weight ca 25 g with max memory Humidity max 95 r F not condensed Storage Temp Range 40 to 90 C Operating Temp Range Standard 0 C to 70 C Extended 40 C to 90 C Operating voltages Voltage 3 3V 3 3 5 Voltage 5V 5 5 Battery VBAT 3 V 10 Operating Power 40 MHz frequency Consumption Voltage 3 3V 1 MByte SRAM Typ 300 mA Voltage 5V 512 kByte Flash Typ 40 mA2 Voltage 3 3V 4 MByte SRAM Typ 620 mA Voltage 5V 4 MByte Flash Typ 40 mA Battery power supply VBAT 3 V Less than 10 WA RTC and internal Voltage 5V 20V SRAM in MPC555 Voltage 3 3 V 0 V Table 9 Technical Data These data apply to the standard configurations at the time of printing of this manual l Applies to all PCBs 1169 2 and higher PCB thickness for earlier PCB versions was 1 1 mm 2 Without I O access and load of MIOS TPU ADC etc 44 PHYTEC Me technik GmbH 2005 1 523 5 Technical Specifications Connectors on the phy CORE MPC555 Contact rows on the module Manufacturer Molex Number of pins per contact rows 160 2 rows of 80 Molex part number 52760 1679 lead free PHYTEC part number VM042 The Molex connectors mating with the ones populating the phyCORE MPC555 are available in two different sizes The mated height given describes the distance between the two PCBs they connect e Component height 5
3. Pi wi EG phyCORE MPC555 Hardware Manual Edition July 2005 A product of a PHYTEC Technology Holding company phyCORE MPC555 In this manual are descriptions for copyrighted products that are not explicitly indicated as such The absence of the trademark and copyright symbols does not imply that a product is not protected Additionally registered patents and trademarks are similarly not expressly indicated in this manual The information in this document has been carefully checked and is believed to be entirely reliable However PHYTEC Me technik GmbH assumes responsibility for any inaccuracies PHYTEC Me technik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product PHYTEC Me technik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages which might result Additionally PHYTEC Me technik GmbH offers no guarantee nor accepts liability for damages arising from the improper usage or improper installation of the hardware or software PHYTEC Me technik GmbH further reserves the right to alter the layout and or design of the hardware without prior notification and accepts no liability for doing so Copyright 2005 PHYTEC MeBtechnik GmbH D 55129 Mainz Rights including those of translation reprint b
4. 7 Figure 4 Numbering of the Jumper 19 Figure 5 Location of the Jumpers Controller Side and Default Setting Standard Version of the phy CORE MPC 355 esistente ten sued 19 Figure 6 Location of the Jumpers Connector Side and Default Setting Standard Version of the ply CORB MPC 2359 sirara testes a gaga ne tuse redi bi nga aan 20 Fig r 7 Power Concept cioe eae nne tihi pa a RE ed 25 Figure 8 Default Memory Model after Hardware Reset 29 Figure 9 Slave Address of the Serial Memory 08 35 Figure 10 10 pin BDM Connector and Corresponding Pins of the phy C ORESCOBUPCIOE o nace todo die setas urtica 40 Figure 11 Physical Dimensions u s vo pr vs YO Euer aee 43 Table 1 Pinout of the phyCORE Connector 18 Table 2 Jumper epe 24 Table 3 Clock Mode Configuration via Jumpers J2 J3 and J4 27 Table 4 Runtime Memory nnn 3l Table 5 Flash Memory Device and Manufacturers Overview 32 Table 6 Memory Options for the Synchronous BURST SRAM 33 Table 7 Memory Options for the Serial Memory 8 34 Table 8 Address of the Serial Memory aaa me eaaa maea nawan 22 Table 9 E PU 44 Me technik GmbH 2005 L 523e 5 Preface Prefac
5. 28 RS 232 25 RS 232 Interface 44 n rn 40 S Serial Interfaces 44 serial 40 SMT 7 Solder Jumpers 20 SRAM Serial 40 Start up System Configuration nace 31 Supply Voltage serial 26 Supply Voltage 28 Synchronous BURST SRAM 38 System Configuration 31 System Memory 33 Technical Specifications 50 Terminating Resistor 45 A 28 U 40 Wake Up Behavior 29 52 Me technik GmbH 2005 L 523e 5 Suggestions for Improvement Document phyCORE MPC555 Document number L 523e 5 July 2005 How would you improve this manual Did you find any mistakes in this manual page Submitted by Customer number Name Company Address Return to PHYTEC Technologie Holding AG Postfach 100403 D 55135 Mainz Germany Fax 449 6131 9221 33 PHYTEC Me technik GmbH 2005 L 523e 5 Published by a PHYTEC Me technik GmbH 2005 Ordering No L 523e_5 Printed in Germany
6. T o 8 04 06 ol al g Os S oo gu m p3 02 C26 C25 C23 C24 RN RN 7 ANG INT R34 eu z Ru 3 loc loc 3 loc Cc 9 R36 Figure 2 View of the phyCORE MPC555 Me technik GmbH 2005 L 523e 5 5 phyCORE MPC555 6 PHYTEC Me technik GmbH 2005 L 523e 5 Pin Description 2 Pin Description Please note that all module connections are not to exceed their expressed maximum voltage or current Maximum signal input values are indicated in the corresponding controller manuals data sheets As damage from improper connections varies according to use and application it is the user s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals As Figure 3 indicates all controller signals extend to high density 0 635 mm SMT plugs refered to as phyCORE Connector lining two sides of the board refer to section 9 This allows the phyCORE MPC555 to be plugged into any target applic
7. The jumpers J solder jumper have the following functions Jumper default Comment Jl 1 2 2 3 Package Determines the memory for a program start after reset Internal on chip Flash memory D20 VDDL External on board Flash memory D20 gt GND D20 must be externally configured via a 4k7 resistor OR in SMD 0402 J2 J3 J4 1 2 2 3 2 3 1 2 1 2 2 3 1 2 2 3 1 2 Package Type These jumpers configure the clock mode of the 555 When PORESET is active the bit pattern connects to the MODCK 1 3 signals of the MPC555 Only the standard configurations using the MPC555 s oscillator and quartz are shown below The default configuration depends on the frequency of the external quartz populating the module Configurations for use of an external clock source can be found in the MPC555 user s manual 20 MHz Quartz limp mode activated MODCK 1 3 011 20 MHz Quartz limp mode deactivated MODCKT 1 3 2001 4MHz Quartz limp mode activated MODCK 1 3 010 OR in SMD 0402 J5 1 2 2 3 Package Type J5 determines the source of the Hard Reset Configuration Word HRCW During HRESET the HRCW configures the MPC555 The HRCW is read via the data bus Except D20 the data bus is supported by pull down resistors and accordingly guarantees a valid data word J1 configures D20 and determines the internal or external Flash memory as boot code source The internal de
8. 1 do ua 1 F oot ut 2 Flash Memory 23 36 36 36 FRAM Serial 40 G GND Connection 53 H Hard Rest Configuration Word 32 Hints for Handling the Mod l eicit HS 53 I LC BiG odes ian 25 ErequetiCy oerte aa ets 40 Interface eee 40 Introduction aue 1 J d HH WE 56 E senengan Eo bi HE OR DU 56 JA Treen 56 an 56 Memory Banks 38 Memory Configuration 24 26 Memory Model After serenus 33 35 31 4 22 O COR ai Side Ai a tute ais 35 P6402 a dtd 56 Pin Description 7 19 nouos 28 Power Savings Mode 28 Power Supply Internal SRAM 23 PHYTEC Me technik GmbH 2005 L 523e 5 phyCORE MPC555 Power 28 Power Off Behavior 29 Power On Behavior 29 Power On Reset 31 Q Quar AN 23 56 R Real Time Clock 48 Reference Voltage 223 Reset Behavior
9. closed Package Type J9 switches the I O signal MPIOO to the power down input of the synchronous BURST SRAMSs This enables the external RAM banks to be switched to a power saving mode via software During this state the memory cannot be read or written to The signal MPIOO is decoupled from the power down inputs ZZ of the SRAMs and can be used for other functions The ZZ inputs are connected to a pull down resistor The signal MPIOO is connected to the power down inputs ZZ of the SRAMs A power down is activated with high level OR in SMD 0402 J10 open closed Package Type J10 connects the memory bank address signal BAT to the processor address line A9 This jumper must be closed in the case that the module is populated with synchronous BURST SRAMSs that have a capacity of 512k x 32 36 bit 2MB or larger per device In addition Jumper J18 must be specifically set in accordance with the board s memory configuration The factory default setting of J10 will be set according to the particular memory configuration of each individual module Synchronous BURST SRAM devices with a capacity smaller than 512k x 32 36 bit 2MB Synchronous BURST SRAM devices with a capacity of 512k x 32 36 bit 2MB or larger OR in SMD 0402 J11 J12 open closed Package Type J11 and J12 disconnect the CAN receive lines of the MPC555 from the CAN transceivers at U12 and U13 This makes the controllers CAN TTL signal
10. 64 bit Floating Point Unit 26 kByte SRAM capable of battery buffering 448 kByte FLASH Dual UART SPI Dual CAN 2 0B Dual TPU with 16 channels each Two 16 bit timer system Eight channel 16 bit PWM system Dual 10 bit ADC 7us with 32 41 channels ext MUX Multi Purpose I O signal JTAG BDM test debug port 2 PHYTEC Me technik GmbH 2005 L 523e 5 Introduction Memory Configuration SRAM 128 kByte to 8 MB flow through Synchronous Burst RAM 32 bit access 0 wait states 2 1 1 1 Burst mode Flash ROM 0 512 kBytes 1 MB 2 MB 4 MB 32 bit width Memory 4 kByte EEPROM up to 32 kByte alter natively FRAM SRAM Real Time Clock with calendar and alarm function Power down wake up support RTC decrementor or external signal e Dual UART SPI port RS 232 transceiver for both channels RxD TxD also configurable as TTL e Dual CAN port CAN transceiver 82C251 for both channels also configurable as TTL e JTAG BDM test debug port e Available in standard 0 70 and industrial 40 85 C temperature ranges 1 Please contact PHYTEC for more information about additional module configurations Me technik GmbH 2005 L 523e 5 3 phyCORE MPC555 1 1 Block Diagram 40 MHz CPU Clock PLL 20 MHz Quarz 555 32 Bit PowerPC Core 64 Bit FPU 448kB FLASH Eprom 64 Bit Timebase 32 Bit Decrementer
11. 72B A_TPU12 the 555 73B TPUIO 75B A_TPU8 76B A_TPU6 77B A_TPU4 78B A_TPU2 80B A_TPUO Pin row X1C 1C 2C 3V3 I Supply Voltage 3 3 VDC 3C 7C 12C GND Ground OV 17C 22C 27C 32C 37C 42C 47C 52C 57C 4C 5C 5V Supply Voltage 5 VDC 6C VBAT I Connection for external battery 2 4 3 3V 8C 3V3GOOD Indicator signal for a valid input voltage 3 3 PHYTEC Me technik GmbH 2005 1 523 5 11 phyCORE MPC555 Pin Number Connection I O Comments 9C While the HRESET is active the pin serves RSTCNF as an input and determines the source of the Hard Reset Configuration Word HRCW If a low level is applied the HRCW is read from the data bus Otherwise an internal HRCW is used that is derived from either the Flash CMCFIG with HC 0 or in the case that HC 1 will be read as default value 0x00000000 Note that during HRESET phase with RSTCNF high the data bus must be held at tri state In normal operation shut down the pin functions as an output and controls the power switch for VDDH and VDDL 10C HRESET Hard reset signal of the MPC555 An Open Drain transceiver controls HRESET 11C PORSET I O Power on reset of the MPC555 An open drain transceiver controls the PORESET PORESET monitors the input voltage 3V3 and VPD 13C 15 MIOS GPIO signals of the MPC555 14C MPIO13 15C M
12. U8 and Table 9 in Technical PCB 1174 1 Specifications revised 04 July 2005 Manual L 523e_5 Section 9 Technical Specifications thickness 001 corrected and Molex part numbers adjusted to lead free PCB 1169 5 version PCM 995 PCB 1174 1 PHYTEC Me technik GmbH 2005 L 523e_5 47 phyCORE MPC555 48 PHYTEC Me technik GmbH 2005 1 523 5 Appendices A Appendices A A 1 Release Notes The following section contains infomation about deviations to the description in this manual Changes in revision PCB1169 0 through 1169 5 1 If the GAL P640 is installed the function of Jumpers J2 J3 J4 and J5 is different to what s described in section 3 J5 J3 J4 1 2 2 3 2 3 1 2 1 2 2 3 1 2 2 3 1 2 Package Type These jumpers configure the clock mode of the 555 During the active phase of PORESET the bit pattern available on the MODCK 1 3 pins is read by the MPC555 processor Only the standard configurations using the MPC5555 oscillator and quartz are shown below The default configuration depends on the frequency of the external quartz populating the module Configuration options for using an external clock source can be found in the MPC555 user s manual 20 MHz Quartz limp mode activated MODCK 1 3 2011 20 MHz Quartz limp mode deactivated MODCK 1 3 2001 4MHz Quartz limp mode activated MODCK 1 3 010 OR in SMD 0402 J2
13. 11A A30 A29 A27 I O Address lines 13A 14A 15A A24 A22 A21 Alternative 16A 18A 24 A19 A16 A14 SGPIOA30 SGPIOA29 SGPIOA27 25 26 28 A13 All A8 SGPIOA24 SGPIOA22 SGPIOA21 SGPIOA19 SGPIOA16 SGPIOA14 SGPIOA13 SGPIOA11 SGPIOA8 I O For the use of the alternative function note that the address lines are partially used for memory addressing 19A 20A 21A D30 D29 D27 I O Data lines 23A 29A 30A D24 D22 D21 Alternative SGPIOD30 SGPIOD29 31A 33A 38A D19 D16 D14 SGPIOD27 SGPIOD24 SGPIOD22 39A 40 41A D12 D11 D9 SGPIOD21 SGPIOD19 SGPIOD 16 4 44A 45 D6 D4 D3 SGPIOD14 SGPIOD12 SGPIODI1 46A D1 SGPIOD9 SGPIOD6 SGPIOD4 SGPIOD3 SGPIODI I O For use of the alternative function note that the data lines are used to connect the on board memory devices 34A ITA Transfer acknowledge signal of the MPC555 35A VO Transfer error acknowledge signal of the MPC555 36A BB Bus busy signal of MPC555 __ Alternative VF2 IWP3 51 TSIZO I O Transfer size signal of the MPC555 oo PHYTEC Me technik GmbH 2005 L 523e 5 Pin Description Pin Number Connection Comments 48A 49A 50A NC Not connected These contacts should remain unconnected on the target hardware side 53A TS VO Transfer start signal of the 5
14. 142 243 Package Type J2 determines the source of the Hard Reset Configuration Word HRCW During HRESET the HRCW configures the MPC555 processor The HRCW is read via the data bus Except D20 the data bus is connected to pull down resistors and accordingly guarantees a valid data word J1 configures D20 and determines the internal or external Flash memory as boot code source The internal default word is read as HRCW OR in SMD 0402 PHYTEC Me technik GmbH 2005 L 523e 5 49 phyCORE MPC555 2 The power down feature is currently not supported due to a problem with the MPC555 processor None of the PCB revisions supports the ready busy function on ROS MODCK1 If the IRQ5 is to be controlled externally using push button S5 of the Development Board PCM 995 then R37 must be removed 50 PHYTEC Me technik GmbH 2005 L 523e 5 Index Index WAKEUP Signal 25 29 A Alarm Interrupt Output 25 BDM Connector 47 BDM Debug Interface 46 35 C CAN Optical Isolation 24 Latet see teh 24 CAN Interface 45 CAN Transceiver 26 Chip Select Signal 35 87 E EE 31 CCIock MOGO oot inet 31 Contact Rows 52 E EEPROM Serial 40
15. Alternative POB 3 1 digital input D 80D VRH O Reference voltage of the QADC module If Jumper J7 is closed VRH is connected with D VDDA J7 must be opened in order to use an external reference voltage Table 1 Pinout of the phyCORE Connector l Caution Because of the LV Flash devices used the signals A29 A9 D31 D0 50 OE WEO WE2 and HRESET must have signal levels of max 3 3 V 40 5 V PHYTEC Me technik GmbH 2005 L 523e 5 Jumpers 3 Jumpers For configuration purposes the phyCORE MPC555 has 21 solder jumpers some of which have been installed prior to delivery Figure 4 illustrates the numbering of the jumper pads while Figure 5 indicates the location of the jumpers on the board open closed 123 1 1 1 E 2 4 6 8 1 ae 789 eg J2 J5 eg J1 J6 J18 Figure 4 Numbering of the Jumper Pads Figure 5 Location of the Jumpers Controller Side and Default Setting Standard Version of the php CORE MPC555 PHYTEC Me technik GmbH 2005 L 523e 5 19 phyCORE MPC555 J8 J19 ool eee Figure 6 Location of the Jumpers Connector Side and Default Setting Standard Version of the phyCORE MPC555 1 Jumper and J18 might vary because of different memory on the phyCORE MPC555 20 PHYTEC Me technik GmbH 2005 1 523 5 Jumpers
16. Memory Two memory models can be distinuished when using the phyCORE MPC555 the memory model that is active after reset and the runtime model The runtime model is configurable by software 6 1 Memory Model after Reset The memory model after reset is defined through special mechanism While HRESET is active the memory model as well as several other system configurations are determined by the Hard Reset Configuration Word HRCW CSO external Flash memory internal Flash memory J5 1 2 RSTCONF 0 ext HRCW J5 1 2 J ESTCONF O ext HRCW 2 3 FLEN 0 int Flash disabled 1 2 FLEN I int Flash enabled 0x00 0000 external Flash memory m gt 0x00 0000 int Flash A 256 kByte 0x00 0100 Reset Exception 0x00 0100 Reset Exception 0x04 0000 int Flash B 192 kByte OxOF FFFF 1 MB 0x10 0000 0x07 0000 reserved free m gt 0x2F C000 USIU amp Flash Control 16 kB Ox2F C000 USIU amp Flash Control 16 kB 0x30 0000 UIMB amp IMB3 32 kB 0x30 0000 UIMB amp IMB3 32 kByte 0x30 8000 reserved 480 kByte 0x30 8000 reserved 480 kByte 0x38 0000 SRAM Control A 8 Byte 0x38 0000 SRAM Control A 8 Byte 0x38 0008 SRAM Control B 8 Byte 0x38 0008 SRAM Control B 8 Byte 0x38 0010 reserved 485 98 kByte 0x38 0010 reserved 485 98 kByte Ox3F 9800 SRAM A 10 kByte Ox3F 9800 SRAM A 10 kByte Ox3F C000 SRAM B 16 kByte Ox3F C000 SRAM B 16 kByte 0x40 0000 free 0x40 0000 fre
17. low level at the WAKEUP port pin X1C56 of the phyCORE Connector The alarm interrupt IRTC must either be connected to the WAKEUP signal of the board via jumper J15 or brought back externally pin X1D33 connected to pin X1C56 Even if the IRTC is connected to WAKEUP additional input sources may be connected For additional input sources a wired OR connector open drain or open collector transceiver against GND is required 26 PHYTEC Me technik GmbH 2005 1 523 5 Start up System Comfiguration 5 Start up System Configuration The system configuration is done in multiple phases This section describes the mechanism that is active up until execution of the initial software command Power on Reset Phase Hard reset Phase Initialization via software 5 1 Power On Reset Phase The processors clock generator is configured during the power on reset phase Solder jumpers J2 J3 and J4 are used to configure the clock mode Depending on the desired clock source a corresponding bit pattern must be present at the processor lines MODCK 1 3 during the PORESET phase Because these signals are multiplexed with the interrupt inputs 5 IRQ6 and IRW7 no external hardware may interfere with these signals J2 J3 J4 Clock Mode 1 2 2 3 12 3 20 MHz quartz limp mode activated MODCK I1 3 2011 1 2 1 2 2 3 20 MHz quartz limp mode deactivated MODCK 1 3 001 1 2 2 3 142 4 quartz limp mode activa
18. peripheral CS signals of the QSPI interfaces I O SS with the help of this bi directional signal the QSPI interface can switch into Slave Mode General purpose input output of the MPC555 SGPIOC7 is connected to the SCL signal of the I C bus via R38 and serves as the clock signal Alternative IRQOUT interrupt output Alternative LWPO load store watchpoint 0 After Reset the LWPO function is active General purpose input output of the MPC555 SGPIOC6 is connected to the SDA signal of the C bus via R39 and serves as data signal Alternative FRZ freeze O Alternative PTR program trace O After reset the PTR function is active PHYTEC Me technik GmbH 2005 L 523e 5 Pin Description Pin Number Connection Comments 32D SDA IRTC Data line of the bus SDA is connected to MPC555 signal SGPIOC6 via R39 Interrupt output of the RTC IRTC can be connected to WAKEUP using jumper J15 36D 37D 38D 40D 41D 42D 43D 45D 46D DSDO VFLSO VFLS1 2 MPIOO MDAS MDA6 MDA4 MDA2 MDAO I O Development serial data output of the 555 BDM port Alternative test data out of the port O The HRCW D11 determines the function Visible history buffer flush status of the MPC555 BDM port Alternative IWP 0 1 instruction watchpoint O The HRCW D9 D10 determines the
19. potential of the supply voltage 3V3 via the pull up resistor R24 The signal IRTC is connected with the WAKEUP input The interrupt output of the RTC is of the open drain type WAKEUP can further be used on the target hardware side wired OR against GND OR in SMD 0402 J16 J17 1 2 243 1 2 142 2 3 243 2 3 1 2 Package Type J16 and J17 define the slave address A2 and A1 of the serial memory on the bus In the high nibble of the address memory devices have the slave ID OxA The low nibble consists of A2 Al AO and the RAW bit AO is tied to GND It must be noted that the RTC at U10 is also connected to the bus The RTC has the preconfigured address OxA2 0xA3 that cannot be changed A2 0 1 0 0 0 0xAO0 OxA1 A2 1 1 0 0 0 0x A8 A9 A2 0 Al 1 0 0 0x A4 Ox A5 A2 1 Al 1 A020 0xAC OXAD slave address OxAC for write operations and OxAD for read access OR in SMD 0402 Me technik GmbH 2005 L 523e 5 23 phyCORE MPC555 Jumper default Comment J18 1 4 243 3 6 5 8 5 6 7 8 4 7 8 9 6 9 Package J18 connects memory bank address signals BAO and BA1 to the corresponding address lines of the processor The configuration of these jumpers is dependent on the memory size of the synchronous BURST SRAM populating the module The factory setting of J18 is in accordance with the me
20. resistor 35C DSCK I Development Serial Clock of the MPC555 BDM port Alternative TCK Test Clock of the MPC555 JTAG port The HRCW D11 determines which function is active 36C TMS I Test Mode Select of the MPC555 JTAG 39C MPIOI I O MIOS GPIO signals of the MPC555 Alternative VF1 Visible Instruction Queue Flash Status VF bit in MIOSITPCR 0 40C MDA9 Double Action I O MDA 31 29 27 of the 41C 43C MDA7 MDA5 MPC555 MIOS These signals serve either as Input Capture or Output Compare 44C MDA3 Double action MDA 14 12 of the 45C MDAI MPC555 MIOS These signals serve as either Input Capture or Output Compare Alternatively these signals serve the external reload of the counter register within the counter modules 46C MPWMT7 PWM output or I O signals of the MPC555 48C 5 MIOS 49C MPWM3 MPWM19 MPWM17 MPWM3 MPWM1 50C MPWMI MPWMO 51 MPWMO PHYTEC MeBtechnik GmbH 2005 L 523e_5 13 phyCORE MPC555 Pin Number Connection Comments 53 54 55 RXD2_TTL TXD2_TTL PWRON Receive line of the second MPC555 UART Alternative QGPI2 general purpose input D When the alternative function is used solder jumper J14 must be open in order to disconnect the receive output of the RS 232 transceiver Transmit line of the second MPC555 UART Alternative QGPO2 general purpose output PWRON c
21. the accompanying data sheet of the converter 40 PHYTEC Me technik GmbH 2005 1 523 5 Real Time Clock 8 Real Time Clock RTC 8564 U10 The phyCORE MPC555 is equipped with a Real Time Clock This RTC device provides the following features e Serial communication over the bus address 0xA2 up to 400 kHz bus cycles e Power consumption bus active 400 kHz lt 1 mA bus inactive CLKOUT pin inactive 1 pA Clock function with four year calendar Century bit for year 2000 compliance Universal timer with alarm and overflow indication 24 hour format Automatic word address incrementing Programmable alarm timer and interrupt functions If the phyCORE MPCS555 is equipped with a battery VBAT the Real Time Clock runs independently of the board s power supply Programming the Real Time Clock is done via the bus address OxA2 0xA3 with the help of ports SGPIOC7 SCL and SGPIOC6 SDA In standard configuration these processor port pins are connected to the I C bus using the 100 Ohm resistors R38 and R39 Since the MPC555 is not equipped with an internal controller the protocol must be generated with software The Real Time Clock also provides an interrupt output that is extended to the WAKEUP signal via Jumper J15 An interrupt occurs in case of a clock alarm timer alarm timer overflow and event counter alarm It has to be cleared by software With the interrupt function the Real Time
22. unconnected on the target hardware side 51B TSIZ1 Transfer size signal of the MPC555 52B 53B WEI WEO Write enable signal for data lines D 8 15 Alternative AT1 O The alternative function can only be used when no on board memory is populated Write enable signal for data lines D 0 7 Note that DO represents the MSB Alternative ATO O The alternative function can only be used when no on board memory is populated 10 Me technik GmbH 2005 L 523e 5 Pin Description Pin Number Connection I O Comments 55 4 I ARQ4 Interrupt request of the MPC555 Alternative AT2 SGPIOC4 I O 56B MODCK1 I Mode clock select of the MPC555 MODCK1 is active only while PORSET low Afterwards the alternative functions of this pin are available Alternative IRQ5 D SGPIOCS 57B 58B MODCK2 I Mode clock select of MPC555 MODCK3 MODCK2 and MODCK3 are active only while PORSET low Afterwards the alternative functions of these pins are available Alternative IRQ6 IRQ7 D 60B TPUIA I O TPU I O signals connected with the TPU B of 61B B TPUI2 the 555 62B B TPUIO 63B 8 65 B TPU6 66B B TPUA 67B B TPU2 68B TPUO 70B A T2CLK _ I O Clock signal of TPU A of the MPC555 71B A_TPU14 signals connected with the A of
23. 3 are connected to the RxD line of the COM port The ground circuitry of the phyCORE MPC555 must also be connected to the applicable ground pin on the COM port The micrcontroller s on chip UART does not support handshake signal communication However depending on user needs hand shake communication can be replicated using port pins on the microcontroller Use of an RS 232 signal level in support of handshake communication requires use of an external RS 232 transceiver not located on the phyCORE module It is furthermore possible to externally use the TTL signals of both of the UART channels These are located at 53 54 RXD2 TTL TXD2 TTL and XIDI6 XIDI5 RADI TTL TXDI TTL on the phyCORE Connector External connection of TTL signals is required for galvanic decoupling of the interface signals Using solder jumpers J13 and J14 the TTL transceiver outputs of the on board RS 232 devices can be disconnected from the receive lines RXD1_TTL and RXD2_TTL This is required so that the external transceiver does not drive against the on board transceiver The transmit lines TXD1_TTL TXD2_TTL can be connected parallel on the transceiver input without causing a collision PHYTEC Me technik GmbH 2005 L 523e 5 37 phyCORE MPC555 7 2 Interface Two CAN transceivers 82C251 or 80C250 populate the phyCORE MPC555 module at 012 U13 These transceivers enable transmission and receipt of CAN signals via CNTx0
24. 55 54 RDNWR I O Read write RD WR signal of the MPC555 55 BDIP I O Burst data in progress signal of the MPC555 56 BURST I O Burst indicator signal of the MPC555 58 BI STS I O Burst inhibit signal of the MPC555 Alternative special transfer start O 60A TPUIS5 I O TPU I O signals connected to the TPU B of 61A B TPUI3 the MPC555 63A B TPUII 64A TPUO 65A TPU7 66A B_TPUS 68A B_TPU3 69 B_TPU1 70A B T2CLK Clock signal of the TPU B of the 555 71A TPUI5 I O TPU I O signals connected to the TPU A of 73A TPUI3 the MPC555 74 11 75 _ 9 76 A_TPU7 78 _ 5 79A TPU3 80A A TPUI row 1B CLKOUT Processor clock of MPC555 2 1 I IRQI interrupt request of the MPC555 __ Alternative RSV SGPIOCI I O 3B IRQ2 I IRQ2 interrupt request of the MPC555 Alternative CR D SGPIOC2 I O MTS O Per default following a system reset the MTS function is pre selected The function can be configured in the register SIUMCR _ Bits MTSC AB 9B 14B GND Ground 0 V 19B 24B 29B 34B 39B 44B 49B 54B 59B 64B 69B 74B 79B PHYTEC MeBtechnik GmbH 2005 L 523e 5 9 phyCORE MPC555 Connection Comments Pin Number 5B CS3 Free CS signal of the MPC555 6B CSO CS signal of the MPC555 use
25. 9LV400T B 512 kByte ST OO0EE 00EF 20 29LV800T B 1 MB AMD 22DA 225B 01 29LV800T B 1 MB Fujitsu 22DA 225B 04 29LV800T B 1 MB ST 00D7 005B 20 29LV160T B 2 MB AMD 22 4 2249 01 29LV160T B 2 MB Fujitsu 22C4 2249 04 29LV160T B 2 MB ST 22C4 2249 20 Table 5 Flash Memory Device and Manufacturers Overview Use of Flash memory enables in circuit programming of the module The Flash devices on the phyCORE MPC555 are programmable at 3 3 VDC Consequently no dedicated programming voltage is required As of the printing of this manual Flash devices generally have a life expectancy of at least 100 000 erase program cycles 32 PHYTEC Me technik GmbH 2005 L 523e_5 System Memory 6 4 Synchronous BURST SRAM 04 07 Use of synchronous flow through BURST SRAM supports the fastest MPC555 memory interface mode The memory is organized in 32 bit width consisting of four banks These banks appear to the processor as linear address spaces and do not require special activation The SRAM is generally accessed via CS1 without wait states The phyCORE MPC555 can be populated with memory devices of various capacities Generally each memory bank can only be populated with memory devices of a consistent size Configuration of the memory capacity is carried out by hardware using solder jumpers J10 and J18 Table 6 shows all possible memory configurations Capaci
26. AN transmit line TTL of TouCAN module A 555 58D CNRXO CAN receive line TTL of TouCAN module A on the MPC555 With an activated CAN transceiver and J11 closed the transceiver drives this pin 59D 64D 69D GNDA Ground OV for analog signals GNDA is 74D 79D connected to GND using the OR resistor at R31 60D AD15 I O Analog input B AN 59 57 55 of QADC 61D ADI3 module B on the MPC555 62D ADII Alternative B PQA 7 5 3 digital I O 63D B AD9 Analog input AN53 of QADC module on the MPC555 Alternative B MAI of B QADC Alternative B PQAI of the digital I O 65D B AD7 I Analog input B AN 51 49 of QADC 66D AD5 module B on the MPC555 Alternative PQB 7 5 digital input D 67D AD3 I Analog input B AN 3 1 of QADC module 68D ADI B on the MPC555 Alternative B ANZ BANA input D Alternative B POB 3 1 digital input 1 70D A_AD15 Analog input A_AN 59 57 55 of QADC 71D A_AD13 module A the 555 72D A_AD11 Alternative A PQA 7 5 3 digital I O 73D A_AD9 Analog input A AN53 of QADC module A on the MPC555 Alternative A MAI of the A QADC O Alternative PQAI digital I O 75D AD7 I Analog input AN 51 49 of QADC 76D A_AD5 module A on the MPC555 Alternative A_PQB 7 5 digital input TTD AD3 I Analog input AN 3 1 of QADC module 78D A ADI A on the MPC555 Alternative A ANZ A ANX input I
27. CNRXO and B CNTx0 B CNRXO The CAN transceivers support up to Mbaud and up to 110 nodes on a single CAN bus Data transmission occurs with differential signals between CANH and CANL A ground connection between nodes on a CAN bus is not required yet is recommended to better protect the network from electromagnetic interference EMI Additionally the common mode voltage of both CAN transceivers must not exceed a certain threshold 8V 18 for the 82C250 and 40V for the 82C251 If these thresholds cannot be adhered to a galvanized decoupler must be installed This is furthermore recommended for all large CAN networks To decouple signals the lines CANRXO and CANRXO must be disconected from the on board transceiver ICs by means of jumpers J11 and J12 In order to ensure that the CAN transceivers do not use any unnecessary power both can be switched to stand by utilizing jumpers J20 and J21 J20 21 2 3 The CAN TTL signals are routed to the pins of the phyCORE Connector at XID55 X1D56 B CNTXO CNRXO0 and X1D57 X1D58 A CNTXO CNRXO A fast opto coupler should be implemented to galvanically separate external CAN transceivers and the 555 It is recommended to use a Hewlett Packard HCPLO6xx or a Toshiba TLP113 fast opto coupler Parameters for configuring a proper CAN bus system are found in the DS102 norms from the CiA CAN in Automation User and Manufacturer s Interest Group In order to e
28. Clock can be utilized in various applications Closing Jumper J15 allows timed controlled wake up of the phyCORE MPC555 including start up and operation out of power down mode PHYTEC Me technik GmbH 2005 L 523e 5 41 phyCORE MPC555 If the RTC interrupt should be used as a software interrupt which is connected to the corresponding interrupt input of the processor the signal IRTC must be externally connected with a processor interrupt input Additional information on the Real Time Clock registers can be found in the accompanying RTC data sheet Caution After connection of the voltage supply or following a reset the Real Time Clock generates no interrupts as the clock must first be initialized 42 PHYTEC Me technik GmbH 2005 1 523 5 Technical Specifications 9 Technical Specifications The physical dimensions of the 555 are represented in Figure 11 027 3 3 00 9 71 5 0 0 7 Measurements are in mm Figure 11 Physical Dimensions Me technik GmbH 2005 L 523e 5 43 phyCORE MPC555 The height of all components on the top side of the PCB is ca 4 5 mm The PCB itself is approximately 1 25 mm 10 thick The Molex connector pins are located on the underside of the PCB oriented parallel to its two long sides The maximum height of components on the underside of the PCB is 2 mm Additional Technical Data
29. EN bit The register values for CS2 and CS3 depend on the connected peripherals The places designated with an X determine the specific characteristics bus width burst or non burst etc of the bus interface PHYTEC Me technik GmbH 2005 L 523e 5 3l phyCORE MPC555 6 3 Flash Memory 6 3 1 Internal Flash Memory of the 555 To program the internal Flash memory of the MPC555 the on chip Flash must first be unlocked with the EPEE signal EPEE can be contacted via the pin X1D53 in the connector lining the edge of the module EPEE is tied via a pull down resistor to ground This signal must be pulled to high for activation Also EPEE controls switching of the internal Flash s supply voltage from VDDL to VDDH 6 3 2 External Flash Memory U2 U3 Use of Flash as non volatile memory provides the advantages of modern Flash technology Various Flash devices can be used on the phyCORE MPC555 The Flash memory devices used on the phyCORE MPC555 operate in 16 bit mode and are organized in 32 bit with The device at U2 connects to the low data bus while device U3 connects to the high data bus Type Size Manufacturer Device Manufacturer Code Code 29LV200T B 256kByte AMD 223B 22BF 01 29LV200T B 256 kByte Fujitsu 223B 22BF 04 29LV200T B 256 kByte ST 0051 0057 20 29LV400T B 512 kByte AMD 22B9 22BA 01 29LV400T B 512 kByte Fujitsu 22B9 22BA 04 2
30. PIO11 16C MPIO9 19C MPIO7 24C MPIO6 29C 5 a 18C B_CANH CANH output of the CAN transceiver of the second CAN interface 20C ECK I External baud clock input of both UARTs of _ the MPC555 21C RxD2 RxD input of the RS 232 transceiver of the second serial interface J14 must be closed in __ order to use this interface 23C TxD2 TxD output of the RS 232 transceiver of the second serial interface 25C 5 General purpose input output of the 555 Alternative MOSI master out slave in of _ the QSPI interfaces I O 26C 28C QGPIO3 General purpose input output of the MPC555 QGPIOI Alternative PCS3 PCS1 peripheral CS signal of the QSPI interfaces I O MeBtechnik GmbH 2005 L 523e 5 Pin Description Pin Number Connection I O Comments 30C MPIO4 MIOS GPIO signals of the MPC555 38C MPIO3 Alternative VFLS1 VFLSO VFLS bit in MIOSITCR A 31C SCL VO Clock signal The signal can be generated with SGPIOC7 via software or by using an external pin SCL and SGPIOC7 are coupled via the 100R resistor at R38 33C DSDI I Development Serial Data Input of the MPC555 BDM interface Alternative TDI Test Data In of the MPC555 JT AG port The HRCW D11 determines which function is active 34C TRST I Test Reset input of the MPC555 JTAG port TRST is connected with PORESET using a __ 10k
31. ROM memory The on chip BDM interface extends from the MPC555 processor to the Molex connectors aligning the edges of the phyCORE module External BDM signal converter circuitry such as a Wiggler enable connection of MPC555 to a host PC for purposes of debugging and code download Please note that the Development Board for the phyCORE MPCS555 contains such BDM signal converter circuitry through which decoded BDM signals are routed to a DB 25 connector at Pl This enables easy connection of the phyCORE MPC555 as mounted on a Development Board to a host PC for start up download of user code and debugging In addition the original BDM signals from the MPC555 processor are available on 10 pin header connector at X4 the phyCORE MPC555 Development Board Connection to other 3 party BDM devices is possible using this BDM connector refer to Figure 10 PHYTEC Me technik GmbH 2005 L 523e 5 39 phyCORE MPC555 Figure 10 shows the pin assignment for the 10 pin BDM connector X4 on the phyCORE MPC555 Development Board phyCORE Pin BDM phyCORE Pin Connector X1D36 VFLSO 1 2 SRESET X1C10 X1C32 GND 3 4 DSCK X1C35 X1D34 GND z o o 6 VFLSI X1D37 XIDIO HRESET 8 DSDI X1C33 K VCC o 10 DSDO X1D35 Figure 10 10 BDM Connector and Corresponding Pins of the phyCORE Connector X The supply voltage for the external BDM converter depends on the type used For additional information please refer to
32. after 29 6 2 Runtime Memory Model hoe ert UR 3l 6 3 Flash 32 6 3 1 Internal Flash Memory of the 555 32 6 3 2 External Flash Memory U2 03 32 6 4 Synchronous BURST SRAM U4 07 33 6 5 Serial Memory 34 T 37 V 5 232 37 SPIN TRAC 38 7 3 BDM Debug Interface certet aee RO toten prie tatu ri 39 8 Real Time Clock RTC 8564 010 4 42 2 2 12 44 747 41 Technical Specifications 0000000000000 00000000000000 00000000000000 00000000 00e0e0 ne 43 10 Hints for Handling the Module oo000000000 00000000000000 00000000000000 46 11 Revision 2o eiecit tet irren err n Rer vivae el 47 Appendices A 49 A Release NOUS t ee veu loe n eate 49 Rec cH 51 PHYTEC Me technik GmbH 2005 L 523e 5 phyCORE MPC555 Index of Figures and Tables Figure 1 Block Diagram 555 4 Figure 2 View of the phyCORE MPCS555 eere D Figure 3 Pinout of the phyCORE MPC555 Bottom View
33. ation like a big chip Many of the controller port pins accessible at the edges of the board have been assigned alternate functions that can be activated via soft ware Table 1 provides an overview of the pinout of the phyCORE Connector Please refer to the Motorola MPC555 User Manual Data Sheet for details on the functions and features of controller signals and port pins D C B A 1 H B 80 80 80 80 x1 x1 Figure 3 Pinout of the phy CORE MPC555 Bottom View PHYTEC Me technik GmbH 2005 L 523e 5 7 phyCORE MPC555 Pin Number Connection I O Comments X1A 1 EXTCLK Optional external clock input of the MPC555 2A 7A 12A GND Ground 0 V 17A 22A 27A 32A 37A 42A 52A 57 62A 67 72 TIA 3A IRQ3 I interrupt of MPC555 Alternative KR RETRY SGPIOC3 I O 4A IRQO I IRQO interrupt of the MPC555 __ Alternative SGPIOCO I O 5A CS2 Free CS signal of the MPC555 6A CS1 CS signal of processor for control of synchronous SRAM U4 U7 8A WE3 O Write enable signal for the data lines D 24 31 Note that D31 represents the LSB Alternative AT3 O The alternative function may only be used if no on board memory is populated 9A 10A
34. ccessful completion of this cycle PORESET inactive the hard reset cycle is triggered During the hard reset cycle the FET switch is automatically activated in order to set up the local supply voltages VDDH and VDDL The HRESET cycle is fully completed when both local voltages have reached a valid level and the HRESET timeout ca 25 ms of the reset device has finished The processor is now fully functional and will start program execution with the commands given at the reset exception 0x00000100 or OXxFFF00100 Power Off Behavior If the power down mode of the MPC555 has been programmed the bit signal TEXPS TEXP will turn off the FET switches The local supply voltages VDDH and VDDL will drop and the board will remain without current Only the components in the MPC555 that control this mechanism are still supplied with power direct from the 3 3 V input The power consumption is reduced to a minimum PORESET and HRESET remain inactive high during this state Wake Up Behavior After an event that negates the TEXP signal the FET switch is activated again and the HRESET cycle will start Such an event can include a decrementor overflow etc A renewed PORESET cycle will not run Therefore the wake up time of the processor depends only upon the HRESET cycle Events that do not originate from the 555 can also trigger a wake up Such events may include an alarm interrupt of the on board Real Time Clock U10 RTC8563 or a
35. d as control of the on board Flash memory 7B OE Output enable signal of the MPC555 8B 10B 11B 12B 13B 15B 16B 17B 23B 25B 26B 27B A31 A28 A26 A25 A23 A20 A18 A17 A15 A12 A10 A9 YO Address lines A31 is the LSB Alternative SGPIOA31 SGPIOA28 SGPIOA26 SGPIOA25 SGPIOA23 SGPIOA20 SGPIOA18 SGPIOA17 15 12 SGPIOA10 SGPIOA9 I O For use of the alternative function note that the address lines are partially used for memory addressing 18B 20B 21B 22B 28B 30B 31B 32B 37B 38B 40B 41B 42B 43B 45B 46B 33B D31 D28 D26 D25 D23 D20 D18 D17 D15 D13 D10 D8 D7 D5 D2 DO WE2 Data lines D31 is the LSB and DO is the MSB Alternative SGPIOD31 SGPIOD28 SGPIOD26 SGPIOD25 SGPIOD23 SGPIOD20 SGPIOD18 SGPIOD17 SGPIOD15 SGPIOD13 SGPIOD10 SGPIOD8 SGPIOD7 SGPIODS SGPIOD2 SGPIODO I O For use of the alternative function note that the address lines are partially used for memory addressing Write enable signal for data lines D 16 23 Alternative AT2 O The alternative function can only be used when no on board memory is populated 35B BG Bus grant signal of the MPC555 Alternative VFO LWP1 36B 47B 48B 50B BR NC Bus request signal of the MPC555 Alternative VF1 IWP2 Not connected These contacts should remain
36. d laser drilled Microvias components are used on the boards providing phyCORE users with access to this cutting edge miniaturization technology for integration into their own design The phyCORE MPCS555 is a subminiature 72 x 57 mm insert ready Single Board Computer populated with Motorola s PowerPC MPC555 microcontroller Its universal design enables its insertion in a wide range of embedded applications All controller signals and ports extend from the controller to high density 0 635 mm Molex pin header connectors aligning two sides of the board allowing it to be plugged like a big chip into a target application PHYTEC Me technik GmbH 2005 L 523e 5 1 phyCORE MPC555 Precise specifications for the controller populating the board can be found in the applicable controller User s Manual or Data Sheet The descriptions in this manual are based on the MPC555 controller No description of compatible microcontroller derivative functions is included as such functions are not relevant for the basic functioning of the phyCORE MPC555 The phyCORE MPCS55 offers the following features e Single Board Computer in subminiature form factor 72 x 57 mm according to phyCORE specifications e All applicable controller and other logic signals extend to two high density 160 pin Molex connectors e Processor Motorola embedded PowerPC MPC555 40 MHz clock e Internal Features of the MPC555 32 bit PowerPC core 40MHz CPU speed
37. e This phyCORE MPC555 Hardware Manual describes the module s design and functions Precise specifications for the Motorola MPC555 microcontroller series can be found in the enclosed MPC555 microcontroller Data Sheet User s Manual If software is included please also refer to additional documentation for this software In this hardware manual and in the attached schematics low active signals are denoted by a in front of the signal name 1 RD A 0 indicates a logic zero or low level signal while a 1 represents a logic one or high level signal The MSB and LSB of the data and address busses shown in the circuit diagram are based on the conventions of Motorola Accordingly D31 and A31 represent the LSB while DO and AO represent the MSB These conventions are also valid for the parallel I O signals Declaration regarding Electro Magnetic Conformity of the PHYTEC phyCORE MPC555 C PHYTEC Single Board Computers henceforth products are designed for installation in electrical appliances or as dedicated Evaluation Boards 1 for use as a test and prototype platform for hardware software development in laboratory environments Note PHYTEC products lacking protective enclosures are subject to damage by ESD and hence may only be unpacked handled or operated in environments in which sufficient precautionary measures have been taken in respect to ESD dangers It is also necessary that only appropriately trained personnel suc
38. e Internal Resource of the MPC555 Base addresse in IMMR Register Flash memory with BOOT Code 0x0000 0000 default after Reset The capacity of the external Flash 0x0040 0000 memory depends on the memory 0x0080 0000 populated on the phyCORE MPC555 0 00 0 0000 0 0100 0000 0 0140 0000 0 0180 0000 0 01 0 0000 Figure 8 Default Memory Model after Hardware Reset PHYTEC Me technik GmbH 2005 L 523e 5 29 phyCORE MPC555 e Starting from external memory controlled by CSO Configuration 1 2 3 FLEN bit in HRCW is zero After a reset the address space for CSO is pre initialized to 1 MB and begins from the absolute address 0x0000 0000 If the capacity of the external Flash memory exceeds 1 MB the address mask in the ORO register can be changed Starting at address 0x002F 8000 the internal resources reside The base address of the internal resources can be changed in the IMMR register There are seven configurations as shown in Figure 6 After reset the processor run code from the Reset Exception Location at address 0x0000 0100 It is also possible to map the external Flash memory into a completely different address space This is dependent on the application and is further determined by the runtime memory model e Starting from internal Flash memory Configuration 1 1 2 FLEN bit in HRCW is one After reset the internal Flash memory array is present from the absolute address 0x0000 0000 In this case Chip S
39. eat and loosen the bonds Integrating the phy CORE MPCS555 in Application Circuitry Successful integration in user target circuitry depends on whether the layout for the GND connections matches those of the phyCORE module It is recommended that the target application circuitry is equipped with one layer dedicated to carry the GND potential In any case be sure to connect all GND pins neighboring signals that are used in the application circuitry For the supply voltage there must be contact with at least six of the GND pins neighboring the supply voltage pins 46 PHYTEC Me technik GmbH 2005 1 523 5 Revision History 11 Revision History Date Version numbers Changes in this manual 11 Dec 2000 Manual L 523e_1 001 PCB 1169 0 995 PCB 1174 0 First edition 01 Aug 2001 30 Apr 2003 Manual L 523e_2 001 PCB 1169 0 PCM 995 PCB 1174 0 Manual L 523e_3 001 PCB 1169 2 995 PCB 1174 0 Minor revisions regarding spelling errors and conventions Paragraph 4 in Appendix added Description extended to PCB 1169 2 Major revisions in sections 6 and 6 2 Paragraph 2 and 3 in Appendix have been revised This revision history table added 12 Feb 2004 Manual L 523e_4 Top and bottom view to match PCB 1169 5 inserted 001 section 1 2 PCB 1169 5 Pinout Table 1 adjusted to match PCB 1169 5 PCM 995 Table 7 for serial memory
40. elect channel O CSO is disabled During runtime CSO can be re enabled by software The processor run code starting from the Reset Exception Location starting at 0x0000 0100 30 PHYTEC Me technik GmbH 2005 1 523 5 System Memory 6 2 Runtime Memory Model The runtime memory model is configured by software in the internal register of the MPC555 A register set BRx ORx register exists for each Chip Select signal In these registers the base address the size of the address space and the bus characteristic are configured CSO external on board Flash memory CS1 external on board synchronous BURST SRAM CS2 free CS3 free The runtime memory model is dependent on the application Table 4 shows example configurations Address Space Space Peripheral 555 Register 0x0000 0000 448kB yte MPC555 on chip IMMR FLEN 1b 0x0006 FFFF Flash IMMR ISB 000b 0x002F C000 555 Periphery IMMR ISB 000b 0x002F FFFF 0x0000 0000 8 MByte CSO IMMR FLEN 0b 0x007F 0000 on board Flash BRO 0x0000 0003 ORO OxFF80 0020 0x 1000 0000 8 MByte CS1 BR1 0x1000 0001 0 007 FFFF on board SRAM OR 1 OxFF80 0000 0 2000 0000 16 MByte 52 BR2 0 2000 KAKAK 20 FFFF free OR2 OxFFOO KAKA 0x3000 0000 16 MByte CS3 BR3 0x3000 XXXX Ox30FF FFFF free OR3 OxFF00 KAKAK Table 4 Runtime Memory Map The Flash memory space in Table 4 1s either external or internal dependent on the FL
41. fault word is read as HRCW HC 0 the bit pattern CMFCFIG from the internal Flash is read HC 1 the internal default HRCW 0x00000000 is read OR in SMD 0402 J 1 2 2 3 Package Type J6 selects the power supply for the internal SRAM of the MPC555 The module input voltage 3V3 feeds the on chip SRAM The power down power supply VPD feeds the on chip SRAM In the event that there is no 3V3 module input supply the VPD is provided by the battery input OR in SMD 0402 J7 open closed Package Type Selects the source for the positive reference voltage of the A D converter modules of the MPC555 The reference voltage VRH is derived from an external voltage source via phyCORE Connector Pin X1D80 The reference voltage input is connected to the supply network VDDA 5 V OR in SMD 0402 PHYTEC Me technik GmbH 2005 L 523e_5 21 phyCORE MPC555 Jumper default Comment 8 closed Package Type J8 switches Pin 7 of the serial memory at U8 to high level On many memory devices pin 7 enables the activation of a write protection function It is not guaranteed that the standard serial memory populating the phyCORE MPC555 will have this write protection function Please refer to the corresponding memory data sheet for precise information Write protection function is disabled Write protection function is activated OR in SMD 0402 19
42. function MIOS GPIO signals of the MPC555 Alternative VF2 VFO visible instruction queue flush status VF bit in MIOSITPCR Double action I O MDA 30 28 15 of the MPC555 MIOS These signals serve either as input capture or output compare Double action I O MDA 13 11 of the MPC555 MIOS These signals serve either as input capture or output compare Alternatively these signals serve as clock input of the counter submodule MDAO MMCSM6 MDA2 22 47D 48D 50D MPWM6 MPWM4 MPWM2 I O PWM output or I O signals of the MPC555 MIOS MPWM 18 16 2 51D VDDGOOD O Indicator signal for valid supply voltages VDDH 3 3 and VDDL 5 V after the FET switch If the signal is high the voltage is above the HRESET threshold VDDGOOD Inverted VDDGOOD 52D 53D EPEE I EPEE switches the supply voltages of the on chip Flash module on the MPC555 from VDDL 23 3 V to VDDH 5 V It also enables the erase program function 55D 56D B CNTXO CNRXO VO CAN transmit line TTL of TouCAN module on the MPC555 CAN receive line TTL of TouCAN module on the MPC555 With an activated CAN transceiver and Jumper J12 closed the transceiver drives this pin PHYTEC MeBtechnik GmbH 2005 L 523e_5 17 phyCORE MPC555 Pin Number Connection I O Comments 57D C
43. h as electricians technicians and engineers handle and or operate these products Moreover PHYTEC products should not be operated without protection circuitry if connections to the product s pin header rows are longer than 3 m PHYTEC Me technik GmbH 2005 L 523e 5 phyCORE MPC555 PHYTEC products fulfill the norms of the European Union s Directive for Electro Magnetic Conformity only in accordance to the descriptions and rules of usage indicated in this hardware manual particularly in respect to the pin header rows or connectors power connector and serial interface to a host PC Implementation of PHYTEC products into target devices as well as user modifications and extensions of PHYTEC products is subject to renewed establishment of conformity to and certification of Electro Magnetic Directives Users should ensure conformance following any modifications to the products as well as implementation of the products into target systems The phyCORE MPC555 is one of a series of PHYTEC Single Board Computers that can be populated with different controllers and hence offers various functions and configurations PHYTEC supports common 8 16 and selected 32 bit controllers on two types of Single Boards Computers 1 as the basis for Rapid Development Kits which serve as a reference and evaluation platform 2 as insert ready fully functional micro mini and phyCORE OEM modules which can be embedded directly into the
44. k GmbH 2005 L 523e 5 Pin Description Pin Number Connection Comments 75 A_AD6 I Analog input A AN 50 48 of QADC 76 A_AD4 module A on the MPC555 Alternative A_PQB 6 4 digital input 78 A_AD2 I Analog input A_AN 2 0 of QADC module 79C ADO A on the MPC555 Alternative ANY A ANW Alternative A PQB 2 0 digital input I 80C VDDA Voltage supply 5 VDC for analog signals VDDA is coupled with VDDH using a choke at L1 Pin row X1D 1D 2D 3 I Supply Voltage 3 3 VDC 3D 9D 14D GND Ground OV 19D 24D 29D 34D 39D 44D 49D 54D 4D 5D NC Not connected These contacts should remain unconnected on the target hardware side 6D VPD O Power down supply voltage VPD this is generated by VBAT or 3V3 using a diode switch VPD serves as supply voltage for the 555 internal SRAM the Real Time Clock and the serial EPROM 7D PFI I Power fail input is a TTL input that serves as a manual reset input for the PORESET PORESET has a timeout of approximately 50 ms 8D SRESET Soft reset of the MPC555 10D HRESIN I Hard reset input controls the system reset HRESET HRESET has a timeout of approximately 22 ms 11D MPIO14 MIOS GPIO MPIO32B 14 12 10 8 signals 12D MPIO12 of the MPC555 13D MPIO10 15D MPIO8 16D RXD1_TTL Receive line of the first MPC555 UART Alternative gene
45. late the module in support of lower CAN baud rates OR resistor Stand by SMD 0402 Table 2 Jumper Settings H Jumper J10 and J18 might vary because of different memory on the phyCORE MPC555 Me technik GmbH 2005 L 523e 5 Power System and Reset Behavior 4 Power System and Reset Behavior The phyCORE MPC555 must be supplied with two different supply voltages Supply Voltage 1 3 3 V VDDL Supply Voltage 2 5 V VDDH Caution Both supply voltages are necessary for the correct functioning of the phyCORE MPC 555 Never attach a singel supply voltage to the phyCORE MPC555 This might render the board inoperable The power supplies are connected to the module via two field effect transistors FET These FET switches can be switched off via software using the TEXPS bit found in the PLPRCR register This supports the MPC555 s Power Down power savings mode Figure 7 depicts the generation and the distribution of the supply voltages 45V 555 and Periphery 3 3V VDDL 3 3V MPC555 Keep Alive Power int DEC PIT TB RTC TEXP VPD Real Time Clock Serial Memory J19 1 2 VBAT internal SRAM of the MPC555 J6 243 Figure 7 Power Concept PHYTEC Me technik GmbH 2005 L 523e 5 25 phyCORE MPC555 Power On Behavior When both supply voltages are attached to the corresponding ports of the module a power on reset PORESET cycle will start After su
46. mm mated height 6 mm Number of pins per contact row 160 2 rows of 80 Molex part number 55091 1679 lead free PHYTEC part number VB082 e Component height 9 mm mated height 10 mm Number of pins per contact row 160 2 rows of 80 Molex type number 53553 1679 lead free PHYTEC part number VB085 The corresponding mechanical diagrams of the contact elements can be found at www molex com In order to accurately calculate the free space available given the spacing over the PCB provided by the Molex connectors the maximum height of the components on the underside of the phyCORE must be subtracted from the profile of the Molex connectors For instance a 10 mm high Molex connector yields 8 mm of space 10 mm less 2 mm between the phyCORE MPC555 and target circuitry into which it is integrated PHYTEC Me technik GmbH 2005 L 523e 5 45 phyCORE MPC555 10 Hints for Handling the Module Handling of the quartz on the phy CORE MPC555 Removal of the standard quartz is not advisable given the compact nature of the module Should this nonetheless be necessary please ensure that the boards as well as surrounding components and sockets remain undamaged while unsoldering Overheating the board can cause the solder pads to loosen rendering the module inoperable Carefully heat neighboring connections in pairs After a few alternations components can be removed with the solder iron tip Alternatively a hot air gun can be used to h
47. mory configuration of each individual module All four memory banks are typically equipped with the same devices Please note that Jumper J10 must be specifically set in accordance with the board s memory configuration Jumper J10 is only closed when memory devices with a capacity of 512k x 32 36 bits or larger are used In all other cases J10 remains open 32k x 32 36 bits per device J10 open 64k x 32 36 bits per device J10 open 128k x 32 36 bits per device J10 open 256k x 32 36 bits per device J10 open 512k x 32 36 bits per device J10 closed OR in SMD 0402 J19 1 2 2 3 Package Type J19 selects the supply voltage VPD or VDDL of the serial memory VPD is used in the case that a serial SRAM which requires buffering of its memory contents populates the module For EEPROM and FRAM memory VDDL is used as these memory devices are non volatile VPD is used to supply the serial memory at U8 VDDL is used to supply the serial memory at U8 OR in SMD 0402 J20 J21 142 142 243 Package Type J20 and J21 serve to configure the CAN transceiver of both TouCAN channels on the MPC555 82C250 or compatible devices are used as transceivers The CAN signal rise time can be configured via a resistor tied to GND With a OR bridge against VDDH the transceivers can be switched to stand by mode OR resistor minimal rise time To reduce electromagnetic interference EMI a suitable size resistor can popu
48. nsure proper message transmission via the CAN bus a 120 Ohm terminating resistor must be connected to each end of the CAN bus between the pins delivering the CAN_H and CAN_L signals 1 in Automation Founded in March 1992 CiA provides technical product and marketing information with the aim of fostering Controller Area Network s image and providing a path for future developments of the CAN protocol 38 PHYTEC Me technik GmbH 2005 1 523 5 Serial Interfaces Configuration of the on board transceiver Using jumpers J20 and J21 the transceivers at U12 and U13 can be switched to stand by 2 3 Furthermore it is possible to configure the rise time using resistors to close both jumpers at 1 2 leaving 2 3 open With the usage of lower baud rates this achieves a decrease of noise emissions on the CAN bus Further information can be found in the data sheets for the Philips 82C250 82C251 transceiver chips 7 3 BDM Debug Interface The MPC555 offers an on chip Background Debug BDM interface This interface allows external debug access to the controller without requiring any service software or firmware such as a monitor program on the chip This internal debug interface furthermore contains hardware features supporting use with common cross development systems and debug environments such as Metrowerks CodeWarrior For instance the MPC555 features internal breakpoint registers enabling debugging in Flash
49. nt of a power failure Various serial memory devices can be installed at U8 including EEPROM FRAM or SRAM The capacity of these memory devices ranges from 512 Byte to 32 kByte When using SRAM at U8 solder jumper J19 must be connected at pins 1 2 to supply the memory device via VPD Because MPC555 has no interface this protocol must be generated with software The processor port pins SGPIOC6 and SGPIOC7 are connected to SDA and SCL using resistors R39 and R38 per default Table 7 gives an overview of the possible devices for use at US as of the printing of this manual Type Size rc Address Write Life of Device Manufacturer Frequency Pins cycles Data EEPROM 256 512 400 kHz A2 Al 1 000000 100 24 02 04 CATALYST Byte A0 Years 1 2 400 kHz 2 Al 1 000 000 100 24 08 16 AO Years 4 8 kByte 400 kHz 2 Al 1000000 100 24 32 64 CATALYST AO Years 32 kByte 1 MHz Al AO 100000 100 CAT24WC256 CATALYST Years FRAM 512 Byte 1 MHz A2 Al 10 billion 10 FM24CL04 RAMTRON Years 8 kByte 1 MHz A2 Al 10 billion 10 FM24CL64 RAMTRON AO Years SRAM 256 Byte 100 kHz A2 Al l PCF8570 PHILIPS AO Table 7 Memory Options for the Serial Memory U8 Note that the RTC is also connected to the bus The RTC can operate with a bus frequency up to 400 kHz It is advised not to allow higher bus frequency for the access
50. ontrols the FET switch of the 3V VDDL and 5 V VDDH supply voltages 56C WAKEUP Low level at WAKEUP completes a module shut down and prompts activation of the voltage supply On the module the RTC interrupt IRTC can be connected to W AKEUP using Jumper J15 WAKEUP should have a wired OR connection against GND 58C 59C ETRIG2 ETRIGI Trigger inputs of the QADC modules A and B on the MPC555 60C B_AD14 Analog input B AN 58 56 of QADC 61C B_AD12 module B on the MPC555 Alternative B_PQA 6 4 digital I O 62C 67C 72C GNDA Ground OV for analog signals TIC GNDA is connected to GND using the OR resistor at R31 63C B_AD10 Analog input BAN 54 52 of QADC 64C ADS module B on the MPC555 Alternative B MA 2 0 Alternative B PQA 2 0 digital I O 65C B AD6 I Analog input B AN 50 48 of QADC 66C AD4 module B on the MPC555 Alternative B POB 6 4 digital input D 68C Analog input B AN 2 0 of QADC module 69C B ADO B on the MPC555 Alternative B ANY B ANW I Alternative B_PQB 2 0 digital input D 70 A_AD14 Analog input A_AN 58 56 of QADC 71C ADI2 module A on the MPC555 Alternative POA 6 4 digital I O 73C A_AD10 Analog input A_AN 54 52 of QADC 74C ADS8 module A on the MPC555 Alternative MA 2 0 Alternative A PQA 2 0 digital I O PHYTEC Me techni
51. ral purpose input If the alternative function is used solder jumper J13 must be open in order to disconnect the receive output of the RS 232 transceiver 17D TXDI TIL Transmit line of the first MPC555 UART Alternative QGPO1 general purpose output PHYTEC Me technik GmbH 2005 L 523e 5 15 phyCORE MPC555 Pin Number Connection Comments 18D 20D B_CANL A_CANL CANL output of the CAN transceiver for the second CAN interface CANL output of the CAN transceiver for the first CAN interface 21D 22D A_CANH RxD1 output of CAN transceiver for the first CAN interface RxD input of the RS 232 transceiver for the first serial interface Jumper J13 must be closed to use this interface 23D 25D 26D TxD1 QGPIO6 QGPIO4 TO TO TxD output of the RS 232 transceiver for the first serial interface General purpose input output of the MPC555 Alternative SCK clock of the QSPI interface WO General purpose input output of the MPC555 Alternative MISO Master In Slave Out of the QSPI interface I O 27D QGPIO2 VO General purpose input output of the MPC555 Alternative PCS2 peripheral CS signals of the QSPI interfaces I O 28D 30D 31D QGPIOO SGPIOC7 SGPIOC6 General purpose input output of the 555 Alternative PCSO
52. roadcast photomechanical or similar reproduction and storage or processing in computer systems in whole or in part are reserved No reproduction may occur without the express written consent from PHYTEC Me technik GmbH EUROPE NORTH AMERICA Address PHYTEC Technologie Holding AG PHYTEC America LLC Robert Koch Str 39 203 Parfitt Way SW Suite G100 D 55129 Mainz Bainbridge Island WA 98110 GERMANY USA Ordering 49 800 0749832 1 800 278 9913 Information order phytec de sales phytec com Technical 49 6131 9221 31 1 800 278 9913 Support support phytec de support phytec com Fax 49 6131 9221 33 1 206 780 9135 Web Site http www phytec de http www phytec com 5th Edition July 2005 PHYTEC Me technik GmbH 2005 L 523e 5 Contents 1 1 IntroductioHna 1 11 1 a A NG AN 4 1 2 View of the phy COREBE MPG5359 retire HIS 5 2 ImDescript n deren eniseceoudeseusubyo ice cued eue vus us de agna dva 7 3 lbs a be TREE A EN a 19 4 Power System and Reset Behavior 00000000000000 000000000 25 5 Start up System Configuration 00000000000000 0000000000000000 27 5 1 Power On Reset PRase igs eters eal ette dte 27 5 2 Hard Reset Configuration 28 System Memory 29 6 1 Memory Model
53. s available at pins X1D58 CAN_A and X1D56 CAN_B This is useful for optically decoupling the CAN bus signals from the core logic The CAN receive signals _ and B CANRXO are disconnected from the CAN transceiver and are available at pin 1058 A CANRXO and X1D56 B CNRXO The CAN receive signals A CANRXO and B CANRXO are connected to the CAN transceiver OR in SMD 0402 22 Me technik GmbH 2005 L 523e 5 Jumpers Jumper default Comment J13 J14 open closed Package Type and J14 connect the receive lines of both MPC555 UARTs to the RS 232 transceiver at U11 When left open the controller s RS 232 TTL signals are available at pins X1D16 RXD1_TTL and X1C53 RXD2_TTL This is useful for optically decoupling the RS 232 signals from the core logic The UART receive signals RXD1_TTL and RXD2_TTL are disconnected from the RS 232 transceiver These signals are available at X1D16 RXD1_TTL and X1C53 RXD2_TTL The UART receive signals RXD1_TTL and RXD2_TTL are connected to the RS 232 transceiver OR in SMD 0402 J15 open closed Package Type Jumper J15 connects the alarm interrupt output of the Real Time Clock RTC to the WAKEUP signal of the power supply Through programming of the RTC alarm functions a precise wake up from a power down can be executed The signal IRTC is disconnected from the WAKEUP input WAKEUP is tied to the
54. ted MODCK 1 3 010 Table 3 Clock Mode Configuration via Jumpers J2 J3 and J4 PHYTEC Me technik GmbH 2005 L 523e 5 27 phyCORE MPC555 5 2 Hard Reset Configuration Word The components of the MPC555 which are necessary for accessing and executing of the start up code are initialized during the hard reset phase A data value the hard reset configuration word HRCW determines the initialization process The HRCW can be supplied by various sources Possible sources are the data bus the internal on chip Flash memory or an internal default data value The sources for the HRCW is determined by two conditions setting of jumper J5 and the HC bit in the internal Flash memory External HRCW When the HC bit in internal Flash memory is cleared HC 1 and J5 is closed at 1 2 the HRCW is read via the data bus On the phyCORE the data bus is connected with pull down resistors except D20 The signal level of D20 is configured to low or high via jumper Jl D20 determines the Flash memory that is active after reset 1 2 internal Flash 2 3 external Flash Internal Default HRCW If JS is closed at 2 3 and HC 1 Flash is cleared then the internal default HRCW 0x00000000 1s read Internal Flash HRCW CMFCFIG If JS is closed at pins 2 3 and HC 0 the bit pattern CMFCFIG from the internal Flash is read 28 PHYTEC Me technik GmbH 2005 1 523 5 System Memory 6 System
55. to serial memory The RTC has the bus slave address 2 The slave address of the serial memory can be configured via solder jumpers J16 Al and J17 A2 in a manner that avoids signal collision The address input AO is hard wired to GND 34 PHYTEC Me technik GmbH 2005 1 523 5 System Memory Address of the Serial Memory Te a oo Par OxA 17 16 GND Figure 9 Slave Address of the Serial Memory US Below are possible configurations Address J16 JA7 A1 A2 0 1 142 2 3 OxAA OxAS 243 248 Ox AS Ox A9 1 2 1 2 OxAC OxAD 248 Table 8 Address of the Serial Memory When selecting the slave address of the serial memory please note that not all memory types make address pins Al and A2 externally available to the user PHYTEC Me technik GmbH 2005 L 523e 5 35 phyCORE MPC555 36 PHYTEC Me technik GmbH 2005 1 523 5 Serial Interfaces 7 Serial Interfaces 7 1 RS 232 Interface A dual channel RS 232 transceiver is located the phyCORE MPC555 at U11 This device adjusts the signal levels for the RXDI TTL RXD2 TTL and TXDI TTL TXD2 lines The RS 232 interface enables connection of the module to a COM port on a host PC In this instance the RxD1 or RxD2 line X1D22 X1C21 of the transceiver are connected to the TxD line of the COM port while the TxD1 or TxD2 line X1D23 X1C2
56. ty Type Device J18 J10 128 kByte 32k x 32 36 bit UA 144 243 open 256 kByte 32k x 32 36 bit U4 5 1 4 2 3 64k x 32 36 bit U4 3 6 5 8 384 32k x 32 36 bit U4 6 1 4 2 3 512 32k x 32 36 bit U4 7 1 4 2 3 64k x 32 36 bit U4 5 3 6 5 8 128k x 32 36 bit U4 5 6 7 8 768 64k x 32 36 bit U4 6 3 6 5 8 1 MB 64k x 32 36 bit U4 7 3 6 5 8 128k x 32 36 bit U4 5 5 6 7 8 256k x 32 36 bit U4 4 7 8 9 open 1 512 MB 128k x 32 36 bit U4 6 5 6 7 8 2 128k x 32 36 bit U4 7 5 6 7 8 256k x 32 36 bit U4 5 4 7 8 9 open 512k x 32 36 bit U4 6 9 closed 3 MB 256k x 32 36 bit U4 6 4 7 849 open 4 MB 256k x 32 36 bit U4 7 4 7 849 open 512k x 32 36 bit U4 5 6 9 closed 6 MB 512k x 32 36 Bit U4 6 6 9 closed 8 MB 512k x32 36 bit U4 7 6 9 closed Table 6 Memory Options for the Synchronous BURST SRAM Caution The address space for the memory bank must always be configured to the maximum possible memory space That means that if for example only one memory device with 256k x 32 36 bit capacity is populated the address space has to be set to 4 MByte PHYTEC Me technik GmbH 2005 L 523e 5 33 phyCORE MPC555 6 5 Serial Memory US The phyCORE MPCS555 is populated with a non volatile memory device with a serial interface This memory serves as storage for configuration data or parameters that must be protected in the eve
57. user s peripheral hardware design PHYTEC s microcontroller modules allow engineers to shorten development horizons reduce design costs and speed project concepts from design to market PHYTEC Me technik GmbH 2005 L 523e 5 Introduction 1 Introduction The phyCORE MPC555 belongs to PHYTEC s phyCORE Single Board Computer module family The phyCORE SBCs represent the continuous development of PHYTEC Single Board Computer technology Like its mini micro and nanoMODUL predecessors the phyCORE boards integrate all core elements of a microcontroller system on a sub miniature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments As independent research indicates that approximately 70 96 of all EMI Electro Magnetic Interference problems stem from insufficient supply voltage grounding of electronic components in high frequency environments the phyCORE board design features an increased pin package The increased pin package allows dedication of approximately 20 of all pin header connectors on the phyCORE boards to Ground This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE boards even in high noise environments phyCORE boards achieve their small size through modern SMD technology and multi layer design In accordance with the complexity of the module 0402 packaged SMD an

Hardware Manual - Phytec Messtechnik GmbH

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