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System Resets, Interrupts, and Operating Modes

1. USART Peripheral Interface UART Mode 13 21 USART Registers UART Mode UxCTL USART Control Register 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 1 PENA Bit 7 Parity enable 0 Parity disabled 1 Parity enabled Parity bit is generated UTXDx and expected URXDx In address bit multiprocessor mode the address bit is included in the parity calculation PEV Bit 6 Parity select PEV is not used when parity is disabled 0 Odd parity 1 Even parity SPB Bit 5 Stop bit select Number of stop bits transmitted The receiver always checks for one stop bit 0 One stop bit 1 Two stop bits CHAR Bit 4 Character length Selects 7 bit or 8 bit character length 0 7 bit data 1 8 bit data LISTEN Bit 3 Listen enable The LISTEN bit selects loopback mode 0 Disabled 1 Enabled UTXDx is internally fed back to the receiver SYNC Bit 2 Synchronous mode enable 0 UART mode 1 SPI Mode MM Bit 1 Multiprocessor mode select 0 Idle line multiprocessor protocol 1 Address bit multiprocessor protocol SWRST Bit 0 Software reset enable 0 Disabled USART reset released for operation 1 Enabled USART logic held in reset state 13 22 USART Peripheral Interface UART Mode USART Registers UART Mode UxTCTL USART Transmit Control Register 7 rw 0 Unused CKPL SSELx URXSE TXWAKE Unused TXEPT Bit 7 Bit 6 Bits 5 4 Bit 3 Bit 2 Bit 1 Bit 0 5
2. 13 21 Contents 14 USART Peripheral Interface SPI Mode 14 1 14 1 USART Introduction SPI Mode 0 cece esee en 14 2 14 2 USART Operation SPI Mode 14 4 14 2 1 USART Initialization and 14 4 14 2 2 Master eh Beater ides ek See ae Se cea EE eh es 14 5 14 2 8 Slave Mode 0 ccc eee hn 14 6 14 2 4 SPI Enable nobi nope hb Ee eats ERNEUT nis 14 7 14 2 5 Serial Clock Control llllsssssesesssesessss ens 14 9 14 2 6 SPI Interrupts 0 s m 14 11 14 3 USART Registers SPI Mode 14 13 15 USART Peripheral Interface IC Mode 15 1 15 1 12C Module Introduction visive dca ad utis et Parvi Re re b en aa Cem 15 2 15 2 Module Operation 50535 Sted teste ted AS ttes elei ipfe 15 4 15 23 86 Seal Data nass eden istud iino at E Mese bbs maed Pada pida 15 5 15 2 2 12 START STOP Conditions 15 6 15 2 3 12 Addressing Modes 15 7 15 2 4 12 Module Operating Modes 15 8 15 2 5 The 2C Data Register I2CDR 15 15 15 2 6 12C Clock Generati
3. n n hne 3 9 3 3 1 sHegister Mode e ie E Sea ea ee i es 3 10 3 3 2 Indexed Mode e keel eR DER ein pid eed Reena 3 11 3 3 3 Symbolic Mode E E eens 3 12 3 9 4 Absolute Mode sic setae peter nea thas ates itis 3 13 3 8 5 Indirect Register Mode 3 14 3 8 6 Indirect Autoincrement Mode 3 15 3 3 7 Immediate Mode 0 cece eee 3 16 INSHUCHON Seine fine Gee eet Se Bene peces Bahri i Me Gad dag d RR Road 3 17 3 4 1 Double Operand Format 1 Instructions 3 18 3 4 2 Single Operand Format Il Instructions 3 19 3 4 9 Jumps eee eet ae tee rl ceci ere iae de 3 20 3 4 4 Instruction Cycles and Lengths 3 72 3 4 5 Instruction Set Description 0 00 eens 3 74 A Basic Clock Module 4 0 9 0 oon cae ie SEAS evi Ra ae ae 4 1 4 1 Basic Clock Module Introduction 0 0 cece cece teen eens 4 2 4 2 Basic Clock Module Operation 4 4 4 2 1 Basic Clock Module Features for Low Power Applications 4 4 4 2 2 OscillatOr Ran ena dtes Dae 4 5 42 3 XT2 Osclllator ean eee ERU ees 4 6 4 2 4 D
4. 2 p Fault Interrupt Request E XT10ff P LFXT1 OscFault e XT OscFault gt XT2off OF IRQ NMI l XT2 OscFault ARQA e xr e IFG1 1 OFIE IE1 1 Clear IRQA LENNON gt Mal yer RE ER ae tg ah RELIER ee jc emp are Xe 7 lies oii Soak etna oe Ae re tua rs MM DS Oscillator Fault Fail Safe Logic e XTS m M d XSELM1 e SELMO IDH oe Fault_from XT2 Fault from XT1 e m E r zer plusque 21 XT2 Is an internal signal 2 0 on devices without 2 MSP430x11xx and MSP430x12xx XT2 1 on devices with XT2 MSP430F 13x MSP430F14x MSP430F 15x and MSP430F16x IRQA Interrupt request accepted LFXT1_OscFault Only applicable to LFXT1 oscillator in HF mode Basic Clock Module 4 11 Basic Clock Module Operation Sourcing MCLK from a Crystal 4 12 After a PUC the basic clock module uses DCOCLK for MCLK If required MCLK may be sourced from LFXT1 or XT2 The sequence to switch the MCLK source from the DCO clock to the crystal clock LFXT1CLK or XT2CLK is 1 Switch on the crystal oscillator 2 Clear the OFIFG flag 3 Wa
5. M3P Timer A Introduction Figure 11 1 Timer A Block Diagram 1 Timer Block TASSELx ID MCx TACLK 00 Divider 16 OI Tuner Count loi 1 2 4 8 gt la Mode EQUO i Clear SMCLK 10 i INCLK 11 SetTAIFG lm W n EET AE EE E E AE CCRO CCR1 CCR2 i CCISx CMx i CCI2A 00 Capture ccieB o1 Mode CCR2 4101 vec 11 4 CCI i EQU2 CAP i i A Y EN Set TACCR2 CCIFG i OUT Output Unit2 OUT2 Signal EQUO a Timer A 11 3 Timer A Operation 11 2 Timer A Operation The Timer A module is configured with user software The setup and operation of Timer A is discussed in the following sections 11 2 1 16 Bit Timer Counter The 16 bit timer counter register TAR increments or decrements depending on mode of operation with each rising edge of the clock signal TAR can be read or written with software Additionally the timer can generate an interrupt when it overflows TAR may be cleared by setting the TACLR bit Setting TACLR also clears the clock divider and count direction for up down mode OLLI AUOD S Note Modifying Timer A Registers It is recommended to stop the timer before modifying its operation with exception of the interrupt enable and i
6. eee teen eee ees 18 9 18 2 6 ADC10 Data Transfer 18 15 18 2 7 Using the Integrated Temperature Sensor 18 21 18 2 8 A D Grounding and Noise Considerations 18 22 18 2 9 ADC10 Interrupts 0 06 18 23 18 3 ADG10 Registers ise sebbene ender atone nbes vate 18 24 19 DAC12 et tot a Ee alot ch ieee 19 1 194 4DAGT12 INTRODUCTION uod ote e ede te ate eee 19 2 19 2 DAC12 Operation 0 nnet dennig Nanri a ga rh 19 4 19 24 DACT12 Core hors tka wel hee eR Op abd RN TOI RES 19 4 19 2 2 DAC12 Reference 19 5 19 2 3 Updating the DAC12 Voltage Output 19 5 19 2 4 DAC12 xDAT Data Format 19 6 19 2 5 DAC12 Output Amplifier Offset Calibration 19 7 19 2 6 Grouping Multiple DAC12 Modules 19 8 19 2 7 Using DAC12 With the DMA Controller 19 9 19 2 8 DAC12 Interrupts 00 tenets 19 9 19 8 DAG12 Registers oe bee DO ce eae tate s 19 10 xii Chapter 1 Introduction This chapter describes the architecture of the MSP430 Topic Page T Architecture 1 2 12 Flexible Clock e 1 2 1 31 Em
7. 1 Note Watchdog Timer Powers Up Active After a PUC the WDT module is automatically configured in the watchdog mode with an initial 32 ms reset interval using the DCOCLK The user must setup or halt the WDT prior to the expiration of the initial reset interval LLLLL O A A A A A A Watchdog Timer Watchdog Timer Introduction Figure 10 1 Watchdog Timer Block Diagram WDTCTL MSB MDB 16 bit Password Pulse Counter Compare Generator 16 bit Tue Cc Write Enable Low Byte R W SMCLK WDTHOLD ACLK WDTNMIES WDTNMI WDTTMSEL Watchdog Timer 10 3 Watchdog Timer Operation 10 2 Watchdog Timer Operation The WDT module can be configured as either a watchdog or interval timer with the WDTCTL register The WDTCTL register also contains control bits to configure the RST NMI pin WDTCTL is a 16 bit password protected read write register Any read or write access must use word instructions and write accesses must include the write password 05Ah in the upper byte Any write to WDTCTL with any value other than 05Ah in the upper byte is a security key violation and triggers a PUC system reset regardless of timer mode Any read of WDTCTL reads 069h i
8. 0 Receive ae USPIEx 1 Solos Handle Interrupt Disable Enabled External Clock Character Conditions USPIEx 0 Present Character USPIEx 1 Received PUC USPIEx 0 USART Peripheral Interface SPI Mode USART Operation SPI Mode 14 2 5 Serial Clock Control UCLK is provided by the master on the SPI bus When MM 1 BITCLK is provided by the USART baud rate generator on the UCLK pin as shown in Figure 14 8 When MM 0 the USART clock is provided on the UCLK pin by the master and the baud rate generator is not used and the SSELx bits are don t care The SPI receiver and transmitter operate in parallel and use the same clock source for data transfer Figure 14 8 SPI Baud Rate Generator UCLKI ACLK SMCLK SMCLK Compare 0 or 1 ix BITCLK R Modulation Data Shift Register LSB first mX m7 8 m0 A UxMCTL Bit Start The 16 bit value of UXBRO UxBR1 is the division factor of the USART clock source BRCLK The maximum baud rate that can be generated in master mode is BRCLK 2 The modulator in the USART baud rate generator is not used for SPI mode and is recommended to be set to 000h The UCLK frequency is given by BRCLK Baud rate UxBR with UxBR UxBR1 UxBRO USART Peripheral Interface SPI Mode 14 9 USART Operation SPI Mode Serial Clock Polarity and Phase The polarity and phase of UCLK are independently configured via the CKPL and CKPH control
9. 10 2 10 2 Watchdog Timer Operation 0 0 cece eee eee 10 4 10 2 1 Watchdog Timer Counter 10 4 10 2 2 Watchdog Mode 10 4 10 2 3 Interval Timer Mode 10 4 10 2 4 Watchdog Timer Interrupts 2 0 0 eee 10 5 10 2 5 Operation in Low Power Modes 10 6 10 2 6 Software Examples 10 6 10 3 Watchdog Timer Registers 10 7 AT TimMer DERE 11 1 11 1 Timer A Introduction sss dsrs eee a 11 2 11 2 Timer A hn 11 4 11 2 1 16 Bit Timer Counter 0 0 00 teenies 11 4 11 2 2 Starting the Timer Misean iaaa cece cnet ees 11 5 11 2 3 Timer Mode Control 0 00 cect eee eens 11 5 11 2 4 Capture Compare Blocks 11 11 11 2 5 oio ciate Ri rati MEE 11 13 11 2 6 Timer Interrupts Eee a eh 11 17 11 3 Timer A Beglsters soe mew Ue X ay ular ob DUE RR UEX vir Rs 11 19 12 Timer icr hee vita x cedere ois ica e eee ede were 12 1 12 1 Timer B Introduction arenero rnama ma I RII 12 2 12 1 1 Similarities
10. SHI tsample gt lt tconvert gt ADC12 ADC12 Operation Sample Timing Considerations When SAMPCON 0 all Ax inputs are high impedance When SAMPCON 1 the selected Ax input can be modeled as an RC low pass filter during the sampling time tsampje as shown below in Figure 17 5 An internal MUX on input resistance Rj max 2 in series with capacitor Cj max 40 pF is seen by the source The capacitor voltage Vc must be charged to within 1 2 LSB of the source voltage Vs for an accurate 12 bit conversion Figure 17 5 Analog Input Equivalent Circuit Vs Rs MSP430 Input voltage at Ax RI Vs External source voltage Rg External source resistance Vo Internal MUX on input resistance C Input capacitance CI Capacitance charging voltage The resistance of the source Rg and R affect tsample The following equation can be used to calculate the minimum sampling time tsample for a 12 bit conversion t Rg x 11 213 x 1 gt sample Substituting the values for Rj and C given above the equation becomes t Rg 2kQ x 9 011 x 40pF 2 gt sample For example if Rg is 10 tsample must be greater than 4 33 us ADC12 17 9 ADC12 Operation 17 2 5 Conversion Memory There are 16 ADC12MEMXx conversion memory registers to store conversion results Each ADC12MEMX is configured with an associated A
11. Example 1 E BIS NMIIE OFIE ACCVIE amp 1 Instruction Example 2 BIS Mask amp IEl Mask enables only interrupt sources RETI End of NMI Interrupt Handler E SGS a LIE OECD SL Note Enabling NMI Interrupts with ACCVIE NMIIE and OFIE The ACCVIE NMIIE and OFIE enable bits should notbe set inside of an NMI interrupt service routine unless they are set by the last instruction of the routine before the RETI instruction Otherwise nested NMI interrupts may occur causing stack overflow and unpredictable operation _ _ _ 2 2 2 Maskable Interrupts Maskable interrupts are caused by peripherals with interrupt capability including the watchdog timer overflow in time mode Each maskable interrupt source can be disabled individually by an interrupt enable bit or all maskable interrupts can be disabled by the general interrupt enable GIE bit in the status register SR Each individual peripheral interrupt is discussed in the associated peripheral module chapter in this manual System Resets Interrupts and Operating Modes System Reset and Initialization 2 2 3 Interrupt Processing When an interrupt is requested from a peripheral and the peripheral interrupt enable bit and GIE bit are set the interrupt service routine is requested Only the individual enable b
12. eeeseseeeeeee nnn nn nnn nnn 6 1 6 1 Introduction oni EUR o CORRIERE GEM UNE 6 2 6 2 SVS Operation el eis Sie ee 6 4 6 21 Configuring the SVS nett eee 6 4 6 2 2 SVS Comparator Operation 6 4 6 23 Changing the VLDx Bits 0 0 cece eens 6 5 6 24 SVS Operating Range 6 6 6 3 SVS Registe S soccer CURE COR CR ane ate RIEGO 6 7 7 Hardware Multiplier IRI III IIR 7 1 7 1 Hardware Multiplier Introduction 7 2 7 2 Hardware Multiplier Operation 00 cece cee III 7 3 7 2 1 Operand Registers 0 000 teen eee eens 7 3 7 2 2 Result Registers 0 a R eee 7 4 7 2 3 Software Examples 0 00 eee een eee eens 7 5 7 2 4 Indirect Addressing of RESLO 0 00 eee eee eee 7 6 2 5 Usimg Interr pts oss Saeed mad knew esl beach Ghee med ipe dang wens 7 6 7 3 Hardware Multiplier Registers 7 7 DMA Controller 2 carn qu eae Jeet Ec eai date 8 1 8 1 DMA Introduction eee a eens 8 2 8 2 DMA Operations au eth cea daw tale pad LAE QUE ease 8 4 8 21 DMA Addressing
13. SMCLK Sub main clock SMCLK is software selectable as LFXT1CLK XT2CLK if available or DCOCLK SMCLK is divided by 1 2 4 or 8 SMCLK is software selectable for individual peripheral modules The block diagram of the basic clock module is shown in Figure 4 1 Basic Clock Module Figure 4 2 Basic Clock Block Diagram Basic Clock Module Introduction DIVAx Divider gt LFXTCLK OSCOFF XTS 1 2 4 8 ACLK Auxillary Clock SELMx Divider 1 2 4 8 XIN mn L XOUT o ETAT X vhi en 1 gt XT2CLK XT20FF XT2IN je XT20UT XT2 Oscillator n CCP cde E MODx DCOR SCGO RSELx off DC Generator P2 5 Rosc Modulator lt MCLK gt DCOCLK Main System Clock SELS DIVSx Divider 1 2 4 8 Sub System Clock Note XT2 Oscillator The XT2 Oscillator is not present on MSP430x11xx or MSP430x12xx devices The LFXT1CLK is used in place of XT2CLK Basic Clock Module 4 3 Basic Clock Module Operation 4 2 Basic Clock Module Operation 4 2 1 4 4 After a PUC MCLK and SMCLK are sourced from DCOCLK at 800 kHz see device specific datasheet for parameters and ACLK is sourced from LFXT1 in LF mode Status register control bits SCGO SCG1 OSCOFF and CPUOFF configure the MSP430 operating modes and enable or disable portions of the basic
14. 2 0 No 8x SCL js Ack nox 1 Stop State I2CSTP is Cleared USART Peripheral Interface I C Mode I2CBB is Cared Yes I2CSTP 1 7 x l2CPSC 4 x l2CPSC 4 x l2CPSC 15 9 12C Module Operation Figure 15 10 Master Receiver Mode I2ZCWORD 1 IDLE l2CSTT 1 4 x l2CPSC Generate Start Condition from l2CSTT 1 4 x l2CPSC I2CBB is Set 2CSTT is Cleared Send Slave Address bits 6 0 with RAW No Ack Ack XA 1 10 bit address Send Slave Address bits 9 7 extended with R W No Ack 4 x l2CPSC Generate 2nd Start Condition from Ack Ack XA 0 7 bit address Send Slave Address bits 6 0 with R W Receive Data Low Byte from Slave Receive Data High Byte from Slave 15 10 USART Peripheral Interface 2 Mode Yes I2CRM 1 Stop State Yes Yes I2CSTP 1 Yes I2CSTP 1 7 x l2CPSC 4 x l2CPSC I2CBB is Seed 4 x l2CPSC I2CSTP is Arbitration 12C Module Operation If two or more master transmitters simultaneously start a transmission on the bus an arbitration procedure is invoked Figure 15 11 illustrates the arbitration procedure between two devices The arbitration procedure uses the data presented on SDA by the competing transmitters The first master transmitter that generates a lo
15. TEXAS INSTRUMENTS MSP430x1xx Family User s Guide 2003 Mixed Signal Products SLAU049C IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed Tl assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other
16. VCC U a S TCK VCC Reset G 5 my P6 7 A7 50us gt M Set POR D3D pe tReset 50us NE iid SVSOut e 1 25V WH Set SVSFG SVSCTL Bits Supply Voltage Supervisor 6 3 SVS Operation 6 2 SVS Operation The SVS detects if the AVcc voltage drops below a selectable level It can be configured to provide a POR or seta flag when a low voltage condition occurs The SVS is disabled after a POR to conserve current consumption 6 2 1 Configuring the SVS The VLDx bits are used to enable disable the SVS and select one of 14 threshold levels V sys for comparison with AVcc The SVS is off when VLDx 0 and on when VLDx gt 0 The SVSON bit does not turn on the SVS Instead it reflects the on off state of the SVS and can be used to determine when the SVS is on When VLDx 1111 the external SVSin channel is selected The voltage on SVSin is compared to an internal level of approximately 1 2 V 6 2 2 SVS Comparator Operation A low voltage condition exists when AVcc drops below the selected threshold or when the external voltage drops below its 1 2 V threshold Any low voltage condition sets the SVSFG bit The PORON bit enables or disables the device reset function of the SVS If PORON 1 a POR is generated when SVSFG is set If PORON 0 a low voltage condition sets SVSFG but does not generate a POR The SVSFG bit is latched This allows user software to determine if a lo
17. d d Unsigned multiply accumulate d c 16x16 bits 16x8 bits 8x16 bits 8x8 bits The hardware multiplier block diagram is shown in Figure 7 1 Figure 7 1 Hardware Multiplier Block Diagram MPY 130h MPYS 132h MAC 134h MACS 136h Accessible Register MPY 0000 MACS MPYS MAC 32 bit Multiplexer RESHI 13Ch RESLO 13Ah 31 rw rw 0 SUMEXT13En 13Eh eee 7 2 Hardware Multiplier Hardware Multiplier Operation 7 2 Hardware Multiplier Operation The hardware multiplier supports unsigned multiply signed multiply unsigned multiply accumulate and signed multiply accumulate operations The type of operation is selected by the address the first operand is written to The hardware multiplier has two 16 bit operand registers OP1 and OP2 and three result registers RESLO RESHI and SUMEXT RESLO stores the low word of the result RESHI stores the high word of the result and SUMEXT stores information about the result The result can be read with the next instruction after writing to OP2 except when using an indirect addressing mode 7 2 1 Operand Registers The operand one register OP1 has four addresses shown in Table 7 1 used to select the multiply mode Writing the first operand to the desired address selects the type of multiply operation but does not start any operation Writing the second operand to the operand two register OP2 initiates the multiply operation
18. 0 Write mode is off 1 Write mode is on Reserved Always read as 0 Mass erase and erase These bits are used together to select the erase mode MERAS and ERASE are automatically reset when EMEX is set MERAS ERASE Erase Cycle 0 0 No erase 0 1 Erase individual segment only 1 0 Erase all main memory segments 1 1 Erase all main and information memory segments Reserved Always read as 0 Flash Memory Controller Flash Memory Registers FCTL2 Flash Memory Control Register 15 14 13 12 11 10 9 8 FWKEYx Read as 096h Must be written as 0A5h 7 NNI rw 0 FWKEYx FSSELx rw 1 Bits 15 8 Bits 7 6 Bits 5 0 rw 0 rw 0 rw 0 rw 0 rw 1 rw 0 FCTLx password Always read as 096h Must be written as OA5h or a PUC will be generated Flash controller clock source select 00 ACLK 01 10 SMCLK 11 SMCLK Flash controller clock divider These six bits select the divider for the flash controller clock The divisor value is FNx 1 For example when FNx 00h the divisor is 1 When FNx 02Fh the divisor is 64 Flash Memory Controller 5 19 Flash Memory Registers FCTL3 Flash Memory Control Register FCTL3 15 14 13 12 11 10 9 8 FWKEYx Read as 096h Must be written as 0A5h 7 6 5 4 3 2 1 0 ro ro rw 0 rw 1 r 1 rw 0 r w 0 FWKEYx Reserved EMEX LOCK WAIT ACCVIFG KEYV BUSY 5 20 Bits 15 8 Bits 7 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 rw 0
19. 13 12 11 10 9 8 rw 0 rw 0 7 6 rw 0 rw 0 rw 0 rw 0 rw 0 5 4 3 2 1 rw 0 0 ADC12 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 Modifiable only when ENC 0 CSTART Bits ADDx 15 12 SHSx Bits 11 10 SHP Bit 9 ISSH Bit 8 ADC12DIVx Bits 7 5 Conversion start address These bits select which ADC12 conversion memory register is used for a single conversion or for the first conversion in a sequence The value of CSTARTADDx is 0 to OFh corresponding to ADC12MEMO to ADC12MEM15 Sample and hold source select 00 ADC12SC bit 01 Timer A OUT1 10 Timer B OUTO 11 Timer B OUT1 Sample and hold pulse mode select This bit selects the source of the sampling signal SAMPCON to be either the output of the sampling timer or the sample input signal directly 0 SAMPCON signal is sourced from the sample input signal 1 SAMPCON signal is sourced from the sampling timer Invert signal sample and hold 0 The sample input signal is not inverted 1 The sample input signal is inverted ADC 12 clock divider 000 1 001 2 010 011 4 100 5 101 6 110 7 111 8 ADC12 17 23 ADC12 Registers ADC12 Bits ADC12 clock source select SSELx 4 3 00 ADC120SC 01 ACLK 10 MCLK 11 SMCLK CONSEQx Bits Conversion sequence mode select 2 1 00 Single channel single conversion 01 Sequence of channels 10 Repeatsingle channel 11 Repeat sequence of channels ADC12 Bit 0 ADC12 busy This bit indicates
20. 7 rw 0 5 4 3 2 1 0 0 rw 0 rw 0 rw 0 rw 0 rw rw 0 rw 0 Modifiable only when I2CEN 0 I2CWORD I2CRM I2CSSELx I2CTRX I2CSTB I2CSTP I2CSTT Bit 7 Bit 6 Bits 5 4 Bit 3 Bit 2 Bit 1 Bit 0 12C word mode Selects byte or word mode for the 12C data register 0 Byte mode 1 Word mode 12 repeat mode 0 I2CNDAT defines the number of bytes transmitted 1 Number of byte transmitted is controlled by software I2CNDAT is unused 12C clock source select When MST 1 and arbitration is lost the external SCL signal is automatically used 00 No clock 12C module is inactive 01 ACLK 10 SMCLK 11 SMCLK I2C transmit This bit selects the transmit or receive function for the 12C controller when MST 1 When MST 0 the R W bit of the address byte defines the data direction and I2CTRX reflects the direction of the SDA pin 0 Receive mode Data is received on the SDA pin 1 Transmit mode Data transmitted on the SDA pin Start byte Setting the I2CSTB bit when MST 1 initiates a start byte 0 action 1 Send START condition start byte 03h but no stop condition Stop bit This bitis used to generate STOP condition After the stop condition the I2CSTP is automatically cleared 0 action 1 Send STOP condition Start bit This bit is used to generate a START condition After the start condition the I2CSTT is automatically cleared 0 No action 1 Send
21. Figure 13 1 USAHT Block Diagram UART Mode SWRST URXEx URXEIE URXWIE FE PE OE BRK Receive Control Receive Status Receiver Buffer UXRXBUF RXERR RXWAKE Receiver Shift Register SSELO sp CHAR EV Baud Rate Generator Prescaler Divider UxBRx Modulator UxMCTL SP CHAR PEV PENA Transmit Shift Register Transmit Buffer UXTXBUF Transmit Control SWRST UTXEx TXEPT STC Lis ull Clock Phase and Polarity Refer to the device specific datasheet for SFR locations SYNC 0 LISTEN MM SYNC PENA 1 URXD UCLKS qt sro SSEL1 P Sx 1 SIMO TXWAKE UTXIFGx SYNC CKPH CKPL USART Peripheral Interface UART Mode 13 3 USART Operation UART Mode 13 2 USART Operation UART Mode In UART mode the USART transmits and receives characters at a bit rate asynchronous to another device Timing for each character is based on the selected baud rate of the USART The transmit and receive functions use the same baud rate frequency 13 2 1 USART Initialization and Reset The USART is reset by a PUC or by setting the SWRST bit After a PUC the SWRST bitis automatically set keeping the USART in a reset condition When set the SWRST bit resets the URXIEx UTXIEx URXIFGx RXWAKE TXWAKE RXERR BRK PE OE and FE bits and sets the UTXIFGx and TXEPT bits The receive and transmit enable flags URXEx and UTXEx are not altered by SWRST Clearing SWRST relea
22. The DCO temperature coefficient can be reduced by using an external resistor Rosc to source the current for the DC generator Figure 4 7 shows the typical relationship of fpco vs temperature for both the internal and external resistor options Using an external Rosc reduces the DCO temperature coefficient to approximately 0 05 C See the device specific data sheet for parameters Rosc also allows the DCO to operate at higher frequencies For example the internal resistor nominal value is approximately 200 kO allowing the DCO to operate up to approximately 5 MHz When using an external Rosc of approximately 100 kO the DCO can operate up to approximately 10 MHz The user should take care to not exceed the maximum MCLK frequency specified in the datasheet even though the DCO is capable of exceeding it Figure 4 7 DCO Frequency vs Temperature 4 8 DCO External Internal Celsius Basic Clock Module Basic Clock Module Operation 4 2 5 DCO Modulator The modulator mixes two DCO frequencies fpco and fpco 1 to produce an intermediate effective frequency between fpco and fpco 4 and spread the clock energy reducing electromagnetic interference EMI The modulator mixes fpco and fpco 1 for32 DCOCLK clock cycles andis configured with the MODx bits When MODx 0 the modulator is off The modulator mixing formula is t 32 MODx x tpco MODx x tpco 1 Because fpcois lower than the effective frequency and fpco i
23. When changing TACCRO while the timer is running and counting in the down direction the timer continues its descent until it reaches zero The new period takes affect after the counter counts down to zero When the timer is counting in the up direction and the new period is greater than or equal to the old period or greater than the current count value the timer counts up to the new period before counting down When the timer is counting in the up direction and the new period is less than the current count value the timer begins counting down However one additional count may occur before the counter begins counting down Mode The up down mode supports applications that require dead times between output signals See section Timer_A Output Unit For example to avoid overload conditions two outputs driving an H bridge must never be in a high state simultaneously In the example shown in Figure 11 9 the tgeag is tdead ttimer TACCR1 TACCR2 With tgeag Time during which both outputs need to be inactive ttimer Cycle time of the timer clock TACCRx Content of capture compare register x The TACCRx registers are not buffered They update immediately when written to Therefore any required dead time will not be maintained automatically Output Unit in Up Down Mode gt P Dead Time Output Mode 6 Toggle Set Output Mode 2 Toggle Reset EQU1 EQU1 Tairg FQU1
24. 4 4 Basic Clock Module Introduction 4 1 Basic Clock Module Introduction 4 1 Basic Clock Module Introduction 4 2 The basic clock module supports low system cost and ultralow power consumption Using three internal clock signals the user can select the best balance of performance and low power consumption The basic clock module can be configured to operate without any external components with one external resistor with one or two external crystals or with resonators under full software control The basic clock module includes two or three clock sources LFXT1CLK Low frequency high frequency oscillator that can be used either with low frequency 32 768 Hz watch crystals or standard crystals resonators or external clock sources in the 450 kHz to 8 MHz range Lj XT2CLK Optional high frequency oscillator that can be used with standard crystals resonators or external clock sources in the 450 kHz to 8 MHz range DCOCLK Internal digitally controlled oscillator DCO with RC type characteristics Three clock signals are available from the basic clock module ACLK Auxiliary clock The ACLK is the buffered LFXT1CLK clock source divided by 1 2 4 or 8 ACLK is software selectable for individual peripheral modules J MCLK Master clock MCLK is software selectable as LFXT1CLK XT2CLK if available or DCOCLK MCLK is divided by 1 2 4 or8 MCLK is used by the CPU and system
25. 7 or 8 bit data length 3 pin and 4 pin SPI operation Master or slave modes Independent transmit and receive shift registers Separate transmit and receive buffer registers Selectable UCLK polarity and phase control Programmable UCLK frequency in master mode L LE GO O O G Independent interrupt capability for receive and transmit Figure 14 1 shows the USART when configured for SPI mode 14 2 USART Peripheral Interface SPI Mode Figure 14 1 USART Block Diagram SPI Mode SWRST USPIEx URXEIE URXWI Receive Control FE PE OE BRK RXERR RXWAKE SSEL1 SSELO sp CHAR P EV Baud Rate Generator ACLK 4 SMCLK Prescaler Divider UxBRx SMCLK 4 Modulator UXMCTL SP CHAR PEV Transmit Shift Register Transmit Buffer UXTXBUF Transmit Control TXWAKE UTXIFGx TXEPT SWRST USPIEx STC PENA PENA USART Introduction SPI Mode E SYNC 1 URXIFGx LISTEN 1 URXD UCLKS 0 STE 4 lt UTXD SYNC CKPH CKPL UCLKI 4 Refer to the device specific datasheet for SFR locations Clock Phase and Polarity USART Peripheral Interface SPI Mode 14 3 USART Operation SPI Mode 14 2 USART Operation SPI Mode In SPI mode serial data is transmitted and received by multiple devices using a shared clock provided by the master An additional pin STE is provided as to enable a device to receive and transmit data and is
26. Bit 7 Bit 6 Bits 5 4 Bit 3 Bit 2 Bit 1 Bit 0 5 4 3 2 1 0 rw 0 rw 1 rw 0 rw 0 rw 0 rw 0 rw 0 Clock phase select Controls the phase of UCLK 0 Normal UCLK clocking scheme 1 UCLK is delayed by one half cycle Clock polarity select 0 The inactive level is low data is output with the rising edge of UCLK input data is latched with the falling edge of UCLK 1 The inactive level is high data is output with the falling edge of UCLK input data is latched with the rising edge of UCLK Source select These bits select the BRCLK source clock 00 External UCLK valid for slave mode only 01 valid for master mode only 10 SMCLK valid for master mode only 11 SMCLK valid for master mode only Unused Unused Slave transmit control 0 4 pin SPI mode STE enabled 1 3 pin SPI mode STE disabled Transmitter empty flag The TXEPT flag is not used in slave mode 0 Transmission active and or data waiting in UXTXBUF 1 UxTXBUF and TX shift register are empty USART Peripheral Interface SPI Mode 14 15 USART Registers SPI Mode UxRCTL USART Receive Control Register rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 FE Bit 7 Framing error flag This bit indicates a bus conflict when MM 1 and STC 0 FE is unused in slave mode 0 No conflict detected 1 A negative edge occurred on STE indicating bus conflict Undefined Bit6 Unused OE Bit 5 Overrun error flag This bit is set when a character is transferr
27. FCTLx password Always read as 096h Must be written as 0A5h or a PUC will be generated Reserved Always read as 0 Emergency exit 0 No emergency exit 1 Emergency exit Lock This bit unlocks the flash memory for writing or erasing The LOCK bit can be set anytime during a byte word write or erase operation and the operation will complete normally In the block write mode if the LOCK bit is set while BLKWRT WAIT 1 then BLKWRT and WAIT are reset and the mode ends normally 0 Unlocked 1 Locked Wait Indicates the flash memory is being written to 0 The flash memory is not ready for the next byte word write 1 The flash memory is ready for the next byte word write Access violation interrupt flag 0 No interrupt pending 1 Interrupt pending Flash security key violation This bit indicates an incorrect FCTLx password was written to any flash control register and generates a PUC when set KEYV must be reset with software 0 FCTLx password was written correctly 1 FCTLx password was written incorrectly Busy This bit indicates the status of the flash timing generator 0 Not Busy 1 Busy Flash Memory Controller Flash Memory Registers IE1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 ACCVIE Bits 7 6 4 0 Bit 5 rw 0 These bits may be used by other modules See device specific datasheet Flash memory access violation interrupt enable This bit enables the ACCVIFG interrupt Because other bits in IE1 may be used f
28. Mode Bits Example Example Subtract source from destination Subtract source from destination SUB src dst or SUB W src dst SUB B src dst dst NOT src 1 gt dst or dst src dst The source operand is subtracted from the destination operand by adding the source operand s 1s complement and the constant 1 The source operand is not affected The previous contents of the destination are lost N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Setif there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Setif an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected See example at the SBC instruction See example at the SBC B instruction _ Note Borrow Is Treated as a NOT The borrow is treated as a NOT carry Borrow Carry bit Yes 0 No 1 LLLLL OOCEA 3 66 RISC 16 Bit CPU SUBC W SBB W SUBC B SBB B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Subtract source and borrow NOT carry from destination Subtract source and borrow NOT carry from destination SUBC src dst or SUBC W src dst or
29. O OERIAXAXAEAm G RISC 16 Bit CPU 3 9 Addressing Modes 3 3 1 Register Mode The register mode is described in Table 3 4 Table 3 4 Register Mode Description Assembler Code Content of ROM MOV R10 R11 MOV R10 R11 Length One or two words Operation Move the content of R10 to R11 R10 is not affected Comment Valid for source and destination Example MOV R10 R11 Before After Note Data in Registers The data in the register can be accessed using word or byte instructions If byte instructions are used the high byte is always 0 in the result The status bits are handled according to the result of the byte instruction 3 10 RISC 16 Bit CPU Addressing Modes 3 3 2 Indexed Mode The indexed mode is described in Table 3 5 Table 3 5 Indexed Mode Description Content of ROM MOV X R5 Y R6 2 6 Assembler Code MOV 2 R5 6 R6 X Y Length Two or three words Operation Move the contents of the source address contents of R5 2 to the destination address contents of R6 6 The source and destination registers R5 and R6 are not affected In indexed mode the program counter is incremented automatically so that program execution continues with the next instruction Comment Valid for source and destination Example MOV 2 R5 6 R6 Before After Address Register Address Register Space Space Oxxxxh PC OFF16h 00006h R5 01080h OFF16h 00006h R5 01080h OFF14h 0000
30. The Timer A Output Unit 2 The polarity of the SHI signal source can be inverted with the ISSH bit The SHTx bits select the sample period tsample to be 4 8 16 or 64 ADC10CLK cycles The sampling timer sets SAMPCON high for the selected sample period after synchronization with ADC10CLK Total sampling time is tsample plus tsync The high to low SAMPCON transition starts the analog to digital conversion which requires 13 ADC10CLK cycles as shown in Figure 18 3 Figure 18 3 Sample Timing Start Stop Start Conversion Sampling Sampling Conversion Complete SHI SAMPCON 13 x ADC10CLKs lt lt sample 54 Iconvert 9 4 tsync ADC10 18 7 ADC10 Operation Sample Timing Considerations When SAMPCON 0 all Ax inputs are high impedance When SAMPCON 1 the selected Ax input can be modeled as an RC low pass filter during the sampling time tsampje as shown below in Figure 18 4 An internal MUX on input resistance Rj max 2 in series with capacitor Cj max 20 pF is seen by the source The capacitor C voltage Vc must be charged to within 1 2 LSB of the source voltage Vg for an accurate 10 bit conversion Figure 18 4 Analog Input Equivalent Circuit 18 8 MSP430 V Input voltage at pin Ax Rs V RI Vg External source voltage V Rs External source resistance S C Internal MUX on input resistance C Input capacitance Capacitance charging v
31. 0 rw 0 rw 0 rw 0 5 rw 0 rw rw rw rw Modifiable only when DAC12ENC 0 t Not used for DAC12 1 on MSP430x15x and MSP430x16x devices Reserved DAC12 SREFx DAC12 RES DAC12 LSELx DAC12 CALON DAC12IR Bit 15 Bits 14 13 Bit 12 Bits 11 10 Bit 9 Bit 8 Reserved DAC12 select reference voltage 00 VREF 01 VREF 10 Vener 11 Vengr DAC12 resolution select 0 12 bit resolution 1 8 bit resolution DAC12 load select Selects the load trigger for the DAC12 latch DAC12ENC must be set for the DAC to update except when DAC12LSELx 0 00 DAC12latch loads when DAC12 xDAT written DAC12ENC is ignored 01 DAC12 latch loads when DAC12 xDAT written or when grouped when all DAC12 xDAT registers in the group have been written 10 Rising edge of Timer AS3 OUT1 TA1 11 Rising edge of Timer B7 OUT2 TB2 DAC12 calibration on This bit initiates the DAC12 offset calibration sequence and is automatically reset when the calibration completes 0 Calibration is not active 1 Initiate calibration calibration in progress DAC12 input range This bit sets the reference input and voltage output range 0 DAC12 full scale output 3x reference voltage 1 DAC12 full scale output 1x reference voltage DAC12 19 11 DAC12 Registers DAC12 AMPx DAC12DF DAC12IE DAC12IFG DAC12 ENC DAC12 GRP 19 12 Bits 7 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DAC12 DAC12 ampl
32. 5 Continuous Mode Flag Setting Wah JA GE NC Vf PR Timer Set TBIFG Timer B 12 7 Timer B Operation Use of the Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies Each time an interval is completed an interrupt is generated The next time interval is added to the TBCLx latch in the interrupt service routine Figure 12 6 shows two separate time intervals ty and t4 being added to the capture compare registers The time interval is controlled by hardware not software without impact from interrupt latency Up to three Timer or 7 Timer B7 independent time intervals or output frequencies can be generated using capture compare registers Figure 12 6 Continuous Mode Time Intervals 12 8 TBR max TBCLOa Oh EQUO Interrupt EQUI Interrupt Timer_B TBCL1b TBCL1c TBCLOb TBOLOc TBCL1a TBCLid j to b ty ty ty Time intervals can be produced with other modes as well where TBCLO is used as the period register Their handling is more complex since the sum of the old TBCLx data and the new period can be higher than the TBCLO value When the sum of the previous TBCLx value plus ty is greater than the TBCLO data the old TBCLO value must be subtracted to obtain the correct time interval Up Down Mode Timer B Operation The up down mode is used if the timer period must be different fro
33. ADD OV AND BR CMP OV OV OV OV OV OV Example R5 R8 R9 R5 3 R6 R8 EDE R5 amp EDE R4 R5 R8 R5 8 R6 R5 EDE R5 amp EDE R5 R6 R9 E 0 SP E amp TONI D D EDE TONI D D E R8 E O0 SP E amp TONI RQ m m m m EDE TONI D D RISC 16 Bit CPU 3 73 Instruction Set 3 4 5 Instruction Set Description The instruction map is shown in Figure 3 20 and the complete instruction set is summarized in Table 3 17 Figure 3 20 Core Instruction Map 000 040 080 100 140 180 1CO 200 240 280 2C0 300 340 380 LLLA eee LS c r i uz RRC Rro _ mma nmae revi f S T S S S Pe a imam AD S po cda cue uo sp 3 74 RISC 16 Bit CPU Table 3 17 MSP430 Instruction Set Mnemonic ADC B ADD B ADDC B AND B BIC B BIS B BIT B BR CALL CLR B CLRC CLRN CLRZ CMP B DADC B DADD B DEC B DECD B DINT EINT INC B INCD B INV B JC JHS JEQ JZ JGE JL JMP JN JNC JLO JNE JNZ MOV NOP P
34. At least one instruction is needed between loading the second operand and accessing one of the result registers Access mul OV OV OV OP OV OV 7 2 5 Using Interrupts 7 6 RESLO R5 amp amp amp OPER2 amp OP2 QR5 amp XXX 5 amp ltiplier resul ts with indirect addressing RESLO address in R5 for indirect Load Load Need 1 2 st operand nd operand Move Move O R R ne cycl ESLO ESHI If an interrupt occurs after writing OP1 but before writing OP2 and the multiplier is used in servicing that interrupt the original multiplier mode selection is lost and the results are unpredictable To avoid this disable interrupts before using the hardware multiplier or do not use the multiplier in interrupt service routines Disable interrupts before using the hardware multiplier DINT OP OV OV EINT Hardware Multiplier xxh amp MPY xxh amp OP2 Disable interrupts Required for DINT Load lst operand Load 2nd operand Interrupts may b nable befor Process results Hardware Multiplier Registers 7 3 Hardware Multiplier Registers The hardware multiplier registers are listed in Table 7 4 Table 7 4 Hardware Multiplier Registers Register Short Form Register Type Address Initial State Operand one multiply MPY Read write 0130h Unchanged Operand one signed multiply MPYS Read
35. BCSCTL2 Basic Clock System Control Register 2 SELMx DIVMx SELS DIVSx DCOR 4 16 Bits Select MCLK These bits select the MCLK source 7 6 00 01 10 11 DCOCLK DCOCLK XT2CLK when XT2 present LFXT1CLK when XT2 not present LFXT1CLK BitS Divider for MCLK 5 4 00 01 10 11 1 2 4 8 Bit 3 Select SMCLK This bit selects the SMCLK source 0 1 DCOCLK XT2CLK when XT2 present LFXT1CLK when XT2 not present BitS Divider for SMCLK 2 1 00 01 10 11 Bit 0 DCO 0 1 Basic Clock Module 1 2 4 8 resistor select Internal resistor External resistor Basic Clock Module Registers IE1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 OFIE Bits 7 2 Bit 1 Bits 0 rw 0 These bits may be used by other modules See device specific datasheet Oscillator fault interrupt enable This bit enables the OFIFG interrupt Because other bits in IE1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled This bit may be used by other modules See device specific datasheet IFG1 Interrupt Flag Register 1 7 6 5 4 3 2 1 0 OFIFG Bits Bit 1 Bits 0 rw 0 These bits may be used by other modules See device specific datasheet Oscillator fault interrupt flag Because other bits in IFG1 may be used for other modules it is recommended
36. I C Mode I2CDR Loaded I2CDR Written Send Data Low Byte to Master I2CDR Empty 8x SCL No Ack Send Data Low Byte to Master Ack 8x SCL No Ack Stop detected Yes ARDYIFG is set I2CBB is cleared Ack No Re start detected NACKIFG is set 15 13 12C Module Operation Figure 15 13 Slave Receiver I2ZCWORD 1 4 x l2CPSC 8x SCL 1x SCL Start detected Yes STTIFG is Set CD Receive Slave Address bits 6 0 with R W 0 Match s Matched 2 Acknowledge XA 1 8x sci 0 bit address Receive Slave Address bits 9 7 15 14 NO XA 0 Match Matched X 7 bit address 2 Acknowledge OAIFG set if Yes USART Peripheral Interface 12C Mode Re start detected No Receive Data Low Byte from Master 1x SCL Yes 8x SCL Receive Data High Byte from Master 1x SCL Send Acknowledge Yes 8x SCL Receive Data High Byte from Master Stop State Yes I2CSTP 1 7 locpsc ARDYIFG is Set D 12C Module Operation 15 2 5 The I2C Data Register I2CDR The I2CDR register can be accessed as an 8 bit or 16 bit register selected by the I2CWORD bit The I2CDR register functions as described in Table 15 2 Table 15 2 I2CDHR Register Function Transmit Underflow Receive Overrun I2
37. If URXWIE remains set only address characters address bit 1 willbe received The URXWIE bit is not modified by the USART hardware automatically Figure 13 4 Address Bit Multiprocessor Format aaa Blocks of Frames m Idle Periods of No Significance UTXDx URXDx Expanded UTXDx URXDx First Frame Within Block AD Frame Bit Is 0 Is an Address AD Frame Bit Is 1 for Data Within Block Idle Time Is of No Significance For address transmission in address bit multiprocessor mode the address bit of acharacter can be controlled by writing to the TXWAKE bit The value of the TXWAKE bit is loaded into the address bit of the character transferred from UxTXBUF to the transmit shift register automatically clearing the TXWAKE bit TXWAKE must not be cleared by software It is cleared by USART hardware after it is transferred to WUT or by setting SWRST USART Peripheral Interface UART Mode 13 7 USART Operation UART Mode Automatic Error Detection Glitch suppression prevents the USART from being accidentally started Any low level on URXDx shorter than the deglitch time t approximately 300 ns will be ignored See the device specific datasheet for parameters When a low period on URXDx exceeds t a majority vote is taken for the start bit If the majority vote fails to detect a valid start bit the USART halts character reception and waits for the next low period on URXDx The majority vote is also used for each bit in a char
38. RISC 16 Bit CPU 3 19 Instruction Set 3 4 3 Jumps Figure 3 11 shows the conditional jump instruction format Figure 3 11 Jump Instruction Format is id 13 12 1 10 9 8 7 6 5 4 3 2 1 0 Table 3 13 lists and describes the jump instructions Table 3 13 Jump Instructions Mnemonic S Reg D Reg Operation JEQ IZ Label Jump to label if zero bit is set JNE JNZ Label Jump to label if zero bit is reset JC Label Jump to label if carry bit is set JNC Label Jump to label if carry bit is reset JN Label Jump to label if negative bit is set JGE Label Jump to label if XOR V 0 Ji Label Jump to label if N XOR V 1 JMP Label Jump to label unconditionally Conditional jumps support program branching relative to the PC and do not affect the status bits The possible jump range is from 511 to 4512 words relative to the PC value at the jump instruction The 10 bit program counter offset is treated as a signed 10 bit value that is doubled and added to the program counter PCnew 2 PCoffset x 2 3 20 RISC 16 Bit CPU ADC W ADC B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Instruction Set Add carry to destination Add carry to destination ADC dst or ADC W dst ADC B dst dst C dst ADDC 0 dst ADDC B 0 dst The carry bit C is added to the destination operand The previous contents of the destination are lost N Set if re
39. TAIE Bit 1 Timer A interrupt enable This bit enables the TAIFG interrupt request 0 Interrupt disabled 1 Interrupt enabled TAIFG Bit 0 Timer_A interrupt flag 0 No interrupt pending 1 Interrupt pending 11 20 Timer_A Timer A Registers TAR Timer A Register 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 TARx Bits Timer A register The TAR register is the count of Timer A 15 0 Timer A 11 21 Timer A Registers TACCTLx Capture Compare Control Register 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 r 0 rw 0 7 6 4 3 2 1 0 0 r rw 0 rw 0 0 rw 0 rw 0 CMx Bit 15 14 CCISx Bit 13 12 SCS Bit 11 SCCI Bit 10 Unused Bit 9 CAP Bit 8 OUTMODx Bits 7 5 11 22 Timer A 5 rw 0 rw Capture mode 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both rising and falling edges Capture compare input select These bits select the TACCRx input signal See the device specific datasheet for specific signal connections 00 CCIxA 01 CCIxB 10 GND 11 Synchronize capture source This bit is used synchronize the capture input signal with the timer clock 0 Asynchronous capture 1 Synchronous capture Synchronized capture compare input The selected CCI input signal is latched with the EQUx signal and can be read via this bit
40. TBCCRx data old TBCCRx data Second the load event must occur Table 12 3 Compare Latch Operating Modes TBCLGRPx Grouping Update Control 00 None Individual 01 TBCL1 TBCL2 TBCCR1 TBCL3 TBCL4 TBCCR3 TBCL5 TBCL6 TBCCR5 10 TBCL1 TBCL2 TBCL3 TBCCR1 TBCL4 TBCL5 TBCL6 TBCCR4 11 TBCLO TBCL1 TBCL2 TBCCR1 TBCL3 TBCL4 TBCL5 TBCL6 Timer_B 12 13 Timer B Operation 12 2 5 Output Unit Each capture compare block contains an output unit The output unit is used to generate output signals such as PWM signals Each output unit has eight operating modes that generate signals based on the EQUO and EQUx signals The TBoutH pin function can be used to put all Timer B outputs into a high impedance state When the TBoutH pin function is selected for the pin and when the pin is pulled high all Timer B outputs are in a high impedance state Output Modes The output modes are defined by the OUTMODx bits and are described in Table 12 4 The OUTx signal is changed with the rising edge of the timer clock for all modes except mode 0 Output modes 2 3 6 and 7 are not useful for output unit 0 because EQUx EQUO Table 12 4 Output Modes OUTMODx 000 001 010 011 100 101 110 111 12 14 Timer B Mode Output Set Toggle Reset Set Reset Toggle Reset Toggle Set Reset Set Description The output signal OUTx is defined by the OUTx bit The OUTx signal updates immediately when OUTx is updated
41. Table 14 1 USAHTO Control and Status Registers Register Short Form Register Type Address Initial State USART control register UOCTL Read write 070h 001h after PUC Transmit control register UOTCTL Read write 071h 001h after PUC Receive control register UORCTL Read write 072h 000h after PUC Modulation control register UOMCTL Read write 073h Unchanged Baud rate control register 0 UOBRO Read write 074h Unchanged Baud rate control register 1 UOBR1 Read write 075h Unchanged Receive buffer register UORXBUF Read 076h Unchanged Transmit buffer register UOTXBUF Read write 077h Unchanged SFR module enable register 1t ME1 Read write 004h 000h after PUC SFR interrupt enable register 1t IE1 Read write 000h 000h after PUC SFR interrupt flag register 1t IFG1 Read write 002h 082h after PUC t Does not apply to MSP430x12xx devices Refer to the register definitions for registers and bit positions for these devices Table 14 2 USAHT1 Control and Status Registers Register Short Form Register Type Address Initial State USART control register U1CTL Read write 078h 001h after PUC Transmit control register U1TCTL Read write 079h 001h after PUC Receive control register U1RCTL Read write 07Ah 000h after PUC Modulation control register U1MCTL Read write 07Bh Unchanged Baud rate control register 0 U1BRO Read write 07Ch Unchanged Baud rate control register 1 U1BR1 Read write 07Dh Unchanged Receive buffer register U1RXBUF Read 07Eh Unchanged Transmit buffer register U
42. The ADC10CLK is used both as the conversion clock and to generate the sampling period The ADC10 source clock is selected using the ADC10SSELx bits and can be divided from 1 8 using the ADC10DIVx bits Possible ADC10CLK sources are SMCLK MCLK ACLK and an internal oscillator ADC10OSC The ADC10OSC generated internally is in the 5 MHz range but varies with individual devices supply voltage and temperature See the device specific data sheet for the ADC10OSC specification The user must ensure that the clock chosen for ADC10CLK remains active until the end of a conversion If the clock is removed during a conversion the operation will not complete and any result will be invalid ADC10 Operation 18 2 2 ADC10 Inputs and Multiplexer The eight external and four internal analog signals are selected as the channel for conversion by the analog input multiplexer The input multiplexer is a break before make type to reduce input to input noise injection resulting from channel switching as shown in Figure 18 2 The input multiplexer is also a T switch to minimize the coupling between channels Channels that are not selected are isolated from the A D and the intermediate node is connected to analog ground AVss so that the stray capacitance is grounded to help eliminate crosstalk The ADC10 uses the charge redistribution method When the inputs are internally switched the switching action may cause transients on the input signal These transi
43. This fetch is the JMP PC instruction Any 0 ACCVIFG 1 LOCK 1 Read 1 ACCVIFG 0 OSFFFh is the value read Block write Write 1 ACCVIFG 0 Write is ignored Instruction 1 ACCVIFG 1 LOCK 1 fetch All interrupt sources should be disabled before initiating any flash operation If an enabled interrupt were to occur during a flash operation the CPU would fetch OSFFFh as the address of the interrupt service routine The CPU would then execute the JMP PC instruction while BUSY 1 When the flash operation finished the CPU would begin executing code at address O3FFFh not the correct address for interrupt service routine 5 14 Flash Memory Controller Flash Memory Operation 5 3 5 Stopping a Write or Erase Cycle Any write or erase operation can be stopped before its normal completion by setting the emergency exit bit EMEX Setting the EMEX bit stops the active operation immediately and stops the flash controller All flash operations cease the flash returns to read mode and all bits in the FCTL1 register are reset The result of the intended operation is unpredictable 5 3 6 Configuring and Accessing the Flash Memory Controller The FCTLx registers are 16 bit password protected read write registers Any read or write access must use word instructions and write accesses must include the write password OA5h in the upper byte Any write to any FCTLx register with any value other than OA5h in the upper byte is a security key violation
44. Unused Read only Always read as 0 Capture mode 0 Compare mode 1 Capture mode Output mode Modes 2 3 6 and 7 are not useful for TACCRO because EQUx EQUO 000 OUT bit value 001 Set 010 Toggle reset 011 Set reset 100 Toggle 101 Reset 110 Toggle set 111 Reset set CCIE Bit 4 CCI Bit 3 OUT Bit 2 COV Bit 1 CCIFG Bit 0 Timer A Registers Capture compare interrupt enable This bit enables the interrupt request of the corresponding CCIFG flag 0 Interrupt disabled 1 Interrupt enabled Capture compare input The selected input signal can be read by this bit Output This bit indicates the state of the output For output mode O this bit directly controls the state of the output 0 Output low 1 Output high Capture overflow This bit indicates a capture overflow occurred COV must be reset with software 0 No capture overflow occurred 1 Capture overflow occurred Capture compare interrupt flag 0 No interrupt pending 1 Interrupt pending TAIV Timer A Interrupt Vector Register ro 7 15 14 13 12 11 10 9 8 ro ro ro ro ro ro ro 5 4 3 2 1 0 ro ro TAIVx Bits 15 0 ro ro r 0 r 0 r 0 ro Timer A Interrupt Vector value Interrupt TAIV Contents Interrupt Source Interrupt Flag Priority 00h No interrupt pending 02h Capture compare 1 TACCR1 CCIFG Highest 04h Capture compare 2 TACCR2 CCIFG 06h Reserved E 08h Reserved E 0Ah Timer overflow TAIFG OCh Reserved OEh Reserved B Lo
45. sets the KEYV flag and triggers a PUC system reset Any read of any FCTLx registers reads 096h in the upper byte Any write to FCTL1 during an erase or byte word write operation is an access violation and sets ACCVIFG Writing to FCTL1 is allowed in block write mode when WAIT 1 but writing to FCTL1 in block write mode when WAIT 0 is an access violation and sets ACCVIFG Any write to FCTL2 when the BUSY 1 is an access violation Any FCTLx register may be read when BUSY 1 A read will not cause an access violation 5 3 7 Flash Memory Controller Interrupts The flash controller has two interrupt sources KEYV and ACCVIFG ACCVIFG is set when an access violation occurs When the ACCVIE bit is re enabled after a flash write or erase a set ACCVIFG flag will generate an interrupt request ACCVIFG sources the NMI interrupt vector so it is not necessary for GIE to be set for ACCVIFG to request an interrupt ACCVIFG may also be checked by software to determine if an access violation occurred ACCVIFG must be reset by software The key violation flag KEYV is set when any of the flash control registers are written with an incorrect password When this occurs a PUC is generated immediately resetting the device 5 3 8 Programming Flash Memory Devices There are three options for programming an MSP430 flash device All options support in system programming Program via JTAG _j Program via the Bootstrap Loader Program via a custom
46. transfer counter is initially equal to n The internal pointer and counter are not visible to software The DTC transfers the word value of ADC10MEM to the address pointer ADC10SA After each DTC transfer the internal address pointer is incremented by two and the internal transfer counter is decremented by one The DTC transfers continue with each loading of ADC10MEM until the internal transfer counter becomes equal to zero No additional DTC transfers will occur until a write to ADC10SA When using the DTC in the one block mode the ADC1OIFG flag is set only after a complete block has been transferred Figure 18 10 shows a state diagram of the one block mode ADC10 Operation Figure 18 10 State Diagram for Data Transfer Control in One Block Transfer Mode n 0 ADC10DTC1 n 0 Wait for write to ADC10SA Initialize Prepare Start Address in ADC10SA DTC 2 ll i Write to ADC10SA n is latched in counter x Write to ADC10SA or n 0 Wait until ADC10MEM is written Write to ADC10MEM completed Write to ADC10SA Synchronize with MCLK DTC operation Write to ADC10SA 1 x MCLK cycle Transfer data to Address AD AD AD 2 ADC10TB 20 and x 0 ADC10CT 1 ADC10TB 0 ADC10CT 0 ADC10 18 17 ADC10 Operation Two Block Transfer Mode The two block mode is selected if the ADC10TB bit is set The value n in ADC10DTC1 defines the number of tra
47. 0 ENC must be set to 1 before any conversion can take place Conversion Clock Selection 174 ADC12 The ADC12CLK is used both as the conversion clock and to generate the sampling period when the pulse sampling mode is selected The ADC12 source clock is selected using the ADC12SSELx bits and can be divided from 1 8 using the ADC12DIVx bits Possible ADC12CLK sources are SMCLK MCLK ACLK and an internal oscillator ADC12O0SC The ADC12OSO generated internally is in the 5 MHz range but varies with individual devices supply voltage and temperature See the device specific data sheet for the ADC12OSC specification The user must ensure that the clock chosen for ADC12CLK remains active until the end of a conversion If the clock is removed during a conversion the operation will not complete and any result will be invalid ADC12 Operation 17 2 2 ADC12 Inputs and Multiplexer The eight external and four internal analog signals are selected as the channel for conversion by the analog input multiplexer The input multiplexer is a break before make type to reduce input to input noise injection resulting from channel switching as shown in Figure 17 2 The input multiplexer is also a T switch to minimize the coupling between channels Channels that are not selected are isolated from the A D and the intermediate node is connected to analog ground AVss so that the stray capacitance is grounded to help eliminate crosstalk The ADC12 uses
48. 0 Module not enabled 1 Module enabled USART1 receive enable This bit enables the receiver for USART1 0 Module not enabled 1 Module enabled These bits may be used by other modules See device specific datasheet USARTO transmit enable This bit enables the transmitter for USARTO 0 Module not enabled 1 Module enabled USARTO receive enable This bit enables the receiver for USARTO 0 Module not enabled 1 Module enabled USART Peripheral Interface UART Mode 13 27 USART Registers UART Mode IE1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 rw 0 rw 0 UTXIEOT Bit 7 USARTO transmit interrupt enable This bit enables the UTXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled URXIEOT Bit 6 USARTO receive interrupt enable This bit enables the URXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled Bits These bits may be used by other modules See device specific datasheet 5 0 T Does not apply to MSP430x12xx devices See IE2 for the MSP430x12xx USARTO interrupt enable bits IE2 Interrupt Enable Register 2 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 Bits These bits may be used by other modules See device specific datasheet 7 6 UTXIE1 Bit 5 USART1 transmit interrupt enable This bit enables the UTXIFG1 interrupt 0 Interrupt not enabled 1 Interrupt enabled URXIE1 Bit 4 USART1 receive interrupt enable This bit enables the URXIFG1 interrupt 0 Interrupt not enabled 1 Interrupt enabled Bits These bits may be used
49. 0 No interrupt pending 1 Interrupt pending USARTO receive interrupt flag URXIFGO is set when UORXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules See device specific datasheet t Does not apply to MSP430x12xx devices See IFG2 for the MSP430x12xx USARTO interrupt flag bits IFG2 Interrupt Flag Register 2 7 Bits 7 6 UTXIFG1 Bit 5 URXIFG1 Bit 4 Bits 3 2 UTXIFGO Bit 1 URXIFGO Bito MSP430x12xx devices only 6 5 4 3 2 1 0 1 1 rw 0 rw rw 0 rw These bits may be used by other modules See device specific datasheet USART1 transmit interrupt flag UTXIFG1 is set when U1TXBUF is empty 0 No interrupt pending 1 Interrupt pending USART1 receive interrupt flag URXIFG1 is set when U1 RXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules See device specific datasheet USARTO transmit interrupt flag UTXIFGO is set when UOTXBUF is empty 0 No interrupt pending 1 Interrupt pending USARTO receive interrupt flag URXIFGO is set when UORXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending USART Peripheral Interface SPI Mode 14 21 14 22 USART Peripheral Interface SPI Mode Chapter 15 USART Peripheral Interface I2C Mode The universal synchronous asynchronous receive transmit USART peripheral interface supports
50. 1 gt Bit Period gt m corresponding modulation bit R Remainder from N 2 division USART Peripheral Interface UART Mode 13 11 USART Operation UART Mode Baud Rate Bit Timing The first stage of the baud rate generator is the 16 bit counter and comparator Atthe beginning of each bit transmitted or received the counter is loaded with INT N 2 where N is the value stored in the combination of UXBRO and UxBR1 The counter reloads INT N 2 for each bit period half cycle giving a total bit period of N BRCLKs For a given BRCLK clock source the baud rate used determines the required division factor N N BRCLK baud rate The division factor N is often a non integer value of which the integer portion can be realized by the prescaler divider The second stage of the baud rate generator the modulator is used to meet the fractional part as closely as possible The factor N is then defined as n 1 N UxBR 1 5 m n Where N Target division factor UxBR 16 bit representation of registers UxBRO and UxBR1 Bit position in the frame n Total number of bits in the frame Data of each corresponding modulation bit 1 or 0 Baud rate BRCLK _ BRCLK UxBR 3S m i 0 The BITCLK can be adjusted from bit to bit with the modulator to meet timing requirements when a non integer divisor is needed Timing of each bit is expanded by one BRCLK clock cycle if the modulator bit mj is set Each time a bit is receiv
51. 1 re enable and watchdog 514 kHz lt SMCLK lt 952 kHz Assumes ACCVIE NMIIE OFIE OV WDTPW WDTHOLD amp WDTCTL DINT L1 BIT BUSY amp FCTL3 JNZ L1 OV FWKEY FSSEL1 FNO amp FCTL2 OV FWKEY amp FCTL3 OV FWKEY ERASE amp FCTL1 CLR amp L2 BUSY amp FCTL3 JNZ L2 OV FWKEY LOCK amp FCTL3 EINT 0 Disable WDT Disable interrupts Test BUSY Loop while busy SMCLK 2 Clear LOCK Enable erase Dummy write erase S1 Test BUSY Loop while busy Done set LOCK Re enable WDT Enable interrupts Flash Memory Controller 5 7 Flash Memory Operation 5 3 3 Writing Flash Memory The write modes selected by the WRT and BLKWRT bits are listed in Table 5 1 Table 5 2 Write Modes Byte Word Write BLKWRT WRT Write Mode 0 1 Byte word write 1 1 Block write Both write modes use a sequence of individual write instructions but using the block write mode is approximately twice as fast as byte word mode because the voltage generator remains on for the complete block write Any instruction that modifies a destination can be used to modify a flash location in either byte word write mode or block write mode The BUSY bit is set while a write operation is active and cleared when the operation completes If the write operation is initiated from RAM the CPU must not access flash while BUSY 1 Otherwise an access viol
52. 1100 1024 1101 1024 1110 1024 1111 1024 ADC12 17 21 ADC12 Registers MSC REF2 5V REFON ADC120N Bit 7 Bit 6 Bit 5 Bit 4 ADC120VIE Bit ADC12 TOVIE ENC ADC12SC 17 22 Bit 2 Bit 1 Bit 0 ADC12 Multiple sample and conversion Valid only for sequence or repeated modes 0 The sampling timer requires a rising edge of the SHI signal to trigger each sample and conversion 1 The first rising edge of the SHI signal triggers the sampling timer but further sample and conversions are performed automatically as soon as the prior conversion is completed Reference generator voltage REFON must also be set 0 1 5 V 1 2 5 V Reference generator on 0 Reference off 1 Reference on ADC12 on 0 ADC 12 off 1 ADC12 on ADC12MEMXx overflow interrupt enable The GIE bit must also be set to enable the interrupt 0 Overflow interrupt disabled 1 Overflow interrupt enabled ADC12 conversion time overflow interrupt enable The GIE bit must also be set to enable the interrupt 0 Conversion time overflow interrupt disabled 1 Conversion time overflow interrupt enabled Enable conversion 0 ADC12 disabled 1 ADC12 enabled Start conversion Software controlled sample and conversion start ADC12SC and ENC may be set together with one instruction ADC12SC is reset automatically 0 No sample and conversion start 1 Start sample and conversion ADC12 Registers ADC12CTL1 ADC12 Control Register 1 15 14
53. 18 15 help avoid this In addition to grounding ripple and noise spikes on the power supply lines due to digital switching or switching power supplies can corrupt the conversion result A noise free design is important to achieve high accuracy Figure 18 16 ADC10 Grounding and Noise Considerations 18 22 ADC10 gt Power Supply L Decoupling a can MSP430F12x2 MSP430F11x2 Ve REF External Reference VREF ADC10 Operation 18 2 9 ADC10 Interrupts One interrupt and one interrupt vector are associated with the ADC10 as shown in Figure 18 17 When the DTC is not used ADC10DTC1 0 ADC10IFG is set when conversion results are loaded into ADC10MEM When DTC is used ADC10DTC1 gt 0 ADC1OIFG is set when a block transfer completes and the internal transfer counter n 0 If both the ADC10IE and the GIE bits are set then the ADC10IFG flag generates an interrupt request The ADC10IFG flag is automatically reset when the interrupt request is serviced or may be reset by software Figure 18 17 ADC10 Interrupt System Set ADC10IFG 20 ADC10IE IRQ Interrupt Service Requested ADC10CLK IRACC Interrupt Request Accepted ADC10 18 23 ADC10 Registers 18 3 ADC10 Registers The ADC10 registers are listed in Table 18 3 Table 18 3 ADC10 Registers Register Short Form Register Type Address Initial State ADC10 Input enable register ADC10AE Read write 04Ah Reset with
54. 2 s compliment data for the DAC When using straight binary data format the formula for the output voltage is given in Table 19 1 Table 19 1 DAC12 Full Scale Range Vref Vapgp or VREF Resolution DAC12RES DAC12IR Output Voltage Formula 12 bit 0 0 DAC12_xDAT 12 bit 0 1 DAC12_xDAT Vout Vref x 4096 i 1 zen Vout Vref x 3 x DACIA XDAT 256 8 bit 1 1 DAC12_xDAT Vout Vref x 956 In 8 bit mode the maximum useable value for DAC12 xDAT is OFFh and in 12 bit mode the maximum useable value for DAC12 xDAT is OFFFh Values greater than these may be written to the register but all leading bits are ignored DAC12 Port Selection The DAC12 outputs are multiplexed with the port P6 pins and ADC12 analog inputs When DAC12AMPx gt 0 the DAC12 function is automatically selected for the pin regardless of the state of the associated P6SELx and P6DIRx bits 19 4 DAC12 DAC12 Operation 19 2 2 DAC12 Reference The reference for the DAC12 is configured to use either of two external reference voltages or the internal 1 5 V 2 5 V reference from the ADC12 module with the DAC12SREFx bits When DAC12SREFx 0 1 the VREF signal is used as the reference and when DAC12SREFx 2 3 the VeREF signal is used as the reference To use the ADC12 internal reference it must be enabled and configured via the applicable ADC12 control bits see the ADC 12 chapter Once the ADC12 reference is configured the reference voltage appears
55. 3 lt Cumulative Programming Time lt 3ms Current Consumption is Increased r Generate Programming Operation Active Remove ramming Voltage Pa ter Programming Voltage id Flash Memory Controller 5 11 Flash Memory Operation Block Write Flow and Example A block write flow is shown in Figure 5 8 and the following example Figure 5 12 Block Write Flow Disable all interrupts and watchdog yes i Setup flash controller Set BLKWRT WRT 1 Write byte or word ttt yes Block Border H Set BLKWRT 0 yes Another Block H Set WRT 0 LOCK 1 re enable interrupts and WDT 5 12 Flash Memory Controller L1 L2 L3 L4 Write one bloc k starting at OFO000h Flash Memory Operation Must be executed from RAM Assumes Flash is already erased 514 kHz SMCLK 952 kHz Assumes ACCVIE NMIIE OFIE MOV MOV MOV DINT BIT JNZ MOV MOV MOV MOV BIT 32 OFO 11 R5 00h R6 WDTPW WDTHOLD amp WDTCTL BUSY amp FCTL3 FWK FWKI EY FSSEL1 FNO amp FCTL2 EY amp FCTL3 FWKI L3 R6 R5 L2 FWK EY BLKWRTI WRT amp 1 Write _Value 0 R6 WAIT amp FCTL3 EY amp FCTL1 L4 FWKI BUSY amp FCTL3 EY LOCK amp FCTL3 Use as write counter Write pointer Disable WDT Disable interrupts Test BUSY Loop w
56. 3 Address Space 1 4 Address Space The MSP430 von Neumann architecture has one address space shared with special function registers SFRs peripherals RAM and Flash ROM memory as shown in Figure 1 2 See the device specific data sheets for specific memory maps Code access are always performed on even addresses Data can be accessed as bytes or words The addressable memory space is 64 KB with future expansion planned Figure 1 2 Memory Map OFFFFh OFFEOh OFFDFh 0200h O1FFh 0100h OFFh 010h OFh Oh 1 4 1 Flash ROM 1 4 22 RAM 1 4 Introduction Access Interrupt Vector Table Word Byte Flash ROM Word Byte Word Byte 16 Bit Peripheral Modules Word 8 Bit Peripheral Modules Byte Special Function Registers Byte The start address of Flash ROM depends on the amount of Flash ROM present and varies by device The end address for Flash ROM is OFFFFh Flash can be used for both code and data Word or byte tables can be stored and used in Flash ROM without the need to copy the tables to RAM before using them The interrupt vector table is mapped into the the upper 16 words of Flash ROM address space with the highest priority interrupt vector at the highest Flash ROM word address OFFFEh RAM starts at 0200h The end address of RAM depends on the amount of RAM present and varies by device RAM can be used for both code and data Address Space 1 4 3 Peripheral Modules Peripheral modules are map
57. 3 12 Figure 3 12 Decrement Overlap EDE gt TONI EDE 254 TONI 254 RISC 16 Bit CPU 3 37 Instruction Set DECD W DECD B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Double decrement destination Double decrement destination DECD dst or DECD W dst DECD B dst dst 2 dst SUB 2 dst SUB B 2 dst The destination operand is decremented by two The original contents are lost N Set if result is negative reset if positive Z Set if dst contained 2 reset otherwise C Reset if dst contained 0 or 1 set otherwise V Set if an arithmetic overflow occurs otherwise reset Set if initial value of destination was 08001 or 08000h otherwise reset Set if initial value of destination was 081 or 080h otherwise reset OSCOFF CPUOFF and GIE are not affected R10 is decremented by 2 DECD R10 Decrement R10 by two Move a block of 255 words from memory location starting with EDE to memory location starting with TONI Tables should not overlap start of destination address TONI must not be within the range EDE to EDE 0FEh Example MOV EDE R6 MOV 510 R10 L 1 MOV R6 TONI EDE 2 R6 DECD R10 JNZ L 1 Memory at location LEO is decremented by two DECD B LEO Decrement MEM LEO Decrement status byte STATUS by two DECD B STATUS 3 38 RISC 16 Bit CPU DINT Syntax Operation Emulation Description Status Bits Mode Bits
58. 3 4 4 1 RRC R9 Rn 3 4 5 1 SWPB GR10 N See note 4 5 2 CALL 81H X Rn 4 5 5 2 CALL 2 R7 EDE 4 5 5 2 PUSH ED amp EDE 4 5 5 2 SXT amp ED Note Instruction Format Il Immediate Mode Do not use instructions RRA RRC SWPB and SXT with the immediate mode in the destination field Use of these in the immediate mode results in an unpredictable program operation a as Format lll Jump Instruction Cycles and Lengths All jump instructions require one code word and take two CPU cycles to execute regardless of whether the jump is taken or not 3 72 RISC 16 Bit CPU Format l Double Operand Instruction Cycles and Lengths Instruction Set Table 3 16 lists the length and CPU cycles for all addressing modes of format instructions Table 3 16 Format 1 Instruction Cycles and Lengths Addressing Mode Src Rn Rn Rn N x Rn EDE amp EDE Dst Rm PC x Rm EDE amp EDE Rm PC x Rm EDE amp EDE Rm PC x Rm EDE amp EDE Rm PC x Rm EDE amp EDE Rm PC TONI x Rm amp TONI Rm PC TONI x Rm amp TONI Rm PC TONI x Rm amp TONI No of Cycles c OO DW WIDD DAWA a NIA C101 NIA a aw NIA A A Length of Instruction WN OO OO N OO OO N NIN N N H HAITM N N AITNMN N N H A MOV BR ADD XOR MOV AND BR XOR MOV XOR ADD BR XOR OV OV OV BR OV ADD ADD OV BR OV
59. 4 3 2 1 0 CKPL SSELx URXSE TXWAKE rw 0 rw 1 rw 0 rw 0 rw 0 rw 0 rw 0 Unused Clock polarity select 0 UCLKI UCLK 1 UCLKI inverted UCLK Source select These bits select the BRCLK source clock 00 UCLKI 01 ACLK 10 SMCLK 11 SMCLK UART receive start edge The bit enables the UART receive start edge feature 0 Disabled 1 Enabled Transmitter wake 0 Next frame transmitted is data 1 Next frame transmitted is an address Unused Transmitter empty flag 0 UART is transmitting data and or data is waiting in UXTXBUF 1 Transmitter shift register and UXTXBUF are empty or SWRST 1 USART Peripheral Interface UART Mode 13 23 USART Registers UART Mode UxRCTL USART Receive Control Register rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 FE Bit 7 Framing error flag 0 No error 1 Character received with low stop bit PE Bit 6 Parity error flag When PENA 0 PE is read as 0 0 No error 1 Character received with parity error OE Bit 5 Overrun error flag This bit is set when a character is transferred into UxRXBUF before the previous character was read 0 No error 1 Overrun error occurred BRK Bit4 Break detect flag 0 No break condition 1 Break condition occurred URXEIE Bit 3 Receive erroneous character interrupt enable 0 Erroneous characters rejected and URXIFGx is not set 1 Erroneous characters received will set URXIFGx URXWIE Bit 2 Receive wake up interrupt enable This bit enables URXIFGx to
60. 4 KB 256 byte FFFFh F000h 10FFh 1000h Flash Memory SegmentO 4 kbyte Flash Main Memory 256 byte Flash information Memor SegmentA SegmentB Flash Memory Controller 5 3 Flash Memory Operation 5 3 Flash Memory Operation The default mode of the flash memory is read mode In read mode the flash memory is not being erased or written the flash timing generator and voltage generator are off and the memory operates identically to ROM MSP430 flash memory is in system programmable ISP without the need for additional external voltage The CPU can program its own flash memory The flash memory write erase modes are selected with the BLKWRT WRT MERAS and ERASE bits and are L Byte word write Block write Segment Erase Mass Erase all main memory segments D D All Erase all segments Reading or writing to flash memory while it is being programmed or erased is prohibited If CPU execution is required during the write or erase the code to be executed must be in RAM Any flash update can be initiated from within flash memory or RAM 5 3 4 Flash Memory Timing Generator Write and erase operations are controlled by the flash timing generator shown in Figure 5 3 The flash timing generator operating frequency must be in the range from 257 kHz to 476 kHz see device specific datasheet Figure 5 3 Flash Memory Timing Generator Block Diagram ACLK MCLK SMCLK SMCLK FSS
61. 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 I2CNDATx Bits 12C number of bytes These bits support automatic data byte counting In word 7 0 mode I2CNDATx must be an even value Write to register Number of bytes Read from register 2 1 Number of bytes remaining in transfer Read from register 2 0 Number of bytes to be transferred T SN ES au ooo Note I2CNDAT Register Do not change the I2CNDAT register while I2CBB 1 and I2CRM 0 USART Peripheral Interface I C Mode 15 25 I C Module Registers I2CPSC I2C Clock Prescaler Register 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 m Modifiable only when I2CEN 0 I2CPSCx Bits I2C clock prescaler The 12C clock input is divided by the IPCPSCx value to 7 0 produce the internal 12C clock frequency The division rate is 2 9 1 000h Divide by 1 001h Divide by 2 OFFh Divide by 256 15 26 USART Peripheral Interface 12C Mode 12C Module Registers I2CSCLH I C Shift Clock High Register 7 6 5 4 3 2 1 0 I2CSCLHx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 m Modifiable only when I2CEN 0 I2CSCLHx Bits I2C shift clock high These bits define the high period of SCL when the 12C 7 0 controller is in master mode The SCL high period is I2CSCLH 2 x I2CPSC 000h N A 001h N A 002h N A 003h SCL high period 5 x I2CPSC OFFh SCL high period 257 x I2ZCPSC I2CSCLL Shift Clock Low Register 6 5 4 3 2 1 0 rw 0
62. 6 device specific OFFEAh 5 device specific OFFE8h 4 HO Fore maskable OFFE6h 3 VO ESRES 8 t0 maskabee OFFE4h 2 device specific OFFE2h 1 device specific OFFEOh 0 lowest 2 2 5 Special Function Registers SFRs Some module enable bits interrupt enable bits and interrupt flags are located in the SFRs The SFRs are located in the lower address range and are implemented in byte format SFRs must be accessed using byte instructions See the device specific datasheet for the SFR configuration System Resets Interrupts and Operating Modes 2 13 Operating Modes 2 3 Operating Modes The MSP430 family is designed for ultralow power applications and uses different operating modes shown in Figure 2 10 The operating modes take into account three different needs _j Ultralow power Speed and data throughput Minimization of individual peripheral current consumption The MSP430 typical current consumption is shown in Figure 2 9 Figure 2 9 Typical Current Consumption of 13x and 14x Devices vs Operating Modes ICC u A AM LPMO LPM2 LPM3 LPM4 Operating Modes The low power modes 0 4 are configured with the CPUOFF OSCOFF SCGO0 and SCG1 bits in the status register The advantage of including the CPUOFF OSCOFF SCGO and SCG1 mode control bits in the status register is that the present operating mode is saved onto the stack during an interrupt service routine Program flow returns
63. BIS B 4 SWRST amp UxCTL 2 Initialize all USART registers with SWRST 1 including UxCTL 3 Enable USART module via the MEx SFRs USPIEx 4 Clear SWRST via software BIC B SWRST amp UxCTL 5 Enable interrupts optional via the IEx SFRs URXIEx and or UTXIEx rae DTS DH Failure to follow this process may result in unpredictable USART behavior USART Peripheral Interface SPI Mode USART Operation SPI Mode 14 2 2 Master Mode Figure 14 2 USAHT Master and External Slave MASTER Receive Buffer UXRXBUF Transmit Buffer UXTXBUF Receive Shift Register LSB SCLK MSP430 USART COMMON SPI Figure 14 2 shows the USART as a master in both 3 pin and 4 pin configurations The USART initiates data transfer when data is moved to the transmit data buffer UXTXBUF The UxTXBUF data is moved to the TX shift register when the TX shift register is empty initiating data transfer on SIMO starting with the most significant bit Data on SOMI is shifted into the receive shift register on the opposite clock edge starting with the most significant bit When the character is received the receive data is moved from the RX shift register to the received data buffer UXRXBUF and the receive interrupt flag URXIFGx is set indicating the RX TX operation is complete A set transmit interrupt flag UTXIFGx indicates that data has moved from UxTXBUF to the TX shift register and UXTXBUF is ready for ne
64. Branch to LABEL if R5 is O TST R5 JZ LABEL RISC 16 Bit CPU 3 45 Instruction Set JGE Syntax Operation Description Status Bits Example Jump if greater or equal JGE label If N XOR V 0 then jump to label PC 2 x offset PC If N XOR V 1 then execute the following instruction The status register negative bit N and overflow bit V are tested If both N and V are set or reset the 10 bit signed offset contained in the instruction LSBs is added to the program counter If only one is set the instruction following the jump is executed This allows comparison of signed integers Status bits are not affected When the content of R6 is greater or equal to the memory pointed to by R7 the program continues at label EDE CMP R7 R6 R6 2 R7 compare on signed numbers JGE EDE Yes R6 gt R7 No proceed 3 46 RISC 16 Bit CPU JL Syntax Operation Description Status Bits Example Instruction Set Jump if less JL label If N XOR V 1 then jump to label PC 2 x offset PC If N XOR V 0 then execute following instruction The status register negative bit N and overflow bit V are tested If only one is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If both N and V are set or reset the instruction following the jump is executed This allows comparison of signed integers Status bits are not affected W
65. C from destination Set C Set N Set Z Subtract source from destination Subtract source and not C from dst Swap bytes Extend sign Test destination Exclusive OR source and destination dst C gt dst src dst gt dst src dst C gt dst src and dst dst not src and dst dst Src or dst dst src and dst dst PC PC 2 gt stack dst PC 0 2 dst 02C 0 gt N 02Z dst src dst C dst decimally src dst C dst decimally dst 1 dst dst 2 2 dst 0 2 GIE 1o GIE dst 1 dst dst 2 dst not dst gt dst PC 2 x offset 2 PC src gt dst SP dst SP 2 2 SP SP 2 SP src gt SP SP PC SP 25 SP dst OFFFFh C gt dst 13C 1 gt N 12C dst not src 1 gt dst dst not src C gt dst dst OFFFFh 1 Src xor dst dst o 1 Instruction Set N 2 Cc 0 0 n 0 1 1 gt lt 1 1 RISC 16 Bit CPU 3 75 3 76 Chapter 4 Basic Clock Module The basic clock module provides the clocks for MSP430x1 xx devices This chapter describes the operation of the basic clock module The basic clock module is implemented in all MSP430x1xx devices Topic 4 2 Basic Clock Module Operation 4 3 Basic Clock Module Registers
66. DMADSTBYTE and DMASRCBYTE bits determine if they are incremented decremented by one byte or word t Once started the burst block mode operates continuously until the DMAEN bit is reset No additional trigger events are required 8 8 DMA Controller 8 2 3 Initiating DMA Transfers DMA Operation DMA transfers are initiated from software or hardware and are described in Table 8 1 Each DMA channel is independently configured for its trigger source with the DMAXTSELx bits Table 8 1 DMA Trigger Sources DMAx TSELx DMA Trigger Trigger Action 0000 0001 0010 0011 0100 0101 0110 0111 1101 1110 1111 DMAREQ TACCR2 CCIFG TBCCR2 CCIFG 12 data received 12C transmit ready DAC12 0 DAC12IFG ADC12IFGx No Trigger DMAxIFG DMAEO Setting the DMAREQ bit triggers a DMA transfer DMAREQ is automatically reset when the DMA transfer starts A DMA transfer is triggered when the TACCR2 CCIFG flag is set TACCR2 CCIFG is automatically reset when the DMA transfer starts A DMA transfer is triggered when the TBCCR2 CCIFG flag is set The TBCCR2 CCIFG is automatically reset when the DMA transfer starts A DMA transfer is triggered when the 12C module receives new data The DMA trigger is the condition not the RXRDYIFG flag RXRDYIFG is not cleared when the DMA transfer starts and setting RXRDYIFG with software will not trigger a DMA transfer A DMA transfer is triggered when the 12C mo
67. Example Instruction Set Disable general interrupts DINT 0 2 GIE or OFFF7h AND SR SR AND dst dst BIC 8 SR All interrupts are disabled The constant 08h is inverted and logically ANDed with the status register SR The result is placed into the SR Status bits are not affected GIE is reset OSCOFF and CPUOFF are not affected The general interrupt enable GIE bit in the status register is cleared to allow a nondisrupted move of a 32 bit counter This ensures that the counter is not modified during the move by any interrupt DINT All interrupt events using the GIE bit are disabled NOP MOV COUNTHI R5 Copy counter MOV COUNTLO R6 EINT All interrupt events using the GIE bit are enabled TTT A A Note Disable Interrupt If any code sequence needs to be protected from interruption the DINT should be executed at least one instruction before the beginning of the uninterruptible sequence or should be followed by a NOP instruction es RISC 16 Bit CPU 3 39 Instruction Set EINT Syntax Operation Emulation Description Status Bits Mode Bits Example Enable general interrupts EINT 19 GIE or 0008h OR SR SR src OR dst dst BIS 8 SR All interrupts are enabled The constant 08h and the status register SR are logically ORed The result is placed into the SR Status bits are not affected GIE is set OSCOFF and C
68. Figure 15 1 USART Block Diagram 12C Mode MST LISTEN Receive Shift Register I2CSSELx A SCL gt No clock o I2C Clock Generator ACLK I2CPSC SMCLK I2CSCLL SMCLK I2CSCLH 0 SDA Transmit Shift Register Y v O Receive Transmit I2C Data Register I2CDR 077h I2C Data Register I2CDR 076h USART Peripheral Interface I C Mode 15 3 12C Module Operation 15 2 12C Module Operation The I2C module supports any slave or master I2C compatible device Figure 15 2 shows an example of an 12C bus Each 12C device is recognized by a unique address and can operate as either a transmitter or a receiver A device connected to the I2C bus can be considered as the master or the slave when performing data transfers A master initiates a data transfer and gener ates the clock signal SCL Any device addressed by a master is considered a slave Figure 15 2 12C Bus Connection Diagram 15 4 Pull Up MSP430 2 Resistors 12 Device A Serial Data SDA Serial Clock SCL 12 12C Device B Device C 12C data is communicated using the serial data pin SDA and the serial clock pin SCL Both SDA and SCL are bidirectional and must be connected to a positive supply voltage using a pull up resistor Note SDA and SCL Levels The MSP430 SDA and SCL pins must not be pulled up above the MSP430 Vcc level LC _ ea __ _____________ USART Peripheral Interface 12C Mod
69. MSBs of the RAM word LEO are cleared BIC 0FC00h LEO Clear 6 MSBs in MEM LEO The five MSBs of the RAM byte LEO are cleared BIC B 0F8h LEO Clear 5 MSBs in Ram location LEO RISC 16 Bit CPU 3 25 Instruction Set BIS W BIS B Syntax Operation Description Status Bits Mode Bits Example Example Set bits in destination Set bits in destination BIS src dst or BIS W src dst BIS B src dst src OR dst dst The source operand and the destination operand are logically ORed The result is placed into the destination The source operand is not affected Status bits are not affected OSCOFF CPUOFF and GIE are not affected The six LSBs of the RAM word TOM are set BIS 003Fh TOM set the six LSBs in RAM location TOM The three MSBs of RAM byte TOM are set BIS B 0E0h TOM set the 3 MSBs in RAM location TOM 3 26 RISC 16 Bit CPU BIT W BIT B Syntax Operation Description Status Bits Mode Bits Example Example Example Instruction Set Test bits in destination Test bits in destination BIT src dst or BIT W src dst src AND dst The source and destination operands are logically ANDed The result affects only the status bits The source and destination operands are not affected N Set if MSB of result is set reset otherwise Z Setif result is zero reset otherwise C Setif result is not zero reset otherwise NOT Zero V Reset OSCOFF CPUOFF and GIE are not affect
70. No acknowledge interrupt enable 0 Interrupt enabled 1 Interrupt disabled ALIE Bit 0 Arbitration lost interrupt enable 0 Interrupt enabled 1 Interrupt disabled 15 30 USART Peripheral Interface 12C Mode 12C Module Registers I2CIFG 12C Interrupt Flag Register STTIFG GCIFG TXRDYIFG RXRDYIFG ARDYIFG ore NACKIFG ALIFG rw 0 STTIFG GCIFG TXRDYIFG RXRDYIFG ARDYIFG OAIFG NACKIFG ALIFG rw 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 rw 0 rw 0 rw 0 Start detect interrupt flag 0 No interrupt pending 1 Interrupt pending General call interrupt flag 0 No interrupt pending 1 Interrupt pending Transmit ready interrupt flag 0 No interrupt pending 1 Interrupt pending Receive ready interrupt flag 0 No interrupt pending 1 Interrupt pending Access ready interrupt flag The ARDYIFG set conditions are Mode Applicable Bits ARDYIFG Set Conditions Master transmit I2CSTP 1 I2CNDAT 0 and all data transmitted I2CRM 0 I2CRM 1 Last byte of data sent after I2CSTP has been set Master receive I2CSTP 1 2 0 and receive buffer I2CRM 0 empty I2CRM 1 Last byte of data received and receive buffer empty after I2CSTP has been set Slave transmit Stop condition received Slave receive Stop condition received and receive buffer empty Own address interrupt flag 0 No interrupt pending 1 Interrupt pending No acknowledge interrupt flag 0
71. OFFFFh 11 Up down The timer repeatedly counts from zero up to the value of TACCRO and back down to zero Timer A 11 5 Timer A Operation Up Mode The up mode is used if the timer period must be different from OFFFFh counts The timer repeatedly counts up to the value of compare register TACCRO which defines the period as shown in Figure 11 2 The number of timer counts in the period is TACCRO 1 When the timer value equals TACCRO the timer restarts counting from zero If up mode is selected when the timer value is greater than TACCRO the timer immediately restarts counting from zero Figure 11 2 Up Mode OFFFFh TACCRO Oh The TACCRO CCIFG interrupt flag is set when the timer equals the TACCRO value The TAIFG interrupt flag is set when the timer counts from TACCRO to zero Figure 11 3 shows the flag set cycle Figure 11 3 Up Mode Flag Setting Timer Clock Timer Set TAIFG Set TACCRO CCIFG Changing the Period Register TACCRO 11 6 Timer A When changing TACCRO while the timer is running if the new period is greater than or equal to the old period or greater than the current count value the timer counts up to the new period If the new period is less than the current count value the timer rolls to zero However one additional count may occur before the counter rolls to zero Timer A Operation Continuous Mode Inthe continuous mode the timer repeatedly counts
72. Operation UART Mode Receive Bit Timing Receive timing consists of two error sources The first is the bit to bit timing error The second is the error between a start edge occurring and the start edge being accepted by the USART Figure 13 9 shows the asynchronous timing errors between data on the URXDx pin and the internal baud rate clock Figure 13 9 Receive Error i 0 1 2 tideal to T 11 213 4 5le 7 8 1 11 12 1 14 1 2 3 4 5 e 8 12 13 14 1 2 3 4 5 6 URXDx st DO D2 URXDS ST DO D2 tactual to t t2 9 Synchronization Error 0 5x BRCLK Sample PAGES Int UxBR 2 m0 UxBR m1 1341 14 UxBR m2 13 0 13 fan int 13 2 1 6 1 17 fan Majority Vote Taken Majority Vote Taken PE TIR The ideal start bit timing tigeaj o is half the baud rate timing tbaud rate because the bitis tested in the middle of its period The ideal baud rate timing tigeay for the remaining character bits is the baud rate timing tbaud rate The individual bit errors can be calculated by Error ve eee x 2 x mo int A i x UxBR Tm 1 100 Where baud rate is the required baud rate BRCLKis the input frequency selected for UCLK ACLK or SMCLK j for the start bit 1 for data bit DO and so on UxBH is the division factor in registers UXBR1 and UxBRO 13 14 USART Peripheral Interface UART Mode USART Operation UART Mode For exa
73. POR ADC10 control register 0 ADC10CTLO Read write 01BOh Reset with POR ADC10 control register 1 ADC10CTL1 Read write 01B2h Reset with POR ADC10 memory ADC10MEM Read 01B4h Unchanged ADC10 data transfer control register ADC10DTCO Read write 048h Reset with POR ADC10 data transfer control register 1 ADC10DTC1 Read write 049h Reset with POR ADC10 data transfer start address ADC10SA Read write 01BCh 0200h with POR 18 24 ADC10 ADC10 Registers ADC10CTLO ADC10 Control Register 0 15 14 13 12 Abciosm merour rereuRsT rw 0 rw 0 rw 0 rw 0 REF2_5V mo anciora rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Modifiable only when ENC 0 SREFx Bits 15 13 ADC10 Bits SHTx 12 11 ADC10SR Bit 10 REFOUT Bit 9 REFBURST Bit 8 Select reference 000 Vg and Vp AVss 001 Vn VREF and VR AVss 010 Vg Vengr and Vp AVss 011 Vr Vengr and Vp AVss 100 Vg and Vp Vnggr VeREF 101 Vg Vref and Vp VREF Vengr 110 Vg Vengr and Vp Vngr Vengr 111 Vg Verner and Vp Vpgr Vengr ADC10 sample and hold time 00 4xADC1O0OCLKs 01 8x ADC10CLKs 10 16x ADC10CLKs 11 64x ADC10CLKs ADC10 sampling rate This bit selects the approximate maximum sample rate of the ADC10 0 200 ksps 1 50 ksps Reference output 0 Reference output off 1 Reference output
74. PUC is always generated when a POR is generated but a POR is not generated by a PUC The following events trigger a PUC A POR signal Watchdog timer expiration when in watchdog mode only d L Watchdog timer security key violation d A Flash memory security key violation 2 2 System Resets Interrupts and Operating Modes System Reset and Initialization 2 1 4 Power On Reset POR When the Vcc rise time is slow the POR detector holds the POR signal active until has risen above the V pog level as shown in Figure 2 2 When the Vcc supply provides a fast rise time the POR delay t poR_DELAY provides active time on the POR signal to allow the MSP430 to initialize If power to the MSP430 is cycled the supply voltage Vcc must fall below V min to ensure that another POR signal occurs when Vcc is powered up again If Vcc does notfall below V min during a cycle or a glitch a PORis notgenerated and power up conditions do not set correctly See device specific datasheet for parameters Figure 2 2 POR Timing V VCC minp 5 j 4 A f oul eee ee ee OG ec m Vu S a p Set Signal for POR circuitry 1 POR DELAY 1 0 DELAY System Resets Interrupts and Operating Modes 2 3 System Reset and Initialization 2 1 2 Brownout Reset BOR Some devices have a brownout reset circuit see device specific datasheet that replaces the
75. R3 add LSDs DADD R6 R4 add MSDs with carry JC OVERFLOW If carry occurs go to error handling routine The two digit decimal counter in the RAM byte CNT is incremented by one CLRC clear Carry DADD B 1 CNT increment decimal counter Or SETC DADD B 80 CNT DADC B CNT 3 36 RISC 16 Bit CPU DEC W DEC B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Instruction Set Decrement destination Decrement destination DEC dst or DEC W dst DEC B dst dst 1 dst SUB 1 dst SUB B 1 dst The destination operand is decremented by one The original contents are lost N Set if result is negative reset if positive 2 Set if dst contained 1 reset otherwise C Reset if dst contained 0 set otherwise V Set if an arithmetic overflow occurs otherwise reset Set if initial value of destination was 08000h otherwise reset Set if initial value of destination was 080h otherwise reset OSCOFF CPUOFF and GIE are not affected R10 is decremented by 1 DEC R10 Decrement R10 Move a block of 255 bytes from memory location starting with EDE to memory location starting with TONI Tables should not overlap start of destination address TONI must not be within the range EDE to EDE 0FEh L 1 MOV EDE R6 MOV 255 R10 MOV B R6 TONI EDE 1 R6 DEC R10 JNZ L 1 not transfer tables using the routine above with the overlap shown in Figure
76. Registers 3 2 2 Stack Pointer SP The stack pointer SP R1 is used by the CPU to store the return addresses of subroutine calls and interrupts It uses a predecrement postincrement scheme In addition the SP can be used by software with all instructions and addressing modes Figure 3 3 shows the SP The SP is initialized into RAM by the user and is aligned to even addresses Figure 3 4 shows stack usage Figure 3 3 Stack Pointer 15 Lo Stack Pointer Bits 15 to 1 ES MOV 2 SP R6 Item I2 gt R6 MOV R7 0 SP Overwrite TOS with R7 PUSH 0123h Put 0123h onto TOS POP R8 R8 0123h Figure 3 4 Stack Usage Address PUSH 0123h POP R8 Oxxxh Oxxxh 2 Oxxxh 4 Oxxxh 6 Oxxxh 8 SP The special cases of using the SP as an argument to the PUSH and POP instructions are described and shown in Figure 3 5 Figure 3 5 PUSH SP POP SP Sequence PUSH SP POP SP SPolg SP4 SP SP2 SP The stack pointer is changed after The stack pointer is not changed after a POP SP a PUSH SP instruction instruction The POP SP instruction places SP1 into the stack pointer SP SP2 SP1 RISC 16 Bit CPU 3 5 CPU Registers 3 2 3 Status Register SR Figure 3 6 Status Register Bits The status register SR R2 used as a source or destination register can be used in the register mode only addressed with word instructions The remain ing combinations of addressing modes are used to support the const
77. TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2003 Texas Instruments Incorporated About This Manual Preface Read This First This manual discusses modules and peripherals of the MSP430x1 xx family of devices Ea
78. The output is set when the timer counts to the TBCLx value It remains set until a reset of the timer or until another output mode is selected and affects the output The output is toggled when the timer counts to the TBCLx value It is reset when the timer counts to the TBCLO value The output is set when the timer counts to the TBCLx value It is reset when the timer counts to the TBCLO value The output is toggled when the timer counts to the TBCLx value The output period is double the timer period The output is reset when the timer counts to the TBCLx value It remains reset until another output mode is selected and affects the output The output is toggled when the timer counts to the TBCLx value It is set when the timer counts to the TBCLO value The output is reset when the timer counts to the TBCLx value It is set when the timer counts to the TBCLO value Timer B Operation Output Example Timer in Up Mode The OUTxsignal is changed whenthe timer counts upto the TBCLx value and rolls from TBCLO to zero depending on the output mode An example is shown in Figure 12 12 using TBCLO and TBCL1 Figure 12 12 Output Example Timer in Up Mode Example EQU1 Used TBR max TBCLO TBCL1 Output Mode 1 Set Output Mode 2 Toggle Reset Output Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set E
79. When using block or burst block modes only one trigger is required to initiate the block or burst block transfer Level Sensitive Triggers When DMALEVEL 1 level sensitive triggers are used For proper operation level sensitive triggers can used only be used when external trigger DMAEO is selected as the DMA trigger When DMALEVEL 1 DMA transfers are triggered as long as the trigger signal is high and the DMAEN bit remains set DMA transfer modes DMADTx 0 1 2 3 are recommended when DMALEVEL 1 because the DMAEN bit is automatically reset after the configured DMA transfer When DMALEVEL 1 the trigger signal must remain high for a block or burst block transfer to complete If the trigger signal goes low during a block or burst block transfer the DMA controller is held in its current state until the trigger goes back high or until the DMA registers are modified by software If the DMA registers are not modified by software when trigger signal goes high again the transfer resumes from where it was when the trigger signal went low Halting Executing Instructions for DMA Transfers The DMAONFETCH bit controls when the CPU is halted for a DMA transfer When DMAONFETCH 0 the CPU is halted immediately and the DMA transfer begins when a DMA trigger is received When DMAONFETCH 1 the CPU finishes the currently executing instruction before the DMA controller halts the CPU and the DMA transfer begins 8 10 DMA Controller DM
80. Writing OP2 starts the selected operation with the values stored in OP1 and OP2 The result is written into the three result registers RESLO RESHI and SUMEXT Repeated multiply operations may be performed without reloading OP1 if the OP1 value is used for successive operations It is not necessary to re write the OP1 value to perform the operations Table 7 1 OP1 addresses OP1 Address Register Name Operation 0130h MPY Unsigned multiply 0132h MPYS Signed multiply 0134h MAC Unsigned multiply accumulate 0136h MACS Signed multiply accumulate Hardware Multiplier 7 8 Hardware Multiplier Operation 7 2 2 Result Registers The result low register RESLO holds the lower 16 bits of the calculation result The result high register RESHI contents depend on the multiply operation and are listed in Table 7 2 Table 7 2 RESHI Contents Mode MPY MPYS MAC MACS RESHI Contents Upper 16 bits of the result The MSB is the sign of the result The remaining bits are the upper 15 bits of the result Two s complement notation is used for the result Upper 16 bits of the result Upper 16 bits of the result Two s complement notation is used for the result The sum extension registers SUMEXT contents depend on the multiply operation and are listed in Table 7 3 Table 7 3 SUMEXT Contents MACS Underflow and Overflow 74 Mode MPY MPYS MAC MACS SUMEXT SUMEXT is always 0000h SUMEXT contains the extended sig
81. a flash write or erase operation is 2 7 V If Vcc falls below 2 7 V during a write or erase the result of the write or erase will be unpredictable Figure 5 1 Flash Memory Module Block Diagram Address Latch Data Latch Enable Address Latch Timing Generator Enable Data Latch Programming Voltage Generator 5 2 Flash Memory Controller Flash Memory Segmentation 5 2 Flash Memory Segmentation MSP430 flash memory is partitioned into segments Single bits bytes or words can be written to flash memory but the segment is the smallest size of flash memory that can be erased Three erase modes provide the ability to erase a single segment erase all main segments or erase all segments main and information segments The flash memory is partitioned into main and information memory sections There is no difference in the operation of the main and information memory sections Code or data can be located in either section The differences between the two sections are the segment size and the physical addresses The information memory has two 128 byte segments MSP430x1101 devices have only one The main memory has two or more 512 byte segments See the device specific datasheet for the complete memory map of a device Figure 5 2 shows the flash segmentation using an example of 4 KB flash that has eight main segments and both information segments Figure 5 2 Flash Memory Segments 4 KB Example
82. and Differences From 12 2 12 2 Timer B Operation cece nents 12 4 12 2 1 16 Bit Timer Counter 0 00 cent ees 12 4 12 2 2 Starting the Timer 0 0 cece teen eens 12 5 12 2 8 Timer Mode Control ete eet eens 12 5 12 2 4 Capture Compare Blocks 12 11 12 2 5 Ult c 2 et delights an otto aed nosing wll dice te ead whe 12 14 12 2 6 Timer Interrupts eee 12 18 12 3 Shimer B Registers rikni denie s AnA pele kee hide bee 12 20 13 USART Peripheral Interface UART Mode 13 1 13 1 USART Introduction UART 13 2 13 2 USART Operation UART Mode 13 4 13 2 1 USART Initialization and 13 4 13 2 2 Character Format s assassina neeaaea 13 4 13 2 3 Asynchronous Communication Formats 13 5 13 2 4 USART Receive Enable 13 9 13 2 5 USART Transmit Enable 13 10 13 2 6 UART Baud Rate Generation 13 11 19 2 7 USART Interrupts aces nim aber iiss bbe bert eee Ake 13 17 13 3 USART Registers UART
83. based on a ratiometric conversion principle The ratio of two capacitor discharge times is calculated as shown in Figure 16 6 Figure 16 6 Timing for Temperature Measurement Systems Vo Voc 0 25 x Vcc pres re Phase I Phase Il Phase III Phase IV t by Charge Discharge li Charge ly Discharge tref tmeas gt The Vcc voltage and the capacitor value should remain constant during the conversion but are not critical since they cancel in the ratio V f R meas X C x In Nmeas E Voc Nret Fret X C x In vet re V CC Nmeas _ Hmeas N ef R ef N meas Rmeas Pref X N ref Comparator A 16 7 Comparator A Registers 16 3 Comparator A Registers The Comparator_A registers are listed in Table 16 1 Table 16 1 Comparator A Registers Register Short Form Register Type Address Comparator_A control register 1 CACTL1 Read write 059h Comparator control register 2 CACTL2 Read write 05Ah Comparator A port disable CAPD Read write 05Bh 16 8 Comparator A Initial State Reset with POR Reset with POR Reset with POR Comparator A Registers CACTL1 Comparator A Control Register 1 7 rw 0 CAEX CARSEL CAREF CAON CAIES CAIE CAIFG Bit 7 Bit 6 Bits 5 4 Bit 3 Bit 2 Bit 1 Bit 0 5 4 rw rw 3 2 1 0 0 0 rw 0 rw 0 rw 0 rw 0 rw 0 Comparator_A exchange This bit exchanges the comparator i
84. clock module See Chapter System Resets Interrupts and Operating Modes The DCOCTL BCSCTL1 and BCSCTL2 registers configure the basic clock module The basic clock can be configured or reconfigured by software at any time during program execution for example BIS B RSEL2 RSEL1 RSELO amp BCSCTL1 BIS B DCO2 DCO1 DCO0 amp DCOCTL Set max DCO frequency Basic Clock Module Features for Low Power Applications Conflicting requirements typically exist in battery powered MSP430x1xx applications Low clock frequency for energy conservation and time keeping High clock frequency for fast reaction to events and fast burst processing capability The basic clock module addresses the above conflicting requirements by allowing the user to select from the three available clock signals ACLK MCLK and SMCLK For optimal low power performance the ACLK can be configured to oscillate with a low power 32 786 Hz watch crystal providing a stable time base for the system and low power stand by operation The MCLK can be configured to operate from the on chip DCO that can be only activated when requested by interrupt driven events The SMCLK can be configured to operate from either the watch crystal or the DCO depending on peripheral requirements A flexible clock distribution and divider system is provided to fine tune the individual clock requirements Basic Clock Module Basic Clock Module Operation 4 2 2 LFXT1 O
85. controlled by the master Three or four signals are used for SPI data exchange SIMO Slave in master out Master mode SIMO is the data output line Slave mode SIMO is the data input line SOMI Slave out master in Master mode SOMI is the data input line Slave mode SOMI is the data output line UCLK USART SPI clock Master mode UCLK is an output Slave mode UCLK is an input STE Slave transmit enable Used in 4 pin mode to allow multiple masters on a single bus Not used in 3 pin mode 4 Pin master mode When STE is high SIMO and UCLK operate normally When STE is low SIMO and UCLK are set to the input direction 4 pin slave mode When STE is high RX TX operation of the slave is disabled and SOMI is forced to the input direction When STE is low RX TX operation of the slave is enabled and SOMI operates normally 14 2 1 USART Initialization and Reset 14 4 The USART is reset by a PUC or by the SWRST bit After a PUC the SWRST bit is automatically set keeping the USART in a reset condition When set the SWRST bit resets the URXIEx UTXIEx URXIFGx OE and FE bits and sets the UTXIFGx flag The USPIEx bit is not altered by SWRST Clearing SWRST releases the USART for operation See also chapter USART Module I2C mode for USARTO when reconfiguring from 12 mode to SPI mode Note Initializing or Re Configuring the USART Module The required USART initialization re configuration process is 1 Set SWRST
86. different contents CMP R7 R8 COMPARE R7 WITH R8 JNE TONI if different jump e if equal continue RISC 16 Bit CPU 3 51 Instruction Set MOV W MOV B Syntax Operation Description Status Bits Mode Bits Example Loop Example Loop Move source to destination Move source to destination MOV src dst or MOV W src dst MOV B src dst src gt dst The source operand is moved to the destination The source operand is not affected The previous contents of the destination are lost Status bits are not affected OSCOFF CPUOFF and GIE are not affected The contents of table EDE word data are copied to table TOM The length of the tables must be 020h locations MOV EDE R10 Prepare pointer MOV 020h R9 Prepare counter MOV QR104 TOM EDE 2 R10 Use pointer in R10 for both tables DEC R9 Decrement counter JNZ Loop Counter z 0 continue copying BL Copying completed The contents of table EDE byte data are copied to table TOM The length of the tables should be 020h locations MOV EDE R10 Prepare pointer MOV 020h R9 Prepare counter MOV B QQR10 TOM EDE 1 R10 Use pointer in R10 for both tables DEC R9 Decrement counter JNZ Loop Counter z 0 continue copying s Copying completed 3 52 RISC 16 Bit CPU NOP Syntax Operation Emulation Description Status Bits Instruction Set No operation NOP None MOV 0 R3 No operation is performed The instruction
87. enabled to generate an NMI interrupt by setting the OFIE bit The OFIFG flag can then be tested by NMI the interrupt service routine to determine if the NMI was caused by an oscillator fault A PUC signal can trigger an oscillator fault because the PUC switches the LFXT1 to LF mode therefore switching off the HF mode The PUC signal also switches off the XT2 oscillator Flash Access Violation The flash ACCVIFG flag is set when a flash access violation occurs The flash access violation can be enabled to generate an NMI interrupt by setting the ACCVIE bit The ACCVIFG flag can then be tested by NMI the interrupt service routine to determine if the NMI was caused by a flash access violation System Resets Interrupts and Operating Modes 2 9 System Reset and Initialization Example of an NMI Interrupt Handler The NMI interrupt is a multiple source interrupt An NMI interrupt automatically resets the NMIIE OFIE and ACCVIE interrupt enable bits The user NMI service routine resets the interrupt flags and re enables the interrupt enable bits according to the application needs as shown in Figure 2 6 Figure 2 6 NMI Interrupt Handler Start of NMI Interrupt Handler Reset by HW OFIE NMIE ACCVIE Reset OFIFG Reset ACCVIFG Reset NMIIFG User s Software User s Software User s Software Oscillator Fault Flash Access External NMI Handler Violation Handler Handler Optional Set NMIIE OFIE ACCV
88. equal to an arithmetic division by 2 RRA R5 R5 2 R5 The value in R5 is multiplied by 0 75 0 5 0 25 PUSH R5 hold R5 temporarily using stack RRA R5 R5 x 0 5 R5 ADD SP R5 R5x0 5 R5 1 5xR5 R5 RRA R5 1 5 x R5 x 0 5 0 75 x R5 gt R5 Example The low byte of R5 is shifted right one position The MSB retains the old value It operates equal to an arithmetic division by 2 RRA B R5 R5 2 R5 operation is on low byte only High byte of R5 is reset RRA B R5 R5x0 5 R5 PUSH B R5 R5x0 5 TOS RRA B SP TOS x 0 5 0 5 x R5 x 0 5 0 25 x R5 TOS ADD B SP R5 R5x0 5 R5 x0 25 0 75 x R5 R5 3 60 RISC 16 Bit CPU RRC W RRC B Syntax Operation Description Instruction Set Rotate right through carry Rotate right through carry RRC dst or RRC W dst RRC dst C MSB MSB 1 LSB 1 gt LSB gt C The destination operand is shifted right one position as shown in Figure 3 17 The carry bit C is shifted into the MSB the LSB is shifted into the carry bit C Figure 3 17 Destination Operand Carry Right Shift Status Bits Mode Bits Example Example Word 15 0 7 0 N Set if result is negative reset if positive Z Setif result is zero reset otherwise C Loaded from the LSB V Setif initial destination is positive and initial carry is set otherwise reset OSCOFF CPUOFF and GIE are not affected R5 is s
89. for programming erasing or updating the flash memory Figure 5 13 User Developed Programming Solution 5 16 Host Flash Memory Commands data etc 7 430 CPU executes user software Read write flash memory Flash Memory Controller Flash Memory Registers 5 4 Flash Memory Registers The flash memory registers are listed in Table 5 4 Table 5 4 Flash Memory Registers Register Short Form Register Type Address Initial State Flash memory control register 1 FCTL1 Read write 0128h 09600h with PUC Flash memory control register 2 FCTL2 Read write 012Ah 09642h with PUC Flash memory control register 3 FCTL3 Read write 012Ch 09618h with PUC Interrupt Enable 1 IE1 Read write 000h Reset with PUC Flash Memory Controller 5 17 Flash Memory Registers FCTL1 Flash Memory Control Register 15 14 13 12 11 10 9 8 FRKEY Read as 096h FWKEY Must be written as 0A5h rw 0 FRKEY FWKEY BLKWRT Reserved MERAS ERASE Reserved 5 18 Bits 15 8 Bit 7 Bit 6 Bits 5 3 Bit 2 Bit 1 Bit 0 7 6 5 4 3 2 1 0 rw 0 ro ro rw 0 ro rw 0 FCTLx password Always read as 096h Must be written as OA5h or a will be generated Block write mode WRT must also be set for block write mode BLKWRT is automatically reset when EMEX is set 0 Block write mode is off 1 Block write mode is on Write This bit is used to select any write mode WRT is automatically reset when EMEX is set
90. g 0A4h Core instruction MOV PC PC BR EXEC Branch to the address contained in EXEC Core instruction MOV X PC PC Indirect address BR amp EXEC Branch to the address contained in absolute address EXEC Core instruction MOV X 0 PC Indirect address BR R5 Branch to the address contained in R5 Core instruction MOV R5 PC Indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 Core instruction MOV R5 PC Indirect indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 and increment pointer in R5 afterwards The next time S W flow uses R5 pointer it can alter program execution due to access to next address in a table pointed to by R5 Core instruction MOV R5 PC Indirect indirect R5 with autoincrement BR X R5 Branch to the address contained in the address pointed to by R5 X e g table with address starting at X X can be an address or a label Core instruction MOV X R5 PC Indirect indirect R5 X 3 28 RISC 16 Bit CPU CALL Syntax Operation Description Status Bits Example Instruction Set Subroutine CALL dst dst tmp dst is evaluated and stored SP 2 SP PC SP PC updated to TOS tmp PC dst saved to PC A subroutine call is made to an address anywhere in the 64K address space All addressing modes can be used The return address the address of the following instruction is st
91. guarded from noise coupling from other sources The crystal should be placed as close as possible to the MSP430 with the crystal housing grounded and the crystal traces guarded with ground traces The LFXT1 oscillator in LF mode requires a 5 1 resistor from XOUT to Vss when Vcc lt 2 5 V ee Basic Clock Module 4 5 Basic Clock Module Opera tion 4 23 XT2 Oscillator Some devices have a second crystal oscillator XT2 XT2 sources XT2CLK and its characteristics are identical to LFXT1 in HF mode The XT2OFF bit disables the XT2 oscillator if XT2CLK is not used for MCLK or SMCLK as shown in Figure 4 4 Figure 4 4 Off Signals for Oscillator XT2 XT2OFF CPUOFF SELM1 SELMO SCG1 SELS 4 24 Digitally Cont Disabling the DCO Figure 4 5 On Off Co E ed y XT20ff Internal signal rolled Oscillator DCO The DCO is an integrated ring oscillator with RC type characteristics As with any RC type oscillator frequency varies with temperature voltage and from device to device The DCO frequency can be adjusted by software using the DCOx MODx and RSELx bits The digital control of the oscillator allows frequency stabilization despite its RC type characteristics Software can disable DCOCLK when not used to source SMCLK or MCLK as shown in Figure 4 5 ntrol of DCO TIN DCOCLK on XSELM1 e 1 SCGim gt 0 off SELS D Q DCOCLK CL POR SMCLK D
92. mal number pointed to by R8 CLRC Reset carry next instruction s start condition is defined DADD R5 0 R8 Add LSDs C DADC 2 R8 Add carry to MSD The two digit decimal number contained in R5 is added to a four digit decimal number pointed to by R8 CLRC Reset carry next instruction s start condition is defined DADD B R5 0 R8 Add LSDs C DADC 1 R8 Add carry to MSDs RISC 16 Bit CPU 3 35 Instruction Set DADD W DADD B Syntax Operation Description Status Bits Mode Bits Example Example Source and carry added decimally to destination Source and carry added decimally to destination DADD src dst or DADD W src dst DADD B src dst src dst C dst decimally The source operand and the destination operand are treated as four binary coded decimals BCD with positive signs The source operand and the carry bit C are added decimally to the destination operand The source operand is not affected The previous contents of the destination are lost The result is not defined for non BCD numbers N Setif the MSB is 1 reset otherwise Z Setif result is zero reset otherwise C Setif the result is greater than 9999 Set if the result is greater than 99 V Undefined OSCOFF CPUOFF and GIE are not affected The eight digit BCD number contained in R5 and R6 is added decimally to an eight digit BCD number contained in R3 and R4 R6 and R4 contain the MSDs CLRC CLEAR CARRY DADD R5
93. map However when using an instruction that modifies the contents of the destination the user must ensure the destination address is writable For example a masked ROM location would be a valid destination address butthe contents are not modifiable so the results of the instruction would be lost E Note Use of Labels and TONI Throughout MSP430 documentation EDE and TONI are used as generic labels They are only labels They have no special meaning RISC 16 Bit CPU 3 17 Instruction Set 3 4 1 Double Operand Format 1 Instructions Figure 3 9 illustrates the double operand instruction format Figure 3 9 Double Operand Instruction Format Table 3 11 lists and describes the double operand instructions Table 3 11 Double Operand Instructions Mnemonic S Reg Operation Status Bits D Reg V N Z C B src dst src dst ADD B src dst src dst dst gt ADDC B src dst SrC 051 C dst SUB B src dst dst not src 1 dst SUBC B src dst dst not src C gt dst CMP B src dst dst src DADD B src dst src 451 dst decimally BIT B src dst Src and dst 0 T BIC B src dst dst dst BIS B src dst src or dst gt dst XOR B Src dst src xor dst gt dst E ii AND B src dst src and dst dst 0 i The status bit is affected status bit is not affected 0 The status bit i
94. most important factor for reducing power consumption is using the MSP430 s clock system to maximize the time in LPM3 LPM3 power consumption is less than 2 uA typical with both a real time clock function and all interrupts active A 32 kHz watch crystal is used for the ACLK and the CPU is clocked from the DCO normally off which has a 6 us wake up Use interrupts to wake the processor and control program flow Peripherals should be switched on only when needed _j Use low power integrated peripheral modules in place of software driven functions For example Timer and Timer B can automatically generate PWM and capture external timing with no CPU resources 2 5 Connection of Unused Pins Calculated branching and fast table look ups should be used in place of flag polling and long software calculations L Avoid frequent subroutine and function calls due to overhead For longer software routines single cycle CPU registers should be used The correct termination of all unused pins is listed in Table 2 2 Table 2 2 Connection of Unused Pins Pin AVcc AVss VREF VeREF VnEr Vener XIN XOUT XT2IN XT2OUT Px 0 to Px 7 RST NMI Test Vpp Test TDO TDI TMS TCK Potential DVcc DVss Open DVss DVss DVss Open DVss Open Open DVcc or Voc DVss DVss Open Open Open Open Comment 13x 14x 15x and 16x devices 13x 14x 15x and 16x devices Switched to port function output directio
95. operand is compared with zero The status bits are set accord ing to the result The destination is not affected N Set if destination is negative reset if positive Z Set if destination contains zero reset otherwise C Set V Reset OSCOFF CPUOFF and GIE are not affected R7 is tested If it is negative continue at R7NEG if it is positive but not zero continue at R7POS TST R7 Test R7 JN R7NEG R7 is negative JZ R7ZERO R7 is zero R7POS a R7 is positive but not zero R7NEG R7 is negative R7ZERO R7 is zero The low byte of R7 is tested If itis negative continue at R7NEG if it is positive but not zero continue at R7POS TST B R7 Test low byte of R7 JN R7NEG Low byte of R7 is negative JZ R7ZERO Low byte of R7 is zero R7POS J Low byte of R7 is positive but not zero R7NEG Low byte of R7 is negative R7ZERO Low byte of R7 is zero 3 70 RISC 16 Bit CPU XOR W XOR B Syntax Operation Description Status Bits Mode Bits Example Example Example Instruction Set Exclusive OR of source with destination Exclusive OR of source with destination XOR src dst or XOR W src dst XOR B src dst src XOR dst dst The source and destination operands are exclusive ORed The result is placed into the destination The source operand is not affected N Set if result MSB is set reset if not set Z Set if result is zero reset otherwise C Set if re
96. ro 7 6 5 4 3 2 1 0 ONFETCH ROBIN ro ro ro ro rw 0 rw 0 rw 0 Reserved Bits Reserved Read only Always read as 0 15 3 DMA Bit 2 DMA on fetch ONFETCH 0 The DMA transfer occurs immediately 1 The DMA transfer occurs on next instruction fetch after the trigger ROUND Bit 1 Round robin This bit enables the round robin DMA channel priorities ROBIN DMA channel priority is DMA1 DMA2 1 DMA channel priority changes with each transfer ENNMI Bit 0 Enable NMI This bit enables the interruption of a DMA transfer by an NMI interrupt When NMI interrupts a DMA transfer the current transfer is completed normally further transfers are stopped and DMAABORT is set 0 NMI interrupt does not interrupt DMA transfer 1 NMI interrupt interrupts a DMA transfer 8 16 DMA Controller DMA Registers DMAxCTL DMA Channel x Control Register 15 Reserved rw 0 rw Reserved DMADTx DMA DSTINCRx DMA SRCINCRx DMA DSTBYTE 14 13 12 11 10 9 8 DMADTx DMADSTINCRx DMASRCINCRx rw 0 7 6 5 4 3 2 1 0 DMA DMA DMA 0 rw 0 0 0 0 Bit 15 Bits 14 12 Bits 11 10 Bits 9 8 Bit 7 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw rw 0 rw 0 rw 0 rw rw Reserved DMA Transfer mode 000 Single transfer 001 Block transfer 010 Burst block transfer 011 Burst block transfer 100 Repeated single transfer 101 Repeated block transfer 110 Repeated burst block transfer 111 Repea
97. single channel mode and then reset ENC ss 17 2 7 Using ADC12 with the DMA Controller MSP430 devices with an integrated DMA controller can automatically move data from any ADC12MEM x register to another location DMA transfers are done without CPU intervention and independently of any low power modes The DMA controller increases throughput of the ADC12 module and enhances low power applications allowing the CPU to remain off while data transfers occur DMA transfers can be triggered from any ADC12IF Gx flag When CONSEQx 0 2 the ADC12IFGx flag for the ADC12MEMXx used for the conversion can trigger a DMA transfer When CONSEQx 1 3 the ADC12IF Gx flag for the last ADC12MEMx in the sequence can trigger a DMA transfer Any ADC12IFGx flag is automatically cleared when the DMA controller accesses the corresponding ADC12MEMXx See the DMA Controller chapter ADC12 17 15 ADC12 Operation 17 2 8 Using the Integrated Temperature Sensor To use the on chip temperature sensor the user selects the analog input channel INCHx 1010 Any other configuration is done as if an external channel was selected including reference selection conversion memory selection etc The typical temperature sensor transfer function is shown in Figure 17 10 When using the temperature sensor the sample period must be greater than 30 us The temperature sensor offset error can be large and may need to be calibrated for most applications See device sp
98. solution Flash Memory Controller 5 15 Flash Memory Operation Programming Flash Memory via JTAG MSP430 devices can be programmed via the JTAG port The JTAG interface requires four signals 5 signals on 20 and 28 pin devices ground and optionally Voc and RST NMI The JTAG port is protected with a fuse Blowing the fuse completely disables the JTAG port and is not reversible Further access to the device via JTAG is not possible For more details see the Application report Programming a Flash Based MSP430 Using the JTAG Interface at www ti com sc msp430 Programming Flash Memory via the Bootstrap loader BSL Every MSP430 flash device contains a bootstrap loader The BSL enables users to read or program the flash memory or RAM using a UART serial interface Access to the MSP430 flash memory via the BSL is protected by a 256 bit user defined password For more details see the Application report Features of the MSP430 Bootstrap Loader at www ti com sc msp430 Programming Flash Memory via a Custom Solution The ability of the MSP430 CPU to write to its own flash memory allows for in system and external custom programming solutions as shown in Figure 5 13 The user can choose to provide data to the MSP430 through any means available UART SPI etc User developed software can receive the data and program the flash memory Since this type of solution is developed by the user it can be completely customized to fit the application needs
99. specific datasheet for parameters Figure 13 12 Glitch Suppression USART Receive Not Started URXDx URXS LE A When a glitch is longer than t or a valid start bit occurs on URXDx the USART receive operation is started and a majority vote is taken as shown in Figure 13 13 If the majority vote fails to detect a start bit the USART halts character reception If character reception is halted an active BRCLK is not necessary A time out period longer than the character receive duration can be used by software to indicate that a character was not received in the expected time and the software can disable BRCLK Figure 13 13 Glitch Suppression USART Activated Majority Vote Taken 13 20 USART Peripheral Interface UART Mode USART Registers UART Mode 13 3 USART Registers UART Mode Table 13 3 lists the registers for all devices implementing a USART module Table 13 4 applies only to devices with a second USART module USART1 Table 13 3 SARTO Control and Status Registers Register Short Form Register Type Address Initial State USART control register UOCTL Read write 070h 001h after PUC Transmit control register UOTCTL Read write 071h 001h after PUC Receive control register UORCTL Read write 072h 000h after PUC Modulation control register UOMCTL Read write 073h Unchanged Baud rate control register 0 UOBRO Read write 074h Unchanged Baud rate control register 1 UOBR1 Read write 075h Unchanged Receive buf
100. the analog to digital conversion which requires 13 ADC12CLK cycles Two different sample timing methods are defined by control bit SHP extended sample mode and pulse mode Extended Sample Mode The extended sample mode is selected when SHP 0 The SHI signal directly controls SAMPCON and defines the length of the sample period tsample When SAMPCON is high sampling is active The high to low SAMPCON transition starts the conversion after synchronization with ADC12CLK See Figure 17 3 Figure 17 3 Extended Sample Mode Start Stop Start Conversion Sampling Sampling Conversion Complete e 5 SAMPCON 13 x ADC12CLK sample gt 4 teonvert synci ADC12 17 7 ADC12 Operation Pulse Sample Mode The pulse sample mode is selected when SHP 1 The SHI signal is used to trigger the sampling timer The SHTOx and SHT 1x bits in ADC12CTLO control the interval of the sampling timer that defines the SAMPCON sample period tsample The sampling timer keeps SAMPCON high after synchronization with AD12CLK for a programmedintervaltsampje The total sampling time is tsample plus tsync See Figure 17 4 The SHTx bits select the sampling time in 4x multiples of ADC12CLK SHTOx selects the sampling time for ADC12MCTLO to 7 and SHT1x selects the sampling time for ADC12MCTL8 to 15 Figure 17 4 Pulse Sample Mode 17 8 Start Stop Start Conversion Sampling Sampling Conversion Complete
101. the charge redistribution method When the inputs are internally switched the switching action may cause transients on the input signal These transients decay and settle before causing errant conversion Figure 17 2 Analog Multiplexer R 100 Ohm ADC12MCTLx 0 3 e m i ESD Protection Analog Port Selection The ADC12 inputs are multiplexed with the port P6 pins which are digital CMOS gates When analog signals are applied to digital CMOS gates parasitic current can flow from Voc to GND This parasitic current occurs if the input voltage is near the transition level of the gate Disabling the port pin buffer eliminates the parasitic current flow and therefore reduces overall current consumption The P6SELx bits provide the ability to disable the port pin input buffer P6 0 and P6 1 configured for analog input BIS B 3h amp P6SEL P6 1 and P6 0 ADC12 function BIC B 3h amp P6DIR P6 1 and P6 0 input direction ADC12 17 5 ADC12 Operation 17 2 3 Voltage Reference Generator 17 6 ADC12 The ADC12 module contains a built in voltage reference with two selectable voltage levels 1 5 V and 2 5 V Either of these reference voltages may be used internally and externally on pin VREF Setting REFON 1 enables the internal reference When REF2 5V 1 the internal reference is 2 5 V the reference is 1 5 V when REF2 5V 0 The reference can be turned off to save power when not in use For proper opera
102. the clocks from the different masters must be synchronized A device that first generates a low period on SCL overrules the other devices forcing them to start their own low periods SCL is then held low by the device with the longest low period The other devices must wait for SCL to be released before starting their high periods Figure 15 15 illustrates the clock synchronization A slow slave may pull SCL low to slow down a fast master When this occurs all other devices must enter the wait state This allows a slow slave to slow down a fast master Figure 15 15 Synchronization of Two 2C Clock Generators During Arbitration 15 16 SCL From Device 1 SCL From Device 2 Bus Line SCL Wait K Start HIGH State Period USART Peripheral Interface 12C Mode 12C Module Operation 15 2 7 Using the I2C Module with Low Power Modes The 12 module can be used with MSP430 low power modes When the internal clock source for the I2C module is present the module operates normally regardless of the MSP430 operating mode When in slave mode and when the internal clock source is not present the I2C module can provide automatic start bit detection to wake the CPU To enable this feature the STTIE and GIE bits mustbe setto enable the STTIFG flag to interrupt the CPU When the 12C module detects a start condition the STTIFG flag is set and the module holds the SCL line low halting further bus activity The interrupt servi
103. timer continues its descent until it reaches zero The new period takes effect after the counter counts down to zero If the timer is counting in the up direction when the new period is latched into TBCLO and the new period is greater than or equal to the old period or greater than the current count value the timer counts up to the new period before counting down When the timer is counting in the up direction and the new period is less than the current count value when TBCLO is loaded the timer begins counting down However one additional count may occur before the counter begins counting down Mode The up down mode supports applications that require dead times between output signals see section Timer B Output Unit For example to avoid overload conditions two outputs driving an H bridge must never be in a high state simultaneously In the example shown in Figure 12 9 the tgeag is tdead ttimer x TBCL1 TBCL3 With tgeaq Time during which both outputs need to be inactive ttimer Cycle time of the timer clock TBCLx Content of compare latch x The ability to simultaneously load grouped compare latches assures the dead times Figure 12 9 Output Unit in Up Down Mode 12 10 TBR max TBCLO TBCL1 TBCL3 Oh TBIFG Timer_B Dead Time Output Mode 6 Toggle Set Output Mode 2 Toggle Reset EQU1 EQUT EQUI Interrupt Events EQUO EQUO EQUS EQU3 E
104. to the previous operating mode if the saved SR value is not altered during the interrupt service routine Program flow can be returned to a different operating mode by manipulating the saved SR value on the stack inside of the interrupt service routine The mode control bits and the stack can be accessed with any instruction When setting any of the mode control bits the selected operating mode takes effect immediately Peripherals operating with any disabled clock are disabled until the clock becomes active The peripherals may also be disabled with their individual control register settings All port pins and RAM registers unchanged Wake up is possible through all enabled interrupts 2 14 System Resets Interrupts and Operating Modes Operating Modes Figure 2 10 MSP430x1xx Operating Modes For Basic Clock System RST NMI Reset Active WDT Active Time Expired Overflow WDTIFG 0 WDTIFG 1 RST NMI is Reset Pin WDTIFG 1 WDT is Active RST NMI NMI Active WDT Active Security Key Violation Active Mode CPUOFF 1 CPU Is Active CPUOFF 1 SCGO 0 Peripheral Modules Are Active OSCOFF 1 SCG1 0 SCGO 1 SCG1 1 LPMO CPU Off MCLK Off SMCLK ACLK On LPM4 CPU Off MCLK Off DCO Off ACLK Off CPUOFF 1 SCGO 1 SCG1 0 D ff CPUOFF 1 C Generator O CPUOFF 1 SCGO 1 SCG0 0 SCG1 1 SCG1 1 LPM3 C
105. transfer the DTC requires one or two MCLK clock cycles to synchronize one for the actual transfer while the CPU is halted and one cycle of wait time Because the DTC uses MCLK the DTC cycle time is dependent on the MSP430 operating mode and clock system setup If the MCLK source is active but the CPU is off the DTC uses the MCLK source for each transfer without re enabling the CPU If the MCLK source is off the DTC temporarily restarts MCLK sourced with DCOCLK only during a transfer The CPU remains off and after the DTC transfer MCLK is again turned off The maximum DTC cycle time for all operating modes is show in Table 18 2 Table 18 2 Maximum DTC Cycle Time 18 20 ADC10 CPU Operating Mode Clock Source Maximum DTC Cycle Time _ Active mode MCLK DCOCLK 3 MCLK cycles Active mode MCLK LFXT1CLK 3 MCLK cycles Low power mode LPMO0 1 MCLK DCOCLK 4 MCLK cycles Low power mode LPM3 4 MCLK DCOCLK 4 MCLK cycles 6 ust Low power mode LPMO 1 MCLK LFXT1CLK 4 MCLK cycles Low power mode LPM3 MCLK LFXT1CLK 4 MCLK cycles Low power mode LPM4 MCLK LFXT1CLK 4 MCLK cycles 6 ust t The additional 6 us are needed to start the DCOCLK It isthe t _PMx parameter in the data sheet ADC10 Operation 18 2 7 Using the Integrated Temperature Sensor To use the on chip temperature sensor the user selects the analog input channel INCHx 1010 Any other configuration is done as if an external channel was selected including reference sel
106. write 0132h Unchanged Operand one multiply accumulate MAC Read write 0134h Unchanged Operand one signed multiply accumulate MACS Read write 0136h Unchanged Operand two OP2 Read write 0138h Unchanged Result low word RESLO Read write 013Ah Undefined Result high word RESHI Read write 013Ch Undefined Sum Extension register SUMEXT Read 013Eh Undefined Hardware Multiplier 7 7 7 8 Hardware Multiplier Chapter 8 DMA Controller The DMA controller module transfers data from one address to another without CPU intervention This chapter describes the operation of the DMA controller The DMA controller is implemented in MSP430x15x and MSP430x16x devices Topic Page SG ESDMA Introductions etre e nre eer ete epe enr II 8 2 8 2 TDMA Operati M 8 4 8 3 TDMA Registers 8 12 8 1 DMA Introduction 8 1 DMA Introduction The direct memory access DMA controller transfers data from one address to another without CPU intervention across the entire address range For example the DMA controller can move data from the ADC12 conversion memory to RAM Using the DMA controller can increase the throughput of peripheral modules It can also reduce system power consumption by allowing the CPU to remain in a low power mode without having to awaken to move data to or from a peripheral The DMA controller features include Three independent transfer channels Configurable DMA channel priorities Requir
107. 0 The ADC10 internal voltage reference generator is designed for low power applications with specific features for a fast startup For proper operation an external storage capacitance is not required and has no associated bias time The total reference turn on time is less than 30 us Normal power supply decoupling across Vcc and Vss using a parallel combination of 10 uF and 100 nF capacitors are all that is required L When using Vcc and Vss as reference voltages the internal reference should be powered off completely with REFON 0 When using an external reference the internal reference should be powered off completely External references may be supplied for VR and Vp through pins A4 and respectively J When the internal reference is used and the maximum conversion rate is below 50 ksps setting ADC10SR 1 reduces the current consumption of the internal reference buffer approximately 50 When both REFOUT 1 and REFBURST 1 the reference is present externally only during the sample and conversion period When REFOUT 1 and REFBURST 0 is cleared the reference voltage is continuously present externally ADC10 Operation 18 2 4 Sample and Conversion Timing An analog to digital conversion is initiated with a rising edge of sample input signal SHI The source for SHI is selected with the SHSx bits and includes the following The ADC10SC bit The Timer A Output Unit 1 The Timer A Output Unit 0
108. 0 rw 0 rw 0 rw 0 rw 0 I2CSAx Bits 12 slave address The I2CSA register contains the slave address of the 15 0 external device to be addressed by the MSP430 It is only used in master mode The I2CSA register is right justified Bit 6 is the MSB Bits 15 7 are always 0 I2CSA I C Slave Address Register 10 Bit Addressing Mode rw 0 ee rw 0 rw 0 rw 0 rw 0 rw 0 I2CSAx Bits I2C slave address The 2CSA register contains the slave address of the 15 0 external device to be addressed by the MSP430 It is only used in master mode The I2CSA register is right justified Bit 9 is the MSB Bits 15 10 are always 0 USART Peripheral Interface I C Mode 15 29 I C Module Registers I2CIE 12 Interrupt Enable Register STTIE GCIE TXRDYIE RXRDYIE ARDYIE ALIE rw 0 rw 0 rw 0 rw 0 rw 0 STTIE Bit 7 Start detect interrupt enable 0 Interrupt enabled 1 Interrupt disabled GCIE Bit 6 General call interrupt enable 0 Interrupt enabled 1 Interrupt disabled TXRDYIE Bit 5 Transmit ready interrupt enable TXRDYIE is automatically cleared when TXDMAEN 1 0 Interrupt enabled 1 Interrupt disabled RXRDYIE Bit 4 Receive ready interrupt enable RXRDYIE is automatically cleared when RXDMAEN 1 0 Interrupt enabled 1 Interrupt disabled ARDYIE Bit 3 Access ready interrupt enable 0 Interrupt enabled 1 Interrupt disabled OAIE Bit 2 Own address interrupt enable 0 Interrupt enabled 1 Interrupt disabled NACKIE Bit 1
109. 0194h Reset with POR Timer B capture compare control 2 TBCCTL2 Read write 0186h Reset with POR Timer capture compare 2 TBCCR2 Read write 0196h Reset with POR Timer B capture compare control TBCCTL3 Read write 0188h Reset with POR Timer_B capture compare 3 TBCCR3 Read write 0198h Reset with POR Timer_B capture compare control 4 TBCCTL4 Read write 018Ah Reset with POR Timer_B capture compare 4 TBCCR4 Read write 019Ah Reset with POR Timer_B capture compare control 5 TBCCTL5 Read write 018Ch Reset with POR Timer B capture compare 5 TBCCR5 Read write 019Ch Reset with POR Timer B capture compare control 6 TBCCTL6 Read write 018Eh Reset with POR Timer_B capture compare 6 TBCCR6 Read write 019Eh Reset with POR Timer_B Interrupt Vector TBIV Read only 011Eh Reset with POR 12 20 Timer_B Timer B Registers Timer B Control Register TBCTL 15 14 13 12 11 10 9 8 wee o omnem o ome m tosses rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 w 0 rw 0 rw 0 Unused Bit15 Unused TBCLGRP Bit TBCLx group 14 13 00 Each TBCLx latch loads independently 01 TBCL1 TBCL2 TBCCR1 CLLDXx bits control the update TBCL3 TBCL4 TBCCRS CLLDx bits control the update TBCL5 TBCL6 TBCCR5 CLLDx bits control the update TBCLO independent 10 TBCL1 TBCL2 TBCL3 TBCCR1 CLLDx bits control the update TBCL4 TBCL5 TBCL6 TBCCR4 CLLDx bits control the update TBCLO independent 11 TBCLO TBCL1 TBCL
110. 0DTC1 register to a nonzero value When the DTC is enabled each time the ADC10 completes a conversion and loads the result to ADC10MEM a data transfer is triggered No software intervention is required to manage the ADC10 until the predefined amount of conversion data has been transferred Each DTC transfer requires one CPU MCLK To avoid any bus contention during the DTC transfer the CPU is halted if active for the one MCLK required for the transfer A DTC transfer must not be initiated while the ADC10 is busy Software must ensure that no active conversion or sequence is in progress when the DTC is configured ADC10 activity test BIC W ENC amp ADC1OCTLO busy test BIT W BUSY amp ADC1OCTLI1 JNZ busy test 7 OV W amp ADC10SA Safe OV B xx amp ADC1ODTC1 continue setup ADC10 18 15 ADC10 Operation One Block Transfer Mode The one block mode is selected if the ADC10TB is reset The value n in ADC10DTC1 defines the total number of transfers for a block The block start address is defined anywhere in the MSP430 address range using the 16 bit register ADC10SA The block ends at ADC10SA 2n 2 The one block transfer mode is shown in Figure 18 9 Figure 18 9 One Block Transfer 18 16 ADC10 TB 0 E sd n th transfer ADC10SA 2n 2 ADC10SA 2n 4 iN 2nd transfer ADC10SA 2 1st transfer ADC10SA The internal address pointer is initially equal to ADC10SA and the internal
111. 1 Timer A capture compare control 2 Timer A capture compare 2 Short Form TACTL TAR TACCTLO TACCRO TACCTL1 TACCR1 TACCTL2 TACCR2 TAIV Register Type Address Read write Read write Read write Read write Read write Read write Read write Read write 0160h 0170h 0162h 0172h 0164h 0174h 0166h 0176h 012Eh Timer_A Registers Initial State Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Timer_A Interrupt Vector Read only Timer_A 11 19 Timer A Registers TACTL Timer A Control Register 15 14 13 12 11 10 9 8 om rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 oom o 9 rw 0 rw 0 rw 0 rw 0 rw 0 w 0 rw 0 rw 0 Unused Bits Unused 15 10 TASSELx Bits Timer A clock source select 9 8 00 TACLK 01 10 SMCLK 11 INCLK IDx Bits Input divider These bits select the divider for the input clock 7 6 00 A 01 2 10 4 11 8 MCx Bits Mode control Setting MCx 00h when Timer A is not in use conserves 5 4 power 00 Stop mode the timer is halted 01 Up mode the timer counts up to TACCRO 10 Continuous mode the timer counts up to OFFFFh 11 Up down mode the timer counts up to TACCRO then down to 0000h Unused Bit 3 Unused TACLR Bit 2 Timer A clear Setting this bit resets TAR IDx and count direction The TACLR bit is automatically reset and is always read as zero
112. 10 10 Watchdog Timer Chapter 11 Timer A Timer A is a 16 bit timer counter with three capture compare registers This chapter describes Timer A Timer A is implemented in all MSP430x1xx devices Topic Page disi TimerzA Introd ction 11 2 11 2 mimer A Operatiom 3 11 4 11 3 primer A Registers 11 19 Timer A Introduction 11 1 Timer A Introduction 11 2 Timer A Timer A is a 16 bit timer counter with three capture compare registers Timer A can support multiple capture compares PWM outputs and interval timing Timer A also has extensive interrupt capabilities Interrupts may be generated from the counter on overflow conditions and from each of the capture compare registers Timer A features include Asynchronous 16 bit timer counter with four operating modes Selectable and configurable clock source Three configurable capture compare registers Configurable outputs with PWM capability Asynchronous input and output latching DL D DLUD LU Interrupt vector register for fast decoding of all Timer A interrupts The block diagram of Timer A is shown in Figure 11 1 Note Use of the Word Count Count is used throughout this chapter It means the counter must be in the process of counting for the action to take place If a particular value is directly written to the counter then an associated action will not take place LLLLLSSS
113. 12C communication in USARTO modules on the MSP430x15x and MSP430x16x devices This chapter describes the 12C mode Topic Page 15 1 12C Module Introduction 15 2 15 2 I2C Module Operation E A 15 4 15 3 I2C Module Registers r a 15 21 15 1 12C Module Introduction 15 1 12C Module Introduction The inter IC control 12C module provides an interface between the MSP430 and I2C compatible devices connected by way of the two wire 12C serial bus External components attached to the 12C bus serially transmit and or receive serial date to from the USART through the 2 wire 12C interface The 12C module has the following features Compliance to the Philips Semiconductor 12C specification v2 1 Bit Byte format transfer 7 bit and 10 bit device addressing modes General call Start restart stop Multi master transmitter slave receiver mode Multi master receiver slave transmitter mode Combined master transmit receive and receive transmit mode Standard mode up to100 kbps and fast mode up to 400 kbps support Built in FIFO for buffered read and write Programmable clock generation 16 bit wide data access to maximize bus throughput Designed for low power Two DMA triggers Extensive interrupt capability Db oo Implemented on USARTO only The 12C block diagram is shown in Figure 15 1 15 2 USART Peripheral Interface 12C Mode 12C Module Introduction
114. 1TXBUF Read write 07Fh Unchanged SFR module enable register 2 ME2 Read write 005h 000h after PUC SFR interrupt enable register 2 IE2 Read write 001h 000h after PUC SFR interrupt flag register 2 IFG2 Read write 003h 020h after PUC a aT Note Modifying the SFR bits To avoid modifying control bits for other modules it is recommended to set or clear the IEx and IFGx bits using BIS Bor BIC B instructions rather than MOV B Or CLR B instructions USART Peripheral Interface SPI Mode 14 13 USART Registers SPI Mode UxCTL USART Control Register 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 1 Unused Bits Unused 7 6 12 Bit 5 I2C mode enable This bit selects 12C or SPI operation when SYNC 1 0 SPI mode 1 12C mode CHAR Bit 4 Character length 0 7 bit data 1 8 bit data LISTEN Bit 3 Listen enable The LISTEN bit selects the loopback mode 0 Disabled 1 Enabled The transmit signal is internally fed back to the receiver SYNC Bit 2 Synchronous mode enable 0 UART mode 1 SPI mode MM Bit 1 Master mode 0 USART is slave 1 USART is master SWRST Bit 0 Software reset enable 0 Disabled USART reset released for operation 1 Enabled USART logic held in reset state t Applies to USARTO on MSP430x15x and MSP430x16x devices only 14 14 USART Peripheral Interface SPI Mode USART Registers SPI Mode UxTCTL USART Transmit Control Register 7 rw 0 CKPH CKPL SSELx Unused Unused STC TXEPT
115. 2 1 Non Maskable Interrupts NMI Reset NMI Pin Non maskable NMI interrupts are not masked by the general interrupt enable bit GIE but are enabled by individual interrupt enable bits ACCVIE NMIIE OFIE When a NMI interrupt is accepted all NMI interrupt enable bits are automatically reset Program execution begins at the address stored in the non maskable interrupt vector OFFFCh User software must set the required NMI interrupt enable bits for the interrupt to be re enabled The block diagram for NMI sources is shown in Figure 2 5 A non maskable NMI interrupt can be generated by three sources An edge on the RST NMI pin An oscillator fault occurs Lj An access violation to the flash memory At power up the RST NMI pin is configured in the reset mode The function of the RST NMI pins is selected in the watchdog control register WDTCTL If the RST NMI pin is set to the reset function the CPU is held in the reset state as long as the RST NMI pin is held low After the input changes to a high state the CPU starts program execution at the word address stored in the reset vector OFFFEh If the RST NMI pin is configured by user software to the NMI function a signal edge selected by the NMIES bit generates an NMI interrupt if the NMIIE bit is set The RST NMI flag NMIFG is also set Wy Ee d Note Holding RST NMI Low When configured in the NMI mode a signal generating an NMI event should not hold the
116. 2 TBCL3 TBCL4 TBCL5 TBCL6 TBCCR1 CLLDx bits control the update CNTLx Bits Counter Length 12 11 00 16 bit TBR may OFFFFh 01 12 bit TBR may OFFFh 10 10 bit TBR max O3FFh 11 8 bit TBR max OFFh Unused Bit 10 Unused TBSSELx Bits Timer B clock source select 9 8 00 TBCLK 01 ACLK 10 SMCLK 11 INCLK IDx Bits Input divider These bits select the divider for the input clock 7 6 00 01 72 10 4 11 4 8 MCx Bits Mode control Setting MCx 00h when Timer B is not in use conserves 5 4 power 00 Stop mode the timer is halted 01 Up mode the timer counts up to TBCLO 10 Continuous mode the timer counts up to the value set by TBCNTLx 11 Up down mode the timer counts up to TBCLO and down to 0000h Timer B 12 21 Timer B Registers Unused Bit 3 Unused TBCLR Bit 2 Timer B clear Setting this bit resets TBR IDx and count direction The TBCLR bit is automatically reset and is always read as zero TBIE Bit 1 Timer B interrupt enable This bit enables the TBIFG interrupt request 0 Interrupt disabled 1 Interrupt enabled TBIFG Bit 0 Timer_B interrupt flag 0 No interrupt pending 1 Interrupt pending TBR Timer_B Register 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 TBRx Bits Timer B register The TBR register is the count of Timer B 15 0 12 22 Timer B Timer B Registers TBCCTLx Capture Compare Contr
117. 28 2 19 4 19 3 12 Registers oreeson aanne a aee e a 19 10 19 1 DAC12 Introduction 19 1 DAC12 Introduction 19 2 DAC12 The DAC12 module is a 12 bit R ladder voltage output DAC The DAC12 can be configured in 8 or 12 bit mode and may be used in conjunction with the DMA controller When multiple DAC12 modules are present they may be grouped together for synchronous update operation Features of the DAC12 include 12 bit monotonic output 8 or 12 bit voltage output resolution Programmable settling time vs power consumption Internal or external reference selection Straight binary or 2 s compliment data format Self calibration option for offset correction Synchronized update capability for multiple DAC 12s DL L LI LDLLBuLn Multiple DAC12 modules can be grouped for simultaneous update Note Multiple DAC12 Modules Some devices may integrate more than one DAC12 module In the case where more than one DAC12 is present on a device the multiple DAC12 modules operate identically Throughout this chapter nomenclature appears such as DAC12 xDAT or DAC12 xCTL to describe register names When this occurs the x is used to indicate which DAC12 module is being discussed In cases where operation is identical the register is simply referred to as DAC12 xCTL The block diagram of the two DAC12 modules in the MSP430F15x 16x devices is shown in Figure 19 1 DAC12 Introductio
118. 2MEM5 interrupt flag ADC12MEM6 interrupt flag ADC12MEWM interrupt flag ADC12MEMS8 interrupt flag ADC12MENO interrupt flag ADC12MEM10 interrupt flag ADC12MEM11 interrupt flag ADC12MEM12 interrupt flag ADC12MEM 13 interrupt flag ADC12MEM 14 interrupt flag ADC12MEM 15 interrupt flag 2 1 ADC12 Registers 15 14 13 12 11 10 9 8 ro ro ro ro ro 0 ro Interrupt Interrupt Flag Priority ADC12IFGO ADC12IFG1 ADC12IFG2 ADC12IFG3 ADC12IFG4 ADC12IFG5 ADC12IFG6 ADC12IFG7 ADC12IFG8 ADC12IFG9 ADC12IFG10 ADC12IFG11 ADC12IFG12 ADC12IFG13 ADC12IFG14 ADC12IFG15 ADC12 Highest Lowest 17 27 17 28 ADC12 Chapter 18 ADC10 The ADC10 module is a high performance 10 bit analog to digital converter This chapter describes the ADC10 The ADC10 is implemented in the MSP430x11x2 MSP430x12x2 devices Topic Page 18 1 C ADG 10 Introduction eS eyes eee sieie Sse 18 2 18 227 ADG10 Operationy 18 4 18 3 ADC10 Registers 57 95 e TEE 18 24 18 1 ADC10 Introduction 18 1 ADC10 Introduction 18 2 ADC10 The ADC10 module supports fast 10 bit analog to digital conversions The module implements a 10 bit SAR core sample select control reference generator and data transfer controller DTC The DTC allows ADC10 samples to be converted and stored anywhere in memory without CPU intervention The module can be configured with user software to support a var
119. 2h R6 0108Ch OFF14h 00002h R6 0108Ch OFF12h 04596h PC OFF12h 04596h 0108Ch 01094h 0006h 01094 01092h 05555h 01092h oiooon 01234h 01080h 01082h 01082h 01080h 01082h 01234h RISC 16 Bit CPU 3 11 Addressing Modes 3 3 8 Symbolic Mode The symbolic mode is described in Table 3 6 Table 3 6 Symbolic Mode Description Assembler Code Content of ROM MOV EDE TONI MOV X PC Y PC X EDE PC Y 2 TONI PC Length Two or three words Operation Move the contents of the source address EDE contents of PC X to the destination address TONI contents of PC Y The words after the instruction contain the differences between the PC and the source or destination addresses The assembler computes and inserts offsets X and Y automatically With symbolic mode the program counter PC is incremented automatically so that program execution continues with the next instruction Comment Valid for source and destination Example MOV EDE TONI Source address EDE OF016h Dest address TONI 01114h Before After Address Register Address Register Space Space Oxxxxh PC OFF16h O11FEh OFF16h 011FEh OFF14h OF102h OFF14h OF102h OFF12h 04090h PC OFF12h 04090h OFF14h OF018h 0F102h OF018h oFo16h OA123h OF016h gFo16h QA123h OFF16h 1114h 01114h 05555h 0 01114h 0A123h 3 12 RISC 16 Bit CPU Addressing Modes 3 3 4 Absolute Mode
120. 3 10 Figure 13 10 Transmit Interrupt Operation UTXIEx PUC or SWRST Interrupt Service Requested x SWRST Character Moved From Buffer to Shift Register Data written to UXTXBUF IRQA USART Peripheral Interface UART Mode 13 17 USART Operation UART Mode USART Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loaded into UXRXBUF An interrupt request is generated if URXIEx and GIE are also set URXIFGx and URXIEx are reset by a system reset PUC signal or when SWRST 1 URXIFGx is automatically reset if the pending interrupt is served when URXSE 0 or when UxRXBUF is read The operation is shown in Figure 13 11 Figure 13 11 Receive Interrupt Operation From URXD Erroneous Character Rejection PE _ FE BRK RXEIE L URXWIE Fo 18 18 SYNC m Valid Start Bit Receiver Collects Character URXSE ipee URXIEx Interrupt Service a Requested URXIFGx m SWRST PUC UxRXBUF Read URXSE IRQA Character Received or Break Detected URXEIE is used to enable or disable erroneous characters from setting URXIFGx When using multiprocessor addressing modes URXWIE is used to auto detect valid address characters and reject unwanted data characters Two types of characters do not set URXIFGx Erroneous c
121. 4 ask star Return No interrupt ALIFG NACKIFG OAIFG ARDYIFG RXRDYTI FG TXRDYII GCIFG ts here ts here ts here ts here ts here ts here ts here ts here FG 15 3 12C Module Registers 12C Module Registers The 12C module registers and respective addresses are listed in Table 15 3 Table 15 3 12 Registers Register I2C interrupt enable I2C interrupt flag 12C data count USART control I2C transfer control 12C data control 12C prescaler 2 SCL high 2 SCL low 2 data 12C own address 2 slave address I2C interrupt vector Short Form I2CIE I2CIFG I2CNDAT UOCTL I2CTCTL I2CDCTL I2CPSC I2CSCLH I2CSCLL I2CDR 2 I2CSA I2CIV Register Type Address Read write Read write Read write Read write Read write Read only Read write Read write Read write Read write Read write Read write Read only 050h 051h 052h 070h 071h 072h 073h 074h 075h 076h 0118h 011Ah 011Ch Initial State Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC USART Peripheral Interface I C Mode 15 21 I C Module Registers UOCTL USARTO Control Register I2C Mode 7 rw 0 RXDMAEN TXDMAEN 12C XA LISTEN SYNC MST I2CEN 15 22 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 1 Bit 7
122. 8 4 8 2 2 DMA Transfer Modes 0 cee eect nn 8 6 8 2 3 Initiating DMA lt 8 9 8 24 Stopping DMA Transfers 0 6 aasan eaaa 8 10 8 25 Channel Priorities 8 10 8 26 DMA Transfer Cycle Time 8 11 8 27 Using DMA with System 1 1 8 11 8 28 DMA 8 11 8 32 DMA Regale gf IEEE Segen 8 12 9 Digital l O Poa ar na oe 9 1 9 1 Digital I O Introduction a E Im 9 2 9 2 Digital O Operation teen II 9 3 9 2 1 Input Register PnIN ce isea a a E III III 9 3 9 2 2 Output Registers PROUT 0 0 ccc seh 9 3 9 2 3 Direction Registers PnDIR 0 2 ett 9 3 9 2 4 Function Select Registers _ 9 4 9 255 P1andP2 Interrupts cette eee 9 5 9 2 6 Configuring Unused Port Pins 9 6 9 3 Digital lO Registers ba SX ue ee 9 7 Contents 10 Watchdog Timer 223 0 226635 Sia illus le lu euin tial eas eae ERR 10 1 10 1 Watchdog Timer Introduction
123. A Operation 8 2 4 Stopping DMA Transfers There are two ways to stop DMA transfers in progress L Asingle block or burst block DMA transfer may be stopped with an NMI interrupt if the ENNMI bit is set in register DMACTL1 Lj Aburst block transfer may be stopped by clearing the DMAEN bit 8 2 5 DMA Channel Priorities The default DMA channel priorities are DMA0 DMA1 DMA2 If two or three DMA triggers happen simultaneously or are pending the channel with the highest priority completes its DMA transfer single block or burst block transfer first then the second priority channel then the third priority channel DMA transfers in progress are not halted if a higher priority DMA channel is triggered The higher priority channel waits until the DMA transfer in progress completes before starting The DMA channel priorities are configurable with the ROUNDROBIN bit When the ROUNDROBIN bitis set the channel that completes a DMA transfer becomes the lowest priority The order of the priority of the DMA channels always stays the same DMAO DMA1 DMAQ for example DMA Priority Transfer Occurs New DMA Priority DMAO DMA1 DMA2 DMA1 DMA2 DMAO DMA1 DMA2 DMAO DMA1 DMA2 DMAO DMA1 DMA2 DMAO DMA1 DMA2 DMAO DMA1 DMA2 DMAO When the ROUNDROBIN bit is cleared the DMA priority returns to the default priority DMA Controller 8 11 DMA Operation 8 2 6 DMA Transfer Cycle Time The DMA requires one or two MCL
124. A0h Reset with POR ADC12 control register 1 ADC12CTL1 Read write 01A2h Reset with POR ADC12 interrupt flag register ADC12IFG Read write 01A4h Reset with POR ADC12 interrupt enable register ADC12IE Read write 01A6h Reset with POR ADC12 interrupt vector word ADC12IV Read 01A8h Reset with POR ADC12 memory 0 ADC12MEMO Read write 0140h Unchanged ADC12 memory 1 ADC12MEM 1 Read write 0142h Unchanged ADC12 memory 2 ADC12MEM2 Read write 0144h Unchanged ADC12 memory 3 ADC12MEM3 Read write 0146h Unchanged ADC12 memory 4 ADC12MEM4 Read write 0148h Unchanged ADC12 memory 5 ADC12MEM5 Read write 014Ah Unchanged ADC12 memory 6 ADC12MEM6 Read write 014Ch Unchanged ADC12 memory 7 ADC12MEM7 Read write 014Eh Unchanged ADC12 memory 8 ADC12MEM8 Read write 0150h Unchanged ADC12 memory 9 ADC12MEM9 Read write 0152h Unchanged ADC12 memory 10 ADC12MEM10 Read write 0154h Unchanged ADC12 memory 11 ADC12MEM11 Read write 0156h Unchanged ADC12 memory 12 ADC12MEM12 Read write 0158h Unchanged ADC12 memory 13 ADC12MEM13 Read write 015Ah Unchanged ADC12 memory 14 ADC12MEM14 Read write 015Ch Unchanged ADC12 memory 15 ADC12MEM15 Read write 015Eh Unchanged ADC12 memory control 0 ADC12MCTLO Read write 080h Reset with POR ADC12 memory control 1 ADC12MCTL1 Read write 081h Reset with POR ADC12 memory control 2 ADC12MCTL2 Read write 082h Reset with POR ADC12 memory control 3 ADC12MCTL3 Read write 083h Reset with POR ADC12 memory control 4 ADC12MCTL4 Read write 084h Reset with POR ADC12 memory
125. ADC10AE Analog Input Enable Control Register 7 6 5 4 3 2 1 0 ADC10AE7 ADC10AE6 ADC10AE5 ADC10AE4 ADC10AE3 ADC10AE2 ADC10AE1 ADC10AEO 0 0 0 0 0 rw 0 0 rw 0 rw rw rw rw rw rw ADC10AEx Bits ADC10 analog enable 7 0 0 Analog input disabled 1 Analog input enabled 18 28 ADC10 ADC10 Registers ADC10MEM Conversion Memory Register Binary Format 15 14 13 12 11 10 9 8 ro ro ro ro ro ro r r 7 6 5 4 3 2 1 0 Conversion Results r r r r r r r r Conversion Bits The 10 bit conversion results are right justified straight binary format Bit 9 Results 15 0 is the MSB Bits 15 10 are always O ADC10MEM Conversion Memory Register 2s Complement Format 15 14 18 12 11 10 9 8 r r r r r r r r 7 6 5 4 3 2 1 0 r r ro ro ro ro ro ro Conversion Bits The 10 bit conversion results are left justified 2 s complement format Bit 15 Results 15 0 is the MSB Bits 5 0 are always O ADC10 18 29 ADC10 Registers ADC10DTCO Data Transfer Control Register 0 7 ro Reserved ADC10TB ADC10CT ADC10B1 ADC10 FETCH 18 30 6 3 2 1 0 ADC10 0 0 rw 0 0 ro Bits 7 4 Bit 3 Bit 2 Bit 1 Bit 0 ADC10 5 4 ro rw rw rw Reserved Always read as 0 ADC10 two block mode 0 One block transfer mode 1 Two block transfer mode ADC10 continuous transfer 0 Data transfer stops when one block one block mode or two blocks two block mode hav
126. AxSZ register is copied into a temporary register and decrements with every transfer When the DMAxSZ register decrements to zero it is reloaded from its temporary register and the corresponding DMAIFG flag is set 8 6 DMA Controller Block Transfers DMA Operation In block mode a transfer of a complete block of data occurs after just one trigger Setting DMADTx 1 configures block transfer mode When DMADTx 1 the DMAEN bit is cleared after the completion of the block transfer and must be set again before another block transfer can be triggered After a DMA block transfer has been triggered further trigger signals occurring during the block transfer are ignored Setting DMADTx 5 configures repeated block transfer mode When DMADTx 5 the DMAEN bit remains set after completion of the block transfer The next trigger after the completion of a repeated block transfer triggers another block transfer The DMAxSZ register is used to define the size of the block and the DMADSTINCR and DMASRCINCR bits select if the DMA destination address DMAxDA and the DMA source address DMAxSA are incremented or decremented after each transfer of the block During a block or repeated block transfer the DMAxSA DMAxDA and DMAxSZ registers are copied into temporary registers The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block The DMAxSZ register is decremented after each transfer of the block a
127. B of the result reset otherwise V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected R5 and R6 are compared If they are equal the program continues at the label EQUAL CMP R5 R6 R5 R6 JEQ EQUAL YES JUMP Two RAM blocks are compared If they are not equal the program branches to the label ERROR MOV NUM R5 number of words to be compared L 1 amp BLOCK1 amp BLOCK2 Are Words equal JNZ ERROR No branch to ERROR DEC R5 Are all words compared JNZ L 1 No another compare The RAM bytes addressed by EDE and TONI are compared If they are equal the program continues at the label EQUAL CMP B EDE TONI JEQ EQUAL MEM EDE MEM TONI YES JUMP 3 34 RISC 16 Bit CPU DADC W DADC B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Instruction Set Add carry decimally to destination Add carry decimally to destination DADC dst or DADC W src dst DADC B dst dst C dst decimally DADD 0 dst DADD B 0 dst The carry bit C is added decimally to the destination N Set if MSB is 1 Z Set if dst is 0 reset otherwise C Set if destination increments from 9999 to 0000 reset otherwise Set if destination increments from 99 to 00 reset otherwise V Undefined OSCOFF CPUOFF and GIE are not affected The four digit decimal number contained in R5 is added to an eight digit deci
128. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 rw 0 rw 0 rw 0 rw Receive DMA enable This bit enables the DMA controller to be used to transfer data from the 12C module after the 12C modules receives data When RXDMAEN 1 RXRDYIE is automatically cleared 0 Disabled 1 Enabled Transmit DMA enable This bit enables the DMA controller to be used to provide data to the 12C module for transmission When TXDMAEN 1 TXRDYIE is automatically cleared 0 Disabled 1 Enabled 12C mode enable This bit select 12C or SPI operation when SYNC 1 0 SPI mode 1 12C mode Extended Addressing 0 7 bit addressing 1 10 bit addressing Listen This bit selects loopback mode LISTEN is only valid when MST 1 and I2CTRX 1 master transmitter 0 Normal mode 1 SDA is internally fed back to the receiver loopback Synchronous mode enable 0 UART mode 1 SPlor l2C mode Master This bit selects master or slave mode The MST bit is automatically cleared when arbitration is lost 0 Slave mode 1 Master mode 12 enable The bit enables or disables the 12C module The initial condition for this bit is set and SWRST function for UART or SPI When the I2C and SYNC bits are first set after a PUC this bit becomes I2CEN function and is automatically cleared 0 12 is disabled 1 12C operation is enabled USART Peripheral Interface 12C Mode 12C Module Registers I2CTCTL I2C Transmit Control Register
129. C10B1 SREF1 SREFO ADC100SC ADC10SSELx ADC10DIVx 00 Divider 01 ACLK h 8 10 MCLK 11 SMCLK ADC1OCLK SHSx ISSH ADC10SC TAI TAO TA2 RAM Flash Peripherials ee Halt CPU ADC10 18 3 ADC10 Operation 18 2 ADC10 Operation The ADC10 module is configured with user software The setup and operation of the ADC10 is discussed in the following sections 18 2 1 10 Bit ADC Core The ADC core converts an analog input to its 10 bit digital representation and stores the result in the ADC10MEM register The core uses two programmable selectable voltage levels Vp and Vp_ to define the upper and lower limits of the conversion The digital output NApc is full scale OSFFh when the input signal is equal to or higher than and zero when the input signal is equal to or lower than Vp The input channel and the reference voltage levels Vg and Vp are defined in the conversion control memory Conversion results may be in straight binary format or 2s complement format The conversion formula for the ADC result when using straight binary format is Vn N Vp Vin 1023 The ADC10 is configured by two control registers ADC10CTLO and ADC10CTL1 The core is enabled with the ADC10ON bit With few exceptions the ADC10 control bits can only be modified when ENC 0 ENC must be set to 1 before any conversion can take place Conversion Clock Selection 18 4 ADC10
130. CO Gen on SCGOm 1 on 0 off 4 6 Basic Clock Module Basic Clock Module Operation Adjusting the DCO frequency After a PUC the internal resistor is selected for the DC generator RSELx 4 and DCOx 3 allowing the DCO to start at a mid range frequency MCLK and SMCLK are sourced from DCOCLK Because the CPU executes code from MCLK which is sourced from the fast starting DCO code execution begins from PUC in less than 6 us The frequency of DCOCLK is set by the following functions Thecurrentinjected into the DC generator by either the internal or external resistor defines the fundamental frequency The DCOR bit selects the internal or external resistor Thethree RSELx bits select one of eight nominal frequency ranges for the DCO These ranges are defined for an individual device in the device specific data sheet The three DCOx bits divide the DCO range selected by the RSELx bits into 8 frequency steps separated by approximately 10 The five MODx bits switch between the frequency selected by the DCOx bits and the next higher frequency set by DCO 1 The DCOx and RSELx ranges and steps are shown in Figure 4 6 Figure 4 6 DCOx Range and RSELx Steps 10000 kHz RSEL 7 RSEL 6 RSEL 5 RSEL 4 1000 kHz RSEL 3 RSEL 2 RSEL 1 RSEL 0 100 kHz DCO 0 DCO 1 DCO 2 DCO 3 DCO 4 DCO 5 DCO 6 DCO 7 Basic Clock Module 4 7 Basic Clock Module Operation Using an External Resistor Rosc for the DCO
131. DC12IE13 ADC12IE12 ADC12IE11 ADC12IE10 ADC12IFG9 ADC12IE8 rw 0 rw 0 rw 0 rw 0 rw 0 w 0 ADC12IE7 ADC12IE6G ADC12IE5 ADC12IEA ADC12IE3 ADC12IE2 ADC12IE1 ADC12IEO rw 0 rw 0 rw 0 n w 0 w 0 rw 0 ADC12IEx Bits Interrupt enable These bits enable or disable the interrupt request for the 15 0 ADC12IFGx bits 0 Interrupt disabled 1 Interrupt enabled ADC12IFG ADC12 Interrupt Flag Register ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 IFG15 IFG14 IFG13 IFG12 IFG11 IFG10 IFG9 IFG8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 IFG7 IFG6 IFG5 IFG4 IFG3 IFG2 IFG1 IFGO rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12IFGx Bits ADC12MEM x Interrupt flag These bits are set when corresponding 15 0 ADC12MEMx is loaded with a conversion result The ADC12IFGx bits are reset if the corresponding ADC12MEM x is accessed or may be reset with software 0 No interrupt pending 1 Interrupt pending 17 26 ADC12 ADC12IV ADC12 Interrupt Vector Register ro 7 ro ADC12IVx Bits 15 0 6 ro 5 4 3 ADC12 interrupt vector value ADC12IV Contents 000h 002h 004h 006h 008h 00Ah 00Ch OOEh 010h 012h 014h 016h 018h 01Ah 01Ch 01Eh 020h 022h 024h Interrupt Source No interrupt pending ADC12MEMXx overflow Conversion time overflow ADC12MEMO interrupt flag ADC12MEM1 interrupt flag ADC12MEN2 interrupt flag ADC12MEMs3 interrupt flag ADC12MEM4 interrupt flag ADC1
132. DC12MCTLx control register The SREFx bits define the voltage reference and the INCHx bits select the input channel The EOS bit defines the end of sequence when a sequential conversion mode is used A sequence rolls over from ADC12MEM15 to ADC12MEMO when the EOS bit in ADC12MCTL15 is not set The CSTARTADDx bits define the first ADC12MCTLx used for any conversion If the conversion mode is single channel or repeat single channel the CSTARTADDx points to the single ADC12MCTLx to be used If the conversion mode selected is either sequence of channels repeat sequence of channels CSTARTADDx points to the first ADC12MCTLx location to be used in a sequence A pointer not visible to software is incremented automatically to the next ADC12MCTLx in a sequence when each conversion completes The sequence continues until an EOS bit in ADC12MCTLx is processed this is the last control byte processed When conversion results are written to a selected ADC12MEMx the corresponding flag in the ADC12IFGx register is set 17 2 6 ADC12 Conversion Modes The ADC12 has four operating modes selected by the CONSEQx bits as discussed in Table 17 1 Table 17 1 Conversion Mode Summary 17 10 CONSEQx MODE OPERATION 00 Single channel A single channel is converted once single conversion 01 Sequence of A sequence of channels is converted once channels 10 Repeat single A single channel is converted repeatedly channel 11 Repeat sequence A s
133. E are not affected Figure 3 18 Destination Operand Byte Swap Example Example 15 8 7 6 MOV 040BFh R7 0100000010111111 R7 BN Bd 1011111101000000 in R7 The value in R5 is multiplied by 256 The result is stored in R5 R4 SWPB R5 MOV R5 R4 the swapped value to R4 BIC 0FFOOh R5 Correct the result BIC 00FFh R4 Correct the result 3 68 RISC 16 Bit CPU SXT Syntax Operation Description Status Bits Mode Bits Instruction Set Extend Sign SXT dst Bit 7 Bit 8 Bit 15 The sign of the low byte is extended into the high byte as shown in Figure 3 19 N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Setif result is not zero reset otherwise NOT Zero V Reset OSCOFF CPUOFF and GIE are not affected Figure 3 19 Destination Operand Sign Extension Example 15 8 7 0 R7 is loaded with the P1IN value The operation of the sign extend instruction expands bit 8 to bit 15 with the value of bit 7 R7 is then added to R6 MOV B amp P1IN R7 P1IN 080h 1000 0000 SXT R7 R7 OFF80h 1111 1111 1000 0000 RISC 16 Bit CPU 3 69 Instruction Set TST W TST B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Test destination Test destination TST dst or TST W dst TST B dst dst OFFFFh 1 dst OFFh 1 CMP 0 dst CMP B 0 dst The destination
134. ELx Reset Divider 1 64 Flash Timing Generator BUSY WAIT The flash timing generator can be sourced from ACLK SMCLK or MCLK The selected clock source should be divided using the FNx bits to meet the frequency requirements for f FTq If the fiera frequency deviates from the specification during the write or erase operation the result of the write or erase may be unpredictable or the flash memory may be stressed above the limits of reliable operation 5 4 Flash Memory Controller Flash Memory Operation 5 3 2 Erasing Flash Memory The erased level of a flash memory bit is 1 Each bit can be programmed from 1 to 0 individually but to reprogram from 0 to 1 requires an erase cycle The smallest amount of flash that can be erased is a segment There are three erase modes selected with the ERASE and MERAS bits listed in Table 5 1 Table 5 1 Erase Modes MERAS ERASE Erase Mode 0 1 Segment erase 1 0 Mass erase all main memory segments 1 1 Erase all flash memory main and information segments Any erase is initiated by a dummy write into the address range to be erased The dummy write starts the flash timing generator and the erase operation Figure 5 4 shows the erase cycle timing The BUSY bitis setimmediately after the dummy write and remains set throughout the erase cycle BUSY MERAS and ERASE are automatically cleared when the cycle completes The erase cycle timing is not dependent on the amount of flash memo
135. EQUI Interrupt Events EQUO EQUO EQU2 EQU2 EQU2 EQU2 Timer A Operation 11 2 4 Capture Compare Blocks Capture Mode Three identical capture compare blocks TACCRx are present in Timer A Any of the blocks may be used to capture the timer data or to generate time intervals The capture mode is selected when CAP 1 Capture mode is used to record time events It can be used for speed computations or time measurements Thecapture inputs CCIxA and CCIxB are connected to external pins or internal signals and are selected with the CCISx bits The CMx bits select the capture edge of the input signal as rising falling or both A capture occurs on the selected edge of the input signal If a capture occurs The timer value is copied into the TACCRx register The interrupt flag CCIFG is set The input signal level can be read at any time by via the CCI bit MSP430x1xx family devices may have different signals connected to CCIxA and CCIxB Refer to the device specific datasheet for the connections of these signals The capture signal can be asynchronous to the timer clock and cause a race condition Setting the SCS bit will synchronize the capture with the next timer clock Setting the SCS bitto synchronize the capture signal with the timer clock is recommended This is illustrated in Figure 11 10 Figure 11 10 Capture Signal SCS 1 CCI Capture Set TACCRx CCIFG l Overflow logic is provided in ea
136. Example Source AND destination Source AND destination AND src dst or AND W src dst AND B src dst src AND dst dst The source operand and the destination operand are logically ANDed The result is placed into the destination N Setif result MSB is set reset if not set Z Setif result is zero reset otherwise C Set if result is not zero reset otherwise NOT Zero V Reset OSCOFF CPUOFF and GIE are not affected The bits set in R5 are used as a mask OAA55h for the word addressed by TOM If the result is zero a branch is taken to label TONI MOV 0AA55h R5 Load mask into register R5 AND R5 TOM mask word addressed by TOM with R5 JZ TONI ae Result is not zero or AND 0AA55h TOM JZ TONI The bits of mask 40A5h are logically ANDed with the low byte TOM If the result is zero a branch is taken to label TONI AND B 0A5h TOM mask Lowbyte TOM with R5 JZ TONI Result is not zero 3 24 RISC 16 Bit CPU BIC W BIC B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Clear bits in destination Clear bits in destination BIC src dst or BIC W src dst BIC B src dst NOT src AND dst dst The inverted source operand and the destination operand are logically ANDed The result is placed into the destination The source operand is not affected Status bits are not affected OSCOFF CPUOFF and GIE are not affected The six
137. F and any applicable error bit is set When any of the FE PE OE BRK or RXERR bits is set the bit remains set until user software resets it or UXRXBUF is read 13 8 USART Peripheral Interface UART Mode USART Operation UART Mode 13 2 4 USART Receive Enable The receive enable bit URXEx enables or disables data reception on URXDx as shown in Figure 13 5 Disabling the USART receiver stops the receive operation following completion of any character currently being received or immediately if no receive operation is active The receive data buffer UxRXBUF contains the character moved from the RX shift register after the character is received Figure 13 5 State Diagram of Receiver Enable No Valid Start Bit Not Completed URXEx 1 Valid Start Bit Idle State Receiver Enabled Receiver Collects Character Receive Disable Handle Interrupt Conditions Character Received URXEx 0 Ca we ee ee ee SS pt et st An Note Re Enabling the Receiver Setting URXEx UART Mode When the receiver is disabled URXEx 0 re enabling the receiver URXEx 1 is asynchronous to any data stream that may be present on URXDx at the time Synchronization can be performed by testing for an idle line condition before receiving a valid character see URXWIE 0 USART Peripheral Interface UART Mode 13 9 USART Operation UART Mode 13 2 5 USART Transmit Enable When UT
138. I2C bit when SYNC 1 selects the I2C mode The SYNC I2C bits can be set together in a single instruction to select the 12C mode for USARTO After module initialization the 12C module is ready for transmit or receive operation Clearing I2CEN releases the I2C module for operation Note Re Configuring the 12C Module for UART or SPI operation The required USART re configuration process is 1 Clear the I2C bit BIC B I2C amp UOCTI 2 Clear UOCTL and set SWRST bit MOV B SWRST amp UOCTL 3 Initialize all USART registers with SWRST 1 including UxCTL 4 Enable USART module via the MEx SFRs URXEx and or UTXEx 5 Clear SWRST via software BIC B SWRST amp UxCTL 6 Enable interrupts optional via the IEx SFRs URXIEx and or UTXIEx Failure to follow this process may result in unpredictable USART behavior L a p COEREER IMa d Note Re Configuring the I2C Module for Different 12C Conditions The required 12C re configuration process is 1 Clear the I2CEN bit BIC B I2CEN amp UOCTL 2 Re configure the 12C module with 2 0 3 Set I2CEN via software BIS B 2 amp UOCTL Failure to follow this process may result in unpredictable USART behavior After a PUC the USART module is configured in the UART mode with SWRST 1 In I2C mode setting I2CEN 0 has the following effects I2C communication stops SDA and SCL are high impedance I2CTCTL bits 3 0 are cleare
139. K SP SR src TOS WDT Auxiliary Clock Analog to Digital Converter Brown Out Reset Bootstrap Loader Central Processing Unit Digital to Analog Converter Digitally Controlled Oscillator Destination Frequency Locked Loop General Interrupt Enable Integer portion of N 2 Input Output Interrupt Service Routine Least Significant Bit Least Significant Digit Low Power Mode Memory Address Bus Master Clock Memory Data Bus Most Significant Bit Most Significant Digit Non Maskable Interrupt Program Counter Power On Reset Power Up Clear Random Access Memory System Clock Generator Special Function Register Sub System Master Clock Stack Pointer Status Register Source Top of Stack Watchdog Timer See Basic Clock Module See System Resets Interrupts and Operating Modes See www ti com msp430 for application reports See RISC 16 Bit CPU See Basic Clock Module See RISC 16 Bit CPU See FLL in MSP430x4xx Family User s Guide See System Resets Interrupts and Operating Modes See Digital I O See System Resets Interrupts and Operating Modes See Basic Clock Module See System Resets Interrupts and Operating Modes See RISC 16 Bit CPU See System Resets Interrupts and Operating Modes See System Resets Interrupts and Operating Modes See System Resets Interrupts and Operating Modes See Basic Clock Module See RISC 16 Bit CPU See RISC 16 Bit CPU See RISC 16 Bit CPU See RISC 16 Bit CPU See Watchdog Timer Register Bit Co
140. K clock cycles to synchronize before each single transfer or complete block or burst block transfer Each byte word transfer requires two MCLK cycles after synchronization and one cycle of wait time after the transfer Because the DMA uses MCLK the DMA cycle time is dependent on the MSP430 operating mode and clock system setup If the MCLK source is active but the CPU is off the DMA will use the MCLK source for each transfer without re enabling the CPU If the MCLK source is off the DMA will temporarily restart MCLK sourced with DCOCLK for the single transfer or complete block or burst block transfer The CPU remains off and after the transfer completes MCLK is turned off The maximum DMA cycle time for all operating modes is show in Table 8 2 Table 8 2 Maximum DMA Cycle Time CPU Operating Mode Clock Source Maximum DMA Cycle Time _ Active mode MCLK DCOCLK 4 MCLK cycles Active mode MCLK LFXT1CLK 4 MCLK cycles Low power mode LPMO0 1 MCLK DCOCLK 5 MCLK cycles Low power mode LPM3 4 MCLK DCOCLK 5 MCLK cycles 6 ust Low power mode LPMO 1 MCLK LFXT1CLK 5 MCLK cycles Low power mode LPM3 MCLK LFXT1CLK 5 MCLK cycles Low power mode LPM4 MCLK LFXT1CLK 5 MCLK cycles 6 ust T The additional 6 us are neededto startthe DCOCLK It isthe t _PMx parameter in the data sheet 8 12 DMA Controller DMA Operation 8 2 7 Using DMA with System Interrupts DMA transfers are not interruptible by system interrupts System interrupts remain p
141. LADGO GOE ccs vr erre pex eh a ce 17 4 17 2 2 ADC12 Inputs and 17 5 17 2 3 Voltage Reference Generator 17 6 17 2 4 Sample and Conversion Timing 17 7 17 2 5 Conversion Memory 17 10 17 2 6 ADC12 Conversion 17 10 17 2 7 Using ADC12 with the DMA Controller 17 15 17 2 8 Using the Integrated Temperature Sensor 17 16 17 2 9 ADC12 Grounding and Noise Considerations 17 17 17 2 10 ADC12 Interrupts 17 18 1 3 ADG12 REGISIClS 5 2 oou ose Lee to nerenser deli DTE 17 20 xi Contents 18 E DOS RIS rinde 18 1 18 1 ADC10 Introduction eee 18 2 18 2 ADC10 Operation a a hh 18 4 18 2 1 10 Bit ADC Core s 18 4 18 2 2 ADC10 Inputs and 18 5 18 2 3 Voltage Reference Generator 18 6 18 2 4 Sample and Conversion Timing 18 7 18 2 5 Conversion
142. MPYS 7 MOV B 034h amp 0138h SXT amp OP2 MOV MOV 01234h amp MAC 05678h amp OP2 8x8 Unsigned Multiply MOV B MOV B 16x16 Signed Multiply MOV MOV 05678h amp OP2 f MOV B 012h amp 0136h SXT amp MACS MOV 034h R5 SXT R5 MOV _ R5 amp 0P2 8x8 Signed Multiply Abso 012h amp 0134h 034h amp 0138h 01234h amp MACS 8x8 Signed Multiply Accumulate 16x16 Unsigned Multiply Load first operand Load second operand Process results Absolute addressing Load first operand Load 2nd operand Process results Load first operand Load 2nd operand Process results lute addressing Load first operand Sign extend first operand Load 2nd operand Sign extend 2nd operand triggers 2nd multiplication Process results 16x16 Unsigned Multiply Accumulate Load first operand Load 2nd operand Process results Accumulate Absolute addressing Load first operand Load 2nd operand Process results Accumulate Load first operand Load 2nd operand Process results Absolute addressing Load first operand Sign extend first operand Temp location for 2nd operand Sign extend 2nd operand Load 2nd operand Process results Hardware Multiplier Hardware Multiplier Operation 7 2 4 Indirect Addressing of RESLO When using indirect or indirect autoincrement addressing mode to access the result registers
143. Modes for information on entering and exiting low power modes The now active BRCLK allows the USART to receive the balance of the character After the full character is received and moved to UxRXBUF URXIFGx is set and an interrupt service is again requested Upon ISR entry URXIFGx 1 indicating a character was received The URXIFGx flag is cleared when user software reads UxRXBUF Interrupt handler for frame start condition and Character receive BRCLK DCO UORX Int BIT B URXIFGO amp IFG2 Test URXIFGx to determine JNE ST COND If start or character OV B amp UxRXBUF dst Read buffer oe RETI ST COND BIC B 4URXSE amp UOTCTL Clear URXS signal BIS B URXSE amp UOTCTL R nabl dge detect BIC SCGO SCG1 0 SP Enable BRCLK DCO RETI H Ey a gt 2 9 ae oF gt Fo oak 4a 2 Note Break Detect With Halted UART Clock When using the receive start edge detect feature a break condition cannot be detected when the BRCLK source is off USART Peripheral Interface UART Mode 13 19 USART Operation UART Mode Receive Start Edge Detect Conditions When URXSE 1 glitch suppression prevents the USART from being accidentally started Any low level on URXDx shorter than the deglitch time t approximately 300 ns will be ignored by the USART and no interrupt request will be generated as shown in Figure 13 12 See the device
144. NC 1 or 4 and ADC10SC Wait for Trigger SAMPCON 4 Nee 4 8 16 64 x ADC10CLK Sample Input Channel 12 x ADC10CLK 1 x ADC10CLK Conversion Completed Result to ADC10MEM ADC1OIFG is Set x input channel Ax t Conversion result is unpredictable 18 10 ADC10 ADC10 Operation Sequence of Channels Mode A sequence of channels is sampled and converted once The sequence begins with the channel selected by INCHx and decrements to channel AO Each ADC result is written to ADC10MEM The sequence stops after conversion of channel AO Figure 18 6 shows the sequence of channels mode When ADC10SC triggers a sequence successive sequences can be triggered by the ADC10SC bit When any other trigger source is used ENC must be toggled between each sequence Figure 18 6 Sequence of Channels Mode If x gt 0 then x x 1 MSC 1 x input channel Ax CONSEQx 01 ADC100N 1 x INCHx Wait for Enable SHS 0 and ENC 1 4 ADC10SC 4 Wait for Trigger SAMPCON 4 8 16 64 x ADC10CLK Sample Input Channel Ax If x gt O then x x 1 12 x ADC10CLK and xz0 1 x ADC10CLK Conversion Completed Result to ADC10MEM ADCA10IFG is Set ADC10 18 11 ADC10 Operation Repeat Single Channel Mode A single channel selected by INCHx is sampled and converted continuously Each ADC result is writ
145. No interrupt pending 1 Interrupt pending Arbitration lost interrupt flag 0 No interrupt pending 1 Interrupt pending USART Peripheral Interface I C Mode 15 31 I C Module Registers I2CIV 12C Interrupt Vector Register 15 14 13 12 11 10 9 8 ro ro ro ro 7 6 5 4 3 2 1 0 ro ro ro r 0 r 0 r 0 r 0 ro I2CIVx Bits 12C interrupt vector value 15 0 I2CIV Interrupt Interrupt Contents Interrupt Source Flag Priority 000h No interrupt pending 002h Arbitration lost ALIFG Highest 004h No acknowledgement NACKIFG 006h Own address OAIFG 008h Register access ready ARDYIFG 00Ah Receive data ready RXRDYIFG 00Ch Transmit data ready TXRDYIFG OOEh General call GCIFG 010h Start condition received STTIFG Lowest 15 32 USART Peripheral Interface 2 Mode Chapter 16 Comparator A Comparator A is an analog voltage comparator This chapter describes Comparator A is implemented in MSP430x11x1 MSP430x12x MSP430x13x MSP430x14x MSP430x15x and MSP430x16x devices Topic Page 16 1 Comparator A Introduction 16 2 16 2 Comparator A Operation 16 3 16 3 Comparator A Registers 16 8 16 1 Comparator A Introduction 16 1 Comparator A Introduction The comparator A module supports precision slope analog to digital conversions supply voltage supervision and monitoring of
146. OP B PUSH B RET RETI RLA B RLC B RRA B RRC B SBC B SETC SETN SETZ SUB B SUBC B SWPB SXT TST B XOR B dst src dst src dst src dst src dst src dst src dst dst dst dst src dst dst src dst dst dst label label label label label label label label src dst dst dst dst dst dst dst src dst src dst dst dst dst src dst Emulated Instruction Description Add C to destination Add source to destination Add source and C to destination AND source and destination Clear bits in destination Set bits in destination Test bits in destination Branch to destination Call destination Clear destination Clear C Clear N Clear Z Compare source and destination Add C decimally to destination Add source and C decimally to dst Decrement destination Double decrement destination Disable interrupts Enable interrupts Increment destination Double increment destination Invert destination Jump if C set Jump if higher or same Jump if equal Jump if Z set Jump if greater or equal Jump if less Jump Jump if N set Jump if C not set Jump if lower Jump if not equal Jump if Z not set Move source to destination No operation Pop item from stack to destination Push source onto stack Return from subroutine Return from interrupt Rotate left arithmetically Rotate left through C Rotate right arithmetically Rotate right through C Subtract not
147. OR SVSFG causes a POR SVS on This bit reflects the status of SVS operation This bit DOES NOT turn on the SVS The SVS is turned on by setting VLDx gt 0 0 1 SVS is Off SVS is On SVS output This bit reflects the output value of the SVS comparator 0 1 SVS comparator output is high SVS comparator output is low SVS flag This bit indicates a low voltage condition SVSFG remains set after a low voltage condition until reset by software 0 1 No low voltage condition occurred A low condition is preset or has occurred Supply Voltage Supervisor 6 7 6 8 Supply Voltage Supervisor Chapter 7 Hardware Multiplier This chapter describes the hardware multiplier The hardware multiplier is implemented in MSP430x14x and MSP430x16x devices Topic Page 7 1 Hardware Multiplier 7 2 7 2 Hardware Multiplier Operation 7 3 7 3 Hardware Multiplier 7 7 7 1 Hardware Multiplier Introduction 7 1 Hardware Multiplier Introduction The hardware multiplier is a peripheral and is not part of the MSP430 CPU This means its activities do not interfere with the CPU activities The multiplier registers are peripheral registers that are loaded and read with CPU instructions The hardware multiplier supports Unsigned multiply Signed multiply Signed multiply accumulate
148. OT carry Borrow Carry bit Yes 0 No 1 3 62 RISC 16 Bit CPU SETC Syntax Operation Emulation Description Status Bits Mode Bits Example DSUB Instruction Set Set carry bit SETC 1 gt BIS 1 SR The carry bit C is set N Not affected Z Not affected C Set V Not affected OSCOFF CPUOFF and GIE are not affected Emulation of the decimal subtraction Subtract R5 from R6 decimally Assume that R5 3987 and R6 4137 ADD 6666h R5 Move content R5 from 0 9 to 6 0Fh R5 03987 6666 09FEDh INV R5 Invert this result back to 0 9 R5 NOT R5 06012h SETC Prepare carry 1 DADD R5 R6 Emulate subtraction by addition of 10000 R5 1 R6 R6 R5 1 4137 06012 1 1 0150 0150 RISC 16 Bit CPU 3 63 Instruction Set SETN Syntax Operation Emulation Description Status Bits Mode Bits Set negative bit SETN 1 gt N BIS 4 SR The negative bit N is set N Set Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected 3 64 RISC 16 Bit CPU Instruction Set SETZ Set zero bit Syntax SETZ Operation 1 Z Emulation BIS 2 SR Description The zero bit Z is set Status Bits N Not affected Z Set C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected RISC 16 Bit CPU 3 65 Instruction Set SUBLW SUB B Syntax Operation Description Status Bits
149. POR detect and POR delay circuits The brownout reset circuit detects low supply voltages such as when a supply voltage is applied to or removed from the Vcc terminal The brownout reset circuit resets the device by triggering a POR signal when power is applied or removed The operating levels are shown in Figure 2 3 The POR signal becomes active when Vcc crosses the Vcc start level It remains active until Vcc crosses the V p jr threshold and the delay elapses The delay tigon is adaptive being longer for a slow ramping Vcc The hysteresis _1 ensures that the supply voltage must drop below to generate another POR signal from the brownout reset circuitry Figure 2 3 Brownout Timing VCC start Set Signal for POR circuitry lt gt As the level is significantly above the Vmin level of the POR circuit the BOR provides a reset for power failures where Vcc does not fall below V MIN See device specific datasheet for parameters 2 4 System Resets Interrupts and Operating Modes System Reset and Initialization 2 1 3 Device Initial Conditions After System Reset After a POR the initial MSP430 conditions are m m Software Initialization The RST NMI pin is configured in the reset mode I O pins are switched to input mode as described in the Digital I O chapter Other peripheral modules and registers are initialized as described in their res
150. PU Off MCLK Off SMCLK Off DCO Off ACLK On LPM1 CPU Off MCLK Off SMCLK ACLK On LPM2 CPU Off MCLK Off SMCLK DC Generator Off if DCO Off DCO Off ACLK On not used in active mode DC Generator Off SCG1 SCGO OSCOFF CPUOFF Mode CPU and Clocks Status 0 Active CPU is active all enabled clocks are active LPMO CPU MCLK are disabled SMCLK ACLK are active 0 1 0 1 LPM1 CPU MCLK DCO osc are disabled DC generator is disabled if the DCO is not used for MCLK or SMCLK in active mode SMCLK ACLK are active 1 0 0 1 LPM2 CPU MCLK SMCLK DCO osc are disabled DC generator remains enabled ACLK is active 1 1 0 1 LPM3 CPU MCLK SMCLK DCO osc are disabled DC generator disabled ACLK is active 1 1 1 1 LPM4 CPU and all clocks disabled System Resets Interrupts and Operating Modes 2 15 Operating Modes 2 3 1 Entering and Exiting Low Power Modes An enabled interrupt event wakes the MSP430 from any of the low power operating modes The program flow is Enter interrupt service routine m The PC and SR are stored on the stack B The CPUOFF SCG1 and OSCOFF bits are automatically reset Options for returning from the interrupt service routine B The original SR is popped from the stack restoring the previous operating mode The SR bits stored on the stack can be modified within the interrupt service routine returning to a different operating mode when the RETI instructi Ent
151. PUC SFR interrupt flag register 1 IFG1 Read write 0002h Reset with PUC 1 WDTIFG is reset with POR Watchdog Timer 10 7 Watchdog Timer Registers WDTCTL Watchdog Timer Register 15 14 13 12 11 10 9 8 Read as 069h WDTPWXx must be written as 05Ah rw 0 WDTPWx WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTISx 7 6 5 4 3 2 WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTISx rw 0 ro w Bits 15 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bits 0 1 rw 0 rw 0 rw 0 rw 0 rw 0 Watchdog timer password Always read as 069h Must be written as 05Ah or a PUC will be generated Watchdog timer hold This bit stops the watchdog timer Setting WDTHOLD 1 when the WDT is not in use conserves power 0 Watchdog timer is not stopped 1 Watchdog timer is stopped Watchdog timer NMI edge select This bit selects the interrupt edge for the NMI interrupt when WDTNMI 1 Modifying this bit can trigger an NMI Modify this bit when WDTNMI 0 to avoid triggering an accidental NMI 0 NMI on rising edge 1 NMI on falling edge Watchdog timer NMI select This bit selects the function for the RST NMI pin 0 Reset function 1 NMI function Watchdog timer mode select 0 Watchdog mode 1 Interval timer mode Watchdog timer counter clear Setting WDTCNTCL 1 clears the count value to 0000h WDTCNTCL is automatically reset 0 No action 1 WDTONT 0000h Watchdog timer c
152. PUOFF are not affected The general interrupt enable GIE bit in the status register is set Interrupt routine of ports P1 2 to P1 7 P1IN is the address of the register where all port bits are read P1IFG is the address of the register where all interrupt events are latched MaskOK PUSH B amp P1IN BIC B SP amp P1IFG Reset only accepted flags EINT Preset port 0 interrupt flags stored on stack other interrupts are allowed BIT Mask SP JEQ MaskOK Flags are present identically to mask jump BIC Mask SP INCD SP Housekeeping inverse to PUSH instruction at the start of interrupt subroutine Corrects the stack pointer RETI Note Enable Interrupt The instruction following the enable interrupt instruction EINT is always executed even if an interrupt service request is pending when the interrupts are enable p 3 40 RISC 16 Bit CPU INCLW INC B Syntax Operation Emulation Description Status Bits Mode Bits Example Instruction Set Increment destination Increment destination INC dst or INC W dst INC B dst dst 1 dst ADD 1 dst The destination operand is incremented by one The original contents are lost N Set if result is negative reset if positive 2 Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise C Set if dst contained OFFFFh
153. Pc Register OFF18h OFF16h OFF14h OFF12h R10 OFA34h R11 010A8h OFA34h OFA32h OFA30h 010AAh 010A8h 010A6h The autoincrementing of the register contents occurs after the operand is fetched This is shown in Figure 3 8 Figure 3 8 Operand Fetch Operation Instruction Address RISC 16 Bit CPU 3 15 Addressing Modes 3 3 7 Immediate Mode The immediate mode is described in Table 3 10 Table 3 10 Immediate Mode Description Assembler Code Content of ROM MOV 45h MOV 45 X TONI PC Length Two or three words It is one word less if a constant of CG1 or CG2 can be used Operation Move the immediate constant 45h which is contained in the word following the instruction to destination address TONI When fetching the source the program counter points to the word following the instruction and moves the contents to the destination Comment Valid only for a source operand Example MOV 45h TONI Before After Address Register Address Register Space Space OFF18h Oxxxxh PC OFF16h 01192h OFF16h 01192h OFF14h 00045h OFF14h 00045h OFF12h 040B0h PC OFF12h 040BOh OFF16h 010AAh 01192h 010AAh 010A8h 01234h 010A8h dtoash 00045h 3 16 RISC 16 Bit CPU Instruction Set 3 4 Instruction Set The complete MSP430 instruction set consists of 24 core instructions and 27 emulated instructions The core instruc
154. QUO EQUI EQUO EQUI EQUO TBIFG TBIFG TBIFG Events Timer_B 12 15 Timer B Operation Output Example Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TBCLx and TBCLO values depending on the output mode An example is shown in Figure 12 13 using TBCLO and TBCL1 Figure 12 13 Output Example Timer in Continuous Mode TBR max TBCLO TBCL1 Oh TBIFG EQU1 EQUO TBIFG EQU1 EQUO Interrupt Events 12 16 Timer B Timer B Operation Output Example Timer in Up Down Mode The OUTx signal changes when the timer equals TBCLx in either count direction and when the timer equals TBCLO depending on the output mode An example is shown in Figure 12 14 using TBCLO and TBCL3 Figure 12 14 Output Example Timer in Up Down Mode TBR max TBCLO TBCL3 EQU3 TBIFG EQUO EQU3 TBIFG EQUO Output Mode 1 Set Output Mode 2 Toggle Reset Output Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set EQU3 EQU3 Interrupt Events Note Switching Between Output Modes When switching between output modes one of the OUTMODx bits should remain set during the transition unless switching to mode 0 Otherwise output glitching can occur because a NOR gate decodes output mode 0 A safe method for switching between output modes is to use output mode 7 as a transit
155. QUS EQUS Timer B Operation 12 2 4 Capture Compare Blocks Capture Mode Three or seven identical capture compare blocks TBCCRx are present in Timer B Any of the blocks may be used to capture the timer data or to generate time intervals The capture mode is selected when CAP 1 Capture mode is used to record time events It can be used for speed computations or time measurements Thecapture inputs CCIxA and CCIxB are connected to external pins or internal signals and are selected with the CCISx bits The CMx bits select the capture edge of the input signal as rising falling or both A capture occurs on the selected edge of the input signal If a capture is performed The timer value is copied into the TBCCRx register The interrupt flag CCIFG is set The input signal level can be read at any time via the CCI bit MSP430x1xx family devices may have different signals connected to CCIxA and CCIxB Refer to the device specific datasheet for the connections of these signals The capture signal can be asynchronous to the timer clock and cause a race condition Setting the SCS bit will synchronize the capture with the next timer clock Setting the SCS bitto synchronize the capture signal with the timer clock is recommended This is illustrated in Figure 12 10 Figure 12 10 Capture Signal SCS 1 CCI Set TBCCRx CCIFG Overflow logic is provided in each capture compare register to indica
156. R5 Add 10 to Lowbyte of R5 JC TONI Carry occurred if R5 gt 246 OAh 0F6h x No carry 3 22 RISC 16 Bit CPU ADDC W ADDC B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Add source and carry to destination Add source and carry to destination ADDC src dst or ADDC W src dst ADDC B src dst SIC dst C dst The source operand and the carry bit C are added to the destination operand The source operand is not affected The previous contents of the destination are lost N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise V Setif an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected The 32 bit counter pointed to by R13 is added to a 32 bit counter eleven words 20 2 2 2 above the pointer in R13 ADD R13 20 R13 ADD LSDs with no carry in ADDC R13 20 R13 ADD MSDs with carry resulting from the LSDs The 24 bit counter pointed to by R13 is added to a 24 bit counter eleven words above the pointer in R13 ADD B R13 10 R13 ADD LSDs with no carry in ADDC B R13 10 R13 ADD medium Bits with carry ADDC B R13 10 R13 ADD MSDs with carry resulting from the LSDs RISC 16 Bit CPU 3 23 Instruction Set AND W AND B Syntax Operation Description Status Bits Mode Bits Example
157. RST NMI pin low If a PUC occurs from a different source while the NMI signal is low the device will be held in the reset state because a PUC changes the RST NMI pin to the reset function p 1 Note Modifying NMIES When NMI mode is selected and the NMIES bit is changed an NMI can be generated depending on the actual level at the RST NMI pin When the NMI edge select bit is changed before selecting the NMI mode no NMI is generated System Resets Interrupts and Operating Modes 2 7 System Reset and Initialization Figure 2 5 Block Diagram of Non Maskable Interrupt Sources ACCV ACCVIFG b FCTL1 1 IE1 5 Clear PUC Flash Module RST NMI POR PUC KEYV Voc PUC System Reset Generator POR gt NMIRS IFG1 4 NMIES TMSEL NMI WDTQn EQU POR A A A A PUC o IE1 4 IRQ IFG1 0 PUC WDT Counter OSCFault POR OFIFG IB IFG1 1 IRQA OFIE TMSEL WDTIE IE1 1 Clear IE1 0 NMI IRQA Clear PUC Watchdog Timer Module PUC IRQA Interrupt Request Accepted 2 8 System Resets Interrupts and Operating Modes System Reset and Initialization Oscillator Fault The oscillator fault signal warns of a possible error condition with the crystal oscillator The oscillator fault can be
158. SBB src dst or SBB W src dst SUBC B src dst or SBB B src dst dst NOT src C gt dst or dst src 1 C dst The source operand is subtracted from the destination operand by adding the source operand s 1s complement and the carry bit C The source operand is not affected The previous contents of the destination are lost N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Setif there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Setif an arithmetic overflow occurs reset otherwise OSCOFF CPUOFF and GIE are not affected Two floating point mantissas 24 bits are subtracted LSBs are in R13 and R10 MSBs are in R12 and R9 SUB W R13 R10 16 bit part LSBs SUBC B R12 R9 8 bit part MSBs The 16 bit counter pointed to by R13 is subtracted from a 16 bit counter in R10 and R11 MSD SUB B R13 R10 Subtract LSDs without carry SUBC B Q9R13 R11 Subtract MSDs with carry resulting from the LSDs Note Borrow Implementation The borrow is treated as a NOT carry Borrow Carry bit Yes 0 No 1 RISC 16 Bit CPU 3 67 Instruction Set SWPB Syntax Operation Description Status Bits Mode Bits Swap bytes SWPB dst Bits 15 to 8 lt gt bits 7 to 0 The destination operand high and low bytes are exchanged as shown in Figure 3 18 Status bits are not affected OSCOFF CPUOFF and GI
159. START condition USART Peripheral Interface I C Mode 15 23 I C Module Registers I2CDCTL I2C Data Control Register 7 6 5 4 3 2 1 0 12 I2XTXUDF I2CRXOVR 12 SCLLOW r 0 r 0 r 0 r 0 r 0 ro Unused 12C SCLLOW I2CSBD I2CTXUDF I2ZCRXOVR I2CBB 15 24 Bits 7 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unused Always read as 0 12 SCL low This bit indicates if a slave is holding the SCL line low while the MSP430 is the master and is unused in slave mode 0 SCL is not being held low 1 SCL is being held low I2C single byte data This bit indicates if the receive register holds a word or a byte I2CSBD is valid only when I2CWORD 1 0 A complete word was received 1 Only the lower byte in I2CDR is valid 12C transmit underflow 0 No underflow occurred 1 Transmit underflow occurred 12C receive overrun 0 No receive overrun occurred 1 Receiver overrun occurred 2 busy bit A start condition sets 2 to 1 I2CBB is reset by a stop condition or when I2CEN O 0 Not busy 1 Busy USART Peripheral Interface 12C Mode 12C Module Registers I2CDR I2C Data Register 15 14 13 12 11 10 9 8 I2C Data High Byte second to be tranceived rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 I2C Data Low Byte first to be tranceived rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 I2CDRx Bits 12C data 15 0 I2CNDAT I2C Transfer Byte Count Register 6
160. TL Read write 01E8h Reset with POR DMA channel 1 source address DMA1SA Read write 01EAh Unchanged DMA channel 1 destination address DMA1DA Read write 01ECh Unchanged DMA channel 1 transfer size DMA1SZ Read write 01EEh Unchanged DMA channel 2 control DMA2CTL Read write 01FO0h Reset with POR DMA channel 2 source address DMA2SA Read write 01F2h Unchanged DMA channel 2 destination address DMA2DA Read write 01F4h Unchanged DMA channel 2 transfer size DMA2SZ Read write 01F6h Unchanged 8 14 DMA Controller DMA Hegisters DMACTLO DMA Control Register 0 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Reserved Bits Reserved 15 12 DMA2 Bits DMA trigger select These bits select the DMA transfer trigger TSELx 11 8 0000 DMAREQ bit software trigger 0001 Timer A CCR2 output 0010 Timer B CCR2 output 0011 12C receive ready 0100 12C transmit ready 0101 DAC12 OCTL DAC12IFG bit 0110 ADC12 ADC12IFGx 0111 No action 1000 No action 1001 No action 1010 No action 1011 No action 1100 No action 1101 No action 1110 DMAOIFG bit triggers DMA channel 1 DMA1IFG bit triggers DMA channel 2 DMA2IFG bit trigger DMA channel 0 1111 External trigger DMAEO DMA1 Bits Same as DMA2TSELx TSELx 7 4 DMAO Bits Same as DMA2TSELx TSELx 3 0 DMA Controller 8 15 DMA Registers DMACTL1 DMA Control Register 1 15 14 13 12 11 10 9 8 ro ro ro ro ro ro ro
161. TXWAKE is reset automatically 2 Write desired address character to UXTXBUF UxTXBUF must be ready for new data UTXIFGx 1 The new character representing the specified address is shifted out following the address identifying idle period on UTXDx Writing the first don t care character to UxTXBUF is necessary in order to shift the TXWAKE bit to WUT and generate an idle line condition This data is discarded and does not appear on UTXDx USART Peripheral Interface UART Mode USART Operation UART Mode Address Bit Multiprocessor Format When MM 1 the address bit multiprocessor format is selected Each processed character contains an extra bit used as an address indicator shown in Figure 13 4 The first character in a block of frames carries a set address bit which indicates that the character is an address The USART RXWAKE bit is set when a received character is a valid address frame and is transferred to UxRXBUF The URXWIE bit is used to control data reception in the address bit multiprocessor format If URXWIE is set data characters address bit 0 are assembled by the receiver but are not transferred to UxRXBUF and no interrupts are generated When a character containing a set address bit is received the receiver is temporarily activated to transfer the character to UxRXBUF and set URXIFGx All applicable error status flags are also set If an address is received user software must reset URXWIE to continue receiving data
162. The absolute mode is described in Table 3 7 Table 3 7 Absolute Mode Description Assembler Code Content of ROM MOV amp EDE amp TONI MOV 0 0 X EDE Y Length Two or three words Operation Move the contents of the source address EDE to the destination address TONI The words after the instruction contain the absolute address of the source and destination addresses With absolute mode the PC is incremented automatically so that program execution continues with the next instruction Comment Valid for source and destination Example MOV amp EDE amp TONI Source address EDE 0F016h dest address TONI 01114h Before After Address Register Address Register Space Space Oxxxxh PC OFF16h 01114h OFF16h 01114h OFF14h OFO16h OFF14h OF0O16h OFF12h 04292h PC OFF12h 04292h OF016h 0A123h OF016h 0A123h 01114h 01234h 01114h 0A123h This address mode is mainly for hardware peripheral modules that are located at an absolute fixed address These are addressed with absolute mode to ensure software transportability for example position independent code RISC 16 Bit CPU 3 13 Addressing Modes 3 3 5 Indirect Register Mode The indirect register mode is described in Table 3 8 Table 3 8 Indirect Mode Description Assembler Code Content of ROM MOV GR10 0 R11 MOV 8R10 0 R11 Length One or two words Operation Move the contents of the source addr
163. U intervention ADC12 features include Greater than 200 ksps maximum conversion rate Monotonic 12 bit converter with no missing codes Sample and hold with programmable sampling periods controlled by software or timers Conversion initiation by software Timer A or Timer B Software selectable on chip reference voltage generation 1 5 V or 2 5 V Software selectable internal or external reference Eight individually configurable external input channels DL D ODO Q Conversion channels for internal temperature sensor AVcc and external references E Independent channel selectable reference sources for both positive and negative references Selectable conversion clock source Single channel repeat single channel sequence and repeat sequence conversion modes ADC core and reference voltage can be powered down separately Interrupt vector register for fast decoding of 18 ADC interrupts 16 conversion result storage registers The block diagram of ADC12 is shown in Figure 17 1 Figure 17 1 ADC12 Block Diagram ADCt12 Introduction REFON INCHX 0AI VeREF gt VREF 1 5 Vor2 5 V VREF VenEpr Reference gt AVCC INCHx SREF1 11 10 01 00 Ayes 10 9 00 SREFO 0 12090 A0 SREF2 1 0 ADC120N ADC12SSELx A1 45 ADC12DIVx A3 V V 00 AS SE 01 ACLK A5 Divider AG 12
164. XExis set the UART transmitter is enabled Transmissionis initiated by writing data to UxTXBUF The data is then moved to the transmit shift register on the next BITCLK after the TX shift register is empty and transmission begins This process is shown in Figure 13 6 When the UTXEx bit is reset the transmitter is stopped Any data moved to UxTXBUF and any active transmission of data currently in the transmit shift register prior to clearing UTXEx will continue until all data transmission is completed Figure 13 6 State Diagram of Transmitter Enable 18 10 UTXEx 0 No Data Written to Transmit Buffer Not Completed UTXEx 1 Data Written to Transmit Buffer Idle State Transmitter Enabled Transmit Disable Transmission Active Handle Interrupt Conditions UTXEx 0 Character Transmitted UTXEx 0 And Last Buffer Entry Is Transmitted When the transmitter is enabled UTXEx 1 data should not be written to UxTXBUF unless it is ready for new data indicated by UTXIFGx 1 Violation can result in an erroneous transmission if data in UXTXBUF is modified as it is being moved into the TX shift register It is recommended that the transmitter be disabled UTXEx 0 only after any active transmission is complete This is indicated by a set transmitter empty bit TXEPT 1 Any data written to UXTXBUF while the transmitter is disabled will be held in the buffer but wi
165. ZCWORD 2CTRX I2CDR Function 0 1 Byte mode Transmit Only the low byte is used The byte is double buffered If a new byte is written before the previous byte has been transmitted the new byte is held in a temporary buffer before being latched into the I2CDR low byte TXRDYIFG is set when I2CDR is ready to be accessed 0 0 Byte mode receive Only the low byte is used The byte is double buffered If a new byte is received before the previous byte has been read the new byte is held in a temporary buffer before being latched into the I2CDR low byte RXRDYIFG is set when I2CDR is ready to be read 1 1 Word mode transmit The low byte of the word is sent first then the high byte The register is double buffered If a new word is written before the previous word has been transmitted the new word is held in atemporary buffer before being latched into the I2CDR register If the last data of a transmission is only one byte then the high byte must be zero TXRDYIFG is set when I2CDR is ready to be accessed 1 0 Word mode receive The low byte of the word was received first then the high byte The register is double buffered If a new word is received before the previous word has been read the new word is held in a temporary buffer before being latched into the I2CDR register If the last reception was only one byte then the high byte is 00h and the I2CSDB bit is set RXRDYIFG is set when I2CDR is ready to be accessed In master mode underflo
166. a Written to Transmit Buffer USPIEx 1 Idle State Transmitter Enabled Transmit Disable Handle Interrupt Conditions Transmission Active USPIEx 0 Character Transmitted PUC USPIEx 0 And Last Buffer Entry Is Transmitted Figure 14 5 Slave Transmit Enable State Diagram USPIEx 0 No Clock at UCLK Not Completed USPIEx 1 Transmit PE State Transmission Handle Interrupt Disabl Transmitter i Conditions TENE Enabled External Clock Active USPIEx 0 Present Character USPIEx 1 Transmitted PUC USPIEx 0 USART Peripheral Interface SPI Mode 14 7 USART Operation SPI Mode Receive Enable The SPI receive enable state diagrams are shown in Figure 14 6 and Figure 14 7 When USPIEx 0 UCLK is disabled from shifting data into the RX shift register Figure 14 6 SPI Master Receive Enable State Diagram USPIEx 0 No Data Written to UXTXBUF Not Completed USPIEx 1 Receive ene USPIEx 1 pecan Handle Interrupt Enabled Data Written Character Conditions USPIEx 0 to UXTXBUF Character Received PUC USPIEx 1 USPIEx 0 Figure 14 7 SPI Slave Receive Enable State Diagram No Clock LK USPIEx 0 o lockat YG Not Completed 14 8 USPIEx 1
167. abled ADC12 interrupt generates a number in the ADC12IV register see register description This number can be evaluated or added to the program counter to automatically enter the appropriate software routine Disabled ADC12 interrupts do not affect the ADC12IV value Any access read or write of the ADC12IV register automatically resets the ADC12OV condition the ADC12TOV condition if either was the highest pending interrupt Neither interrupt condition has an accessible interrupt flag The ADC12IFGx flags are not reset by an ADC12IV access ADC12IFGx bits are reset automatically by accessing their associated ADC12MEMXx register or may be reset with software If another interrupt is pending after servicing of an interrupt another interrupt is generated For example if the ADC12OV and ADC12IFG3 interrupts are pending when the interrupt service routine accesses the ADC12IV register the ADC120OV interrupt condition is reset automatically After the RETI instruction ofthe interrupt service routine is executed the ADC12IFG3 generates another interrupt ADC12 Operation ADC12 Interrupt Handling Software Example The following software example shows the recommended use of ADC12IV and the handling overhead The ADC12IV value is added to the PC to automatically jump to the appropriate routine The numbers at the right margin show the necessary CPU cycles for each instruction The software overhead for different interrupt sources includes int
168. acter to prevent bit errors The USART module automatically detects framing errors parity errors overrun errors and break conditions when receiving characters The bits FE PE OE and BRK are set when their respective condition is detected When any of these error flags are set RXERR is also set The error conditions are described in Table 13 1 Table 13 1 Receive Error Conditions Error Condition Description A framing error occurs when a low stop bit is detected When two stop bits are used only the first stop bit is checked for framing error When a framing error is detected the FE bit is set A parity error is a mismatch between the number of 1s in a frame and the value of the parity bit When Parity error an address bit is included in the frame it is included in the parity calculation When a parity error is detected the PE bit is set An overrun error occurs when a character is loaded Receive overrun error into UXRXBUF before the prior character has been read When an overrun occurs the OE bit is set A break condition is a period of 10 or more low bits received on URXDx after a missing stop bit When a Break condition break condition is detected the BRK bit is set A break condition can also set the interrupt flag URXIFGx Framing error When URXEIE 0 and a framing error parity error or break condition is detected no character is received into UxRXBUF When URXEIE 1 characters are received into UXRXBU
169. an active sample or conversion operation BUSY 0 is active 1 A sequence sample or conversion is active ADC12MEMx ADC12 Conversion Memory Registers 5 is 13 12 11 10 9 8 ESqERENRESEE WM ro ro ro ro ni nij m 7 6 5 4 3 2 rw rw rw rw r a x Conversion Bits The 12 bit conversion results are right justified Bit 11 is the MSB Bits 15 12 Results 15 0 are always 0 Writing to the conversion memory registers will corrupt the results 17 24 ADC12 ADC12 Registers ADC12MCTLx ADC12 Conversion Memory Control Registers Modifiable only when ENC 0 EOS Bit 7 End of sequence Indicates the last conversion in a sequence 0 1 Not end of sequence End of sequence SREFx Bits Select reference 6 4 000 001 010 011 100 101 110 111 INCHx Bits Input 3 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 VR and Vp AVss VR VREF and Vp AVss VR Vener and Vp AVss VR Vengr and Vp AVss Vn AVcc and Vp Vngr Vengr VR VREF and Vg VREF Vengr VR Vener Vp Vngr Vengr VR Vener and Vp VREF Vengr channel select VenEF VnEr VenEr Temperature diode AVcc AVgs 2 AVcc AVss AVcc AVss ue AVss 2 2 2 AVcc AVss 2 ADC12 17 25 ADC12 Registers ADC12IE ADC12 Interrupt Enable Register ADC12l1E15 ADC12IE14 A
170. ant gen erator Figure 3 6 shows the SR bits 15 9 8 7 0 OSC CPU rw 0 Table 3 1 describes the status register bits Table 3 1 Description of Status Register Bits 3 6 Bit V SCG1 SCGO OSCOFF CPUOFF GIE N RISC 16 Bit CPU Description Overflow bit This bit is set when the result of an arithmetic operation overflows the signed variable range ADD B ADDC B Set when Positive Positive Negative Negative Negative Positive otherwise reset SUB B SUBC B CMP B Set when Positive Negative Negative Negative Positive Positive otherwise reset System clock generator 1 This bit when set turns off the SMCLK System clock generator 0 This bit when set turns off the DCO dc generator if DCOCLK is not used for MCLK or SMCLK Oscillator Off This bit when set turns off the LFXT1 crystal oscillator when LFXT1CLK is not use for MCLK or SMCLK CPU off This bit when set turns off the CPU General interrupt enable This bit when set enables maskable interrupts When reset all maskable interrupts are disabled Negative bit This bit is set when the result of a byte or word operation is negative and cleared when the result is not negative Word operation N is set to the value of bit 15 of the result Byte operation N is set to the value of bit 7 of the result Zero bit This bit is set when the result of a byte or word operation is 0 and cleared when the res
171. aracter from the receive shift register Reading UxRXBUF resets the receive error bits the RXWAKE bit and URXIFGx In 7 bit data mode UxRXBUF is LSB justified and the MSB is always reset UxTXBUF USART Transmit Buffer Register 7 6 5 4 3 2 1 0 EXEXENEXE NEUEN rw rw rw rw rw rw rw rw UxTXBUFx Bits The transmit data buffer is user accessible and holds the data waiting to be 7 0 moved into the transmit shift register and transmitted on UTXDx Writing to the transmit data buffer clears UTXIFGx The MSB of UxTXBUF is not used for 7 bit data and is reset 13 26 USART Peripheral Interface UART Mode USART Registers UART Mode ME1 Module Enable Register 1 7 6 5 4 3 2 1 0 rw 0 rw 0 UTXEOT Bit 7 URXEot Bit 6 Bits 5 0 USARTO transmit enable This bit enables the transmitter for USARTO 0 Module not enabled 1 Module enabled USARTO receive enable This bit enables the receiver for USARTO 0 Module not enabled 1 Module enabled These bits may be used by other modules See device specific datasheet T Does not apply to MSP430x12xx devices See ME2 for the MSP430x12xx USARTO module enable bits ME2 Module Enable Register 2 7 Bits 7 6 UTXE1 Bit 5 URXE1 Bit 4 Bits UTXEOt Bit 1 URXEot Bit 0 MSP430x12xx devices only 6 5 4 3 2 1 0 0 rw 0 rw 0 rw 0 rw These bits may be used by other modules See device specific datasheet USART1 transmit enable This bit enables the transmitter for USART1
172. as changed sign N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Loaded from the MSB V Setif an arithmetic overflow occurs the initial value is 04000h lt dst lt 0C000h reset otherwise Set if an arithmetic overflow occurs the initial value is 040h lt dst OCOh reset otherwise OSCOFF CPUOFF and GIE are not affected R7 is multiplied by 2 RLA R7 Shift left R7 x 2 The low byte of R7 is multiplied by 4 RLA B R7 Shift left low byte of R7 x 2 RLA B R7 Shift left low byte of R7 x 4 Note RLA Substitution The assembler does not recognize the instruction RLA R5 nor RLAB R5 It must be substituted by ADD R5 2 R5 or ADD B QR5 1 R5 3 58 RISC 16 Bit CPU RLC W RLC B Syntax Operation Emulation Description Instruction Set Rotate left through carry Rotate left through carry RLC dst or RLC W dst RLC B dst C lt MSB lt MSB 1 LSB 1 lt LSB lt ADDC dst dst The destination operand is shifted left one position as shown in Figure 3 15 The carry bit C is shifted into the LSB and the MSB is shifted into the carry bit C Figure 3 15 Destination Operand Carry Left Shift Status Bits Mode Bits Example Example Example 0 7 0 Set if result is negative reset if positive Set if result is zero reset otherwise Loaded from the MSB Set if an arit
173. aster device The slave device does not generate the clock but it can hold SCL low if intervention of the CPU is required after a byte has been received Slave transmitter mode can only be entered from the slave receiver mode The slave transmitter mode is entered if the slave address byte transmitted by the master is the same as its own address and a set R W bit has been transmitted indicating a request to send data to the master The slave transmitter shifts the serial data out on SDA with the clock pulses that are generated by the master device The slave device does not generate the clock but it can hold SCL low while intervention of the CPU is required after a byte has been transmitted 15 12 USART Peripheral Interface 2 Mode Figure 15 12 Slave Transmitter IPCWORD 1 Start detected Yes 12C Module Operation STTIFG is Set 4 x l2CPSC 8x SCL No Match Receive Slave Address bits 6 0 with R W 0 Matched 1xscL Generate Ack XA 1 10 bit Address 8x SCL Receive Slave Address bits 9 7 extended with R W Matches ixScL 2 Generate Ack OAIFG is set if not re start No 2nd Start Detected Yes STTIFG is set XA 0 7 bit OAIFG is set if not re start Yes Address 1x SCL S Generate Ack Matches I2COA 8x SCL Receive Slave Address bits 6 0 with R W 1 USART Peripheral Interface
174. ata direction specified by the R W bit The RESTART condition is shown in Figure 15 8 Figure 15 8 12C Module Addressing Format with Repeated START Condition Dum cuo EBEN Br Slave Address Wa ml Slave Address k Number 9 Number USART Peripheral Interface I C Mode 15 7 12C Module Operation 15 2 4 12C Module Operating Modes 12C module operates in master transmitter master receiver slave transmitter or slave receiver mode Master Mode In master mode transmit and receive operation is controlled with the I2CRM I2CSTT I2CSTP bits as described in Table 15 1 The master receiver mode is entered by setting 2 0 after a slave address byte and a set R W bit has been transmitted The master transmitter and master receiver modes are shown in Figure 15 9 and Figure 15 10 SCL is held low when the intervention of the CPU is required after a byte has been transmitted Table 15 1 Master Operation 15 8 I2CRM I2CSTP I2CSTT Condition Or Bus Activity X 0 0 The 12C module is in master mode but is idle No start or stop condition is generated 0 0 1 Setting I2CSTT initiates activity IACNDAT is used to determine length of transmission A stop condition is not automatically generated after the I2CNDAT number of bytes have been transferred Software must set I2CSTP to generate a stop condition at the end of transmiss
175. ation occurs ACCVIFG is set and the flash write is unpredictable A byte word write operation can be initiated from within flash memory or from RAM When initiating from within flash memory all timing is controlled by the flash controller and the CPU is held while the write completes After the write completes the CPU resumes code execution with the instruction following the write The byte word write timing is shown in Figure 5 7 Figure 5 7 Byte Word Write Timing EM 1 li E 4 gt lt gt lt gt Programming Operation Active Generate Remove Programming Voltage Programming Voltage Programming Time Vcc Current Consumption is Increased lt Bug qr His t Word Write 33 f FTG When a byte word write is executed from RAM the CPU continues to execute code from RAM The BUSY bit must be zero before the CPU accesses flash again otherwise an access violation occurs ACCVIFG is set and the write result is unpredictable 5 8 Flash Memory Controller Flash Memory Operation Initiating a Byte Word Write from Within Flash Memory The flow to initiate a byte word write from flash is shown in Figure 5 8 Figure 5 8 Initiating a Byte Word Write from Flash Disable all interrupts and watchdog Setup flash controller and set WRT 1 Write byte or word Set WRT 0 LOCK 1 re enable interrupts and watchdog y Byte word write from flash 514 kHz SMCLK 952 kHz Assu
176. be set when an address character is received When URXEIE 0 an address character will not set URXIFGx if it is received with errors 0 All received characters set URXIFGx 1 Only received address characters set URXIFGx RXWAKE Bit 1 Receive wake up flag 0 Received character is data 1 Received character is an address RXERR Bit 0 Receive error flag This bit indicates a character was received with error s When RXERR 1 on or more error flags FE PE OE BRK is also set RXERR is cleared when UxRXBUF is read 0 No receive errors detected 1 Receive error detected 13 24 USART Peripheral Interface UART Mode USART Registers UART Mode UxBRO USART Baud Rate Control Register 0 7 6 5 4 3 2 1 0 EES ESESESESERES rw rw rw rw rw rw rw rw UxBR1 USART Baud Rate Control Register 1 7 6 5 4 3 2 1 0 ee qp epic e rw rw rw rw rw rw rw rw UxBRx The valid baud rate control range is 3 lt UxBR lt OFFFFh where UxBR UxBR1 UxBR0O Unpredictable receive and transmit timing occurs if UxBR 3 UxMCTL USART Modulation Control Register 7 6 5 4 3 2 1 0 EXELIRZENXEXERENEA rw rw rw rw rw rw rw rw UxMCTLx Bits Modulation bits These bit select the modulation for BRCLK 7 0 USART Peripheral Interface UART Mode 13 25 USART Registers UART Mode UxRXBUF USART Receive Buffer Register 7 6 5 4 3 2 1 0 EXEZAENENEEZEESERES r r r r r r r r UxRXBUFx Bits The receive data buffer is user accessible and contains the last received 7 0 ch
177. bedded Em lation E 1 3 T Address Space E n 1 4 Architecture 1 1 Architecture The MSP430 incorporates a 16 bit RISC CPU peripherals and a flexible clock System that interconnect using a von Neumann common memory address bus MAB and memory data bus MDB Partnering a modern CPU with modular memory mapped analog and digital peripherals the MSP430 offers solutions for demanding mixed signal applications Key features of the MSP430 include Ultralow power architecture extends battery life 0 1 uA RAM retention 0 8 uA real time clock mode 250 MIPS active High performance analog ideal for precision measurement 12 bit or 10 bit ADC 200 ksps temperature sensor Vner B 12 bit dual DAC B Comparator gated timers for measuring resistive elements B Supply voltage supervisor 16 bit RISC CPU enables new applications at a fraction of the code size B Large register file eliminates working file bottleneck Compact core design reduces power consumption and cost B Optimized for modern high level programming Only 27 core instructions and seven addressing modes B Extensive vectored interrupt capability Lj In system programmable Flash permits flexible code changes field upgrades and data logging 1 2 Flexible Clock System 1 2 Introduction The clock system is designed specifically for battery powered applications A low frequency uxiliary
178. bit SAR A B 7 11 SMCLK Sonen ADC12CLK BUSY SHSx SHP SHTOx ISSH SHI 00 ADC12S Sample Timer 01 14 11024 q SAMPCON 1 1 136 11 TB1 SHT1x MSC INCHx 0Bh Ref_x ADC12MEMO ADC12MCTLO 8 CSTARTADDx E 16 x 12 16x8 e i Memory Memory mo Buffer Control 5 R LX CONSEQx ah _ I ADC12MEM15 ADC12MCTL15 AVSS ADC12 17 3 ADC12 Operation 17 2 ADC12 Operation The ADC12 module is configured with user software The setup and operation of the ADC12 is discussed in the following sections 17 2 1 12 Bit ADC Core The ADC core converts an analog input to its 12 bit digital representation and stores the result in conversion memory The core uses two programmable selectable voltage levels Vp and Vp_ to define the upper and lower limits of the conversion The digital output Napc is full scale OFFFh when the input signal is equal to or higher than and zero when the input signal is equal to or lower than Vp The input channel and the reference voltage levels Vg and Vp_ are defined in the conversion control memory The conversion formula for the ADC result Napc is Vin V VR VR Napc 4095 x The ADC12 core is configured by two control registers ADC12CTLO and ADC12CTL1 The core is enabled with the ADC12ON bit The ADC12 can be turned off when not in use to save power With few exceptions the ADC12 control bits can only be modified when ENC
179. bits of the USART Timing for each case is shown in Figure 14 9 Figure 14 9 USAHT SPI Timing Odet 1 p 2 3 4 s je 7 ja 0 UaK 0 1 1 1 1 UCLK oox ce ox 98 Move to UxTXBUF RX Sample Points 14 10 USART Peripheral Interface SPI Mode USART Operation SPI Mode 14 2 6 SPI Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception SPI Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UXTXBUF is ready to accept another character An interrupt request is generated if UTXIEx and GIE are also set UTXIFGx is automatically reset if the interrupt request is serviced or if a character is written to UXTXBUF UTXIFGx is set after a PUC or when SWRST 1 UTXIEx is reset after a PUC or when SWRST 1 The operation is shown is Figure 14 10 Figure 14 10 Transmit Interrupt Operation UTXIEx ott SYNC 1 L 4 PUC or SWRST UTXIFGx Q 4 Service Requested gt SWRST Character Moved From Buffer to Shift Register Data moved to UXTXBUF IRQA Note Writing to UXTXBUF in SPI Mode Data written to UXTXBUF when UTXIFGx 0 and USPIEx 1 may result in erroneous data transmission LLLLLS S O O A OA OA USART Perip
180. by other modules See device specific datasheet 3 2 UTXIEOt Bit 1 USARTO transmit interrupt enable This bit enables the UTXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled URXIEOt Bit 0 USARTO receive interrupt enable This bit enables the URXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled t MSP430x12xx devices only 13 28 USART Peripheral Interface UART Mode USART Registers UART Mode IFG1 Interrupt Flag Register 1 7 6 5 4 3 2 1 0 rw 1 rw 0 UTXIFGOt Bit 7 URXIFGOT Bit 6 Bits 5 0 USARTO transmit interrupt flag UTXIFGO is set when UOTXBUF is empty 0 No interrupt pending 1 Interrupt pending USARTO receive interrupt flag URXIFGO is set when UORXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules See device specific datasheet t Does not apply to MSP430x12xx devices See IFG2 for the MSP430x12xx USARTO interrupt flag bits IFG2 Interrupt Flag Register 2 7 Bits 7 6 UTXIFG1 Bit 5 URXIFG1 Bit 4 Bits 3 2 UTXIFGO Bit 1 URXIFGO Bito MSP430x12xx devices only 6 5 4 3 2 1 0 1 1 rw 0 rw rw 0 rw These bits may be used by other modules See device specific datasheet USART1 transmit interrupt flag UTXIFG1 is set when U1TXBUF empty 0 No interrupt pending 1 Interrupt pending USART1 receive interrupt flag URXIFG1 is setwhen U1RXBUF has received a complete character 0 No interrupt pe
181. ce routine must then re enable the 12 internal clock source for the 12 module to release the SCL line and allow bus activity to continue normally 15 2 8 Using the I2C Module with the DMA Controller The 12C module provides two trigger sources for the DMA controller The RXRDYIFG flag can trigger a DMA transfer when new 12C data is received and the TXRDYIFG flag can trigger a DMA transfer when the 12 module needs new transmit data The TXDMAEN and RXDMAEN bits enable or disable the use of the DMA controller with the 12C module When RXDMAEN 1 the DMA controller can be used to transfer data from the I2C module after the I2C modules receives data When RXDMAEN 1 RXDYIE is automatically cleared When TXDMAEN 1 the DMA controller can be used to transfer data to the I2C module for transmission When TXDMAEN 1 the TXRDYIE is automatically cleared See the DMA Controller chapter for more details on the DMA controller USART Peripheral Interface I C Mode 15 17 12C Module Operation 15 2 9 Configuring the USART for I2C Operation 12C Module Reset The 12C controller is part of the USART peripheral Individual bit definitions when using USARTO in 12C mode are different from that in SPI or UART mode The default value for the UOCTL register is the UART mode and the register contains the following bits To select SPI or 12C operation the SYNC bit must be set Setting the SYNC bit with SWRST 1 selects SPI mode Setting the
182. ch capture compare register to indicate if a second capture was performed before the value from the first capture was read Bit COV is set when this occurs as shown in Figure 11 11 COV must be reset with software Timer_A 11 11 Timer A Operation Figure 11 11 Capture Cycle Idle Capture Capture Read No Capture Taken Read Taken Capture Capture Taken Capture Capture Read and No Capture Capture Clear Bit COV in Register TACCTLx Second Capture Taken COV 1 Idle Capture Initiated by Software Captures can be initiated by software The CMx bits can be set for capture on both edges Software then sets CCI 1 and toggles bit CCISO to switch the capture signal between Vcc and GND initiating a capture each time CCISO changes state MOV CAP SCS CCIS1 CM_3 amp TACCTLx Setup TACCTLx XOR CCISO amp TACCTLx TACCTLx TAR Compare Mode The compare mode is selected when CAP 0 The compare mode is used to generate PWM output signals or interrupts at specific time intervals When TAR counts to the value in a TACCRx Interrupt flag CCIFG is set Internal signal EQUx 1 EQUXx affects the output according to the output mode The input signal CCI is latched into SCCI 11 12 Timer A 11 2 5 Output Unit Timer A Operation Each capture compare block contains an output unit The output unit is used to generate output signals such as PWM s
183. ch discussion presents the module or peripheral in a general sense Not all features and functions of all modules or peripherals are present on all devices In addition modules or peripherals may differ in their exact implementation between device families or may not be fully implemented on an individual device or device family Pin functions internal signal connections and operational paramenters differ from device to device The user should consult the device specific datasheet for these details Related Documentation From Texas Instruments FCC Warning For related documentation see the web site http www ti com msp430 This equipment is intended for use in a laboratory test environment only It gen erates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in other en vironments may cause interference with radio communications in which case the user at his own expense will be required to take whatever measures may be required to correct this interference Notational Conventions Program examples are shown in a special typeface Glossary Glossary ACLK ADC BOR BSL CPU DAC DCO dst FLL GIE INT N 2 ISR LSB LSD LPM MAB MCLK MDB MSB MSD NMI PC POR PUC RAM SCG SFR SMCL
184. clock ACLK is driven directly from a common 32 kHz watch crystal The ACLK can be used for a background real time clock self wake up function An integrated high speed digitally controlled oscillator DCO can source the master clock MCLK used by the CPU and high speed peripherals By design the DCO is active and stable in less than 6 us MSP430 based solutions effectively use the high performance 16 bit RISC CPU in very short bursts Low frequency auxiliary clock Ultralow power stand by mode High speed master clock High performance signal processing Embedded Emulation Figure 1 1 MSP430 Architecture ee ong oe T INERAT EDIT SURE EE Ee ee 1 ACLK Flash ROM o MAB 16 Bit RISCCPU 8 16 Bit x MDB 16 Bit Gus MDB 8 Bit gt 1 3 Embedded Emulation Dedicated embedded emulation logic resides on the device itself and is accessed via JTAG using no additional system resources The benefits of embedded emulation include Unobtrusive development and debug with full speed execution breakpoints and single steps in an application are supported Development is in system subject to the same characteristics as the final application L Mixed signal integrity is preserved and not subjectto cabling interference Introduction 1
185. control 5 ADC12MCTL5 Read write 085h Reset with POR ADC12 memory control 6 ADC12MCTL6 Read write 086h Reset with POR ADC12 memory control 7 ADC12MCTL7 Read write 087h Reset with POR ADC12 memory control 8 ADC12MCTL8 Read write 088h Reset with POR ADC12 memory control 9 ADC12MCTL9 Read write 089h Reset with POR ADC12 memory control 10 ADC12MCTL10 Read write 08Ah Reset with POR ADC12 memory control 11 ADC12MCTL11 Read write 08Bh Reset with POR ADC12 memory control 12 ADC12MCTL12 Read write 08Ch Reset with POR ADC12 memory control 13 ADC12MCTL13 Read write 08Dh Reset with POR ADC12 memory control 14 ADC12MCTL14 Read write 08Eh Reset with POR ADC12 memory control 15 ADC12MCTL15 Read write 08Fh Reset with POR 17 20 ADC12 ADC12 Registers ADC12CTLO ADC12 Control Register 0 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 wee ancreowe 802 oec rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Modifiable only when ENC 0 SHT1x Bits Sample and hold time These bits define the number of ADC12CLK cycles in 15 12 the sampling period for registers ADC12MEM8 to ADC12MEM 15 SHTOx Bits Sample and hold time These bits define the number of ADC12CLK cycles in 11 8 the sampling period for registers ADC12MEMO to ADC12MEM7 SHTx Bits ADC12CLK cycles 0000 4 0001 8 0010 16 0011 32 0100 64 0101 96 0110 128 0111 192 1000 256 1001 384 1010 512 1011 768
186. d and bits 7 4 are unchanged I2CDCTL and I2CDR register is cleared Transmit and receive shift registers are cleared UOCTL I2CNDAT I2CPSC I2CSCLL I2CSCLH registers are unchanged I2COA I2CSA I2CIE I2CIFG and I2CIV registers are unchanged LU LU 15 18 USART Peripheral Interface 2 Mode 15 2 10 12C Interrupts 12C Module Operation The 12C module has one interrupt vector for eight interrupt flags Each interrupt flag has its own interrupt enable bit When an interrupt is enabled and the GIE bit is set the interrupt flag will generate an interrupt request The 12 interrupt events are Interrupt Flag ALIFG NACKIFG OAIFG ARDYIFG RXRDYIFG TXRDYIFG GCIFG STTIFG Interrupt Condition Arbitration lost Arbitration can be lost when two or more transmitters start a transmission simultaneously or when the software attempts to initiate an 12C transfer while 2 1 The ALIFG flag is set when arbitration has been lost When ALIFG is set the MST and I2CSTP bits are cleared and the I2C controller becomes a slave receiver No acknowledge interrupt This flag is set when the master does not receive an acknowledge from the slave NACKIFG is used in master mode only Own address interrupt The OAIFG interrupt flag is set when another master has addressed the I2C module OAIFG is used in slave mode only Register access ready interrupt This flag is set when the previously programmed tran
187. d and byte addressing and instruction formats The block diagram of the CPU is shown in Figure 3 1 RISC 16 Bit CPU CPU Introduction Figure 3 1 CPU Block Diagram MDB Memory Data Bus Memory Address Bus MAB 15 0 RO PC Program Counter R1 SP Stack Pointer gt R2 SR CG1 Status lt gt amp lt gt lt 7 lt gt lt gt amp lt gt lt gt 2 2 Carry C Overflow V Negative N 16 RISC 16 Bit CPU 3 3 CPU Registers 3 2 CPU Registers The CPU incorporates sixteen 16 bit registers RO R1 R2 and R3 have dedicated functions R4 to R15 are working registers for general use 3 2 1 Program Counter PC The 16 bit program counter PC RO points to the next instruction to be executed Each instruction uses an even number of bytes two four or six and the PC is incremented accordingly Instruction accesses in the 64 KB address space are performed on word boundaries and the PC is aligned to even addresses Figure 3 2 shows the program counter Figure 3 2 Program Counter 15 1 0 Program Counter Bits 15 to 1 The PC be addressed with all instructions and addressing modes A few examples MOV LABEL PC Branch to address LABEL MOV LABEL PC Branch to address contained in LABEL MOV R14 PC Branch indirect indirect R14 3 4 RISC 16 Bit CPU CPU
188. d conversion start 1 Start sample and conversion ADC10 Registers ADC10CTL1 ADC10 Control Register 1 15 14 13 12 11 10 9 8 ee rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 Modifiable only when ENC 0 INCHx Bits Input channel select 15 12 0000 AO 0001 A1 0010 A2 0011 A3 0100 A4 0101 A5 0110 A6 0111 A7 1000 Vepgr 1001 Vpgr Vepngr 1010 Temperature diode 1011 AVsg 2 1100 AVsg 2 1101 AVcc AVsg 2 1110 AVcc AVsg 2 1111 AVcc AVsg 2 SHSx Bits Sample and hold source select 11 10 00 ADC10SC bit 10 Timer A OUT1 10 Timer A OUTO 11 Timer A OUT2 ADC10DF Bit 9 ADC10 data format 0 Straight binary 1 2 s complement ISSH Bit 8 Invert signal sample and hold 0 The sample input signal is not inverted 1 The sample input signal is inverted ADC10 18 27 ADC10 Registers ADC1ODIVx Bits ADC10 clock divider 7 5 000 001 2 010 3 011 4 100 5 101 6 110 7 111 8 ADC10 Bits ADC10 clock source select SSELx 4 3 00 ADC100SC 01 ACLK 10 MCLK 11 SMCLK CONSEQx Bits Conversion sequence mode select 2 1 00 Single channel single conversion 01 Sequence of channels 10 Repeatsingle channel 11 Repeatsequence of channels ADC10 Bit 0 ADC10 busy This bit indicates an active sample or conversion operation BUSY O No operation is active 1 A sequence sample or conversion is active
189. data buffer is user accessible and contains current data to be 7 0 transmitted When seven bit character length is used the data should be MSB justified before being moved into UxTXBUF Data is transmitted MSB first Writing to UxTXBUF clears UTXIFGx 14 18 USART Peripheral Interface SP Mode USART Registers SPI Mode ME1 Module Enable Register 1 7 6 5 4 3 2 1 0 rw 0 Bit 7 This bit may be used by other modules See device specific datasheet USPIEOT Bit 6 USARTO SPI enable This bit enables the SPI mode for USARTO 0 Module not enabled 1 Module enabled Bits These bits may be used by other modules See device specific datasheet 5 0 T Does not apply to MSP430x12xx devices See ME2 for the MSP430x12xx USARTO module enable bit ME2 Module Enable Register 2 7 6 5 4 3 2 1 0 rw 0 rw 0 Bits These bits may be used by other modules See device specific datasheet 7 5 USPIE1 Bit 4 USART1 SPI enable This bit enables the SPI mode for USART1 0 Module not enabled 1 Module enabled Bits These bits may be used by other modules See device specific datasheet 3 1 USPIEOt Bit 0 USARTO SPI enable This bit enables the SPI mode for USARTO 0 Module not enabled 1 Module enabled t MSP430x12xx devices only USART Peripheral Interface SPI Mode 14 19 USART Registers SPI Mode IE1 Interrupt Enable Register 1 rw 0 UTXIEOT Bit 7 URXIEOT Bit 6 Bits 5 0 7 6 5 4 3 2 1 0 rw 0 USARTO transmit interrupt enable This bit e
190. dress to block addresses MS Address Space Controller Block Addresses to Block Addresses DMA Controller 8 5 DMA Operation 8 2 2 DMA Transfer Modes Single Transfer The DMA controller has six transfer modes Single transfer Block transfer Burst block transfer Repeated single transfers Repeated block transfers Repeated burst block transfers Each DMA channel can be individually configurable for its transfer mode with the corresponding DMADTx bits For example channel 0 may be configured in single transfer mode while channel 1 is configured for burst block transfer mode and channel 2 operates in repeated block mode The DMA transfer mode is configured independently from the DMA addressing mode Any DMA addressing mode can be used with any DMA transfer mode The DMA state diagram is shown in Figure 8 3 When a DMA channel is configured in single transfer mode each byte word transfer requires a separate trigger Setting DMADTx 0 configures single transfer mode When DMADTx 0 the DMAEN bit is cleared after each transfer and must be set again for another transfer to occur Setting DMADTx 4 configures repeated single transfer mode When DMADTx 4 the DMA controller remains enabled with DMAEN 1 anda DMA transfer occurs every time a trigger occurs The DMAxSZ register contains the number of transfers to be made If DMAxSZ 0 not transfers occur The DM
191. dule is ready to transmit new data The DMA trigger is the condition not the TXRDYIFG flag TXRDYIFG is not cleared when the DMA transfer starts and setting TXRDYIFG with software will not trigger a DMA transfer A DMA transfer is triggered when the DAC12 0 DAC12IFG flag is set The DAC12 0 DAC12IFG flag is automatically cleared when the DMA transfer starts A DMA transfer is triggered when ADC12IFGx is set The ADC12IFGx flag is automatically selected by the ADC12 configuration When the ADC12 performs a single or repeated conversion on a single channel the ADC12IFGx flag for conversion is the DMA trigger When the ADC12 performs a single or repeated sequence of conversions the ADC12IFGx for the last conversion in the sequence is the DMA trigger ADC121FGx flags are not automatically reset when a DMA transfer starts All ADC121FGx flags are automatically reset when the corresponding ADC12MEM x register is accessed either by software or by the DMA controller No DMA transfers triggered DMAOIFG triggers DMA channel 1 DMA1IFG triggers DMA channel 2 DMA2IFG triggers DMA channel 0 None of the DMAxIFG flags are automatically reset when the DMA transfer starts External trigger DMAEO DMA Controller 8 9 DMA Operation Edge Sensitive Triggers When DMALEVEL 0 edge sensitive triggers are used and the rising edge of the trigger signal initiates the transfer In single transfer mode each DMA transfer requires its own trigger
192. e 12C Module Operation 15 2 1 12C Serial Data One clock pulse is generated by the master device for each data bit transferred The I2C module operates with byte data Data is transferred most significant bit first as shown in Figure 15 3 The first byte after a START condition consists of a 7 bit slave address and the R W bit When R W 0 the master transmits data to a slave When R W 1 the master receives data from a slave The ACK bit is sent from the receiver after each byte on the 9th SCL clock Figure 15 3 12C Module Data Transfer i al pee so INI Z XX MSB Acknowledgement Acknowledgement Signal From Receiver Signal From Receiver s TAS 1 1 T eG 1 2 7 8 9 1 2 8 9 START 2 STOP Condition S R W ACK ACK Condition P Data on SDA must be stable during the high period of SCL as shown in Figure 15 4 The high and low state of SDA can only change when SCL is low otherwise start or stop conditions will be generated Figure 15 4 Bit Transfer on the 12 Bus Data Line Stable Data SCL Change of Data Allowed USART Peripheral Interface I C Mode 15 5 12C Module Operation 15 2 2 12C START and STOP Conditions START and STOP conditions are generated by the master and are shown in Figure 15 5 A START condition is a high to low transition on the SDA line while SCL is high A STOP condition is a low to high transition on the SDA line while SCL is hi
193. e 12 2 The number of timer counts in the period is TBCLO 1 When the timer value equals TBCLO the timer restarts counting from zero If up mode is selected when the timer value is greater than TBCLO the timer immediately restarts counting from zero Figure 12 2 Up Mode TBR max TBCLO Oh The TBCCRO CCIFG interrupt flag is set when the timer equals the TBCLO value The TBIFG interrupt flag is set when the timer counts from TBCLO to zero Figure 11 3 shows the flag set cycle Figure 12 3 Up Mode Flag Setting Timer Set TBIFG Set TBCCRO CCIFG Changing the Period Register TBCLO 12 6 Timer B When changing TBCLO while the timer is running and when the TBCLO load mode is immediate if the new period is greater than or equal to the old period or greater than the current count value the timer counts up to the new period If the new period is less than the current count value the timer rolls to zero However one additional count may occur before the counter rolls to zero Timer B Operation Continuous Mode In continuous mode the timer repeatedly counts up to TBR may and restarts from zero as shown in Figure 12 4 The compare latch TBCLO works the same way as the other capture compare registers Figure 12 4 Continuous Mode TBR max Oh The TBIFG interrupt flag is set when the timer counts from TBR max to zero Figure 12 5 shows the flag set cycle Figure 12
194. e Initial Conditions After System Reset 2 5 2 252 Interr pts a os fakes Lee A is HE honed a ih ah du bale its 2 6 2 2 1 Non Maskable Interrupts NMI sees 2 7 2 2 2 Maskable lt 8 8 2 10 2 2 3 Interrupt Processirigr sss otre re i eve VE X RW QETW 2 11 ZLA Interrupt Vectors v sve oy pines VER ES UG eae Gee Ex Rx 2 13 2 2 5 Special Function Registers 2 13 2 3 Operating Modes sieeve cae rr ne EROR RR I EC RAGIONE EE RR RUE 2 14 2 8 1 Entering and Exiting Low Power Modes 2 16 2 4 Principles for Low Power Applications 2 17 2 5 Connection of Unused Pins 000 cece eee 2 17 vii Contents 3 RISC6 BIUCPU nuns a IRR RR 3 1 3 1 CPU Introduction menie a ee ata eee ts eee eee 3 2 3 2 GPU Reglsters serrie i r E DIR MORIA ODORE apo dde ade duo 3 4 3 2 1 Program Counter PC sssssssssssssssssse ns 3 4 3 2 2 Stack Pointer i oe bald dane ER Preterea Run pede 3 5 3 2 8 Status Register SR 0 0 eect tenes 3 6 3 2 4 Constant Generator Registers CG1 and CG2 3 7 3 2 5 General Purpose Registers R4 R15 3 8 3 3 Addressing Modes
195. e and convert function is available When MSC 1 and CONSEQx gt 0 the first rising edge of the SHI signal triggers the first conversion Successive conversions are triggered automatically as soon as the prior conversion is completed Additional rising edges on SHI are ignored until the sequence is completed in the single sequence mode or until the ENC bit is toggled in repeat single channel orrepeated sequence modes The function of the ENC bit is unchanged when using the MSC bit Stopping Conversions Stopping ADC10 activity depends on the mode of operation The recommended ways to stop an active conversion or conversion sequence are Resetting ENC in single channel single conversion mode stops a conversion immediately and the results are unpredictable For correct results poll the ADC10BUSY bit until reset before clearing ENC Li Resetting ENC during repeat single channel operation stops the converter at the end of the current conversion Resetting ENC during a sequence or repeat sequence mode stops the converter at the end of the sequence Any conversion mode may be stopped immediately by setting the CONSEQx 0 and resetting the ENC bit Conversion data is unreliable 18 14 ADC10 ADC10 Operation 18 2 6 ADC10 Data Transfer Controller The ADC10 includes a data transfer controller DTC to automatically transfer conversion results from ADC10MEM to other on chip memory locations The DTC is enabled by setting the ADC1
196. e completed 1 Data is transferred continuously DTC operation is stopped only if ADC10CT cleared or ADC10SA is written to ADC10 block one This bit indicates for two block mode which block is filled with ADC10 conversion results ADC10B1 is valid only after ADC10IFG has been set the first time during DTC operation ADC10TB must also be set 0 Block 1 is filled 1 Block 2 is filled This bit should normally be reset ADC10 Registers ADC10DTC1 Data Transfer Control Register 1 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 DTC Bits DTC transfers These bits define the number of transfers in each block Transfers 7 0 0 DTC is disabled O1h OFFh Number of transfers per block ADC10SA Start Address Register for Data Transfer 15 14 13 12 11 10 9 8 ADC10SAx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 1 rw 0 7 6 5 4 3 2 1 ADC10SAx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ro BH ADC10SAx Bits ADC10 start address These bits are the start address for the DTC A write 15 1 to register ADC10SA is required to initiate DTC transfers Unused Bit 0 Unused Read only Always read as 0 ADC10 18 31 18 32 ADC10 Chapter 19 DAC12 The DAC12 module is a 12 bit voltage output digital to analog converter This chapter describes the DAC12 Two DAC12 modules are implemented in the MSP430x15x and MSP430x16x devices Topic Page 19 1 DAC 12Introduction onn TESTER eere eee 19 2 9
197. e counter must be in the process of counting for the action to take place If a particular value is directly written to the counter then an associated action does not take place 12 1 1 Similarities and Differences From Timer A 12 2 Timer B Timer B is identical to Timer A with the following exceptions The length of Timer B is programmable to be 8 10 12 or 16 bits Li Timer B TBCCRx registers are double buffered and can be grouped All Timer B outputs can be put into a high impedance state The SCCI bit function is not implemented in Timer B Figure 12 1 TBCLK ACLK SMCLK INCLK Timer_B Block Diagram Timer_B Introduction 1 Timer Block TBSSELx IDx Timer Clock MCx 1 15 0 i 1 n 1 00 Divider 16 bit Timer Count oi 1 2 4 8 gt TBR RC EQUO Clear 8 10 12 16 10 CNTLx 11 TBCLR 00 TBCLGRPx 01 SetTBIFG 10 Group T i Load Logic CCRO CCR1 CCR2 CCR3 CCR4 CCR5 CCR6 1 1 i i CCI6A 00 Capture ccieB 01 Mode EN TBCCR6 GND 19 Timer Clock Sync ocre VCC 11 y i i CLLDx Capture Latch TBCL6 i Load Logic i 1 V 1 1 i EQUO UP DOWN EQU6 cap 1 Set TBCCR6 CCIFG i 1 i OUT I Output i 1 EQUO Unit6 OUTS Signal 1 I 1 OUTMODx i a ee l Saa ela ih aah Ka a a
198. ecific data sheet for parameters Selecting the temperature sensor automatically turns on the on chip reference generator as a voltage source forthe temperature sensor However it does not enable the Vggr output or affect the reference selections for the conversion The reference choices for converting the temperature sensor are the same as with any other channel Figure 17 10 Typical Temperature Sensor Transfer Function 17 16 ADC12 Volts 1 300 1 200 1 100 1 000 0 900 VTEMP 0 00355 TEMPC 0 986 0 800 0 700 Celsius ADC12 Operation 17 2 9 ADC12 Grounding and Noise Considerations As with any high resolution ADC appropriate printed circuit board layout and grounding techniques should be followed to eliminate ground loops unwanted parasitic effects and noise Ground loops are formed when return current from the A D flows through paths that are common with other analog or digital circuitry If care is not taken this current can generate small unwanted offset voltages that can add to or subtract from the reference or input voltages of the A D converter The connections shown in Figure 17 11 help avoid this In addition to grounding ripple and noise spikes on the power supply lines due to digital switching or switching power supplies can corrupt the conversion result A noise free design using separate analog and digital ground planes with a single point connection is recommend to achieve high accu
199. ection conversion memory selection etc The typical temperature sensor transfer function is shown in Figure 18 13 When using the temperature sensor the sample period must be greater than 30 us The temperature sensor offset error can be large and may need to be calibrated for most applications See the device specific data sheet for the parameters Selecting the temperature sensor automatically turns on the on chip reference generator as a voltage source for the temperature sensor However it does not enable the Vref output or affect the reference selections for the conversion The reference choices for converting the temperature sensor are the same as with any other channel Figure 18 14 Typical Temperature Sensor Transfer Function Volts 1 300 1 200 1 100 1 000 0 900 0 800 0 700 VTEMP 0 00355 TEMPc 0 986 Celsius ADC10 18 21 ADC10 Operation 18 2 8 A D Grounding and Noise Considerations As with any high resolution ADC appropriate printed circuit board layout and grounding techniques should be followed to eliminate ground loops unwanted parasitic effects and noise Ground loops are formed when return current from the A D flows through paths that are common with other analog or digital circuitry If care is not taken this current can generate small unwanted offset voltages that can add to or subtract from the reference or input voltages of the A D converter The connections shown in Figure
200. ed If bit 9 of R8 is set a branch is taken to label TOM BIT 0200h R8 bit 9 of R8 set JNZ TOM Yes branch to TOM No proceed If bit 3 of R8 is set a branch is taken to label TOM BIT B 8 R8 JC TOM A serial communication receive bit RCV is tested Because the carry bit is equal to the state of the tested bit while using the BIT instruction to test a single bit the carry bit is used by the subsequent instruction the read information is shifted into register RECBUF Serial communication with LSB is shifted first XXXX XXXX XXXX BIT B RCV RCCTL Bit info into carry RRC RECBUF Carry gt MSB of RECBUF CXXX XXXX ds repeat previous two instructions m 8 times CCCC CCCC MSB LSB Serial communication with MSB is shifted first BIT B RCV RCCTL Bit info into carry RLC B RECBUF Carry LSB of RECBUF XXXX XXXC SS repeat previous two instructions uns 8 times CCCC CCCC sl LSB MSB RISC 16 Bit CPU 3 27 Instruction Set BR BRANCH Syntax Operation Emulation Description Status Bits Example Branch to destination BR dst dst PC MOV dst PC An unconditional branch is taken to an address anywhere in the 64K address space All source addressing modes can be used The branch instruction is a word instruction Status bits are not affected Examples for all addressing modes are given BR EXEC Branch to label EXEC or direct branch e
201. ed OSCOFF CPUOFF and GIE are not affected The contents of the status register and R8 are saved on the stack PUSH SR save status register PUSH R8 save R8 The contents of the peripheral TCDAT is saved on the stack PUSH B amp TCDAT save data from 8 bit peripheral module address TCDAT onto stack Note The System Stack Pointer The system stack pointer SP is always decremented by two independent of the byte suffix 1 RISC 16 Bit CPU 3 55 Instruction Set RET Return from subroutine Syntax RET Operation SP PC SP 2 SP Emulation MOV SP PC Description The return address pushed onto the stack by a CALL instruction is moved to the program counter The program continues at the code address following the subroutine call Status Bits Status bits are not affected 3 56 RISC 16 Bit CPU Instruction Set RETI Return from interrupt Syntax RETI Operation TOS SR SP 2 SP TOS PC SP 2 SP Description The status register is restored to the value at the beginning of the interrupt service routine by replacing the present SR contents with the TOS contents The stack pointer SP is incremented by two The program counter is restored to the value at the beginning of interrupt service This is the consecutive step after the interrupted program flow Restoration is performed by replacing the present PC contents with the TOS memory contents The
202. ed into UxRXBUF before the previous character was read OE is automatically reset when UxRXBUF is read when SWRST 1 or can be reset by software 0 No error 1 Overrun error occurred Unused Bit 4 Unused Unused Bit 3 Unused Unused Bit 2 Unused Unused Bit 1 Unused Unused Bit 0 Unused 14 16 USART Peripheral Interface SPI Mode USART Registers SP Mode UxBRO USART Baud Rate Control Register 0 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw UxBR1 USART Baud Rate Control Register 1 7 6 5 4 3 2 1 0 ee qp ee e rw rw rw rw rw rw rw rw UxBRx The baud rate generator uses the content of UxBR1 UxBR0O to set the baud rate The smallest division factor is two UxMCTL USART Modulation Control Register 7 6 5 4 3 2 1 0 ER EREGEXEXEXESXEN rw rw rw rw rw rw rw rw UxMCTLx Bits The modulation control register is not used for SPI mode and should be set 7 0 to 000h USART Peripheral Interface SPI Mode 14 17 USART Registers SPI Mode UxRXBUF USART Receive Buffer Register 7 6 5 4 3 2 1 0 EXEZAENENEEZESERES r r r r r r r r UxRXBUFx Bits The receive data buffer is user accessible and contains the last received 7 0 character from the receive shift register Reading UxRXBUF resets the OE bit and URXIFGx flag In 7 bit data mode UxRXBUF is LSB justified and the MSB is always reset UxTXBUF USART Transmit Buffer Register 7 6 5 4 3 2 1 0 EXE rw rw rw rw rw rw rw rw UxTXBUFx Bits The transmit
203. ed or transmitted the next bit in the modulation control register determines the timing for that bit A set modulation bit increases the division factor by one while a cleared modulation bit maintains the division factor given by UxBR The timing for the start bit is determined by UxBR plus the next bit is determined by UxBR plus m1 and so on The modulation sequence begins with the LSB When the character is greater than 8 bits the modulation sequence restarts with and continues until all bits are processed Determining the Modulation Value 18 12 Determining the modulation value is an interactive process Using the timing error formula provided beginning with the start bit the individual bit errors are calculated with the corresponding modulator bit set and cleared The modulation bit setting with the lower error is selected and the next bit error is calculated This process is continued until all bit errors are minimized When a frame contains more than 8 bits the modulation bits repeat For example the 9th bit of a frame uses modulation bit 0 USART Peripheral Interface UART Mode USART Operation UART Mode Transmit Bit Timing The timing for each character is the sum of the individual bit timings By modulating each bit the cumulative bit error is reduced The individual bit error can be calculated by o baud rate i pen ee Error 96 BRCLK u 1 x UxBR Zm j n x 100 With baud rate Desi
204. el sensitive DMAEN Bit 4 DMA enable 0 Disabled 1 Enabled DMAIFG Bit 3 DMA interrupt flag 0 No interrupt pending 1 Interrupt pending DMAIE Bit 2 DMA interrupt enable 0 Disabled 1 Enabled DMA Bit 1 DMA Abort This bit indicates if a DMA transfer was interrupt by an NMI ABORT 0 DMA transfer not interrupted 1 DMA transfer was interrupted by NMI DMAREQ Bit 0 DMA request Software controlled DMA start DMAREQ is Reset automatically 0 No DMA start 1 Start DMA DMAxSA DMA Source Address Register 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw DMAxSAx Bits DMA source address The source address register points to the DMA source 15 0 address for single transfers orthe first source address for block transfers The source address register remains unchanged during block and burst block transfers 8 18 DMA Controller DMA Registers DMAxDA DMA Destination Address Register 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw DMAxDAx Bits DMA destination address The destination address register points to the 15 0 destination address for single transfers or the first address for block transfers The DMAxDA register remains unchanged during block and burst block transfers DMAxSZ DMA Size Address Register 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw DMAxSZx Bits DMA size The DMA size register defi
205. emory xxxAh xxx9h xxx8h xxx7h xxx6h Word High Byte xxxbh Word Low Byte xxx4h Introduction 1 5 Introduction Chapter 2 System Resets Interrupts and Operating Modes This chapter describes the MSP430x1xx system resets interrupts and operating modes Topic Page 2 1 System Reset and 1 2 2 2 2 ACU NS 2 6 2 32 Operating Modes 33677775 2 14 2 4 Principles for Low Power Applications 2 17 2 5 Connection of Unused Pins 2 17 2 1 System Reset and Initialization 2 1 System Reset and Initialization The system reset circuitry shown in Figure 2 1 sources both a power on reset POR and a power up clear PUC signal Different events trigger these reset signals and different initial conditions exist depending on which signal was generated Figure 2 1 Power On Reset and Power Up Clear Schematic Vcc Voc i Detect Delay POR oV OV RST NMI gt gt ____ NMI WDTCTL S T m X m _ WDTQn WDTIEGT Resetwd1 PUC EQut Resetwd2 KEYV from flash module MCLK t From watchdog timer peripheral module A POR is a device reset A POR is only generated by the following two events Powering up the device A low signal on the RST NMI pin when configured in the reset mode A
206. en an address character is received the receiver is temporarily activated to transfer the character to UXRXBUF and sets the URXIFGx interrupt flag Any applicable error flag is also set The user can then validate the received address If an address is received user software can validate the address and must reset URXWIE to continue receiving data If URXWIE remains set only address characters will be received The URXWIE bit is not modified by the USART hardware automatically For address transmission in idle line multiprocessor format a precise idle period can be generated by the USART to generate address character identifiers on UTXDx The wake up temporary WUT flag is an internal flag double buffered with the user accessible TXWAKE bit When the transmitter is loaded from UxTXBUF WUT is also loaded from TXWAKE resetting the TXWAKE bit The following procedure sends out an idle frame to indicate an address character will follow 1 Set TXWAKE then write any character to UXTXBUF UxTXBUF must be ready for new data UTXIFGx 1 The TXWAKE value is shifted to WUT and the contents of UXTXBUF are shifted to the transmit shift register when the shift register is ready for new data This sets WUT which suppresses the start data and parity bits of a normal transmission then transmits an idle period of exactly 11 bits When two stop bits are usedforthe idle line the second stop bit is counted as the first mark bit of the idle period
207. ending until the completion of the DMA transfer NMI interrupts can interrupt the DMA controller if the ENNMI bit is set System interrupt service routines are interrupted by DMA events If an interrupt service routine or other routine must execute with no interruptions the DMA controller should be disabled prior to executing the routine 8 2 8 DMA Controller Interrupts Each DMA channel has its own DMAIFG flag Each DMAIFG flag is set in any mode when the corresponding DMAxSZ register counts to zero If the corre sponding DMAIE and GIE bits are set an interrupt request is generated All DMAIFG flags source only one DMA controller interrupt vector and the interrupt vector is shared with the DAC12 module Software must check the DMAIFG and DAC12IFG flags to determine the source of the interrupt The DMAIFG flags are not reset automatically and must be reset by software DMA Controller 8 13 DMA Registers 8 3 DMA Registers The DMA registers are listed in Table 8 3 Table 8 3 DMA Registers Register Short Form Register Type Address Initial State DMA control 0 DMACTLO Read write 0122h Reset with POR DMA control 1 DMACTL1 Read write 0124h Reset with POR DMA channel 0 control DMAOCTL Read write 01E0h Reset with POR DMA channel 0 source address DMAOSA Read write 01E2h Unchanged DMA channel 0 destination address DMAODA Read write 01E4h Unchanged DMA channel 0 transfer size DMAOSZ Read write 01E6h Unchanged DMA channel 1 control DMA1C
208. ents decay and settle before causing errant conversion Figure 18 2 Analog Multiplexer Analog Port Selection R 1000hm INCHx e m i ESD Protection The ADC10 external inputs AO to A4 and Vengr and Vppr share terminals with I O port P2 which are digital CMOS gates Optional inputs A5 to A7 are shared on port P3 on selected devices see device specific data sheet When analog signals are applied to digital CMOS gates parasitic current can flow from Vcc to GND This parasitic current occurs if the input voltage is near the transition level of the gate Disabling the port pin buffer eliminates the parasitic current flow and therefore reduces overall current consumption The ADC10AEx bits provide the ability to disable the port pin input buffer P2 3 configured for analog input BIS B 4h amp ADC10AE P2 3 ADC10 function and enable BIC B 4h amp P2DIR P2 3 input direction ADC10 18 5 ADC10 Operation 18 2 3 Voltage Reference Generator The ADC10 module contains a built in voltage reference with two selectable voltage levels 1 5 V and 2 5 V Either of these reference voltages may be used internally and externally on pin VREF Setting REFON 1 enables the internal reference When REF2 5V 1 the internal reference is 2 5 V the reference is 1 5 V when REF2 5V 0 External references may be supplied for Vp and Vp through pins A4 and respectively Low Power Applications 18 6 ADC1
209. equence of channels is converted of channels repeatedly ADC12 ADC12 Operation Single Channel Single Conversion Mode A single channel is sampled and converted once The ADC result is written to the ADC12MEM x defined by the CSTARTADDX bits Figure 17 6 shows the flow of the Single Channel Single Conversion mode When ADC12SC triggers a conversion successive conversions can be triggered by the ADC12SC bit When any other trigger source is used ENC must be toggled between each conversion Figure 17 6 Single Channel Single Conversion Mode CONSEQx 00 ADC120N 1 x CSTARTADDx Wait for Enable SHSx 0 l and ENC 1or 4 and ADC12SC 4 Wait for Trigger ENC O0 SAMPCON 4 HE SAMPCON 1 is Sample Input Channel Defined in ENC ot ADC12MCTLx D SAMPCON Y i 12 x ADC12CLK M ENC ot 1 x ADC12CLK Ne Conversion N Completed EE Result Stored Into ADC12MEMXx ADC12IFG x is Set x pointer to ADC12MCTLx TConversion result is unpredictable ADC12 17 11 ADC12 Operation Sequence of Channels Mode A sequence of channels is sampled and converted once The ADC results are written to the conversion memories starting with the ADCMEMX defined by the CSTARTADDx bits The sequence stops after the measurement of the channel with a set EOS bit Figure 17 7 shows the sequence of channels mode When ADC12SC triggers a sequence successive seq
210. er LPMO on is executed Example BIS GI E CPUOFF SR BIC CPUOFF 0 SP RETI Enter LPM3 Example BIS GI BIC RETI Extended Time in Low Power Modes E CPUOFF SCG1 SCG0 SR Ld rd Ld F Exit LPMO Interrupt Service Routine Exit Exit LPM3 Interrupt Service Routine CPUOFF SCG1 SCGO0 0 SP Exit Enter LPMO Program stops nere LPMO on RETI Enter LPM3 Program stops nere LPM3 on RETI The negative temperature coefficient of the DCO should be considered when the DCO is disabled for extended low power mode periods If the temperature changes significantly the DCO frequency at wake up may be significantly different from when the low power mode was entered and may be out of the specified operating range To avoid this the DCO can be set to it lowest value before entering the low power mode for extended periods of time where temperature can change 2 16 Enter LPM4 BIC RS BIS GI BIC RETI EL2 RSEL1 RS ELO amp BCSCTL1 E CPUO System Resets Interrupts and Operating Modes nterrupt Service Routine CPUOFF OSCOFF SCG1 SCG0 0 SR FEF OSCOFF SCG1 SCG0 SR Example with lowest DCO Setting Lowest RSEL Enter LPM Program s 4 tops Exit LPM4 on RETI Principles for Low Power Applications 2 4 Principles for Low Power Applications Often the
211. er_B The timer clock TBCLK can be sourced from ACLK SMCLK or externally via TBCLK or INCLK The clock source is selected with the TBSSELx bits The selected clock source may be passed directly to the timer or divided by 2 4 or 8 using the IDx bits Timer B Operation 12 2 2 Starting the Timer The timer may be started or restarted in the following ways The timer counts when MCx gt 0 and the clock source is active When the timer mode is either up or up down the timer may be stopped by loading 0 to TBCLO The timer may then be restarted by loading a nonzero value to TBCLO In this scenario the timer starts incrementing in the up direction from zero 12 2 3 Timer Mode Control The timer has four modes of operation as described in Table 12 1 stop up continuous and up down The operating mode is selected with the MCx bits Table 12 1 Timer Modes MCx Mode Description 00 Stop The timer is halted 01 Up The timer repeatedly counts from zero to the value of compare register TBCLO 10 Continuous The timer repeatedly counts from zero to the value se lected by the TBCNTLx bits 11 Up down The timer repeatedly counts from zero up to the value of TBCLO and then back down to zero Timer B 12 5 Timer B Operation Up Mode The up mode is used ifthe timer period must be different from TBR may counts The timer repeatedly counts up to the value of compare latch TBCLO which defines the period as shown in Figur
212. errupt latency and return from interrupt cycles but not the task handling itself The latencies are LJ ADC12IFGO ADC121FG14 ADC12TOV and ADC12OV 16 cycles ADC12IFG15 14 cycles The interrupt handler for ADC121FG15 shows a way to check immediately if a higher prioritized interrupt occurred during the processing of ADC121FG15 This saves nine cycles if another ADC12 interrupt is pending Interrupt handler for ADC12 INT ADC12 Enter Interrupt Service Routine 6 ADD amp ADCI2IV PC Add offset to PC 3 RETI Vector 0 No interrupt 5 JMP ADOV Vector 2 ADC overflow 2 JMP ADTOV Vector 4 ADC timing overflow 2 JMP ADMO Vector 6 ADC12IFGO 2 SA Vectors 8 32 2 JMP ADM14 Vector 34 ADC12IFG14 2 Handler for ADC12IFG15 starts here No JMP required ADM15 MOV amp ADC12MEM15 xxx Move result flag is reset Other instruction needed JMP INT ADC12 Check other int pending ADC12IFG14 ADC12IFG1 handlers go here ADMO MOV amp 12 Move result flag is reset Other instruction needed RETI Return 5 ADTOV hes Handle Conv time overflow RETI Return 5 i ADOV es Handle ADCMEMx overflow RETI Return 5 ADC12 17 19 ADC12 Registers 17 3 ADC12 Registers The ADC12 registers are listed in Table 17 2 Table 17 2 ADC 12 Registers Register Short Form Register Type Address Initial State ADC12 control register 0 ADC12CTLO Read write 01
213. es only two MCLK clock cycles Byte or word and mixed byte word transfer capability Block sizes up to 65535 bytes or words Configurable transfer trigger selections Selectable edge or level triggered transfer Four transfer addressing modes LEE BE LED Single block or burst block transfer modes The DMA controller block diagram is shown in Figure 8 1 8 2 DMA Controller Figure 8 1 DMA Controller Block Diagram DMAOTSELx DMAREQ TACCR2 CCIFG TBCCR2 CCIFG I2C Receive Ready I2C Transmit Ready DAC12 OIFG ADC12 IFGx DMA2IFG DMAEO DMAREQ TACCR2 CCIFG TBCCR2 CCIFG I2C Receive Ready I2C Transmit Ready DAC12 OIFG ADC12_IFGx DMAOIFG DMAEO DMAREQ TACCR2 CCIFG TBCCR2 CCIFG I2C Receive Ready I2C Transmit Ready DAC12 OIFG ADC12 IFGx DMA1IFG DMAEO 1041002 puy uoud YNG CF DMADSTINCRx DMADTx DMADSTBYTE 3 ROUNDROBIN DMA Channel 0 DMAOSA DMAODA DMAOSZ DMASRSBYTE DMASRCINCRx DMAEN DMADSTINCRx DMADTx m DMADSTBYTE DMA Channel 1 DMA1SA DMA1DA DMA1SZ DMASRSBYTE DMASRCINCRx DMAEN DMADSTINCRx DMADTx DMADSTBYTE DMA Channel 2 DMA2SA DMA2DA DMA2SZ DMASRSBYTE DMASRCINCRx DMAEN DMAONFETCH DMA Introduction CC JTAG Active NMI Interrupt Request ENNMI Address Space Halt CPU DMA Controller 8 3 DMA Operation 8 2 DMA Operation The DMA controller is configured with user software The setup and operation of
214. ess contents of R10 to the destination address contents of R11 The registers are not modified Comment Valid only for source operand The substitute for destination operand is 0 Rd Example MOV B QR10 0 R11 Before After f Address Register Address Register Space Space Oxxxxh Oxxxxh PC OFF16h OFF 14h OFF12h 0000h R10 OFA33h OFF16h 0000h R10 OFA33h O4AEBh PC R11 002A7h OFF14h O4AEBh R11 002A7h OFA34h Oxxxxh OFA34h OFA32h 05BC1h OFA32h 05BC1h 002A8h 002A7h 002A6h 002A8h 002A7h 002A6h 3 14 RISC 16 Bit CPU Indirect Autoincrement Mode Addressing Modes The indirect autoincrement mode is described in Table 3 9 Table 3 9 Indirect Autoincrement Mode Description Assembler Code MOV R10 0 R11 Length One or two words Operation Content of ROM MOV R10 0 R11 Move the contents of the source address contents of R10 to the destination address contents of R11 Register R10 is incremented by 1 for a byte operation or 2 for a word operation after the fetch it points to the next address without any overhead This is useful for table processing Comment Valid only for source operand The substitute for destination operand is O Rd plus second instruction INCD Rd Example MOV Before Address Space Register OFF18h OFF16h OFF 14h OFF12h OFA34h OFA32h OFA30h 010AAh 010A8h 010A6h R10 0 R11 Address Space ooo
215. evels for SVS and Brownout Reset Circuit Software Sets VLD gt 0 Aoc SVS_IT VsvSstart a FR a i O V hys SVS IT MB 1 6C start Reape ee ie ype ee Brownout Out gt Brownout Region Region 1 9 t SVSout A d BOR SVS Circuit Active gt d BOR 1 0 IN la SVSon Set POR 1 0 1 undefined 6 6 Supply Voltage Supervisor 6 3 SVS Registers The SVS registers are listed in Table 6 1 Table 6 1 SVS Registers Register SVS Control Register SVS Registers Short Form Register Type Address Initial State SVSCTL Read write 050h Reset with POR SVSCTL SVS Control Register 7 6 5 4 rw 0 VLDx PORON SVSON SVSOP SVSFG rw 0 Bits 7 4 Bit 3 Bit 2 Bit 1 Bit 0 rw 0 rw 0 3 2 1 0 rw 0 r r rw 0 Voltage level detect These bits turn on the SVS and select the nominal SVS threshold voltage level See the device specific datasheet for parameters 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 SVS is off 1 9 V 24V 2 2 V 2 3 V 2 4 V 2 5 V 2 65 V 2 8 V 2 9 V 3 05 3 2 V 3 35 V 3 5 V 3 7 V Compares external input voltage SVSin to 1 2 V POR on This bit enables the SVSFG flag to cause a POR device reset 0 1 SVSFG does not cause a P
216. external analog signals The Comparator A block diagram is shown in Figure 16 1 Features of Comparator_A include d d d d d d Inverting and non inverting terminal input multiplexer Software selectable RC filter for the comparator output Output provided to Timer A capture input Software control of the port input buffer Interrupt capability Selectable reference voltage generator Comparator and reference generator can be powered down Figure 16 1 Comparator A Block Diagram Voc 0V 2 CAON CA1 Ge P2CA1 16 2 Comparator A CARSEL 9 EE enr 2 gt CCHB 1 l Wve CAOUT NA D Lj Set CAIFG Tau 2 0us OV CAREFx D 5 o 0 5x Voc 0 25x VCC CE Gylis SF Comparator A Operation 16 2 Comparator A Operation 16 2 1 Comparator The comparator A module is configured with user software The setup and operation of comparator A is discussed in the following sections The comparator compares the analog voltages at the and input terminals If the terminal is more positive than the terminal the comparator output CAOUT is high The comparator can be switched on or off using control bit CAON The comparator should be switched off when not in use to reduce current consumption When the comparator is switched off the CAOUT is always low 16 2 2 Input Analog Switches The ana
217. fer register UORXBUF Read 076h Unchanged Transmit buffer register UOTXBUF Read write 077h Unchanged SFR module enable register 11 ME1 Read write 004h 000h after PUC SFR interrupt enable register 1 IE1 Read write 000h 000h after PUC SFR interrupt flag register 1 IFG1 Read write 002h 082h after PUC t Does not apply to 12xx devices Refer to the register definitions for registers and bit positions for these devices Table 13 4 USART1 Control and Status Registers Register Short Form Register Type Address Initial State USART control register U1CTL Read write 078h 001h after PUC Transmit control register U1TCTL Read write 079h 001h after PUC Receive control register U1RCTL Read write 07Ah 000h after PUC Modulation control register U1MCTL Read write 07Bh Unchanged Baud rate control register 0 U1BRO Read write 07Ch Unchanged Baud rate control register 1 U1BR1 Read write 07Dh Unchanged Receive buffer register U1RXBUF Read 07Eh Unchanged Transmit buffer register U1TXBUF Read write 07Fh Unchanged SFR module enable register 2 ME2 Read write 005h 000h after PUC SFR interrupt enable register 2 IE2 Read write 001h 000h after PUC SFR interrupt flag register 2 IFG2 Read write 003h 000h after PUC Note Modifying SFR bits To avoid modifying control bits of other modules it is recommended to set or clear the IEx and IFGx bits using BIS B or BIC B instructions rather than MOV B Or CLR B instructions E M M
218. gh The busy bit I2CBB is set after a START and cleared after a STOP Figure 15 5 12C Module START and STOP Conditions START STOP Condition S Condition P 15 6 USART Peripheral Interface 12C Mode 12C Module Operation 15 2 3 12C Addressing Modes The 12C module supports7 bit and 10 bit addressing modes 7 Bit Addressing In the 7 bit addressing format shown in Figure 15 6 the first byte is the 7 bit slave address and the R W bit The ACK bit is sent from the receiver after each byte Figure 15 6 12C Module 7 Bit Addressing Format Pete 8 8 Slave Address ACK Data ACK P 10 Bit Addressing In the 10 bit addressing format shown in Figure 15 7 the first byte is made up of 11110b plus the two MSBs of the 10 bit slave address and the R W bit The ACK bit is sent from the receiver after each byte The next byte is the remaining 8 bits of the 10 bit slave address followed by the ACK bit and the 8 bit data Figure 15 7 12C Module 10 Bit Addressing Format t 8 1 eis Slave Address 1st byte Slave Address 2nd byt ACK Data ACK P 1 31 31 10 X XJ Repeated Start Conditions The direction of data flow on SDA can be changed by the master without first stopping a transfer by issuing a repeated START condition This is called a RESTART After a RESTART is issued the slave address is again sent out with the new d
219. gic high is overruled by the opposing master generating a logic low The arbitration procedure gives priority to the device that transmits the serial data stream with the lowest binary value The master transmitter that lost arbitration switches to the slave receiver mode and sets the arbitration lost flag ALIFG If two or more devices send identical first bytes arbitration continues on the subsequent bytes Figure 15 11 Arbitration Procedure Between Two Master Transmitters Bus Line SCL Data From Device 1 Data From Device 2 Bus Line SDA AV NY Nu Noi Device 1 Lost Arbitration x and Switches Off n If the arbitration procedure is in progress when a repeated START condition or STOP condition is transmitted on SDA the master transmitters involved in arbitration must send the repeated START condition or STOP condition at the same position in the format frame Arbitration is not allowed between Arepeated START condition and a data bit A STOP condition and a data bit Arepeated START condition and a STOP condition USART Peripheral Interface I C Mode 15 11 12C Module Operation Slave Mode In slave mode transmit and receive operations are controlled automatically by the 12C module The slave transmitter and slave receiver modes are shown in Figure 15 12 and Figure 15 13 In slave receiver mode serial data bits received on SDA are shifted in with the clock pulses that are generated by the m
220. h Test BUSY Loop while busy Clear WRT Set LOCK Re enable WDT Enable interrupts Block Write Flash Memory Operation The block write can be used to accelerate the flash write process when many sequential bytes or words need to be programmed A block is 64 bytes starting at Oxx00h Oxx40h Oxx80h or OxxCOh and ending at Oxx3Fh Oxx7Fh OxxBFh or OxxFFh as shown in Figure 5 10 The flash programming voltage remains on for the duration of writing the 64 byte block Figure 5 10 Flash Memory Blocks A block write cannot be initiated from within flash memory The block write mustbe initiated from RAM or ROM only The BUSY bit remains set throughout the duration of the block write The WAIT bit must be checked between writing each byte or word in the block When WAIT is set the next byte or word of the block can be written When writing successive blocks the BLKWRT bit must be cleared after the current block is complete BLKWRT can be set initiating the next block write after the required flash recovery time given by t end BUSY is cleared following each block write completion indicating the next block can be written Figure 5 11 shows the block write timing Figure 5 11 Block Write Cycle Timing BLKWRT bit Write to Flash e g MOV 123h amp Flash Y Prog BUSY gt liblockwrite byteo 30 fterG tbytes 1 63 20 f ErG t bytes1 63 20 f EG tena 9f FG WAIT L i L
221. h PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC 9 7 9 8 Digital O Watchdog Timer The watchdog timer is a 16 bit timer that can be used as a watchdog or as an interval timer This chapter describes the watchdog timer The watchdog timer is implemented in all MSP430x1xx devices Topic Page 10 1 Watchdog Timer Introduction uses 10 2 10 2 Watchdog Timer Operation 10 4 10 2 Watchdog Timer Registers 10 7 10 1 Watchdog Timer Introduction 10 1 Watchdog Timer Introduction 10 2 The primary function of the watchdog timer WDT module is to perform a controlled system restart after a software problem occurs If the selected time interval expires a system reset is generated If the watchdog function is not needed in an application the module can be configured as an interval timer and can generate interrupts at selected time intervals Features of the watchdog timer module include Eight software selectable time intervals Watchdog mode Interval mode Access to WDT control register is password protected Control of RST NMI pin function Selectable clock source LJ LE GELOGL GLO L Q Can be stopped to conserve power The WDT block diagram is shown in Figure 9 1 p LATUM E PA TT T S
222. h flag requested an interrupt The highest priority enabled interrupt generates a number in the I2CIV register This number can be evaluated or added to the program counter to automatically enter the appropriate software routine Disabled 12C interrupts do not affect the I2CIV value Any access reador write ofthe I2CIV register automatically resets the highest pending interrupt flag If another interrupt flag is set another interrupt is immediately generated after servicing the initial interrupt I2CIV Software Example The following software example shows the recommended use of I2CIV The I2CIV value is added to the PC to automatically jump to the appropriate routine I2C STT ALI NAC OAI ARD RXR TXR GCI ISR ADD RETI JMP JMP JMP JMP JMP JMP JMP IFG ISR RETI FG ISR RETI KIFG ISR RETI FG ISR RETI DYTEG ISR RETI DYIFG ISR RETI FG ISR RETI amp I2CIV PC ALIFG ISR NACKIFG ISR OAIFG ISR ARDYIFG ISR RXRDYIFG_ISR TXRDYIFG_ISR GCIFG_ISR USART Peripheral Interface 12C Mode Add offset to jump table Vector 0 Vector 2 Vector 4 Vector 6 Vector 8 Vector 10 Vector 12 Vector 14 Vector 16 Task star Return Vector 2 Task star Return Vector 4 ask star Return Vector 6 ask star Return Vector 8 Sk star Return Vector 10 Sk star Return Vector 12 Sk star Return Vector 1
223. haracters when URXEIE 0 Non address characters when URXWIE 1 When URXEIE 1 abreak condition will set the BRK bit and the URXIFGx flag USART Peripheral Interface UART Mode USART Operation UART Mode Receive Start Edge Detect Operation The URXSE bit enables the receive start edge detection feature The recommended usage of the receive start edge feature is when BRCLK is sourced by the DCO and when the DCO is off because of low power mode operation The ultra fast turn on of the DCO allows character reception after the start edge detection When URXSE URXIEx and GIE are set and a start edge occurs on URXDx the internal signal URXS will be set When URXS is set a receive interrupt request is generated but URXIFGx is not set User software in the receive interrupt service routine can test URXIFGx to determine the source of the interrupt When URXIFGx 0 a start edge was detected and when URXIFGx 1 a valid character or break was received When the ISR determines the interrupt request was from a start edge user software toggles URXSE and must enable the BRCLK source by returning from the ISR to active mode or to a low power mode where the source is active If the ISR returns to a low power mode where the BRCLK source is inactive the character will not be received Toggling URXSE clears the URXS signal and re enables the start edge detect feature for future characters See chapter System Resets Interrupts and Operating
224. he MSB Bits 11 8 are don t care and do not effect the DAC12 core 8 bit 2s complement The DAC12 data are right justified Bit 7 is the MSB sign Bits 11 8 are don t care and do not effect the DAC12 core DAC12 19 13
225. he DAC12 output can settle The user must assure the DAC12 settling time is not violated when using the DMA controller See the device specific data sheet for parameters Cn O E 19 2 8 DAC12 Interrupts The DAC12 interrupt vector is shared with the DMA controller Software must check the DAC12IFG and DMAIFG flags to determine the source of the interrupt The DAC12IFG bit is set when DAC12xLSELx gt 0 and DAC12 data is latched from the DAC12_xDAT register into the data latch When DAC12xLSELx 0 the DAC12IFG flag is not set A set DAC12IFG bit indicates that the DAC12 is ready for new data If both the DAC12IE and GIE bits are set the DAC12IFG generates an interrupt request The DAC12IFG flag is not reset automatically It must be reset by software DAC12 19 9 DAC12 Registers 19 3 DAC12 Registers The DAC12 registers are listed in Table 19 2 Table 19 2 DAC12 Registers Register Short Form Register Type Address Initial State DAC12_0 control DAC12_0CTL Read write 01COh Reset with POR DAC12_0 data DAC12 ODAT Read write 01C8h Reset with POR DAC12_1 control DAC12_1CTL Read write 01C2h Reset with POR DAC12_1 data DAC12_1DAT Read write 01CAh Reset with POR 19 10 DAC12 DAC12 Registers DAC12 xCTL DAC12 Control Register 15 Reserved rw 0 7 rw 0 14 13 12 11 10 9 8 DAC12 DAC12SREFx DAC12RES DAC12LSELx CALON DAC12IR rw 0 6 4 3 2 1 0 DAC12 0 0 0 0 0 rw 0 rw 0 rw 0 rw
226. he TACCRO value When the previous TACCRx value plus t is greater than the TACCRO data the TACCRO value must be subtracted to obtain the correct time interval Timer A Operation Up Down Mode The up down mode is used if the timer period must be different from OFFFFh counts and if symmetrical pulse generation is needed The timer repeatedly counts up to the value of compare register TACCRO and back down to zero as shown in Figure 11 7 The period is twice the value in TACCRO Figure 11 7 Up Down Mode OFFFFh TACCRO Oh The count direction is latched This allows the timer to be stopped and then restarted in the same direction it was counting before it was stopped If this is not desired the TACLR bit must be set to clear the direction The TACLR bit also clears the TAR value and the TACLK divider In up down mode the TACCRO CCIFG interrupt flag and the TAIFG interrupt flag are set only once during a period separated by 1 2 the timer period The TACCRO CCIFG interrupt flag is set when the timer counts from TACCRO 1 to TACCRO and TAIFG is set when the timer completes counting down from 0001h to 0000h Figure 11 8 shows the flag set cycle Figure 11 8 Up Down Mode Flag Setting Up Down Set TAIFG Set TACCRO CCIFG Timer A 11 9 Timer A Operation Changing the Period Register TACCRO Use of the Up Down Figure 11 9 11 10 OFFFFh TACCRO TACCR1 TACCR2 Oh TAIFG Timer_A
227. hen the content of R6 is less than the memory pointed to by R7 the program continues at label EDE CMP QR7 R6 R6 R7 compare on signed numbers JL EDE Yes R6 lt R7 No proceed RISC 16 Bit CPU 3 47 Instruction Set JMP Jump unconditionally Syntax JMP label Operation PC 2x offset gt PC Description The 10 bit signed offset contained in the instruction LSBs is added to the program counter Status Bits Status bits are not affected Hint This one word instruction replaces the BRANCH instruction in the range of 511 to 512 words relative to the current program counter 3 48 RISC 16 Bit CPU JN Syntax Operation Description Status Bits Example L 1 Instruction Set Jump if negative JN label if N 1 PC 2x offset gt if N 2 0 execute following instruction The negative bit N of the status register is tested If itis set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If N is reset the next instruction following the jump is executed Status bits are not affected The result of a computation in R5 is to be subtracted from COUNT If the result is negative COUNT is to be cleared and the program continues execution in another path SUB R5 COUNT COUNT R5 COUNT JN L 1 If negative continue with COUNT 0 at PC L 1 Continue with COUNT20 RISC 16 Bit CPU 3 49 Instruction Set JNC JLO Syntax Operation De
228. heral Interface SPI Mode 14 11 USART Operation SPI Mode SPI Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loaded into UXRXBUF as shown in Figure 14 11 and Figure 14 12 An interrupt request is generated if URXIEx and GIE are also set URXIFGx and URXIEx are reset by a system reset PUC signal or when SWRST 1 URXIFGx is automatically reset if the pending interrupt is served or when UxRXBUF is read The operation is shown in Figure 14 11 Receive Interrupt Operation SYNC g 5 IC TRANCE CO SYNC 1 Valid Start Bit URXS ote Receiver Collects Character URXSE From URXD URXIEx Interrupt Service FER Da Requested BRKE URXEIE URXIFGx URXWIE Bo RXWAKE e m SWRST PUC UxRXBUF Read URXSE IRQA Character Received Figure 14 12 Receive Interrupt State Diagram SWRST 1 URXIFGx 0 URXIEx 0 Wait For Next Start SWRST 1 Receive Character USPIEx 0 USPIEx 0 Interrupt Service Started 0 URXIFGx 0 Receive Character Completed USPIEx 1 USPIEx 1 and URXIEx 1 and GIE 1 and Priority Valid 14 12 USART Peripheral Interface SPI Mode USART Registers SPI Mode 14 3 USART Registers SPI Mode The USART registers shown in Table 14 1 and Table 14 2 are byte structured and should be accessed using byte instructions
229. hi ma jati i pa ot pah a a a a Timer_B 12 3 Timer B Operation 12 2 Timer B Operation The Timer B module is configured with user software The setup and operation of Timer B is discussed in the following sections 12 2 1 16 Bit Timer Counter TBR Length The 16 bit timer counter register TBR increments or decrements depending on mode of operation with each rising edge of the clock signal TBR can be read or written with software Additionally the timer can generate an interrupt when it overflows TBR may be cleared by setting the TBCLR bit Setting TBCLR also clears the clock divider and count direction for up down mode P TP DSO TH a Note Modifying Timer_B Registers It is recommended to stop the timer before modifying its operation with exception of the interrupt enable and interrupt flag to avoid errant operating conditions When TBCLK is asynchronous to the CPU clock any read from TBR should occur while the timer is not operating or the results may be unpredictable Any write to TBR will take effect immediately Timer_B is configurable to operate as an 8 10 12 or 16 bit timer with the CNTLx bits The maximum count value TBR max for the selectable lengths is OFFh O3FFh OFFFh and OFFFFh respectively Data written to the TBR register in 8 10 and 12 bit mode is right justified with leading zeros Clock Source Select and Divider 12 4 Tim
230. hifted right one position The MSB is loaded with 1 SETC Prepare carry for MSB RRC R5 R5 2 8000h R5 R5 is shifted right one position The MSB is loaded with 1 SETC Prepare carry for MSB RRC B R5 R5 2 80h R5 low byte of R5 is used RISC 16 Bit CPU 3 61 Instruction Set SBC W SBC B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Subtract source and borrow NOT carry from destination Subtract source and borrow NOT carry from destination SBC dst or SBC W dst SBC B dst dst OFFFFh C dst dst OFFh C dst SUBC 0 dst SUBC B 0 dst The carry bit C is added to the destination operand minus one The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Set if an arithmetic overflow occurs reset otherwise OSCOFF CPUOFF and GIE are not affected The 16 bit counter pointed to by R13 is subtracted from a 32 bit counter pointed to by R12 SUB R13 0 R12 Subtract LSDs SBC 2 R12 Subtract carry from MSD The 8 bit counter pointed to by R13 is subtracted from a 16 bit counter pointed to by R12 SUB B R13 0 R12 Subtract LSDs SBC B 1 R12 Subtract carry from MSD Note Borrow Implementation The borrow is treated as a N
231. hile busy SMCLK 2 Clear LOCK Enable block write Write location Test WAIT Loop while WAIT 0 Point to next word Decrement write counter End of block Clear WRT BLKWRT Test BUSY Loop while busy Set LOCK Re enable WDT if needed Enable interrupts Flash Memory Controller 5 13 Flash Memory Operation 5 3 4 Flash Memory Access During Write or Erase When any write or any erase operation is initiated from RAM and while BUSY 1 the CPU may not read or write to or from any flash location Otherwise an access violation occurs ACCVIFG is set and the result is unpredictable Also if a write to flash is attempted with WRT 0 the ACCVIFG interrupt flag is set and the flash memory is unaffected When a byte word write or any erase operation is initiated from within flash memory the flash controller returns op code OSFFFh to the CPU at the next instruction fetch Op code O3FFFh is the JMP Pc instruction This causes the CPU to loop until the flash operation is finished When the operation is finished and BUSY 0 the flash controller allows the CPU to fetch the proper op code and program execution resumes The flash access conditions while BUSY 1 are listed in Table 5 3 Table 5 3 Flash Access While BUSY 1 Flash Flash WAIT Result Operation Access Read 0 ACCVIFG 1 O3FFFh is the value read Any erase or Write ACCVIFG 1 Write is ignored Byte word write i struction 0 ACCVIFG 0 CPU fetches 03FFFh
232. hmetic overflow occurs the initial value is 04000h lt dst lt OCOOOh reset otherwise Set if an arithmetic overflow occurs the initial value is 040h lt dst OCOh reset otherwise OSCOFF CPUOFF and GIE are not affected R5 is shifted left one position RLC R5 R5 x 2 C R5 The input P11N 1 information is shifted into the LSB of R5 BIT B 2 amp P1IN Information gt Carry RLC R5 0 1 LSB of R5 The MEM LEO content is shifted left one position RLC B LEO Mem LEO x 2 C Mem LEO Note RLC and RLC B Emulation The assembler does not recognize the instruction RLC RS5 It must be substituted by ADDC R5 2 R5 RISC 16 Bit CPU 3 59 Instruction Set RRA W Rotate right arithmetically RRA B Rotate right arithmetically Syntax RRA dst or RRA W dst RRA B dst Operation MSB MSB MSB gt MSB 1 LSB41 LSB LSB gt C Description The destination operand is shifted right one position as shown in Figure 3 16 The MSB is shifted into the MSB the MSB is shifted into the MSB 1 and the LSB 1 is shifted into the LSB Figure 3 16 Destination Operand Arithmetic Right Shift Word 15 0 Status Bits N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Loaded from the LSB V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example R5 is shifted right one position The MSB retains the old value It operates
233. iety of applications ADC 10 features include LE LOL IE E O d d Greater than 200 ksps maximum conversion rate Monotonic10 bit converter with no missing codes Sample and hold with programmable sample periods Conversion initiation by software or Timer A Software selectable on chip reference voltage generation 1 5 V or 2 5 V Software selectable internal or external reference Eight external input channels Conversion channels for internal temperature sensor AVcc and external references Selectable conversion clock source Single channel repeated single channel sequence and repeated sequence conversion modes ADC core and reference voltage can be powered down separately Data transfer controller for automatic storage of conversion results The block diagram of ADC10 is shown in Figure 18 1 Figure 18 1 ADC10 Block Diagram ADC10 Introduction REFOUT REFBURST Vener ADC10SR ALME x VREF 1 5 Vor2 5 V L Avec Reference VnEr4 VenErF INCHx Hi Auto CONSEQx AO SREF2 1 of Al A2 A3 Sample 9 5 AG Hold A7 S H Convert SAMPCON 11 10 01 00 TANNE ADC100N 10 bit SAR BUSY Sample Timer lt ADC10DF INCHx 0Bh Ref_x V Data Transfer Controller AAA Bs m q RC QD ap 4 8 16 64 ADC10SHTx MSC ADC10MEM ADC10SA ADC10CT ADC10TB AD
234. ifier setting These bits select settling time vs current consumption for the DAC12 input and output amplifiers DAC12AMPx Input Buffer 000 Off 001 Off 010 Low speed current 011 Low speed current 100 Low speed current 101 Medium speed current 110 Medium speed current 111 High speed current DAC12 data format 0 Straight Binary 1 2 s compliment DAC 12 interrupt enable 0 Disabled 1 Enabled DAC12 Interrupt flag 0 No interrupt pending 1 Interrupt pending Output Buffer DAC12 off output high Z DAC12 off output 0 V Low speed current Medium speed current High speed current Medium speed current High speed current High speed current DAC12 enable conversion This bit enables the DAC12 module when DAC12LSELx gt 0 when DAC12LSELx 0 DAC12ENC is ignored 0 DAC12 disabled 1 DAC12 enabled DAC12 group Groups DAC12_x with the next higher DAC12 x 0 Not grouped 1 Grouped DAC12 Registers DAC12 xDAT DAC12 Data Register 15 14 13 12 11 10 9 8 0 0 0 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Unused Bits Unused These bits are always 0 and do not affect the DAC12 core 15 12 DAC12 Data Bits DAC12 data 11 0 DAC12 Data Format DAC12 Data 12 bit binary The DAC12 data are right justified Bit 11 is the MSB 12 bit 2s complement The DAC12 data are right justified Bit 11 is the MSB sign 8 bit binary The DAC12 data are right justified Bit 7 is t
235. igitally Controlled Oscillator DCO 4 6 4 25 DGO Modulator aie ree eene tee a a es 4 9 4 2 0 Basic Clock Module Fail Safe Operation 4 10 4 2 7 Synchronization of Clock Signals 4 13 4 3 Basic Clock Module Registers 4 14 5 Flash Memory Controller eueeeeeeeeeee III II nnn 5 1 5 1 Flash Memory Introduction inie eere III 5 2 5 2 Flash Memory Segmentation 5 3 5 3 Flash Memory Operation 5 4 5 3 1 Flash Memory Timing Generator 5 4 5 3 2 Erasing Flash Memory teen 5 5 5 3 3 Writing Flash Memory seesi IH 5 8 5 3 4 Flash Memory Access During Write or Erase 5 14 5 3 5 Stopping a Write or Erase 5 15 5 3 6 Configuring and Accessing the Flash Memory Controller 5 15 5 3 7 Flash Memory Controller Interrupts 5 15 5 3 8 Programming Flash Memory Devices 5 15 5 4 Flash Memory lt 5 17 viii Contents 6 Supply Voltage Supervisor
236. ignals Each output unit has eight operating modes that generate signals based on the EQUO and EQUx signals Output Modes The output modes are defined by the OUTMODXx bits and are described in Table 11 2 The OUTx signal is changed with the rising edge of the timer clock for all modes except mode 0 Output modes 2 3 6 and 7 are not useful for output unit 0 because EQUx EQUO Table 11 2 Output Modes OUTMODx 000 001 010 011 100 101 110 111 Mode Output Set Toggle Reset Set Reset Toggle Reset Toggle Set Reset Set Description The output signal OUTx is defined by the OUTx bit The OUTx signal updates immediately when OUTx is updated The output is set when the timer counts to the TACCRx value It remains set until a reset of the timer or until another output mode is selected and affects the output The output is toggled when the timer counts to the TACCRx value It is reset when the timer counts to the TACCRO value The output is set when the timer counts to the TACCRx value It is reset when the timer counts to the TACCRO value The output is toggled when the timer counts to the TACCRx value The output period is double the timer period The output is reset when the timer counts to the TACCRx value It remains reset until another output mode is selected and affects the output The output is toggled when the timer counts to the TACCRx value It is set when the timer c
237. imer B Capture compare interrupt enable This bit enables the interrupt request of the corresponding CCIFG flag 0 Interrupt disabled 1 Interrupt enabled Capture compare input The selected input signal can be read by this bit Output This bit indicates the state of the output For output mode 0 this bit directly controls the state of the output 0 Output low 1 Output high Capture overflow This bit indicates a capture overflow occurred COV must be reset with software 0 No capture overflow occurred 1 Capture overflow occurred Capture compare interrupt flag 0 No interrupt pending 1 Interrupt pending Timer B Registers TBIV Timer B Interrupt Vector Register 15 14 13 12 11 10 9 8 ro ro ro ro ro ro ro 7 6 5 4 3 2 1 0 ro ro ro ro r 0 r 0 r 0 ro TBIVx Bits Timer B interrupt vector value 15 0 Interrupt TBIV Contents Interrupt Source Interrupt Flag Priority 00h No interrupt pending 02h Capture compare 1 TBCCR1 CCIFG Highest 04h Capture compare 2 TBCCR2 CCIFG 06h Capture compare TBCCR3 CCIFG 08h Capture compare 41 TBCCR4 CCIFG OAh Capture compare 5t TBCCR5 CCIFG OCh Capture compare 6t TBCCR6 CCIFG OEh Timer overflow TBIFG Lowest t X14x xT6x devices only Timer B 12 25 12 26 Timer B Chapter 13 USART Peripheral Interface UART Mode The universal synchronous asynchronous receive transmit USART peripheral interface supports two serial modes with one hardware module This chapter d
238. inary data format the full scale output value is OFFFh in 12 bit mode OFFh in 8 bit mode as shown in Figure 19 2 Figure 19 2 Output Voltage vs DAC12 Data 12 Bit Straight Binary Mode Output Voltage Full Scale Output DAC Data OFFFh When using 2 s compliment data format the range is shifted such that a DAC12 xDAT value of 0800h 0080h in 8 bit mode results in a zero output voltage 0000h is the mid scale output voltage and 07FFh 007Fh for 8 bit mode is the full scale voltage output as shown in Figure 19 3 Figure 19 3 Output Voltage vs DAC12 Data 12 Bit 2s Compliment Mode Output Voltage Full Scale Output Mid Scale Output 0 DAC Data 0800h 2048 0 07FFh 2047 19 6 DAC12 DAC12 Operation 19 2 5 DAC12 Output Amplifier Offset Calibration The offset voltage of the DAC12 output amplifier can be positive or negative When the offset is negative the output amplifier attempts to drive the voltage negative but cannot do so The output voltage remains at zero until the DAC12 digital input produces a sufficient positive output voltage to overcome the negative offset voltage resulting in the transfer function shown in Figure 19 4 Figure 19 4 Negative Offset Output Voltage 0 7 Negative 7 DAC Data When the output amplifier has a positive offset a digital input of zero does not result in a zero output voltage The DAC12 output voltage reaches the maximum output level before
239. ion 0 1 1 I2CNDAT is used to determine length of transmission Setting I2CSTT initiates activity A stop condition is automatically generated after IICNDAT number of bytes have been transferred 1 0 1 I2CNDAT is not used to determine length of transmission Software must control the length of the transmission Setting the I2CSTT bit initiates activity Software must set the I2CSTP bit to initiate a stop condition and stop activity This mode is useful if gt 256 bytes are to be transferred 0 1 0 Setting the I2CSTP bit generates a stop condition on the bus after I2ZCNDAT number of bytes have been sent or immediately if I2CNDAT number of bytes have already been sent 1 1 0 Setting the I2CSTP bit generates a stop condition on the bus after the current transmission completes or immediately if no transmission is currently active 1 1 1 Reserved no bus activity USART Peripheral Interface 12C Mode I2C State Diagrams Figure 15 9 Master Transmitter Mode IEC WORD 1 IDLE l2CSTT 1 4 x l2CPSC Generate Start Condition from l2CSTT 1 4 x l2CPSC I2CBB is Set 2CSTT is Cleared 8x SCL Send Slave Address bits 6 0 with R W Ack XA 1 OAK 10 bit address Send Slave Address bits 9 7 extended with R W Ack XA 0 7 bit address 12C Module Operation I2CRM 1 I2CDR Yes Stop State No Loaded 7 No I2CDR 8x SCL Written All bytes sent
240. ion Bit 1 The port pin is switched to output direction Digital I O 9 3 Digital I O Operation 9 2 4 Function Select Registers PnSEL 9 4 Digital I O Port pins are often multiplexed with other peripheral module functions See the device specific data sheet to determine pin functions Each PnSEL bit is used to select the pin function I O port or peripheral module function Bit 0 I O Function is selected for the pin Bit 1 Peripheral module function is selected for the pin Setting PnSELx 1 does not automatically set the pin direction Other peripheral module functions require the PnDIRx bits to be configured according to the direction needed for the module function Output ACLK on P2 0 on MSP430F11x1 BIS B 401h amp P2SEL Select ACLK function for pin BIS B 401h amp P2DIR Set direction to output Required S E Note P1 and P2 Interrupts Are Disabled When PnSEL 1 When any P1SELx or P2SELx bit is set the corresponding pin s interrupt function is disabled Therefore signals on these pins will not generate P1 or P2 interrupts regardless of the state of the corresponding P1IE or P2IE bit ss When a port pin is selected as an input to a peripheral the input signal to the peripheral is a latched representation of the signal at the device pin While PnSELx 1 the internal input signal follows the signal at the pin However if the PnSELx 0 the input to the peripheral
241. ion state BIS BIC TOU TOU TMOD 7 amp TBCCTLx Set output mode 7 TMODx amp TBCCTLx Clear unwanted bits LLLA A A Timer B 12 17 Timer B Operation 12 2 6 Timer B Interrupts Two interrupt vectors are associated with the 16 bit Timer B module TBCCRO interrupt vector for TBCCRO CCIFG TBIV interrupt vector for all other CCIFG flags and TBIFG In capture mode any CCIFG flag is set when a timer value is captured in the associated TBCCRx register In compare mode any CCIFG flag is set when TBR counts the associated TBCLx value Software may also set or clear any CCIFG flag All CCIFG flags request an interrupt when their corresponding CCIE bit and the GIE bit are set TBCCRO Interrupt Vector The TBCCRO CCIFG flag has the highest Timer_B interrupt priority and has a dedicated interrupt vector as shown in Figure 12 15 The TBCCRO CCIFG flag is automatically reset when the TBCCRO interrupt request is serviced Figure 12 15 Capture Compare TBCCRO Interrupt Flag Capture EQUO IRQ Interrupt Service Requested IRACC Interrupt Request Accepted TBIV Interrupt Vector Generator 12 18 Timer B The TBIFG flag and TBCCRx CCIFG flags excluding TBCCRO CCIFG are prioritized and combined to source a single interrupt vector The interrupt vector register TBIV is used to determine which flag requested an interrupt The highest priority e
242. iscusses the operation of the asynchronous UART mode USARTO is implemented on the MSP430x12xx MSP430x13xx and MSP430x15x devices In addition to USARTO the MSP430x14x and MSP430x16x devices implement a second identical USART module USART1 Topic Page 13 1 USART Introduction UART Mode 13 2 13 2 USART Operation UART Mode 13 4 13 3 USART Registers UART Mode 13 21 13 1 USART Introduction UART Mode 13 1 USART Introduction UART Mode 13 2 In asynchronous mode the USART connects the MSP430 to an external system via two external pins URXD and UTXD UART mode is selected when the SYNC bit is cleared UART mode features include m LJ O O Q C O Q 7 or 8 bit data with odd even or non parity Independent transmit and receive shift registers Separate transmit and receive buffer registers LSB first data transmit and receive Built in address bit communication protocols for multiprocessor systems Receiver start edge detection for auto wake up from LPMx modes Programmable baud rate with modulation for fractional baud rate support Status flags for error detection and suppression and address detection Independent interrupt capability for receive and transmit Figure 13 1 shows the USART when configured for UART mode USART Peripheral Interface UART Mode USART Introduction UART Mode
243. isters are used to configure P1 and P2 Four registers are used to configure ports P6 The digital I O registers are listed in Table 9 1 Register Input Output Direction Interrupt Flag Interrupt Edge Select Interrupt Enable Port Select Input Output Direction Interrupt Flag Interrupt Edge Select Interrupt Enable Port Select Input Output Direction Port Select Input Output Direction Port Select Input Output Direction Port Select Input Output Direction Port Select Short Form Address P1IN P1OUT P1DIR P1IFG P1IES P1IE P1SEL P2IN P2OUT P2DIR P2IFG 21 5 P2IE P2SEL PSIN P30UT P3DIR P3SEL P4IN PAOUT PADIR PASEL P5OUT P5DIR P5SEL P6IN PeOUT PeDIR PeSEL 020h 021h 022h 023h 024h 025h 026h 028h 029h 02Ah 02Bh 02Ch 02Dh 02Eh 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 030h 031h 032h 033h 034h 035h 036h 037h Register Type Read only Read write Read write Read write Read write Read write Read write Read only Read write Read write Read write Read write Read write Read write Read only Read write Read write Read write Read only Read write Read write Read write Read only Read write Read write Read write Read only Read write Read write Read write Digital I O Initial State Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset wit
244. it 0 Comparator_A output This bit reflects the value of the comparator output Writing this bit has no effect Comparator_A Port Disable Register CAPD CAPD7 CAPD6 CAPD5 CAPD4 CAPD3 CAPD2 CAPD1 CAPDO rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw CAPDx Bits Comparator_A port disable These bits individually disable the input buffer 7 0 for the pins of the port associated with Comparator_A For example if CAOUT is on pin P2 2 the CAPDx bits can be used to individually enable or disable each P2 x pin buffer CAPDO disables P2 0 CAPD1 disables P2 1 etc 0 The input buffer is enabled 1 The input buffer is disabled 16 10 Comparator A Chapter 17 ADC12 The ADC12 module is a high performance 12 bit analog to digital converter This chapter describes the ADC12 The ADC12 is implemented in the MSP430x13x MSP430x14x MSP430x1 5x and MSP430x16x devices Topic Page 17 1 ADGC121Introduction nny sect ermine RECENTE TET 17 2 17 29 ADG12 Operationy 9 17 4 17 3 12 57 95 e e a ea 17 20 17 1 ADCt12 Introduction 17 1 ADC12 Introduction 17 2 ADC12 The ADC12 module supports fast 12 bit analog to digital conversions The module implements a 12 bit SAR core sample select control reference generator and a 16 conversion and control buffer The conversion and control buffer allows up to 16 independent ADC samples to be converted and stored without any CP
245. it at least 50 us 4 Test OFIFG and repeat steps 1 4 until OFIFG remains cleared Select LFXT1 HF mode for MCLK BIC OSCOFF SR BIS B XTS BCSCTL1 L1 BIC B OFIFG amp IFG1 OV 0FFh R15 2 DEC R15 JNZ L2 BIT B OFIFG amp IFG1 JNZ Li BIS B SELM1 SELMO amp BCSCTL2 Basic Clock Module TUL on OSes HF mode Clear OFIFG Delay Re test OFIFG Repeat test if needed Select Basic Clock Module Operation 4 2 7 Synchronization of Clock Signals When switching MCLK or SMCLK from one clock source to the another the Switch is synchronized to avoid critical race conditions as shown in Figure 4 12 1 The current clock cycle continues until the next rising edge 2 The clock remains high until the next rising edge of the new clock 3 The new clock source is selected and continues with a full high period Figure 4 12 Switch MCLK from DCOCLK to LEXT1CLK Select LFXT1CLK v DCOCLK LFXTICLK MCLK pcocLK Wait for LFXT1GbK 9 LFXT1CLK Basic Clock Module 4 13 Basic Clock Module Registers 4 3 Basic Clock Module Registers The basic clock module registers are listed in Table 4 1 Table 4 1 Basic Clock Module Registers Register Short Form Register Type Address Initial State DCO control register DCOCTL Read write 056h 056h with PUC Basic clock system con
246. it must be set for non maskable interrupts to be requested Interrupt Acceptance The interrupt latency is 6 cycles starting with the acceptance of an interrupt request and lasting until the start of execution of the first instruction of the interrupt service routine as shown in Figure 2 7 The interrupt logic executes the following 1 Any currently executing instruction is completed 2 The PC which points to the next instruction is pushed onto the stack 3 The SR is pushed onto the stack 4 The interrupt with the highest priority is selected if multiple interrupts occurred during the last instruction and are pending for service 5 The interrupt request flag resets automatically on single source flags Multiple source flags remain set for servicing by software 6 The SR is cleared with the exception of SCGO which is left unchanged This terminates any low power mode 7 The content of the interrupt vector is loaded into the PC the program continues with the interrupt service routine at that address Figure 2 7 Interrupt Processing Before After Interrupt Interrupt TOS SP gt TOS System Resets Interrupts and Operating Modes 2 11 System Reset and Initialization Return From Interrupt The interrupt handling routine terminates with the instruction ETI return from an interrupt service routine The return from the interrupt takes 5 cycles to execute the following actions and is illus
247. k pointer is incremented by two afterwards Status bits are not affected The contents of R7 and the status register are restored from the stack POP R7 POP SR Restore R7 Restore status register The contents of RAM byte LEO is restored from the stack LEO The low byte of the stack is moved to LEO The contents of R7 is restored from the stack POP B R7 The low byte of the stack is moved to R7 the high byte of R7 is 00h The contents of the memory pointed to by R7 and the status register are restored from the stack POP B 0 R7 The low byte of the stack is moved to the the byte which is pointed to by R7 Example R7 203h Mem R7 low byte of system stack Example R7 2 20Ah Mem R7 low byte of system stack POP SR Note The System Stack Pointer The system stack pointer SP is always incremented by two independent of the byte suffix LLLLLLSS A 3 54 RISC 16 Bit CPU PUSH W PUSH B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Push word onto stack Push byte onto stack PUSH src or PUSH W src PUSH B SIC SP 2SP src gt SP The stack pointer is decremented by two then the source operand is moved to the RAM word addressed by the stack pointer TOS Status bits are not affect
248. l Internal and external parasitic effects and cross coupling on and between signal lines power supply lines and other parts of the system are responsible for this behavior as shown in Figure 16 2 The comparator output oscillation reduces accuracy and resolution of the comparison result Selecting the output filter can reduce errors associated with comparator oscillation Figure 16 2 RC Filter Response at the Output of the Comparator Terminal Terminal _ Comparator Inputs Comparator Output Unfiltered at CAOUT Comparator Output Filtered at CAOUT 16 2 4 Voltage Reference Generator The voltage reference generator is used to generate VcAngrp which can be applied to either comparator input terminal The CAREFx bits control the output of the voltage generator The CARSEL bit selects the comparator terminal to which VcAngr is applied If external signals are applied to both comparator input terminals the internal reference generator should be turned off to reduce current consumption The voltage reference generator can generate a fraction of the device s Vcc or a fixed transistor threshold voltage of 0 55 V The transistor threshold voltage has a tolerance and temperature coefficient specified in the device specific datasheet 16 4 Comparator A Comparator A Operation 16 2 5 Comparator A Port Disable Register CAPD The comparator input and output functions are multiplexed with the a
249. ll not be moved to the transmit shift register or transmitted Once UTXEx is set the data in the transmit buffer is immediately loaded into the transmit shift register and character transmission resumes USART Peripheral Interface UART Mode USART Operation UART Mode 13 2 6 UART Baud Rate Generation The USART baud rate generator is capable of producing standard baud rates from non standard source frequencies The baud rate generator uses one prescaler divider and a modulator as shown in Figure 13 7 This combination supports fractional divisors for baud rate generation The maximum USART baud rate is one third the UART source clock frequency BRCLK Figure 13 7 MSP430 Baud Rate Generator UCLKI ACLK SMCLK SMCLK 40 or 1 Compare 0 or 1 bu BITCLK gt R Modulation Data Shift Register R LSB first lt ma m7 8 A UxMCTL Bit Start Timing for each bit is shown in Figure 13 8 For each bit received a majority vote is taken to determine the bit value These samples occur at the N 2 1 N 2 and N 2 1 BRCLK periods where N is the number of BRCLKs per BITCLK Figure 13 8 BITCLK Baud Rate Timing Majority Vote m Oy Y Bit Start l y y 1 404 Eos AU UU UU UU UU L N 2 N 2 1 N 2 2 1 N2 N2 1 Counter i N 2 1 N 2 2 i i 0 i 2 N2 1 1 N mk M NTN m 0 J NEVEN INT N 2 gt INT N 2 1 Nopp INT N 2 R
250. lock source select 0 SMCLK 1 ACLK Watchdog timer interval select These bits select the watchdog timer interval to set the WDTIFG flag and or generate a PUC 00 Watchdog clock source 32768 01 Watchdog clock source 8192 10 Watchdog clock source 512 11 Watchdog clock source 64 10 8 Watchdog Timer Watchdog Timer Registers IE1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 rw 0 Bits These bits may be used by other modules See device specific datasheet 7 1 WDTIE Bit 0 Watchdog timer interrupt enable This bit enables the WDTIFG interrupt for interval timer mode It is not necessary to set this bit for watchdog mode Because other bits in IE1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled IFG1 Interrupt Flag Register 1 7 6 5 4 3 2 1 0 0 rw Bits These bits may be used by other modules See device specific datasheet 7 1 WDTIFG Bit 0 Watchdog timer interrupt flag In watchdog mode WDTIFG remains set until reset by software In interval mode WDTIFG is reset automatically by servicing the interrupt or can be reset by software Because other bits in IFG1 may be used for other modules itis recommended to clear WDTIFG by using BIS B Or BIC B instructions rather than MOV B or CLR B instructions 0 No interrupt pending 1 Interrupt pending Watchdog Timer 10 9
251. log input switches connect or disconnect the two comparator input terminals to associated port pins using the P2CAx bits Both comparator terminal inputs can be controlled individually The P2CAx bits allow L Application of an external signal to the and terminals of the comparator Routing of an internal reference voltage to an associated output port pin Internally the input switch is constructed as a T switch to suppress distortion in the signal path V7 1 Note Comparator Input Connection When the comparator is on the input terminals should be connected to a signal power or ground Otherwise floating levels may cause unexpected interrupts and increased current consumption _ _ The CAEX bit controls the input multiplexer exchanging which input signals are connected to the comparator s and terminals Additionally when the comparator terminals are exchanged the output signal from the comparator is inverted This allows the user to determine or compensate for the comparator input offset voltage Comparator A 16 3 Comparator A Operation 16 2 3 Output Filter The output of the comparator can be used with or without internal filtering When control bit CAF is set the output is filtered with an on chip RC filter Any comparator output oscillates if the voltage difference across the input terminals is smal
252. ly and as quickly as possible a multiple sample and convert function is available When MSC 1 CONSEQx gt 0 and the sample timer is used the first rising edge of the SHI signal triggers the first conversion Successive conversions are triggered automatically as soon as the prior conversion is completed Additional rising edges on SHI are ignored until the sequence is completed in the single sequence mode or until the ENC bit is toggled in repeat single channel or repeated sequence modes The function of the ENC bit is unchanged when using the MSC bit Stopping Conversions Stopping ADC12 activity depends on the mode of operation The recommended ways to stop an active conversion or conversion sequence are Resetting ENC in single channel single conversion mode stops a conversion immediately and the results are unpredictable For correct results poll the busy bit until reset before clearing ENC Resetting ENC during repeat single channel operation stops the converter at the end of the current conversion Resetting ENC during a sequence or repeat sequence mode stops the converter at the end of the sequence Lj Any conversion mode may be stopped immediately by setting the CONSEQx 0 and resetting ENC bit Conversion data are unreliable oS ey Note No EOS Bit Set For Sequence If no EOS bit is set and a sequence mode is selected resetting the ENC bit does not stop the sequence To stop the sequence first select a
253. m TBR may counts and if symmetrical pulse generation is needed The timer repeatedly counts up to the value of compare latch TBCLO and back down to zero as shown in Figure 12 7 The period is twice the value in TBCLO Note TBCLO TBR max If TBCLO gt TBR may the counter operates as if it were configured for continuous mode It does not count down from TBR may to zero Figure 12 7 Up Down Mode TBCLO Oh The count direction is latched This allows the timer to be stopped and then restarted in the same direction it was counting before it was stopped If this is not desired the TBCLR bit must be used to clear the direction The TBCLR bit also clears the TBR value and the TBCLK divider In up down mode the TBCCRO CCIFG interrupt flag and the TBIFG interrupt flag are set only once during the period separated by 1 2 the timer period The TBCCRO CCIFG interrupt flag is set when the timer counts from 0 1 to TBCLO and TBIFG is set when the timer completes counting down from 0001h to 0000h Figure 12 8 shows the flag set cycle Figure 12 8 Up Down Mode Flag Setting Timer Clock Timer Up Down Set TBIFG Set TBCCRO CCIFG a ea ae a Timer B 12 9 Timer B Operation Changing the Value of Period Register TBCLO Use of the Up Down When changing TBCLO while the timer is running and counting in the down direction and when the TBCLO load mode is immediate the
254. maintains the value of the input signal at the device pin before the PnSELx bit was reset Digital I O Operation 9 2 5 P1 and P2 Interrupts Each pin in ports P1 and P2 have interrupt capability configured with the PnIFG PnIE and PnIES registers All P1 pins source a single interrupt vector and all P2 pins source a different single interrupt vector The PnIFG register can be tested to determine the source of a P1 or P2 interrupt Interrupt Flag Registers P1IFG P2IFG Each PnIFGx bit is the interrupt flag for its corresponding I O pin and is set when the selected input signal edge occurs at the pin All PnIFGx interrupt flags request an interrupt when their corresponding PnlE bit and the GIE bit are set Each PnIFG flag must be reset with software Software can also set each PnIFG flag providing a way to generate a software initiated interrupt Bit 0 No interrupt is pending Bit 1 An interrupt is pending Only transitions not static levels cause interrupts If any PnIFGx flag becomes set during a Px interrupt service routine or is set after the RETI instruction of a Px interrupt service routine is executed the set PnIFGx flag generates another interrupt This ensures that each transition is acknowledged Note PnIFG Flags When Changing PnOUT or PnDIR Writing to P1OUT P1DIR P2OUT or P2DIR can result in setting the corresponding P1IFG or P2IFG flags 1 E S ALTERUM Note Length of I O Pin Interrupt Even
255. may be reset by software The interrupt vector address in interval timer mode is different from that in watchdog mode ae So Ss oe re Note Modifying the Watchdog Timer The WDT interval should be changed together with WDTCNTCL 1 ina single instruction to avoid an unexpected immediate PUC or interrupt The WDT should be halted before changing the clock source to avoid a possible incorrect interval ee Watchdog Timer Watchdog Timer Operation 10 2 4 Watchdog Timer Interrupts The WDT uses two bits in the SFRs for interrupt control The WDT interrupt flag WDTIFG located in IFG1 0 L The WDT interrupt enable WDTIE located in IE1 0 When using the WDT in the watchdog mode the WDTIFG flag sources a reset vector interrupt The WDTIFG can be used by the reset interrupt service routine to determine if the watchdog caused the device to reset If the flag is set then the watchdog timer initiated the reset condition either by timing out or by a security key violation If WDTIFG is cleared the reset was caused by a different source When using the WDT in interval timer mode the WDTIFG flag is set after the selected time interval and requests a WDT interval timer interrupt if the WDTIE and the GIE bits are set The interval timer interrupt vector is different from the reset vector used in watchdog mode In interval timer mode the WDTIFG flag is reset automatically when the interrupt is serviced or can be reset with s
256. may be used for the elimination of instructions during the software check or for defined waiting times Status bits are not affected The NOP instruction is mainly used for two purposes L To hold one two or three memory words To adjust software timing p A A Note Emulating No Operation Instruction Other instructions can emulate the NOP function while providing different numbers of instruction cycles and code words Some examples are Examples MOV 0 R3 1 cycle 1 word MOV 0 R4 0 R4 6 cycles 3 words MOV R4 0 R4 5 cycles 2 words BIC 0 EDE R4 4 cycles 2 words JMP 42 2 cycles 1 word BIC 0 R5 1 cycle 1 word However care should be taken when using these examples to prevent unintended results For example if MOV 0 R4 0 R4 is used and the value in R4 is 120h then a security violation will occur with the watchdog timer address 120h because the security key was not used RISC 16 Bit CPU 3 53 Instruction Set POP W Syntax Operation Emulation Emulation Description Status Bits Example Example Example Example Pop word from stack to destination Pop byte from stack to destination POP dst dst SP gt temp SP 2 SP temp dst MOV SP dst or MOVW SP dst MOV B SP dst The stack location pointed to by the stack pointer TOS is moved to the destination The stac
257. mes OFFIEh is already erased Assumes ACCVIE NMIIE OFIE O WDTPW WDTHOLD amp WDTCTL Disable WDT Disable interrupts FWKEY FSSELI FNO amp FCTL2 SMCLK 2 FWKEY amp FCTL3 Clear LOCK FWKEY WRT amp FCTLI Enable write 0123h amp S0FF1Eh 0123h gt OFFI1Eh FWKEY amp FCTL1 Done Clear WRT FWKEY LOCK amp FCTL3 Set LOCK Re enable WDT Enable interrupts Flash Memory Controller 5 9 Flash Memory Operation Initiating a Byte Word Write from RAM The flow to initiate a byte word write from RAM is shown in Figure 5 9 Figure 5 9 Initiating a Byte Word Write from RAM 5 10 L1 L2 Disable all interrupts and watchdog Set WRT 0 LOCK 1 re enable interrupts and watchdog Byte word write from Assumes OFF1Eh is already erased Assumes ACCVIE OV DINT BIT JNZ OV OV OV OV BIT JNZ OV OV EINT Flash Memory Controller RAM 514 kHz NMIIE BUSY amp FCTL3 L1 OFIE WDTPW WDTHOLD amp WDTCTL FWKEY ESSE FWKEY amp FCTL3 FWKEY WRT amp FCTL1 0123h amp 0 1 BUSY amp FCTL3 L2 FWKEY amp FCTL1 FWKEY LOCK amp FCTL3 1 FN0 amp FCTL2 0 lt SMCLK lt 952 kHz Disable WDT Disable interrupts Test BUSY Loop while busy SMCLK 2 Clear LOCK Enable write 0123h gt OFF1E
258. mple the receive errors for the following conditions are are calculated Baud rate 2400 BRCLK 32 768 Hz ACLK UxBR 13 since the ideal division factor is 13 65 UxMCTL 6B m7 0 m6 1 m5 1 m4z0 m3 1 m2 0 m1 1 and m0 1 The LSB of UxMCTL is used first Start bit Error x 2x 1 6 0 x UXBR 0 1 0 x 100 2 54 BRCLK Data bit DO Error x 2x 1 6 1 x UxBR 1 1 1 x 100 5 08 Data bit D1 Error Data bit D2 Error Data bit D3 Error Data bit D4 Error Data bit D5 Error Data bit D6 Error Data bit D7 Error adate rate y BRCLK baud rate o BRGLK x 2x 1 6 2 x UxBR 1 I 1 2 x 100 0 29 baud rate d o BRGLK x 2x 1 6 8 x UxBR 2 1 100 2 83 baud rate TP Paua raie BRGLK eX 6 4 x UxBR 2 1 zJ x 100 1 95 baud rate o BRGLK x 2x 1 6 5 x UxBR 3 I 1 5 x 100 0 59 baud rate of o BRGLK x 2x 1 6 6 x UxBR 4 1 6 x 100 3 13 baud rate Of ane o 2x 1 6 7 UxBR 4 1 7 x 100 1 6696 DPC K 6 8 x UxBR 51 8 x 100 0 88 Parity bit Error x 2 1 6 9 x UxBR 6 1 9 100 3 42 Stop bit 1 Error BRCLK baud rate Th UE eras F BRclk 2 0 6 10 x UxBR 6 I 1 10 x 100 1 3796 The result
259. n CLR dst or CLR W dst CLR B dst 0 dst MOV 0 dst MOV B 0 dst The destination operand is cleared Status bits are not affected RAM word TONI is cleared CLR TONI 0 Register R5 is cleared CLR R5 RAM byte TONI is cleared CLR B TONI 0 gt 3 30 RISC 16 Bit CPU CLRC Syntax Operation Emulation Description Status Bits Mode Bits Example Instruction Set Clear carry bit CLRC 0 gt BIC 1 SR The carry bit C is cleared The clear carry instruction is a word instruction N Not affected Z Not affected C Cleared V Not affected OSCOFF CPUOFF and GIE are not affected The 16 bit decimal counter pointed to by R13 is added to a 32 bit counter pointed to by R12 CLRC C 0 defines start DADD R13 0 R12 add 16 bit counter to low word of 32 bit counter DADC 2 R12 add carry to high word of 32 bit counter RISC 16 Bit CPU 3 31 Instruction Set CLRN Syntax Operation Emulation Description Status Bits Mode Bits Example SUBR SUBRET Clear negative bit CLRN 0 N or NOT src AND dst dst BIC 4 SR The constant 04h is inverted OFFFBh and is logically ANDed with the destination operand The result is placed into the destination The clear negative bit instruction is a word instruction N Reset to 0 Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected The Negative bit i
260. n Figure 19 1 DAC12 Block Diagram e To ADC12 module VeREF 9 5 55 4 2 5 V or 1 5 V from ADC12 DAC12SREFx REF module internal reference DAC12AMP e ANA 2R e 2R 2 9 N a c REM 1 0 DAC12IR AVss DAC12LSELx DAC12_0OUT Latch Bypass DAC12RES DAC12DF TB2 DAC12GRP DAC12 ODAT Updated DAC12SREFx DAC12AMP 00 e 01 o 10 CH o e EX anacan VR VR DAC12 1 DAC12_10UT 2R DAC12RES DAC12 1Latch DAC12DF DAC12_1DAT Latch Bypass DAC12GRP DAC12 1DAT ENC Updated lt DAC12 19 3 DAC12 Operation 19 2 DAC12 Operation The DAC12 module is configured with user software The setup and operation of the DAC12 is discussed in the following sections 19 2 1 DAC12 Core The DAC12 can be configured to operate in 8 or 12 bit mode using the DAC12RES bit In addition the full scale output is programmable to be 1x or 3x the selected reference voltage via the DAC12IR bit This feature allows the user to control the dynamic range of the DAC12 When using the internal reference the full scale output is always 1x the reference voltage The DAC12DF bit allows the user to select between straight binary data and
261. n Pullup resistor 100 kQ P11x devices 11xx and 12xx devices System Resets Interrupts and Operating Modes 2 17 2 18 System Resets Interrupts and Operating Modes Chapter 3 RISC 16 Bit CPU This chapter describes the MSP430 CPU addressing modes and instruction set Topic Page cpl CPU Introductiong 3 2 3 2 CPU Registers 3 4 3 3 Addressing Modes 3 9 3 AxuInstructioniSet 76 3 17 3 1 CPU Introduction 3 1 CPU Introduction 3 2 The CPU incorporates features specifically designed for modern programming techniques such as calculated branching table processing and the use of high level languages such as C The CPU can address the complete address range without paging The CPU features include d E d d RISC architecture with 27 instructions and 7 addressing modes Orthogonal architecture with every instruction usable with every addressing mode Full register access including program counter status registers and stack pointer Single cycle register operations Large 16 bit register file reduces fetches to memory 16 bit address bus allows direct access and branching throughout entire memory range 16 bit data bus allows direct manipulation of word wide arguments Constant generator provides six most used immediate values and reduces code size Direct memory to memory transfers without intermediate register holding Wor
262. n of the result 00000h Result was positive OFFFFh Result was negative SUMEXT contains the carry of the result 0000h No carry for result 0001h Result has a carry SUMEXT contains the extended sign of the result 00000h Result was positive OFFFFh Result was negative The multiplier does not automatically detect underflow or overflow in the MACS mode The accumulator range for positive numbers is 0 to 7FFF FFFFh and for negative numbers is OFFFF FFFFh to 8000 0000h An overflow occurs when the sum of two negative numbers yields a result that is in the range for a positive number An underflow occurs when the sum of two positive numbers yields a result that is in the range for a negative number In both of these cases the SUMEXT register contains the correct sign of the result OFFFFh for overflow and 0000h for underflow User software must detect and handle these conditions appropriately Hardware Multiplier 7 2 8 Software Examples Hardware Multiplier Operation Examples for all multiplier modes follow All 8x8 modes use the absolute address for the registers because the assembler will not allow B access to word registers when using the labels from the standard definitions file MOV MOV 01234h amp MPY 05678h amp OP2 8x8 Unsigned Multiply MOV B 012h amp 0130h MOV B 034h amp 0138h 16 16 Signed Multiply MOV 01234h amp MPYS MOV 05678h amp OP2 MOV B 012h amp 0132h SXT amp
263. n the status register is cleared This avoids special treatment with negative numbers of the subroutine called CLRN CALL SUBR JN SUBRET If input is negative do nothing and return RET 3 32 RISC 16 Bit CPU CLRZ Syntax Operation Emulation Description Status Bits Mode Bits Example Instruction Set Clear zero bit CLRZ 02Z or NOT src AND dst dst BIC 2 SR The constant 02h is inverted OFFFDh and logically ANDed with the destination operand The result is placed into the destination The clear zero bit instruction is a word instruction N Not affected Z Reset to 0 C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected The zero bit in the status register is cleared CLRZ RISC 16 Bit CPU 3 33 Instruction Set CMPI W CMP B Syntax Operation Description Status Bits Mode Bits Example Example Example Compare source and destination Compare source and destination CMP src dst or CMP W src dst CMP B src dst dst NOT src 1 or dst src The source operand is subtracted from the destination operand This is accomplished by adding the 1s complement of the source operand plus 1 The two operands are not affected and the result is not stored only the status bits are affected N Set if result is negative reset if positive src gt dst Z Set if result is zero reset otherwise src dst C Set if there is a carry from the MS
264. n the upper byte 10 2 1 Watchdog Timer Counter The watchdog timer counter WDTCNT is a 16 bit up counter that is not directly accessible by software The WDTCNT is controlled and time intervals selected through the watchdog timer control register WDTCTL The WDTONT can be sourced from ACLK or SMCLK The clock source is selected with the WDTSSEL bit 10 2 2 Watchdog Mode After a PUC condition the WDT module is configured in the watchdog mode with an initial 32 ms reset interval using the DCOCLK The user must setup halt or clear the WDT prior to the expiration of the initial reset interval or another PUC will be generated When the WDT is configured to operate in watchdog mode either writing to WDTCTL with an incorrect password or expiration of the selected time interval triggers a PUC A PUC resets the WDT to its default condition and configures the RST NMI pin to reset mode 10 2 3 Interval Timer Mode 10 4 Setting the WDTTMSEL bitto 1 selects the interval timer mode This mode can be used to provide periodic interrupts In interval timer mode the WDTIFG flag is set at the expiration of the selected time interval A PUC is not generated in interval timer mode at expiration of the selected timer interval and the WDTIFG enable bit WDTIE remains unchanged When the WDTIE bit and the GIE bit are set the WDTIFG flag requests an interrupt The WDTIFG interrupt flag is automatically reset when its interrupt request is serviced or
265. nabled interrupt excluding TBCCRO CCIFG generates a number in the TBIV register see register description This number can be evaluated or added to the program counter to automatically enter the appropriate software routine Disabled Timer B interrupts do not affect the TBIV value Any access read or write of the TBIV register automatically resets the highest pending interrupt flag If another interrupt flag is set another interrupt is immediately generated after servicing the initial interrupt For example if the TBCCR1 and TBCCR2 CCIFG flags are set when the interrupt service routine accesses the TBIV register TBCCR1 CCIFG is reset automatically After the RETI instruction of the interrupt service routine is executed the TBCCR2 CCIFG flag will generate another interrupt Timer B Operation TBIV Interrupt Handler Examples Thefollowing software example shows the recommended use of TBIV and the handling overhead The TBIV value is added to the PC to automatically jump to the appropriate routine The numbers at the right margin show the necessary CPU clock cycles for each instruction The software overhead for different interrupt sources includes interrupt latency and return from interrupt cycles but not the task handling itself The latencies are Capture compare block CCRO 11 cycles Capture compare blocks CCR1 to CCR6 16 cycles Timer overflow TBIFG 14 cycles The following software example shows the recommended u
266. nables the UTXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled USARTO receive interrupt enable This bit enables the URXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules See device specific datasheet T Does not apply to MSP430x12xx devices See IE2 for the MSP430x12xx USARTO interrupt enable bits IE2 Interrupt Enable Register 2 7 Bits 7 6 UTXIE1 Bit 5 URXIE1 Bit 4 Bits UTXIEOt Bit 1 URXIEOt Bit 0 t MSP430x12xx devices only 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 These bits may be used by other modules See device specific datasheet USART1 transmit interrupt enable This bit enables the UTXIFG1 interrupt 0 Interrupt not enabled 1 Interrupt enabled USART1 receive interrupt enable This bit enables the URXIFG1 interrupt 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules See device specific datasheet USARTO transmit interrupt enable This bit enables the UTXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled USARTO receive interrupt enable This bit enables the URXIFGO interrupt for USARTO 0 Interrupt not enabled 1 Interrupt enabled 14 20 USART Peripheral Interface SPI Mode USART Registers SPI Mode IFG1 Interrupt Flag Register 1 7 6 5 4 3 2 1 0 rw 1 rw 0 UTXIFGOt Bit7 URXIFGOT Bit 6 Bits 5 0 USARTO transmit interrupt flag UTXIFGO is set when UOTXBUF is empty
267. nd shows the number of transfers remaining in the block When the DMAxSZ register decrements to zero it is reloaded from its temporary register and the corresponding DMAIFG flag is set During a block transfer the CPU is halted until the complete block has been transferred The block transfer takes 2 x MCLK x DMAxSZ clock cycles to complete CPU execution resumes with its previous state after the block transfer is complete Burst Block Transfers Burst block transfers are block transfers with CPU activity interleaved In burst block mode the CPU executes 2 MCLK cycles after every four byte word transfers of the block During a burst block transfer the CPU executes at 20 capacity Setting DMADT 2 3 configures the burst block mode After the burst block CPU execution resumes at 100 capacity the DMAEN bit is cleared DMAEN must be set again before another burst block transfer can be triggered After a DMA burst block transfer has been triggered further trigger signals occurring during the burst block transfer are ignored Setting DMADT 6 7 configures repeated burst block mode When DMADTx 6 7 the DMAEN bit remains set after completion of the burst block transfer and no further trigger signals are required to initiate another burst block transfer Another burst block transfer begins immediately after completion of a burst block transfer In this case the DMA transfers must be stopped by by clearing the DMAEN bit or by an NMI in
268. nding 1 Interrupt pending These bits may be used by other modules See device specific datasheet USARTO transmit interrupt flag UTXIFGO is set when UOTXBUF is empty 0 No interrupt pending 1 Interrupt pending USARTO receive interrupt flag URXIFGO is set when UORXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending USART Peripheral Interface UART Mode 13 29 13 30 USART Peripheral Interface UART Mode Chapter 14 USART Peripheral Interface SPI Mode The universal synchronous asynchronous receive transmit USART peripheral interface supports two serial modes with one hardware module This chapter discusses the operation of the synchronous peripheral interface or SPI mode USARTO is implemented on the MSP430x1 2 MSP430x13xx and MSP430x15x devices In addition to USARTO the MSP430x14x and MSP430x16x devices implement a second identical USART module USART1 Topic Page 14 4 USART Introduction SPI Mode 14 2 14 2 USART Operation SPI Mode 14 4 14 3 USART Registers SPI Mode 14 13 14 1 USART Introduction SPI Mode 14 1 USART Introduction SPI Mode In synchronous mode the USART connects the MSP430 to an external system via three or four pins SIMO SOMI UCLK and STE SPI mode is selected when the SYNC bit is set and the 12C bit is cleared SPI mode features include
269. ned offset contained in the instruction LSBs is added to the program counter If C is reset the next instruction following the jump is executed JC jump if carry higher or same is used for the comparison of unsigned numbers 0 to 65536 Status bits are not affected The P1IN 1 signal is used to define or control the program flow BIT 01h amp P1IN State of signal Carry JC PROGA If carry 1 then execute program routine A n Carry 0 execute program here R5 is compared to 15 If the content is higher or the same branch to LABEL CMP 15 R5 JHS LABEL Jump is taken if R5 2 15 Continue here if R5 15 3 44 RISC 16 Bit CPU JEQ JZ Syntax Operation Description Status Bits Example Example Example Instruction Set Jump if equal jump if zero JEQ label JZ label IfZ 1 PC 2x offset gt PC If Z 2 0 execute following instruction The status register zero bit Z is tested If it is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If Z is not set the instruction following the jump is executed Status bits are not affected Jump to address TONI if R7 contains zero TST R7 Test R7 JZ TONI if zero JUMP Jump to address LEO if R6 is equal to the table contents CMP R6 Table R5 Compare content of R6 with content of MEM table address content of R5 JEQ LEO Jump if both data are equal EO No data are not equal continue here
270. nes the number of data per block 15 0 transfer DMAxSZ register decrements with each word or byte transfer When DMAxSZ decrements to 0 it is immediately and automatically reloaded with its previously initialized value 00000h Transfer is disabled 00001h One byte or word is transferred 00002h Two bytes or words are transferred OFFFFh 65535 bytes or words are transferred DMA Controller 8 19 8 20 DMA Controller Chapter 9 Digital This chapter describes the operation of the digital I O ports Ports P1 P2 are implemented in MSP430x11xx devices Ports P1 P3 are implemented in MSP430x12xx devices Ports P1 P6 are implemented in MSP430x13x MSP430x14x MSP430x15x and MSP430x16x devices Topic Page 9 tS Digitalil O Introductionu eyes 9 2 9 2 Operation ce s 22 259 ener 9 3 9 3XDigitalil O Registers cern a E e sis E e S 9 7 9 1 Digital I O Introduction 9 1 Digital I O Introduction 9 2 Digital I O MSP430 devices have up to 6 digital I O ports implemented P1 P6 Each port has eight I O pins Every I O pin is individually configurable for input or output direction and each I O line can be individually read or written to Ports P1 and P2 have interrupt capability Each interrupt for the P1 and P2 I O lines can be individually enabled and configured to provide an interrupt on a rising edge or falling edge of an input signal All P1 I O lines source a single interrup
271. nputs and inverts the comparator output Comparator A reference select This bit selects which terminal the VcAREE is applied to When CAEX 0 0 VCAREF S applied to the terminal 1 VCAREF S applied to the terminal When CAEX 1 0 VCAREF is applied to the terminal 1 VCAREF S applied to the terminal Comparator A reference These bits select the reference voltage VcAREF O0 Internal reference off An external reference can be applied 01 0 25 Vcc 10 0 50 Vcc 11 Diode reference is selected Comparator_A on This bit turns on the comparator When the comparator is off it consumes no current The reference circuitry is enabled or disabled independently 0 Off 1 On Comparator_A interrupt edge select 0 Rising edge 1 Falling edge Comparator A interrupt enable 0 Disabled 1 Enabled The Comparator A interrupt flag 0 No interrupt pending 1 Interrupt pending Comparator A 16 9 Comparator A Registers Comparator A Control Register CACTL2 7 6 5 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Unused Bits Unused 7 4 P2CA1 Bit 3 Pin to CA1 This bit selects the CA1 pin function 0 The pin is not connected to CA1 1 The pin is connected to CA1 2 Bit 2 Pin to CAO This bit selects the CAO pin function 0 The pin is not connected to CAO 1 The pin is connected to CAO CAF Bit 1 Comparator_A output filter 0 Comparator_A output is not filtered 1 Comparator_A output is filtered CAOUT B
272. nsfers for one block The address range of the first block is defined anywhere in the MSP430 address range with the 16 bit register ADC10SA The first block ends at ADC10SA 2n 2 The address range for the second block is defined as SA 2n to SA 4n 2 The two block transfer mode is shown in Figure 18 11 Figure 18 11 Two Block Transfer 18 18 ADC10 TB 1 2x n th transfer ADC10SA 4n 2 ADC10SA 4n 4 DTC n th transfer ADC10SA 2n 2 ADC10SA 2n 4 2nd transfer ADC10SA 2 1st transfer ADC10SA The internal address pointer is initially equal to ADC10SA and the internal transfer counter is initially equal to n The internal pointer and counter are not visible to software The DTC transfers the word value of ADC10MEM to the address pointer ADC10SA After each DTC transfer the internal address pointer is incremented by two and the internal transfer counter is decremented by one The DTC transfers continue with each loading of ADC10MEM until the internal transfer counter becomes equal to zero At this point block one is full and both the ADC10IFG flag the ADC10B1 bit are set The user can test the ADC10B1 bit to determine that block one is full The DTC continues with block two The internal transfer counter is automatically reloaded with n At the next load of the ADC10MEM the DTC begins transferring conversion results to block two After n transfers have completed block two is full The ADC10IFG flag is
273. nted by two INCD B 0 SP Byte on TOS is increment by two 3 42 RISC 16 Bit CPU INVLW INV B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Example Instruction Set Invert destination Invert destination INV dst INV B dst NOT dst gt dst XOR 0OFFFFh dst XOR B 0FFh dst The destination operand is inverted The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise C Set if result is not zero reset otherwise NOT Zero Set if result is not zero reset otherwise NOT Zero V Set if initial destination operand was negative otherwise reset OSCOFF CPUOFF and GIE are not affected Content of R5 is negated twos complement MOV ZOOAEh R5 R5 000AEh INV R5 Invert R5 R5 OFF51h INC R5 R5 is now negated R5 OFF52h Content of memory byte LEO is negated MOV B SOAEh LEO MEM LEO INV B LEO Invert LEO MEM LEO 051h INC B LEO MEM LEO is negated MEM LEO 052h RISC 16 Bit CPU 3 43 Instruction Set JC JHS Syntax Operation Description Status Bits Example Example Jump if carry set Jump if higher or same JC label JHS label If C 1 2x offset gt PC If C 2 0 execute following instruction The status register carry bit C is tested If it is set the 10 bit sig
274. nterrupt flag to avoid errant operating conditions When the TACLK is asynchronous to the CPU clock any read from TAR should occur while the timer is not operating or the results may be unpredictable Any write to TAR will take effect immediately LLLL X Clock Source Select and Divider 11 4 Timer A The timer clock TACLK can be sourced from ACLK SMCLK or externally via TACLK or INCLK The clock source is selected with the TASSELx bits The selected clock source may be passed directly to the timer or divided by 2 4 or 8 using the IDx bits Timer A Operation 11 2 2 Starting the Timer The timer may be started or restarted in the following ways The timer counts when MCx gt 0 and the clock source is active When the timer mode is either up or up down the timer may be stopped by writing O to TACCRO The timer may then be restarted by writing a nonzero value to TACCRO In this scenario the timer starts incrementing in the up direction from zero 11 2 3 Timer Mode Control The timer has four modes of operation as described in Table 11 1 stop up continuous and up down The operating mode is selected with the MCx bits Table 11 1 Timer Modes MCx Mode Description 00 Stop The timer is halted 01 Up The timer repeatedly counts from zero to the value of TACCRO 10 Continuous The timer repeatedly counts from zero to
275. nventions Register Bit Conventions Each register is shown with a key indicating the accessibility of the each individual bit and the initial condition Register Bit Accessibility and Initial Condition Key Bit Accessibility Read write Read only Read as 0 Read as 1 Write only Write as 0 Write as 1 No register bit implemented writing a 1 results in a pulse The register bit is always read as 0 Cleared by hardware Set by hardware Condition after PUC Condition after POR vi 1 Contents nigerelI ei 0o np CE 1 1 Wel Architectures esce oc ee ve eRDLEDRURReRDUbPRI GU ER heen RUBER been EE eS 1 2 1 2 Flexible Clock System ssssssssessssssssses en 1 2 1 3 Embedded Emulation ioii eA a a a 1 3 V4 dAddress Space ener red emat bs ee eer 1 4 1 4 1 Elash BOM ted aud Cte be o betae br o bao ef Bune Du a 1 4 1 42 BAM orsi etx E querere ebrei als ee ue iria 1 4 1 43 Peripheral Modules e 1 5 1 4 4 Special Function Registers 1 5 1 4 5 Memory Organization 0 2 0 0 cc teens 1 5 System Resets Interrupts and Operating Modes 2 1 2 1 System Reset and Initialization 0 2 2 2 1 4 Power On Reset POR 2 3 2 1 2 Brownout Reset 2 4 2 1 8 Devic
276. oftware Note No Oscillator Fault Detection for LFXT1 in LF Mode Oscillator fault detection is only applicable for LFXT1 in HF mode and XT2 There is no oscillator fault detection for LFXT1 in LF mode ss OFIFG is set by the oscillator fault signal XT_OscFault XT_OscFault is set at POR when LFXT1 has an oscillator fault in HF mode or when XT2 has an oscillator fault When XT2 or LFXT1 in HF mode is stopped with software the XT_OscFault signal becomes active immediately remains active until the oscillator is re started and becomes inactive approximately 50 us after the oscillator re starts as shown in Figure 4 9 Figure 4 10 Oscillator Fault Signal 4 10 XT1OFF XT2OFF LFXT1CLK XT2CLK XT_OscFault software enables OSC software disables OSC OSC faults v Basic Clock Module Basic Clock Module Operation Oscillator Fault Detection Signal XT OscFault triggers the OFIFG flag as shown in Figure 4 11 The LFXT1 OscFault signal is low when LFXT1 is LF mode On devices without XT2 the OFIFG flag cannot be cleared when LFXT1 is in LF mode MCLK may be sourced by LFXT1CLK in LF mode by setting the SELMX bits even though OFIFG remains set On devices with XT2 the OFIFG flag can be cleared by software when LFXT1 is in LF mode and it remains cleared MCLK may be sourced by LFXT1CLK in LF mode regardless of the state of the OFIFG flag Figure 4 11 Oscillator Fault Interrupt
277. oftware Watchdog Timer 10 5 Watchdog Timer Operation 10 2 5 Operation in Low Power Modes The MSP430 devices have several low power modes Different clock signals are available in different low power modes The requirements of the user s application and the type of clocking used determine how the WDT should be configured For example the WDT should not be configured in watchdog mode with SMCLK as its clock source if the user wants to use low power mode 3 because SMCLK is not active in LPM3 and the WDT would not function When the watchdog timer is not required the WDTHOLD bit can be used to hold the WDTONT reducing power consumption 10 2 6 Software Examples Any write operation to WDTCTL must be a word operation with 05Ah WDTPW in the upper byte Periodically clear an active watchdog MOV WDTPW WDTCNTCL amp WDTCTL Change watchdog timer interval MOV WDTPW WDTCNTL SSEL amp WDTCTL Stop the watchdog MOV WDTPW WDTHOLD amp WDTCTL Change WDT to interval timer mode clock 8192 interval MOV WDTPW WDTCNTCL WDTTMSEL WDTISO amp WDTCTL 10 6 Watchdog Timer Watchdog Timer Registers 10 3 Watchdog Timer Registers The watchdog timer module registers are listed in Table 10 1 Table 10 1 Watchdog Timer Registers Register Short Form Register Type Address Initial State Watchdog timer control register WDTCTL Read write 0120h 06900h with PUC SFR interrupt enable register 1 IE1 Read write 0000h Reset with
278. ol Register 15 rw 0 7 rw 0 CMx CCISx scs CLLDx OUTMODx 14 CMx rw 0 6 4 3 2 1 0 0 r 0 0 0 rw 0 Bit 15 14 Bit 13 12 Bit 11 Bit 10 9 Bit 8 Bits 7 5 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 r 0 rw 0 5 rw 0 rw rw rw Capture mode 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both rising and falling edges Capture compare input select These bits select the TBCCRx input signal See the device specific datasheet for specific signal connections 00 CCIxA 01 CCIxB 10 GND 11 Vcc Synchronize capture source This bit is used to synchronize the capture input signal with the timer clock 0 Asynchronous capture 1 Synchronous capture Compare latch load These bits select the compare latch load event 00 TBCLx loads on write to TBCCRx 01 TBCLx loads when TBR counts to 0 10 TBOLxloads when TBR counts to 0 up or continuous mode TBCLx loads when TBR counts to TBCLO or to 0 up down mode 11 TBCLxloads when TBR counts to TBCLx Capture mode 0 Compare mode 1 Capture mode Output mode Modes 2 3 6 and 7 are not useful for TBCLO because EQUx EQUO 000 OUT bit value 001 Set 010 Toggle reset 011 Set reset 100 Toggle 101 Reset 110 Toggle set 111 Reset set Timer B 12 23 Timer B Registers CCIE CCI OUT COV CCIFG 12 24 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T
279. oltage The resistance of the source Rg R affect tsampje The following equation can be used to calculate the minimum sampling time for 10 bit conversion 11 1 tsample gt Rg x In 2 x 1 Substituting the values for and C given above the equation becomes 2 tsample gt Rg 2k x 7 625 x 20pF 2 For example if Rg is 10 tsample Must be greater than 1 83 us ADC10 18 2 5 Conversion Modes ADC10 Operation The ADC10 has four operating modes selected by the CONSEQx bits as discussed in Table 18 1 Table 18 1 Conversion Mode Summary CONSEQx MODE 00 Single channel single conversion 01 Sequence of channels 10 Repeat single channel 11 Repeat sequence of channels OPERATION A single channel is converted once A sequence of channels is converted once A single channel is converted repeatedly A sequence of channels is converted repeatedly ADC10 18 9 ADC10 Operation Single Channel Single Conversion Mode Asingle channel selected by INCHx is sampled and converted once The ADC result is written to ADC10MEM Figure 18 5 shows the flow of the single channel single conversion mode When ADC10SC triggers a conversion successive conversions can be triggered by the ADC10SC bit When any other trigger source is used ENC must be toggled between each conversion Figure 18 5 Single Channel Single Conversion Mode SHS 0 and E
280. on Reference burst REFOUT must also be set 0 Reference voltage output continuously 1 Reference voltage output only during sample and conversion ADC10 18 25 ADC10 Registers MSC REF2 5V REFON ADC100N ADC10IE ADC10IFG ENC ADC10SC 18 26 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADC10 Multiple sample and conversion Valid only for sequence or repeated modes 0 The sampling requires a rising edge of the SHI signal to trigger each sample and conversion 1 The first rising edge of the SHI signal triggers the sampling timer but further sample and conversions are performed automatically as soon as the prior conversion is completed Reference generator voltage REFON must also be set 0 1 5V 1 2 5V Reference generator on 0 Reference off 1 Reference on ADC10 on 0 ADC 10 off 1 ADC10 on ADC 10 interrupt enable 0 Interrupt disabled 1 interrupt enabled ADC 10 interrupt flag This bit is set if ADC10MEM is loaded with a conversion result Itis automatically reset when the interrupt request is accepted or it may be reset by software When using the DTC this flag is set when a block of transfers is completed 0 No interrupt pending 1 Interrupt pending Enable conversion 0 ADC10 disabled 1 ADC 10 enabled Start conversion Software controlled sample and conversion start ADC10SC and ENC may be set together with one instruction ADC10SC is reset automatically 0 No sample an
281. on and Synchronization 15 16 15 2 7 Using the 12C Module with Low Power Modes 15 17 15 2 8 Using the I2C Module with the DMA Controller 15 17 15 2 9 Configuring the USART for I2C 15 18 15 2 10 126 Intel T ple oue ano old Mare bed emu exti acta Los T Php pReIS 15 19 15 3 12C Module Registers tecto tete decl aic ss aifend asap us 15 21 16 Comparator p L 16 1 16 1 Comparator A Introduction 00 nett eens 16 2 16 2 Comparator A Operation 0c cece een 16 3 16 2 4 Comparator xr ERE e bbb ade etu eigo iri pue 16 3 16 2 2 Input Analog Switches 16 3 16 2 3 O tput Fiter on neck eae oa dton De bURAU BERE Cups a irt legen 16 4 16 2 4 Voltage Reference Generator 16 4 16 2 5 Comparator A Port Disable Register CAPD 16 5 16 2 6 Comparator A Interrupts 16 5 16 2 7 Comparator_A Used to Measure Resistive Elements 16 6 16 3 Comparator A Registers 0 ccc eee es en 16 8 17 PERDE 17 1 17 15 ADGT2 Introduction bed bre wbbe 17 2 17 2 ADG12 Operation 22 okcserDeXekCCDb4eXBgue abb raria eo eae Pe dne d Du 17 4 1724 12 BI
282. on the Vref signal DAC12 Reference Input and Voltage Output Buffers The reference input and voltage output buffers of the DAC12 can be configured for optimized settling time vs power consumption Eight combinations are selected using the DAC12AMPx bits In the low low setting the settling time is the slowest and the current consumption of both buffers is the lowest The medium and high settings have faster settling times but the current consumption increases See the device specific data sheet for parameters 19 2 3 Updating the DAC12 Voltage Output The DAC12 xDAT register can be connected directly to the DAC12 core or double buffered The trigger for updating the DAC1 2 voltage output is selected with the DAC12LSELx bits When DAC12LSELx 0 the data latch is transparent and the DAC12_xDAT register is applied directly to the DAC12 core the DAC12 output updates immediately when new DAC 12 data is written to the DAC12 xDAT register regardless of the state of the DAC12ENC bit When DAC12LSELx 1 DAC12 data is latched and applied to the DAC12 core after new data is written to DAC12 xDAT When DAC12LSELx 2 or 3 data is latched on the rising edge from the Timer A CCR1 output or Timer B CCR 2 output respectively DAC12ENC must be set to latch the new data when DAC12LSELx gt 0 DAC12 19 5 DAC12 Operation 19 2 4 DAC12 xDAT Data Format The DAC12 supports both straight binary and 2 s compliment data formats When using straight b
283. ons For example the single operand instruction CLR dst is emulated by the double operand instruction with the same length MOV R3 dst where the 0 is replaced by the assembler and R3 is used with As 00 INC is replaced by ADD dst 0 R3 dst RISC 16 Bit CPU 3 7 CPU Registers 3 2 5 General Purpose Registers R4 R15 The twelve registers R4 R15 are general purpose registers All of these registers can be used as data registers address pointers or index values and can be accessed with byte or word instructions as shown in Figure 3 7 Figure 3 7 Register Byte Byte Register Operations Register Byte Operation High Byte Low Byte Dues Register Memory Example Register Byte Operation R5 0A28Fh R6 0203h Mem 0203h 012h ADD B R5 0 R6 08Fh 012h OA1h Mem 0203h OA1h C 0 Z 0 N 1 Low byte of register Addressed byte gt Addressed byte 3 8 RISC 16 Bit CPU Byte Register Operation High Byte Low Byte Example Byte Register Operation R5 01202h R6 0223h Mem 0223h 05Fh ADD B R6 R5 05Fh 002h 00061h R5 00061h C 0 Z 0 N 0 Addressed byte Low byte of register gt Low byte of register zero to High byte Addressing Modes 3 3 Addressing Modes Seven addressing modes for the source operand and four addressing modes for the destination operand can address the complete address space with no exceptions The bit number
284. or A Used to Measure Resistive Elements The Comparator A can be optimized to precisely measure resistive elements using single slope analog to digital conversion For example temperature can be converted into digital data using a thermistor by comparing the thermistor s capacitor discharge time to that of a reference resistor as shown in Figure 16 5 A reference resister Rref is compared to Rmeas Figure 16 5 Temperature Measurement System CAO CCHB Capture Input Of Timer A dre 0 25xVcc The MSP430 resources used to calculate the temperature sensed by Rmeas are Two digital I O pins to charge and discharge the capacitor set to output high Vcc to charge capacitor reset to discharge I O switched to high impedance input with CAPDx set when not in use One output charges and discharges the capacitor via Rref One output discharges capacitor via Rmeas The terminal is connected to the positive terminal of the capacitor The terminal is connected to a reference level for example 0 25 x Vcc The output filter should be used to minimize switching noise L LE L L L LU LE Lt CAOUT used to gate Timer A CCI1B capturing capacitor discharge time More than one resistive element can be measured Additional elements are connected to CAO with available I O pins and switched to high impedance when not being measured 16 6 Comparator A Comparator A Operation The thermistor measurement is
285. or other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled Flash Memory Controller 5 21 5 22 Flash Memory Controller Chapter 6 Supply Voltage Supervisor This chapter describes the operation of the SVS The SVS is implemented in MSP430x15x and MSP430x16x devices Topic Page iy SVS Introductionis 0 6 2 6 2 SVS Operation n o meeneem eame 6 4 6 33 SVS Begisters 6 7 6 1 SVS Introduction 6 4 SVS Introduction The supply voltage supervisor SVS is used to monitor the AVcc supply voltage or an external voltage The SVS can be configured to set a flag or generate a POR reset when the supply voltage or external voltage drops below a user selected threshold The SVS features include AVcc monitoring Selectable generation of POR Output of SVS comparator accessible by software Low voltage condition latched and accessible by software 14 selectable threshold levels DL D DD LU External channel to monitor external voltage The SVS block diagram is shown in Figure 6 1 6 2 Supply Voltage Supervisor SVS Introduction Figure 6 1 SVS Block Diagram D D 9 a A Tau 50ns S q
286. ored on the stack The call instruction is a word instruction Status bits are not affected Examples for all addressing modes are given CALL EXEC Callonlabel EXEC or immediate address e g 0A4h SP 2 5 SP PC 2 5 SP PC PC CALL EXEC Call on the address contained in EXEC SP 2 2 SP PC 2 5 SP X PC PC Indirect address CALL amp EXEC Call on the address contained in absolute address EXEC SP 2 2 SP PC 2 5 SP X 0 2 PC Indirect address CALL R5 Call on the address contained in R5 SP 2 gt SP PC42 gt SP R5 5 PC Indirect R5 CALL R5 Call on the address contained in the word pointed to by R5 SP 2 2 SP PC 2 gt SP R5 gt PC Indirect indirect R5 CALL R5 Call on the address contained in the word pointed to by R5 and increment pointer in R5 The next time S W flow uses R5 pointer it can alter the program execution due to access to next address in a table pointed to by R5 SP 2 2 SP PC 2 5 SP R5 gt PC Indirect indirect R5 with autoincrement CALL X R5 Call on the address contained in the address pointed to by R5 X e g table with address starting at X X can be an address or a label SP 2 2 SP PC 2 5 SP X R5 2 PC Indirect indirect R5 X RISC 16 Bit CPU 3 29 Instruction Set CLR W CLR B Syntax Operation Emulation Description Status Bits Example Example Example Clear destination Clear destinatio
287. ounts to the TACCRO value The output is reset when the timer counts to the TACCRx value It is set when the timer counts to the TACCRO value Timer A 11 13 Timer A Operation Output Example Timer in Up Mode The OUTx signal is changed when the timer counts up to the TACCRx value and rolls from TACCRO to zero depending on the output mode An example is shown in Figure 11 12 using TACCRO and TACCR1 Figure 11 12 Output Example Timer in Up Mode OFFFFh Example EQU1 Used TACCRO TACCRt Oh Output Mode 1 Set uc Es Output Mode 2 Toggle Reset Output Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set EQUO EQUI EQUO EQUI EQUO TAIFG TAIFG TAIFG Events 11 14 Timer A Timer A Operation Output Example Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TACCRx and TACCRO values depending on the output mode An example is shown in Figure 11 13 using TACCRO and TACCR1 Figure 11 13 Output Example Timer in Continuous Mode OFFFFh TACCRO TACCR1 Oh TAIFG EQU1 EQUO TAIFG EQU1 EQUO Interrupt Events Timer_A 11 15 Timer A Operation Output Example Timer in Up Down Mode The OUTx signal changes when the timer equals TACCRx in either count direction and when the timer equals TACCRO depending on the output mode An example is
288. pective chapters in this manual Status register SR is reset The watchdog timer powers up active in watchdog mode Program counter PC is loaded with address contained at reset vector location OFFFEh CPU execution begins at that address After a system reset user software must initialize the MSP430 for the application requirements The following must occur m m Initialize the SP typically to the top of RAM Initialize the watchdog to the requirements of the application Configure peripheral modules to the requirements of the application Additionally the watchdog timer oscillator fault and flash memory flags can be evaluated to determine the source of the reset System Resets Interrupts and Operating Modes 2 5 System Reset and Initialization 2 2 Interrupts The interrupt priority is shown in Figure 2 4 The priorities are defined by the arrangement of the modules in the connection chain The nearer a module is to the CPU NMIRS the higher the priority There are three types of interrupts System reset L Non maskable NMI Maskable Figure 2 4 Interrupt Priority Priority High L w PUC OSCfault Flash ACCV Circuit Reset NMI WDT Security Key Ge Flash Security Key i Z RFA 5LSBs gt 2 6 System Resets Interrupts and Operating Modes System Reset and Initialization 2
289. ped into the address space The address space from 0100 to 01FFh is reserved for 16 bit peripheral modules These modules should be accessed with word instructions If byte instructions are used only even addresses are permissible and the high byte of the result is always O The address space from 010h to OFFh is reserved for 8 bit peripheral modules These modules should be accessed with byte instructions Read access of byte modules using word instructions results in unpredictable data in the high byte If word data is written to a byte module only the low byte is written into the peripheral register ignoring the high byte 1 4 4 Special Function Registers SFRs Some peripheral functions are configured in the SFRs The SFRs are located in the lower 16 bytes of the address space and are organized by byte SFRs must be accessed using byte instructions only See the device specific data sheets for applicable SFR bits 1 4 5 Memory Organization Bytes are located at even or odd addresses Words are only located at even addresses as shown in Figure 1 3 When using word instructions only even addresses may be used The low byte of a word is always an even address The high byte is atthe next odd address For example if a data word is located at address xxx4h then the low byte of that data word is located at address xxx4h and the high byte of that word is located at address xxx5h Figure 1 3 Bits Bytes and Words in a Byte Organized M
290. period updates The user cannot directly access TBCLx Compare data is written to each TBCCRx and automatically transferred to TBCLx The timing of the transfer from TBCCRx to TBCLx is user selectable with the CLLDx bits as described in Table 12 2 Table 12 2 TBCLx Load Events CLLDx Description 00 New data is transferred from TBCCRx to TBCLx immediately when TBCCRx is written to 01 New data is transferred from TBCCRx to TBCLx when TBR counts to 0 10 New data is transferred from TBCCRx to TBCLx when TBR counts to 0 for up and continuous modes New data is transferred to from TBCCRx to TBCLx when TBR counts to the old TBCLO value or to 0 for up down mode 11 New data is transferred from TBCCRx to TBCLx when TBR counts to the old TBCLx value Grouping Compare Latches Multiple compare latches may be grouped together for simultaneous updates with the TBCLGRPx bits When using groups the CLLDx bits of the lowest numbered TBCCRx in the group determine the load event for each compare latch of the group except when TBCLGRP 3 as shown in Table 12 3 The CLLDx bits of the controlling TBCCRx must not be set to zero When the CLLDx bits of the controlling TBCCRx are set to zero all compare latches update immediately when their corresponding TBCCRx is written no compare latches are grouped Two conditions must existfor the compare latches to be loaded when grouped First all TBCCRx registers of the group must be updated even when new
291. racy Figure 17 11 ADC12 Grounding and Noise Considerations DVcc Digital S Power Supply 7x Decoupling d DVss 10uF 100nF Analog aie E Power Supply Decoupling AVss 10uF 100nF MSP430F13x MSP430F14x Using an External die VeREF Mo EP Positive T Reference 10uF 100nF Using the Internal VREF Reference TY Generator 10uF 100nF Using an External Vpgr VenEgr Negative m Reference 10uF 100nF ADC12 17 17 ADC12 Operation 17 2 10 ADC12 Interrupts The ADC12 has 18 interrupt sources ADC12IFGO ADC12IFG15 ADC12OV ADC12MEMXx overflow Ly ADC12TOV ADC12 conversion time overflow The ADC12IF Gx bits are set when their corresponding ADC 12MEMx memory register is loaded with a conversion result An interrupt request is generated if the corresponding ADC12IEx bit and the GIE bit are set The ADC120V condition occurs when a conversion result is written to any ADC12MEMx before its previous conversion result was read The ADC12TOV condition is generated when another sample and conversion is requested before the current conversion is completed ADC12IV Interrupt Vector Generator 17 18 ADC12 All ADC12 interrupt sources are prioritized and combined to source a single interrupt vector The interrupt vector register ADC12IV is used to determine which enabled ADC12 interrupt source requested an interrupt The highest priority en
292. red baud rate BRCLK Input frequency UCLKI ACLK or SMCLK fi Bit position 0 for the start bit 1 for data bit DO and so on UxBR Division factor in registers UXBR1 and UxBRO For example the transmit errors for the following conditions are are calculated Baud rate 2400 BRCLK 32 768 Hz ACLK UxBR 13 since the ideal division factor is 13 65 UxMCTL 6Bh m7 0 m6 1 m5 1 m4z0 m38 1 m2 0 m1 21 and m0 1 The LSB of UxMCTL is used first Start bit Error x 0 1 x UxBR n2 x 100 2 54 Data bit DO Error aua rate x 1 1 x UxBR 2 2 x 100 5 08 Data bit D1 Error Paud rate x 2 1 x UxBR 2 s x 100 0 29 Data bit D2 Error Daud rate x 3 1 x UxBR 3 4 x 100 2 83 Data bit D3 Error Daud Tale x 4 1 x UxBR 3 s x 100 1 9596 Data bit D4 Error Daud rate x 5 1 x UxBR 4 e x 100 0 59 Data bit D5 Error baud rate x 6 1 x UxBR 5 7 x 100 3 13 Data bit D6 Error x 7 1 x UxBR 5 He x 100 1 66 Data bit D7 Error toute x 8 1 x UxBR 6 9 x x 100 0 88 BRCLK Stop bit 1 Error Paud rate x 10 1 x UxBR 7 11 100 1 37 Parity bit Error rate 9 1 x UxBR 7 10 x 100 3 42 The results show the maximum per bit error to be 5 08 of a BITCLK period USART Peripheral Interface UART Mode 13 13 USART
293. reset otherwise Set if dst contained OFFh reset otherwise V Set if dst contained 07FFFh reset otherwise Set if dst contained 07Fh reset otherwise OSCOFF CPUOFF and GIE are not affected The status byte of a process STATUS is incremented When it is equal to 11 a branch to OVFL is taken INC B STATUS 47H1 STATUS JEQ OVFL RISC 16 Bit CPU 3 41 Instruction Set INCD W INCD B Syntax Operation Emulation Emulation Example Status Bits Mode Bits Example Example Double increment destination Double increment destination INCD dst INCD W dst INCD B dst dst 2 dst ADD 2 dst ADD B 2 dst The destination operand is incremented by two The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFEh reset otherwise Set if dst contained OFEh reset otherwise C Set if dst contained OFFFEh or OFFFFh reset otherwise Set if dst contained OFEh or OFFh reset otherwise V Set if dst contained O7FFEh or 07FFFh reset otherwise Set if dst contained 07Eh or 07Fh reset otherwise OSCOFF CPUOFF and GIE are not affected The item on the top of the stack TOS is removed without using a register PUSH R5 R5 is the result of a calculation which is stored in the system stack INCD SP Remove TOS by double increment from stack Do not use INCD B SP is a word aligned register RET The byte on the top of the stack is increme
294. rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 mE Modifiable only when I2CEN 0 I2CSCLLx Bits I2C shift clock low These bits define the low period of SCL when the 12C 7 0 controller is in master mode The SCL low period is I2CSCLL 2 x l2CPSC 000h N A 001h N A 002h N A 003h SCL low period 5 x l2CPSC OFFh SCL low period 257 x I2CPSC USART Peripheral Interface I C Mode 15 27 I C Module Registers I2COA I2C Own Address Register 7 Bit Addressing Mode 15 14 13 12 11 10 9 8 ro ro ro ro ro ro 7 6 5 4 3 2 1 0 0 rw 0 rw 0 rw 0 r rw 0 rw 0 rw 0 rw 0 Modifiable only when I2CEN 0 N Q o gt x Bits 12 own address The I2COA register contains the local address of the 15 0 MSP430 I C controller The I2COA register is right justified Bit 6 is the MSB Bits 15 7 are always 0 I2COA I2C Own Address Register 10 Bit Addressing Mode 15 14 13 12 11 10 9 8 ro ro ro ro rw 0 rw 0 7 6 5 4 3 2 1 0 I2COAx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Modifiable only when I2CEN 0 N Q o gt x Bits 2 own address The I2COA register contains the local address of the 15 0 MSP430 I C controller The 2 register is right justified Bit 9 is the MSB Bits 15 10 are always 0 15 28 USART Peripheral Interface IC Mode 12C Module Registers I2CSA I2C Slave Address Register 7 Bit Addressing Mode 15 14 13 12 11 10 9 8 ro ro ro ro ro ro ro RN rw
295. ry present on a device Erase cycle times are equivalent for all MSP430 devices Figure 5 4 Erase Cycle Timing i ld E 4 gt lt gt Generate Erase Operation Active Remove Programming Voltage Programming Voltage Erase Time Vcc Current Consumption is Increased BUSY tall erase t mass erase S297 ftETG lisegment erase 7 481 9 f FTG A dummy write to an address not in the range to be erased does not start the erase cycle does not affect the flash memory and is not flagged in any way This errant dummy write is ignored Interrupts should be disabled before a flash erase cycle After the erase cycle has completed interrupts may be re enabled Any interrupt that occurred during the erase cycle will have its associated flag set and will generate an interrupt request when re enabled Flash Memory Controller 5 5 Flash Memory Operation Initiating an Erase from Within Flash Memory Any erase cycle can be initiated from within flash memory or from RAM When aflash segment erase operation is initiated from within flash memory all timing is controlled by the flash controller and the CPU is held while the erase cycle completes After the erase cycle completes the CPU resumes code execution with the instruction following the dummy write When initiating an erase cycle from within flash memory it is possible to erase the code needed for execution after the erase If this occurs CPU exec
296. s cleared The status bit is set Note Instructions CMP and SUB The instructions CMP and SUB are identical except for the storage of the result The same is true for the BIT and AND instructions LLLLLLL OEO XAXA 3 18 RISC 16 Bit CPU 3 4 2 Single Operand Format Il Instructions Instruction Set Figure 3 10 illustrates the single operand instruction format Figure 3 10 Single Operand Instruction Format 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 Table 3 12 lists and describes the single operand instructions Table 3 12 Single Operand Instructions Mnemonic S Reg D Reg RRC B dst RRA B dst PUSH sre SWPB dst CALL dst RETI SXT dst Operation C gt MSB LSB gt C MSB 5 MSB LSB gt C SP 2 gt SP src gt SP Swap bytes SP 2 gt SP PC 2 gt SP dst gt PC TOS gt SR SP 2 gt SP TOS gt PC SP 2 gt SP Bit 7 gt Bit 8 Bit 15 The status bit is affected The status bit is not affected 0 The status bit is cleared 1 The status bit is set Status Bits V N Z C All addressing modes are possible for the CALL instruction If the symbolic mode ADDRESS the immediate mode N the absolute mode amp EDE or the indexed mode x RN is used the word that follows contains the address information
297. s higher than the effective frequency the error of the effective frequency integrates to zero It does not accumulate The error of the effective frequency is zero every 32 DCOCLK cycles Figure 4 8 illustrates the modulator operation The modulator settings and DCO control are configured with software The DCOCLK can be compared to a stable frequency of known value and adjusted with the DCOx RSELx and MODx bits See http Awww ti com sc msp430 for application notes and example code on configuring the DCO Figure 4 8 Modulator Patterns MODx Lower DCO Tap Frequency fpco Upper DCO Tap Frequency fpco 1 Basic Clock Module 4 9 Basic Clock Module Operation 4 2 6 Basic Clock Module Fail Safe Operation The basic clock module incorporates an oscillator fault detection fail safe feature The oscillator fault detector is an analog circuit that monitors the LFXT1CLK in HF mode and the XT2CLK An oscillator fault is detected when either clock signal is not present for approximately 50 us When an oscillator fault is detected and when MCLK is sourced from either LFXT1 in HF mode or XT2 MCLK is automatically switched to the DCO for its clock source This allows code execution to continue even though the crystal oscillator has stopped When OFIFG is set and OFIE is set an NMI interrupt is requested The NMI interrupt service routine can test the OFIFG flag to determine if an oscillator fault occurred The OFIFG flag must be cleared by s
298. s in Table 3 3 describe the contents of the As source and Ad destination mode bits Table 3 3 Source Destination Operand Addressing Modes As Ad Addressing Mode Syntax Description 00 0 Register mode Rn Register contents are operand 01 1 Indexed mode X Rn Rn X points to the operand X is stored in the next word 01 1 Symbolic mode ADDR PC X points to the operand X is stored in the next word Indexed mode X PC is used 01 1 Absolute mode amp ADDR The word following the instruction contains the absolute address X is stored in the next word Indexed mode X SR is used 10 Indirect register Rn Rn is used as a pointer to the mode operand 11 Indirect Rn Rnis used as a pointer to the autoincrement operand Rn is incremented afterwards by 1 for B instructions and by 2 for W instructions 11 Immediate mode N The word following the instruction contains the immediate constant N Indirect autoincrement mode PC is used The seven addressing modes are explained in detail in the following sections Most of the examples show the same addressing mode for the source and destination but any valid combination of source and destination addressing modes is possible in an instruction Note Use of Labels EDE and TONI Throughout MSP430 documentation EDE and TONI are used as generic labels They are only labels They have no special meaning LLLLLS S OO O
299. s show the maximum per bit error to be 5 0896 of a BITCLK period USART Peripheral Interface UART Mode 13 15 USART Operation UART Mode Typical Baud Rates and Errors Standard baud rate frequency data for UxBRx and UxMCTL are listed in Table 13 2 for a 32 768 Hz watch crystal ACLK and a typical 1 048 576 Hz SMCLK The receive error is the accumulated time versus the ideal scanning time in the middle of each bit The transmit error is the accumulated timing error versus the ideal time of the bit period Table 13 2 Commonly Used Baud Rates Baud Rate Data and Errors Divide Divide by A BRCLK 32 768 Hz B BRCLK 1 048 576 Hz Max jin i Max Max Baud TX TX RX Rate Bra E EN E 926 r EN EH ais Error 1200 27 27 31 873 81 81 n 2 3 t2 13 16 USART Peripheral Interface UART Mode USART Operation UART Mode 13 2 7 USART Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception USART Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UXTXBUF is ready to accept another character An interrupt request is generated if UTXIEx and GIE are also set UTXIFGx is automatically reset if the interrupt request is serviced or if a character is written to UXTXBUF UTXIFGx is set after a PUC or when SWRST 1 UTXIEx is reset after a PUC or when SWRST 1 The operation is shown is Figure 1
300. scillator The LFXT1 oscillator supports ultralow current consumption using a 32 768 Hz watch crystalin LF mode XTS 0 A watch crystal connects to XIN and XOUT without any other external components Internal 12 pF load capacitors are provided for LFXT1 in LF mode The capacitors add serially providing a match for standard 32 768 Hz crystals requiring a 6 pF load Additional capacitors can be added if necessary The LFXT1 oscillator also supports high speed crystals or resonators when in HF mode XTS 1 The high speed crystal or resonator connects to XIN and XOUT and requires external capacitors on both terminals These capacitors should be sized according to the crystal or resonator specifications Software can disable LFXT1 by setting OSCOFF if this signal does not source SMCLK or MCLK as shown in Figure 4 3 Figure 4 3 Off Signals for the LFXT1 Oscillator XTS m OSCOFF m LFoff CPUOFF SELMO E SELM1 E XT2 ES _ gt XT off Le XT2 is an Internal Signal XT2 0 MSP430x11xx MSP430x12xx devices scai 8 SELS XT2 1 MSP430x13x MSP430x14x MSP430x15x and MSP430x16x devices Note LFXT1 Oscillator Characteristics Low frequency crystals often require hundreds of milliseconds to start up depending on the crystal It is recommended to leave the LFXT1 oscillator on when in LF mode Ultralow power oscillators such as the LFXT1 in LF mode should be
301. scription Status Bits Example ERROR CONT Example Jump if carry not set Jump if lower JNC label JLO label if C 20 PC 2x offset gt PC if C 2 1 execute following instruction The status register carry bit C is tested If it is reset the 10 bit signed offset contained in the instruction LSBs is added to the program counter If C is set the nextinstruction following the jump is executed JNC jump if no carry lower is used for the comparison of unsigned numbers 0 to 65536 Status bits are not affected The result in R6 is added in BUFFER If an overflow occurs an error handling routine at address ERROR is used ADD R6 BUFFER BUFFER R6 BUFFER JNC CONT No carry jump to CONT em Error handler start reum Continue with normal program flow Branch to STL2 if byte STATUS contains 1 or 0 CMP B 2 STATUS JLO STL2 STATUS lt 2 STATUS gt 2 continue here 3 50 RISC 16 Bit CPU JNE JNZ Syntax Operation Description Status Bits Example Instruction Set Jump if not equal Jump if not zero JNE label JNZ label If Z 0 PC 2x offset PC If Z 1 execute following instruction The status register zero bit Z is tested If it is reset the 10 bit signed offset contained in the instruction LSBs is added to the program counter If Z is set the next instruction following the jump is executed Status bits are not affected Jump to address TONI if R7 and R8 have
302. se of TBIV for Timer B3 Interrupt handler for TBCCRO CCIFG Cycles CCIFG 0 HND eects Start of handler Interrupt latency 6 RETI 5 Interrupt handler for TBIFG TBCCR1 and TBCCR2 CCIFG TB_HND Interrupt latency 6 ADD amp TBIV PC Add offset to Jump table 3 RETI Vector 0 No interrupt 5 JMP CCIFG 1 HND Vector 2 Module 1 2 JMP CCIFG 2 HND Vector 4 Module 2 2 RETI Vector 6 RETI Vector 8 RETI Vector 10 RETI Vector 12 TBIFG_HND Vector 14 TIMOV Flag a Task starts here RETI 5 CCIFG 2 HND Vector 4 Module 2 Task starts here RETI Back to main program 5 The Module 1 handler shows a way to look if any other interrupt is pending 5 cycles have to be spent but 9 cycles may be saved if another interrupt is pending CCIFG 1 HND Vector 6 Module 3 Asse Task starts here JMP TB HND Look for pending ints 2 Timer B 12 19 Timer B Registers 12 3 Timer B Registers The Timer B registers are listed in Table 12 5 Table 12 5 Timer B Registers Register Short Form Register Type Address Initial State Timer B control TBCTL Read write 0180h Reset with POR Timer counter TBR Read write 0190h Reset with POR Timer_B capture compare control 0 TBCCTLO Read write 0182h Reset with POR Timer_B capture compare 0 TBCCRO Read write 0192h Reset with POR Timer_B capture compare control 1 TBCCTL1 Read write 0184h Reset with POR Timer_B capture compare 1 TBCCR1 Read write
303. ses the USART for operation See also chapter USART Module I2C mode for USARTO when reconfiguring from 12C mode to UART mode D c t t ee ee ee Sie EMT s n Note Initializing or Re Configuring the USART Module The required USART initialization re configuration process is 1 Set SWRST BIS B 4 SWRST amp UxCTL 2 Initialize all USART registers with SWRST 1 including UxCTL 3 Enable USART module via the MEx SFRs URXEx and or UTXEx 4 5 Clear SWRST via software BIC B SWRST amp UxCTL Enable interrupts optional via the IEx SFRs URXIEx and or UTXIEx we Failure to follow this process may result in unpredictable USART behavior ee 13 2 2 Character Format The UART character format shown in Figure 13 2 consists of a start bit seven or eight data bits an even odd no parity bit an address bit address bit mode and one or two stop bits The bit period is defined by the selected clock source and setup of the baud rate registers Figure 13 2 Character Format Mark ST DO D6 PA SP SP 2nd Stop Bit SP 1 Pou Parity Bit PENA 1 Address Bit MM 1 Optional Bit Condition 8th Data Bit CHAR 1 13 4 USART Peripheral Interface UART Mode USART Operation UART Mode 13 2 3 Asynchronous Communication Formats When two devices communicate asynchronously the idle line format is used for
304. set and the ADC10B1 bit is cleared User software can test the cleared ADC10B1 bit to determine that block two is full Figure 18 12 shows a state diagram of the two block mode n 0 ADC10DTC1 DTC reset ADC10B1 0 ADC10TB 1 n 0 in Wait for write to ADC10SA Initialize Start Address in ADC10SA Write to ADC10SA nis latched in counter x Write to ADC10SA or Wait until ADC10MEM n 0 is written Write to ADC10MEM completed Write to ADC10SA Synchronize 0 CPU ready with MCLK 2 Write to ADC10SA 1x MCLK cycle Transfer data to Address AD AD 2 1 ADC10B1 1 or ADC10CT 1 eee and ADC10B1 0 ADC10IFG 1 Toggle ADC10B1 ADC10 Operation Figure 18 12 State Diagram for Data Transfer Control in Two Block Transfer Mode Prepare DTC DTC operation ADC10 18 19 ADC10 Operation Continuous Transfer A continuous transfer is selected if ADC10CT bit is set The DTC will not stop after block one in one block mode or block two two block mode has been transferred The internal address pointer and transfer counter are set equal to ADC10SA and n respectively Transfers continue starting in block one If the ADC10CT bit is reset DTC transfers cease after the current completion of transfers into block one in the one block mode or block two in the two block mode have been transfer DTC Transfer Cycle Time For each ADC10MEM
305. sfer has completed and the status bits have been updated This interrupt is used to notify the CPU that the 12C registers are ready to be accessed Receive ready interrupt status this flag is set when the 12C module has received new data RXRDYIFG is automatically cleared when I2CDR is read and the receive buffer is empty A receiver overrun is indicated if bit I2ZCRXOVR 1 RXRDYIFG is used in receive mode only Transmit ready interrupt status the I2CDR register is ready for new transmit data when I2CNDAT gt 0 OR I2CRM 1 master transmit mode or when another master is requesting data slave transmit mode TXRDYIFG is automatically cleared when I2CDR and the transmit buffer are full A transmit underflow is indicated if I2ZCTXUDF 1 Unused in receive mode General call interrupt This flag is set when the 12C module received the general call address 00h GCIFG is used in receive mode only Start condition detected interrupt This flag is set when the 12C module detects a start condition while in slave mode This allows the MSP430 to be in a low power mode with the 12C clock source inactive until a master initiates 12C communication STTIFG is used in slave mode only USART Peripheral Interface I C Mode 15 19 12C Module Operation I2CIV Interrupt Vector Generator 15 20 The 12C interrupt flags are prioritized and combined to source a single interrupt vector The interrupt vector register I2CIV is used to determine whic
306. shown in Figure 11 14 using TACCRO TACCR2 Figure 11 14 Output Example Timer in Up Down Mode OFFFFh TACCRO TACCR2 Oh Equ2 EQu2 EQU EQU intet Eden TAIFG EQUO TAIFG EQUO ale ca oo ee Note Switching Between Output Modes When switching between output modes one of the OUTMODx bits should remain set during the transition unless switching to mode 0 Otherwise output glitching can occur because a NOR gate decodes output mode 0 A safe method for switching between output modes is to use output mode 7 as a transition state BIS OUTMOD_7 amp TACCTLx Set output mode 7 BIC OUTMODx amp TACCTLx Clear unwanted bits d M J 11 16 Timer A Timer A Operation 11 2 6 Timer A Interrupts TACCRO Interrupt Two interrupt vectors are associated with the 16 bit Timer A module TACCRO interrupt vector for TACCRO CCIFG 1 TAIV interrupt vector for all other CCIFG flags and TAIFG In capture mode any CCIFG flag is set when a timer value is captured in the associated TACCRx register In compare mode any CCIFG flag is set if TAR counts to the associated TACCRx value Software may also set or clear any CCIFG flag All CCIFG flags request an interrupt when their corresponding CCIE bit and the GIE bit are set The TACCRO CCIFG flag has the highest Timer A in
307. ssociated I O port pins which are digital CMOS gates When analog signals are applied to digital CMOS gates parasitic current can flow from Voc to GND This parasitic current occurs if the input voltage is near the transition level of the gate Disabling the port pin buffer eliminates the parasitic current flow and therefore reduces overall current consumption The CAPDx bits when set disable the corresponding P2 input buffer as shown in Figure 16 3 When current consumption is critical any P2 pin connected to analog signals should be disabled with their associated CAPDx bit Figure 16 3 Transfer Characteristic and Power Dissipation in a CMOS Inverter Buffer VI ee Vo lcc lcc v a VI V qe 0 Lo E 1 Vss 16 2 6 Comparator_A Interrupts One interrupt flag and one interrupt vector are associated with the Comparator_A as shown in Figure 16 4 The interrupt flag CAIFG is set on either the rising or falling edge of the comparator output selected by the CAIES bit If both the CAIE and the GIE bits are set then the CAIFG flag generates an interrupt request The CAIFG flag is automatically reset when the interrupt request is serviced or may be reset with software Figure 16 4 Comparator A Interrupt System SET CAIFG IRQ Interrupt Service Requested IRACC Interrupt Request Accepted Comparator A 16 5 Comparator A Operation 16 2 7 Comparat
308. stack pointer SP is incremented Status Bits N restored from system stack Z restored from system stack C restored from system stack V restored from system stack Mode Bits OSCOFF CPUOFF and GIE are restored from system stack Example Figure 3 13 illustrates the main program interrupt Figure 3 13 Main Program Interrupt PC 6 PC 4 Interrupt Request PC 2 ae PC v Interrupt Accepted PC 42 PC 2 is Stored PC PCi Onto Stack PC 44 PCi 2 PC 6 PCi 4 PC 8 e v PCi n 4 PCi n 2 PCi n RETI RISC 16 Bit CPU 3 57 Instruction Set RLAL W RLA B Syntax Operation Emulation Description Rotate left arithmetically Rotate left arithmetically RLA dst or RLA W dst RLA B dst C lt MSB lt MSB 1 LSB 1 LSB lt 0 ADD dst dst ADD B dst dst The destination operand is shifted left one position as shown in Figure 3 14 The MSB is shifted into the carry bit C and the LSB is filled with 0 The RLA instruction acts as a signed multiplication by 2 An overflow occurs if dst gt 04000h and dst lt 0C000h before operation is performed the result has changed sign Figure 3 14 Destination Operand Arithmetic Shift Left Status Bits Mode Bits Example Example Word 15 0 jew erect Byte 7 0 An overflow occurs if dst gt 040h and dst lt OCOh before the operation is performed the result h
309. sult is negative reset if positive Z Set if result is zero reset otherwise C Set if dst was incremented from OFFFFh to 0000 reset otherwise Set if dst was incremented from OFFh to 00 reset otherwise V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected The 16 bit counter pointed to by R13 is added to a 32 bit counter pointed to by R12 ADD R13 0 R12 Add LSDs ADC 2 R12 Add carry to MSD The 8 bit counter pointed to by R13 is added to a 16 bit counter pointed to by R12 ADD B R13 0 R12 Add LSDs ADC B 1 R12 Add carry to MSD RISC 16 Bit CPU 3 21 Instruction Set ADD W ADD B Syntax Operation Description Status Bits Mode Bits Example Example Add source to destination Add source to destination ADD src dst or ADD W Src dst ADD B src dst src dst dst The source operand is added to the destination operand The source operand is not affected The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the result cleared if not V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected R5 is increased by 10 The jump to TONI is performed on a carry ADD 10 R5 JC TONI Carry occurred Joys No carry R5 is increased by 10 The jump to TONI is performed on a carry ADD B 10
310. sult is not zero reset otherwise NOT Zero V Setif both operands are negative OSCOFF CPUOFF and GIE are not affected The bits set in R6 toggle the bits in the RAM word TONI XOR R6 TONI Toggle bits of word TONI on the bits set in R6 The bits set in R6 toggle the bits in the RAM byte TONI XOR B R6 TONI Toggle bits in word TONI on bits set in low byte of R6 Reset to 0 those bits in low byte of R7 that are different from bits in RAM byte EDE XOR B 7 Set different bit to 1s INV B R7 Invert Lowbyte Highbyte is Oh RISC 16 Bit CPU 3 71 Instruction Set 3 4 4 Instruction Cycles and Lengths The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used not the instruction itself The number of clock cycles refers to the MCLK Interrupt and Reset Cycles Table 3 14 lists the CPU cycles for interrupt overhead and reset Table 3 14 Interrupt and Reset Cycles No of Length of Action Cycles Instruction Return from interrupt RETI 5 1 Interrupt accepted 6 WDT reset 4 Reset RST NMI 4 Format ll Single Operand Instruction Cycles and Lengths Table 3 15 lists the length and CPU cycles for all addressing modes of format ll instructions Table 3 15 Format Il Instruction Cycles and Lengths No of Cycles Addressing RRA RRC Length of Mode SWPB SXT PUSH CALL Instruction Example Rn 1 3 4 1 SWPB R5 Rn
311. t Any external interrupt event should be at least 1 5 times MCLK or longer to ensure that it is accepted and the corresponding interrupt flag is set Eaa Digital I O 9 5 Digital I O Operation Interrupt Edge Select Registers P1IES P2IES Each PnIES bit selects the interrupt edge for the corresponding I O pin Bit 0 The PnIFGx flag is set with a low to high transition Bit 1 The PnIFGx flag is set with a high to low transition FRI TY Note Writing to PnIESx Writing to P1IES or P2IES can result in setting the corresponding interrupt flags PnIESx PnINx PnIFGx 0 5 1 0 Unchanged 0 5 1 1 May be set 10 0 May be set 1 Unchanged 120 EIIL J Interrupt Enable 1 P2IE Each PnIE bit enables the associated PnIFG interrupt flag Bit 0 The interrupt is disabled Bit 1 The interrupt is enabled 9 2 6 Configuring Unused Port Pins Unused I O pins should be configured as I O function output direction and left unconnected on the PC board to reduce power consumption The value of the PxOUT bit is don t care since the pin is unconnected See chapter System Hesets Interrupts and Operating Modes for termination unused pins 9 6 Digital O 9 3 Digital I O Registers Table 9 1 Digital I O Registers Port P1 P2 P4 P5 P6 Digital I O Registers Seven reg
312. t vector and all P2 I O lines source a different single interrupt vector The digital I O features include Independently programmable individual I Os Any combination of input or output d _j Individually configurable P1 and P2 interrupts c Independent input and output data registers Digital I O Operation 9 2 Digital I O Operation The digital I O is configured with user software The setup and operation of the digital I O is discussed in the following sections 9 2 1 Input Register PnIN Each bit in each PnIN register reflects the value of the input signal at the corresponding I O pin when the pin is configured as I O function Bit 2 0 The input is low Bit 1 The input is high V7 1 Note Writing to Read Only Registers PxIN Writing these read only registers results in increased current consumption while the write attempt is active es 9 2 2 Output Registers PhOUT Each bit in each PnOUT register is the value to be output on the corresponding I O pin when the pin is configured as I O function and output direction Bit 0 The output is low Bit 1 The output is high 9 2 3 Direction Registers PnDIR Each bit in each PnDIR register selects the direction of the corresponding I O pin regardless of the selected function for the pin PnDIR bits for I O pins that are selected for other module functions must be set as required by the other function Bit 0 The port pin is switched to input direct
313. ta is moved from the RX shift register to UxRXBUF the URXIFGx interrupt flag is set indicating that data has been received The overrun error bit OE is set when the previously received data is not read from UxRXBUF before new data is moved to UxRXBUF Four Pin SPI Slave Mode In 4 pin slave mode STE is used by the slave to enable the transmit and receive operations and is provided by the SPI master When STE is low the slave operates normally When STE is high Any receive operation in progress on SIMO is halted SOMI is set to the input direction A high STE signal does not reset the USART module The STE input signal is not used in 3 pin slave mode 14 6 USART Peripheral Interface SPI Mode USART Operation SPI Mode 14 2 4 SPI Enable The SPI transmit receive enable bit USPIEx enables or disables the USART in SPI mode When USPIEx 0 the USART stops operation after the current transfer completes or immediately if no operation is active A PUC or set SWRST bit disables the USART immediately and any active transfer is terminated Transmit Enable When USPIEx 0 any further write to UXTXBUF does not transmit Data written to UXTXBUF will begin to transmit when USPIEx 1 and the BRCLK source is active Figure 14 4 and Figure 14 5 show the transmit enable state diagrams Figure 14 4 Master Mode Transmit Enable No Data Written to Transfer Buffer USPIEx 0 Not Completed USPIEx 1 Dat
314. te if a second capture was performed before the value from the first capture was read Bit COV is set when this occurs as shown in Figure 12 11 COV must be reset with software Timer B 12 11 Timer B Operation Figure 12 11 Capture Cycle Idle Capture Capture Read No Capture Taken Read Taken Capture Capture Taken Capture Capture Read and No Capture Capture Clear Bit COV in Register TBCCTLx Second Capture Taken COV 1 Idle Capture Initiated by Software Captures can be initiated by software The CMx bits can be set for capture on both edges Software then sets bit CCIS1 1 and toggles bit CCISO to switch the capture signal between Vcc and GND initiating a capture each time CCISO changes state MOV CAP SCS CCIS1 CM_3 amp TBCCTLx Setup TBCCTLx XOR CCISO amp TBCCTLx TBCCTLx TBR Compare Mode The compare mode is selected when CAP 0 Compare mode is used to generate PWM output signals or interrupts at specific time intervals When TBR counts to the value in a TBCLx Interrupt flag CCIFG is set Internal signal EQUx 1 EQUXx affects the output according to the output mode 12 12 Timer B Timer B Operation Compare Latch TBCLx The TBCCRx compare latch TBCLx holds the data for the comparison to the timer value in compare mode TBCLx is buffered by TBCCRx The buffered compare latch gives the user control over when a compare
315. ted burst block transfer DMA destination increment This bit selects automatic incrementing or decrementing of the destination address after each byte or word transfer When DMADSTBYTE 1 the destination address increments by one When DMADSTBYTE O the destination address increments by two The DMAxDA is copied into a temporary register and the temporary register is incremented or decremented DMAxDA is not incremented or decremented 00 Destination address is unchanged 01 Destination address is unchanged 10 Destination address is decremented 11 Destination address is incremented DMA source increment This bit selects automatic incrementing or decrementing of the source address for each byte or word transfer When DMASRCBYTE 1 the source address increments by one When DMASRCBYTE 0 the source address increments by two The DMAXSA is copied into a temporary register and the temporary register is incremented or decremented DMAXSA is not incremented or decremented 00 Source address is unchanged 01 Source address is unchanged 10 Source address is decremented 11 Source address is incremented DMA destination byte This bit selects the destination as a byte or word 0 Word 1 Byte DMA Controller 8 17 DMA Hegisters DMA Bit 6 DMA source byte This bit selects the source as a byte or word SRCBYTE 0 Word 1 Byte DMA Bit 5 DMA level This bit selects between edge sensitive and level sensitive LEVEL triggers 0 Edge sensitive 1 Lev
316. ten to ADC10MEM Figure 18 7 shows the repeat single channel mode Figure 18 7 Repeat Single Channel Mode x INCHx Wait for Enable SHS 0 and ENC 1 4 ADC10SC 4 ENC 0 Sample Input Channel Ax x ADC10CLK MSC 1 ENC 1 1 x ADC10CLK Conversion Completed Result to ADC10MEM ADC1OIFG is Set X input channel Ax 18 12 ADC10 ADC10 Operation Repeat Sequence of Channels Mode A sequence of channels is sampled and converted repeatedly The sequence begins with the channel selected by INCHx and decrements to channel AO Each ADC result is written to ADC10MEM The sequence ends after conversion of channel AO and the next trigger signal re starts the sequence Figure 18 8 shows the repeat sequence of channels mode Figure 18 8 Repeat Sequence of Channels Mode x INCHx Wait for Enable SHS 0 and ENC 1 or 4 and ADC10SC 4 Wait for Trigger 4 8 16 64 x ADC10CLK If x 0 then x INCH else x x 1 Sample Input Channel Ax If x 0 then x INCH else x x 1 12 x ADC10CLK ENC 0 and x 0 MSC 1 and ENC 1 1 x ADC10CLK or x 0 Conversion Completed Result to ADC10MEM ADC10IFG is Set x input channel Ax ADC10 18 13 ADC10 Operation Using the MSC Bit To configure the converter to perform successive conversions automatically and as quickly as possible a multiple sampl
317. terrupt priority and has a dedicated interrupt vector as shown in Figure 11 15 The TACCRO CCIFG flag is automatically reset when the TACCRO interrupt request is serviced Figure 11 15 Capture Compare TACCRO Interrupt Flag Capture IRQ Interrupt Service Requested IRACC Interrupt Request Accepted TAIV Interrupt Vector Generator The TACCR1 CCIFG TACCR2 CCIFG and TAIFG flags are prioritized and combined to source a single interrupt vector The interrupt vector register TAIV is used to determine which flag requested an interrupt The highest priority enabled interrupt generates a number in the TAIV register see register description This number can be evaluated or added to the program counter to automatically enter the appropriate software routine Disabled Timer_A interrupts do not affect the TAIV value Any access read or write of the TAIV register automatically resets the highest pending interrupt flag If another interrupt flag is set another interrupt is immediately generated after servicing the initial interrupt For example if the TACCR 1 and TACCR2 CCIFG flags are set when the interrupt service routine accesses the TAIV register TACCR1 CCIFG is reset automatically After the RETI instruction of the interrupt service routine is executed the TACCR2 CCIFG flag will generate another interrupt Timer A 11 17 Timer A Operation TAIV Software Example The following software example shows the recommended
318. terrupt when ENNMI is set In repeated burst block mode the CPU executes at 2096 capacity continuously until the repeated burst block transfer is stopped DMA Controller 8 7 DMA Operation Figure 8 3 DMA State Diagram DMAEN 0 DMAEN 0 DMAREQ 0 DMAxSZ T Size a DMAxSA T_SourceAdd i DMAxDA T DestAdd a DMAABORT 1 ll 2 ll P 5 DMAREQ 0 2 T Size gt DMAxSZ E DMAABORT 0 DMAxSA T SourceAdd 2 DMAxDA T DestAdd fa X OZ 2 20 oc il a I Wait for Trigger EN N I a L gt xO z T i lt z Trigger AND DMALEVEL 0 az 9 2 8 OR one ER Tri 21 AND DMALEVEL 1 8 g 2 x MCLK Trigger cm a ind noun 2 Hold CPU lt lt gt 7 Transfer one word byte 7 gt N z Qao e z amp a a A 2 a lt ox T Size 2 DMAxSZ T i DMAxSA T SourceAdd z ono DMAxDA T DestAdd z zo 2 az lt E Decrement DMAxSZ Modify T SourceAddt 2 J Modify T DestAddt LH 2 DMADT 2 3 AND DMAxSZ gt 0 EFN py OR DMADT 6 7 12 iQ AND a multiple of 4 words bytes ac ke lt gt as were transferred 12 lt 206 Za arz as 2 x MCLK ees lt Burst State J E release CPU for 2XMCLK t The temporary registers are incremented or decremented depending on the DMASRCINCR and DMADSTINCR bits The
319. th DAC12_x DAC12LSELx gt 0 and either DAC12ENC 0 neither DAC12 will update Figure 19 6 DAC12 Group Update Example Timer_A3 Trigger DAC12_0 DAC12GRP DAC12 0 and DAC12 1 Updated Simultaneously Ne DAC12_0 DAC12ENC TimerA OUT1 DAC12 ODAT New Data DAC12 1DAT a DACI2 0 Updated New Data _ _____________ RA D Ll DAC12 0 Latch Trigger DAC12 0 DACI2LSELx 2 DAC12 0 DAC12LSELx gt 0 AND DAC12 1 DAC12LSELx 2 19 8 DAC12 DAC12 Operation 19 2 7 Using DAC12 With the DMA Controller MSP430 devices with an integrated DMA controller can automatically move data to the DAC12_xDAT register DMA transfers are done without CPU intervention and independently of any low power modes The DMA controller increases throughput to the DAC12 module and enhances low power applications allowing the CPU to remain off while data transfers occur Applications requiring periodic waveform generation can benefit from using the DMA controller with the DAC12 For example an application that produces a sinusoidal waveform may store the sinusoid values in a table The DMA controller can continuously and automatically transfer the values to the DAC12 at specific intervals creating the sinusoid zero CPU execution See the DMA Controller chapter for more information on the DMA controller aan Note DAC12 Settling Time The DMA controller is capable of transferring data to the DAC12 faster than t
320. the DAC12 data reaches the maximum code This is shown in Figure 19 5 Figure 19 5 Positive Offset Output Voltage DAC Data Full Scale Code The DAC12 has the capability to calibrate the offset voltage of the output amplifier Setting the DAC12CALON bit initiates the offset calibration The calibration should complete before using the DAC12 When the calibration is complete the DAC12CALON bit is automatically reset The DAC12AMPx bits should be configured before calibration DAC12 19 7 DAC12 Operation 19 2 6 Grouping Multiple DAC12 Modules Multiple DAC12s can be grouped together with the DAC12GRP bit to synchronize the update of each DAC12 output Hardware ensures that all DAC12 modules in a group update simultaneously independent of any interrupt or NMI event On the MSP430x15x and MSP430x16x devices DAC12 0 and DAC12 1 are grouped by setting the DAC12GRP bit of DAC12 0 The DAC12GRP bit of DAC12_1 is don t care When DAC12 0 and 12 1 are grouped Li The DAC12 1 DAC12LSELx bits select the update trigger for both DACs The DAC12LSELx bits for both DACs must be gt 0 The DAC12ENC bits of both DACs must be set to 1 When DAC12_0 and DAC12_1 are grouped both DAC12_xDAT registers must be written to before the outputs update even if data for one or both of the DACs is not changed Figure 19 6 shows latch update timing example for grouped DAC12_0 and DAC12_1 When DAC12_0 DAC12GRP 1 and bo
321. the DMA is discussed in the following sections 8 2 1 DMA Addressing Modes The DMA controller has four transfer addressing modes shown in Figure 8 2 Lj Fixed address to fixed address Fixed address to block of addresses _j Block of addresses to fixed address Lj Block of addresses to block of addresses The transfer addressing mode for each DMA channel is independently configurable For example channel 0 may transfer between two fixed addresses while channel 1 transfers between two blocks of addresses The DMA addressing modes are configured with the DMASRCINCR and DMADSTINCR control bits The DMASRCINCR bit selects if the DMA source address DMAxSA is incremented decremented or unchanged after each DMA transfer The DMADSTINCR bit selects if the DMA destination address DMAxDA is incremented decremented or unchanged after each DMA transfer DMA transfers may be byte to byte word to word byte to word or word to byte When transferring word to byte only the lower byte of the source word transfers When transferring byte to word the upper byte of the destination word is cleared when the transfer occurs 8 4 DMA Controller Figure 8 2 DMA Addressing Modes DMA Controller Address Space Fixed Address to Fixed Address DMA Address Space Controller Block Addresses to Fixed Address DMA Operation DMA Controller Address Space Fixed ad
322. the protocol When three or more devices communicate the USART supports the idle line and address bit multiprocessor communication formats Idle Line Multiprocessor Format When MM 0 the idle line multiprocessor format is selected Blocks of data are separated by an idle time on the transmit or receive lines as shown in Figure 13 3 An idle receive line is detected when 10 or more continuous ones marks are received after the first stop bit of a character When two stop bits are used for the idle line the second stop bit is counted as the first mark bit of the idle period The first character received after an idle period is an address character The RXWAKE bit is used as an address tag for each frame In the idle line multiprocessor format this bit is set when a received character is an address and is transferred to UXRXBUF Figure 13 3 Idle Line Format Blocks of n Characters E t d Idle Periods of 10 Bits or More UTXDX URXDx Expanded UTXDx URXDx First Frame Within Block Frame Within Block Frame Within Block Is Address It Follows Idle Period of 10 Bits or More Idle Period Less Than 10 Bits USART Peripheral Interface UART Mode 13 5 USART Operation UART Mode 13 6 The URXWIE bit is used to control data reception in the idle line multiprocessor format When the URXWIE bit is set all non address characters are assembled but not transferred into the UxRXBUF and interrupts are not generated Wh
323. tion the internal voltage reference generator must be supplied with storage capacitance across Vngr and Ayss The recommended storage capacitance is a parallel combination of 10 uF and 0 1 uF capacitors From turn on a maximum of 17 ms must be allowed for the voltage reference generator to bias the recommended storage capacitors If the internal reference generator is not used for the conversion the storage capacitors are not required Note Reference Decoupling Approximately 200 uA is required from any reference used by the ADC12 while the two LSBs are being resolved during a conversion A parallel combination of 10 uF and 0 1 uF capacitors is recommended for any reference used LLLLLL 3 External references may be supplied for VR and Va through pins Verner and VnEr Vegnrgr respectively ADC12 Operation 17 2 4 Sample and Conversion Timing An analog to digital conversion is initiated with a rising edge of the sample input signal SHI The source for SHI is selected with the SHSx bits and includes the following Lj The ADC12SC bit The Timer A Output Unit 1 The Timer B Output Unit 0 The Timer B Output Unit 1 The polarity of the SHI signal source can be inverted with the ISSH bit The SAMPCON signal controls the sample period and start of conversion When SAMPCON is high sampling is active The high to low SAMPCON transition starts
324. tions are instructions that have unique op codes decoded by the CPU The emulated instructions are instructions that make code easier to write and read but do not have op codes themselves instead they are replaced automatically by the assembler with an equivalent core instruction There is no code or performance penalty for using emulated instruction There are three core instruction formats Dual operand Single operand Jump All single operand and dual operand instructions can be byte or word instructions by using B or W extensions Byte instructions are used to access byte data or byte peripherals Word instructions are used to access word data or word peripherals If no extension is used the instruction is a word instruction The source and destination of an instruction are defined by the following fields src The source operand defined by As and S reg dst The destination operand defined by Ad and D reg As The addressing bits responsible for the addressing mode used for the source src S reg The working register used for the source src Ad The addressing bits responsible for the addressing mode used for the destination dst D reg The working register used for the destination dst B W Byte or word operation 0 word operation 1 byte operation 1 Note Destination Address Destination addresses are valid anywhere in the memory
325. to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 No interrupt pending 1 Interrupt pending This bit may be used by other modules See device specific datasheet Basic Clock Module 4 17 4 18 Basic Clock Module Chapter 5 Flash Memory Controller This chapter describes the operation of the MSP430 flash memory controller Topic Page 5 1 Flash Memory Introduction cc cece eee eee eee eee eee 5 2 5 2 Flash Memory Segmentation 5 3 5 3 Flash Memory Operation 5 4 5 4 Flash Memory Registers 5 17 5 1 Flash Memory Introduction 5 1 Flash Memory Introduction The MSP430 flash memory is bit byte and word addressable and programmable The flash memory module has an integrated controller that controls programming and erase operations The controller has three registers a timing generator and a voltage generator to supply program and erase voltages MSP430 flash memory features include Lj Internal programming voltage generation Lj Bit byte or word programmable Ultralow power operation Segment erase and mass erase The block diagram of the flash memory and controller is shown in Figure 5 1 Ex 424 beeen ote wc 7 3 a fue Um et Note Minimum Vcc During Flash Write or Erase The minimum Vcc voltage during
326. trated in Figure 2 8 1 TheSR with all previous settings pops from the stack All previous settings of GIE CPUOFF etc are now in effect regardless of the settings used during the interrupt service routine 2 The PC pops from the stack and begins execution at the point where it was interrupted Figure 2 8 Return From Interrupt Before After Return From Interrupt Interrupt nesting is enabled if the GIE bit is set inside the interrupt service routine 2 12 System Resets Interrupts and Operating Modes System Reset and Initialization 2 2 4 Interrupt Vectors The interrupt vectors and the power up starting address are located in the address range OFFFFh OFFEOh as described in Table 2 1 A vector is programmed by the user with the 16 bit address of the corresponding interrupt service routine See the device specific data sheet for the complete interrupt vector list Table 2 1 Interrupt Sources Flags and Vectors INTERRUPT SYSTEM WORD INTERRUPT SOURCE FLAG INTERRUPT ADDRESS PRIORITY Power up external reset watchdog ele Reset OFFFEh 15 highest flash password NMI oscillator fault NMIIFG non maskable flash memory access OFIFG non maskable OFFFCh 14 violation ACCVIFG non maskable device specific OFFFAh 13 device specific OFFF8h 12 device specific OFFF6h 11 Watchdog timer WDTIFG maskable OFFF4h 10 device specific OFFF2h 9 device specific OFFFOh 8 device specific OFFEEh 7 device specific OFFECh
327. trol 1 BCSCTL1 Read write 057h 084h with PUC Basic clock system control 2 BCSCTL2 Read write 058h Reset with POR SFR interrupt enable register 1 IE1 Read write 0000h Reset with PUC SFR interrupt flag register 1 IFG1 Read write 0002h Reset with PUC 4 14 Basic Clock Module Basic Clock Module Registers DCOCTL DCO Control Register 7 6 5 rw 0 rw 1 rw 1 rw 0 rw 0 rw 0 rw 0 rw 0 DCOx Bits DCO frequency select These bits select which of the eight discrete DCO 7 5 frequencies of the RSELx setting is selected MODx Bits Modulator selection These bits define how often the fpco 4 frequency is 4 0 used within a period of 32 DCOCLK cycles During the remaining clock cycles 32 MOD the fpco frequency is used Not useable when DCOx 7 BCSCTL1 Basic Clock System Control Register 1 7 6 5 4 3 2 1 0 XT20FF XTS DIVAx XT5V RSELx rw 1 rw 0 rw 0 rw 0 rw 0 rw 1 rw 0 rw 0 XT20FF Bit 7 XT2 off This bit turns off the XT2 oscillator 0 XT2 is on 1 XT2 is off if it is not used for MCLK or SMCLK XTS Bit 6 LFXT1 mode select 0 Low frequency mode 1 High frequency mode DIVAx Bits Divider for ACLK 5 4 00 01 02 10 4 11 8 XT5V Bit 3 Unused XT5V should always be reset RSELx Bits Resistor Select The internal resistor is selected in eight different steps 2 0 The value of the resistor defines the nominal frequency The lowest nominal frequency is selected by setting RSELx 0 Basic Clock Module 4 15 Basic Clock Module Registers
328. uences can be triggered by the ADC12SC bit When any other trigger source is used ENC must be toggled between each sequence Figure 17 7 Sequence of Channels Mode CONSEQx 01 ADC120ON 1 4 x CSTARTADDx Wait for Enable SHSx 0 and ENC 1 4 ADC12SC 5 Wait for Trigger SAMPCON 47 EOS x 1 SAMPCON 1 Sample Input Channel Defined in ADC12MCTLx Ifx lt 15thenx x 1 else x 0 Ifx lt 15thenx x 1 else x 0 SAMPCON Y MSC 1 and SHP 1 and EOS x 0 1 x ADC12CLK Conversion Completed Result Stored Into ADC12MEMXx ADC12IFG x is Set x pointer to ADC12MCTLx 17 12 ADC12 ADC12 Operation Repeat Single Channel Mode A single channel is sampled and converted continuously The ADC results are written to the ADC12MEMXx defined by the CSTARTADDX bits It is necessary to read the result after the completed conversion because only one ADC12MEMx memory is used and is overwritten by the next conversion Figure 17 8 shows repeat single channel mode Figure 17 8 Repeat Single Channel Mode CONSEQx 10 ADC120N 1 x CSTARTADDx Wait for Enable SHSx 0 and ENC 1 or 4 and ADC12SC Wait for Trigger SAMPCON amp ENC 0 SAMPCON 1 Sample Input Channel Defined in ADC12MCTLx SAMPCON Y 12 x ADC12CLK MSC 1 and SHP 1 and ENC 1 1
329. ult is not 0 Carry bit This bit is set when the result of a byte or word operation produced a carry and cleared when no carry occurred 3 2 4 Constant Generator Registers CG1 and CG2 CPU Registers Six commonly used constants are generated with the constant generator registers R2 and R3 without requiring an additional 16 bit word of program code The constants are selected with the source register addressing modes As as described in Table 3 2 Table 3 2 Values of Constant Generators CG1 CG2 Register R2 R2 R2 R2 R3 R3 R3 R3 The constant generator advantages are As 00 01 10 11 00 01 10 11 Constant 0 00004h 00008h 00000h 00001h 00002h OFFFFh No special instructions required Remarks Register mode Absolute address mode 4 bit processing 8 bit processing 0 word processing 1 2 bit processing 1 word processing No additional code word for the six constants No code memory access required to retrieve the constant The assembler uses the constant generator automatically if one of the six constants is used as an immediate source operand Registers R2 and R3 used in the constant mode cannot be addressed explicitly they act as source only registers Constant Generator Expanded Instruction Set The RISC instruction set ofthe MSP430 has only 27 instructions However the constant generator allows the MSP430 assembler to support 24 additional emulated instructi
330. up to OFFFFh and restarts from zero as shown in Figure 11 4 The capture compare register TACCRO works the same way as the other capture compare registers Figure 11 4 Continuous Mode OFFFFh Oh The TAIFG interrupt flag is set when the timer counts from OFFFFh to zero Figure 11 5 shows the flag set cycle Figure 11 5 Continuous Mode Flag Setting FFFEh Y FFFFh Y oh Set TAIFG Timer Timer A 11 7 Timer A Operation Use of the Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies Each time an interval is completed an interrupt is generated The next time interval is added to the TACCRx register in the interrupt service routine Figure 11 6 shows two separate time intervals tg and t4 being added to the capture compare registers In this usage the time interval is controlled by hardware not software without impact from interrupt latency Up to three independent time intervals or output frequencies can be generated using all three capture compare registers Figure 11 6 Continuous Mode Time Intervals 11 8 TACCR1b TACCR1c TACCROb TACCROc TAGE ROE og NM a Timer_A TACCROa TACCR1a TACCRId Time intervals can be produced with other modes as well where TACCRO is used as the period register Their handling is more complex since the sum of the old TACCRx data and the new period can be higher than t
331. use of TAIV and the handling overhead The TAIV value is added to the PC to automatically jump to the appropriate routine The numbers at the right margin show the necessary CPU cycles for each instruction The software overhead for different interrupt sources includes interrupt latency and return from interrupt cycles but not the task handling itself The latencies are Capture compare block TACCRO 11 cycles Capture compare blocks TACCR1 TACCR2 16 cycles Timer overflow TAIFG 14 cycles Interrupt handler for TACCRO CCIFG Cycles CCIFG 0 HND i Start of handler Interrupt latency 6 RETI Interrupt handler for TAIFG and TACCR2 CCIFG TA HND dts Interrupt latency 6 ADD amp TAIV PC Add offset to Jump table 3 RETI Vector 0 No interrupt 5 JMP CCIFG 1 HND Vector 2 TACCR1 2 JMP CCIFG 2 HND Vector 4 TACCR2 2 RETI Vector 6 Reserved 5 RETI Vector 8 Reserved 5 TAIFG HND Vector 10 TAIFG Flag Task starts here RETI 5 CCIFG 2 HND Vector 4 TACCR2 Task starts here RETI Back to main program 5 CCIFG 1 HND Vector 2 TACCRI Task starts here RETI Back to main program 5 11 18 Timer A 11 3 Timer A Registers The Timer A registers are listed in Table 11 3 Table 11 3 Timer A Registers Register Timer A control Timer A counter Timer A capture compare control 0 Timer A capture compare 0 Timer A capture compare control 1 Timer A capture compare
332. ution will be unpredictable after the erase cycle The flow to initiate an erase from flash is shown in Figure 5 5 Figure 5 5 Erase Cycle from Within Flash Memory Disable all interrupts and watchdog Setup flash controller and erase mode Set LOCK 1 re enable Interrupts and watchdog Segment Erase from flash 514 kHz SMCLK 952 kHz Assumes ACCVIE NMIIE OFIE 0 OV WDTPW WDTHOLD amp WDTCTL Disable WDT DINT Disable interrupts OV FWKEY FSSELI1 FNO amp FCTL2 SMCLK 2 OV FWKEY amp FCTL3 Clear LOCK OV FWKEY ERASE amp FCTL1 Enable segment eras CLR amp 0FC10h Dummy write erase S1 OV FWKEY LOCK amp FCTL3 Done set LOCK p Re enable WDT EINT Enable interrupts Flash Memory Controller Initiating an Erase from RAM Flash Memory Operation Any erase cycle may be initiated from RAM In this case the CPU is not held and can continue to execute code from RAM The BUSY bit must be polled to determine the end of the erase cycle before the CPU can access any flash address again If a flash access occurs while BUSY 1 itis an access violation ACCVIFG will be set and the erase results will be unpredictable The flow to initiate an erase from flash from RAM is shown in Figure 5 6 Figure 5 6 Erase Cycle from Within RAM Disable all interrupts and watchdog Segment Set LOCK interrupts Erase from RA
333. w data It does not indicate RX TX completion To receive data into the USART in master mode data must be written to UxTXBUF because receive and transmit operations operate concurrently Four Pin SPI Master Mode In 4 pin master mode STE is used to prevent conflicts with another master The master operates normally when STE is high When STE is low SIMO and UCLK are set to inputs no longer drive the bus The error bit FE is set indicating a communication integrity violation to be handled by the user A low STE signal does not reset the USART module The STE input signal is not used in 3 pin master mode USART Peripheral Interface SPI Mode 14 5 USART Operation SPI Mode 14 2 3 Slave Mode Figure 14 3 USAHT Slave and External Master MASTER MSB COMMON SPI SPI Receive Buffer SPI Receive Bufer Receive Buffer UXRXBUF Receive Shift Register LSB MSB MSP430 USART Figure 14 3 shows the USART as a slave in both 3 pin and 4 pin configurations UCLK is used as the input for the SPI clock and must be supplied by the external master The data transfer rate is determined by this clock and not by the internal baud rate generator Data written to UXTXBUF and moved to the TX shift register before the start of UCLK is transmitted on SOMI Data on SIMO is shifted into the receive shift register on the opposite edge of UCLK and moved to UxRXBUF when the set number of bits are received When da
334. w occurs when the transmit shift register and the transmit buffer are empty and I2CNDAT gt 0 In slave mode underflow occurs when the transmit shift register and the transmit buffer are empty and the external I2C master still requests data When transmit underflow occurs the I2CTXUDF bit is set Writing data to I2CDR register or resetting I2CEN bit resets I2CTXUDF I2CTXUDF is used in transmit mode only Receive overrun occurs when the receive shift register is full and the receive buffer is full The I2CRXOVR bit is set when receive overrun occurs No data is lost because SCL is held low in this condition which stops further bus activity Reading the I2CDR register or resetting I2CEN bit resets IACRXOVR bit The I2CRXOVR bit is used in receive mode only USART Peripheral Interface I C Mode 15 15 12C Module Operation 15 2 6 12C Clock Generation and Synchronization Figure 15 14 I2CIN The 12C module is operated with the clock source selected by the I2CSSELx bits The prescaler I2CPSC and the I2CSCLH and I2CSCLL registers determine the frequency and duty cycle of the SCL clock signal for master mode as shown in Figure 15 14 The 12C module clock source must be at least 10x the SCL frequency in both master and slave modes 12C Module SCL Generation ecese LT L I2CCLK dua WE I2CPSC I2CSCLH 1 I2CPSC I2CSCLL 1 During the arbitration procedure
335. w voltage condition occurred previously The SVSFG bit must be reset by user software If the low voltage condition is still present when SVSFG is reset it will be immediately set again by the SVS 6 4 Supply Voltage Supervisor SVS Operation 6 2 3 Changing the VLDx Bits When the VLDx bits are changed two settling delays are implemented to allows the SVS circuitry to settle During each delay the SVS will not set SVSFG The delays tq Svson and tgettle are shown in Figure 6 2 The ta SVSon delay takes affect when VLDx is changed from zero to any non zero value and is a approximately 50 us The tserje delay takes affect when the VLDx bits change from any non zero value to any other non zero value and is a maximum of 12 us See the device specific datasheet for the delay parameters During the delays the SVS will not flag a low voltage condition or reset the device and the SVSON bit is cleared Software can test the SVSON bit to determine when the delay has elapsed and the SVS is monitoring the voltage properly Figure 6 2 SVSON state When Changing VLDx VLDx 15 SVSON VLD vs Time tsettle Supply Voltage Supervisor 6 5 SVS Operation 6 2 4 SVS Operating Range Each SVS level has hysteresis to reduce sensitivity to small supply voltage changes when AVcc is close to the threshold The SVS operation and SVS Brownout interoperation are shown in Figure 6 3 Figure 6 3 Operating L
336. west Timer A 11 23 11 24 Timer A Chapter 12 Timer B Timer Bisa 16 bit timer counter with multiple capture compare registers This chapter describes Timer B Timer B3 three capture compare registers is implemented in MSP430x13x and MSP430x15x devices Timer B7 seven capture compare registers is implemented in MSP430x14x and MSP430x16x devices Topic Page 12 1 mimer B introduction ee e 22 520 12 2 12 2 TimMer B Operation 12 4 12 3 mimer B Registers 7 12 20 12 1 Timer B Introduction 12 1 Timer B Introduction Timer B is a 16 bit timer counter with three or seven capture compare registers Timer B can support multiple capture compares PWM outputs and interval timing Timer B also has extensive interrupt capabilities Interrupts may be generated from the counter on overflow conditions and from each of the capture compare registers Timer B features include Lj Asynchronous 16 bit timer counter with four operating modes and four selectable lengths Selectable and configurable clock source Three or seven configurable capture compare registers Configurable outputs with PWM capability Double buffered compare latches with synchronized loading LLL OLD DQ Interrupt vector register for fast decoding of all Timer B interrupts The block diagram of Timer B is shown in Figure 12 1 Note Use of the Word Count Count is used throughout this chapter It means th
337. x ADC12CLK Conversion Completed Result Stored Into ADC12MEMXx ADC12IFG x is Set x pointer to ADC12MCTLx ADC12 17 13 ADC12 Operation Repeat Sequence of Channels Mode A sequence of channels is sampled and converted repeatedly The ADC results are written to the conversion memories starting with the ADC12MEMx defined by the CSTARTADDXx bits The sequence ends after the measurement of the channel with a set EOS bit and the next trigger signal re starts the sequence Figure 17 9 shows the repeat sequence of channels mode Figure 17 9 Repeat Sequence of Channels Mode CONSEQx 11 ADC12ON 1 x CSTARTADDx Wait for Enable SHSx 0 and ENC 1 0rd and ADC12SC amp Wait for Trigger ENC 0 and EOS x 1 SAMPCON 4 SAMPCON 1 Sample Input Channel Defined in If EOS x 1 then x ADC12MCTLx CSTARTADDx else if x lt 15 then x x 1 else SAMPCON Y x 0 If EOS x 1 then x 1 x ADC12CLK CSTARTADDx else if x lt 15 then x x 1 else MSC 0 0 or i SHP 0 Bos i and SHP 1 1 x ADC12CLK ENC 1 and Conversion or ENC 1 Completed EOS x 0 or Result Stored Into ADC12MEMx EOS x 0 ADC12IFG x is Set X pointer to ADC12MCTLx 17 14 ADC12 ADC12 Operation Using the Multiple Sample and Convert MSC Bit To configure the converter to perform successive conversions automatical

System Resets, Interrupts, and Operating Modes

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