CLC018 8 x 8 Digital Crosspoint Switch, 1.485
Contents
1. Load I P 0 to All O Ps TRI STATE All O P 0 TRI STATE O P 0 TRI STATE O P 1 TRI STATE O P 2 O ooo X X X w ee x X X Po o x XX X 0 1 X 1 1 1 1 o o o o Xx X a a lo TRI STATE O P CBA 23 w gt o o o Load I P POR to O P CBA and Enable O P CBA Load I P 0 to O P 0 Load I P 0 to O P 1 Load I P 0 to O P 2 Load I P 0 to O P 3 Load I P 0 to O P 4 Load I P 0 to O P 5 Load I P 0 to O P 6 Load I P 0 to O P 7 Load I P 1 to O P 0 Load I P 1 to O P 1 Load I P 1 to O P 2 oj olo ol o o o o o o o o oo olo o o o o o o o Oo o o o o o o o o o o o a o o o o o o o o o o o o o o o o o o o o o o o o o o xvc o o o o o o o o o o o o o o o o o o o o o o gs a Load I P 1 to O P 3 Load I P 1 to O P 7 Load I P 7 to O P 6 16 Submit Documentation Feedback Product Folder Links CLC018 Copyright 2004 2006 Texas Instruments Incorporated OBSOLETE li TEXAS INSTRUMENTS CLC018 www ti com SNLS019C MAY 2004 REVISED AUGUST 2006 CONFIGURATION TRUTH TABLE continued 1 1 1 1 1 1 0 0 0 1 Load I P 7 to O P 7 X X X X X X X 0 0 1 Activate New Configuration Copyright 2004 2006 Texas Inst2. CLC018 NE SNLS019C MAY 2004 REVISED AUGUST 2006 www ti com CONNECTION DIAGRAM Top View CLC018 64 Lead POFP See Package Number NBH0064A PIN DESCRIPTIONS POWER PINS Vec is the most positive rail for the data path When the data levels are ECL compatible then Vcc should be connected to GND For PECL data 5V referenced ECL Vcc is connected to the 5V supply Please refer to the Device Operation section in this datasheet for recommendations on the bypassing and ground power plane reguirements of this device Veg is the most negative rail for the data path When the data levels are ECL compatible then Vegg is connected to a 5 2V power supply For PECL data 5V referenced ECL V gg is connected to GND Vit is the logic level power supply If the control signals are referenced to 5V VL is connected to a 5V supply If control signals are ECL compatible Vi is connected to GND DATA INPUT PINSDIO and DIO through DI7 and D17 are the data input pins to the CLC018 Depending upon how the Power pins are connected please refer to the Power Pins section the data may be either differential ECL or differential PECL To drive the CLC018 inputs with a single ended signal please refer to the section Using Single Ended Data in the OPERATION section of this datasheet DATA OUTPUT PINS DOO and DOO through DO7 and DO7 are the data output pins of the CLC018 The CLC018 outputs are differential current outputs which can be converted
3. I I i i LOAD S N I i I I I i I I I I I I l I i I I I I I I I I I I i i i l l Data Data DATA i t OUT I I I I I I I t7 t8 t9 I I IG gt Figure 10 Timing Diagram Switch Configuration OPERATION INPUT INTERFACING The inputs to the CLC018 are high impedance differential inputs see the equivalent input circuit in Figure 11 The CLC018 can be operated with either ECL or PECL 5V referenced ECL depending upon the power supply connections The inputs are differential and must both be within the range of Voc 2V to Voc 0 4V in order to function properly Figure 11 Equivalent Input Circuit 8 Submit Documentation Feedback Copyright 2004 2006 Texas Instruments Incorporated Product Folder Links CLC018 OBSOLETE Ii TEXAS INSTRUMENTS CLC018 www ti com SNLS019C MAY 2004 REVISED AUGUST 2006 SINGLE ENDED INPUTS Differential inputs are the preferred method of providing data to the CLC018 however there are times when the only signal available is single ended To use the CLC018 with a single ended input the unused input pin needs to be biased at a point higher than the low logic level and lower than the high logic level For best noise performance the middle of the range is best For ECL signals this point is about 2 diode drops below ground It is possible to bias the unused input with a low pass filtered version of the data as shown in Figure 12 In som
4. At the fast transition times of the CLC016 small amounts of stray capacitance at outputs can produce large output and supply transient currents Controlling transient currents requires particular attention to minimizing stray capacitances and to providing effective bypassing in the design Good and effective bypassing consisting of 0 01 uF to 0 1 uF monolithic ceramic and 4 7 uF to 10 uF 35V tantalum capacitors These capacitors should be placed as close to power pins as practical and tightly connected to the power plane sandwich using multiple vias Needless to say multilayer board technology should be employed for the CLC018 and similar high frequency capability devices CONFIGURING THE SWITCH The CLC018 can be configured so that any output may be independently connected to any input and any input be connected to any or all outputs Each output may be independently enabled or placed in a high impedance state Data controlling the switch matrix and output mode are stored in two ranks of eight 4 bit registers one register per output The three most significant bits in each register identify the input to be connected to that output The least significant bit controls whether the output is active or TRI STATE A particular register in the first rank the LOAD REGISTERS is selected by a 3 bit word placed on the output address OA bus Data to be written into the load register consisting of the 3 bit address of the input to be connected to that outp
5. disclaimers thereto appears at the end of this data sheet All trademarks are the property of their respective owners PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters Copyright 2004 2006 Texas Instruments Incorporated OBSOLETE CLC018 SNLS019C MAY 2004 REVISED AUGUST 2006 CLC018 BLOCK DIAGRAM LE ES Input Address TRI Output Address 1 TEXAS INSTRUMENTS www ti com Output Eye Pattern 1 4Gbps 150ps div A These devices have limited built in ESD protection The leads should be shorted together or the device placed in conductive foam hid during storage or handling to prevent electrostatic damage to the MOS gates ABSOLUTE MAXIMUM RATINGS Supply Voltage Vcc V EE 0 3V to 6 0V Vit Maximum Voc 6V Vit Minimum Voc 0 5V Storage Temperature Range 65 C to 150 C Lead Temp Soldering 4 sec 260 C ESD Rating TBD 83 64 Pin QFP 75 C W Package Thermal Resistance 8 c 64 Pin QFP 15 C W Reliability Information Transistor Count 3000 1 Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured They are not meant to imply that the devices should be operated at these limits The table of Electrical Characteristics specifie
6. 2 Connect Vcc and Vi to the ground plane 3 A power plane isn t required for Vee but can be used 1 Bypass each Vcc supply with a 0 01 uF capacitor 2 Bypass the Vit supply with a 0 01 uF 3 Connect Vee to the ground plane 4 Use a 5V power plane for Vcc EXPANDING THE NUMBER OF OUTPUT PORTS To expand the number of output ports in a switch array the inputs of multiple CLC018s are connected in parallel The bus used to connect the input ports should be a controlled impedance transmission line as shown in Figure 18 To control the switch array the IA OA and TRI buses are all connected in parallel and a decoder is used to assert high the CS of the CLC018 that is to be addressed This is also shown in Figure 18 Copyright 2004 2006 Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links CLC018 OBSOLETE I TEXAS CLC018 INSTRUMENTS SNLS019C MAY 2004 REVISED AUGUST 2006 www ti com OA3 CS OA3 CLC018 OUT CS OA5 CLC018 TRI Figure 18 8 x 16 Crosspoint Example EXPANDING THE NUMBER OF INPUT PORTS Expanding the number of inputs in a switch array is accomplished by wire ORing the outputs together and TRI STATEing the outputs of the CLC018s that do not have their inputs selected The output bus should be a controlled impedance transmission line with proper termination This is shown in Figure 19 The circuit uses a 1 of 2 decoder with complemented outputs
7. ITY The output signal eye pattern shown in Figure 17 was acquired using an Agilent 86100A scope and 86112A plug in along with a TEK P6330 3GHz differential probe The differential signal was probed across the output pins of the CLC018 75 Ohm pull up resistor were used as shown in Figure 16 A PRBS23 pattern was driven through the part and the resulting eye pattern is shown in Figure 17 The eye pattern is affected by the HF roll off of the probe which degrades the output transition time and affects jitter Even with this loading the CLC018 provides excellent signal quality and low jitter at 1 485 Gbps Note 150 ps div and 250 mV div Copyright 2004 2006 Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links CLC018 OBSOLETE f CLC018 NE SNLS019C MAY 2004 REVISED AUGUST 2006 www ti com Figure 17 1 485 Gbps Eye Pattern POWER SUPPLIES GROUNDING AND BYPASSING The CLC018 uses separate power supplies for control and data circuitry Data circuitry is supplied via Vcc and control circuitry via Vi Supply connection Veg the negative most supply is the common return for both Connection details for the different powering modes is shown in Table 1 Internal and external capacitances normal and parasitic must be charged and discharged with changes in output voltage Charging current depends upon the size of these capacitances and the rate of change of voltage
8. OBSOLETE I TEXAS INSTRUMENTS www ti com CLC018 SNLS019C MAY 2004 REVISED AUGUST 2006 CLC018 8 x 8 Digital Crosspoint Switch 1 485 Gbps Check for Samples CLC018 FEATURES e Supports SMPTE 259M SMPTE 344M and SMPTE 292M Fully Differential Signal Path e Non Blocking Flexible Expansion to Larger Array Sizes with Very Low Power e Single 5 5V or Dual 5V Operation TRI STATE Outputs Double Row Latch Architecture e 64 Lead QFP Package APPLICATIONS Routing Switchers e Production Switchers Master Control Switchers Telecom Datacom Switchers Storage Area Network SAM e Packet Switching e ATM SONET KEY SPECIFICATIONS High Speed gt 1 485 Gbps e Low Jitter lt 50 pSpp for Rates lt 500 Mbps lt 100 pspp for Rates lt 1 485 Gbps e Low Power 850 mW with all Outputs Active Fast Output Edge Speeds 250 ps DESCRIPTION The CLC018 is a fully differential 8x8 digital crosspoint switch capable of operating at data rates exceeding 1 485 Gbps per channel Its non blocking architecture utilizes eight independent 8 1 multiplexers to allow each output to be independently connected to any input and any input to be connected to any or all outputs Additionally each output can be individually disabled and set to a high impedance state This TRI STATE feature allows flexible expansion to larger switch array sizes Low channel to channel crosstalk allows the CLC018 to p
9. T OUT 8 CT1 RS1 1 of 4 1of4 1A3 Select CT2 OA3 Select RS2 1A4 CT3 OA4 RS3 NC RS4 Figure 20 24 x 32 Output Switch Array 14 Submit Documentation Feedback Copyright 2004 2006 Texas Instruments Incorporated Product Folder Links CLC018 OBSOLETE li TEXAS INSTRUMENTS CLC018 www ti com SNLS019C MAY 2004 REVISED AUGUST 2006 CALCULATING THE POWER DISSIPATION IN AN EXPANDED ARRAY The CLC016 dissipates about 100 mW per active output plus about 50 mW quiescent power With all outputs active this is about 850 mW In an expanded array all devices will dissipate quiescent power but only those devices with active outputs will dissipate the 100 mW output So an N by M device array an 8xN input by 8xM output switch with all outputs active will dissipate N x M x 50 mW 8 x M x 100 mW A 32 input x 32 output 4 x 4 device switch array dissipates 4 x 4 x 50 mW 8 x 4 x 100 mW 4W CONTROLLED IMPEDANCE TRANSMISSION LINES AND OTHER LAYOUT TECHNIQUES All transmission lines whose length is greater than 1 4 wavelength of the highest frequencies present in the transmitted signal require proper attention to impedance control to avoid distortion of the signal Digital signals are especially susceptible to distortion due to poorly controlled line characteristics and reflections With its 250 ps output transitions which imply a bandwidth of 4 GHz or more transmission lines driven by the CLC018 must be carefully designed and correctly termin
10. ated Either microstrip line which resides on the outer surfaces of a printed circuit board and paired with an image ground plane or stripline which is sandwiched in an inner layer between image ground planes may be used in CLC018 designs With either line type it is important to maintain a uniform characteristic impedance over the entire extent of the transmission line system Likewise the receiving end of these lines must be terminated in a resistance equal to the characteristic impedance to preserve signal fidelity Figure 21 shows representative methods of interfacing to and from the CLC018 Often when voltage mode drivers such as ECL with low output impedance also called equivalent generator resistance are used to drive bus networks a series resistor connects the output of the amplifier to the transmission line This resistor serves both as a termination for any signals travelling toward the source end of the line and as the series leg of a voltage divider with the transmission line as the shunt leg to reduce the transmitted signal level This resistor s correct value is Zo R our However a value equal to Zo may be used successfully in most situations The receiving end of the line is terminated in a resistance equal to the value of Zo of the receiving end of the line A resistance equal to the line s Zo works in most situations In cases where the bus is heavily loaded the receiving end termination s value may need to be reduced to the
11. ay T7 20 ns CNFG to Output TRI STATE Delay Tg 20 ns CNFG to Output Active Delay To 70 ns CONTROL TIMING RESET TRI to RES 1 Setup Time T149 5 ns RES to TRI Hold Time T41 5 ns Min Pulse Width RES T42 10 ns RES 1 to TRI STATE Mode Delay T43 20 ns RES 1 to Broadcast Mode Delay T44 70 ns STATIC PERFORMANCE Signal I O Min Input Swing Differential See 19 150 200 200 mVpp Input Voltage Range Lower Limit 2 V Input Voltage Range Upper Limit 0 4 V Input Bias Current See 19 and 11 1 5 0 4 3 1 0 3 3 8 HA output Output Current See 10 10 7 8 53 12 80 7 20 14 3 mA Output Voltage Swing RLoap 750 800 640 960 540 1060 mV Output Voltage Range Lower Limit 2 5 V Output Voltage Range Upper Limit 0 V 1 VL and all VEE supply pins are bypassed with 0 01 uF ceramic capacitor 2 Min max ratings are based on product characterization and simulation Individual parameters are tested as noted Outgoing quality levels are determined from tested parameters Bit error rate less than 1079 over 50 of the bit cell interval Measured using a pseudo random 2 3 1 pattern binary sequence with all other channels active with an uncorrelated signal Spread in propagation delays for all input output combinations Measured between the 20 and 80 levels of the waveform Refer to the Configuration Timing Diagram Refer to the Reset Timing Diagram J level spec is 100 tested at 25 C 3 4 5 6 7 Differe
12. e coding schemes there are pathological patterns that result in long sequences with no data transitions During these patterns the bias on the unused input will drift towards the other input reducing the noise immunity which makes this scheme undesirable The most robust solution for single ended inputs is to place a comparator with hysteresis in front of the CLC018 Such a part is the MC10E1652 See Figure 13 for an example of how to hook this up CLC018 Hysteresis Input Control CLC018 nput plane Signal DIX DIX is MC10E1652 Figure 12 Single Ended Input to CLC018 Figure 13 Single Ended Input to CLC018 OUTPUT INTERFACING The outputs of the CLC018 are differential current source outputs They can be converted to ECL compatible levels with the use of resistive loads as shown in Figure 14 The output swings will have a similar temperature coefficient to 10KECL if a 1N4148 diode is used to set Voy For most commercial temperature range applications a 750 resistor can be used as shown in Figure 15 Many circuits with differential inputs such as the CLC016 Data Retimer With Automatic Rate Selection do not reguire true ECL levels so the load resistors can be connected directly to the positive rail as shown in Figure 16 CLC018 CLC016 Data IN4148 Retimer CLC018 750 DOX DOX Figure 14 Generating 10k ECL Figure 15 Generating ECL Figure 16 Connecting the Outputs Outputs CLC018 to the CLC016 OUTPUT SIGNAL QUAL
13. e states with TRI low all outputs are connected to input 0 with TRI high all outputs are put in TRI STATE condition TRI will program the selected output to be in a high impedance or TRI STATE condition To place an output in TRI STATE assert a logic high level on the TRI input when the desired input and output addresses are asserted on the respective address inputs and strobe the LOAD input as depicted in the 6 Submit Documentation Feedback Copyright 2004 2006 Texas Instruments Incorporated Product Folder Links CLC018 OBSOLETE l TEXAS INSTRUMENTS CLC018 www ti com SNLS019C MAY 2004 REVISED AUGUST 2006 Configuration Truth Table To enable an output assert a logic low level on the TRI input together with the appropriate addresses and strobe the LOAD input as previously described CNFG is the configuration register latch control When CNFG is high the Configuration register is made transparent and the switch matrix is set to the state loaded into the Load registers When CNFG is low the state of the switch matrix is latched TIMING DIAGRAMS RES DATA OUT TRI RES DATA OUT Invalid Data La t14 _ gt Figure 9 Timing Diagram Broadcast Reset Copyright 2004 2006 Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links CLC018 OBSOLETE I TEXAS CLC018 INSTRUMENTS SNLS019C MAY 2004 REVISED AUGUST 2006 www ti com TRI E O O O I I
14. for compliance with all legal and regulatory requirements in connection with such use TI has specifically designated certain components as meeting ISO TS16949 requirements mainly for automotive use In any case of use of non designated products TI will not be responsible for any failure to meet ISO TS16949 Products Applications Audio www ti com audio Automotive and Transportation www ti com automotive Amplifiers amplifier ti com Communications and Telecom www ti com communications Data Converters DLP Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID OMAP Applications Processors Wireless Connectivity dataconverter ti com www dlp com www ti com clocks interface ti com logic ti com microcontroller ti com www ti rfid com www ti com omap Computers and Peripherals Consumer Electronics Energy and Lighting Industrial Medical Security Space Avionics and Defense Video and Imaging TI E2E Community www ti com wirelessconnectivity www ti com computers www ti com consumer apps www ti com energy www ti com industrial www ti com medical www ti com security www ti com space avionics defense www ti com video Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2013 Texas Instruments Incorporated
15. loaded Zo of the line Please see the material on distributed loading effects on line characteristics in the Fairchild F100K ECL 300 Series Databook and Design Guide Current mode drivers with their high equivalent generator resistance when used as bus drivers require a resistance egual to Z o at each end of the bus to either power or ground as appropriate for the design A detailed discussion of digital transmission line design technigues is beyond the scope of this data sheet but many good references are available from Texas Instruments and others Extensive material is available in the Texas Instruments Interface Databook the Fairchild F100K ECL 300 Series Databook and Design Guide and the Motorola MECL System Design Handbook Especially useful is the Texas Instruments Transmission Line RAPIDESIGNERO Sliderule and user manual AN 905 SNLA035 Copyright 2004 2006 Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links CLC018 CLC018 OBSOLETE SNLS019C MAY 2004 REVISED AUGUST 2006 Input Input Bussing Voltage Source Driver CLC018 CLC018 IN IN Transmision Line CLC018 IN Output Bussing Current Outputs CLC016 IN Zo 1000 OUT OUT OUT CLC018 CLC018 CLC018 Figure 21 Input Output Busing CONFIGURATION TRUTH TABLE I TEXAS INSTRUMENTS www ti com OA2 OA1 OAO TRI RES LOAD CNFG CS Condition of Device X X X NO CHANGE X
16. n its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures monitor failures and their consequences lessen the likelihood of failures that might cause harm and take appropriate remedial actions Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety critical applications In some cases TI components may be promoted specifically to facilitate safety related applications With such components TI s goal is to help enable customers to design and create their own end product solutions that meet applicable functional safety standards and requirements Nonetheless such components are subject to these terms No Tl components are authorized for use in FDA Class III or similar life critical medical equipment unless authorized officers of the parties have executed a special agreement specifically governing such use Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use in military aerospace applications or environments Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer s risk and that Buyer is solely responsible
17. nce in propagation delay for output low to high vs output high to low transition 8 9 10 11 The bias current for high speed data input depends on the number of data outputs that are selecting that input Copyright 2004 2006 Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links CLC018 OBSOLETE I TEXAS CLC018 INSTRUMENTS SNLS019C MAY 2004 REVISED AUGUST 2006 www ti com ELECTRICAL CHARACTERISTICS continued Voc OV Vee 5V Vu OV unless otherwise specified Parameter Conditions ole pete Ne Units 85 C 2 Control Inputs Input Voltage HIGH V iu min See 12 1 0 5 0 5 V Input Voltage LOW V iL max See 12 4 4 5 4 5 V Input Voltage HIGH V iH min Vip 4 5V 12 4 4 5 4 5 V Input Voltage LOW VL max VL 512 1 0 5 0 5 V Input Current HIGH Vin Vit 1 0 2 2 0 0 1 2 5 uA Input Current LOW ViL Vu 5V2 100 200 10 250 15 uA MISCELLANEOUS PERFORMANCE Voc Supply Current All Outputs Active 12 13 14 157 127 202 119 217 mA Vcc Supply Current All Outputs TRISTATE 2 7 3 11 2 12 mA VL Supply Current Vit 0V 12 2 5 1 7 3 3 1 5 3 5 mA VL Supply Current Vip 5V 12 v mA Input Capacitance 1 5 pF Output Capacitance 2 pF 12 J level spec is 100 tested at 25 C 13 The Vec supply current is a function of the number of active data outputs lvcc 18 N 7 mA where N is an integer f
18. nfiguration of all crosspoints is effected 10 Submit Documentation Feedback Copyright 2004 2006 Texas Instruments Incorporated Product Folder Links CLC018 Ii TEXAS INSTRUMENTS www ti com OBSOLETE CLC018 SNLS019C MAY 2004 REVISED AUGUST 2006 The CLC018 Configuration Truth Table is shown at the end of the datasheet EXPANDING THE SWITCH SIZE The CLC018 was designed for easy expansion to larger array sizes without paying a significant penalty in either speed or power The power dissipation of the expanded array will be dominated by the number of active outputs therefore power will increase linearly with the array size even though the number of components reguired increases as the square of the array size As an example a single CLC018 can be used for an 8x8 array and it will dissipate about 0 85W A 32 x 32 array will require 16 CLC018s and will consume only about 4W Table 1 Interfacing of the Power Supplies and Bypass Capacitors Supply Operation Single 5V Single 5V Dual 5V VO Data Level ECL PECL ECL Control Signal Low High 5V GND GND 5V GND 5V Connection 5V 5V 5V O1LF 4 5V 0 01uF 4 1 Bypass each Veg supply with a 0 01 uF capacitor 2 Bypass the Vit supply with a 0 01 UF 3 Connect Vcc to the ground plane 4 A power plane isn t required for 5V Vy or 5V VEE supplies but can be used 5V Key Information 1 Bypass each Veg supply with a 0 01 uF capacitor
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20. rom 0 to 8 14 Ivee lycce ve 4 Submit Documentation Feedback Copyright 2004 2006 Texas Instruments Incorporated Product Folder Links CLC018 l TEXAS INSTRUMENTS www ti com Output Current mA Prop Delay ps Jitter ps rms OBSOLETE CLC018 SNLS019C MAY 2004 REVISED AUGUST 2006 TYPICAL PERFORMANCE CHARACTERISTICS Jitter vs Data Rate B a 8 no a 20 100 300 500 70 900 Data Rate Mbps Figure 1 1100 1300 Output Current vs Supply Voltage 49 5 1 Supply Voltage Figure 3 5 3 Prop Delay vs Temperature 900 850 800 750 700 650 600 20 10 40 Temperature C Figure 5 70 100 Copyright 2004 2006 Texas Instruments Incorporated Percent Eye Opening vs Data Rate 100 80 T a 60 gt if 4 P a 20 0 500 700 900 1100 1300 Data Rate Mbps Figure 2 Output Current vs Temperature 12 115 lt E z l 2 S 10 5 o a 10 6 9 5 9 50 20 10 40 70 100 Temperature C Figure 4 Total Supply Current vs Temperature 170 _ 165 lt E 160 2 5 155 o gt Q 150 o O 145 140 50 20 10 40 70 100 Temperature C Figure 6 Submit Documentation Feedback 5 Product Folder Links CLC018 OBSOLETE f
21. rovide superior all hostile jitter of 50 pspp This excellent signal fidelity along with low power consumption of 850 mW make the CLC018 ideal for digital video switching plus a variety of data communication and telecommunication applications The fully differential signal path provides excellent noise immunity and the I Os support ECL and PECL logic levels In addition the inputs may be driven single ended or differentially and accept a wide range of common mode levels including the positive supply Single 5V or 5V supplies or dual 5V supplies are supported Dual supply mode allows the control signals to be referenced to the positive supply 5V while the high speed I O remains ECL compatible The double row latch architecture utilized in the CLC018 allows switch reprogramming to occur in the background during operation Activation of the new configuration occurs with a single configure pulse Data integrity and jitter performance on unchanged outputs are maintained during reconfiguration Two reset modes are provided Broadcast reset results in all outputs being connected to input port DIO TRI STATE Reset results in all outputs being disabled The CLC018 is fabricated on a high performance BiCMOS process and is available in a 64 lead plastic quad flat pack QFP Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and
22. ruments Incorporated Submit Documentation Feedback 17 Product Folder Links CLC018 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections enhancements improvements and other changes to its semiconductor products and services per JESD46 latest issue and to discontinue any product or service per JESD48 latest issue Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All semiconductor products also referred to herein as components are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its components to the specifications applicable at the time of sale in accordance with the warranty in TI s terms and conditions of sale of semiconductor products Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by applicable law testing of all parameters of each component is not necessarily performed TI assumes no liability for applications assistance or the design of Buyers products Buyers are responsible for their products and applications using TI components To minimize the risks associated with Buyers products and applications Buyers should provide adequate design and operating safeguards TI does not warrant or represent that any license either ex
23. s conditions of device operation 2 If Military Aerospace specified devices are required please contact the Texas Instruments Sales Office Distributors for availability and specifications RECOMMENDED OPERATING CONDITIONS Supply Voltage Vcc V EE 4 5V to 5 5V Operating Temperature 40 C to 85 C Vit Voc or Voc 5V 2 Submit Documentation Feedback Product Folder Links CLC018 Copyright 2004 2006 Texas Instruments Incorporated li TEXAS INSTRUMENTS www ti com ELECTRICAL CHARACTERISTICS OBSOLETE Voc OV Vee 5V Vu OV unless otherwise specified CLC018 SNLS019C MAY 2004 REVISED AUGUST 2006 Parameter Conditions ole pete 20 C Units DYNAMIC PERFORMANCE Max Data Rate Channel NRZ See 1 485 Gbps Data Rate lt 500 Mbps 50 PSpp Channel Jitter Data Rate lt 1 485 Gbps 100 PSpp Propagation Delay input to output 0 75 ns Propagation Delay Match See 200 ps Output Rise Fall Time See 9 250 ps Duty Cycle Distortion See 10 ps CONTROL TIMING CONFIGURATION OA Bus to LOAD Setup Time T4 15 ns LOAD to OA Bus Hold Time To 0 ns IA Bus TRI to LOAD Setup Time Ta ns LOAD to IA Bus TRI Hold Time T4 ns Min Pulse Width Ts LOAD 10 ns CNFG 10 ns LOAD 1 to CNFG 1 Delay Te 0 ns CNFG f to Valid Del
24. to ECL or PECL compatible outputs through the use of load resistors Please refer to the Output Interfacing paragraph in the OPERATION section of this datasheet for more details CONTROL PINS IA2 IA1 and IA0 are the three bit input selection address bus The input port to be addressed is placed on this bus IA2 is the Most Significant Bit MSB If input port 6 is to be addressed IA2 IA1 IAO should have 1 1 0 asserted on them The IA bus should be driven with CMOS levels if V is 5V These levels are thus 5V referenced standard CMOS If V is connected to GND the input levels are referenced to the 5V and GND supplies OA2 OA1 and OAO are the output selection address bus The output port selected by the OA bus is connected to the input port selected on the IA bus when the data is loaded into the configuration registers OA2 is the MSB If OA2 OA1 OAO are set to 0 0 1 then output port 1 will be selected CS is an active high chip select input When CS is high the RES LOAD and CNFG pins will be enabled LOAD is the latch control for the LOAD register When LOAD is high the load register is transparent Outputs follow the state of the IA bus and are presented to the inputs of the Configuration register selected by the OA bus When LOAD is low the outputs of the Load register are latched RES is the reset control of the configuration and load registers A high going pulse on the RES pin programs the switch matrix to one of two possibl
25. to control the TRI pins of the CLC018s in the array Thus all CLC018s are programmed simultaneously and all of them except for the one with the selected input are placed in the TRI STATE mode EXPANDING BOTH INPUTS AND OUTPUTS To increase both the number of inputs and outputs in an array apply both the input port and output port expansion techniques simultaneously In Figure 20 this is shown for the case of a 24 input by 32 output switch array Note that both input and output buses need to be controlled impedance transmission lines The CS pins for rows of CLC018s are connected together and become the row select inputs whereas the TRI pins are connected together for the columns of CLC018s and become the column select pins 12 Submit Documentation Feedback Copyright 2004 2006 Texas Instruments Incorporated Product Folder Links CLC018 OBSOLETE li TEXAS INSTRUMENTS CLC018 www ti com SNLS019C MAY 2004 REVISED AUGUST 2006 IA3 TRI CS OA CLC018 IN OUT CS IN IAO 2 Figure 19 Expanded Input Ports Copyright 2004 2006 Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links CLC018 OBSOLETE I TEXAS CLC018 INSTRUMENTS SNLS019C MAY 2004 REVISED AUGUST 2006 www ti com INPUTS 8 8 8 RS1 cs I CS CS CT3 IN TRI IN TRI IN TRI OUT OUT OUT OUT ee Ee CS IN TRI o C i co z J wm a D Z Q o i D co oAcviIcoO TRI IN TRI IN TRI OUT OU
26. ut and the output enable control bit are placed on the input address IA bus Input data is stored in the load registers at the low to high transition of the LOAD input pin with chip select CS high true The contents of the load registers are transferred to the second rank of CONFIGURATION REGISTERS at the low to high transition of the CNFG input signal with CS high This causes the state of the entire switch matrix to be set to the selected configuration The entire crosspoint may be placed in an initializing state with all outputs connected to input 0 and with all outputs either enabled or TRI STATE To do so hold TRI low to make outputs active or high to place outputs in TRI STATE and apply a high going pulse to the RES input pin with CS high In summary outputs are configured by a First placing the 3 bit address of that output on the OA bus together with The 3 bit address of the input to be connected to that output on the IA bus The output enable TRI STATE control bit for that output on the IA bus Making chip select CS true and then Providing a high going pulse to the LOAD input pin Repeat these four steps for each output to be configured o 800 oc The entire crosspoint matrix may now be configured with the data held in the load registers To implement the configuration apply a high going pulse to the CNFG input pin The contents of the load registers are transferred to the configuration registers and the new co
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