MC68306UMAD2_AD MC68306 Integrated EC000 Processor
Contents
1. DC Electrical Specifications The DC electrical specifications on page 8 4 section 8 5 have been changed a The minimum DC Input Low Voltage is GND undershoot has been listed as a separate spec of 0 3V b The clock inputs EXTAL and X1 are CMOS inputs Clock Input Low Voltage has been respecified as a function of Vpp Pullup Pulldown and Output Current specifications have been added d Power dissipation has been recalculated for a worst case current drain of 100mA at 5 25V not 5 0V DC ELECTRICAL SPECIFICATIONS Characteristic Symbol Min Max Unit Input Low Voltage except clocks VIL GND 0 8 V Clock Input High Voltage EXTAL X1 0 8 VCc Vec V Clock Input Low Voltage EXTAL X1 VILC 0 0 2 V Undershoot B 0 3 V Pullup Current Q Vi OV HALT RESET AS UDS LDS 50 10 DTACK BERR TRST TMS TDI Pulldown Current Viy VoCTCK J 10 T5 Output Current CLKOUT RAS1 RASO CAS1 CASO IOH 8 mA DRAMW A15 DRAMA14 A1 DRAMAO IOL 8 Others IOH 4 mA IOL 4 Power Dissipation f 16 67 MHz PD 0 525 7 Operating Conditions The following table was omitted from page 8 1 OPERATING CONDITIONS Rating Min Max Unit Supply Voltage 4 75 5 25 V Input Voltage 0 VCC V Operating Temperature Range 0 70 NOTES 1 Unused input and bidirectional pins must be terminated to a valid logic one or zero l2. Figure 8 5 Chip Select and Interrupt Acknowledge Timing Diagram 21 Clock Output Timing The current drive levels and test points for the MC68306 input and output clocks are shown in the revised Fig ure 8 2 below see page 8 5 EXTAL CLKOUT Figure 8 2 Clock Output Timing MOTOROLA MC68306 USER S MANUAL ADDENDUM 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 22 DRAM Address Hold Time Specification 13A below has been added to the AC electrical specifications on page 8 5 A revised figure 8 8 from page 8 13 shows the new specification address hold from AS UDS LDS negate near state S7 A15 DRAMA 14 CLKOUT FCO FC2 A1 DRAMA 0 AS UDS LDS RW UW LW Oey LS DTACK 15 00 DRAMW 16 67 MHz Num Characteristic Min Max Unit 13A AS LDS UDS Negated to Address Invalid DRAM Cycle 0 ns Figure 8 8 DRAM Timing 0 Wait Read No Refresh 23 Interrupt Level Description Error In paragraph 6 1 4 the last sentence on page 6 3 should read When an interrupt at this level is acknowledged the serial module is serviced before the external IRQx of the same level 24 Bus Timeout Period Register Address Error In paragraph 5 2 3 on page 5 4 the bus timeout period register address should be FFFFFFFD 25 Chip Select Configuration Registe
3. 475BSC 12 06 BSC RR1 B 0 950BSC 24 13 BSC K1 Bi 0475BSC 12 06 BSC Y GAGE C 0160 0 180 406 457 0 14 ci 0 020 0 040 051 1 02 c2 0 135 0 145 343 3 68 UW D 0008 0 012 020 0 30 K 01 D1 0 012 0 016 030 0 41 D2 0 008 0 011 0 20 0 28 132X D E 0 006 0 008 0 15 0 20 0 008 0 200 T LM SN E1 0 005 0 007 0 13 0 18 F 0012 0014 0 30 0 36 SECTION AA AA G 0 025BSC 0 64 BSC J 1100BSC 27 94 BSC J1 0 550 BSC 13 97 BSC K 0 034 0 044 0 86 1 11 Ki 0 010 BSC 0 25 BSC P 1400BSC 27 94 BSC Pi 0 550 BSC 13 97 BSC Ri 0 015 REF 0 38 BSC S 1 080BSC 27 43 BSC S1 0 540 BSC 13 72 BSC 0 025 REF 0 64 REF V 1 080BSC 27 43 BSC vi 0 540BSC 13 72 BSC CASE 831A 02 ISSUE B MOTOROLA MC68306 USER S MANUAL ADDENDUM For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability i
4. Freescale Semiconductor Inc Order this document by MOTOROLA MC68306UMAD AD Microprocessor and Memory Technologies Group MC68306 ADDENDUM TO MC68306 Integrated EC000 Processor User s Manual September 8 1995 This addendum to the initial release of the MC68306UM AD User s Manual provides corrections to the original text plus additional information not included in the original This document and other information on this prod uct is maintained on the AESOP BBS which can be reached at 800 843 3451 from the US and Canada or 512 891 3650 Configure the modem for up to 14 4K baud 8 bits 1 stop bit and no parity Terminal software should support VT100 emulation Internet access is provided by telneting to pirs aus sps mot com 129 38 233 1 or through the World Wide Web at http pirs aus sps mot com 1 Reset and Three State Outputs In the signal summary tables beginning page 2 3 most outputs which three state during bus arbitration also three state during reset The DRAM control signals in Table 2 3 on page 2 3 are the exception these signals are three stated during reset but periodically drive for refresh cycles to keep DRAM data alive The DRAM control signals do not drive for refreshes during bus arbitration and alternate master tenures greater than the refresh period may result in lost refresh cycles Use pullups as indicated to keep three stated signals from inadvertently accessing memory during either bus arbitration or
5. OR N A i 1 lt A1 gt 17 N 117 E eue d 18 116 VIEW AB SA PIN 1 P1 VIEW AB IDENT BASE METAL N MW B 0 7 j A Y Y P L d pA 7 AA 1 i je D2 E1 AA WITH 50 84 PLATING Y SECTION AC AC 51 83 T Z7 0 002 0 05 L M 2X A 0 016 0 40 ax 4 0 05 NOTES O 0 012 0 30 TILMOIN 4X33 TIPS 1 DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 2 CONTROLLING DIMENSION INCH O 0 012 0 30 HILMOIN 4 3 DIMENSIONS A B J AND P DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE MOLD 0 002 0 05 N 2x PROTRUSION FOR DIMENSIONS A AND B IS 0 010 0 25 FOR DIMENSIONS J AND P IS 0 007 0 18 DATUM PLANE H IS LOCATED AT THE UNDERSIDE OF LEADS WHERE LEADS EXIT PACKAGE BODY 0 004 0 10 T DATUMS L M AND N TO BE DETERMINED WHERE CENTER LEADS EXIT PACKAGE BODY AT ZT SEATING DATUM Hi PLANE DIMENSIONS U AND V TO BE DETERMINED AT SEATING PLANE DATUM T DIMENSIONS A B J AND TO BE DETERMINED AT DATUM PLANE H DIMENSION F DOES NOT INCLUDE DAMBAR A a EC gt j F 132 PL PROTRUSIONS DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0 019 0 008 0 200 T 0 48 INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0 950 BSC 24 13 BSC H 1 0
6. a Ltd 4 32 1 Nishi Gotanda Shinagawa ku Tokyo 141 J apan ASIA PACIFIC Motorola Seminconductors H K Ltd Silicon Harbour Center No 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong te SE VICONDUCTOHR PRODUCT INFORMATION For More Information On This Product Go to www freescale com
7. d The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting BGACK Figure 8 6 on page 8 10 shows timing for 2 wire bus arbitration BGACK not used Flgure 8 7 on the following page shows timing for 3 wire bus arbitration BGACK used 18 Omission of Control Bit Definition In paragraph 7 3 on page 7 4 the following sentences should be added immediately before Table 7 1 All con trol bits with overbars and HiZ are active low Their respective output bits are enabled when a zero is shifted into the control bit The other control bits are active high 19 HiZ Control Function In table 7 2 on page 7 5 the HiZ control function in the boundry scan definition bit 67 should be shown as active low HiZ rather than active high HiZ 4 MC68306 USER S MANUAL ADDENDUM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 20 ACKx Assertion Time IACKx is shown asserted too early in Figure 8 5 on page 8 9 The figure below shows IACKx assertion time spec 70 correctly referenced to the rising edge of state S4 READ WRITE S0 S1 52 53 54 55 56 512 513 514 515 516 517 518 NOTE 1 CEU ao ae iw ee a oO 65 EX A23 A0 AS NOTE 1 LDS UDS NOTE THE WRITE CYCLE ILLUSTRATED IS PART AND SET INSTRUCTION
8. evel 8 Maximum Ratings Input Voltage On page 8 1 the maximum input voltage rating is either 7 0V or 0 3 whichever is less 9 New System Interface Specifications The following new electrical specifications have been added Num Characteristic Min Max Unit 104 AMODE IRQx Setup and Hold to RESET Negation 60 ns 105 Port Pin Setup to AS Asserted Port Pin Read 30 ns 105A Port Pin Hold from AS Negated Port Pin Read 30 ns 106 UDS LDS Asserted to Port Pin Port Write 0 60 ns 2 MC68306 USER S MANUAL ADDENDUM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 10 Drive Levels and Test Points for AC Specifications The current drive levels and test points for the MC68306 are shown in the revised Figure 8 1 below page 8 3 CLKOUT OUTPUTS 1 T p m 0 8V INPUTS 3 INPUTS 4 ALL SIGNALS 5 NOTES 1 This output timing is applicable to all parameters specified relative to the rising edge of the clock 2 This output timing is applicable to all parameters specified relative to the falling edge of the clock 3 This input timing is applicable to all parameters specified relative to the rising edge of the clock 4 This input timing is applicable to all parameters specified relative to the falling edge of the clock 5 This timing is applicable to all parameters specified rela
9. ncluding without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and M are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer Literature Distribution Centers USA EUROPE Motorola Literature Distribution Box 20912 Arizona 85036 J APAN Nippon Motorol
10. ns On page 6 6 the following paragraphs should be added 6 2 11 Channel B Receiver Clock Timer Clock RxCB TCLK IP2 This pin can be used as the channel B receiver clock source the counter timer clock source or as a dedi cated parallel input It can generate an interrupt on change of state 6 2 11 1 RxCB When used for this function the received data is sampled on the rising clock edge 6 2 11 2 Timer Clock When used for this function the counter timer decrements on the rising clock edge 6 2 11 3 IP2 When used for this function this signal is a general purpose input 6 2 12 Parallel Output OP3 6 2 12 1 Counter Timer Output Channel B Clock Output This output can be used as the open drain active low counter ready output the open drain timer output the channel B transmitter 1X clock output or the channel B receiver 1X clock output 6 2 12 2 OP3 When used for this function this output is controlled by bit three in the DUOP register 16 Receiver Clock Select Error In Table 6 5 on page 6 25 IP2 can be used as the RxCB clock input RCS3 RCSO values 1110 and 1111 are valid for CSRB only and select IP2 16X and IP2 1X clock sources respectively Lack of IP5 prevents use of a 1X transmit clock for the current implementation 17 Bus Arbitration For specification 37A on page 8 10 BGACK Asserted to BR Negated the minimum value must be met to guar antee proper operation If the maximum value is exceeded BG may be reasserte
11. r Reset State Error In paragraph 5 2 6 2 on page 5 10 the reset value of CSO bit 15 CSR Chip Select Read enable is one not zero MC68306 USER S MANUAL ADDENDUM For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc 26 DRAM Refresh Cycles The specifications for DRAM refresh timing in the AC Specifications on page 8 12 and in Figure 8 10 on page 8 14 referenced the wrong clock edges Corrected specifications and figures are shown below AC ELECTRICAL SPECIFICATIONS DRAM 16 67 MHz 0 Wait 1 Wait Num Characteristic Min Max Min Max Unit 95 CLKOUT High to CASx Asserted Refresh Cycle 0 20 0 20 ns 96 CLKOUT Low to CASx Negated Refresh Cycle 0 20 0 20 ns 98 CASx Asserted to RASx Asserted Refresh Cycle 20 60 20 60 ns 99 CLKOUT Low to RASx Asserted Refresh Cycle 0 30 0 30 ns 100 CLKOUT High to RASx Negated Refresh Cycle 0 25 0 25 ns 102 DRAMW High to RASx Asserted Refresh Cycle 20 60 20 60 ns CLKOUT DRAMW CLKOUT DRAMW RAS CAS b 1 Wait State Figure 8 10 DRAM Timing Refresh MOTOROLA MC68306 USER S MANUAL ADDENDUM 7 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 27 DRAM Timing for 1 Wait Access Figure 8 9 on page 8 14 is missing a wait state see the revised figure below Spec 13A has also been added to this figu
12. re CLKOUT FCO FC2 A15 DRAMA 14 A1 DRAMA 0 AS UDS LDS Figure 8 9 DRAM Timing 1 Wait Write No Refresh 28 Pin Assignment Orientation Error The pin assignment diagram of the 144 Lead Thin Quad Flat Pack TQFP on page 9 3 of section 9 2 should be rotated 90 degrees counter clockwise including pins As a result the pin one dot should be in the lower left hand corner The part number should still be horizontally displayed in the drawing All TQFP parts are marked such that pin one is in the lower left hand corner when viewing the part with the markings oriented normally 29 Package Dimensions Diagram Error The 132 pin package diagram on page 9 4 shows 32 pins on a side There are actually 33 pins on a side The specifications for the case size and pin spacing are correct 8 MC68306 USER S MANUAL ADDENDUM MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ni J gt je 128 G J1 La 1 X L M
13. reset 2 Pullup Recommendations The pullup resistor recommendations in the signal summary tables beginning page 2 3 are intended as gen eral guidelines only the specific values shown can be modified to suit individual applications The values shown were selected to provide reasonable rise times while remaining within DC IOL drive limits 3 Halt and Three State Outputs For section 3 4 3 Halt Operation on page 3 26 the bus interface is in an inactive state during halt The data bus three states and other outputs remain driven 4 Bus Description Error In Figure 3 27 on page 3 28 the reset time should be 132 clocks minimum Also the note that all control sig nals go inactive is wrong all bus control signals address bus data bus etc go to a high impedance state during reset The address bus on the MC68306 does not go high impedance between bus cycles as shown in all bus timing diagrams in Section 3 5 Crystal Oscillator Recommendations Crystals for either the CPU oscillator or the serial module oscillator should be specified for parallel resonant operation with series resistance less than 80Q This document contains information on a product under development Motorola reserves the right to change or discontinue this product without notice ee SEMICONDUCTOR PRODUCT INFORMATION mem 1995 Motorola Inc All Rights Reserved For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 6
14. tive to the assertion negation of another signal LEGEND A Maximum output delay specification B Minimum output hold time C Minimum input setup time specification D Minimum input hold time specification E Signal valid to signal valid specification maximum or minimum F Signal invalid to signal invalid specification maximum or minimum Figure 8 1 Drive Levels and Test Points for AC Specifications 11 Counter Timer Mode Clock Source Select Bits In Table 6 10 on page 6 31 the entry under Clock Source Select Command for Crystal or External Clock with MISC2 0 should be Crystal or External Clock Divided by 16 MOTOROLA MC68306 USER S MANUAL ADDENDUM 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 12 Memory Map Error In Table 5 1 on page 5 2 the entry for address FFFFFFF4 5 should be labeled PORT A PINS and PORT B PINS rather than PORT A PIN ASSIGNMENT and PORT B PIN ASSIGNMENT Note 4 should read Dupli cate of FFFFF7EO FFFFF7FF 13 DIV and MUL Instructions The DIVS and DIVU summaries on page 4 9 and the MULS and MULU summaries on page 4 10 incorrectly show longword L variants The 68EC306 only supports word sized W operations for these instructions 14 X1 Clock Addition The last sentence in paragraph 6 2 1 on page 6 4 should read If the serial module is not being used at all the X1 CLK input may be tied to Vcc or GND 15 IP2 OP3 Signal Descriptio
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