AT91 ARM Thumb-based Microcontrollers Application Note
Contents
1. AMEL 7 6431B ATARM 07 May 09 Signal Name AMEL Recommended Pin Connection Description ICE and JTAG TCK Pull up 100 kOhm This pin is a Schmitt trigger input No internal pull up resistor TMS Pull up 100 kOhm This pin is a Schmitt trigger input No internal pull up resistor TDI Pull up 100 kOhm This pin is a Schmitt trigger input No internal pull up resistor TDO Floating Output driven at up to Vyppiop RTCK Floating Output driven at up to Vyppiop Can be left unconnected NTRST It is strongly recommended to tie this Internal pull up resistor to Vyppiop 100 kOhm pin to Vppiopo in harsh environments In harsh environments It is strongly JTAGSEL recommended to tie this pin to GNDBU Internal pull down resistor to GNDBU 15 kOhm if not used or to add an external low Must be tied to Vyppgu to enter JTAG Boundary Scan value resistor such as 1 kOhm Reset Test NRST is configured as an output at power up Application dependent NRST Can be connected to a push button for NRST is controlled by the Reset Controller RSTC hardware reset An internal pull up resistor to Vyppiop 100 kOhm is available for User Reset and External Reset control In harsh environments It is strongly TST recommended to He this pin to GNDBU Internal pull down resistor to GNDBU 15 kOhm if not used or to add an external low value resistor such as 1 kOhm Must be tied to Vyppi2. Powers the PLL cells 0 9V to 1 1V The VDDOSC power supply pin draws small current but it VDDPLL Decoupling filtering RLC circuit is noise sensitive Care must be taken in VDDOSC power supply routing decoupling and also on bypass capacitors Supply ripple must not exceed 10mV 0 9V to 1 1V Powers the Backup I O lines VDDBU Geasnaiia a ere 100 nF 0 Slow Clock Oscillator and a part of the System are Controller Powers the oscillator 1 65V to 3 6V The VDDOSC power supply pin draws small current but it VDDOSC is noise sensitive Care must be taken in VDDOSC power Decoupling Filtering RLC circuit supply routing decoupling and also on bypass capacitors Supply ripple must not exceed 30mV Powers External Bus Interface I O lines 1 65V to 1 95V Dual voltage range supported or The voltage ranges are selected by programming the VDDIOM 3 0V to 3 6V VDDIOMSEL bit in the EBI_CSA register Deco nlin Filtern capador At power up the selected voltage is 3 3V nominal and Go M re Fyne power supply pins can accept either 1 8V or 3 3V nF an u Decoupling Filtering capacitors must be added to improve startup stability and reduce source voltage drop 3V to 3 6V Powers USB transceivers VDDUSB Decoupling Filtering capacitors 100 nF and 10yF 2 Decoupling Filtering capacitors must be added to improve H startup stability and reduce source voltage drop 1 65V to 3 6V Powers all peripherals VDDIOP Decoupling Filtering capacitors es 100 nF
3. and the Main Oscillator is bypassed Table 5 4 Supported Input Frequencies MHz 3 0 3 6864 3 84 4 4 9152 5 24288 6 0 6 144 6 4 6 5536 7 3728 8 0 9 8304 10 0 11 05920 12 0 12 288 14 31818 14 7456 16 0 16 367667 17 734470 18 432 20 0 24 0 24 576 25 0 28 224 32 0 33 0 40 0 48 0 50 0 Note Booting either on USB or on DBGU is possible with any of these input frequencies SAM BA Boot The SAM BA Boot Assistant supports serial communication via the DBGU or the USB Device Port Table 5 5 Pins Driven during SAM BA Boot Program Execution Peripheral Pin PIO Line DBGU DRXD PB14 DBGU DTXD PB15 DataFlash Boot The DataFlash Boot program searches for a valid application in the SPI DataFlash memory The DataFlash must be connected to NPCSO or NPCS1 of the SPIO Table 5 6 Pins Driven during DataFlash Boot Program Execution Peripheral Pin PIO Line SPIO MOSI PA1 SPIO MISO PAO SPIO SPCK PA2 SPIO NPCSO PA3 SPIO NPCS1 PC11 NAND Flash Boot The NAND Flash Boot program searches for a valid application in the NAND Flash memory Table 5 7 Pins Driven during NAND Flash Boot Program Execution Peripheral Pin PIO Line PIOC PIOC14 for NAND Chip Select PC14 PIOC PIOC13 for NAND Ready Busy PC13 Address Bus NAND CLE A22 Address Bus NAND ALE A21 Application Note mmm 6431B ATARM 07 May 09 es caton Note 5 5 EEPROM B
4. ARM Thumb instruction sets Embedded in circuit emulator ARM9Eu S Technical Reference Manual ARM926EJ S Technical Reference Manual Evaluation Kit User Guide AT91SAM9G20 EK Evaluation Board User Guide Using SDRAM on AT91SAM9 Microcontrollers Using SDRAM on AT91SAM9 Microcontrollers NAND Flash Support in AT91SAM9 Microcontrollers NAND Flash Support in AT91SAM9 Microcontrollers 2 Application Note mem 6431B ATARM 07 May 09 es caton Note 3 Schematic Check List CAUTION The AT91SAM9 board design must comply with the power up and power down sequence guidelines provided in the Electrical Characteristics section in the datasheet to guarantee reliable operation of the device 1V and 3 3V Dual Power Supply with 3 3V Powered Memories Schematic Example 1uH AA VDDOSC 1R 100nF 4 7uF DC DC Converter P 100nF 4 7uF GNDPLL 100nF DC DC Converter GNDBU I OREN VDDCORE 10pF 100nF cy GND 1V and 3 3V Dual Power Supply Schematic Example 3 3V external memories VDDIOM ADC VDDANA is used AMEL 6431B ATARM 07 May 09 AMEL Signal Name Recommended Pin Connection Description 0 9V to 1 1V Powers the device VDDCORE Decoupling Filtering capacitors EI 100 nF and 10yF 2 Decoupling Filtering capacitors must be added to improve H startup stability and reduce source voltage drop
5. Application dependent To reduce power consumption if USB Device is not used DDM must be left unconnected Notes 1 These values are given only as a typical example 2 Decoupling capacitors must be connected as close as possible to the microcontroller and on each concerned pin 100nF Hi VDDCORE 100nF VDDCORE 100nF i VDDCORE GND 3 The power supplies VDDIOM and VDDIOP and VDDUSB power the device differently when interfacing with memories or with peripherals 4 It is recommended to establish accessibility to a JTAG connector for debug in any case 5 Ina well shielded environment subject to low magnetic and electric field interference the pin may be left unconnected In noisy environments a connection to ground is recommended 10 Application Note memm 6431B ATARM 07 May 09 Application Note 6 Example of USB Host connection A termination serial resistor Rey must be connected to HDPA HDPB and HDMA HDMB A recommended resistor value is defined in the electrical specifications of the AT91SAM9G20 datasheet 5V 0 20A LL 2 Ei oo J OnF Rext Type A Connector HDMA or HDMB HDPA or HDPB Rext 7 Example of USB Device connection As there is an embedded pull up no external circuitry is necessary to enable and disable the 1 5 kOhm pull up Internal pull downs on DDP and DDM are embedded to prevent over consumption when the host is disconnected A termination s
6. and 10yF 2 Decoupling Filtering capacitors must be added to improve H startup stability and reduce source voltage drop 3 0V to 3 6V o VDDANA Decoupling capacitor 100 nF 2 Powers the Analog a e ADC and some Application dependent l GND pins are common to VDDCORE VDDIOM VDDIOP GND Ground and VDDUSB pins GND pins should be connected as shortly as possible to the system ground plane Application Note mem 6431B ATARM 07 May 09 es caton Note Mw Signal Name Recommended Pin Connection Description GNDBU pin is provided for VDDBU pin GNDBU Backup Ground GNDBU pin should be connected as shortly as possible to the system ground plane GNDPLL pin is provided for VDDPLL pin GNDPLL PLL and Main Oscillator Ground GNDPLL pin should be connected as shortly as possible to the system ground plane GNDANA pin is provided for VDDANA pin GNDANA Analog Ground GNDANA pin should be connected as shortly as possible to the system ground plane AMEL s 6431B ATARM 07 May 09 Signal Name AMEL Recommended Pin Connection Description Clock Oscillator and PLL XIN XOUT Main Oscillator in Normal Mode Crystals between 3 and 20 MHz Capacitors on XIN and XOUT crystal load capacitance dependent 1 kOhm resistor on XOUT only required for crystals with frequencies lower than 8 MHZ Crystal Load Capacitance to check Ccrystat AT91SAM9G20 XOUT i i l i r l Li Cor
7. 09 AMEL 13 AMEL Table 4 2 EBI Pins and External Device Connections Continued Pins of the Interfaced Device mpactFlash Signals SDRAM al a be a NAND Flash EBI_ EBI ony EBI only Controller SDRAMC SMC SDCKE CKE RAS RAS CAS CAS SDWE WE 7 NWAIT WAIT WAIT m Pxx CD1 or CD2 CD1 or CD2 Pxx CE Pxx RDY Notes 1 Not directly connected to the CompactFlash slot Permits the control of the bidirectional buffer between the EBI data bus and the CompactFlash slot Any PIO line For SDRAM connection examples See Using SDRAM on AT91SAM9 Microcontrollers application note For NAND Flash connection examples See NAND Flash Support in AT91SAM9 Microcontrollers application note 1 08 1 015 bits used only for 16 bit NAND Flash CE connection depends on the NAND Flash For standard NAND Flash devices it must be connected to any free PIO line For CE don t care NAND Flash devices it can be connected either to NCS3 NANDCS or to any free PIO line oak w LP 14 Application Note memm 6431B ATARM 07 May 09 es caton Note 5 AT91SAM Boot Program Hardware Constraints See the AT91SAM Boot Program section of the AT91SAM9G20 datasheet for more details on the boot program 5 1 AT91SAM Boot Program Supported Crystals and Input Frequencies 5 1 1 On chip RC Selected OSCSEL 0 If the Internal RC Oscillator is u
8. AT91SAM9G20 Microcontroller Schematic Check List 1 Introduction This application note is a schematic review check list for systems embedding the Atmel ARM Thumb based AT91SAM9G20 microcontroller It gives requirements concerning the different pin connections that must be consid ered before starting any new board design and describes the minimum hardware resources required to quickly develop an application with the AT91SAM9G20 It does not consider PCB layout constraints It also gives advice regarding low power design constraints to minimize power consumption This application note is not intended to be exhaustive Its objective is to cover as many configurations of use as possible The Check List table has a column reserved for reviewing designers to verify the line item has been checked AMEL T O AT91 ARM Thumb based Microcontrollers Application Note 6431B ATARM 07 May 09 2 Associated Documentation Before going further into this application note it is strongly recommended to check the latest AMEL documents for the AT91SAM9G20 microcontroller on Atmel s Web site Table 2 1 gives the associated documentation needed to support full understanding of this appli cation note Table 2 1 Associated Documentation Information Document Title User Manual Electrical Mechanical Characteristics Ordering Information Errata AT91SAM9G20 Product Datasheet Internal architecture of processor
9. I Data Bus DO to D31 Data Bus lines DO to D15 are pulled up inputs to Vyppiom DO D15 at reset D16 D31 Application dependent Note Data Bus lines D16 to D31 are multiplexed with the PIOC controller Their I O line reset state is input with pull up enabled too Address Bus AO to A25 All Address Lines are driven to 0 at reset A0 A22 PERE Application dependent A23 A25 Note A23 PC4 A24 PC5 and A25 PC10 are enabled by default at reset through the PIO controllers SMC SDRAM Controller CompactFlash Support NAND Flash Support See External Bus Interface EBI Hardware Interface on page 12 AMEL 6431B ATARM 07 May 09 AMEL i Signal Name Recommended Pin Connection Description USB Host UHP HDPA Internal pull down resistors HDPB Application dependent Refer to the electrical specifications of the AT91SAM9G20 datasheet HDMA Internal pull down resistors HDMB Application dependent Refer to the electrical specifications of the AT91SAM9G20 datasheet USB Device UDP Integrated programmable pull up resistor UDP_TXVC Integrated pull down resistor to prevent over consumption when the host is disconnected DDP Application dependent To reduce power consumption if USB Device is not used DDP must be left unconnected Integrated pull down resistor to prevent over consumption when the host is disconnected DDM
10. TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifica tions and product descriptions at any time without notice Atmel does not make any commitment to update the information contained herein Unless specifically pro vided otherwise Atmel products are not suitable for and shall not be used in automotive applications Atmel s products are not intended authorized or warranted for use as components in applications intended to support or sustain life OWERED ARMz 2008 Atmel Corporation All rights reserved Atmel Atmel logo and combinations thereof DataFlash SAM BA and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries ARM the ARM Powered logo Thumb and others are registered trade marks or trademarks of ARM Ltd Other terms and product names may be the trademarks of others 6431B ATARM 07 May 09
11. erial resistor Rex must be connected to DDP and DDM A recommended resistor value is defined in the electrical specifications of the AT91SAM9G20 datasheet 5V Bus Monitoring 27K PIO DDM DDP 3 TypeB 4 Rext Connector AMEL n 6431B ATARM 07 May 09 AMEL 4 External Bus Interface EBI Hardware Interface Table 4 1 and Table 4 2 detail the connections to be applied between the EBI pins and the external devices for each Memory Controller Table 4 1 EBI Pins and External Static Devices Connections Pins of the Interfaced Device Signa 8 bit Static re 16 bit Static 2 at 32 bit Static EBL Device Devices Device Devices Devices Device Controller SMC DO D7 DO D7 DO D7 DO D7 DO D7 DO D7 DO D7 D8 D15 D8 D15 D8 D15 D8 D15 D8 15 D8 15 D16 D23 D16 D23 D16 D23 D16 D23 D24 D31 D24 D31 D24 D31 D24 D31 AO NBSO AO NLB NLB BEO A1 NWR2 NBS2 Al AO AO WE NLB BE2 A2 A22 A 2 22 A 1 21 A 1 21 A 0 20 A 0 20 A 0 20 A23 A25 A 23 25 A 22 24 A 22 24 A 21 23 A 21 23 A 21 23 NCSO CS CS CS CS CS CS NCS1 SDCS CS CS CS CS cs CS NCS2 CS CS CS CS CS cs NCS3 NANDCS CS CS CS CS cs CS NCS4 CFCSO CS CS CS CS cs CS NCS5 CFCS1 CS CS CS CS cs cs NRD CFOE OE OE OE OE OE OE NWRO NWE WE WE WE WE WE WE NWR1 NBS1 WE NUB WE NUB BE1 NWR3 NBS3 WE NUB BE3 Note
12. oot The EEPROM Boot program searches for a valid application in the EEPROM memory con nected to the TWI Table 5 8 Pins driven during EEPROM Boot Program Execution Peripheral Pin PIO Line TWI TWCK PA24 TWI TWD PA23 5 6 SD Card Boot The SD Card Boot program searches for a valid application in the SD Card memory Table 5 9 Pins Driven during SD Card Boot Program Execution Peripheral Pin PIO Line MCI1 MCCK PA8 MCI1 MCCDA PA7 MCI1 MCDAO PA6 MCI1 MCDA1 PAQ MCI1 MCDA2 PA10 MCI1 MCDA3 PA11 SD Card Boot support depends on component version Refer to the AT91SAM9G20 datasheet AMEL 7 6431B ATARM 07 May 09 Revision History Change Request Doc Rev Comments Ref Remove PLLRCA pin from Section 3 Schematic Check List rfo 1V to 3 3V change in Section 3 Schematic Check List 5942 Add Section 5 5 EEPROM Boot and Section 5 6 SD Card Boot on page 17 6144 6431B Edit SHDN in Section 3 Schematic Check List 6028 Edit the hyperlink to AT91SAM9G20 product in Section 2 Associated Documentation on page 2 5912 Add 2 sentences at the end of Section 5 1 1 On chip RC Selected OSCSEL 0 on page 15 6143 Add a Caution paragraph on top of Section 3 Schematic Check List 6124 6431A First Issue 18 Application Note memm 6431B ATARM 07 May 09 AIMEL T Headquarters Atmel Corporation 2325 Orchard Parkway San Jo
13. op to boot on Embedded ROM BMS Application dependent Must be tied to GND to boot on external memory EBI Chip Select 0 Shutdown Wakeup Logic Application dependent A typical application connects the pin SHDN to the shutdown input of the DC DC ae Converter providing the main power The SHDN pin is a tri state output supplies No internal pull up resistor SHDN An external pull up to VDDBU is needed SHDN pin is driven low to GNDBU by the Shutdown and its value is to be higher than 1 MOhm Controller SHDWC The resistor value is calculated according to the regulator enable implementation and the SHDN level This pin is an input only WKUP OV to Vyppgu WKUP behavior can be configured through the Shutdown Controller GHDWC Application Note memm 6431B ATARM 07 May 09 es caon Note yw Signal Name Recommended Pin Connection Description PIO All PlOs are pulled up inputs at reset except those which are multiplexed with the Address Bus signals that require to be enabled as peripherals FAX PC4 A23 PC5 A24 and PC10 A25 PBx Application dependent PCx To reduce power consumption if not used the concerned PIO can be configured as an output driven at 0 with internal pull up disabled ADC 2 8V to Vvppana ADVREF is a pure analog input ADVREF Decoupling Filtering capacitors Application dependent To reduce power consumption if ADC is not used connect ADVREF to GNDANA EB
14. s 1 NWR1 enables upper byte writes NWRO enables lower byte writes 2 NWRx enables corresponding byte x writes x 0 1 2 or 3 3 NBSO and NBS1 enable respectively lower and upper bytes of the lower 16 bit word 4 NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16 bit word 5 BEx Byte x Enable x 0 1 2 or 3 12 Application Note meem 6431B ATARM 07 May 09 es caton Note Table 4 2 EBI Pins and External Device Connections Pins of the Interfaced Device CompactFlash Signals SDRAM gti True ibe Mode NAND Flash EBI_ EBI only Controller SDRAMC SMC DO D7 DO D7 DO D7 DO D7 1 00 1 07 D8 D15 D8 D15 D8 15 D8 15 1 08 1 015 D16 D31 D16 D31 AO NBSO DQMO AO AO A1 NWR2 NBS2 DQM2 A1 A1 A2 A10 A 0 8 A 2 10 A 2 10 A11 A9 SDA10 A10 A12 A13 A14 A 11 12 A15 A16 BA0 BAO A17 BA1 BAI A18 A20 A21 ALE A22 REG REG CLE A23 A24 A25 CFRNW CFRNW NCSO NCS1 SDCS CS NCS2 NCS3 NANDCS CE NCS4 CFCSO CFCSo CFCSo NCS5 CFCS1 CFcs1 CFcs1 NANDOE RE NANDWE WE NRD CFOE OE NWRO NWE CFWE WE WE NWR1 NBS1 CFIOR DQM1 IOR IOR NWR3 NBS3 CFIOW DQM3 IOW IOW CFCE1 CE1 cso CFCE2 CE2 CS1 SDCK CLK 6431B ATARM 07 May
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16. sed OSCSEL 0 and the Main Oscillator is active Table 5 1 Supported Crystals MHz 3 0 8 0 18 432 Other Crystal Boot on DBGU Yes Yes Yes Yes Boot on USB Yes Yes Yes No Note Any other crystal can be used but it prevents using the USB for SAM BA Boot If the Internal RC Oscillator is used OSCSEL 0 and the Main Oscillator is bypassed Table 5 2 Supported Input Frequencies MHz 3 0 8 0 20 0 50 0 Other Frequency Boot on DBGU Yes Yes Yes Yes Yes Boot on USB Yes Yes Yes Yes No Note Any other input frequency can be used but it prevents using the USB for SAM BA Boot For the current AT91SAM9G20 revisions A and B booting from the Internal RC Oscillator OSCSEL 0 prevents from using SAM BA Boot through the USB device interface More details in the errata section of the product datasheet 5 1 2 External 32 768 Hz Crystal Selected OSCSEL 1 If an external 32 768 Hz Oscillator is used OSCSEL 1 and the Main Oscillator is active Table 5 3 Supported Crystals MHz 3 0 3 6864 3 84 4 4 9152 5 24288 6 0 6 144 6 4 6 5536 7 3728 8 0 9 8304 10 0 11 05920 12 0 12 288 14 31818 14 7456 16 0 16 367667 17 734470 18 432 20 0 Note Booting either on USB or on DBGU is possible with any of these crystals AMEL s 6431B ATARM 07 May 09 5 2 5 3 5 4 16 AMEL If an external 32 768 Hz Oscillator is used OSCSEL 1
17. ystat i GNDPLL j x aa Crex Crex T Example for an 18 432 MHz crystal with a load capacitance of CepystaL 17 5 pF external capacitors are required C ey 12 pF Refer to the electrical specifications of the AT91SAM9G20 datasheet XIN XOUT Main Oscillator in Bypass Mode XIN external clock source XOUT can be left unconnected 3 3V Square wave signal External Clock Source up to 50 MHz Duty Cycle 40 to 60 Refer to the electrical specifications of the AT91SAM9G20 datasheet Application Note m 6431B ATARM 07 May 09 es caon Note Mw Signal Name Recommended Pin Connection Description Crystal Load Capacitance to check CoprystaL22 AT91SAM9G20 XOUT32 XINS2 32 768 kHz Crystal XOUT32 Capacitors on XIN32 and XOUT32 Slow Clock f crystal load capacitance dependent Oscillator ch Clext32 T Cl exT32 Example for an 32 768 kHz crystal with a load capacitance of CorystaLa2 12 5 pF external capacitors are required C exrt32 17pF Refer to the electrical specifications of the AT91SAM9G20 datasheet Slow Clock Oscillator Selection Application dependent ee p Must be tied to Vyppgu to select the external 32 768 Hz Please refer to the I O line considerations OSCSEL and errata section of the AT91SAM9G20 i crystal l datasheet ust be tied to GNDBU to select the on chip RC oscillator
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