ADM-XRC-II Pro (ADM-XP) Hardware Manual
Contents
1. DDR2 IO Connector Config Bridge JTAG SDRAM SSRAM SSRAM headers Control Config CPLD Flash bea Target User lt Flash Virtex FG676 2V1500 Local Bus 64 66 PCI Virtex Pro FF1704 146 Bit PCIX 133 Alpha Data PCI 2VP70 2VP125 IO Bus PCIX to Local Bus X Clocks Bridge MGT Bus Target Config DDR2 Flash SDRAM SSRAM SSRAM PN4 IO ADM XR IIPro User Manual Page 7 of 29 Version 0 2 ADM XP User Manual The physical layout is shown in the diagram below The DDR DRAM and DDR2 SSRAM devices are clam shelled and appear on both sides of the board Page 8 of 29 2V1500 Bridge 2VP70 2VP100 Target J5 Jtag Header U13 Samtec DP Connector 5 MGT s Jr 5 ier U8 Samtec 180 Connector 2 3 2 5V Select IO ADM XR IIPro User Manual Version 0 2 4 Local Bus Architecture The XP implements a multi master local bus between the bridge and the target FPGA using a 32 or 64 multiplexed address and data path The bridge design is asynchronous and allows the local bus to be run faster or slower than the PCI bus clock to suit the complexity of the user design 4 1 Local Bus signals 4 2 Local Bus Transfers ADM XP User Manual Signalling Virtex2Pro default 2 5V fast LVCMOS LVTTL 92. Name FPGA Pin Type Description ZBTx ad 0 21 Output Address bus ZBTx dq 0 31 Bidir Data bus ZBTx rw Output Read 1 Write 0 ZBTx bwe 0 3 Output Byte enables for writes ZBTx nld Output Initiates a transaction ZBTx_Cclk ZBTx_nCclk Output SSRAM Output Data Clock 2 2 nKclk Output SSRAM Clock for Inputs ZBTx DOFF Output SSRAM DLL Enable The SSRAM pins should be configured for HSTL 18 operation The SSRAM clock Cclks and Kclks are intended to be used with clock forwarding implemented in a DDR IOB with a DCM used to adjust for SSRAM clock to output delays on the data input path to the FPGA Page 13 of 29 ADM XR IIPro User Manual Version 0 2 ADM XP User Manual 5 5 Flash Memory The XP supports a flash device connected to the V2PRO for general purpose applications Typically in applications that use a PPC core the flash is used to hold bootstrap or application code The flash memory has its own set of pins located within banks 3 and 4 of the V2Pro and the IO voltage on the Flash device is set at 2 5V It is recommended that the LVCMOS 25 V2Pro IO standard be used for the Flash Interface Bank 3 amp 4 205 3V3 VCCO 2 5V Flash adv n Flash wp n Flash cs n Flash we n Flash oe n Flash rst n RC28F256K3 ad 0 23 Strataflash K3 dq 0 15 Flash clk Flash sts Flash wait 2VP70 2VP100 FF1704 5 6 Power Supply The PMC connectors supply 5V and 3V3 to the XP
3. 5 6 23 INSTALLING THE ADM XP ONTO 6 24 INSTALLING THE ADM XP IF FITTED TO AN 4 44 6 3 HARDWARE dd do du sa asm aad 7 4 LOCAL BUS 0 sa saa R R4 dd 44 sa ssa R R4 R4 44 sa mss aa 4d do du sa Ram suada dd Rod 4 9 4 1 LOCAL BUS SIGNALS oraiiio i eaa ENAA T i a AE E A AE aa A A EAE Ea a AEA EE 9 42 9 5 TARGET FPGA ets Pi Se aan Sdn sd ud sa EO 10 5 1 CONFIGURATION a a a 10 DAMES 10 53 SDRAM DDR MEMORY 0ccccccccccceseeeeceeeeeceaeeeeececeeceaeeaeeeeseeseueaueaseseseeeeeaueaueseeeeesseeauaeeseeeseeaneaseseees 12 54 DDRZSSRAML erre re eade aes d one c Se 13 5 5 FLASH MEMORY e rione P Ded aerae e ea Dey rx en ra ruv Re 14 5 6 ROWER SUPPIN tette 14 6 FRONT Viu 15 6 1 SAMTEC 180 CONNECTOR 08 8 8 SE EAEE EE EERE EREE EE EEEE R EEEE Eene nn 15 6 2 RockETIO MULTI GIGABIT TRANSCEIVERS 1 17 7 USERIO PMC PN4 REAR 4 18 8 JTAG AGCGESS conuenit never
4. 10 AD9 2V1500 PCI AD10 Target FPGA PCI BUS to AF7 2VP70 2VP100 Local Bus Bridge AG12 Signal Type Purpose lad 0 63 bidir Address and data bus Ireset unidir Reset to target lads bidir Indicates address phase Iblast bidir Indicates last word Ibterm bidir Indicates ready and requests new address phase Iready bidir Indicates that target accepts or presents new data Iclk unidir Clock to synchronise bridge and target Ibe 0 7 bidir Byte qualifiers dreq_ 0 1 unidir DMA request from target to bridge dack_ 0 1 unidir DMA acknowledge from bridge to target fhold unidir Target bus request fholda unidir Bridge bus acknowledge Please refer to the ADM XRC SDK Help for Windows supplied with the XP for information on local bus transfers Page 9 of 29 ADM XR IIPro User Manual Version 0 2 ADM XP User Manual 5 Target FPGA The target FPGA is a V2PRO 2VP70 2VP100 or 2VP125 when available an FF1704 package On the XP all of the resources such as DDR DDR2 SSRAM IO and Flash are available no matter what device is fitted The V2PRO has 8 banks of I O and banks 0 and 1 provide the User to the front panel The VCCIO voltage for banks 0 and 1 is selectable using JP1 JP1 Link Posn VCCIO Front IO 1 2 3V3 2 3 2V5 5 1 Configuration The target FPGA can be configured using two primary mechanisms In the first JTAG from the J6 header can be use
5. H26 93 Data 40 ve User 90 R56 J31 94 Data 41 ve User 92 R55 K24 95 Data 40 ve User 91 H31 96 Data 41 ve User 93 J24 97 Data 42 User 94 R58 G33 98 Data 43 ve User 96 R57 D23 99 Data 42 ve User 95 F33 100 Data 43 ve User 97 C23 101 Data 44 ve User 98 R60 E34 102 Data 45 ve User 100 R59 H24 103 Data 44 ve User 99 F34 104 Data 45 ve User 101 G24 105 Data 46 ve User 102 R62 J33 106 Data 47 ve User 104 R63 L25 107 Data 46 ve User 103 H33 108 Data 47 ve User 105 K25 109 Single 6 User 108 N a D19 110 Clock 2 User 106 R46 G22 111 Single 7 User 109 N a E28 112 Clock 2 ve User 107 F22 113 5V fused 114 5V fused ADM XR IIPro User Manual Page 25 of 29 Version 0 2 ADM XP User Manual Pin Function UCF name Tem VII Pro Pin Function UCF name Tem VII Pro Res Pin Res Pin 115 Data 48 ve User 110 R65 C32 116 Data 49 ve User 112 R61 K30 117 Data 48 ve User 111 C33 118 Data 49 ve User 113 J30 119 50 User 114 R68 H34 5 120 Data 51 ve User 116 R66 F24 121 Data 50 ve User 115 G34 5 122 Data b1 ve User 117 E24 123 Data 52 ve User 118 R71 D33 124 Data 53 ve User 120 R69 L23 125 Data 52 ve User 119 E33 126
6. eer emn a c e Ce aor x xr be s D Ee a e EE e n 19 8 1 6 19 9 5252 vets ae aveo sie ee 20 9 1 INTRODUCTION 52 t EI IM md uM LI 20 92 GENERAL PURPOSE l Q iiu Paca 20 MI MIL MULT 20 9 4 21 9 5 INPUT AND OUTPUT ASSIGNMENTS 22 9 5 1 Mictor VO 22 9 5 2 22 9 5 3 23 9 5 4 ee ae a wa So wg ET 23 10 USER I O XRM 10146 FRONT PANEL VARIANT 2 0 24 11 USER I O XRM 10146 ROCKET uu cccccccccccsscseseseseceenessesesesecueeeneeesauenaeenssueseeuseneausaueeeeeaesaneseeeeeeeneaes 27 ADM XR IIPro User Manual Page 4 of 29 Version 0 2 ADM XP User Manual 1 Introduction The ADM XP XP is an advanced PCI Mezzanine PMC supporting Xilinx Virtex II PRO
7. ve User 49 K17 50 Data 21 ve User 51 F15 51 Data 22 ve User 52 R27 H17 52 Data 23 ve User 54 R26 C14 53 Data 22 ve User 53 J17 54 Data 23 ve User 55 C15 55 Data 24 ve User 56 R29 G18 56 Data 25 ve User 58 R28 L16 57 Data 24 ve User 57 H18 58 Data 25 ve User 59 M16 59 Data 26 ve User 60 R37 E17 60 Data 27 ve User 62 R30 J16 61 Data 26 ve User 61 E18 62 Data 27 ve User 63 K16 63 Data 28 ve User 64 R41 J19 64 Data 29 ve User 66 R38 H16 65 Data 28 ve User 65 K19 66 Data 29 ve User 67 G16 67 Data 30 ve User 68 R44 G19 68 Data 31 ve User 70 R42 M18 69 Data 30 ve User 69 H19 70 Data 31 ve User 71 M17 71 Single 3 User 37 N a J27 72 Clock 1 ve User 72 R67 K21 73 Single 4 User 38 N a K27 74 Clock 1 ve User 73 J21 75 5V fused 76 Single 5 User 39 N a F19 Pin Function UCF Term VII Pro Pin Function UCF Term VII Pro name Res Pin name Res Pin 77 Data 32 User 74 R48 G27 78 Data 33 ve User 76 R45 C28 79 Data 32 ve User 75 27 80 Data 33 User 77 C29 81 Data 34 ve User 78 R50 K26 82 Data 35 ve User 80 R49 C30 83 Data 34 ve User 79 L26 84 Data 35 ve User 81 D30 85 Data 36 ve User 82 R52 M24 86 Data 37 ve User 84 R51 M26 87 Data 36 ve User 83 L24 88 Data 37 ve User 85 M25 89 Data 38 ve User 86 R54 E26 90 Data 39 ve User 88 R53 J26 91 Data 38 ve User 87 E25 92 Data 39 ve User 89
8. 143 MGT SYS RXP2 N a A39 144 MGT SYS TXP2 N a A40 145 MGT SYS RXN2 N a A38 146 MGT SYS TXN2 N a A41 147 Single 11 N a M27 148 Single 2 R47 E19 149 Single 10 N a L27 150 Single 3 F19 151 Single 9 152 Single 8 Notes 1 Data signals can be used for differential Pairs or single ended signals 2 Clock can be used for differential clocks or single ended clock signals 3 XRM 10146 connector AMP TYCO 767044 4 152 pin Receptacle 4 Suggested mating part AMP TYCO 1 767007 1 152 pin Mictor Plug or similar ADM XR IIPro User Manual Page 29 of 29 Version 0 2
9. Data 53 ve User 121 K23 127 Data 54 ve User 122 R73 C24 128 Data b5 ve User 124 R72 H30 129 Data 54 ve User 123 D24 130 Data 55 ve User 125 G30 131 Data 56 ve User 126 R77 F30 132 Data 57 ve User 128 R74 H25 133 Data b6 ve User 127 E30 134 Data 57 ve User 129 G25 135 Data 58 ve User 130 R79 L31 136 Data 59 ve User 132 R78 F31 137 Data 58 ve User 131 K31 138 Data 59 ve User 133 G31 139 Data 60 ve User 134 R81 G26 140 Data 61 ve User 136 R80 M30 141 Data 60 ve User 135 F26 142 Data 61 ve User 137 L30 143 Data 62 ve User 138 R84 F32 144 Data 63 ve User 140 R21 H23 145 Data 62 ve User 139 E32 146 Data 63 ve User 141 J23 147 Single 8 User 144 N a F28 148 Clock 3 ve User 142 R47 J22 149 Single 9 User 145 N a L27 150 Clock 3 ve User 143 K22 151 5V fused 152 5V fused Notes 1 Data signals can be used for differential Pairs or single ended signals 2 Clock can be used for differential clocks or single ended clock signals 3 XRM 10146 connector AMP TYCO 767044 4 152 pin Mictor Receptacle 4 Suggested mating part AMP TYCO 1 767007 1 152 pin Mictor Plug or similar 5 When using the Virtex Pro DCI these pins are not available for ADM XR IIPro User Manual Page 26 of 29 Version 0 2 ADM XP User Manual 11 User I O XRM 10146 Rocket The 0
10. G9 IO 1P 1 17 18 IO 34P 1 E13 H9 IO 1N 1 19 20 IO 34N 1 F13 J12 IO 25N 1 21 22 IO 2N 1 E9 H12 IO 25P 1 23 24 IO 2P 1 F9 M13 IO 28N 1 25 26 IO 29P 1 K13 L13 IO 28P 1 27 28 IO 29N 1 J13 L12 IO 21N 1 29 30 IO 20P 1 C11 K12 IO 21P 1 31 32 IO 20N 1 C10 G17 IO 49N 1 33 34 IO 26N 1 F12 F17 IO 49P 1 35 36 IO 26P 1 G12 D16 IO 50P 1 37 38 IO 75P 1 F21 3V3 39 40 75 1 21 3V3 41 42 Serial ID 3V3 43 44 Nc 5V 45 46 Vref1 Note 1 5V 47 48 2V5 Vbatt 49 50 2V5 12V 51 52 2V5 12V 53 54 12V Presence 55 56 TDI TCK 57 58 TRST TMS 59 60 TDO Note 1 Vref1 can be provided by the XRM if required and is applied to banks 0 and 1 in common Note 2 TCK TMS TDI and TDO are connected to the Coolrunner and not the V2PRO ADM XR IIPro User Manual Page 15 of 29 Version 0 2 ADM XP User Manual Continued FPGA Signal Connector Pins Signal FPGA Pin Pin D20 IO 73N 1 61 62 68N 1 H20 C20 IO 73P 1 63 64 68P 1 J20 K17 IO 47N 1 65 66 IO 37N 1 F15 L17 IO 47P 1 67 68 IO 37P 1 E15 J17 IO 48N 1 69 70 38N 1 C15 H17 IO 48P 1 71 72 38P 1 C14 H18 IO 55N 1 73 74 IO 39P 1 L16 G18 IO 55P 1 75 76 IO 39 1 16 17 56 1 77 78 IO 43N 1 K16 E18 IO 56N 1 79 80 IO 43 1 J16 K19 IO 59N 1 81 82 IO 44P 1 H16 J19 IO 59P 1 83 84 44N 1 G16 H19 IO 60N 1 85 86 IO 46N 1 M17 G19 IO 60P 1 87 88 IO 46
11. V2PRO devices the latest development in FPGA technology The XP supports 2VP70 2VP100 or 2VP125 devices with two embedded PowerPC processors The XP utilises an FPGA PCI bridge developed by Alpha Data supporting 64 bit PCI at up to 66MHz Future enhancements will provide compatibility with PCI X A high speed multiplexed address and data bus connects the bridge to the target FPGA Memory resources provided on board include DDR SDRAM DDR2 55 and flash all of which are optimised for direct use by the FPGA using IP and toolkits provided by Xilinx Flexible I O is the key to the ADM XRC II series of boards and the is compatible with a wide selection of XRM modules that use the 180 pin Samtec interface 1 4 Specifications The ADM XP supports high performance PCI operation without the need to integrate proprietary cores into the FPGA Physically conformant to IEEE P1386 Common Mezzanine Card standard High performance PCI and asynchronous local bus Local bus speeds of up to 80MHz Four banks of 256K 32 bits of DDR2 SSRAM option for 512K 32 bits Two banks of 64MB DDR SDRAM option for 128MB Two flash devices of 16MB each for bridge and target devices User clock programmable between 5MHz and 200MHz User front panel adapter with up to 146 free IO signals Supports 3 3V PCI or PCIX at 64 bits On board 125MHz LVPECL oscillator 8 x RocketlO Multi Gigabit Transceiver Connections optional 2 5Gb s ADM XR IIPro User M
12. 42 ve User 95 F33 100 Data 43 ve User 97 C23 101 Data 44 ve User 98 R60 E34 102 Data 45 ve User 100 R59 H24 103 Data 44 ve User 99 F34 104 Data 45 ve User 101 G24 105 Data 46 ve User 102 R62 J33 106 Data 47 ve User 104 R63 L25 107 Data 46 ve User 103 H33 108 Data 47 ve User 105 K25 109 Data 50 ve User 108 N a J22 110 Clock 2 ve User 106 R46 G22 111 Data 50 ve User 109 N a K22 112 Clock 2 ve User 107 F22 113 5V fused 114 5V fused ADM XR IIPro User Manual Page 28 of 29 Version 0 2 ADM XP User Manual Pin Function Tem VII Pro Pin Function Tem VII Pro UCF name Res Pin UCF name Res Pin 115 MGT SYS RXP22 N a BB35 116 MGT SYS TXP22 N a BB36 117 MGT SYS RXN22 N a BB34 118 MGT SYS TXN22 N a BB37 119 MGT SYS RXP11 N a A3 120 MGT SYS TXP11 N a A4 121 SYS RXN11 N a A2 122 MGT SYS TXN11 N a A5 123 Single 5 R71 D19 124 Single 7 R69 F28 125 Single 4 C19 126 Single 6 E28 127 MGT SYS RXP10 N a A7 128 MGT SYS TXP10 N a A8 129 MGT SYS RXN10 N a A6 130 MGT SYS TXN10 N a A9 131 MGT SYS RXP15 N a BB7 132 MGT SYS TXP15 N a BB8 133 MGT SYS RXN15 N a BB6 134 MGT SYS TXN15 N a BB9 135 MGT SYS RXP14 N a BB3 136 MGT SYS TXP14 N a BB4 137 MGT_SYS_RXN14 Nia BB2 138 MGT_SYS_TXN14 Nia BB5 139 MGT_SYS_RXP3 Nia A35 140 MGT SYS TXP3 N a A36 141 MGT SYS RXN3 N a A34 142 MGT SYS TXN3 N a A37
13. C13 9 Data 4 ve User 8 R5 H10 10 Data 5 ve User 10 R6 L19 11 Data 4 ve User 9 J10 12 Data 5 ve User 11 M19 13 Data 6 ve User 12 R7 F10 14 Data 7 ve User 14 R8 K18 15 Data 6 ve User 13 G10 16 Data 7 ve User 15 L18 17 Data 8 ve User 16 R9 L20 18 Data 9 ve User 18 R10 E13 19 Data 8 ve User 17 K20 20 Data 9 ve User 19 F13 21 Data 10 ve User 20 R11 H12 22 Data 11 ve User 22 R12 F9 23 Data 10 ve User 21 J12 24 Data 11 ve User 23 E9 25 Data 12 ve User 24 R14 L13 26 Data 13 ve User 26 R15 K13 27 Data 12 ve User 25 M13 28 Data 13 ve User 27 J13 29 Data 14 ve User 28 R16 K12 30 Data 15 ve User 30 R17 C11 31 Data 14 ve User 29 L12 32 Data 15 ve User 31 C10 33 Data 48 ve User 34 N a C32 34 Clock 0 ve User 32 R64 F21 35 Data 48 ve User 35 C33 36 Clock 0 ve User 33 G21 37 5V fused 38 Single1 User 36 Nia D16 Pin Function UCF Term VII Pro Pin Function UCF Term VII Pro name Res Pin name Res Pin 39 Data 16 ve User 40 R19 F17 40 Data 17 ve User 42 R20 G12 41 Data 16 ve User 41 G17 42 Data 17 ve User 43 F12 43 Data 18 ve User 44 R23 C20 44 Data 19 ve User 46 R22 J20 45 Data 18 ve User 45 D20 46 Data 19 ve User 47 H20 47 Data 20 ve User 48 R25 L17 48 Data 21 ve User 50 R24 E15 49 Data 20 ve User 49 K17 50 Data 21 ve User 51 F15 51 Data 22 ve User 52 R27 H17 52 Data 23 ve User 54 R26 C14 53 Data 22 ve User 53 J17 54 Data 23 ve U
14. Data 1 ve User 3 G13 5 Data 2 ve User 4 R3 E11 6 Data 3 ve User 6 R2 D13 7 Data 2 ve User 5 F11 8 Data 3 ve User 7 C13 9 Data 4 ve User 8 R5 H10 10 Data 5 ve User 10 R6 L19 11 Data 4 ve User 9 J10 12 Data 5 ve User 11 M19 13 Data 6 ve User 12 R7 F10 14 Data 7 ve User 14 R8 K18 15 Data 6 ve User 13 G10 16 Data 7 ve User 15 L18 17 Data 8 ve User 16 R9 G9 5 18 Data 9 ve User 18 R10 E13 19 Data 8 ve User 17 H9 5 20 Data 9 ve User 19 F13 21 Data 10 ve User 20 R11 H12 22 Data 11 ve User 22 R12 F9 23 Data 10 ve User 21 J12 24 Data 11 ve User 23 E9 25 Data 12 ve User 24 R14 L13 26 Data 13 ve User 26 R15 K13 27 Data 12 ve User 25 M13 28 Data 13 ve User 27 J13 29 Data 14 ve User 28 R16 K12 30 Data 15 ve User 30 R17 C11 31 Data 14 ve User 29 L12 32 Data 15 ve User 31 C10 33 Single 0 User 34 N a D16 34 Clock 0 ve User 32 R64 F21 35 Single 1 User 35 N a E19 36 Clock 0 ve User 33 G21 37 5V fused 38 Single 2 User 36 N a C19 Pin Function UCF Term VII Pro Pin Function UCF Term VII Pro name Res Pin name Res Pin 39 Data 16 ve User 40 R19 F17 40 Data 17 ve User 42 R20 G12 41 Data 16 ve User 41 G17 42 Data 17 ve User 43 F12 43 Data 18 ve User 44 R23 C20 44 Data 19 ve User 46 R22 J20 45 Data 18 ve User 45 D20 46 Data 19 ve User 47 H20 47 Data 20 ve User 48 R25 L17 48 Data 21 ve User 50 R24 E15 49 Data 20
15. 1 TXO GND 4 3 RX0 POL 6 5 NC GND 8 7 TX1 GND 10 9 RX1 ADM XR IIPro User Manual Page 23 of 29 Version 0 2 ADM XP User Manual 10 User I O 10146 Front Panel Variant Rev2 0 There 146 signals available on the front panel connector and these be used individually or in pairs All of these pins are compatible with 2 5V and 3 3V signaling dependant on IO voltage setting on JP1 Care must be taken when using these signal pins not to exceed the maximum ratings for the V2PRO device Each pair of I O signals is routed as shown below FPGA User 0 User 1 User 2 User 3 The default manufacturing option is Rs OR and Rt not fitted Other options are available Rs can be used to provide series damping in point to point applications but for LVDS is OR Rt is required for LVDS inputs to provide the termination voltage from the line current 151 152 Pin numbering looking into front of XRM IO146 connector ADM XR IIPro User Manual Page 24 of 29 Version 0 2 ADM XP User Manual Pin Function UCF Term VII Pro Pin Function UCF Term VII Pro name Res Pin name Res Pin 1 Data 0 ve User 0 R1 E10 2 Data 1 ve User 2 R4 H13 3 Data 0 ve User 1 D10 4
16. 146 Rocket is based on the XRM IO146 module but has bank 4 on the mictor used to bring out the 7 MGT channels available on the ADM XP boards The termination scheme on the differential and single ended IO has also been changed from the standard 10146 allowing termination for LVPECL and BLVDS standards to be implemented on the XRM module rather than externally FPGA User CON User User User The default manufacturing option is Rs OR and Rt not fitted Other options are available Rs can be used to provide series damping in point to point applications but for LVDS is OR Rt is required for LVDS inputs to provide the termination voltage from the line current LVDS Select IO MGT Rocket IO 151 s2 y Pin numbering looking into front of XRM 10146 Rocket connector ADM XR IIPro User Manual Page 27 of 29 Version 0 2 ADM XP User Manual Pin Function UCF Term VII Pro Pin Function UCF Term VII Pro name Res Pin name Res Pin 1 Data 0 ve User 0 R1 E10 2 Data 1 ve User 2 R4 H13 3 Data 0 ve User 1 D10 4 Data 1 ve User 3 G13 5 Data 2 ve User 4 R3 E11 6 Data 3 ve User 6 R2 D13 7 Data 2 ve User 5 F11 8 Data 3 ve User 7
17. 5 2 5V 75 22 5 2 5 4P AN22 PN4 fpga P3 PN4 IO clocks 5 2 5V 55 22 PN4 fpga 3 If required XRM related clocks should be terminated on the XRM itself No terminations are provided the XP main board Page 11 of 29 ADM XR IIPro User Manual Version 0 2 ADM XP User Manual 5 3 SDRAM DDR Memory The XP provides 2 independent banks of 64MB of DDR SDRAM with the option of 128MB when devices become available Two Micron MT46V16M16 devices are fitted and are organised as 4Mx16x4 These devices can be operated at between 75MHz and 133MHz and depending on resource usage within the FPGA a 2VP70 can easily achieve 100MHz DDR200 operation Both banks are driven from Bank2 of the V2Pro DDR SDRAM DDR SDRAM Bank 0 Bank 2 VCCO 2 5V DDR DQO 0 15 SDRAM PQ9S0 0 1 DQMO 0 1 T DDRO AD BA CTL DDR1 AD BA CTL DDRO CLK DDR1 CLK DDRO CLKB DDR1 CLKB DDRO CLK FB DDR1 CLK FB DQSO 2 3 DQMO 2 3 2VP70 2VP100 FF1704 The pins required for the SDRAM controller for each bank are listed below Name Type DDR_ad 0 12 Output DDR dq 0 31 Bidir DDR dqs 0 3 Bidir DDR rasb Output DDR casb Output DDR web Output DDR ba 0 1 Output DDR Output DDR clkb Output DDR csb Output DDR cke Output DDR 0 1 Output DDR fb Input The DDR controller uses SSTL1 IOB s for data and control and SSTL1 for address and clocks Please refe
18. 5 MGT SYS TXN11 23 24 MGT SYS RXN11 A2 BB36 MGT SYS TXP22 25 26 MGT SYS RXP22 BB35 BB37 MGT SYS TXN22 27 28 MGT SYS RXN22 BB34 Page 17 of 29 ADM XR IIPro User Manual Version 0 2 ADM XP User Manual 7 UserlO PMC PN4 rear panel User is presented on the User Connector Pn4 via a standard 64 way PMC connector This should be routed via a suitable compliant motherboard to an external adapter FPGAPin Signal Signal 24 REARIO 7 24 REARIO 13 13 14 REARIO 12 4 REARIO 5 15 716 REARIO 14 26 REARIO 17 17 18 REARIO 16 AV25 5 AN25 21 5 AU26 REARIO 23 AR26 REARIO 25 AP26 AM26 REARIO 27 6 AR27 REARIO 31 31 32 REARIO 30 AT27 AV28 REARIO 39 39 40 REARIO 38 AU28 Aw30 REARIO 41 441 42 REARIO 40 43 44 2 00 AT30 REARIO 45 45 46 REARIO 44 AR30 47 48 6 AN30 w AM30 REARIO 49 49 50 REARIO 48 AL30 AT34 REARIO 51 51 52 REARODO AUS AR31_ REARI S 53 54 REARIO 52 REARODS 55 56 REARIO 54 AM31 AY33 57 57 58 REARIO 56 2 59 460 REARIO 58 02 6 462 60 53 650 4644 REARIQ 2 AP33 32 REARIO 59 AV33 REARIO 61 AR33 REARIO 63 ADM XR IIPro User Manual Page 1
19. 8 of 29 Version 0 2 8 JTAG Access ADM XP User Manual The XP provides JTAG access for the fabric of the board through J6 This header will connect to Xilinx download cables using 3V3 signalling levels and has the following devices present in the scan chain hdr TDI Bridge The standard XP is configured with the JTAG chain as shown in the table below hdr TMS 2V1500 TDI gt 2V1500 2VP70 100 gt TDO 8 1 JTAG Header J6 The table below shows the pin out for J5 the primary JTAG connector 2 5 Function 3V3 GND nc TCK nc TDO TDI POL ooo On amp do Po TMS Page 19 of 29 ADM XR IIPro User Manual Version 0 2 ADM XP User Manual 9 XRM ETH 9 1 Introduction The XRM ETH is a general purpose adaptor for the ADM XPL and ADM XRC II series of PMC modules It provides 10 100 Ethernet RS 232 and general purpose for use with a wide variety of IP The XRM ETH is supplied with two cables to enable connections from the XRM ETH to 15 way PC COM ports and RJ45 Ethernet XRM ETH CABO1 for Ethernet XRM ETH CABO2 for RS232 IMPORTANT The XRM ETH REV 1 requires the use of 2 5V signalling over the XRM connector and this should be checked prior to power up Mictor 38 RS232 2x5 hdr o O 2 Magnetics Info
20. ADM XRC II Pro ADM XP Hardware Manual DATA ADM XR IIPro User Manual Page 1 of 29 Version 0 2 Page 2 of 29 Alpha Data Alpha Data 4 West Silvermills Lane 226 Airport Parkway Edinburgh EH3 5BD Suite 470 UK San Jose CA 95110 USA Phone 44 0 131 558 2600 44 0 131 558 2700 Email support alphadata co uk Phone 408 467 5076 Fax 408 436 5524 Email support alpha data com Copyright 2002 2003 2004 Alpha Data Parallel Systems Ltd All rights reserved This publication is protected by Copyright Law with all rights reserved No part of this publication may be reproduced in any shape or form without prior written consent from Alpha Data Parallel Systems Limited ADM XR IIPro User Manual Version 0 2 Revision History Revision Date Comments 0 1 Jul 04 Initial 0 1 DATA1 DATA8 DATA13 and DATA15 polarity swapped DATA38 pin nos swapped in Manual Clock pins updated for XP pinouts were XPL pinouts 0 2 Nov 04 Removed XRM Pro Debug Section added XRM ETH ADM XR IIPro User Manual Page 3 of 29 Version 0 2 ADM XP User Manual Contents 1 INTRODUCTION MEE 5 1 1 SPECIFICATIONS 5 2 INSTALLATION Pe acra 6 24 MOTHERBOARD 2 858 99 serere sr ss sd sen 6 22 HANDLING INSTRUCTIONS
21. LK1 1 F19 95 37 SINGLE 37 1 E19 93 38 SINGLE 38 9 5 2 DCI Terminations These pins should be prohibited for place and route These pins have no other purpose on the XRM ETH FPGA XRM ETH Bank Pin Samtec Value Signal 0 G27 103 100 VRN_O 0 H27 101 100 0 1 G9 17 100 VRN 1 1 H9 19 100 VRP 1 ADM XR IIPro User Manual Page 22 of 29 Version 0 2 ADM XP User Manual 9 5 3 Ethernet MAC All of these signals use VCCFPIO signalling levels The VCCO selected by the jumper on the XRC II XPL should match the IOSTANDARD for these pins FPGA XRM ETH Bank Pin Samtec MAC Signal Comment 1 H20 62 RXC O ST 1 G20 64 TXC O ST 1 F15 66 PD 1 15 68 1 19 90 RXDV O PD 0 G22 97 RXD3 O PD 0 F22 99 RXD2 O PD 1 D19 92 RXD1 O PD 0 E28 94 RXDO O PD 0 F28 96 TXEN 0 29 98 TXDO 0 28 100 TXD1 0 22 102 TXD2 0 K22 104 TXD3 0 27 106 COL O PD 0 K27 107 CRS O PD 1 E13 18 MDC 1 13 20 MDIO 1 K13 26 RST N 1 913 28 RXER O Key Input O Output O PD Output with 2K pulldown O ST Output with 25R source resistor 9 5 4 RS232 FPGA XRM ETH Bank Pin Samtec J4 Header Signal 0 C30 122 1 TXO 0 D30 124 3 RXO 0 M26 126 7 TX1 0 M25 128 9 RX1 The header pin out is show below Signal Pin Samtec Signal GND 2
22. O 8N 0 157 158 IO 67N 0 K23 D33 IO 8P 0 159 160 67P 0 L23 C24 IO 65P 0 161 162 IO 30N 0 G30 D24 IO 65N 0 163 164 0 H30 E30 IO 0 165 166 IO 55N 0 G25 F30 IO 34P 0 167 168 55P 0 25 K31 IO 21N 0 169 170 IO 26N 0 G31 L31 IO 21P 0 171 172 IO 26P 0 F31 F26 IO 49N 0 173 174 IO 28N 0 L30 G26 IO 49P 0 175 176 IO 28 0 M30 E32 IO 19N O 177 178 IO 68N 0 J23 F32 IO 19P 0 179 180 lO 68P 0 H23 ADM XR IIPro User Manual Page 16 of 29 Version 0 2 6 2 RocketlO Multi Gigabit Transceivers U13 The ADM XP provides an additional connection upto the XRM module site which provides 7 connection from the Virtex pro device This enables customisable Mulit Gigabit capability using XRM modules interfacing to the additional samtec QSE DP connector Details of the connections to for the XRM MGT signalling is given below ADM XP User Manual FPGA Signal Connector Pins Signal FPGA Pin Pin A40 MGT SYS TXP2 1 2 MGT SYS RXP2 A39 A41 MGT SYS TXN2 3 4 MGT SYS RXN2 A38 A36 MGT SYS TXP3 5 6 MGT SYS RXP3 A35 A37 MGT SYS TXN3 7 8 MGT SYS RXN3 A34 BB4 MGT_SYS_TXP14 9 10 MGT_SYS_RXP14 BB3 BB5 MGT SYS TXN14 11 12 MGT SYS RXN14 BB2 BB8 MGT SYS TXP15 13 14 MGT SYS RXP15 BB7 BB9 MGT SYS TXN15 15 16 MGT SYS RXN15 BB6 A8 MGT SYS TXP10 17 18 MGT SYS RXP10 7 9 5 5 10 19 20 SYS RXN10 A6 A4 MGT SYS TXP11 21 22 MGT SYS RXP11 A3 A
23. P 1 M18 K21 IO 74P 1 89 90 65N 1 C19 J21 IO 74N 1 91 92 IO 65P 1 D19 E19 IO 64P 1 93 94 37N 0 28 19 64 1 95 96 IO 37P 0 F28 G22 75P 0 97 98 38N 0 29 22 75 0 99 100 IO 38P 0 C28 H27 IO 44N 0 101 102 0 J22 G27 44 0 103 104 74 0 K22 J27 IO 43N 0 105 106 IO 39N 0 L27 K27 43 0 107 108 0 27 29 85 0 109 110 67N 1 L20 E29 IO 85P 0 111 112 67P 1 K20 K29 IO 78N 0 113 114 IO 78N 1 L14 L29 IO 78P 0 115 116 IO 78P 1 K14 BB40 MGT SYS TXP23 117 118 MGT SYS RXP23 BB39 BB41 MGT SYS TXN23 119 120 MGT SYS RXN23 BB38 Additional MGT channel provided using these pins FPGA Signal Connector Pins Signal FPGA Pin Pin K26 IO 47P 0 121 122 35P 0 C30 L26 IO 47N 0 123 124 IO 35N 0 D30 L24 58N 0 125 126 46 0 26 24 IO 58P 0 127 128 IO 46N 0 M25 E25 IO 56P 0 129 130 IO 48P 0 J26 E26 IO 56N 0 131 132 IO 48N 0 H26 H31 IO 25N 0 133 134 59N 0 J24 J31 25P 0 135 136 59 0 24 G33 IO 7P 0 137 138 IO 73N 0 C23 F33 IO 7N 0 139 140 73P 0 D23 E34 IO 2P 0 141 142 IO 60N 0 G24 F34 IO 2N 0 143 144 60P 0 H24 H33 IO 6N 0 145 146 IO 29P 0 K30 J33 IO 6P 0 147 148 IO 29N 0 J30 C32 IO 20P 0 149 150 IO 54N 0 K25 C33 IO 20N 0 151 152 IO 54P 0 L25 H34 IO 1P 0 153 154 IO 64N 0 E24 G34 IO 1N 0 155 156 64 0 F24 E33 I
24. and both of these rails are used with the card The 5V rail is used to provide FPGA VIO supplies of 2 5V 0 8A max and 1 8V at 6A max each The 3V3 rails is used to provide the FPGA VCC core of 1 5V 9A max These are maximum values for the individual supply circuits but consideration must be taken to the power envelope that the PMC card is being deployed ADM XR IIPro User Manual Page 14 of 29 Version 0 2 ADM XP User Manual 6 Front Panel I O The XP supports standard XRM s used on the ADM XRC II and ADM XPL cards and also has an additional connector that brings 7 MGT channels upto the XRM Module site using a differential 28 pin Samtec QSE DP series connector to maintain signal integrity The XP supports the standard Samtec 180 pin connector but using either with 2 5V or 3 3V signalling which is globally selected using JP1 JP1 Link Posn VCCIO Front IO 1 2 3V3 2 3 2V5 6 1 Samtec 180 connector U8 The table below details the I O signals that are available on the Samtec 180 connector along with the FPGA pin that each connects to FPGA Signal Connector Pins Signal FPGA Pin Pin D10 IO 8N 1 1 2 IO 35N 1 C13 E10 IO 8P 1 3 4 IO 35P 1 D13 F11 IO 19N 1 5 6 IO 30P 1 H13 E11 IO 19P 1 7 8 IO 30N 1 G13 J10 IO 6N 1 9 10 IO 58N 1 M19 H10 IO 6P 1 11 12 IO 58P 1 L19 G10 7N 1 13 14 IO 54N 1 L18 F10 lO 1 15 16 IO 54P 1 K18
25. anual Page 5 of 29 Version 0 2 ADM XP User Manual 2 Installation This chapter explains how to install the ADM XP onto a PMC motherboard 2 1 Motherboard requirements The XP is a 3 3V only PCI device and is not compatible with systems that use 5V signalling The XP must be installed in a PMC motherboard that supplies 3 3V power to the PMC connectors Ensure that the motherboard satisfies this requirement before powering it up 2 2 Handling instructions Observe precautions for preventing damage to components by electrostatic discharge Personnel handling the board should take SSD precautions Avoid flexing the board 2 3 Installing the ADM XP onto a PMC motherboard Note This operation should not be performed while the PMC motherboard is powered up The ADM XP must be secured to the PMC motherboard using M2 5 screws in the four holes provided The PMC bezel through which the connector protrudes should be flush with the front panel of the PMC motherboard 2 4 Installing the ADM XP if fitted to an ADC PMC The ADM XP can be supplied for use in standard PC systems fitted to an ADC PMC carrier board The ADC PMC can support up to two ADC PMC cards whilst maintaining host PC PCI compatibility If you are using a ADC PMC64 refer to the supplied documentation for information on jumper settings With the ADC PMC64 all that is required for installation is a 5V or 3V PCI slot that has enough space to accommodate the full length card I
26. d to perform downloading of bit streams as well as remote debug using tools such as GDB and ChipScope Pro The drawback of using JTAG is that a download cable must be connected to the board The XP provides a SelectMAP port between the bridge and the target device mapped to the PCI bus This enables very rapid download of configuration data controlled by driver and API code in the host The maximum speed that can be achieved is 33 Mbytes per second 5 2 Clocks There are a number of clock sources in the XP as shown in the diagram below Although the ICS307 is shown connected to the bridge which may appear differently from the block diagram in the previous section the purpose is to provide level translation between the 3 3V output of the clock generator and the 2 5V inputs of the 2VP70 2 5V signalling osc 125MHz Differential Bank1 Pair 0S 1P 4 M 3 3V signalling Bank Pair 2S 3P 2VP70 nk0 Pair 4S 5P iate CLKGEN LCLK 100 125 XRM Osc L i Virtex Banko Pair 6S 7P Interface 5307 MCLK Ro 2 1500 Control PCI Bridge PCI 33 66 MHz M The V2PRO has a dedicated clock for gigabit operation using the Epson 2121CA 125MHz device This is input on GCLK4S 5P in bank 5 and should be received in differential LVDS mode Because of the routing limitations ADM XR IIPro Us
27. er Manual Page 10 of 29 Version 0 2 ADM XP User Manual within the V2Pro device and the allocation of the MGT resources on the board the MGT s are currently limited to 2 5GBps operation using the REFCLK input to the transceivers The MCLK signal is input to the FPGA to provide a user clock of between 10 and 200 2 single ended The local bus uses LCLK to synchronize transfers between the bridge and the target and is derived from MCLK by a divide by 2 in the ICS307 Although the clocks are related phase is not guaranteed A summary of the clock pins is shown in the table below Bank vcco GCLK Pin Signal Description 0 JP1 select 7P K22 lO 74 0 0 JP1 select 65 J22 IO_74P_0 GCLK6S 0 JP1 select 5P F22 lO 75N 0 GCLK5P 0 JP1 select 4S G22 75P O GCLKA4S User clocks to from XRM 1 JP1 select 0S K21 lO 1 GCLKOS 1 JP1 select 1P J21 lO 74 1 GCLK1P 1 JP1 select 25 21 lO 75 1 GCLK2S 1 JP1 select 3P G21 lO 75N 1 GCLK3P 4 2 5V OP AT21 LCLK Local Bus Clock MCLK divided by 2 4 2 5V 1S 021 User programmable up to 200MHz Default is 66MHz 4 2 5 2 21 DDR2 Clock feedback DDR DRAM 1 4 2 5V 3S AN21 DDR1 Clock feedback DDR DRAM 0 2 2 5V AB12 DDR1 Used for clock forwarding of 2 2 5V AA12 DDR1_clkb DDR clock outputs 2 2 5V AA10 DDR2_clk 2 2 5V 9 DDR2 clkb 5 2 5V 6P AU22 MGT_clk Clock for the MGTs
28. for connection to MAC IP in the FPGA A management interface and reset is also provided LEDS are provided on the board and these indicate the following conditions when lit D1 Collision D2 Full Duplex D3 Speed is 100 D4 Activity An Ethernet MAC such as the PLB or OPB Ethernet version supplied with EDK6 1i is compatible with this interface 081 ADM XR IIPro User Manual Page 21 of 29 Version 0 2 ADM XP User Manual 9 5 Input and Output Assignments ADM XP 9 5 1 Mictor I O FPGA XRM ETH Bank Pin Samtec J2 Mictor Signal 1 E10 3 1 PAIR 1 P 1 D10 1 3 PAIR 1 N 1 D13 4 2 PAIR 2 P 1 C13 2 4 PAIR 2 N 1 E11 7 5 PAIR 3 P 1 F11 5 7 PAIR 3 N 1 H13 6 6 PAIR 4 P 1 G13 8 8 PAIR 4 N 1 H10 11 9 PAIR 5 P 1 J10 9 11 PAIR 5 N 1 L19 12 10 PAIR 6 P 1 M19 10 12 PAIR 6 N 1 F10 15 13 PAIR 7 P 1 G10 13 15 PAIR 7 N 1 K18 16 14 PAIR 8 P 1 L18 14 16 PAIR 8 N 1 C20 63 17 PAIR 9 P 1 D20 61 19 PAIR 9 N 1 F9 24 18 PAIR 10 P 1 E9 22 20 PAIR 10 N 1 L17 67 21 PAIR 11 P 1 K17 65 23 PAIR 11 N 1 C11 30 22 PAIR 12 P 1 C10 32 24 PAIR 12 N 1 J19 83 25 PAIR 13 P 1 K19 81 27 PAIR 13 N 1 G12 36 26 PAIR 14 P 1 F12 34 28 PAIR 14 N 1 G19 87 29 PAIR 15 P 1 H19 85 31 PAIR 15 N 1 M18 88 30 PAIR 16 P 1 M17 86 32 PAIR 16 N 1 K21 89 33 CLK2 1 J21 91 35 CLK3 1 F21 38 34 CLKO 1 G21 40 36 C
29. port gt lt 15w 9 2 General Purpose I O XRM ETH provides 18 pairs of differential capable I O plus two single ended signals on 38 pin Mictor connector This connector is compatible with a wide range of Mictor connectors and is well suited to cabling systems from Precision Interconnect The differential pairs are routed on the XRM ETH with 100 Ohm impedance and are not terminated to enable direct routing to the FPGA The user has the choice of using Virtex DCI or DT termination schemes to provide the correct termination for each signal pair For DCI termination the resistor pairs R1 R2 and R4 R5 should be set to the appropriate value for the desired termination value By default these resistors are all 100Ohm The DT scheme can only be used with some Virtex Il PRO devices and provides a fixed 100R termination for LVDS LDT I O standards without the power requirement of the DCI option 9 3 RS232 I O The XRM ETH provides two transmit and two receive RS232 signals that can be used for connection to other XPLs or PC COM ports The supplied cable connects and to a standard 15 pin connector suitable for use with a PC Baud rates up to 115K are supported ADM XR IIPro User Manual Page 20 of 29 Version 0 2 ADM XP User Manual 9 4 10 100 Ethernet The XRM ETH Ethernet capability is supported by a Kendin KS8721B 2 5V PHY This device is capable of auto sensing 10 or 100Mb networks and has a standard MII interface suitable
30. r to the UCF for locations of the DDR pins Please note that the FPGA requires the Vref pins to be connected for correct data reception on bank 3 when using SSTL standard Additionally bank 4 Vref pins connect to board Vref but are not required for user applications These pins should not be configured with pull up or pull down options otherwise the Vref level will be set incorrectly The XP is designed to support DDR interface cores supplied by Xilinx using 90 degree phase shifted clocks for DQS during write operations This requires DQS pins occupy IOB s that do not share a clock signal with DQ pins In the XP DQS 0 1 and DQS 2 3 occupy pairs of IOB s sharing a common clock Note A trace delay has been incorporated on the DQS lines of approx 1 5ns to allow the use of local clocking within the FPGA ADM XR IIPro User Manual Page 12 of 29 Version 0 2 5 4 DDR2 SSRAM ADM XP User Manual The XP supports four independent banks of CIO DDR2 SSRAM memory The devices fitted are Samsung 512K 36 71163684 16 parts or a functional equivalent As an upgrade option 1Mx36 K71323684 FC 16 devices can also be fitted DDR2 SSRAM Bank 0 Bank 6 VCCO 1 8V 2VP100 704 2VP70 FF1 Bank 7 VCCO 1 8V DDR2 SSRAM Bank 2 Add0 0 21 DDR2 SSRAM Bank 3 AddO 0 21 KclkO KclkbO Dq0 0 31 DDR2 SSRAM The pins required for each SSRAM controller bank are listed below
31. ser 55 C15 55 Data 24 ve User 56 R29 G18 56 Data 25 ve User 58 R28 L16 57 Data 24 ve User 57 H18 58 Data 25 ve User 59 M16 59 Data 26 ve User 60 R37 E17 60 Data 27 ve User 62 R30 J16 61 Data 26 ve User 61 E18 62 Data 27 ve User 63 K16 63 Data 28 ve User 64 R41 J19 64 Data 29 ve User 66 R38 H16 65 Data 28 ve User 65 K19 66 Data 29 ve User 67 G16 67 Data 30 ve User 68 R44 G19 68 Data 31 ve User 70 R42 M18 69 Data 30 ve User 69 H19 70 Data 31 ve User 71 M17 71 Data 49 ve User 37 Nia K30 72 Clock 1 ve User 72 R67 K21 73 Data 49 ve User 38 J30 74 Clock 1 ve User 73 J21 75 5V fused 76 Single12 User 39 N a E24 Pin Function UCF Term VII Pro Pin Function UCF Term VII Pro name Res Pin name Res Pin 77 Data 32 ve User 74 R48 G27 78 Data 33 ve User 76 R45 C28 79 Data 32 ve User 75 H27 80 Data 33 ve User 77 C29 81 Data 34 ve User 78 R50 K26 82 Data 35 ve User 80 R49 C30 83 Data 34 ve User 79 L26 84 Data 35 ve User 81 D30 85 Data 36 ve User 82 R52 M24 86 Data 37 ve User 84 R51 M26 87 Data 36 ve User 83 L24 88 Data 37 ve User 85 M25 89 Data 38 ve User 86 R54 E25 90 Data 39 ve User 88 R53 J26 91 Data 38 ve User 87 E26 92 Data 39 ve User 89 H26 93 Data 40 ve User 90 R56 J31 94 Data 41 ve User 92 R55 K24 95 Data 40 ve User 91 H31 96 Data 41 ve User 93 J24 97 Data 42 ve User 94 R58 G33 98 Data 43 ve User 96 R57 D23 99 Data
32. t should be noted that the ADC PMC uses a standard bridge to provide a secondary PCI bus for the ADM XP and that some older BIOS code does not set up these devices correctly Please ensure you have the latest version of BIOS appropriate for your machine ADM XR IIPro User Manual Page 6 of 29 Version 0 2 ADM XP User Manual 3 Hardware Overview The XP is based on the architecture of the ADM XRC II with changes to accommodate the enhanced resources and needs of the Virtex Il PRO device The XP follows the architecture of the ADM XRC series and decouples the target FPGA from the bridge device to allow the entire target to be available for user applications This ensures the user can be up and running with the minimum of effort and without the complexity of PCI design The bridge includes local bus control and monitoring together with flexible configuration options for the bridge and the target device The bridge is capable of 66MHz PCI or PCI X operation with 64 bit or 32 bit operation The local bus supports 64 bit at upto 80Mhz The target FPGA is Virtex II PRO device incorporating FPGA fabric multi gigabit transceivers and two PowerPC cores DDR SDRAM ZBT and flash memory connect to the target FPGA and are supported by Xilinx or third party IP IO functionality is provided using XRM modules connecting to the 180 pin SAMTEC QSE and 28 pin SAMTEC QSE DP connectors
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