NIK HEF
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1. 2 5V SS instanceNamel W Buffers 8 Supply tests CIkPo schematic s a old oldNo oldPo mN NM FastCl GpartName FastCINo Fas m lest TestNo 4 TestPo m Token TokenNo 8 lokenP okenPo E ErrorP H Error W ErrorC TokenChP _KesetAC TokenChN W IICK ErrPside 4M N Lk ErrNside E 5 MS BufEnable 8 us P m ILI TCKo Extern Power in H DI TMSo sweep 3 6V PK Extern Power W TDIo e TRSTBo TRSTB_ 1000 _ Supply Seen a IDO _POnReset No m Pa puppi T External load IDO P SuppCurrDet a Supply SuppMeas components meet spannin Regulator RefOut E E W Supp5huntke s ibd EH NT D ADC PIE 1 25V 25 k controleer de spanning bij Geni e iok SuppPower is gnd open en wanneer in deze is aangesloten SuppShuntRes Figure 9 testschema voor 1 2 2 De 1 251 referentiespanning RefOut Deze referentiespanning wordt gebruikt als common mode spanning voor de analoge HAL25 output op de hybrid Dit circuit wordt gevoed door de VDD 2 5V2. m cikn Buffers S CIkNo Supply tests M CP schematic s B oldN oldNo a oldP oldPo M FastCIN partNamel FastCINo W FastCIP FastCIPo m lest TestNo H N TestP TestPo Token TokenNo E TokenP m ErrorP a Error trrorC TokenChP m W _ResetAC TokenCh SelP_N m BH P E TMS ErcNside a IMS BufEnable E IMS P m m 1 52777 Extern Power 3V The xtern B IRSIB TRSTBo Seu 3V RSTB_ outputvoltage RSTB_P SUPE POnReset BIDO POnReset MN 100 SuppOut M 4 PP Y Ge External Output H SuppcurrDet Supply SuppMeas components Regulator Bett SE SuppShuntR s SR 22 UM 7 ADCIneg 3 m a SuppOn end gnd gnd e Oscln Powerin OscOut 10k sweep 0 2 7 0V 10n Sweep Power in on SuppPower and SuppOn TTT Figure 11 testschema voor 3 B Voor de controle of de regulator aan en uit kan worden gezet door de JTAG controller is he
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4. NATIONAL INSTITUTE FOR NUCLEAR AND HIGH ENERGY PHYSICS ETR XX ALCAPONED 1 control chip TECHNICAL DOCUMENT LHC ALICE Inner Tracker System Silicon Strip Detector EndCap modules 31 March 2003 Project no 43000 Ruud Kluit Jan David Schipper Vladimir Gromov Paul Timmer email r kluit nikhef nl jds nikhef nl logic pault nikhef nl supply vgromov nikhef nl LVDS Abstract This control chip is designed to control the detector front end electronics on the hybrids connected to the double sided Silicon Strip Detectors The electronics at both sides of the detector module operate at different bias potentials The main functions are power regulation and signal distribution buffering The chip itself is programmable via the IEEE 1149 1 JTAG Boundary Scan Test protocol The ALCAPONE has integrated features to be able to use AC coupled signal transfer in order to cross the bias potentials The chip is designed in a 0 25um CMOS process By using gate around layout techniques the chip is radiation tolerant NIKHEF DEPARTMENT OF P O box 41882 NL 1009 DB AMSTERDAM ELECTRONIC TECHNOLOGY 5 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 Contents Eege 2 EE 3 ur PRIUS IAM T 3 veces cen 4 2 on
5. 4 INTEST 0011 5 ENDCAPSTATUS 0100 6 POWERCONTROL 0101 7 DELAYCONTROL 0110 8 CHIPCOUNT 0111 9 POWERREFERENCE 1000 10 ADC 1001 11 ADCINPUT 1010 12 ERRORMASK 1011 13 1100 14 Bypass 1111 The Instructions go together with data registers although INTEST EXTEST SAMPLE PRELOAD share the one Boundary Scantest register The input and output cells which have a BST register can be found in page 15 ALCAPONE Pin descriptions BYPASS and RESET have a register of 0 zero length Reading the instruction register will result in status statusO 0 1 The status bits are defined as 0 In the ALCAPONE the Status bit is Power status and Status0 is the Error sum 2 6 2 IdCode This register holds a pRESET number this is 7000000001 and can only be read IDCODE 0010 IEEE JTAG 1 0 Bits 5 2 Version Number 3 0 0000 0001 Chip ID 3 0 0001 A RESET of the JTAG logic will set the IDCODE instruction in the instruction register Therefore after RESET or Power On the IDCODE can be read out and the JTAG chain can be determined ALCAPONE Version number 0001 2 6 3 Bypass The BYPASS Instruction is a mandatory JTAG instruction and has no real register The instruction puts the chip in a transparent mode for JTAG communication BYPASS 1111 IEEE JTAG 2 6 4 Extest This Instruction is used to test interconnections between chips It puts all output cells in active mode and the EXTEST register
6. Controle of deze spanning 1 25V 50mV is Voor verdere tests is VDD niet meer noodzakelijk 20of 28 gt ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 3 De Supplyregulator A De Supply regulator heeft twee opstart modes remote on off en auto start De remote on off wordt intern door de JTAG controller gestuurd In de auto start mode moet de SuppOn ingang hoog zijn In de praktijk worden dan de SuppPower de SuppShuntRes en de SuppOn doorverbonden Voor controle van het opstarten en de opstarttimer in de regulator is 2 5V voedingsspanning nodig op de SuppPower Na het aanbieden van 2 5V op de SuppOn zal de regulator opstarten Ongeveer 300uSec later zal 2 5 op de POnRESET staan Controle of deze tijd tussen de 250uSec en de 350uSec 2 5V e gnd GinstanceNamel Puffers CIkNo 8 Supply tests CIkPo a schematic s oldN oldNo E oldP oldPo 8 m FastCliN GpartName FastCINo m FastCIPo am lest TestNo E B TestP TestPo m TokenN TokenNo TokenPo m W ErrorP W ErrorN
7. E ErrorC n oscilloscoop P ResetAC TokenChN cp JIAG TCK ICK SelP s rrPsid B P d i wee meet tijd en signaal E ErrNside E TMS S MS BufEnable mW IMS P rra el DI E IDI MSo B TDIP TDlo Extern 3V IRT TRSTB TRSTBo check output u RSTB TDOo default value 22 ower_on or reset T Er Supply d range TO _POnReset wm e TDO SuppOut 5 gt External Output TDO_P SuppCurrDet 31 Supply SuppMeas components E Regulator SuppShuntR s Dow m E SuppPower ADC ADCIn lt 3 gt M 9 M SuppOn i dd Oscln m Power OscOut ao 2 5V Switch on Power in on SuppShuntRes SuppPower d and SuppOn to chech if supply gn will switch on Figure 10 testschema voor 3A C en D B Voor controle van de undervoltageprotector de SuppPower en de SuppOn met de voedings spanning verbinden Deze voedingsspanning in 0 2ms opregelen Controle of de regulator pas boven een aangeboden spanning van 2 1V 50mV opstart Controle of de regulator uitgaat als de aangeboden spanning lager is dan 2 1 V 50mV 21of 28 lt gt ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 vdd 2 5V gnd instanceNamel l
8. 1 2 QN BI EE ee 21 6 2 Test CALCU ALON e 24 222082 ee 24 E 24 AUC AP ONE T TOP OTO 23 ALCAPONEO bond diagram MT LCC Sd Rr 26 CAPONE LOOS Gna VOC TLCS cate EE 2 AON 26 A APO DA 28 List of figures Figure 1 ALCAPONEI schematic symbol Figure 2 LVDS receiver for AC coupling diagram Figure 3 Timing diagram of the token readout Figure 4 Token readout scheme Figure 5 External Power supply components Figure 6 ADC block diagram Figure 7 ALCAPONE pins 27 Figure 9 Adc input range 19 Figure 10 testschema voor I en 2 20 Figure 11 testschema voor C en D 21 Figure 12 testschema voor 3 22 Figure 13 testschema voor E en F en G 23 CONN ta A Changes ALCAPONE1 In the ALCAPONEL ADC is added eot td hum v alex bua dpa Mna a uad Eua 8 In the ALCAPONEI the Status 1 bit is Power status and Status 0 is the Error eum 9 Version number OOOI ERRE 9 In one Input is added LVDS 10 ALCAPONEO the DAC bits are inverted This is solved in sss 11 the ENDCAPSTATUS register has 4 additional 81 888 11 In two bits are added to the PO
9. CMOS selection for the JTAG inputs are defined differently in AL CAPONE This is because of the second chip in EndCap module the power supply circuit should switch on automatically but for JTAG the CMOS signals must be used and not the LVDS signals the JTAG LVDS CMOS input selection is made with the LVDS CMOS input SuppOn defines whether the supply circuit is always on after Power On or not This is only the case on the Interface Card This signals also defines that some of the LVDS receivers and drivers will be enabled or not See table below Signal name In Out SuppOn H SuppOn L TokenChP TokenchN Disabled Enabled ErrorP ErrorN Enabled Disabled e The LVDS CMOS input defines whether the LVDS or the CMOS I O s are used for the JTAG communication LVDS CMOS H means LVDS L means CMOS Signal name In Out LVDS CMOS LVDS CMOS L LVDS_CMOS adcO adc1 adc2 adc3 oscin oscout 55 vdd 55 72 is vdd ALCAPONEO pitch 125 um pad size 95x95 um chip size 2 4 mm 70169168167 vdd power gnd power pad supp power pad 60 44 737475176 vsupp dacbias bandref 1 25 ref 1 E GA N co 980812 Figure 7 pins 17of 28 5 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 4 Connections by functional positio
10. M lt Rep a gt tel d o puhopovif gt po 40 jndinpuexo Le 4 e uoo gyr ke lt M 2 vi 3 N SNOISIAZY Se bel 2 Z y ALICE ITS SSD EndCapModules Appendix 2 ALCAPONEO bond diagram in PLCC84 HoldP HoldN FastC IN P XN mt Z TokenNM TokenPF m ErrorNM ErrorP f TUUS ER T e e mr ErrorC ResetAC TCK R pen zx uu ND I TMS TMS P L TMS mr mm TDO M VIT p PF P P fe eee 5 h a a Ir A nw e e ZS amp i 0 mot E om n uem gt E o e 83 ou 260 28 TRST SuppShuntRes suppPower POnReset NIKHEF Amsterdam 8 7 2003 HoldNo HoldPo FastCINo FastClPo TestNo TestPo TokenNo TokenPo TokenChN TokenChP ErrNSide ErrPSide SelP_N BuffEn ICKo TMSo TDOo TDIo TRSTo VDD VSS RefOut 5uppMeas SuppOut SuppCurrDet ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 Appendix 3 ALCAPONEO Pad
11. TokenChN ng SelP_N ICK_ ErrPsid k m cl meet tijd en signaal de ErrNside Ke 1 5 IMS_ BufEnable i TD Wk 101 ik 7 DI TMSo E 1k 7 0 4 ue EI msr IRSIB TRSTBo 4k 7 B IRSTB_N TDOo B a 2 1 5 _ Supply controleer mo g DO _POnReset spanning n TDO SuppOut Supply Programmable Power in B Uu ppuut CH ogr ki External Output load 25V DO P SuppCurrDet Supply SuppMeas components Regulator RefOut W SuppShuntk s D DC EM ADCIn lt 3 gt e gnd SuppOn gnd Oscln OscOut 1x 10 gnd Figure 12 testschema voor E en F en 6 2 B Voor controle van de over current timer kan ook de vorige meting gebruikt worden Het is dan al leen noodzakelijk dat de maximale stroom overschreden wordt zolang de tijd van de start up ti mer verstreken is De tijd tussen het verschijnen van de POnRESET en het zelfstandig afschake len van de uitgangsspanning is de tijd die bepaald wordt door de overcurrent timer Deze 15 onge veer 30us Een andere manier om de overcurrent timer te testen is om na ongeveer 400uSec een loadcur rent af te nemen die hoger is dan de maximale stroom 500mA De regulator zal deze stroom on geveer 30us leveren dan uitschakelen Controleer of deze tijd tussen de 25u en de 35us li
12. all errors are enabled mask bits 1 ERRORMASK 1011 Control Read default ControlWrite 01 ParityErrorLatched 1 ParityErrorLatched Bit 5 _ErrPsideLatched 1 ErrPsideLatched Bit 6 _ErrNsideLatched 1 ErrNsideLatched In ALCAPONEZ all error status bits are active The mask bits are 1 when masked The bits are inverted with respect to the ALCAPONEO but it more obvious this way The default values are therefore 0 in 130 28 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 2 6 15 RESET By writing this instruction a JTAG Reset signal 15 generated when a following UpdateDR occurs This means that a write action of zero bits must be performed after the instruction 15 set This reset will reset all error latches and load the default values to all registers RESET 1100 Control Read Control Write No bits the JTAG chain remains closed when the RESET instruction is selected In alcaponeO the chain is interrupted after the selection of this instruction The internal TDI TDO connection is not there 2 7 ALCAPONE reset functions The chip has different reset input functions as well as a Reset output RESETAC input active low This 1s the PowerOn reset input of the ALCAPONE it will initialize the following o The JTAG controller is set to Run Test Idle o The registers are loaded with the default values
13. 15 45 WEE 14 227 ALCAPONE reset functions 5 5 5 5 0 14 3 _ALCAPONE Po mi op I 15 3 1 LVDS receivers amp drivers pins for AC coupling ecce eee eee ee eee eene eene eene 15 32 JTAG e H CENE TET T TM 15 3 3 Power stap PINS 15 3 4 OLS PIAS T EN 16 3 5 Test Pads internal pads chip area eee Leere eene eee eee eee eee tree e ettet eese eese essa asas 16 3 6 16 3 6 1 cee 16 3 6 2 17 4 Connections by functional position in ENndCAP cscserssscssccccccccccccccsssssssssssssssccssccccccccsssscssssssssssess 18 2of 28 5 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 2 ONO 19 ALCAPONE ee 20 6 1 upplv amp SIUM 20 IEEE De Shuni NN RET 20 6 1 1 2 De 1 25V reterentiespanning Eet WE nnen tio erra eene ratu uxori Renan ps e pn aedis 20 6
14. The ADC logic is reset and will start if the oscillator runs o input circuits that can be used with AC coupling are set to the correct initial state TRSTB JTAG reset input active low This signal will set the JTAG controller in the Test Logic Reset state No register values are changed only the controller goes to the defined state In it will reset the JTAGOn bit e Reset via the JTAG register This will reset all JTAG registers to the default values It goes without changing the JTAG control ler state This means that the communication is not interrupted e POnReset output active low POnReset output is only valid when the power supply circuit is used After power on the output is low active Once the output voltage has reached the minimum level 1 9V but 15 sta ble the signal becomes inactive high Now the value of the POWERREFERENCE register is con nected to the DAC and the output will go to the required voltage In the case of self powering SuppOn is 1 this reset output can be connected to ResetAC input to initialize the chip itself In the ADC logic is reset by ResetAC In ALCAPONEO ADC was reset by TRSTB so after the power was switched on the user had to assert a TRSTB to start the 140 28 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 3 ALCAPONE Pin descriptions Note that the maximum voltage on each input may not e
15. WERCONTROL register 99250888 12 bit is added in the DELAYCONTROL register 8888 12 In ALCAPONE I the ADC value is GOVE COL NER 13 In ALCAPONE the ADC input selection is correct 13 ALCAPONE all error status bits are active The mask bits are 1 when masked 13 ALCAPONE the JTAG chain remains closed when the RESET instruction is selected 14 In ALCAPONE the ADC logic is reset by _ 14 the JTAG LVDS CMOS input selection is made with the LVDS CMOS input 17 30 28 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 1 Introduction This ASIC Application Specific Integrated Circuit is designed to control e Joe g 98 Front end chips on detector hybrids of the ALICE Silicon Strip nap 5 iuis m Detector Inner Tracker and is called ALCAPONE Control And E Esos POwer NExus The front end chip is the HAL25 1 designed by e LEPSI IRES in Strasbourg p This chip requires JTAG control signals for adjustment of internal reg gt isters e g bias In addition timed signals for sample hold and the readout TokenChP a are required To REA mo a These si
16. atically switched on to the devices behind the chip two bits are added to the POWERCONTROL register When the power is on the JTAG TDOo TDIo connection can still be programmed via this register by the JTAGOn bit The control bit is 0 after power on and should be made 1 to reach JTAG devices behind the chip The bit is reset by TRSTB This can help to reduce the JTAG chain when some parts do not need to be programmed 2 6 9 DELAYCONTROL The delay for the token signals be switched on and off via this register Default 1s 0 off The result can be read back In case the delay is off the TokenOut signal is still 2 Clock cycles delayed Delay off gives the same result as delay and ReadoutTime 0 in CHIPCOUNT DELAYCONTROL Control Read default Control Write 0110 Bit 1 0 Bit 2 one bit is added in the DELAYCONTROL register It determines if the token is connected directly to the output or not no delay This must be selected in the chips in the EndCap that only buffer and distribute the control signals 12of 28 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 2 6 10 CHIPCOUNT In here the WaitTime and the ReadoutTime can be programmed The WaitTime specifies the number of chips which are readout before a token will be sent The ReadoutTime specifies the number of chips to be readout This setting is necessary for t
17. chip 0 25u CMOS technology User manual Design of ladder EndCap electronics for the ALICE ITS SSD Progress report on development of the Low Power LVDS Receiver 0 25u CMOS technology for the ALICE Silicon Strip Detector SSD V Gromov vgromov nikhef nl R Kluit ET NIKHEF Amsterdam 20 January 2003 m m NO KH 8 Appendix 240 28 250 28 7 K 3 y 7 ON 39v2 lt eX ed 29 H MIN re ppa AAT TA S UDIS JDPUNOG 3 E rr e um moe mme Ld ND a Tree 19X0 i 3
18. compatible inputs are also set to a defined state 18of 28 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 5 Bugs amp features RESET for the ADC 15 POnReset internal from power supply circuit This means that the power supply must be on and functional before the ADC can work This is not the preferred behavior and it is changed to the Reset AC put ADC range not correct Reference of Bandgap cell is in reality lower that in simulation By manually increasing the voltage at the test pad the range can be corrected The bias circuit 1s changed to create a better ADC reference 4 Figure 8 Adc input range As result of the previous point the POWERREFERENCE 15 also a bit out of range although the de fault programmed required output voltage of the regulator is ok 2 57V The bias circuit 1s changed The LVDS P and N outputs for the CLK Token FastClear Hold and Test are inverted con nected Output pad cells are mirrored to solve this On some chip s we see a bounce POnReset This makes the logic to automatically switch off the power circuit The bounce can be a result of the slow original signal from the supply circuit This is solved by adding a buffer with hysteresis to the circuit to generate the POnReset The power supply oscillates when connected to the ALCAPONE Vdd itself A large capacitance 18 found between the ALCAPONE Vdd and the bia
19. content is placed in the BST cells to the output drivers The situation of the input cells is sampled in to the EXTEST register and can be read out EXTEST 0000 IEEE JTAG Test out Tetot RW 9of 28 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 Bit 9 70 Bit 10 71 SelectSwitch out Bit 11 2 BufEnable out l 0 1 6 7 8 9 The EXTEXT register bit PonRESET is made read only this is because in some positions of the ALCAPONEO on the ECM POnRESET is connected o RESETAC An EXTEST write would cause an error in this situation 1 Bit 16 77 Error LVDS out l 1 LL ee Ja Jas 1 one Input is added LVDS CMOS This pin is the first pin in the list so it becomes Bit 2 All other Bits shift one position This 1s in the IN TEST EXTEST and SAMPLE PRELOAD register If it is 1 the LVDS JTAG inputs are used else the CMOS 2 6 5 INTEST With this instruction internal functions can be tested In the ALCAPONEO the direct connections between the input and output can be checked In addition the token delay can be checked By asserting a token followed by enough TCK clock cycles according to the programmed delay the TokenOut is latched internal The latched token can be read out via the INTEST instruction and asserting a FastClr signal via the same register can clear the latched token In this way the various delay setti
20. ction Once the signals are received they are directly connected to LVDS output drivers These drivers are modi fied drivers from the cmos6sf25PadLib from RAL CERN The drivers deliver 3 6mA through 100Q The modification is that a disable function is added where the outputs become high impedant when the circuit is disabled This is necessary for the Latch up protection method when the power for the hybrids 1s switched off no current should flow through the signal connections 2 1 3 CMOS AC input The CMOS input circuit is basically a standard cell from the cmos6sf25Pad library The difference is a positive feedback via a 50kQ resistor This is necessary to receive AC coupled signals In addition a RESET function 15 added to determine the initial state after the power 15 switched on Low active inputs are RESET to High Since these circuits do not dissipate power when they are not used there is no disable function 2 1 4 CMOS output The buffered CMOS outputs are slightly modified A disable function is added in such a way that the out puts have high impedance when the drivers are disabled This is for the Latch up protection Most outputs can drive 8mA and some have slew rate limited output stages Outputs that have to drive more inputs have a 20mA output drive capability 2 2 Readout and Token delays The readout control for the front end chip the HAL25 is done using 4 signals e The HOLD this signal activates the sampling of t
21. en 1 5V E gt JTAG test Controleer verbinding met JTAG Lees alle bits schrijf naar alles en controleer of dit goed gaat vol gens de beschrijving van alle registers Controleer of the reset functies werken zie 2 7 Controleer of m b v de Extest instructie de aangeboden signalen goed de chip bereiken En doe het zelfde met Extest of alles er goed uitkomt Doe m b v INTEST een controle van de Token controle logica E 6 5 Readout test Controleer de Token Out delays met alle mogelijke waarden Controleer hierbij ook SelectSwitch en en BufEnable volgens Readout and Token delays op pag 5 6 6 Test time calculation EndCaps IntCard SuppCard sub tot spare yield 144 1 7 50 Number of IC s ALABUF 7 0 1 1008 504 1008 ALCAPONE 31 3 4 4464 2232 4464 ALCAPONE s for LHC __500 50 250 500 prod Information eng Run Jprod Run nodig nr of ALABUF 2520 2500 1400 4344 nr of ALCAPONE 12410 13000 520 12480 Tijd inclusief wafer handling ALABUF test Test periode 4 weken Test duur 20 dagen van 8 uur 6 eff 120 uur Test tijd per chip 2 minuten en 39 seconden ALCAPONE test Test periode 8 weken Test duur 40 dagen van 8 uur 6 eff 240 uur Test tijd per chip 1 minuten en 6 seconden eng run run file size per ALABUF 700 957 2969 531 file size 200 104 2437 5 7 References 1 HAT 25 Hardened ALICE front end
22. es are readout sequentially the token is first sent to one side A delayed delay as long as one module readout token is sent to the other module side The delay can be programmed in See steps of 128 CLK cycles from 0 to 6 steps TokenCheck G maximum number of chips a hybrid Oncea TI hybrid is completely readout it returns the token Token 1 input BufferEnable 1 output Token 2 input Token 3 input Token 3 output P side TokenCheck This is checked by the ALCAPONE An internal delay is used to synchro TokenCheek nize the hybrid return token with the internal token Figure 3 Timing diagram of the token readout The token signal is sampled by the CLK at the rising edge and the token output is released when the CLK goes low If the returned token does not appear at the right moment in the ALCAPONE an error will be gen erated Errors are described later in chapter Error Handling page 8 The readout signals in the EndCap are visualized in Figure 3 and Figure 4 First the signals are received in the ALCAPONE 1 at GND level Then they are sent to each detector side and there again buffered gt Detectors by 2 Then the signals reach the ALCAPONE 3 voles D Alcapone that is connected to the hybrids with the HAL25 me O chips In the
23. es stable the output 15 switched on to Vout min and the POnRESET is held active by the start up circuit During this time the over current protection 1s disabled and capacitive load can be charged 3 The ALCAPONE is now switched on Power DAC 0 2V and after POnRESET 1 finished the de fault value for the power DAC 15 loaded and the output goes to about 2 5V 4 Now the regulator circuit 15 in normal operating mode and sensing the output current The power DAC value can be modified via the JTAG port In ALCAPONEZ every time a change is made to the DAC value the over current protection is disabled for about 30us This is done to prevent the power to be switched off due to an over current of charging load capacitors Specifications Value Tolerance Tof 28 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 2 4 Adc For monitoring purposed is an 8 bit successive approximation ADC Figure 6 implemented the chip input multiplexer has 4 inputs This is followed by a sample and hold circuit This is a switch and a 2pF capacitor with a buffer The voltage has the ALCAPONE input as ground reference The ADC logic is clocked from an oscillator that needs an external RC network 10k amp 10nF for 30kHz Instead Reset defined clock can be connected to the OscIn
24. etector module the token must be sent The delay is programmable via the JTAG bus The 10 CLK that must be distributed inside the ECM use LVDS signals The JTAG signals to the ECM are using LVDS levels but once received they are distributed with CMOS levels inside the ECM and to the front end modules Look in the ALCAPONE Pin descriptions to find which signals are only buffered Aof 28 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 2 1 1 Low Power LVDS AC input These LVDS receivers have been op t Nana DutCMOS timized to work with 1OMHz signals tested up to SOMHz and have low power consumption 550uA 3 The circuit is also provided with a disable control input In the situation where the receiver is not needed it will be dis LL abled to save power tt The receiver 15 supplied with a positive x feedback circuit level adapter in 1 Figure 2 and has a hysteresis of 25mV ed E Enable Figure 2 LVDS receiver for AC coupling diagram This feedback circuit delivers the DC levels of correct LVDS 0 9 amp 1 3V to the receiver input via a high impedance circuit to ensure that the receiver works well when the inputs are AC coupled with 47pF capacitors A reset signal ensures that the total circuit can be reset to the required initial state This 15 neces sary when AC coupled signals are used after power is switched on 2 1 2 LVDS driver with disable fun
25. for the power regulator circuit Specifications Value Tolerance VshuntRef 2 52V 6of 28 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 2 3 2 Power supply regulator The regulator is able to regulate the power for 1 to 15 ALCAPONE chips or for a HAL25 hybrid This corre sponds to 150mA and 1A The circuit is controlled via JTAG and an external signal SuppOn This signal determines if the regulator should switch on after the power 1s switched on or not In this always on mode the shunt regulator must power the power supply circuit Again a Bandgap reference circuit is used to generate a reference voltage for the regulator To adjust the output voltage an 8 bit DAC is imple mented to modify the reference for the output voltage Current Detect The regulator is switched off when the output current exceeds a limit This limit is determined by the value of the current sense resistor R14 in Figure 5 When the voltage over this resistor exceeds 19mV 0 1V the power is switched off It can be switched on again via JTAG or in case that SuppOn is high by switching off and on the external voltage a Output Figure 5 External Power supply components During the power up of the power supply of the ALCAPONE chip the following sequence occurs 1 Until the input power voltage reaches Vin min the start up circuit will keep the output off 2 After this Bandgap reference becom
26. g Pam 4 2 1 LVDS CMOS baren 4 244 IE Powar A P 5 2 1 2 LVDS driver with disable function aan eanaennensennennennssnsensenssensenveneens 5 2 1 3 CMOS TE E 5 2 1 4 CMOS OU se 5 2 2 and Token delays 5 2 3 FO a resula OT E 6 2 31 STEE 6 2252 Power Supply E 7 2 4 8 2 5 Error ET LE 8 I 8 2 6 1 ests 9 2 6 2 I Oa EEN 9 2 6 3 DASS 9 2 6 4 disi EE 9 2 6 5 in S 10 2 6 6 11 2 6 7 del 11 2 6 8 POWER COIR OM 12 2 6 9 Bi UNS PERENNE 12 2 6 10 E Ce ERC ee eee 13 2 6 11 EEN 13 2 6 12 PM E 13 2 6 13 13 2 6 14 ERROR MIA SI E 13 2 6
27. gnals must be distributed through the system End Cap Module m E See 2 and therefore locally buffered In addition local control and monitor 0 functions close to the front end are required This includes power regu n lator and ADC for monitoring Error checking and failure recovery fanc 4 tions are also required Eq ie Figure 1 ALCAPONEI schematic symbol 2 Functional description The ALCAPONE design contains a number of functional blocks e LVDS and CMOS buffers repeaters with AC coupled inputs e Front End readout token control e Power regulator with Latch up protection and shunt regulator for local power ADC for monitoring functions These blocks will be described separately The Logic and de ADC share the same Power input Vdd The shunt regulator for local power and the Power regulator have each a separate power input on the ALCAPONE system overview 15 described in Design of ladder EndCap electronics 2 21 LVDS and CMOS buffers repeaters A number of signals are just feed through the ALCAPONE chip These are Clk Hold FastClr and Test These signals are received via a Low Power LVDS receiver with positive feedback for AC coupling The Fast clear FastClr signal is also used internal to reset the front end readout control This clears the readout cycle during readout The Token output can be delayed from the input This depends to which side of the d
28. gt Receiver amp Buffer test Controleer de doorgaande buffers en drivers LVDS en CMOS en controleer de LVDS CMOS selectie van de JTAG inputs m b v de LVDS CMOS input pin In de chip wordt het POnRESET signaal van de regulator gebruikt als disable signaal voor een aantal LVDS buffers en CMOS buffers Zie 3 1 en 3 2 De betreffende LVDS buffers zijn Po en ClkNo HoldPo en HoldNo FastClPo en FastCINo TestPo en TestNo Po TokenNo De betreffende CMOS buffers zijn TCKo TMSo TDOo TRSTBo PonRESET Controle of deze buffers in hoog ohmige toestand zijn als de regulator uit staat en of deze buf fers actief zijn als de regulator aan staat zie Figure 12 23of 28 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R K luit 8 7 2003 6 3 ADC test A Oscilator test Resistor and 10nF cap to gnd gt 0 4V Vh 1 9V freq 3 1kHz clocked op Osc in 10 100kHz check ADC output met 0 5 en 1 5V ADC test Zet het ADC testmode bit JTAG AlcaponeStatusRegister en de DAC van de ADC zal nu continu aftellen check ramp met scope Deze spanning kan gemeten worden aan een input die m b v het ADC input register is geselecteerd Niet input 3 want daar zit een stroom output aan De inputs 0 1 en 2 controleren Met 100k aan input 3 de ADC uitlezen Meet ook 2 spanningen voor iedere input bv 0 5
29. he input amplifier value of the HAL25 sample and hold This signal only needs to be buffered It is not used inside the ALCAPONE e The CLK activates the logic for the readout It is only available during the readout cycle The ALCAPONE requires 4 CLK cycles before and 4 cycles after the ReturnToken The CLK signal is buffered by the ALCAPONE and used to generate the delayed token signal e This is followed by a Token this signal determines when a specific data sample is multiplexed to the output of the HAL25 chip The Token is sent first to one side of the detector module and de layed to the second side of the module The ALCAPONE generates the delay based on a fixed number of CLK cycles dependant of the number of HAL25 chips to be read out This number is programmable To clear an on going readout cycle FastClear signal must be activated low active This signal is used by the ALCAPONE to clear the internal token readout sequence Sof 28 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 The Test signal is used to simulate a hit in the analogue front end of the HAL25 The Hold signal must be delayed from Test according to the programmed shaper time of the HAL25 chip This signal only needs to be buffered It is not used inside the ALCAPONE The CLK HOLD and FastClear signals can be sent to both sides of a detector module hybrid at the same time However to make sure that the two sid
30. he return token from the hybrids to be checked Default values 6 CHIPCOUNT 0111 Control Read default Control Write 1 0 Bit 4 2 WaitTime 2 0 6 WaitTime 2 0 Bit 7 5 ReadoutTime 2 0 6 ReadoutTime 2 0 2 6 11 POWERREFERENCE The power supply circuit reference voltage can be set using this register Values from 0 to 255 can be used The analogue result is 1 031V to 1 384V This results in an output voltage of 2 07V to 2 78V Default is 149 2 52V output POWERREF Control Read default Control Write 1000 2 6 12 ADC Via this register the result of the 8 bit ADC can be read First one of the 4 inputs must be selected with the ADCINPUT register In ALCAPONEO the bits are swapped 0 7 7 0 and inverted In ALCAPONE the ADC value is correct ADC 1001 Control Read default Control Write 1 0 2 6 13 ADCINPUT This register determines which of the 4 inputs is selected for the ADC Default is 0 Input 3 has a current source of 9 96uA connected for NTC measurements In ALCAPONEO if one selects an input the result is that just that bit is NOT selected but the other three are connected together and connected to the ADC In ALCAPONEZ the ADC input selection is correct ADCINPUT 1010 Control Read default Control Write 2 6 14 ERRORMASK A P in the mask means that a received error will be ed with the others to the ERROR output while a 0 will block the particular error By default
31. logue detector channel can be monitored ALCAPONEO the DAC bits are inverted This is solved in ALCAPONEI 01 Bit 18 11 DAC 7 0 DOSE 2 In the ENDCAPSTATUS register has 4 additional bits ENDCAPSTATUS Control Read default Control Write 0100 Bit 6 SuppOn ext Bit 7 ALCAPONEI LVDS CMOS ext Bit 8 llof 28 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 gt Bit 12 TokenEmorMask O X Bit 13 HALTesMod O X DAC 7 0 951 Bit 22 ALCAPONE TestModeADC 0 X 26 23 Adc Input 3 0 0 X Bitf29 27 1 0 46 X ReadoutTime 2 0 6 _ErrPside 0 P Mask 1 _ErrNside 0 Bit 41 This bit is hardwired so the initial value is determined by the external connection 2 6 8 POWERCONTROL The power regulator can be controlled via this register By default Power is Off Reset 16 0 POWERCONTROL Control Read default Control Write 0101 Once the power is on and ok the PowerStatus bit will be 1 If as result of over current the power is switched off PowerStatusLatch bit will be set This means that the error is latched Writing a 1 to the ResetPowerStatusLatch bit will reset it Only the according bit will be reset If the Power is switched off the JTAG TDOo TDIo connection is made inside the ALCAPONE to bypass the un powered hybrid When the power is on the JTAG chain is autom
32. male stroom is niet afhankelijk van de ingestelde uitgangsspanning Controle van die 330mA 30mA Tijdens deze meting kan de load regulation worden gemeten door de uitgansspanning te meten als functie van de uitgansstroom Controleer of de uitgangsspanning niet meer dan 5mV zakt Controleer of het AC component niet meer dan 1 bedraagt 220 28 5 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 2 6 2 gt E 8 7 2003 vaa 2 5V gnd Supply tests schematic s instanceName Buffers Clk 8 100 check high WB m N 1k impedance oldN oldNo 100E output state oldP oldPo N 1k partNamel FastCINo 100E g FostCIPo 8 inar _ TestN estNo NS TokenN TokenNo m8 x 05 TokenP measure current ed Ls _ shouid be 0 W ErrorP ErrorN gnd W ErrorC TokenChP 13 oscilloscoop ResetAC
33. n EndCap ALCAPONE chip is used 3 different functional positions the EndCap 1 Interface on GND level buffer between EndCap and data acquisition and control 2 AC coupling to P or N side coupling from GND level to detector bias level to 14 hybrid controllers 3 Buffer to detector hybrid the actual controller and buffer for one of the 14 hybrids Depending on the position the following chip connections are made 1 SuppOn to Vdd This defines that the regulator is always on and cannot be controlled via JTAG It 1 used to power the chip itself and the 7 ALABUF chips inside the EndCap 2 5V LVDS JTAG signals use LVDS I O s on GND level CMOS inputs left open The chip is powered by it self from the control power at GND level 2 SuppOn to Vdd The regulator is used to power itself and the ALCAPONE chips on the Supply Cards LVDS CMOS L JTAG signals use CMOS I O s on detector bias level AC coupling LVDS in puts are not enabled The chip is powered by itself from P or N side control power at detector bias level 3 SuppOn not connected L gnd The supply circuit must be controlled JTAG LVDS CMOSL JTAG signals use CMOS I O s on detector bias level but direct connected to previously mentioned ALCAPONE The LVDS inputs are switched off The chip is powered by the ALCAPONE in 2 In all cases ResetAC 15 used to reset the AC coupled inputs not connected AC
34. ngs can be tested via JTAG In addition the activation of BufEnable and SelectSwitch can be checked this way INTEST 0011 IEEE JTAG Bit 5 6 Test out Bit 6 7 Bit 8 9 Bit 9 10 15 6 7 8 ale Bit 19 20 Bit 21 22 No INTEST function can be performed with ResetAC pin This would cause an error E z z 16 EIS 100 28 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 2 6 6 SAMPLE PRELOAD This register 1s used to sample the present input or output state of the I O cells to which the BST registers are connected The PRELOAD is used to set the registers before an INTEST instruction Therefore the con tent of this register 15 the same as the INTEST register 2 6 7 ENDCAPSTATUS The actual chip status can be checked ENDCAPSTATUS Control Read default Control Write 0100 Bito 01 ResetLatches Bit 3 HALTestMode Bit 4 Bit 5 h N Mask 1 This bit is hardwired so the initial value is determined by the external connection By writing a 1 to the ResetLatches bit all the Latched error bits will be RESET This occurs at the time of writing so the bit does not need to be reset The PowerStatus bits are the same as in the POWERCONTROL register The HALTestMode bit enables the user to read the analog output of the front end Transparent mode It will activate BufEnable and SelectSwitch In this way one ana
35. op DIEN 54 431 4 f doi ENT 1 31020224 V Jb o 3 F 24 Po 7 5229 x CU T dv5 0 A NS SATNI f ue 60 1 S m LB B 12525409 a gt k We Nuguexo SOM z Sonano Eu 5 I SEH _ DR 2404901 991 SHS SONT d Sg ujuexo T S bobsluopunegovin i 1269041 z 19 1 B gt M eu A zs ma e DOW E SW a 1 2 1 d SAL d d ADAC OVI z SDS OV 101 9 xa 1 MOL IECH 2 e gt Sun OVID 1X4 sdiuo Luise LLE SfUINTND m m a BR Mh E 3 5 SET MIL 1 u 4 Hb E f sgeiopdn o EN lag i SZT CU H M ise 5409190970 tum SH uopsAuopunog5vif 158 U e BAR RR ur e Ce 909419597 0 Bot gt pu a 309111989 1 241708 v TAG Gei lt in SEP _ BEBE 18319151 Mm m m RR 5 aon Ki Ep SC 4 vy 3521 LI 15913 n gt 7 9 ops n gt gt dino 5 ARIAS Sn AND HE 9NI21524 a S SE S MO TT o u LI e 2 A OT SH 4121504 AND e x SPUIALNO 27 sU 10 ur SJO OM J KO A EE Am
36. or input from the Pside also for AC ErrNSide CMOS Error input from the Pside also for AC SelectSwitch Y Out CMOS Select signal for analogue multiplexer H Select Oey NOS sd TokenChP amp To Y In LVDS Token check input for end of readout He PS nere Error signal out EndCap internal error flag L error wired OR function 20mA open drain Input is connected to 9 96A current source Add RC load R 10k C InF for 30kHz 3 5 Test Pads internal pads in chip area Signal Dir Value Description 3 6 Specials 3 6 1 0 SuppOn defines whether the supply circuit is always on after Power On or not This is only the case on the Interface Card This signal also defines that some of the LVDS receivers and drivers will be enabled or not See table below Signal name In Out SuppOn 1 SuppOn 0 Enabled Disabled TDI P TDI Enabled Disabled TMS P TMS In Enabled Disabled TDO P TDO N Enabled Disabled TokenChP TokenchN In Disabled Enabled ErrorP ErrorN Enabled Disabled n In TRST P TRST N Enabled Disabled In 16of 28 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 ResetAC is used to set the AC coupled inputs into a defined state This signal also is used as Power On Reset for the control logic inside the ALCAPONE With this signal all registers can be initialized 3 6 2 ALCAPONEI The signals SuppOn and the LVDS
37. osc Clock A re Input The conversion time is clock period multiplied _ A by 20 From this clock two non overlapping sig S nals generated to operate the switches mp 2 Tu SAR stout The SAR logic determines the correct DAC value logic that corresponds with the input voltage Hold signal is to prevent the result register to be mud A Vref read and written at the same time the read action is blocked Figure 6 ADC block diagram Specifications Value Tolerance 9 96 A Input 3 is provided with current source output of 10uA This can be to connect a NTC of 100k to monitor the temperature In the ALCAPONE ADC TestMode is added In TestMode the DAC value is counting from 255 to 0 continuously and the resulting voltage can be veri fied at one of the selected analog inputs not 3 In normal operation the ADC continuously digitizes the selected input and the result can be read out via JTAG The analogue range is from 0 to 2 Volts 0 255 2 5 Error Handling Some error situations can be monitored and flagged e Supply switched off due to over current PowerStatusLatch is 1 if the error has occurred PowerStatus 15 1 if the error is still there e Return token from hybrid is not received TokenError is 1 if a token did not return at the expected moment e Parity of all control registers is changed bit flip due to
38. put signal TDI also for AC TRST In CMOS Internal EndCap input signal TRST also for AC D TCKo TMSo TDlo MOS TRSTBo ut MOS Buffered internal EndCap signal TRSTB active low 8mA TDOo CMOS Internal EndCap signal TDO 8mA 2 The LVDS receivers are the only Low Power versions the ALCAPONEO In ALCAPONE all LVDS receivers are the Low Power versions n n n n n n n n 52 Qo 3 3 Power supply pins Signal BST Dir Type Description ShuntRes In Connection for 180 2 resistor for shunt regulator power SuppV dd Out Power Connection of Vdd out for Power Supply Circuit 2 5V 200mV Max CMOS Input to determine if power supply must be on after Pow erOn H on internal pull down SuppOn ShutRes wen E 15of 28 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 _ CMOS PowerOn RESET out Active Low during power on 250us 8mA Drive of power transistor for power supply max 140A Current detection input of power supply circuit Measure Voltage input for power supply circuit analogue output max 100uA wmm DAC and reference circuits 3 SuppVdd powers the BST cells for these pins 3 4 Miscellaneous pins Signal BST Type Description Resets the AC coupled input circuits and is the PowerOn reset input for the logic L Reset 20mA SRL ErrPSide CMOS Err
39. radiation All bits in POWERCONTROL DELAYCONTROL CHIPCOUNT POWERREF and ERRORMASK are used the parity check If a bit flips during normal operation e g due to radiation it is de tected External error from detector P or side received If one of both inputs recognizes an error the ErrP Nside bit is 1 The ErrN P side bit represents that an error has been detected If one of these errors is recognized it will be flagged The flag must be RESET manually via the status reg ister with bit ResetControl flags are now cleared 2 6 logic Via this logic all ALCAPONE functions can be controlled The logic consists of a TAP state machine with the mandatory IEEE 1049 JTAG registers and functions Extra registers have been added for control func tions of the chip If IEEE JTAG is mentioned in the table header the instruction behaves according to the IEEE 1049 1 standard The JTAG communication can occur via CMOS or LVDS signals LVDS signals are used if the ALCAPONE receives the signals over a long distance and the CMOS signals inside the ALICE EndCap mod ule and to the hybrid Via the LVDS CMOS input the selection is made see chapter Specials 3 6 Sof 28 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 2 6 1 Instruction register The JTAG instruction register has four bits that are decoded to the following instructions 1 Extest 0000 2 SAMPLE PRELOAD 0001 3 IdCode 0010
40. rough switch controlled via JTAG will be added The errorLatched flags do not work This 1s caused by the design software which did not recog nize wrong connections in the layout of the chip Now this is known we can manually find these errors and correct them With the latest software version the errors are detected When the RESET instruction was selected the JTAG chain was interrupted Since there is no data register for this instruction it was not multiplexed internal Solved in ALCAPONEI 2 53 V 2 54 V AY LA I max R 76mOhm 250 mA 19of 28 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 6 ALCAPONE Test description Always start with ResetAC This is the power on reset for the AC coupled input circuits the ADC and the logic in the chip 6 1 Supply amp Shunt test 1 De Shuntregulator Controleer of de spanning op de aansluiting SuppShuntRes 2 5V 25mV is Als deze met een serie weerstand van 180 Ohm gesloten op een oplopende voedingsspanning van 3 tot 6 V Deze voedingsspan ning wordt in bedrijf ook gebruikt om de vermogenstransistor die door de supplyregulator wordt aange stuurd te voeden Deze voedingsspanning staat dan op 3V
41. s and probe numbers pins 72 was vdd probecard pin nr testpad not probe pad origin corner pitch 125 um pad size 95x95 um chip size 2 4 mm 70169168167 vdd power gnd power pad supp power pad AR oy Ol KOl KOl Kal On 1 1 C1 0210 BI Ol 92 AN Oo OJ OC INE OD N Co CO gt 1 25v_ref bandref dacbias vsupp NININININININI a a a a a sch ORION ojcdcojoo 4 o o1 gt N C65 RO 0240212 N CO cO 29 80 81 32 corners symetric B58 A58 edge sensor 27of 28 ALICE ITS SSD EndCapModules NIKHEF Amsterdam R Kluit 8 7 2003 Appendix 4 ALCAPONEO layout Appendix 5 ALCAPONEI layout 28of 28
42. s for the power supply reference bias This is 1m proved by adding a separate bias circuit for the ALCAPONE and the supply circuit The OR function in the LVDS AC CMOS inputs JTAG can block the correct input signal Now a multiplexer is implemented and when in SuppOn mode the LVDS inputs are selected and oth erwise the AC CMOS inputs are selected The AC CMOS input did not work reliable By adding an external resistor of 20Q to 1kQ the cir cuit behaves correct it creates hysteresis Now a 4000 resistor is integrated in the chip The SuppOn signal must be high on the Interface card ALCAPONE chips The first one receives the JTAG signals via LVDS However the other two via CMOS signals using AC coupling In the latter case SuppOn 1s high but the CMOS JTAG inputs must be used instead of the LVDS inputs This requires an additional mode for the input selection Solved with extra LVDS CMOS input The Token signal must be synchronous with the falling edge of the ALCAPONE CLK signal Now it is with the rising edge and the signal is not sampled rising edge with the succeeding ALCAPONE chip The FastClr input signal is active low assumed was active high The input cell has changed and the output pins are switched The internal FastClri signal is active high This is the value read by the BST registers In case delay is off TokenOut must be TokenIn without any delay The delay was 1 clock cycle and this must be solved A token feed th
43. se chips the delay must be generated such that each detector side of a module is readout soiis sequentially This chip also controls the analogue dm PEN multiplexer in the ALABUF chip SelectSwitch LT The corresponding analogue channel is activated pum during readout aM our e ILI The first ALCAPONE in the ECM will switch on the o TO analogue buffer chip as soon as the token is re ceived The signal BufEnable is active during the 2 programmed CHIPCOUNT the ReadoutTime time values Alcapone 1 Alcapone Figure 4 Token readout scheme The FastClear signal will RESET the delays but nothing else A readout cycle can be aborted and after re lease of the signal the chip is ready to start a new readout cycle 23 Power regulator A Power supply regulator in the chip is necessary to create latch up protection for the electronics succeed ing the ALCAPONE chips This power block consists of two parts the shunt regulator and the power sup ply regulator 2 5 1 Shunt regulator This circuit is used to generate the correct supply voltage for the power regulator circuit It consists of a Bandgap reference with buffer and a shunt regulator circuit This whole circuit can be supplied from a 3 to 6Volt power supply via a 180Q resistor and it delivers always 2 5V
44. t nodig dat SuppOn niet met SuppPower is doorverbonden Als SuppPower laag interne pull down is 15 de regulator in de remote on off mode Controleer of de regulator met behulp van de JTAG controller aan en uit te zetten is Dit kan pas de JTAG logica een RESET van de regulator heeft gekregen Deze RESET 15 POnRESET is dan doorverbonden RESETAC Voor controle van het bereik van de uitgangsspanning van de regulator 15 het nodig dat m b v de DAC voor de regulator wordt ingesteld De voorinstelling is zodanig dat de uitgangs spanning bij opstarten 2 5V bedraagt Dit kan pas nadat de JTAG inputs een RESET van de regu lator heeft gekregen Deze RESET is POnRESET aan RESETAC Controleer of de uitgangsspanning is in te stellen tussen 2V 25mV en 2 8V 25mV en alle DAC stappen 1 bit 1 5 mV Voor controle van de maximale stroom kan de vorige meting gebruikt worden Met een oplopende loadcurrent de regulator op een bepaald moment de uitgangsspanning afschakelen De maxi male stroom is ongeveer 330mA Als de regulator door overcurrent is afgeschakeld blijft deze afgeschakelde toestand ook al wordt de load losgekoppeld Om de regulator weer te kunnen opstar ten moet deze door de 7 controller uit en weer aan worden gezet of de voedingsspanning de regulator SuppPower moet uit en weer aan worden gezet De maxi
45. xceed 2 7V Regular Vdd is 2 5V The CMOS input output signal levels are 0 to Vdd the LVDS levels are 1V to 1 4V The CMOS switch level 1 Vdd For LVDS the switch level 1 2V 31 LVDS receivers amp drivers pins for AC coupling Signal BST Direction Description CIkN amp CIkP In Readout clock in amp ClkPo Readout clock out direct from input to output HoldN amp HoldP sample and Hold for front end HoldNo amp HoldPo sample and Hold to front end direct from input to output FastCIN amp FastCIP FastClear for front end active low direct from input to output FastClear to front end direct from input to output Test timing signal for front end FastCINo amp FastClPo TestN amp TestNo amp TestPo Test timing signal to front end direct from input to out put Token to start Readout of front end Token to start Readout of front end delayed according to the side of the detector ErrorN amp ErrorP EndCap Error signal to FEROM 0 Only the signal receivers have been adapted for AC coupled signals 1 These outputs are disabled if Power supply is OFF TokenN amp TokenP TokenNo amp TokenPo 3 2 JTAG signal pins Signal Dir Description TCKN amp TMSN amp TMS TDIN amp TDIP TRSTBN amp TRSTBP amp TDOP I I I I TCK In CMOS In CMOS Internal EndCap input signal TMS also for AC TDI In CMOS Internal EndCap in
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